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Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /* This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }	module IntSyncCrossingSource_n1x1( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0 // @[LazyModuleImp.scala:107:25] ); AsyncResetRegVec_w1_i0 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d (auto_in_0), .io_q (auto_out_sync_0) ); // @[AsyncResetReg.scala:86:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_172( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_193 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_430( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_174 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Atomics.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ class Atomics(params: TLBundleParameters) extends Module { val io = IO(new Bundle { val write = Flipped(Bool()) // ignore opcode val a = Flipped(new TLBundleA(params)) val data_in = Flipped(UInt(params.dataBits.W)) val data_out = UInt(params.dataBits.W) }) // Arithmetic, what to do val adder = io.a.param(2) val unsigned = io.a.param(1) val take_max = io.a.param(0) val signBit = io.a.mask & Cat(1.U, ~io.a.mask >> 1) val inv_d = Mux(adder, io.data_in, ~io.data_in) val sum = (FillInterleaved(8, io.a.mask) & io.a.data) + inv_d def sign(x: UInt): Bool = (Cat(x.asBools.grouped(8).map(_.last).toList.reverse) & signBit).orR val sign_a = sign(io.a.data) val sign_d = sign(io.data_in) val sign_s = sign(sum) val a_bigger_uneq = unsigned === sign_a // result if high bits are unequal val a_bigger = Mux(sign_a === sign_d, !sign_s, a_bigger_uneq) val pick_a = take_max === a_bigger // Logical, what to do val lut = VecInit(Seq( (0x6).U, // XOR (0xe).U, // OR (0x8).U, // AND (0xc).U))( // SWAP io.a.param(1,0)) val logical = Cat((io.a.data.asBools zip io.data_in.asBools).map { case (a, d) => lut(Cat(a, d)) }.reverse) // Operation, what to do? (0=d, 1=a, 2=sum, 3=logical) val select = Mux(io.write, 1.U, VecInit(Seq( 1.U, // PutFullData 1.U, // PutPartialData Mux(adder, 2.U, Mux(pick_a, 1.U, 0.U)), // ArithmeticData 3.U, // LogicalData 0.U, // Get 0.U, // Hint 0.U, // AcquireBlock 0.U))( // AcquirePerm io.a.opcode)) // Only the masked bytes can be modified val selects = io.a.mask.asBools.map(b => Mux(b, select, 0.U)) io.data_out := Cat(selects.zipWithIndex.map { case (s, i) => VecInit(Seq(io.data_in, io.a.data, sum, logical).map(_((i + 1) * 8 - 1, i * 8)))(s) }.reverse) }	module Atomics( // @[Atomics.scala:8:7] input clock, // @[Atomics.scala:8:7] input reset, // @[Atomics.scala:8:7] input io_write, // @[Atomics.scala:10:14] input [2:0] io_a_opcode, // @[Atomics.scala:10:14] input [2:0] io_a_param, // @[Atomics.scala:10:14] input [15:0] io_a_mask, // @[Atomics.scala:10:14] input [127:0] io_a_data, // @[Atomics.scala:10:14] input [127:0] io_data_in, // @[Atomics.scala:10:14] output [127:0] io_data_out // @[Atomics.scala:10:14] ); wire io_write_0 = io_write; // @[Atomics.scala:8:7] wire [2:0] io_a_opcode_0 = io_a_opcode; // @[Atomics.scala:8:7] wire [2:0] io_a_param_0 = io_a_param; // @[Atomics.scala:8:7] wire [15:0] io_a_mask_0 = io_a_mask; // @[Atomics.scala:8:7] wire [127:0] io_a_data_0 = io_a_data; // @[Atomics.scala:8:7] wire [127:0] io_data_in_0 = io_data_in; // @[Atomics.scala:8:7] wire [3:0][3:0] _GEN = '{4'hC, 4'h8, 4'hE, 4'h6}; wire [3:0] _lut_WIRE_0 = 4'h6; // @[Atomics.scala:34:20] wire [3:0] _lut_WIRE_1 = 4'hE; // @[Atomics.scala:34:20] wire [3:0] _lut_WIRE_2 = 4'h8; // @[Atomics.scala:34:20] wire [3:0] _lut_WIRE_3 = 4'hC; // @[Atomics.scala:34:20] wire [1:0] _select_WIRE_0 = 2'h1; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_1 = 2'h1; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_3 = 2'h3; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_4 = 2'h0; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_5 = 2'h0; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_6 = 2'h0; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_7 = 2'h0; // @[Atomics.scala:45:42] wire io_a_corrupt = 1'h0; // @[Atomics.scala:8:7, :10:14] wire [31:0] io_a_address = 32'h0; // @[Atomics.scala:8:7, :10:14] wire [5:0] io_a_source = 6'h0; // @[Atomics.scala:8:7, :10:14] wire [2:0] io_a_size = 3'h0; // @[Atomics.scala:8:7, :10:14] wire [127:0] _io_data_out_T_64; // @[Atomics.scala:58:21] wire [127:0] io_data_out_0; // @[Atomics.scala:8:7] wire adder = io_a_param_0[2]; // @[Atomics.scala:8:7, :18:28] wire unsigned_0 = io_a_param_0[1]; // @[Atomics.scala:8:7, :19:28] wire take_max = io_a_param_0[0]; // @[Atomics.scala:8:7, :20:28] wire [15:0] _signBit_T = ~io_a_mask_0; // @[Atomics.scala:8:7, :22:38] wire [14:0] _signBit_T_1 = _signBit_T[15:1]; // @[Atomics.scala:22:{38,49}] wire [15:0] _signBit_T_2 = {1'h1, _signBit_T_1}; // @[Atomics.scala:22:{32,49}] wire [15:0] signBit = io_a_mask_0 & _signBit_T_2; // @[Atomics.scala:8:7, :22:{27,32}] wire [127:0] _inv_d_T = ~io_data_in_0; // @[Atomics.scala:8:7, :23:38] wire [127:0] inv_d = adder ? io_data_in_0 : _inv_d_T; // @[Atomics.scala:8:7, :18:28, :23:{18,38}] wire _sum_T = io_a_mask_0[0]; // @[Atomics.scala:8:7, :24:29] wire _selects_T = io_a_mask_0[0]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_1 = io_a_mask_0[1]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_1 = io_a_mask_0[1]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_2 = io_a_mask_0[2]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_2 = io_a_mask_0[2]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_3 = io_a_mask_0[3]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_3 = io_a_mask_0[3]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_4 = io_a_mask_0[4]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_4 = io_a_mask_0[4]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_5 = io_a_mask_0[5]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_5 = io_a_mask_0[5]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_6 = io_a_mask_0[6]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_6 = io_a_mask_0[6]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_7 = io_a_mask_0[7]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_7 = io_a_mask_0[7]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_8 = io_a_mask_0[8]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_8 = io_a_mask_0[8]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_9 = io_a_mask_0[9]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_9 = io_a_mask_0[9]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_10 = io_a_mask_0[10]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_10 = io_a_mask_0[10]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_11 = io_a_mask_0[11]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_11 = io_a_mask_0[11]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_12 = io_a_mask_0[12]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_12 = io_a_mask_0[12]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_13 = io_a_mask_0[13]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_13 = io_a_mask_0[13]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_14 = io_a_mask_0[14]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_14 = io_a_mask_0[14]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_15 = io_a_mask_0[15]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_15 = io_a_mask_0[15]; // @[Atomics.scala:8:7, :24:29, :57:27] wire [7:0] _sum_T_16 = {8{_sum_T}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_17 = {8{_sum_T_1}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_18 = {8{_sum_T_2}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_19 = {8{_sum_T_3}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_20 = {8{_sum_T_4}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_21 = {8{_sum_T_5}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_22 = {8{_sum_T_6}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_23 = {8{_sum_T_7}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_24 = {8{_sum_T_8}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_25 = {8{_sum_T_9}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_26 = {8{_sum_T_10}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_27 = {8{_sum_T_11}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_28 = {8{_sum_T_12}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_29 = {8{_sum_T_13}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_30 = {8{_sum_T_14}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_31 = {8{_sum_T_15}}; // @[Atomics.scala:24:29] wire [15:0] sum_lo_lo_lo = {_sum_T_17, _sum_T_16}; // @[Atomics.scala:24:29] wire [15:0] sum_lo_lo_hi = {_sum_T_19, _sum_T_18}; // @[Atomics.scala:24:29] wire [31:0] sum_lo_lo = {sum_lo_lo_hi, sum_lo_lo_lo}; // @[Atomics.scala:24:29] wire [15:0] sum_lo_hi_lo = {_sum_T_21, _sum_T_20}; // @[Atomics.scala:24:29] wire [15:0] sum_lo_hi_hi = {_sum_T_23, _sum_T_22}; // @[Atomics.scala:24:29] wire [31:0] sum_lo_hi = {sum_lo_hi_hi, sum_lo_hi_lo}; // @[Atomics.scala:24:29] wire [63:0] sum_lo = {sum_lo_hi, sum_lo_lo}; // @[Atomics.scala:24:29] wire [15:0] sum_hi_lo_lo = {_sum_T_25, _sum_T_24}; // @[Atomics.scala:24:29] wire [15:0] sum_hi_lo_hi = {_sum_T_27, _sum_T_26}; // @[Atomics.scala:24:29] wire [31:0] sum_hi_lo = {sum_hi_lo_hi, sum_hi_lo_lo}; // @[Atomics.scala:24:29] wire [15:0] sum_hi_hi_lo = {_sum_T_29, _sum_T_28}; // @[Atomics.scala:24:29] wire [15:0] sum_hi_hi_hi = {_sum_T_31, _sum_T_30}; // @[Atomics.scala:24:29] wire [31:0] sum_hi_hi = {sum_hi_hi_hi, sum_hi_hi_lo}; // @[Atomics.scala:24:29] wire [63:0] sum_hi = {sum_hi_hi, sum_hi_lo}; // @[Atomics.scala:24:29] wire [127:0] _sum_T_32 = {sum_hi, sum_lo}; // @[Atomics.scala:24:29] wire [127:0] _sum_T_33 = _sum_T_32 & io_a_data_0; // @[Atomics.scala:8:7, :24:{29,44}] wire [128:0] _sum_T_34 = {1'h0, _sum_T_33} + {1'h0, inv_d}; // @[Atomics.scala:8:7, :10:14, :23:18, :24:{44,57}] wire [127:0] sum = _sum_T_34[127:0]; // @[Atomics.scala:24:57] wire _sign_a_T = io_a_data_0[0]; // @[Atomics.scala:8:7, :25:36] wire _logical_T = io_a_data_0[0]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_1 = io_a_data_0[1]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_1 = io_a_data_0[1]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_2 = io_a_data_0[2]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_2 = io_a_data_0[2]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_3 = io_a_data_0[3]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_3 = io_a_data_0[3]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_4 = io_a_data_0[4]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_4 = io_a_data_0[4]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_5 = io_a_data_0[5]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_5 = io_a_data_0[5]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_6 = io_a_data_0[6]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_6 = io_a_data_0[6]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_7 = io_a_data_0[7]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_7 = io_a_data_0[7]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_8 = io_a_data_0[8]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_8 = io_a_data_0[8]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_9 = io_a_data_0[9]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_9 = io_a_data_0[9]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_10 = io_a_data_0[10]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_10 = io_a_data_0[10]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_11 = io_a_data_0[11]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_11 = io_a_data_0[11]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_12 = io_a_data_0[12]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_12 = io_a_data_0[12]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_13 = io_a_data_0[13]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_13 = io_a_data_0[13]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_14 = io_a_data_0[14]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_14 = io_a_data_0[14]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_15 = io_a_data_0[15]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_15 = io_a_data_0[15]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_16 = io_a_data_0[16]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_16 = io_a_data_0[16]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_17 = io_a_data_0[17]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_17 = io_a_data_0[17]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_18 = io_a_data_0[18]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_18 = io_a_data_0[18]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_19 = io_a_data_0[19]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_19 = io_a_data_0[19]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_20 = io_a_data_0[20]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_20 = io_a_data_0[20]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_21 = io_a_data_0[21]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_21 = io_a_data_0[21]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_22 = io_a_data_0[22]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_22 = io_a_data_0[22]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_23 = io_a_data_0[23]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_23 = io_a_data_0[23]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_24 = io_a_data_0[24]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_24 = io_a_data_0[24]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_25 = io_a_data_0[25]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_25 = io_a_data_0[25]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_26 = io_a_data_0[26]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_26 = io_a_data_0[26]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_27 = io_a_data_0[27]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_27 = io_a_data_0[27]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_28 = io_a_data_0[28]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_28 = io_a_data_0[28]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_29 = io_a_data_0[29]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_29 = io_a_data_0[29]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_30 = io_a_data_0[30]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_30 = io_a_data_0[30]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_31 = io_a_data_0[31]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_31 = io_a_data_0[31]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_32 = io_a_data_0[32]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_32 = io_a_data_0[32]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_33 = io_a_data_0[33]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_33 = io_a_data_0[33]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_34 = io_a_data_0[34]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_34 = io_a_data_0[34]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_35 = io_a_data_0[35]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_35 = io_a_data_0[35]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_36 = io_a_data_0[36]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_36 = io_a_data_0[36]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_37 = io_a_data_0[37]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_37 = io_a_data_0[37]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_38 = io_a_data_0[38]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_38 = io_a_data_0[38]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_39 = io_a_data_0[39]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_39 = io_a_data_0[39]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_40 = io_a_data_0[40]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_40 = io_a_data_0[40]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_41 = io_a_data_0[41]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_41 = io_a_data_0[41]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_42 = io_a_data_0[42]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_42 = io_a_data_0[42]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_43 = io_a_data_0[43]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_43 = io_a_data_0[43]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_44 = io_a_data_0[44]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_44 = io_a_data_0[44]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_45 = io_a_data_0[45]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_45 = io_a_data_0[45]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_46 = io_a_data_0[46]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_46 = io_a_data_0[46]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_47 = io_a_data_0[47]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_47 = io_a_data_0[47]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_48 = io_a_data_0[48]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_48 = io_a_data_0[48]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_49 = io_a_data_0[49]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_49 = io_a_data_0[49]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_50 = io_a_data_0[50]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_50 = io_a_data_0[50]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_51 = io_a_data_0[51]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_51 = io_a_data_0[51]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_52 = io_a_data_0[52]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_52 = io_a_data_0[52]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_53 = io_a_data_0[53]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_53 = io_a_data_0[53]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_54 = io_a_data_0[54]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_54 = io_a_data_0[54]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_55 = io_a_data_0[55]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_55 = io_a_data_0[55]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_56 = io_a_data_0[56]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_56 = io_a_data_0[56]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_57 = io_a_data_0[57]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_57 = io_a_data_0[57]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_58 = io_a_data_0[58]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_58 = io_a_data_0[58]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_59 = io_a_data_0[59]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_59 = io_a_data_0[59]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_60 = io_a_data_0[60]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_60 = io_a_data_0[60]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_61 = io_a_data_0[61]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_61 = io_a_data_0[61]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_62 = io_a_data_0[62]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_62 = io_a_data_0[62]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_63 = io_a_data_0[63]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_63 = io_a_data_0[63]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_64 = io_a_data_0[64]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_64 = io_a_data_0[64]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_65 = io_a_data_0[65]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_65 = io_a_data_0[65]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_66 = io_a_data_0[66]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_66 = io_a_data_0[66]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_67 = io_a_data_0[67]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_67 = io_a_data_0[67]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_68 = io_a_data_0[68]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_68 = io_a_data_0[68]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_69 = io_a_data_0[69]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_69 = io_a_data_0[69]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_70 = io_a_data_0[70]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_70 = io_a_data_0[70]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_71 = io_a_data_0[71]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_71 = io_a_data_0[71]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_72 = io_a_data_0[72]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_72 = io_a_data_0[72]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_73 = io_a_data_0[73]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_73 = io_a_data_0[73]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_74 = io_a_data_0[74]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_74 = io_a_data_0[74]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_75 = io_a_data_0[75]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_75 = io_a_data_0[75]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_76 = io_a_data_0[76]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_76 = io_a_data_0[76]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_77 = io_a_data_0[77]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_77 = io_a_data_0[77]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_78 = io_a_data_0[78]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_78 = io_a_data_0[78]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_79 = io_a_data_0[79]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_79 = io_a_data_0[79]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_80 = io_a_data_0[80]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_80 = io_a_data_0[80]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_81 = io_a_data_0[81]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_81 = io_a_data_0[81]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_82 = io_a_data_0[82]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_82 = io_a_data_0[82]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_83 = io_a_data_0[83]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_83 = io_a_data_0[83]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_84 = io_a_data_0[84]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_84 = io_a_data_0[84]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_85 = io_a_data_0[85]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_85 = io_a_data_0[85]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_86 = io_a_data_0[86]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_86 = io_a_data_0[86]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_87 = io_a_data_0[87]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_87 = io_a_data_0[87]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_88 = io_a_data_0[88]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_88 = io_a_data_0[88]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_89 = io_a_data_0[89]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_89 = io_a_data_0[89]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_90 = io_a_data_0[90]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_90 = io_a_data_0[90]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_91 = io_a_data_0[91]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_91 = io_a_data_0[91]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_92 = io_a_data_0[92]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_92 = io_a_data_0[92]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_93 = io_a_data_0[93]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_93 = io_a_data_0[93]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_94 = io_a_data_0[94]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_94 = io_a_data_0[94]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_95 = io_a_data_0[95]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_95 = io_a_data_0[95]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_96 = io_a_data_0[96]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_96 = io_a_data_0[96]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_97 = io_a_data_0[97]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_97 = io_a_data_0[97]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_98 = io_a_data_0[98]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_98 = io_a_data_0[98]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_99 = io_a_data_0[99]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_99 = io_a_data_0[99]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_100 = io_a_data_0[100]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_100 = io_a_data_0[100]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_101 = io_a_data_0[101]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_101 = io_a_data_0[101]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_102 = io_a_data_0[102]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_102 = io_a_data_0[102]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_103 = io_a_data_0[103]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_103 = io_a_data_0[103]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_104 = io_a_data_0[104]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_104 = io_a_data_0[104]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_105 = io_a_data_0[105]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_105 = io_a_data_0[105]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_106 = io_a_data_0[106]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_106 = io_a_data_0[106]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_107 = io_a_data_0[107]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_107 = io_a_data_0[107]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_108 = io_a_data_0[108]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_108 = io_a_data_0[108]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_109 = io_a_data_0[109]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_109 = io_a_data_0[109]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_110 = io_a_data_0[110]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_110 = io_a_data_0[110]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_111 = io_a_data_0[111]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_111 = io_a_data_0[111]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_112 = io_a_data_0[112]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_112 = io_a_data_0[112]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_113 = io_a_data_0[113]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_113 = io_a_data_0[113]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_114 = io_a_data_0[114]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_114 = io_a_data_0[114]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_115 = io_a_data_0[115]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_115 = io_a_data_0[115]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_116 = io_a_data_0[116]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_116 = io_a_data_0[116]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_117 = io_a_data_0[117]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_117 = io_a_data_0[117]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_118 = io_a_data_0[118]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_118 = io_a_data_0[118]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_119 = io_a_data_0[119]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_119 = io_a_data_0[119]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_120 = io_a_data_0[120]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_120 = io_a_data_0[120]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_121 = io_a_data_0[121]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_121 = io_a_data_0[121]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_122 = io_a_data_0[122]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_122 = io_a_data_0[122]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_123 = io_a_data_0[123]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_123 = io_a_data_0[123]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_124 = io_a_data_0[124]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_124 = io_a_data_0[124]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_125 = io_a_data_0[125]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_125 = io_a_data_0[125]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_126 = io_a_data_0[126]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_126 = io_a_data_0[126]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_127 = io_a_data_0[127]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_127 = io_a_data_0[127]; // @[Atomics.scala:8:7, :25:36, :40:32] wire [1:0] sign_a_lo_lo_lo = {_sign_a_T_15, _sign_a_T_7}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_a_lo_lo_hi = {_sign_a_T_31, _sign_a_T_23}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_a_lo_lo = {sign_a_lo_lo_hi, sign_a_lo_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_a_lo_hi_lo = {_sign_a_T_47, _sign_a_T_39}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_a_lo_hi_hi = {_sign_a_T_63, _sign_a_T_55}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_a_lo_hi = {sign_a_lo_hi_hi, sign_a_lo_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_a_lo = {sign_a_lo_hi, sign_a_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_a_hi_lo_lo = {_sign_a_T_79, _sign_a_T_71}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_a_hi_lo_hi = {_sign_a_T_95, _sign_a_T_87}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_a_hi_lo = {sign_a_hi_lo_hi, sign_a_hi_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_a_hi_hi_lo = {_sign_a_T_111, _sign_a_T_103}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_a_hi_hi_hi = {_sign_a_T_127, _sign_a_T_119}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_a_hi_hi = {sign_a_hi_hi_hi, sign_a_hi_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_a_hi = {sign_a_hi_hi, sign_a_hi_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_a_T_128 = {sign_a_hi, sign_a_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_a_T_129 = _sign_a_T_128 & signBit; // @[Atomics.scala:22:27, :25:{33,83}] wire sign_a = \|_sign_a_T_129; // @[Atomics.scala:25:{83,94}] wire _sign_d_T = io_data_in_0[0]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_128 = io_data_in_0[0]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_1 = io_data_in_0[1]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_129 = io_data_in_0[1]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_2 = io_data_in_0[2]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_130 = io_data_in_0[2]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_3 = io_data_in_0[3]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_131 = io_data_in_0[3]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_4 = io_data_in_0[4]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_132 = io_data_in_0[4]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_5 = io_data_in_0[5]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_133 = io_data_in_0[5]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_6 = io_data_in_0[6]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_134 = io_data_in_0[6]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_7 = io_data_in_0[7]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_135 = io_data_in_0[7]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_8 = io_data_in_0[8]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_136 = io_data_in_0[8]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_9 = io_data_in_0[9]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_137 = io_data_in_0[9]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_10 = io_data_in_0[10]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_138 = io_data_in_0[10]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_11 = io_data_in_0[11]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_139 = io_data_in_0[11]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_12 = io_data_in_0[12]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_140 = io_data_in_0[12]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_13 = io_data_in_0[13]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_141 = io_data_in_0[13]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_14 = io_data_in_0[14]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_142 = io_data_in_0[14]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_15 = io_data_in_0[15]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_143 = io_data_in_0[15]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_16 = io_data_in_0[16]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_144 = io_data_in_0[16]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_17 = io_data_in_0[17]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_145 = io_data_in_0[17]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_18 = io_data_in_0[18]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_146 = io_data_in_0[18]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_19 = io_data_in_0[19]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_147 = io_data_in_0[19]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_20 = io_data_in_0[20]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_148 = io_data_in_0[20]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_21 = io_data_in_0[21]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_149 = io_data_in_0[21]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_22 = io_data_in_0[22]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_150 = io_data_in_0[22]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_23 = io_data_in_0[23]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_151 = io_data_in_0[23]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_24 = io_data_in_0[24]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_152 = io_data_in_0[24]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_25 = io_data_in_0[25]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_153 = io_data_in_0[25]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_26 = io_data_in_0[26]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_154 = io_data_in_0[26]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_27 = io_data_in_0[27]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_155 = io_data_in_0[27]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_28 = io_data_in_0[28]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_156 = io_data_in_0[28]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_29 = io_data_in_0[29]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_157 = io_data_in_0[29]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_30 = io_data_in_0[30]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_158 = io_data_in_0[30]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_31 = io_data_in_0[31]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_159 = io_data_in_0[31]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_32 = io_data_in_0[32]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_160 = io_data_in_0[32]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_33 = io_data_in_0[33]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_161 = io_data_in_0[33]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_34 = io_data_in_0[34]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_162 = io_data_in_0[34]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_35 = io_data_in_0[35]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_163 = io_data_in_0[35]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_36 = io_data_in_0[36]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_164 = io_data_in_0[36]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_37 = io_data_in_0[37]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_165 = io_data_in_0[37]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_38 = io_data_in_0[38]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_166 = io_data_in_0[38]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_39 = io_data_in_0[39]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_167 = io_data_in_0[39]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_40 = io_data_in_0[40]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_168 = io_data_in_0[40]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_41 = io_data_in_0[41]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_169 = io_data_in_0[41]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_42 = io_data_in_0[42]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_170 = io_data_in_0[42]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_43 = io_data_in_0[43]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_171 = io_data_in_0[43]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_44 = io_data_in_0[44]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_172 = io_data_in_0[44]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_45 = io_data_in_0[45]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_173 = io_data_in_0[45]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_46 = io_data_in_0[46]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_174 = io_data_in_0[46]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_47 = io_data_in_0[47]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_175 = io_data_in_0[47]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_48 = io_data_in_0[48]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_176 = io_data_in_0[48]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_49 = io_data_in_0[49]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_177 = io_data_in_0[49]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_50 = io_data_in_0[50]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_178 = io_data_in_0[50]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_51 = io_data_in_0[51]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_179 = io_data_in_0[51]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_52 = io_data_in_0[52]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_180 = io_data_in_0[52]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_53 = io_data_in_0[53]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_181 = io_data_in_0[53]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_54 = io_data_in_0[54]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_182 = io_data_in_0[54]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_55 = io_data_in_0[55]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_183 = io_data_in_0[55]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_56 = io_data_in_0[56]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_184 = io_data_in_0[56]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_57 = io_data_in_0[57]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_185 = io_data_in_0[57]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_58 = io_data_in_0[58]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_186 = io_data_in_0[58]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_59 = io_data_in_0[59]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_187 = io_data_in_0[59]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_60 = io_data_in_0[60]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_188 = io_data_in_0[60]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_61 = io_data_in_0[61]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_189 = io_data_in_0[61]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_62 = io_data_in_0[62]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_190 = io_data_in_0[62]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_63 = io_data_in_0[63]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_191 = io_data_in_0[63]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_64 = io_data_in_0[64]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_192 = io_data_in_0[64]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_65 = io_data_in_0[65]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_193 = io_data_in_0[65]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_66 = io_data_in_0[66]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_194 = io_data_in_0[66]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_67 = io_data_in_0[67]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_195 = io_data_in_0[67]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_68 = io_data_in_0[68]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_196 = io_data_in_0[68]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_69 = io_data_in_0[69]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_197 = io_data_in_0[69]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_70 = io_data_in_0[70]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_198 = io_data_in_0[70]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_71 = io_data_in_0[71]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_199 = io_data_in_0[71]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_72 = io_data_in_0[72]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_200 = io_data_in_0[72]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_73 = io_data_in_0[73]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_201 = io_data_in_0[73]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_74 = io_data_in_0[74]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_202 = io_data_in_0[74]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_75 = io_data_in_0[75]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_203 = io_data_in_0[75]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_76 = io_data_in_0[76]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_204 = io_data_in_0[76]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_77 = io_data_in_0[77]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_205 = io_data_in_0[77]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_78 = io_data_in_0[78]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_206 = io_data_in_0[78]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_79 = io_data_in_0[79]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_207 = io_data_in_0[79]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_80 = io_data_in_0[80]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_208 = io_data_in_0[80]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_81 = io_data_in_0[81]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_209 = io_data_in_0[81]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_82 = io_data_in_0[82]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_210 = io_data_in_0[82]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_83 = io_data_in_0[83]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_211 = io_data_in_0[83]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_84 = io_data_in_0[84]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_212 = io_data_in_0[84]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_85 = io_data_in_0[85]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_213 = io_data_in_0[85]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_86 = io_data_in_0[86]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_214 = io_data_in_0[86]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_87 = io_data_in_0[87]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_215 = io_data_in_0[87]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_88 = io_data_in_0[88]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_216 = io_data_in_0[88]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_89 = io_data_in_0[89]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_217 = io_data_in_0[89]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_90 = io_data_in_0[90]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_218 = io_data_in_0[90]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_91 = io_data_in_0[91]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_219 = io_data_in_0[91]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_92 = io_data_in_0[92]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_220 = io_data_in_0[92]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_93 = io_data_in_0[93]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_221 = io_data_in_0[93]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_94 = io_data_in_0[94]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_222 = io_data_in_0[94]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_95 = io_data_in_0[95]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_223 = io_data_in_0[95]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_96 = io_data_in_0[96]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_224 = io_data_in_0[96]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_97 = io_data_in_0[97]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_225 = io_data_in_0[97]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_98 = io_data_in_0[98]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_226 = io_data_in_0[98]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_99 = io_data_in_0[99]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_227 = io_data_in_0[99]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_100 = io_data_in_0[100]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_228 = io_data_in_0[100]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_101 = io_data_in_0[101]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_229 = io_data_in_0[101]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_102 = io_data_in_0[102]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_230 = io_data_in_0[102]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_103 = io_data_in_0[103]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_231 = io_data_in_0[103]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_104 = io_data_in_0[104]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_232 = io_data_in_0[104]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_105 = io_data_in_0[105]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_233 = io_data_in_0[105]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_106 = io_data_in_0[106]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_234 = io_data_in_0[106]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_107 = io_data_in_0[107]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_235 = io_data_in_0[107]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_108 = io_data_in_0[108]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_236 = io_data_in_0[108]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_109 = io_data_in_0[109]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_237 = io_data_in_0[109]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_110 = io_data_in_0[110]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_238 = io_data_in_0[110]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_111 = io_data_in_0[111]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_239 = io_data_in_0[111]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_112 = io_data_in_0[112]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_240 = io_data_in_0[112]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_113 = io_data_in_0[113]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_241 = io_data_in_0[113]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_114 = io_data_in_0[114]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_242 = io_data_in_0[114]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_115 = io_data_in_0[115]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_243 = io_data_in_0[115]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_116 = io_data_in_0[116]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_244 = io_data_in_0[116]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_117 = io_data_in_0[117]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_245 = io_data_in_0[117]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_118 = io_data_in_0[118]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_246 = io_data_in_0[118]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_119 = io_data_in_0[119]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_247 = io_data_in_0[119]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_120 = io_data_in_0[120]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_248 = io_data_in_0[120]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_121 = io_data_in_0[121]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_249 = io_data_in_0[121]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_122 = io_data_in_0[122]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_250 = io_data_in_0[122]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_123 = io_data_in_0[123]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_251 = io_data_in_0[123]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_124 = io_data_in_0[124]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_252 = io_data_in_0[124]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_125 = io_data_in_0[125]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_253 = io_data_in_0[125]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_126 = io_data_in_0[126]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_254 = io_data_in_0[126]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_127 = io_data_in_0[127]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_255 = io_data_in_0[127]; // @[Atomics.scala:8:7, :25:36, :40:55] wire [1:0] sign_d_lo_lo_lo = {_sign_d_T_15, _sign_d_T_7}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_d_lo_lo_hi = {_sign_d_T_31, _sign_d_T_23}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_d_lo_lo = {sign_d_lo_lo_hi, sign_d_lo_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_d_lo_hi_lo = {_sign_d_T_47, _sign_d_T_39}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_d_lo_hi_hi = {_sign_d_T_63, _sign_d_T_55}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_d_lo_hi = {sign_d_lo_hi_hi, sign_d_lo_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_d_lo = {sign_d_lo_hi, sign_d_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_d_hi_lo_lo = {_sign_d_T_79, _sign_d_T_71}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_d_hi_lo_hi = {_sign_d_T_95, _sign_d_T_87}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_d_hi_lo = {sign_d_hi_lo_hi, sign_d_hi_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_d_hi_hi_lo = {_sign_d_T_111, _sign_d_T_103}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_d_hi_hi_hi = {_sign_d_T_127, _sign_d_T_119}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_d_hi_hi = {sign_d_hi_hi_hi, sign_d_hi_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_d_hi = {sign_d_hi_hi, sign_d_hi_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_d_T_128 = {sign_d_hi, sign_d_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_d_T_129 = _sign_d_T_128 & signBit; // @[Atomics.scala:22:27, :25:{33,83}] wire sign_d = \|_sign_d_T_129; // @[Atomics.scala:25:{83,94}] wire _sign_s_T = sum[0]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_1 = sum[1]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_2 = sum[2]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_3 = sum[3]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_4 = sum[4]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_5 = sum[5]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_6 = sum[6]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_7 = sum[7]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_8 = sum[8]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_9 = sum[9]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_10 = sum[10]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_11 = sum[11]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_12 = sum[12]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_13 = sum[13]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_14 = sum[14]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_15 = sum[15]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_16 = sum[16]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_17 = sum[17]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_18 = sum[18]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_19 = sum[19]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_20 = sum[20]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_21 = sum[21]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_22 = sum[22]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_23 = sum[23]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_24 = sum[24]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_25 = sum[25]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_26 = sum[26]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_27 = sum[27]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_28 = sum[28]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_29 = sum[29]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_30 = sum[30]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_31 = sum[31]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_32 = sum[32]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_33 = sum[33]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_34 = sum[34]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_35 = sum[35]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_36 = sum[36]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_37 = sum[37]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_38 = sum[38]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_39 = sum[39]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_40 = sum[40]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_41 = sum[41]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_42 = sum[42]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_43 = sum[43]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_44 = sum[44]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_45 = sum[45]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_46 = sum[46]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_47 = sum[47]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_48 = sum[48]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_49 = sum[49]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_50 = sum[50]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_51 = sum[51]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_52 = sum[52]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_53 = sum[53]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_54 = sum[54]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_55 = sum[55]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_56 = sum[56]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_57 = sum[57]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_58 = sum[58]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_59 = sum[59]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_60 = sum[60]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_61 = sum[61]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_62 = sum[62]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_63 = sum[63]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_64 = sum[64]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_65 = sum[65]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_66 = sum[66]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_67 = sum[67]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_68 = sum[68]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_69 = sum[69]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_70 = sum[70]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_71 = sum[71]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_72 = sum[72]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_73 = sum[73]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_74 = sum[74]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_75 = sum[75]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_76 = sum[76]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_77 = sum[77]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_78 = sum[78]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_79 = sum[79]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_80 = sum[80]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_81 = sum[81]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_82 = sum[82]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_83 = sum[83]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_84 = sum[84]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_85 = sum[85]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_86 = sum[86]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_87 = sum[87]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_88 = sum[88]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_89 = sum[89]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_90 = sum[90]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_91 = sum[91]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_92 = sum[92]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_93 = sum[93]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_94 = sum[94]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_95 = sum[95]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_96 = sum[96]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_97 = sum[97]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_98 = sum[98]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_99 = sum[99]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_100 = sum[100]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_101 = sum[101]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_102 = sum[102]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_103 = sum[103]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_104 = sum[104]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_105 = sum[105]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_106 = sum[106]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_107 = sum[107]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_108 = sum[108]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_109 = sum[109]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_110 = sum[110]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_111 = sum[111]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_112 = sum[112]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_113 = sum[113]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_114 = sum[114]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_115 = sum[115]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_116 = sum[116]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_117 = sum[117]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_118 = sum[118]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_119 = sum[119]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_120 = sum[120]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_121 = sum[121]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_122 = sum[122]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_123 = sum[123]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_124 = sum[124]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_125 = sum[125]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_126 = sum[126]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_127 = sum[127]; // @[Atomics.scala:24:57, :25:36] wire [1:0] sign_s_lo_lo_lo = {_sign_s_T_15, _sign_s_T_7}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_s_lo_lo_hi = {_sign_s_T_31, _sign_s_T_23}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_s_lo_lo = {sign_s_lo_lo_hi, sign_s_lo_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_s_lo_hi_lo = {_sign_s_T_47, _sign_s_T_39}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_s_lo_hi_hi = {_sign_s_T_63, _sign_s_T_55}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_s_lo_hi = {sign_s_lo_hi_hi, sign_s_lo_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_s_lo = {sign_s_lo_hi, sign_s_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_s_hi_lo_lo = {_sign_s_T_79, _sign_s_T_71}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_s_hi_lo_hi = {_sign_s_T_95, _sign_s_T_87}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_s_hi_lo = {sign_s_hi_lo_hi, sign_s_hi_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_s_hi_hi_lo = {_sign_s_T_111, _sign_s_T_103}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_s_hi_hi_hi = {_sign_s_T_127, _sign_s_T_119}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_s_hi_hi = {sign_s_hi_hi_hi, sign_s_hi_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_s_hi = {sign_s_hi_hi, sign_s_hi_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_s_T_128 = {sign_s_hi, sign_s_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_s_T_129 = _sign_s_T_128 & signBit; // @[Atomics.scala:22:27, :25:{33,83}] wire sign_s = \|_sign_s_T_129; // @[Atomics.scala:25:{83,94}] wire a_bigger_uneq = unsigned_0 == sign_a; // @[Atomics.scala:19:28, :25:94, :29:32] wire _a_bigger_T = sign_a == sign_d; // @[Atomics.scala:25:94, :30:29] wire _a_bigger_T_1 = ~sign_s; // @[Atomics.scala:25:94, :30:41] wire a_bigger = _a_bigger_T ? _a_bigger_T_1 : a_bigger_uneq; // @[Atomics.scala:29:32, :30:{21,29,41}] wire pick_a = take_max == a_bigger; // @[Atomics.scala:20:28, :30:21, :31:25] wire _select_T = pick_a; // @[Atomics.scala:31:25, :48:24] wire [1:0] _lut_T = io_a_param_0[1:0]; // @[Atomics.scala:8:7, :39:15] wire [1:0] _logical_T_256 = {_logical_T, _logical_T_128}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_257 = _GEN[_lut_T] >> _logical_T_256; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_258 = _logical_T_257[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_259 = {_logical_T_1, _logical_T_129}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_260 = _GEN[_lut_T] >> _logical_T_259; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_261 = _logical_T_260[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_262 = {_logical_T_2, _logical_T_130}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_263 = _GEN[_lut_T] >> _logical_T_262; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_264 = _logical_T_263[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_265 = {_logical_T_3, _logical_T_131}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_266 = _GEN[_lut_T] >> _logical_T_265; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_267 = _logical_T_266[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_268 = {_logical_T_4, _logical_T_132}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_269 = _GEN[_lut_T] >> _logical_T_268; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_270 = _logical_T_269[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_271 = {_logical_T_5, _logical_T_133}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_272 = _GEN[_lut_T] >> _logical_T_271; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_273 = _logical_T_272[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_274 = {_logical_T_6, _logical_T_134}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_275 = _GEN[_lut_T] >> _logical_T_274; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_276 = _logical_T_275[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_277 = {_logical_T_7, _logical_T_135}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_278 = _GEN[_lut_T] >> _logical_T_277; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_279 = _logical_T_278[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_280 = {_logical_T_8, _logical_T_136}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_281 = _GEN[_lut_T] >> _logical_T_280; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_282 = _logical_T_281[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_283 = {_logical_T_9, _logical_T_137}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_284 = _GEN[_lut_T] >> _logical_T_283; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_285 = _logical_T_284[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_286 = {_logical_T_10, _logical_T_138}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_287 = _GEN[_lut_T] >> _logical_T_286; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_288 = _logical_T_287[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_289 = {_logical_T_11, _logical_T_139}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_290 = _GEN[_lut_T] >> _logical_T_289; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_291 = _logical_T_290[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_292 = {_logical_T_12, _logical_T_140}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_293 = _GEN[_lut_T] >> _logical_T_292; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_294 = _logical_T_293[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_295 = {_logical_T_13, _logical_T_141}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_296 = _GEN[_lut_T] >> _logical_T_295; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_297 = _logical_T_296[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_298 = {_logical_T_14, _logical_T_142}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_299 = _GEN[_lut_T] >> _logical_T_298; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_300 = _logical_T_299[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_301 = {_logical_T_15, _logical_T_143}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_302 = _GEN[_lut_T] >> _logical_T_301; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_303 = _logical_T_302[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_304 = {_logical_T_16, _logical_T_144}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_305 = _GEN[_lut_T] >> _logical_T_304; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_306 = _logical_T_305[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_307 = {_logical_T_17, _logical_T_145}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_308 = _GEN[_lut_T] >> _logical_T_307; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_309 = _logical_T_308[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_310 = {_logical_T_18, _logical_T_146}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_311 = _GEN[_lut_T] >> _logical_T_310; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_312 = _logical_T_311[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_313 = {_logical_T_19, _logical_T_147}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_314 = _GEN[_lut_T] >> _logical_T_313; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_315 = _logical_T_314[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_316 = {_logical_T_20, _logical_T_148}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_317 = _GEN[_lut_T] >> _logical_T_316; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_318 = _logical_T_317[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_319 = {_logical_T_21, _logical_T_149}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_320 = _GEN[_lut_T] >> _logical_T_319; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_321 = _logical_T_320[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_322 = {_logical_T_22, _logical_T_150}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_323 = _GEN[_lut_T] >> _logical_T_322; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_324 = _logical_T_323[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_325 = {_logical_T_23, _logical_T_151}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_326 = _GEN[_lut_T] >> _logical_T_325; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_327 = _logical_T_326[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_328 = {_logical_T_24, _logical_T_152}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_329 = _GEN[_lut_T] >> _logical_T_328; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_330 = _logical_T_329[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_331 = {_logical_T_25, _logical_T_153}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_332 = _GEN[_lut_T] >> _logical_T_331; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_333 = _logical_T_332[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_334 = {_logical_T_26, _logical_T_154}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_335 = _GEN[_lut_T] >> _logical_T_334; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_336 = _logical_T_335[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_337 = {_logical_T_27, _logical_T_155}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_338 = _GEN[_lut_T] >> _logical_T_337; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_339 = _logical_T_338[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_340 = {_logical_T_28, _logical_T_156}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_341 = _GEN[_lut_T] >> _logical_T_340; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_342 = _logical_T_341[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_343 = {_logical_T_29, _logical_T_157}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_344 = _GEN[_lut_T] >> _logical_T_343; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_345 = _logical_T_344[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_346 = {_logical_T_30, _logical_T_158}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_347 = _GEN[_lut_T] >> _logical_T_346; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_348 = _logical_T_347[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_349 = {_logical_T_31, _logical_T_159}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_350 = _GEN[_lut_T] >> _logical_T_349; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_351 = _logical_T_350[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_352 = {_logical_T_32, _logical_T_160}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_353 = _GEN[_lut_T] >> _logical_T_352; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_354 = _logical_T_353[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_355 = {_logical_T_33, _logical_T_161}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_356 = _GEN[_lut_T] >> _logical_T_355; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_357 = _logical_T_356[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_358 = {_logical_T_34, _logical_T_162}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_359 = _GEN[_lut_T] >> _logical_T_358; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_360 = _logical_T_359[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_361 = {_logical_T_35, _logical_T_163}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_362 = _GEN[_lut_T] >> _logical_T_361; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_363 = _logical_T_362[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_364 = {_logical_T_36, _logical_T_164}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_365 = _GEN[_lut_T] >> _logical_T_364; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_366 = _logical_T_365[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_367 = {_logical_T_37, _logical_T_165}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_368 = _GEN[_lut_T] >> _logical_T_367; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_369 = _logical_T_368[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_370 = {_logical_T_38, _logical_T_166}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_371 = _GEN[_lut_T] >> _logical_T_370; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_372 = _logical_T_371[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_373 = {_logical_T_39, _logical_T_167}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_374 = _GEN[_lut_T] >> _logical_T_373; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_375 = _logical_T_374[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_376 = {_logical_T_40, _logical_T_168}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_377 = _GEN[_lut_T] >> _logical_T_376; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_378 = _logical_T_377[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_379 = {_logical_T_41, _logical_T_169}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_380 = _GEN[_lut_T] >> _logical_T_379; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_381 = _logical_T_380[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_382 = {_logical_T_42, _logical_T_170}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_383 = _GEN[_lut_T] >> _logical_T_382; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_384 = _logical_T_383[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_385 = {_logical_T_43, _logical_T_171}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_386 = _GEN[_lut_T] >> _logical_T_385; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_387 = _logical_T_386[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_388 = {_logical_T_44, _logical_T_172}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_389 = _GEN[_lut_T] >> _logical_T_388; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_390 = _logical_T_389[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_391 = {_logical_T_45, _logical_T_173}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_392 = _GEN[_lut_T] >> _logical_T_391; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_393 = _logical_T_392[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_394 = {_logical_T_46, _logical_T_174}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_395 = _GEN[_lut_T] >> _logical_T_394; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_396 = _logical_T_395[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_397 = {_logical_T_47, _logical_T_175}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_398 = _GEN[_lut_T] >> _logical_T_397; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_399 = _logical_T_398[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_400 = {_logical_T_48, _logical_T_176}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_401 = _GEN[_lut_T] >> _logical_T_400; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_402 = _logical_T_401[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_403 = {_logical_T_49, _logical_T_177}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_404 = _GEN[_lut_T] >> _logical_T_403; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_405 = _logical_T_404[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_406 = {_logical_T_50, _logical_T_178}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_407 = _GEN[_lut_T] >> _logical_T_406; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_408 = _logical_T_407[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_409 = {_logical_T_51, _logical_T_179}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_410 = _GEN[_lut_T] >> _logical_T_409; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_411 = _logical_T_410[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_412 = {_logical_T_52, _logical_T_180}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_413 = _GEN[_lut_T] >> _logical_T_412; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_414 = _logical_T_413[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_415 = {_logical_T_53, _logical_T_181}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_416 = _GEN[_lut_T] >> _logical_T_415; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_417 = _logical_T_416[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_418 = {_logical_T_54, _logical_T_182}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_419 = _GEN[_lut_T] >> _logical_T_418; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_420 = _logical_T_419[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_421 = {_logical_T_55, _logical_T_183}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_422 = _GEN[_lut_T] >> _logical_T_421; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_423 = _logical_T_422[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_424 = {_logical_T_56, _logical_T_184}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_425 = _GEN[_lut_T] >> _logical_T_424; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_426 = _logical_T_425[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_427 = {_logical_T_57, _logical_T_185}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_428 = _GEN[_lut_T] >> _logical_T_427; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_429 = _logical_T_428[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_430 = {_logical_T_58, _logical_T_186}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_431 = _GEN[_lut_T] >> _logical_T_430; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_432 = _logical_T_431[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_433 = {_logical_T_59, _logical_T_187}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_434 = _GEN[_lut_T] >> _logical_T_433; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_435 = _logical_T_434[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_436 = {_logical_T_60, _logical_T_188}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_437 = _GEN[_lut_T] >> _logical_T_436; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_438 = _logical_T_437[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_439 = {_logical_T_61, _logical_T_189}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_440 = _GEN[_lut_T] >> _logical_T_439; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_441 = _logical_T_440[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_442 = {_logical_T_62, _logical_T_190}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_443 = _GEN[_lut_T] >> _logical_T_442; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_444 = _logical_T_443[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_445 = {_logical_T_63, _logical_T_191}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_446 = _GEN[_lut_T] >> _logical_T_445; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_447 = _logical_T_446[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_448 = {_logical_T_64, _logical_T_192}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_449 = _GEN[_lut_T] >> _logical_T_448; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_450 = _logical_T_449[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_451 = {_logical_T_65, _logical_T_193}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_452 = _GEN[_lut_T] >> _logical_T_451; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_453 = _logical_T_452[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_454 = {_logical_T_66, _logical_T_194}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_455 = _GEN[_lut_T] >> _logical_T_454; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_456 = _logical_T_455[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_457 = {_logical_T_67, _logical_T_195}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_458 = _GEN[_lut_T] >> _logical_T_457; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_459 = _logical_T_458[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_460 = {_logical_T_68, _logical_T_196}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_461 = _GEN[_lut_T] >> _logical_T_460; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_462 = _logical_T_461[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_463 = {_logical_T_69, _logical_T_197}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_464 = _GEN[_lut_T] >> _logical_T_463; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_465 = _logical_T_464[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_466 = {_logical_T_70, _logical_T_198}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_467 = _GEN[_lut_T] >> _logical_T_466; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_468 = _logical_T_467[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_469 = {_logical_T_71, _logical_T_199}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_470 = _GEN[_lut_T] >> _logical_T_469; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_471 = _logical_T_470[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_472 = {_logical_T_72, _logical_T_200}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_473 = _GEN[_lut_T] >> _logical_T_472; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_474 = _logical_T_473[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_475 = {_logical_T_73, _logical_T_201}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_476 = _GEN[_lut_T] >> _logical_T_475; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_477 = _logical_T_476[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_478 = {_logical_T_74, _logical_T_202}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_479 = _GEN[_lut_T] >> _logical_T_478; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_480 = _logical_T_479[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_481 = {_logical_T_75, _logical_T_203}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_482 = _GEN[_lut_T] >> _logical_T_481; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_483 = _logical_T_482[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_484 = {_logical_T_76, _logical_T_204}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_485 = _GEN[_lut_T] >> _logical_T_484; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_486 = _logical_T_485[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_487 = {_logical_T_77, _logical_T_205}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_488 = _GEN[_lut_T] >> _logical_T_487; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_489 = _logical_T_488[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_490 = {_logical_T_78, _logical_T_206}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_491 = _GEN[_lut_T] >> _logical_T_490; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_492 = _logical_T_491[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_493 = {_logical_T_79, _logical_T_207}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_494 = _GEN[_lut_T] >> _logical_T_493; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_495 = _logical_T_494[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_496 = {_logical_T_80, _logical_T_208}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_497 = _GEN[_lut_T] >> _logical_T_496; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_498 = _logical_T_497[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_499 = {_logical_T_81, _logical_T_209}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_500 = _GEN[_lut_T] >> _logical_T_499; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_501 = _logical_T_500[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_502 = {_logical_T_82, _logical_T_210}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_503 = _GEN[_lut_T] >> _logical_T_502; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_504 = _logical_T_503[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_505 = {_logical_T_83, _logical_T_211}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_506 = _GEN[_lut_T] >> _logical_T_505; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_507 = _logical_T_506[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_508 = {_logical_T_84, _logical_T_212}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_509 = _GEN[_lut_T] >> _logical_T_508; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_510 = _logical_T_509[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_511 = {_logical_T_85, _logical_T_213}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_512 = _GEN[_lut_T] >> _logical_T_511; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_513 = _logical_T_512[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_514 = {_logical_T_86, _logical_T_214}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_515 = _GEN[_lut_T] >> _logical_T_514; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_516 = _logical_T_515[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_517 = {_logical_T_87, _logical_T_215}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_518 = _GEN[_lut_T] >> _logical_T_517; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_519 = _logical_T_518[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_520 = {_logical_T_88, _logical_T_216}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_521 = _GEN[_lut_T] >> _logical_T_520; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_522 = _logical_T_521[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_523 = {_logical_T_89, _logical_T_217}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_524 = _GEN[_lut_T] >> _logical_T_523; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_525 = _logical_T_524[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_526 = {_logical_T_90, _logical_T_218}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_527 = _GEN[_lut_T] >> _logical_T_526; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_528 = _logical_T_527[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_529 = {_logical_T_91, _logical_T_219}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_530 = _GEN[_lut_T] >> _logical_T_529; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_531 = _logical_T_530[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_532 = {_logical_T_92, _logical_T_220}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_533 = _GEN[_lut_T] >> _logical_T_532; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_534 = _logical_T_533[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_535 = {_logical_T_93, _logical_T_221}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_536 = _GEN[_lut_T] >> _logical_T_535; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_537 = _logical_T_536[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_538 = {_logical_T_94, _logical_T_222}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_539 = _GEN[_lut_T] >> _logical_T_538; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_540 = _logical_T_539[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_541 = {_logical_T_95, _logical_T_223}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_542 = _GEN[_lut_T] >> _logical_T_541; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_543 = _logical_T_542[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_544 = {_logical_T_96, _logical_T_224}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_545 = _GEN[_lut_T] >> _logical_T_544; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_546 = _logical_T_545[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_547 = {_logical_T_97, _logical_T_225}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_548 = _GEN[_lut_T] >> _logical_T_547; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_549 = _logical_T_548[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_550 = {_logical_T_98, _logical_T_226}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_551 = _GEN[_lut_T] >> _logical_T_550; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_552 = _logical_T_551[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_553 = {_logical_T_99, _logical_T_227}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_554 = _GEN[_lut_T] >> _logical_T_553; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_555 = _logical_T_554[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_556 = {_logical_T_100, _logical_T_228}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_557 = _GEN[_lut_T] >> _logical_T_556; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_558 = _logical_T_557[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_559 = {_logical_T_101, _logical_T_229}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_560 = _GEN[_lut_T] >> _logical_T_559; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_561 = _logical_T_560[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_562 = {_logical_T_102, _logical_T_230}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_563 = _GEN[_lut_T] >> _logical_T_562; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_564 = _logical_T_563[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_565 = {_logical_T_103, _logical_T_231}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_566 = _GEN[_lut_T] >> _logical_T_565; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_567 = _logical_T_566[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_568 = {_logical_T_104, _logical_T_232}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_569 = _GEN[_lut_T] >> _logical_T_568; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_570 = _logical_T_569[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_571 = {_logical_T_105, _logical_T_233}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_572 = _GEN[_lut_T] >> _logical_T_571; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_573 = _logical_T_572[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_574 = {_logical_T_106, _logical_T_234}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_575 = _GEN[_lut_T] >> _logical_T_574; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_576 = _logical_T_575[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_577 = {_logical_T_107, _logical_T_235}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_578 = _GEN[_lut_T] >> _logical_T_577; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_579 = _logical_T_578[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_580 = {_logical_T_108, _logical_T_236}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_581 = _GEN[_lut_T] >> _logical_T_580; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_582 = _logical_T_581[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_583 = {_logical_T_109, _logical_T_237}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_584 = _GEN[_lut_T] >> _logical_T_583; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_585 = _logical_T_584[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_586 = {_logical_T_110, _logical_T_238}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_587 = _GEN[_lut_T] >> _logical_T_586; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_588 = _logical_T_587[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_589 = {_logical_T_111, _logical_T_239}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_590 = _GEN[_lut_T] >> _logical_T_589; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_591 = _logical_T_590[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_592 = {_logical_T_112, _logical_T_240}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_593 = _GEN[_lut_T] >> _logical_T_592; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_594 = _logical_T_593[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_595 = {_logical_T_113, _logical_T_241}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_596 = _GEN[_lut_T] >> _logical_T_595; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_597 = _logical_T_596[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_598 = {_logical_T_114, _logical_T_242}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_599 = _GEN[_lut_T] >> _logical_T_598; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_600 = _logical_T_599[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_601 = {_logical_T_115, _logical_T_243}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_602 = _GEN[_lut_T] >> _logical_T_601; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_603 = _logical_T_602[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_604 = {_logical_T_116, _logical_T_244}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_605 = _GEN[_lut_T] >> _logical_T_604; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_606 = _logical_T_605[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_607 = {_logical_T_117, _logical_T_245}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_608 = _GEN[_lut_T] >> _logical_T_607; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_609 = _logical_T_608[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_610 = {_logical_T_118, _logical_T_246}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_611 = _GEN[_lut_T] >> _logical_T_610; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_612 = _logical_T_611[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_613 = {_logical_T_119, _logical_T_247}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_614 = _GEN[_lut_T] >> _logical_T_613; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_615 = _logical_T_614[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_616 = {_logical_T_120, _logical_T_248}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_617 = _GEN[_lut_T] >> _logical_T_616; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_618 = _logical_T_617[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_619 = {_logical_T_121, _logical_T_249}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_620 = _GEN[_lut_T] >> _logical_T_619; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_621 = _logical_T_620[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_622 = {_logical_T_122, _logical_T_250}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_623 = _GEN[_lut_T] >> _logical_T_622; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_624 = _logical_T_623[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_625 = {_logical_T_123, _logical_T_251}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_626 = _GEN[_lut_T] >> _logical_T_625; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_627 = _logical_T_626[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_628 = {_logical_T_124, _logical_T_252}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_629 = _GEN[_lut_T] >> _logical_T_628; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_630 = _logical_T_629[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_631 = {_logical_T_125, _logical_T_253}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_632 = _GEN[_lut_T] >> _logical_T_631; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_633 = _logical_T_632[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_634 = {_logical_T_126, _logical_T_254}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_635 = _GEN[_lut_T] >> _logical_T_634; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_636 = _logical_T_635[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_637 = {_logical_T_127, _logical_T_255}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_638 = _GEN[_lut_T] >> _logical_T_637; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_639 = _logical_T_638[0]; // @[Atomics.scala:41:8] wire [1:0] logical_lo_lo_lo_lo_lo_lo = {_logical_T_261, _logical_T_258}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_lo_lo_lo_hi = {_logical_T_267, _logical_T_264}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_lo_lo_lo = {logical_lo_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_lo_lo_hi_lo = {_logical_T_273, _logical_T_270}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_lo_lo_hi_hi = {_logical_T_279, _logical_T_276}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_lo_lo_hi = {logical_lo_lo_lo_lo_hi_hi, logical_lo_lo_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_lo_lo_lo = {logical_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_lo_hi_lo_lo = {_logical_T_285, _logical_T_282}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_lo_hi_lo_hi = {_logical_T_291, _logical_T_288}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_lo_hi_lo = {logical_lo_lo_lo_hi_lo_hi, logical_lo_lo_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_lo_hi_hi_lo = {_logical_T_297, _logical_T_294}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_lo_hi_hi_hi = {_logical_T_303, _logical_T_300}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_lo_hi_hi = {logical_lo_lo_lo_hi_hi_hi, logical_lo_lo_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_lo_lo_hi = {logical_lo_lo_lo_hi_hi, logical_lo_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_lo_lo_lo = {logical_lo_lo_lo_hi, logical_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_hi_lo_lo_lo = {_logical_T_309, _logical_T_306}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_hi_lo_lo_hi = {_logical_T_315, _logical_T_312}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_hi_lo_lo = {logical_lo_lo_hi_lo_lo_hi, logical_lo_lo_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_hi_lo_hi_lo = {_logical_T_321, _logical_T_318}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_hi_lo_hi_hi = {_logical_T_327, _logical_T_324}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_hi_lo_hi = {logical_lo_lo_hi_lo_hi_hi, logical_lo_lo_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_lo_hi_lo = {logical_lo_lo_hi_lo_hi, logical_lo_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_hi_hi_lo_lo = {_logical_T_333, _logical_T_330}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_hi_hi_lo_hi = {_logical_T_339, _logical_T_336}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_hi_hi_lo = {logical_lo_lo_hi_hi_lo_hi, logical_lo_lo_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_hi_hi_hi_lo = {_logical_T_345, _logical_T_342}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_hi_hi_hi_hi = {_logical_T_351, _logical_T_348}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_hi_hi_hi = {logical_lo_lo_hi_hi_hi_hi, logical_lo_lo_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_lo_hi_hi = {logical_lo_lo_hi_hi_hi, logical_lo_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_lo_lo_hi = {logical_lo_lo_hi_hi, logical_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [31:0] logical_lo_lo = {logical_lo_lo_hi, logical_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_lo_lo_lo_lo = {_logical_T_357, _logical_T_354}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_lo_lo_lo_hi = {_logical_T_363, _logical_T_360}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_lo_lo_lo = {logical_lo_hi_lo_lo_lo_hi, logical_lo_hi_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_lo_lo_hi_lo = {_logical_T_369, _logical_T_366}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_lo_lo_hi_hi = {_logical_T_375, _logical_T_372}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_lo_lo_hi = {logical_lo_hi_lo_lo_hi_hi, logical_lo_hi_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_hi_lo_lo = {logical_lo_hi_lo_lo_hi, logical_lo_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_lo_hi_lo_lo = {_logical_T_381, _logical_T_378}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_lo_hi_lo_hi = {_logical_T_387, _logical_T_384}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_lo_hi_lo = {logical_lo_hi_lo_hi_lo_hi, logical_lo_hi_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_lo_hi_hi_lo = {_logical_T_393, _logical_T_390}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_lo_hi_hi_hi = {_logical_T_399, _logical_T_396}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_lo_hi_hi = {logical_lo_hi_lo_hi_hi_hi, logical_lo_hi_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_hi_lo_hi = {logical_lo_hi_lo_hi_hi, logical_lo_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_lo_hi_lo = {logical_lo_hi_lo_hi, logical_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_hi_lo_lo_lo = {_logical_T_405, _logical_T_402}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_hi_lo_lo_hi = {_logical_T_411, _logical_T_408}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_hi_lo_lo = {logical_lo_hi_hi_lo_lo_hi, logical_lo_hi_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_hi_lo_hi_lo = {_logical_T_417, _logical_T_414}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_hi_lo_hi_hi = {_logical_T_423, _logical_T_420}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_hi_lo_hi = {logical_lo_hi_hi_lo_hi_hi, logical_lo_hi_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_hi_hi_lo = {logical_lo_hi_hi_lo_hi, logical_lo_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_hi_hi_lo_lo = {_logical_T_429, _logical_T_426}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_hi_hi_lo_hi = {_logical_T_435, _logical_T_432}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_hi_hi_lo = {logical_lo_hi_hi_hi_lo_hi, logical_lo_hi_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_hi_hi_hi_lo = {_logical_T_441, _logical_T_438}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_hi_hi_hi_hi = {_logical_T_447, _logical_T_444}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_hi_hi_hi = {logical_lo_hi_hi_hi_hi_hi, logical_lo_hi_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_hi_hi_hi = {logical_lo_hi_hi_hi_hi, logical_lo_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_lo_hi_hi = {logical_lo_hi_hi_hi, logical_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [31:0] logical_lo_hi = {logical_lo_hi_hi, logical_lo_hi_lo}; // @[Atomics.scala:40:20] wire [63:0] logical_lo = {logical_lo_hi, logical_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_lo_lo_lo_lo = {_logical_T_453, _logical_T_450}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_lo_lo_lo_hi = {_logical_T_459, _logical_T_456}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_lo_lo_lo = {logical_hi_lo_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_lo_lo_hi_lo = {_logical_T_465, _logical_T_462}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_lo_lo_hi_hi = {_logical_T_471, _logical_T_468}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_lo_lo_hi = {logical_hi_lo_lo_lo_hi_hi, logical_hi_lo_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_lo_lo_lo = {logical_hi_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_lo_hi_lo_lo = {_logical_T_477, _logical_T_474}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_lo_hi_lo_hi = {_logical_T_483, _logical_T_480}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_lo_hi_lo = {logical_hi_lo_lo_hi_lo_hi, logical_hi_lo_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_lo_hi_hi_lo = {_logical_T_489, _logical_T_486}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_lo_hi_hi_hi = {_logical_T_495, _logical_T_492}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_lo_hi_hi = {logical_hi_lo_lo_hi_hi_hi, logical_hi_lo_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_lo_lo_hi = {logical_hi_lo_lo_hi_hi, logical_hi_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_hi_lo_lo = {logical_hi_lo_lo_hi, logical_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_hi_lo_lo_lo = {_logical_T_501, _logical_T_498}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_hi_lo_lo_hi = {_logical_T_507, _logical_T_504}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_hi_lo_lo = {logical_hi_lo_hi_lo_lo_hi, logical_hi_lo_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_hi_lo_hi_lo = {_logical_T_513, _logical_T_510}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_hi_lo_hi_hi = {_logical_T_519, _logical_T_516}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_hi_lo_hi = {logical_hi_lo_hi_lo_hi_hi, logical_hi_lo_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_lo_hi_lo = {logical_hi_lo_hi_lo_hi, logical_hi_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_hi_hi_lo_lo = {_logical_T_525, _logical_T_522}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_hi_hi_lo_hi = {_logical_T_531, _logical_T_528}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_hi_hi_lo = {logical_hi_lo_hi_hi_lo_hi, logical_hi_lo_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_hi_hi_hi_lo = {_logical_T_537, _logical_T_534}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_hi_hi_hi_hi = {_logical_T_543, _logical_T_540}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_hi_hi_hi = {logical_hi_lo_hi_hi_hi_hi, logical_hi_lo_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_lo_hi_hi = {logical_hi_lo_hi_hi_hi, logical_hi_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_hi_lo_hi = {logical_hi_lo_hi_hi, logical_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [31:0] logical_hi_lo = {logical_hi_lo_hi, logical_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_lo_lo_lo_lo = {_logical_T_549, _logical_T_546}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_lo_lo_lo_hi = {_logical_T_555, _logical_T_552}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_lo_lo_lo = {logical_hi_hi_lo_lo_lo_hi, logical_hi_hi_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_lo_lo_hi_lo = {_logical_T_561, _logical_T_558}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_lo_lo_hi_hi = {_logical_T_567, _logical_T_564}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_lo_lo_hi = {logical_hi_hi_lo_lo_hi_hi, logical_hi_hi_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_hi_lo_lo = {logical_hi_hi_lo_lo_hi, logical_hi_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_lo_hi_lo_lo = {_logical_T_573, _logical_T_570}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_lo_hi_lo_hi = {_logical_T_579, _logical_T_576}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_lo_hi_lo = {logical_hi_hi_lo_hi_lo_hi, logical_hi_hi_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_lo_hi_hi_lo = {_logical_T_585, _logical_T_582}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_lo_hi_hi_hi = {_logical_T_591, _logical_T_588}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_lo_hi_hi = {logical_hi_hi_lo_hi_hi_hi, logical_hi_hi_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_hi_lo_hi = {logical_hi_hi_lo_hi_hi, logical_hi_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_hi_hi_lo = {logical_hi_hi_lo_hi, logical_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_hi_lo_lo_lo = {_logical_T_597, _logical_T_594}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_hi_lo_lo_hi = {_logical_T_603, _logical_T_600}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_hi_lo_lo = {logical_hi_hi_hi_lo_lo_hi, logical_hi_hi_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_hi_lo_hi_lo = {_logical_T_609, _logical_T_606}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_hi_lo_hi_hi = {_logical_T_615, _logical_T_612}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_hi_lo_hi = {logical_hi_hi_hi_lo_hi_hi, logical_hi_hi_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_hi_hi_lo = {logical_hi_hi_hi_lo_hi, logical_hi_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_hi_hi_lo_lo = {_logical_T_621, _logical_T_618}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_hi_hi_lo_hi = {_logical_T_627, _logical_T_624}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_hi_hi_lo = {logical_hi_hi_hi_hi_lo_hi, logical_hi_hi_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_hi_hi_hi_lo = {_logical_T_633, _logical_T_630}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_hi_hi_hi_hi = {_logical_T_639, _logical_T_636}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_hi_hi_hi = {logical_hi_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_hi_hi_hi = {logical_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_hi_hi_hi = {logical_hi_hi_hi_hi, logical_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [31:0] logical_hi_hi = {logical_hi_hi_hi, logical_hi_hi_lo}; // @[Atomics.scala:40:20] wire [63:0] logical_hi = {logical_hi_hi, logical_hi_lo}; // @[Atomics.scala:40:20] wire [127:0] logical = {logical_hi, logical_lo}; // @[Atomics.scala:40:20] wire [1:0] _select_T_1 = adder ? 2'h2 : {1'h0, _select_T}; // @[Atomics.scala:8:7, :10:14, :18:28, :48:{8,24}] wire [1:0] _select_WIRE_2 = _select_T_1; // @[Atomics.scala:45:42, :48:8] wire [7:0][1:0] _GEN_0 = {{2'h0}, {2'h0}, {2'h0}, {2'h0}, {2'h3}, {_select_WIRE_2}, {2'h1}, {2'h1}}; // @[Atomics.scala:45:{19,42}] wire [1:0] select = io_write_0 ? 2'h1 : _GEN_0[io_a_opcode_0]; // @[Atomics.scala:8:7, :45:19] wire [1:0] selects_0 = _selects_T ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_1 = _selects_T_1 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_2 = _selects_T_2 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_3 = _selects_T_3 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_4 = _selects_T_4 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_5 = _selects_T_5 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_6 = _selects_T_6 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_7 = _selects_T_7 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_8 = _selects_T_8 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_9 = _selects_T_9 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_10 = _selects_T_10 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_11 = _selects_T_11 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_12 = _selects_T_12 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_13 = _selects_T_13 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_14 = _selects_T_14 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_15 = _selects_T_15 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [7:0] _io_data_out_T = io_data_in_0[7:0]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_0 = _io_data_out_T; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_1 = io_a_data_0[7:0]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_1 = _io_data_out_T_1; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_2 = sum[7:0]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_2 = _io_data_out_T_2; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_3 = logical[7:0]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_3 = _io_data_out_T_3; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_4 = io_data_in_0[15:8]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_1_0 = _io_data_out_T_4; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_5 = io_a_data_0[15:8]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_1_1 = _io_data_out_T_5; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_6 = sum[15:8]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_1_2 = _io_data_out_T_6; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_7 = logical[15:8]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_1_3 = _io_data_out_T_7; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_8 = io_data_in_0[23:16]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_2_0 = _io_data_out_T_8; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_9 = io_a_data_0[23:16]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_2_1 = _io_data_out_T_9; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_10 = sum[23:16]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_2_2 = _io_data_out_T_10; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_11 = logical[23:16]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_2_3 = _io_data_out_T_11; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_12 = io_data_in_0[31:24]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_3_0 = _io_data_out_T_12; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_13 = io_a_data_0[31:24]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_3_1 = _io_data_out_T_13; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_14 = sum[31:24]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_3_2 = _io_data_out_T_14; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_15 = logical[31:24]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_3_3 = _io_data_out_T_15; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_16 = io_data_in_0[39:32]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_4_0 = _io_data_out_T_16; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_17 = io_a_data_0[39:32]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_4_1 = _io_data_out_T_17; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_18 = sum[39:32]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_4_2 = _io_data_out_T_18; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_19 = logical[39:32]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_4_3 = _io_data_out_T_19; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_20 = io_data_in_0[47:40]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_5_0 = _io_data_out_T_20; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_21 = io_a_data_0[47:40]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_5_1 = _io_data_out_T_21; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_22 = sum[47:40]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_5_2 = _io_data_out_T_22; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_23 = logical[47:40]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_5_3 = _io_data_out_T_23; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_24 = io_data_in_0[55:48]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_6_0 = _io_data_out_T_24; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_25 = io_a_data_0[55:48]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_6_1 = _io_data_out_T_25; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_26 = sum[55:48]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_6_2 = _io_data_out_T_26; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_27 = logical[55:48]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_6_3 = _io_data_out_T_27; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_28 = io_data_in_0[63:56]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_7_0 = _io_data_out_T_28; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_29 = io_a_data_0[63:56]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_7_1 = _io_data_out_T_29; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_30 = sum[63:56]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_7_2 = _io_data_out_T_30; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_31 = logical[63:56]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_7_3 = _io_data_out_T_31; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_32 = io_data_in_0[71:64]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_8_0 = _io_data_out_T_32; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_33 = io_a_data_0[71:64]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_8_1 = _io_data_out_T_33; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_34 = sum[71:64]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_8_2 = _io_data_out_T_34; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_35 = logical[71:64]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_8_3 = _io_data_out_T_35; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_36 = io_data_in_0[79:72]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_9_0 = _io_data_out_T_36; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_37 = io_a_data_0[79:72]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_9_1 = _io_data_out_T_37; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_38 = sum[79:72]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_9_2 = _io_data_out_T_38; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_39 = logical[79:72]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_9_3 = _io_data_out_T_39; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_40 = io_data_in_0[87:80]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_10_0 = _io_data_out_T_40; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_41 = io_a_data_0[87:80]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_10_1 = _io_data_out_T_41; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_42 = sum[87:80]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_10_2 = _io_data_out_T_42; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_43 = logical[87:80]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_10_3 = _io_data_out_T_43; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_44 = io_data_in_0[95:88]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_11_0 = _io_data_out_T_44; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_45 = io_a_data_0[95:88]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_11_1 = _io_data_out_T_45; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_46 = sum[95:88]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_11_2 = _io_data_out_T_46; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_47 = logical[95:88]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_11_3 = _io_data_out_T_47; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_48 = io_data_in_0[103:96]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_12_0 = _io_data_out_T_48; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_49 = io_a_data_0[103:96]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_12_1 = _io_data_out_T_49; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_50 = sum[103:96]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_12_2 = _io_data_out_T_50; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_51 = logical[103:96]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_12_3 = _io_data_out_T_51; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_52 = io_data_in_0[111:104]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_13_0 = _io_data_out_T_52; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_53 = io_a_data_0[111:104]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_13_1 = _io_data_out_T_53; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_54 = sum[111:104]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_13_2 = _io_data_out_T_54; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_55 = logical[111:104]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_13_3 = _io_data_out_T_55; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_56 = io_data_in_0[119:112]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_14_0 = _io_data_out_T_56; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_57 = io_a_data_0[119:112]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_14_1 = _io_data_out_T_57; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_58 = sum[119:112]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_14_2 = _io_data_out_T_58; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_59 = logical[119:112]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_14_3 = _io_data_out_T_59; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_60 = io_data_in_0[127:120]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_15_0 = _io_data_out_T_60; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_61 = io_a_data_0[127:120]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_15_1 = _io_data_out_T_61; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_62 = sum[127:120]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_15_2 = _io_data_out_T_62; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_63 = logical[127:120]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_15_3 = _io_data_out_T_63; // @[Atomics.scala:59:{12,59}] wire [3:0][7:0] _GEN_1 = {{_io_data_out_WIRE_1_3}, {_io_data_out_WIRE_1_2}, {_io_data_out_WIRE_1_1}, {_io_data_out_WIRE_1_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_2 = {{_io_data_out_WIRE_3}, {_io_data_out_WIRE_2}, {_io_data_out_WIRE_1}, {_io_data_out_WIRE_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_lo_lo_lo = {_GEN_1[selects_1], _GEN_2[selects_0]}; // @[Atomics.scala:57:47, :58:21] wire [3:0][7:0] _GEN_3 = {{_io_data_out_WIRE_3_3}, {_io_data_out_WIRE_3_2}, {_io_data_out_WIRE_3_1}, {_io_data_out_WIRE_3_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_4 = {{_io_data_out_WIRE_2_3}, {_io_data_out_WIRE_2_2}, {_io_data_out_WIRE_2_1}, {_io_data_out_WIRE_2_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_lo_lo_hi = {_GEN_3[selects_3], _GEN_4[selects_2]}; // @[Atomics.scala:57:47, :58:21] wire [31:0] io_data_out_lo_lo = {io_data_out_lo_lo_hi, io_data_out_lo_lo_lo}; // @[Atomics.scala:58:21] wire [3:0][7:0] _GEN_5 = {{_io_data_out_WIRE_5_3}, {_io_data_out_WIRE_5_2}, {_io_data_out_WIRE_5_1}, {_io_data_out_WIRE_5_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_6 = {{_io_data_out_WIRE_4_3}, {_io_data_out_WIRE_4_2}, {_io_data_out_WIRE_4_1}, {_io_data_out_WIRE_4_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_lo_hi_lo = {_GEN_5[selects_5], _GEN_6[selects_4]}; // @[Atomics.scala:57:47, :58:21] wire [3:0][7:0] _GEN_7 = {{_io_data_out_WIRE_7_3}, {_io_data_out_WIRE_7_2}, {_io_data_out_WIRE_7_1}, {_io_data_out_WIRE_7_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_8 = {{_io_data_out_WIRE_6_3}, {_io_data_out_WIRE_6_2}, {_io_data_out_WIRE_6_1}, {_io_data_out_WIRE_6_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_lo_hi_hi = {_GEN_7[selects_7], _GEN_8[selects_6]}; // @[Atomics.scala:57:47, :58:21] wire [31:0] io_data_out_lo_hi = {io_data_out_lo_hi_hi, io_data_out_lo_hi_lo}; // @[Atomics.scala:58:21] wire [63:0] io_data_out_lo = {io_data_out_lo_hi, io_data_out_lo_lo}; // @[Atomics.scala:58:21] wire [3:0][7:0] _GEN_9 = {{_io_data_out_WIRE_9_3}, {_io_data_out_WIRE_9_2}, {_io_data_out_WIRE_9_1}, {_io_data_out_WIRE_9_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_10 = {{_io_data_out_WIRE_8_3}, {_io_data_out_WIRE_8_2}, {_io_data_out_WIRE_8_1}, {_io_data_out_WIRE_8_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_hi_lo_lo = {_GEN_9[selects_9], _GEN_10[selects_8]}; // @[Atomics.scala:57:47, :58:21] wire [3:0][7:0] _GEN_11 = {{_io_data_out_WIRE_11_3}, {_io_data_out_WIRE_11_2}, {_io_data_out_WIRE_11_1}, {_io_data_out_WIRE_11_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_12 = {{_io_data_out_WIRE_10_3}, {_io_data_out_WIRE_10_2}, {_io_data_out_WIRE_10_1}, {_io_data_out_WIRE_10_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_hi_lo_hi = {_GEN_11[selects_11], _GEN_12[selects_10]}; // @[Atomics.scala:57:47, :58:21] wire [31:0] io_data_out_hi_lo = {io_data_out_hi_lo_hi, io_data_out_hi_lo_lo}; // @[Atomics.scala:58:21] wire [3:0][7:0] _GEN_13 = {{_io_data_out_WIRE_13_3}, {_io_data_out_WIRE_13_2}, {_io_data_out_WIRE_13_1}, {_io_data_out_WIRE_13_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_14 = {{_io_data_out_WIRE_12_3}, {_io_data_out_WIRE_12_2}, {_io_data_out_WIRE_12_1}, {_io_data_out_WIRE_12_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_hi_hi_lo = {_GEN_13[selects_13], _GEN_14[selects_12]}; // @[Atomics.scala:57:47, :58:21] wire [3:0][7:0] _GEN_15 = {{_io_data_out_WIRE_15_3}, {_io_data_out_WIRE_15_2}, {_io_data_out_WIRE_15_1}, {_io_data_out_WIRE_15_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_16 = {{_io_data_out_WIRE_14_3}, {_io_data_out_WIRE_14_2}, {_io_data_out_WIRE_14_1}, {_io_data_out_WIRE_14_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_hi_hi_hi = {_GEN_15[selects_15], _GEN_16[selects_14]}; // @[Atomics.scala:57:47, :58:21] wire [31:0] io_data_out_hi_hi = {io_data_out_hi_hi_hi, io_data_out_hi_hi_lo}; // @[Atomics.scala:58:21] wire [63:0] io_data_out_hi = {io_data_out_hi_hi, io_data_out_hi_lo}; // @[Atomics.scala:58:21] assign _io_data_out_T_64 = {io_data_out_hi, io_data_out_lo}; // @[Atomics.scala:58:21] assign io_data_out_0 = _io_data_out_T_64; // @[Atomics.scala:8:7, :58:21] assign io_data_out = io_data_out_0; // @[Atomics.scala:8:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_4( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_6 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RegisterFile.scala: package saturn.backend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.tile.{CoreModule} import freechips.rocketchip.util._ import saturn.common._ class OldestRRArbiter(val n: Int)(implicit p: Parameters) extends Module { val io = IO(new ArbiterIO(new VectorReadReq, n)) val arb = Module(new RRArbiter(new VectorReadReq, n)) io <> arb.io val oldest_oh = io.in.map(i => i.valid && i.bits.oldest) //assert(PopCount(oldest_oh) <= 1.U) when (oldest_oh.orR) { io.chosen := VecInit(oldest_oh).asUInt io.out.valid := true.B io.out.bits := Mux1H(oldest_oh, io.in.map(_.bits)) for (i <- 0 until n) { io.in(i).ready := oldest_oh(i) && io.out.ready } } } class RegisterReadXbar(n: Int, banks: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val in = Vec(n, Flipped(new VectorReadIO)) val out = Vec(banks, new VectorReadIO) }) val arbs = Seq.fill(banks) { Module(new OldestRRArbiter(n)) } for (i <- 0 until banks) { io.out(i).req <> arbs(i).io.out } val bankOffset = log2Ceil(banks) for (i <- 0 until n) { val bank_sel = if (bankOffset == 0) true.B else UIntToOH(io.in(i).req.bits.eg(bankOffset-1,0)) for (j <- 0 until banks) { arbs(j).io.in(i).valid := io.in(i).req.valid && bank_sel(j) arbs(j).io.in(i).bits.eg := io.in(i).req.bits.eg >> bankOffset arbs(j).io.in(i).bits.oldest := io.in(i).req.bits.oldest } io.in(i).req.ready := Mux1H(bank_sel, arbs.map(_.io.in(i).ready)) io.in(i).resp := Mux1H(bank_sel, io.out.map(_.resp)) } } class RegisterFileBank(reads: Int, maskReads: Int, rows: Int, maskRows: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val read = Vec(reads, Flipped(new VectorReadIO)) val mask_read = Vec(maskReads, Flipped(new VectorReadIO)) val write = Input(Valid(new VectorWrite(dLen))) val ll_write = Flipped(Decoupled(new VectorWrite(dLen))) }) val ll_write_valid = RegInit(false.B) val ll_write_bits = Reg(new VectorWrite(dLen)) val vrf = Mem(rows, Vec(dLen, Bool())) val v0_mask = Mem(maskRows, Vec(dLen, Bool())) for (read <- io.read) { read.req.ready := !(ll_write_valid && read.req.bits.eg === ll_write_bits.eg) read.resp := DontCare when (read.req.valid) { read.resp := vrf.read(read.req.bits.eg).asUInt } } for (mask_read <- io.mask_read) { mask_read.req.ready := !(ll_write_valid && mask_read.req.bits.eg === ll_write_bits.eg) mask_read.resp := DontCare when (mask_read.req.valid) { mask_read.resp := v0_mask.read(mask_read.req.bits.eg).asUInt } } val write = WireInit(io.write) io.ll_write.ready := false.B if (vParams.vrfHiccupBuffer) { when (!io.write.valid) { // drain hiccup buffer write.valid := ll_write_valid \|\| io.ll_write.valid write.bits := Mux(ll_write_valid, ll_write_bits, io.ll_write.bits) ll_write_valid := false.B when (io.ll_write.valid && ll_write_valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } .elsewhen (!ll_write_valid) { // fill hiccup buffer when (io.ll_write.valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } } else { when (!io.write.valid) { io.ll_write.ready := true.B write.valid := io.ll_write.valid write.bits := io.ll_write.bits } } when (write.valid) { vrf.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) when (write.bits.eg < maskRows.U) { v0_mask.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) } } } class RegisterFile(reads: Seq[Int], maskReads: Seq[Int], pipeWrites: Int, llWrites: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val nBanks = vParams.vrfBanking // Support 1, 2, and 4 banks for the VRF require(nBanks == 1 \|\| nBanks == 2 \|\| nBanks == 4) val io = IO(new Bundle { val read = MixedVec(reads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val mask_read = MixedVec(maskReads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val pipe_writes = Vec(pipeWrites, Input(Valid(new VectorWrite(dLen)))) val ll_writes = Vec(llWrites, Flipped(Decoupled(new VectorWrite(dLen)))) }) val vrf = Seq.fill(nBanks) { Module(new RegisterFileBank(reads.size, maskReads.size, egsTotal/nBanks, if (egsPerVReg < nBanks) 1 else egsPerVReg / nBanks)) } reads.zipWithIndex.foreach { case (rc, i) => val xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.read(i) <> xbar.io.out(j) } xbar.io.in <> io.read(i) } maskReads.zipWithIndex.foreach { case (rc, i) => val mask_xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.mask_read(i) <> mask_xbar.io.out(j) } mask_xbar.io.in <> io.mask_read(i) } io.ll_writes.foreach(_.ready := false.B) vrf.zipWithIndex.foreach { case (rf, i) => val bank_match = io.pipe_writes.map { w => (w.bits.bankId === i.U) && w.valid } val bank_write_data = Mux1H(bank_match, io.pipe_writes.map(_.bits.data)) val bank_write_mask = Mux1H(bank_match, io.pipe_writes.map(_.bits.mask)) val bank_write_eg = Mux1H(bank_match, io.pipe_writes.map(_.bits.eg)) val bank_write_valid = bank_match.orR rf.io.write.valid := bank_write_valid rf.io.write.bits.data := bank_write_data rf.io.write.bits.mask := bank_write_mask rf.io.write.bits.eg := bank_write_eg >> vrfBankBits when (bank_write_valid) { PopCount(bank_match) === 1.U } val ll_arb = Module(new Arbiter(new VectorWrite(dLen), llWrites)) rf.io.ll_write <> ll_arb.io.out io.ll_writes.zipWithIndex.foreach { case (w, j) => ll_arb.io.in(j).valid := w.valid && w.bits.bankId === i.U ll_arb.io.in(j).bits.eg := w.bits.eg >> vrfBankBits ll_arb.io.in(j).bits.data := w.bits.data ll_arb.io.in(j).bits.mask := w.bits.mask when (ll_arb.io.in(j).ready && w.bits.bankId === i.U) { w.ready := true.B } } } }	module OldestRRArbiter( // @[RegisterFile.scala:10:7] input clock, // @[RegisterFile.scala:10:7] output io_in_0_ready, // @[RegisterFile.scala:11:14] input io_in_0_valid, // @[RegisterFile.scala:11:14] input [4:0] io_in_0_bits_eg, // @[RegisterFile.scala:11:14] input io_in_0_bits_oldest, // @[RegisterFile.scala:11:14] output io_in_1_ready, // @[RegisterFile.scala:11:14] input io_in_1_valid, // @[RegisterFile.scala:11:14] input [4:0] io_in_1_bits_eg, // @[RegisterFile.scala:11:14] input io_in_1_bits_oldest, // @[RegisterFile.scala:11:14] output io_in_2_ready, // @[RegisterFile.scala:11:14] input io_in_2_valid, // @[RegisterFile.scala:11:14] input [4:0] io_in_2_bits_eg, // @[RegisterFile.scala:11:14] input io_out_ready, // @[RegisterFile.scala:11:14] output io_out_valid, // @[RegisterFile.scala:11:14] output [4:0] io_out_bits_eg // @[RegisterFile.scala:11:14] ); wire _arb_io_in_0_ready; // @[RegisterFile.scala:13:19] wire _arb_io_in_1_ready; // @[RegisterFile.scala:13:19] wire _arb_io_in_2_ready; // @[RegisterFile.scala:13:19] wire _arb_io_out_valid; // @[RegisterFile.scala:13:19] wire [4:0] _arb_io_out_bits_eg; // @[RegisterFile.scala:13:19] wire oldest_oh_0 = io_in_0_valid & io_in_0_bits_oldest; // @[RegisterFile.scala:15:42] wire oldest_oh_1 = io_in_1_valid & io_in_1_bits_oldest; // @[RegisterFile.scala:15:42] wire _GEN = oldest_oh_0 \| oldest_oh_1; // @[RegisterFile.scala:15:42] RRArbiter arb ( // @[RegisterFile.scala:13:19] .clock (clock), .io_in_0_ready (_arb_io_in_0_ready), .io_in_0_valid (io_in_0_valid), .io_in_0_bits_eg (io_in_0_bits_eg), .io_in_1_ready (_arb_io_in_1_ready), .io_in_1_valid (io_in_1_valid), .io_in_1_bits_eg (io_in_1_bits_eg), .io_in_2_ready (_arb_io_in_2_ready), .io_in_2_valid (io_in_2_valid), .io_in_2_bits_eg (io_in_2_bits_eg), .io_out_ready (io_out_ready), .io_out_valid (_arb_io_out_valid), .io_out_bits_eg (_arb_io_out_bits_eg) ); // @[RegisterFile.scala:13:19] assign io_in_0_ready = _GEN ? oldest_oh_0 & io_out_ready : _arb_io_in_0_ready; // @[RegisterFile.scala:10:7, :13:19, :14:6, :15:42, :17:24, :22:{22,38}] assign io_in_1_ready = _GEN ? oldest_oh_1 & io_out_ready : _arb_io_in_1_ready; // @[RegisterFile.scala:10:7, :13:19, :14:6, :15:42, :17:24, :22:{22,38}] assign io_in_2_ready = ~_GEN & _arb_io_in_2_ready; // @[RegisterFile.scala:10:7, :13:19, :14:6, :17:24, :22:22] assign io_out_valid = _GEN \| _arb_io_out_valid; // @[RegisterFile.scala:10:7, :13:19, :14:6, :17:24, :19:18] assign io_out_bits_eg = _GEN ? (oldest_oh_0 ? io_in_0_bits_eg : 5'h0) \| (oldest_oh_1 ? io_in_1_bits_eg : 5'h0) : _arb_io_out_bits_eg; // @[Mux.scala:30:73] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_189( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first \| last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first \| last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid \|\| ((!w_releaseack \|\| !w_rprobeacklast \|\| !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst \|\| !w_pprobeackfirst \|\| !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB \|\| !io.status.bits.blockB) assert (!io.status.bits.nestC \|\| !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe \|\| !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) \|\| (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) \|\| (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid \|\| io.schedule.bits.b.valid \|\| io.schedule.bits.c.valid \|\| io.schedule.bits.d.valid \|\| io.schedule.bits.e.valid \|\| io.schedule.bits.x.valid \|\| io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock \|\| request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty \|\| request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) \|\| !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) \| Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid \|\| meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U \|\| !(request.opcode === PutFullData \|\| request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r \|\| p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c \|\| m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read \|\| clean release can lead to this state eviction(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_D, true) // MMIO write \|\| dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read \|\| clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write \|\| clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read \|\| clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done \| probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done \| probe_bit probes_toN := probes_toN \| Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT \|\| io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst \|\| last_probe w_rprobeacklast := w_rprobeacklast \|\| (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst \|\| last_probe w_pprobeacklast := w_pprobeacklast \|\| (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last \|\| request.offset === 0.U) w_pprobeack := w_pprobeack \|\| set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant \|\| io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U \|\| io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f \|\| p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read \|\| clean release can lead to this state bypass(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_D, true) // MMIO write \|\| dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid \|\| (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid \|\| (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit \|\| (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT \|\| new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock \|\| new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module MSHR_2( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h20; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h20; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body \|\| !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body \|\| !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) \|\| protocol.ready protocol.valid := (!is_const \|\| io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_\|\|_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink \| sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLCToNoC_7( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0; // @[package.scala:243:{46,71,76}] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 9'h1 \| tail_beats1 == 9'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_16( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_272 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_19( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire io_in_d_bits_denied = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1110 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1110; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1110; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] wire _T_1183 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1183; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1183; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1183; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1036 = _T_1110 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1036 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1036 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1036 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1036 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1036 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1082 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1082 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1051 = _T_1183 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1051 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1051 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1051 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1154 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1154 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1136 = _T_1183 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1136 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1136 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1136 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File util.scala: //*************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File execution-unit.scala: //****************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Execution Units //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // The issue window schedules micro-ops onto a specific execution pipeline // A given execution pipeline may contain multiple functional units; one or more // read ports, and one or more writeports. package boom.v4.exu import scala.collection.mutable.{ArrayBuffer} import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.{BP, SFenceReq, CSR} import freechips.rocketchip.rocket.constants.{MemoryOpConstants} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile import freechips.rocketchip.util._ import boom.v4.common._ import boom.v4.ifu.FTQInfo import boom.v4.util._ class Wakeup(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val bypassable = Bool() val speculative_mask = UInt(aluWidth.W) val rebusy = Bool() } class ExeUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val data = Bits(dataWidth.W) val predicated = Bool() // Was this predicated off? val fflags = Valid(UInt(tile.FPConstants.FLAGS_SZ.W)) } class MemGen(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val data = UInt(xLen.W) } class CSRResp(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val data = UInt(xLen.W) val addr = UInt(CSR.ADDRSZ.W) } abstract class ExecutionUnit(name: String)(implicit p: Parameters) extends BoomMultiIOModule { val fu_types = ArrayBuffer[(Int, Bool, String)]() def get_all_fu_types(): Vec[Bool] = { val r = WireInit(VecInit(Seq.fill(FC_SZ) { false.B })) fu_types.map { case (code, _, _) => { r(code) := true.B } } r } def get_ready_fu_types(): Vec[Bool] = { val r = WireInit(VecInit(Seq.fill(FC_SZ) { false.B })) fu_types.map { case (code, ready, _) => { when (ready) { r(code) := true.B } } } r } val io_kill = IO(Input(Bool())) val io_brupdate = IO(Input(new BrUpdateInfo)) val io_status = IO(Input(new freechips.rocketchip.rocket.MStatus)) val io_ready_fu_types = IO(Output(Vec(FC_SZ, Bool()))) val io_fcsr_rm = IO(Input(UInt(tile.FPConstants.RM_SZ.W))) override def toString = { BoomCoreStringPrefix(s"===${name}ExeUnit") + fu_types.map { case (_, _, s) => BoomCoreStringPrefix(s" - ${s}") }.reduce(_+_) } val io_iss_uop = IO(Input(Valid(new MicroOp))) val arb_uop = Reg(Valid(new MicroOp)) arb_uop.valid := io_iss_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, io_iss_uop.bits) arb_uop.bits := UpdateBrMask(io_brupdate, io_iss_uop.bits) val rrd_uop = Reg(Valid(new MicroOp)) rrd_uop.valid := arb_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, arb_uop.bits) rrd_uop.bits := UpdateBrMask(io_brupdate, arb_uop.bits) val exe_uop = Reg(Valid(new MicroOp)) exe_uop.valid := rrd_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, rrd_uop.bits) exe_uop.bits := UpdateBrMask(io_brupdate, rrd_uop.bits) } trait HasIrfReadPorts { this: ExecutionUnit => def nReaders: Int val io_arb_irf_reqs = IO(Vec(nReaders, Decoupled(UInt(maxPregSz.W)))) val io_arb_rebusys = IO(Input (Vec(lsuWidth, Valid(new Wakeup)))) val io_rrd_irf_resps = IO(Input (Vec(nReaders , UInt(xLen.W)))) val io_rrd_irf_bypasses = IO(Input (Vec(coreWidth + lsuWidth, Valid(new ExeUnitResp(xLen))))) def rrd_bypass_hit(prs: UInt, rdata: UInt): (Bool, UInt) = { val hits = io_rrd_irf_bypasses map { b => b.valid && prs === b.bits.uop.pdst } (hits.reduce(_\|\|_), Mux(hits.reduce(_\|\|_), Mux1H(hits, io_rrd_irf_bypasses.map(_.bits.data)), rdata)) } def rebusied(prs: UInt): Bool = { io_arb_rebusys.map { r => r.valid && r.bits.rebusy && r.bits.uop.pdst === prs }.reduce(_\|\|_) } io_arb_irf_reqs(0).valid := arb_uop.valid && arb_uop.bits.lrs1_rtype === RT_FIX && !arb_uop.bits.iw_p1_bypass_hint io_arb_irf_reqs(0).bits := arb_uop.bits.prs1 if (nReaders == 2) { io_arb_irf_reqs(1).valid := arb_uop.valid && arb_uop.bits.lrs2_rtype === RT_FIX && !arb_uop.bits.iw_p2_bypass_hint io_arb_irf_reqs(1).bits := arb_uop.bits.prs2 } val arb_rebusied_prs1 = arb_uop.bits.lrs1_rtype === RT_FIX && rebusied(arb_uop.bits.prs1) val arb_rebusied_prs2 = arb_uop.bits.lrs2_rtype === RT_FIX && rebusied(arb_uop.bits.prs2) && (nReaders == 2).B val arb_rebusied = arb_rebusied_prs1 \|\| arb_rebusied_prs2 val exe_rs1_data = Reg(UInt(xLen.W)) val exe_rs2_data = Reg(UInt(xLen.W)) val (rs1_hit, rs1_data) = rrd_bypass_hit(rrd_uop.bits.prs1, io_rrd_irf_resps(0)) assert(!(rrd_uop.valid && rrd_uop.bits.lrs1_rtype === RT_FIX && rrd_uop.bits.iw_p1_bypass_hint && !rs1_hit)) exe_rs1_data := Mux(rrd_uop.bits.lrs1_rtype === RT_ZERO, 0.U, rs1_data) if (nReaders == 2) { val (rs2_hit, rs2_data) = rrd_bypass_hit(rrd_uop.bits.prs2, io_rrd_irf_resps(1)) assert(!(rrd_uop.valid && rrd_uop.bits.lrs2_rtype === RT_FIX && rrd_uop.bits.iw_p2_bypass_hint && !rs2_hit)) exe_rs2_data := Mux(rrd_uop.bits.lrs2_rtype === RT_ZERO, 0.U, rs2_data) } else { exe_rs2_data := DontCare } } trait HasImmrfReadPort { this: ExecutionUnit => val io_arb_immrf_req = IO(Decoupled(UInt(immPregSz.W))) assert(io_arb_immrf_req.ready) val io_rrd_immrf_resp = IO(Input(UInt(xLen.W))) val io_rrd_immrf_wakeup = IO(Output(Valid(new Wakeup))) io_arb_immrf_req.valid := (arb_uop.valid && !arb_uop.bits.imm_sel.isOneOf(IS_N, IS_SH) ) io_arb_immrf_req.bits := arb_uop.bits.pimm io_rrd_immrf_wakeup.valid := (rrd_uop.valid && !rrd_uop.bits.imm_sel.isOneOf(IS_N, IS_SH) ) io_rrd_immrf_wakeup.bits.speculative_mask := false.B io_rrd_immrf_wakeup.bits.rebusy := false.B io_rrd_immrf_wakeup.bits.bypassable := false.B io_rrd_immrf_wakeup.bits.uop := rrd_uop.bits val exe_imm_data = RegNext(Mux(rrd_uop.bits.imm_sel === IS_SH, Sext(rrd_uop.bits.pimm, xLen), Sext(ImmGen(io_rrd_immrf_resp, rrd_uop.bits.imm_sel), xLen) )) } trait HasPrfReadPort { this: ExecutionUnit => val io_arb_prf_req = IO(Decoupled(UInt(log2Ceil(ftqSz).W))) assert(io_arb_prf_req.ready) val io_rrd_prf_resp = IO(Input(Bool())) io_arb_prf_req.valid := arb_uop.valid io_arb_prf_req.bits := arb_uop.bits.ppred val exe_pred_data = Reg(Bool()) exe_pred_data := io_rrd_prf_resp } trait HasBrfReadPort { this: ExecutionUnit => val io_arb_brf_req = IO(Decoupled(UInt(brTagSz.W))) assert(io_arb_brf_req.ready) val io_rrd_brf_resp = IO(Input(new BrInfoBundle)) io_arb_brf_req.valid := (arb_uop.valid && arb_uop.bits.is_br) io_arb_brf_req.bits := arb_uop.bits.br_tag exe_uop.bits.ldq_idx := io_rrd_brf_resp.ldq_idx exe_uop.bits.stq_idx := io_rrd_brf_resp.stq_idx exe_uop.bits.rxq_idx := io_rrd_brf_resp.rxq_idx } trait HasFrfReadPorts { this: ExecutionUnit => val io_arb_frf_reqs = IO(Vec(3, Decoupled(UInt(maxPregSz.W)))) val io_rrd_frf_resps = IO(Input (Vec(3, UInt((xLen+1).W)))) val io_rrd_frf_bypasses = IO(Input(Vec(fpWidth, Valid(new ExeUnitResp(fLen+1))))) def rrd_bypass_hit(prs: UInt, rdata: UInt): (Bool, UInt) = { val hits = io_rrd_frf_bypasses map { b => b.valid && prs === b.bits.uop.pdst } (hits.reduce(_\|\|_), Mux(hits.reduce(_\|\|_), Mux1H(hits, io_rrd_frf_bypasses.map(_.bits.data)), rdata)) } io_arb_frf_reqs(0).valid := arb_uop.valid && arb_uop.bits.lrs1_rtype === RT_FLT && !arb_uop.bits.iw_p1_bypass_hint io_arb_frf_reqs(0).bits := arb_uop.bits.prs1 io_arb_frf_reqs(1).valid := arb_uop.valid && arb_uop.bits.lrs2_rtype === RT_FLT && !arb_uop.bits.iw_p2_bypass_hint io_arb_frf_reqs(1).bits := arb_uop.bits.prs2 io_arb_frf_reqs(2).valid := arb_uop.valid && arb_uop.bits.frs3_en && !arb_uop.bits.iw_p3_bypass_hint io_arb_frf_reqs(2).bits := arb_uop.bits.prs3 val exe_rs1_data = Reg(UInt((fLen+1).W)) val exe_rs2_data = Reg(UInt((fLen+1).W)) val exe_rs3_data = Reg(UInt((fLen+1).W)) val (rs1_hit, rs1_data) = rrd_bypass_hit(rrd_uop.bits.prs1, io_rrd_frf_resps(0)) assert(!(rrd_uop.valid && rrd_uop.bits.lrs1_rtype === RT_FLT && rrd_uop.bits.iw_p1_bypass_hint && !rs1_hit)) exe_rs1_data := rs1_data val (rs2_hit, rs2_data) = rrd_bypass_hit(rrd_uop.bits.prs2, io_rrd_frf_resps(1)) assert(!(rrd_uop.valid && rrd_uop.bits.lrs2_rtype === RT_FLT && rrd_uop.bits.iw_p2_bypass_hint && !rs2_hit)) exe_rs2_data := rs2_data val (rs3_hit, rs3_data) = rrd_bypass_hit(rrd_uop.bits.prs3, io_rrd_frf_resps(2)) assert(!(rrd_uop.valid && rrd_uop.bits.iw_p3_bypass_hint && !rs3_hit)) exe_rs3_data := rs3_data } trait HasFtqReadPort { this: ExecutionUnit => val io_arb_ftq_reqs = IO(Vec(2, Decoupled(UInt(log2Ceil(ftqSz).W)))) val io_rrd_ftq_resps = IO(Vec(2, Input(new FTQInfo))) // Only allow one SFB branch through multiple pipes, to avoid unnecessary predicate wakeup logic io_arb_ftq_reqs(0).valid := arb_uop.valid && (arb_uop.bits.op1_sel === OP1_PC \|\| arb_uop.bits.is_sfb_br) io_arb_ftq_reqs(0).bits := arb_uop.bits.ftq_idx // Only JALR checks the next-pc io_arb_ftq_reqs(1).valid := arb_uop.valid && (arb_uop.bits.br_type === B_JR \|\| arb_uop.bits.is_sfb_br) io_arb_ftq_reqs(1).bits := WrapInc(arb_uop.bits.ftq_idx, ftqSz) val exe_ftq_data = Reg(Vec(2, new FTQInfo)) exe_ftq_data := io_rrd_ftq_resps } class MemExeUnit( val hasAGen : Boolean = false, val hasDGen : Boolean = false )(implicit p: Parameters) extends ExecutionUnit("Mem") with HasIrfReadPorts with HasImmrfReadPort { def nReaders = 1 val io_squash_iss = IO(Output(Bool())) io_squash_iss := (io_arb_irf_reqs(0).valid && !io_arb_irf_reqs(0).ready) when (io_squash_iss \|\| arb_rebusied) { val will_replay = arb_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, arb_uop.bits) && !arb_rebusied arb_uop.valid := will_replay arb_uop.bits := UpdateBrMask(io_brupdate, arb_uop.bits) arb_uop.bits.iw_p1_bypass_hint := false.B arb_uop.bits.iw_p2_bypass_hint := false.B rrd_uop.valid := false.B } val io_agen = if (hasAGen) { val loads_saturating = exe_uop.valid && exe_uop.bits.uses_ldq && exe_uop.bits.fu_code(FC_AGEN) val saturating_loads_counter = RegInit(0.U(5.W)) when (loads_saturating) { saturating_loads_counter := saturating_loads_counter + 1.U } .otherwise { saturating_loads_counter := 0.U } val pause_mem = RegNext(loads_saturating) && saturating_loads_counter === ~(0.U(5.W)) val load_ready = !pause_mem fu_types += ((FC_AGEN, load_ready, "AGen")) val sum = (exe_rs1_data.asSInt + exe_imm_data.asSInt).asUInt val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U, sum(63,vaddrBits) =/= 0.U) val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt val agen = IO(Output(Valid(new MemGen))) if (enableAgenStage) { val agen_reg = Reg(Valid(new MemGen)) agen_reg.valid := ( exe_uop.valid && exe_uop.bits.fu_code(FC_AGEN) && !IsKilledByBranch(io_brupdate, io_kill, exe_uop.bits) ) agen_reg.bits.uop := UpdateBrMask(io_brupdate, exe_uop.bits) agen_reg.bits.data := Sext(effective_address, xLen) agen := agen_reg } else { agen.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_AGEN) agen.bits.uop := exe_uop.bits agen.bits.data := Sext(effective_address, xLen) } Some(agen) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_AGEN))) None } val io_dgen = if (hasDGen) { fu_types += ((FC_DGEN, true.B, "DGen")) val dgen = IO(Output(Valid(new MemGen))) dgen.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_DGEN) dgen.bits.data := exe_rs1_data dgen.bits.uop := exe_uop.bits Some(dgen) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_DGEN))) None } io_ready_fu_types := get_ready_fu_types() } class UniqueExeUnit( val hasCSR : Boolean = false, val hasMul : Boolean = false, val hasDiv : Boolean = false, val hasIfpu : Boolean = false, val hasRocc : Boolean = false )(implicit p: Parameters) extends ExecutionUnit("Unq") with HasIrfReadPorts with HasImmrfReadPort with MemoryOpConstants { def nReaders = 2 val io_squash_iss = IO(Output(Bool())) io_squash_iss := ((io_arb_irf_reqs(0).valid && !io_arb_irf_reqs(0).ready) \|\| (io_arb_irf_reqs(1).valid && !io_arb_irf_reqs(1).ready)) when (io_squash_iss \|\| arb_rebusied) { val will_replay = arb_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, arb_uop.bits) && !arb_rebusied arb_uop.valid := will_replay arb_uop.bits := UpdateBrMask(io_brupdate, arb_uop.bits) arb_uop.bits.iw_p1_bypass_hint := false.B arb_uop.bits.iw_p2_bypass_hint := false.B rrd_uop.valid := false.B } val exe_int_req = Wire(new FuncUnitReq(xLen)) exe_int_req.uop := exe_uop.bits exe_int_req.rs1_data := exe_rs1_data exe_int_req.rs2_data := exe_rs2_data exe_int_req.rs3_data := DontCare exe_int_req.imm_data := exe_imm_data exe_int_req.pred_data := DontCare exe_int_req.ftq_info := DontCare val io_mul_resp = if (hasMul) { fu_types += ((FC_MUL, true.B, "IMul")) val imul = Module(new PipelinedMulUnit(imulLatency, xLen)) imul.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_MUL) imul.io.req.bits := exe_int_req imul.io.brupdate := io_brupdate imul.io.kill := io_kill imul.io.resp.ready := true.B val resp = IO(Output(Valid(new ExeUnitResp(xLen)))) resp := imul.io.resp Some(resp) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_MUL))) None } val (io_csr_resp, io_sfence) = if (hasCSR) { fu_types += ((FC_CSR, true.B, "CSR")) val alu = Module(new ALUUnit(dataWidth = xLen)) alu.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_CSR) alu.io.req.bits := exe_int_req alu.io.resp.ready := true.B alu.io.brupdate := io_brupdate alu.io.kill := io_kill val c = IO(Output(Valid(new CSRResp))) c.valid := RegNext(alu.io.resp.valid && exe_uop.bits.csr_cmd =/= CSR.N) c.bits.uop := RegNext(alu.io.resp.bits.uop) c.bits.data := RegNext(alu.io.resp.bits.data) c.bits.addr := RegNext(exe_imm_data) val s = IO(Valid(new SFenceReq)) s.valid := RegNext(exe_uop.valid && exe_uop.bits.is_sfence) s.bits.rs1 := RegNext(exe_uop.bits.pimm(0)) s.bits.rs2 := RegNext(exe_uop.bits.pimm(1)) s.bits.addr := RegNext(exe_rs1_data) s.bits.asid := RegNext(exe_rs2_data) s.bits.hv := RegNext(exe_uop.bits.mem_cmd === M_HFENCEV) s.bits.hg := RegNext(exe_uop.bits.mem_cmd === M_HFENCEG) (Some(c), Some(s)) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_CSR))) assert(!(exe_uop.valid && exe_uop.bits.mem_cmd === M_SFENCE)) (None, None) } val (io_rocc_resp, io_rocc_core) = if (hasRocc) { require(hasCSR) val rocc_core = IO(new RoCCShimCoreIO) val rocc_resp = IO(Decoupled(new ExeUnitResp(xLen))) val rocc = Module(new RoCCShim) rocc.io.req.valid := exe_uop.valid && exe_uop.bits.is_rocc rocc.io.req.bits := exe_int_req rocc.io.brupdate := io_brupdate // We should assert on this somewhere rocc.io.status := io_status rocc.io.exception := io_kill rocc_core <> rocc.io.core rocc_resp <> rocc.io.resp (Some(rocc_resp), Some(rocc_core)) } else { assert(!(exe_uop.valid && exe_uop.bits.is_rocc)) (None, None) } val (io_ifpu_resp) = if (hasIfpu) { val ifpu_ready = Wire(Bool()) fu_types += ((FC_I2F, ifpu_ready, "IFPU")) val ifpu = Module(new IntToFPUnit(latency=intToFpLatency)) ifpu.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_I2F) ifpu.io.req.bits := exe_int_req ifpu.io.req.bits.uop.fp_rm := exe_uop.bits.prs2(4,2) ifpu.io.req.bits.uop.fp_typ := exe_uop.bits.prs2(1,0) ifpu.io.fcsr_rm := io_fcsr_rm ifpu.io.brupdate := io_brupdate ifpu.io.kill := io_kill // buffer up results since we share write-port on integer regfile. val queue = Module(new BranchKillableQueue(new ExeUnitResp(xLen+1), entries = intToFpLatency + 6)) // TODO being overly conservative queue.io.enq <> ifpu.io.resp queue.io.brupdate := io_brupdate queue.io.flush := io_kill assert (!(queue.io.enq.valid && !queue.io.enq.ready)) ifpu_ready := RegNext(queue.io.count < 2.U) val ifpu_resp = IO(Decoupled(new ExeUnitResp(xLen+1))) ifpu_resp <> queue.io.deq (Some(ifpu_resp)) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_I2F))) (None) } val (io_div_resp) = if (hasDiv) { val div_ready = Wire(Bool()) fu_types += ((FC_DIV, div_ready, "IDiv")) val div = Module(new DivUnit(xLen)) assert(!(div.io.req.valid && !div.io.req.ready)) div.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_DIV) div.io.req.bits := exe_int_req div.io.brupdate := io_brupdate div.io.kill := io_kill div_ready := (div.io.req.ready && !(exe_uop.valid && exe_uop.bits.fu_code(FC_DIV)) && !(rrd_uop.valid && rrd_uop.bits.fu_code(FC_DIV)) && !(arb_uop.valid && arb_uop.bits.fu_code(FC_DIV)) ) val div_resp = IO(Decoupled(new ExeUnitResp(xLen))) div_resp <> div.io.resp Some(div_resp) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_DIV))) (None) } io_ready_fu_types := get_ready_fu_types() } class ALUExeUnit( val id: Int )(implicit p: Parameters) extends ExecutionUnit("Alu") with HasIrfReadPorts with HasPrfReadPort with HasImmrfReadPort with HasBrfReadPort with HasFtqReadPort { def nReaders = 2 val io_fast_wakeup = IO(Output(Valid(new Wakeup))) io_fast_wakeup.valid := ( io_iss_uop.valid && (io_iss_uop.bits.dst_rtype === RT_FIX) ) io_fast_wakeup.bits.uop := io_iss_uop.bits io_fast_wakeup.bits.speculative_mask := (1 << id).U io_fast_wakeup.bits.rebusy := false.B io_fast_wakeup.bits.bypassable := true.B val io_fast_pred_wakeup = IO(Output(Valid(new Wakeup))) io_fast_pred_wakeup.valid := rrd_uop.valid && rrd_uop.bits.is_sfb_br io_fast_pred_wakeup.bits.uop := rrd_uop.bits io_fast_pred_wakeup.bits.speculative_mask := 0.U io_fast_pred_wakeup.bits.rebusy := false.B io_fast_pred_wakeup.bits.bypassable := false.B val io_squash_iss = IO(Output(Bool())) io_squash_iss := ((io_arb_irf_reqs(0).valid && !io_arb_irf_reqs(0).ready) \|\| (io_arb_irf_reqs(1).valid && !io_arb_irf_reqs(1).ready) \|\| (io_arb_ftq_reqs(0).valid && !io_arb_ftq_reqs(0).ready) \|\| (io_arb_ftq_reqs(1).valid && !io_arb_ftq_reqs(1).ready)) val io_child_rebusy = IO(Output(UInt(aluWidth.W))) io_child_rebusy := 0.U when (arb_rebusied && arb_uop.valid) { io_child_rebusy := (1 << id).U } // The arbiter didn't grant us a slot. Thus, we should replay the instruction in this slot, // But next time we read, it reads from the regfile, not the bypass paths, so disable the bypass hints when (io_squash_iss \|\| arb_rebusied) { val will_replay = arb_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, arb_uop.bits) && !arb_rebusied arb_uop.valid := will_replay arb_uop.bits := UpdateBrMask(io_brupdate, arb_uop.bits) arb_uop.bits.iw_p1_bypass_hint := false.B arb_uop.bits.iw_p2_bypass_hint := false.B rrd_uop.valid := false.B } val exe_int_req = Wire(new FuncUnitReq(xLen)) exe_int_req.uop := exe_uop.bits exe_int_req.rs1_data := exe_rs1_data exe_int_req.rs2_data := exe_rs2_data exe_int_req.rs3_data := DontCare exe_int_req.imm_data := exe_imm_data exe_int_req.pred_data := exe_pred_data exe_int_req.ftq_info := exe_ftq_data fu_types += ((FC_ALU, true.B, "ALU")) val alu = Module(new ALUUnit(dataWidth = xLen)) alu.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_ALU) alu.io.req.bits := exe_int_req alu.io.resp.ready := true.B alu.io.brupdate := io_brupdate alu.io.kill := io_kill val io_alu_resp = IO(Output(Valid(new ExeUnitResp(xLen)))) io_alu_resp.valid := alu.io.resp.valid io_alu_resp.bits := alu.io.resp.bits val io_brinfo = IO(Output(Valid(new BrResolutionInfo))) io_brinfo := alu.io.brinfo io_ready_fu_types := get_ready_fu_types() } class FPExeUnit(val hasFDiv: Boolean = false, val hasFpiu: Boolean = false)(implicit p: Parameters) extends ExecutionUnit("FP") with tile.HasFPUParameters with HasFrfReadPorts { val io_squash_iss = IO(Output(Bool())) io_squash_iss := ( (io_arb_frf_reqs(0).valid && !io_arb_frf_reqs(0).ready) \|\| (io_arb_frf_reqs(1).valid && !io_arb_frf_reqs(1).ready) \|\| (io_arb_frf_reqs(2).valid && !io_arb_frf_reqs(2).ready) ) when (io_squash_iss) { val will_replay = arb_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, arb_uop.bits) arb_uop.valid := will_replay arb_uop.bits := UpdateBrMask(io_brupdate, arb_uop.bits) arb_uop.bits.iw_p1_bypass_hint := false.B arb_uop.bits.iw_p2_bypass_hint := false.B arb_uop.bits.iw_p3_bypass_hint := false.B rrd_uop.valid := false.B } val exe_fp_req = Wire(new FuncUnitReq(xLen+1)) exe_fp_req.uop := exe_uop.bits exe_fp_req.rs1_data := exe_rs1_data exe_fp_req.rs2_data := exe_rs2_data exe_fp_req.rs3_data := exe_rs3_data exe_fp_req.pred_data := DontCare exe_fp_req.imm_data := DontCare exe_fp_req.ftq_info := DontCare val fpu = Module(new FPUUnit) fu_types += ((FC_FPU, true.B, "FPU")) fpu.io.req.valid := exe_uop.valid && ( exe_uop.bits.fu_code(FC_FPU) \|\| (if (hasFpiu) exe_uop.bits.fu_code(FC_F2I) else false.B) ) fpu.io.req.bits := exe_fp_req fpu.io.fcsr_rm := io_fcsr_rm fpu.io.brupdate := io_brupdate fpu.io.kill := io_kill fpu.io.resp.ready := true.B val io_wakeup = IO(Output(Valid(new Wakeup))) val fastWakeupLatency = dfmaLatency - 3 // Three stages WAKE-ISS-ARB require (fastWakeupLatency >= 0) val fast_wakeups = Wire(Vec(fastWakeupLatency + 1, Valid(new Wakeup))) fast_wakeups(0).valid := exe_uop.valid && exe_uop.bits.fu_code(FC_FPU) fast_wakeups(0).bits.uop := exe_uop.bits fast_wakeups(0).bits.speculative_mask := 0.U fast_wakeups(0).bits.rebusy := false.B fast_wakeups(0).bits.bypassable := true.B for (i <- 0 until fastWakeupLatency) { fast_wakeups(i+1) := RegNext(UpdateBrMask(io_brupdate, io_kill, fast_wakeups(i))) } io_wakeup := fast_wakeups(fastWakeupLatency) val io_fpu_resp = IO(Output(Valid(new ExeUnitResp(xLen+1)))) io_fpu_resp.valid := fpu.io.resp.valid && !fpu.io.resp.bits.uop.fu_code(FC_F2I) io_fpu_resp.bits := fpu.io.resp.bits val io_fdiv_resp = if (hasFDiv) { val fdivsqrt_ready = Wire(Bool()) fu_types += ((FC_FDV, fdivsqrt_ready, "FDiv")) val fdivsqrt = Module(new FDivSqrtUnit2) assert(!(fdivsqrt.io.req.valid && !fdivsqrt.io.req.ready)) fdivsqrt.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_FDV) fdivsqrt.io.req.bits := exe_fp_req fdivsqrt.io.brupdate := io_brupdate fdivsqrt.io.kill := io_kill fdivsqrt.io.fcsr_rm := io_fcsr_rm fdivsqrt_ready := (fdivsqrt.io.req.ready && !(exe_uop.valid && exe_uop.bits.fu_code(FC_FDV)) && !(rrd_uop.valid && rrd_uop.bits.fu_code(FC_FDV)) && !(arb_uop.valid && arb_uop.bits.fu_code(FC_FDV)) ) val fdiv_resp = IO(Decoupled(new ExeUnitResp(xLen+1))) fdiv_resp <> fdivsqrt.io.resp Some(fdiv_resp) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_FDV))) None } val (io_fpiu_resp, io_dgen) = if (hasFpiu) { val fpiu_ready = Wire(Bool()) fu_types += ((FC_F2I, fpiu_ready, "Fpiu")) val queue = Module(new BranchKillableQueue(new ExeUnitResp(xLen+1), entries = dfmaLatency + 6)) // TODO being overly conservative fpiu_ready := RegNext(queue.io.count < 2.U) queue.io.enq.valid := ( fpu.io.resp.valid && fpu.io.resp.bits.uop.fu_code(FC_F2I) && !fpu.io.resp.bits.uop.uses_stq) // STA means store data gen for floating point queue.io.enq.bits := fpu.io.resp.bits queue.io.brupdate := io_brupdate queue.io.flush := io_kill assert(!(queue.io.enq.valid && !queue.io.enq.ready)) val fpiu_resp = IO(Decoupled(new ExeUnitResp(xLen))) fpiu_resp <> queue.io.deq val dgen = IO(Valid(new MemGen)) dgen.valid := RegNext(exe_uop.valid && exe_uop.bits.uses_stq && !IsKilledByBranch(io_brupdate, io_kill, exe_uop.bits)) dgen.bits.uop := RegNext(exe_uop.bits) dgen.bits.data := RegNext(ieee(exe_rs2_data)) (Some(fpiu_resp), Some(dgen)) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_F2I))) (None, None) } io_ready_fu_types := get_ready_fu_types }	module ALUExeUnit_1( // @[execution-unit.scala:492:7] input clock, // @[execution-unit.scala:492:7] input reset, // @[execution-unit.scala:492:7] input io_kill, // @[execution-unit.scala:79:19] input [11:0] io_brupdate_b1_resolve_mask, // @[execution-unit.scala:80:23] input [11:0] io_brupdate_b1_mispredict_mask, // @[execution-unit.scala:80:23] input [31:0] io_brupdate_b2_uop_inst, // @[execution-unit.scala:80:23] input [31:0] io_brupdate_b2_uop_debug_inst, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_rvc, // @[execution-unit.scala:80:23] input [39:0] io_brupdate_b2_uop_debug_pc, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iq_type_0, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iq_type_1, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iq_type_2, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iq_type_3, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_0, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_1, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_2, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_3, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_4, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_5, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_6, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_7, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_8, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_9, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_issued, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[execution-unit.scala:80:23] input [11:0] io_brupdate_b2_uop_br_mask, // @[execution-unit.scala:80:23] input [3:0] io_brupdate_b2_uop_br_tag, // @[execution-unit.scala:80:23] input [3:0] io_brupdate_b2_uop_br_type, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_sfb, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_fence, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_fencei, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_sfence, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_amo, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_eret, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_sys_pc2epc, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_rocc, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_mov, // @[execution-unit.scala:80:23] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_edge_inst, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_pc_lob, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_taken, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_imm_rename, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_imm_sel, // @[execution-unit.scala:80:23] input [4:0] io_brupdate_b2_uop_pimm, // @[execution-unit.scala:80:23] input [19:0] io_brupdate_b2_uop_imm_packed, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_op1_sel, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_op2_sel, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_wen, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_toint, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_fma, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_div, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_vec, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_rob_idx, // @[execution-unit.scala:80:23] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[execution-unit.scala:80:23] input [3:0] io_brupdate_b2_uop_stq_idx, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[execution-unit.scala:80:23] input [6:0] io_brupdate_b2_uop_pdst, // @[execution-unit.scala:80:23] input [6:0] io_brupdate_b2_uop_prs1, // @[execution-unit.scala:80:23] input [6:0] io_brupdate_b2_uop_prs2, // @[execution-unit.scala:80:23] input [6:0] io_brupdate_b2_uop_prs3, // @[execution-unit.scala:80:23] input [4:0] io_brupdate_b2_uop_ppred, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_prs1_busy, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_prs2_busy, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_prs3_busy, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_ppred_busy, // @[execution-unit.scala:80:23] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_exception, // @[execution-unit.scala:80:23] input [63:0] io_brupdate_b2_uop_exc_cause, // @[execution-unit.scala:80:23] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_mem_size, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_mem_signed, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_uses_ldq, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_uses_stq, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_unique, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_flush_on_commit, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_ldst_is_rs1, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_ldst, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_lrs1, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_lrs2, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_lrs3, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_frs3_en, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fcn_dw, // @[execution-unit.scala:80:23] input [4:0] io_brupdate_b2_uop_fcn_op, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_val, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_fp_rm, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_fp_typ, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_xcpt_pf_if, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_xcpt_ae_if, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_xcpt_ma_if, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_bp_debug_if, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_bp_xcpt_if, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[execution-unit.scala:80:23] input io_brupdate_b2_mispredict, // @[execution-unit.scala:80:23] input io_brupdate_b2_taken, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_cfi_type, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_pc_sel, // @[execution-unit.scala:80:23] input [39:0] io_brupdate_b2_jalr_target, // @[execution-unit.scala:80:23] input [20:0] io_brupdate_b2_target_offset, // @[execution-unit.scala:80:23] input io_status_debug, // @[execution-unit.scala:81:21] input io_status_cease, // @[execution-unit.scala:81:21] input io_status_wfi, // @[execution-unit.scala:81:21] input [1:0] io_status_dprv, // @[execution-unit.scala:81:21] input io_status_dv, // @[execution-unit.scala:81:21] input [1:0] io_status_prv, // @[execution-unit.scala:81:21] input io_status_v, // @[execution-unit.scala:81:21] input io_status_sd, // @[execution-unit.scala:81:21] input io_status_mpv, // @[execution-unit.scala:81:21] input io_status_gva, // @[execution-unit.scala:81:21] input io_status_tsr, // @[execution-unit.scala:81:21] input io_status_tw, // @[execution-unit.scala:81:21] input io_status_tvm, // @[execution-unit.scala:81:21] input io_status_mxr, // @[execution-unit.scala:81:21] input io_status_sum, // @[execution-unit.scala:81:21] input io_status_mprv, // @[execution-unit.scala:81:21] input [1:0] io_status_fs, // @[execution-unit.scala:81:21] input [1:0] io_status_mpp, // @[execution-unit.scala:81:21] input io_status_spp, // @[execution-unit.scala:81:21] input io_status_mpie, // @[execution-unit.scala:81:21] input io_status_spie, // @[execution-unit.scala:81:21] input io_status_mie, // @[execution-unit.scala:81:21] input io_status_sie, // @[execution-unit.scala:81:21] input [2:0] io_fcsr_rm, // @[execution-unit.scala:84:22] input io_iss_uop_valid, // @[execution-unit.scala:90:22] input [31:0] io_iss_uop_bits_inst, // @[execution-unit.scala:90:22] input [31:0] io_iss_uop_bits_debug_inst, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_rvc, // @[execution-unit.scala:90:22] input [39:0] io_iss_uop_bits_debug_pc, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iq_type_0, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iq_type_1, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iq_type_2, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iq_type_3, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_0, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_1, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_2, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_3, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_4, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_5, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_6, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_7, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_8, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_9, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iw_issued, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_iw_p1_speculative_child, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_iw_p2_speculative_child, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iw_p1_bypass_hint, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iw_p2_bypass_hint, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iw_p3_bypass_hint, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_dis_col_sel, // @[execution-unit.scala:90:22] input [11:0] io_iss_uop_bits_br_mask, // @[execution-unit.scala:90:22] input [3:0] io_iss_uop_bits_br_tag, // @[execution-unit.scala:90:22] input [3:0] io_iss_uop_bits_br_type, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_sfb, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_fence, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_fencei, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_sfence, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_amo, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_eret, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_sys_pc2epc, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_rocc, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_mov, // @[execution-unit.scala:90:22] input [4:0] io_iss_uop_bits_ftq_idx, // @[execution-unit.scala:90:22] input io_iss_uop_bits_edge_inst, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_pc_lob, // @[execution-unit.scala:90:22] input io_iss_uop_bits_taken, // @[execution-unit.scala:90:22] input io_iss_uop_bits_imm_rename, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_imm_sel, // @[execution-unit.scala:90:22] input [4:0] io_iss_uop_bits_pimm, // @[execution-unit.scala:90:22] input [19:0] io_iss_uop_bits_imm_packed, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_op1_sel, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_op2_sel, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_ldst, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_wen, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_ren1, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_ren2, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_ren3, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_swap12, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_swap23, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_fp_ctrl_typeTagIn, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_fp_ctrl_typeTagOut, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_fromint, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_toint, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_fastpipe, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_fma, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_div, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_sqrt, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_wflags, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_vec, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_rob_idx, // @[execution-unit.scala:90:22] input [3:0] io_iss_uop_bits_ldq_idx, // @[execution-unit.scala:90:22] input [3:0] io_iss_uop_bits_stq_idx, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_rxq_idx, // @[execution-unit.scala:90:22] input [6:0] io_iss_uop_bits_pdst, // @[execution-unit.scala:90:22] input [6:0] io_iss_uop_bits_prs1, // @[execution-unit.scala:90:22] input [6:0] io_iss_uop_bits_prs2, // @[execution-unit.scala:90:22] input [6:0] io_iss_uop_bits_prs3, // @[execution-unit.scala:90:22] input [4:0] io_iss_uop_bits_ppred, // @[execution-unit.scala:90:22] input io_iss_uop_bits_prs1_busy, // @[execution-unit.scala:90:22] input io_iss_uop_bits_prs2_busy, // @[execution-unit.scala:90:22] input io_iss_uop_bits_prs3_busy, // @[execution-unit.scala:90:22] input io_iss_uop_bits_ppred_busy, // @[execution-unit.scala:90:22] input [6:0] io_iss_uop_bits_stale_pdst, // @[execution-unit.scala:90:22] input io_iss_uop_bits_exception, // @[execution-unit.scala:90:22] input [63:0] io_iss_uop_bits_exc_cause, // @[execution-unit.scala:90:22] input [4:0] io_iss_uop_bits_mem_cmd, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_mem_size, // @[execution-unit.scala:90:22] input io_iss_uop_bits_mem_signed, // @[execution-unit.scala:90:22] input io_iss_uop_bits_uses_ldq, // @[execution-unit.scala:90:22] input io_iss_uop_bits_uses_stq, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_unique, // @[execution-unit.scala:90:22] input io_iss_uop_bits_flush_on_commit, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_csr_cmd, // @[execution-unit.scala:90:22] input io_iss_uop_bits_ldst_is_rs1, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_ldst, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_lrs1, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_lrs2, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_lrs3, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_dst_rtype, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_lrs1_rtype, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_lrs2_rtype, // @[execution-unit.scala:90:22] input io_iss_uop_bits_frs3_en, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fcn_dw, // @[execution-unit.scala:90:22] input [4:0] io_iss_uop_bits_fcn_op, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_val, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_fp_rm, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_fp_typ, // @[execution-unit.scala:90:22] input io_iss_uop_bits_xcpt_pf_if, // @[execution-unit.scala:90:22] input io_iss_uop_bits_xcpt_ae_if, // @[execution-unit.scala:90:22] input io_iss_uop_bits_xcpt_ma_if, // @[execution-unit.scala:90:22] input io_iss_uop_bits_bp_debug_if, // @[execution-unit.scala:90:22] input io_iss_uop_bits_bp_xcpt_if, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_debug_fsrc, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_debug_tsrc, // @[execution-unit.scala:90:22] input io_arb_irf_reqs_0_ready, // @[execution-unit.scala:106:27] output io_arb_irf_reqs_0_valid, // @[execution-unit.scala:106:27] output [6:0] io_arb_irf_reqs_0_bits, // @[execution-unit.scala:106:27] input io_arb_irf_reqs_1_ready, // @[execution-unit.scala:106:27] output io_arb_irf_reqs_1_valid, // @[execution-unit.scala:106:27] output [6:0] io_arb_irf_reqs_1_bits, // @[execution-unit.scala:106:27] input io_arb_rebusys_0_valid, // @[execution-unit.scala:107:27] input [31:0] io_arb_rebusys_0_bits_uop_inst, // @[execution-unit.scala:107:27] input [31:0] io_arb_rebusys_0_bits_uop_debug_inst, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_rvc, // @[execution-unit.scala:107:27] input [39:0] io_arb_rebusys_0_bits_uop_debug_pc, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iq_type_0, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iq_type_1, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iq_type_2, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iq_type_3, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_0, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_1, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_2, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_3, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_4, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_5, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_6, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_7, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_8, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_9, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_issued, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_dis_col_sel, // @[execution-unit.scala:107:27] input [11:0] io_arb_rebusys_0_bits_uop_br_mask, // @[execution-unit.scala:107:27] input [3:0] io_arb_rebusys_0_bits_uop_br_tag, // @[execution-unit.scala:107:27] input [3:0] io_arb_rebusys_0_bits_uop_br_type, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_sfb, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_fence, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_fencei, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_sfence, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_amo, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_eret, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_rocc, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_mov, // @[execution-unit.scala:107:27] input [4:0] io_arb_rebusys_0_bits_uop_ftq_idx, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_edge_inst, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_pc_lob, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_taken, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_imm_rename, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_imm_sel, // @[execution-unit.scala:107:27] input [4:0] io_arb_rebusys_0_bits_uop_pimm, // @[execution-unit.scala:107:27] input [19:0] io_arb_rebusys_0_bits_uop_imm_packed, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_op1_sel, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_op2_sel, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_div, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_rob_idx, // @[execution-unit.scala:107:27] input [3:0] io_arb_rebusys_0_bits_uop_ldq_idx, // @[execution-unit.scala:107:27] input [3:0] io_arb_rebusys_0_bits_uop_stq_idx, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_rxq_idx, // @[execution-unit.scala:107:27] input [6:0] io_arb_rebusys_0_bits_uop_pdst, // @[execution-unit.scala:107:27] input [6:0] io_arb_rebusys_0_bits_uop_prs1, // @[execution-unit.scala:107:27] input [6:0] io_arb_rebusys_0_bits_uop_prs2, // @[execution-unit.scala:107:27] input [6:0] io_arb_rebusys_0_bits_uop_prs3, // @[execution-unit.scala:107:27] input [4:0] io_arb_rebusys_0_bits_uop_ppred, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_prs1_busy, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_prs2_busy, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_prs3_busy, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_ppred_busy, // @[execution-unit.scala:107:27] input [6:0] io_arb_rebusys_0_bits_uop_stale_pdst, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_exception, // @[execution-unit.scala:107:27] input [63:0] io_arb_rebusys_0_bits_uop_exc_cause, // @[execution-unit.scala:107:27] input [4:0] io_arb_rebusys_0_bits_uop_mem_cmd, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_mem_size, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_mem_signed, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_uses_ldq, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_uses_stq, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_unique, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_flush_on_commit, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_csr_cmd, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_ldst, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_lrs1, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_lrs2, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_lrs3, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_dst_rtype, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_frs3_en, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fcn_dw, // @[execution-unit.scala:107:27] input [4:0] io_arb_rebusys_0_bits_uop_fcn_op, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_val, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_fp_rm, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_fp_typ, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_bp_debug_if, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_debug_fsrc, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_debug_tsrc, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_bypassable, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_speculative_mask, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_rebusy, // @[execution-unit.scala:107:27] input [63:0] io_rrd_irf_resps_0, // @[execution-unit.scala:108:31] input [63:0] io_rrd_irf_resps_1, // @[execution-unit.scala:108:31] input io_rrd_irf_bypasses_0_valid, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_0_bits_uop_inst, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_0_bits_uop_debug_inst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_rvc, // @[execution-unit.scala:109:31] input [39:0] io_rrd_irf_bypasses_0_bits_uop_debug_pc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iq_type_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iq_type_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iq_type_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iq_type_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_4, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_5, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_6, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_7, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_8, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_9, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_issued, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31] input [11:0] io_rrd_irf_bypasses_0_bits_uop_br_mask, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_0_bits_uop_br_tag, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_0_bits_uop_br_type, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_sfb, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_fence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_fencei, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_sfence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_amo, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_eret, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_rocc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_mov, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_uop_ftq_idx, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_edge_inst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_pc_lob, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_taken, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_imm_rename, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_imm_sel, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_uop_pimm, // @[execution-unit.scala:109:31] input [19:0] io_rrd_irf_bypasses_0_bits_uop_imm_packed, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_op1_sel, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_op2_sel, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_rob_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_0_bits_uop_ldq_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_0_bits_uop_stq_idx, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_rxq_idx, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_0_bits_uop_pdst, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_0_bits_uop_prs1, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_0_bits_uop_prs2, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_0_bits_uop_prs3, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_uop_ppred, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_prs1_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_prs2_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_prs3_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_ppred_busy, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_0_bits_uop_stale_pdst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_exception, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_0_bits_uop_exc_cause, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_uop_mem_cmd, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_mem_size, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_mem_signed, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_uses_ldq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_uses_stq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_unique, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_csr_cmd, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_ldst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_lrs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_lrs2, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_lrs3, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_dst_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_frs3_en, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fcn_dw, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_uop_fcn_op, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_val, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_fp_rm, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_fp_typ, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_0_bits_data, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_predicated, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_fflags_valid, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_fflags_bits, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_valid, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_1_bits_uop_inst, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_1_bits_uop_debug_inst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_rvc, // @[execution-unit.scala:109:31] input [39:0] io_rrd_irf_bypasses_1_bits_uop_debug_pc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iq_type_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iq_type_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iq_type_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iq_type_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_4, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_5, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_6, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_7, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_8, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_9, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_issued, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31] input [11:0] io_rrd_irf_bypasses_1_bits_uop_br_mask, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_1_bits_uop_br_tag, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_1_bits_uop_br_type, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_sfb, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_fence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_fencei, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_sfence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_amo, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_eret, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_rocc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_mov, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_1_bits_uop_ftq_idx, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_edge_inst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_pc_lob, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_taken, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_imm_rename, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_imm_sel, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_1_bits_uop_pimm, // @[execution-unit.scala:109:31] input [19:0] io_rrd_irf_bypasses_1_bits_uop_imm_packed, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_op1_sel, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_op2_sel, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_rob_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_1_bits_uop_ldq_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_1_bits_uop_stq_idx, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_rxq_idx, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_1_bits_uop_pdst, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_1_bits_uop_prs1, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_1_bits_uop_prs2, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_1_bits_uop_prs3, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_1_bits_uop_ppred, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_prs1_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_prs2_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_prs3_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_ppred_busy, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_1_bits_uop_stale_pdst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_exception, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_1_bits_uop_exc_cause, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_1_bits_uop_mem_cmd, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_mem_size, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_mem_signed, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_uses_ldq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_uses_stq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_unique, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_csr_cmd, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_ldst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_lrs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_lrs2, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_lrs3, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_dst_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_frs3_en, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fcn_dw, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_1_bits_uop_fcn_op, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_val, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_fp_rm, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_fp_typ, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_1_bits_data, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_predicated, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_valid, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_2_bits_uop_inst, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_2_bits_uop_debug_inst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_rvc, // @[execution-unit.scala:109:31] input [39:0] io_rrd_irf_bypasses_2_bits_uop_debug_pc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iq_type_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iq_type_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iq_type_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iq_type_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_4, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_5, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_6, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_7, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_8, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_9, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_issued, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31] input [11:0] io_rrd_irf_bypasses_2_bits_uop_br_mask, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_2_bits_uop_br_tag, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_2_bits_uop_br_type, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_sfb, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_fence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_fencei, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_sfence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_amo, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_eret, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_rocc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_mov, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_2_bits_uop_ftq_idx, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_edge_inst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_pc_lob, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_taken, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_imm_rename, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_imm_sel, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_2_bits_uop_pimm, // @[execution-unit.scala:109:31] input [19:0] io_rrd_irf_bypasses_2_bits_uop_imm_packed, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_op1_sel, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_op2_sel, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_rob_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_2_bits_uop_ldq_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_2_bits_uop_stq_idx, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_rxq_idx, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_2_bits_uop_pdst, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_2_bits_uop_prs1, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_2_bits_uop_prs2, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_2_bits_uop_prs3, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_2_bits_uop_ppred, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_prs1_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_prs2_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_prs3_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_ppred_busy, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_2_bits_uop_stale_pdst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_exception, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_2_bits_uop_exc_cause, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_2_bits_uop_mem_cmd, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_mem_size, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_mem_signed, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_uses_ldq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_uses_stq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_unique, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_csr_cmd, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_ldst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_lrs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_lrs2, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_lrs3, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_dst_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_frs3_en, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fcn_dw, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_2_bits_uop_fcn_op, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_val, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_fp_rm, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_fp_typ, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_2_bits_data, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_predicated, // @[execution-unit.scala:109:31] output io_arb_prf_req_valid, // @[execution-unit.scala:179:29] output [4:0] io_arb_prf_req_bits, // @[execution-unit.scala:179:29] input io_rrd_prf_resp, // @[execution-unit.scala:181:29] output io_arb_immrf_req_valid, // @[execution-unit.scala:151:31] output [4:0] io_arb_immrf_req_bits, // @[execution-unit.scala:151:31] input [63:0] io_rrd_immrf_resp, // @[execution-unit.scala:153:31] output io_rrd_immrf_wakeup_valid, // @[execution-unit.scala:154:31] output [31:0] io_rrd_immrf_wakeup_bits_uop_inst, // @[execution-unit.scala:154:31] output [31:0] io_rrd_immrf_wakeup_bits_uop_debug_inst, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_rvc, // @[execution-unit.scala:154:31] output [39:0] io_rrd_immrf_wakeup_bits_uop_debug_pc, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iq_type_0, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iq_type_1, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iq_type_2, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iq_type_3, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_0, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_1, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_2, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_3, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_4, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_5, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_6, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_7, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_8, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_9, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_issued, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_dis_col_sel, // @[execution-unit.scala:154:31] output [11:0] io_rrd_immrf_wakeup_bits_uop_br_mask, // @[execution-unit.scala:154:31] output [3:0] io_rrd_immrf_wakeup_bits_uop_br_tag, // @[execution-unit.scala:154:31] output [3:0] io_rrd_immrf_wakeup_bits_uop_br_type, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_sfb, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_fence, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_fencei, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_sfence, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_amo, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_eret, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_rocc, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_mov, // @[execution-unit.scala:154:31] output [4:0] io_rrd_immrf_wakeup_bits_uop_ftq_idx, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_edge_inst, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_pc_lob, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_taken, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_imm_rename, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_imm_sel, // @[execution-unit.scala:154:31] output [4:0] io_rrd_immrf_wakeup_bits_uop_pimm, // @[execution-unit.scala:154:31] output [19:0] io_rrd_immrf_wakeup_bits_uop_imm_packed, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_op1_sel, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_op2_sel, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_div, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_rob_idx, // @[execution-unit.scala:154:31] output [3:0] io_rrd_immrf_wakeup_bits_uop_ldq_idx, // @[execution-unit.scala:154:31] output [3:0] io_rrd_immrf_wakeup_bits_uop_stq_idx, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_rxq_idx, // @[execution-unit.scala:154:31] output [6:0] io_rrd_immrf_wakeup_bits_uop_pdst, // @[execution-unit.scala:154:31] output [6:0] io_rrd_immrf_wakeup_bits_uop_prs1, // @[execution-unit.scala:154:31] output [6:0] io_rrd_immrf_wakeup_bits_uop_prs2, // @[execution-unit.scala:154:31] output [6:0] io_rrd_immrf_wakeup_bits_uop_prs3, // @[execution-unit.scala:154:31] output [4:0] io_rrd_immrf_wakeup_bits_uop_ppred, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_prs1_busy, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_prs2_busy, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_prs3_busy, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_ppred_busy, // @[execution-unit.scala:154:31] output [6:0] io_rrd_immrf_wakeup_bits_uop_stale_pdst, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_exception, // @[execution-unit.scala:154:31] output [63:0] io_rrd_immrf_wakeup_bits_uop_exc_cause, // @[execution-unit.scala:154:31] output [4:0] io_rrd_immrf_wakeup_bits_uop_mem_cmd, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_mem_size, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_mem_signed, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_uses_ldq, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_uses_stq, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_unique, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_flush_on_commit, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_csr_cmd, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_ldst_is_rs1, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_ldst, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_lrs1, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_lrs2, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_lrs3, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_dst_rtype, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_lrs1_rtype, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_lrs2_rtype, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_frs3_en, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fcn_dw, // @[execution-unit.scala:154:31] output [4:0] io_rrd_immrf_wakeup_bits_uop_fcn_op, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_val, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_fp_rm, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_fp_typ, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_xcpt_pf_if, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_xcpt_ae_if, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_xcpt_ma_if, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_bp_debug_if, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_bp_xcpt_if, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_debug_fsrc, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_debug_tsrc, // @[execution-unit.scala:154:31] output io_arb_brf_req_valid, // @[execution-unit.scala:192:29] output [3:0] io_arb_brf_req_bits, // @[execution-unit.scala:192:29] input [3:0] io_rrd_brf_resp_ldq_idx, // @[execution-unit.scala:194:29] input [3:0] io_rrd_brf_resp_stq_idx, // @[execution-unit.scala:194:29] input [1:0] io_rrd_brf_resp_rxq_idx, // @[execution-unit.scala:194:29] input io_arb_ftq_reqs_0_ready, // @[execution-unit.scala:240:28] output io_arb_ftq_reqs_0_valid, // @[execution-unit.scala:240:28] output [4:0] io_arb_ftq_reqs_0_bits, // @[execution-unit.scala:240:28] input io_arb_ftq_reqs_1_ready, // @[execution-unit.scala:240:28] output io_arb_ftq_reqs_1_valid, // @[execution-unit.scala:240:28] output [4:0] io_arb_ftq_reqs_1_bits, // @[execution-unit.scala:240:28] input io_rrd_ftq_resps_0_valid, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_0_entry_cfi_idx_valid, // @[execution-unit.scala:241:28] input [1:0] io_rrd_ftq_resps_0_entry_cfi_idx_bits, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_0_entry_cfi_taken, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_0_entry_cfi_mispredicted, // @[execution-unit.scala:241:28] input [2:0] io_rrd_ftq_resps_0_entry_cfi_type, // @[execution-unit.scala:241:28] input [3:0] io_rrd_ftq_resps_0_entry_br_mask, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_0_entry_cfi_is_call, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_0_entry_cfi_is_ret, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_0_entry_cfi_npc_plus4, // @[execution-unit.scala:241:28] input [39:0] io_rrd_ftq_resps_0_entry_ras_top, // @[execution-unit.scala:241:28] input [4:0] io_rrd_ftq_resps_0_entry_ras_idx, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_0_entry_start_bank, // @[execution-unit.scala:241:28] input [39:0] io_rrd_ftq_resps_0_pc, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_valid, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_entry_cfi_idx_valid, // @[execution-unit.scala:241:28] input [1:0] io_rrd_ftq_resps_1_entry_cfi_idx_bits, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_entry_cfi_taken, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_entry_cfi_mispredicted, // @[execution-unit.scala:241:28] input [2:0] io_rrd_ftq_resps_1_entry_cfi_type, // @[execution-unit.scala:241:28] input [3:0] io_rrd_ftq_resps_1_entry_br_mask, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_entry_cfi_is_call, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_entry_cfi_is_ret, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_entry_cfi_npc_plus4, // @[execution-unit.scala:241:28] input [39:0] io_rrd_ftq_resps_1_entry_ras_top, // @[execution-unit.scala:241:28] input [4:0] io_rrd_ftq_resps_1_entry_ras_idx, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_entry_start_bank, // @[execution-unit.scala:241:28] input [39:0] io_rrd_ftq_resps_1_pc, // @[execution-unit.scala:241:28] output io_fast_wakeup_valid, // @[execution-unit.scala:503:26] output [31:0] io_fast_wakeup_bits_uop_inst, // @[execution-unit.scala:503:26] output [31:0] io_fast_wakeup_bits_uop_debug_inst, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_rvc, // @[execution-unit.scala:503:26] output [39:0] io_fast_wakeup_bits_uop_debug_pc, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iq_type_0, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iq_type_1, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iq_type_2, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iq_type_3, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_0, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_1, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_2, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_3, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_4, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_5, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_6, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_7, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_8, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_9, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iw_issued, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_dis_col_sel, // @[execution-unit.scala:503:26] output [11:0] io_fast_wakeup_bits_uop_br_mask, // @[execution-unit.scala:503:26] output [3:0] io_fast_wakeup_bits_uop_br_tag, // @[execution-unit.scala:503:26] output [3:0] io_fast_wakeup_bits_uop_br_type, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_sfb, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_fence, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_fencei, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_sfence, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_amo, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_eret, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_rocc, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_mov, // @[execution-unit.scala:503:26] output [4:0] io_fast_wakeup_bits_uop_ftq_idx, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_edge_inst, // @[execution-unit.scala:503:26] output [5:0] io_fast_wakeup_bits_uop_pc_lob, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_taken, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_imm_rename, // @[execution-unit.scala:503:26] output [2:0] io_fast_wakeup_bits_uop_imm_sel, // @[execution-unit.scala:503:26] output [4:0] io_fast_wakeup_bits_uop_pimm, // @[execution-unit.scala:503:26] output [19:0] io_fast_wakeup_bits_uop_imm_packed, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_op1_sel, // @[execution-unit.scala:503:26] output [2:0] io_fast_wakeup_bits_uop_op2_sel, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_div, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:503:26] output [5:0] io_fast_wakeup_bits_uop_rob_idx, // @[execution-unit.scala:503:26] output [3:0] io_fast_wakeup_bits_uop_ldq_idx, // @[execution-unit.scala:503:26] output [3:0] io_fast_wakeup_bits_uop_stq_idx, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_rxq_idx, // @[execution-unit.scala:503:26] output [6:0] io_fast_wakeup_bits_uop_pdst, // @[execution-unit.scala:503:26] output [6:0] io_fast_wakeup_bits_uop_prs1, // @[execution-unit.scala:503:26] output [6:0] io_fast_wakeup_bits_uop_prs2, // @[execution-unit.scala:503:26] output [6:0] io_fast_wakeup_bits_uop_prs3, // @[execution-unit.scala:503:26] output [4:0] io_fast_wakeup_bits_uop_ppred, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_prs1_busy, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_prs2_busy, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_prs3_busy, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_ppred_busy, // @[execution-unit.scala:503:26] output [6:0] io_fast_wakeup_bits_uop_stale_pdst, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_exception, // @[execution-unit.scala:503:26] output [63:0] io_fast_wakeup_bits_uop_exc_cause, // @[execution-unit.scala:503:26] output [4:0] io_fast_wakeup_bits_uop_mem_cmd, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_mem_size, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_mem_signed, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_uses_ldq, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_uses_stq, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_unique, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_flush_on_commit, // @[execution-unit.scala:503:26] output [2:0] io_fast_wakeup_bits_uop_csr_cmd, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_ldst_is_rs1, // @[execution-unit.scala:503:26] output [5:0] io_fast_wakeup_bits_uop_ldst, // @[execution-unit.scala:503:26] output [5:0] io_fast_wakeup_bits_uop_lrs1, // @[execution-unit.scala:503:26] output [5:0] io_fast_wakeup_bits_uop_lrs2, // @[execution-unit.scala:503:26] output [5:0] io_fast_wakeup_bits_uop_lrs3, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_dst_rtype, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_lrs1_rtype, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_lrs2_rtype, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_frs3_en, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fcn_dw, // @[execution-unit.scala:503:26] output [4:0] io_fast_wakeup_bits_uop_fcn_op, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_val, // @[execution-unit.scala:503:26] output [2:0] io_fast_wakeup_bits_uop_fp_rm, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_fp_typ, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_xcpt_pf_if, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_xcpt_ae_if, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_xcpt_ma_if, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_bp_debug_if, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_bp_xcpt_if, // @[execution-unit.scala:503:26] output [2:0] io_fast_wakeup_bits_uop_debug_fsrc, // @[execution-unit.scala:503:26] output [2:0] io_fast_wakeup_bits_uop_debug_tsrc, // @[execution-unit.scala:503:26] output io_fast_pred_wakeup_valid, // @[execution-unit.scala:513:31] output [31:0] io_fast_pred_wakeup_bits_uop_inst, // @[execution-unit.scala:513:31] output [31:0] io_fast_pred_wakeup_bits_uop_debug_inst, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_rvc, // @[execution-unit.scala:513:31] output [39:0] io_fast_pred_wakeup_bits_uop_debug_pc, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iq_type_0, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iq_type_1, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iq_type_2, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iq_type_3, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_0, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_1, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_2, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_3, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_4, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_5, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_6, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_7, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_8, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_9, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iw_issued, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_dis_col_sel, // @[execution-unit.scala:513:31] output [11:0] io_fast_pred_wakeup_bits_uop_br_mask, // @[execution-unit.scala:513:31] output [3:0] io_fast_pred_wakeup_bits_uop_br_tag, // @[execution-unit.scala:513:31] output [3:0] io_fast_pred_wakeup_bits_uop_br_type, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_sfb, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_fence, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_fencei, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_sfence, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_amo, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_eret, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_rocc, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_mov, // @[execution-unit.scala:513:31] output [4:0] io_fast_pred_wakeup_bits_uop_ftq_idx, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_edge_inst, // @[execution-unit.scala:513:31] output [5:0] io_fast_pred_wakeup_bits_uop_pc_lob, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_taken, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_imm_rename, // @[execution-unit.scala:513:31] output [2:0] io_fast_pred_wakeup_bits_uop_imm_sel, // @[execution-unit.scala:513:31] output [4:0] io_fast_pred_wakeup_bits_uop_pimm, // @[execution-unit.scala:513:31] output [19:0] io_fast_pred_wakeup_bits_uop_imm_packed, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_op1_sel, // @[execution-unit.scala:513:31] output [2:0] io_fast_pred_wakeup_bits_uop_op2_sel, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_div, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:513:31] output [5:0] io_fast_pred_wakeup_bits_uop_rob_idx, // @[execution-unit.scala:513:31] output [3:0] io_fast_pred_wakeup_bits_uop_ldq_idx, // @[execution-unit.scala:513:31] output [3:0] io_fast_pred_wakeup_bits_uop_stq_idx, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_rxq_idx, // @[execution-unit.scala:513:31] output [6:0] io_fast_pred_wakeup_bits_uop_pdst, // @[execution-unit.scala:513:31] output [6:0] io_fast_pred_wakeup_bits_uop_prs1, // @[execution-unit.scala:513:31] output [6:0] io_fast_pred_wakeup_bits_uop_prs2, // @[execution-unit.scala:513:31] output [6:0] io_fast_pred_wakeup_bits_uop_prs3, // @[execution-unit.scala:513:31] output [4:0] io_fast_pred_wakeup_bits_uop_ppred, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_prs1_busy, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_prs2_busy, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_prs3_busy, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_ppred_busy, // @[execution-unit.scala:513:31] output [6:0] io_fast_pred_wakeup_bits_uop_stale_pdst, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_exception, // @[execution-unit.scala:513:31] output [63:0] io_fast_pred_wakeup_bits_uop_exc_cause, // @[execution-unit.scala:513:31] output [4:0] io_fast_pred_wakeup_bits_uop_mem_cmd, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_mem_size, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_mem_signed, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_uses_ldq, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_uses_stq, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_unique, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_flush_on_commit, // @[execution-unit.scala:513:31] output [2:0] io_fast_pred_wakeup_bits_uop_csr_cmd, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_ldst_is_rs1, // @[execution-unit.scala:513:31] output [5:0] io_fast_pred_wakeup_bits_uop_ldst, // @[execution-unit.scala:513:31] output [5:0] io_fast_pred_wakeup_bits_uop_lrs1, // @[execution-unit.scala:513:31] output [5:0] io_fast_pred_wakeup_bits_uop_lrs2, // @[execution-unit.scala:513:31] output [5:0] io_fast_pred_wakeup_bits_uop_lrs3, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_dst_rtype, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_lrs1_rtype, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_lrs2_rtype, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_frs3_en, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fcn_dw, // @[execution-unit.scala:513:31] output [4:0] io_fast_pred_wakeup_bits_uop_fcn_op, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_val, // @[execution-unit.scala:513:31] output [2:0] io_fast_pred_wakeup_bits_uop_fp_rm, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_fp_typ, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_xcpt_pf_if, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_xcpt_ae_if, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_xcpt_ma_if, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_bp_debug_if, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_bp_xcpt_if, // @[execution-unit.scala:513:31] output [2:0] io_fast_pred_wakeup_bits_uop_debug_fsrc, // @[execution-unit.scala:513:31] output [2:0] io_fast_pred_wakeup_bits_uop_debug_tsrc, // @[execution-unit.scala:513:31] output io_squash_iss, // @[execution-unit.scala:521:25] output [1:0] io_child_rebusy, // @[execution-unit.scala:528:27] output io_alu_resp_valid, // @[execution-unit.scala:565:23] output [31:0] io_alu_resp_bits_uop_inst, // @[execution-unit.scala:565:23] output [31:0] io_alu_resp_bits_uop_debug_inst, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_rvc, // @[execution-unit.scala:565:23] output [39:0] io_alu_resp_bits_uop_debug_pc, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iq_type_0, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iq_type_1, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iq_type_2, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iq_type_3, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_0, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_1, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_2, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_3, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_4, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_5, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_6, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_7, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_8, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_9, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iw_issued, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_dis_col_sel, // @[execution-unit.scala:565:23] output [11:0] io_alu_resp_bits_uop_br_mask, // @[execution-unit.scala:565:23] output [3:0] io_alu_resp_bits_uop_br_tag, // @[execution-unit.scala:565:23] output [3:0] io_alu_resp_bits_uop_br_type, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_sfb, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_fence, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_fencei, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_sfence, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_amo, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_eret, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_rocc, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_mov, // @[execution-unit.scala:565:23] output [4:0] io_alu_resp_bits_uop_ftq_idx, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_edge_inst, // @[execution-unit.scala:565:23] output [5:0] io_alu_resp_bits_uop_pc_lob, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_taken, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_imm_rename, // @[execution-unit.scala:565:23] output [2:0] io_alu_resp_bits_uop_imm_sel, // @[execution-unit.scala:565:23] output [4:0] io_alu_resp_bits_uop_pimm, // @[execution-unit.scala:565:23] output [19:0] io_alu_resp_bits_uop_imm_packed, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_op1_sel, // @[execution-unit.scala:565:23] output [2:0] io_alu_resp_bits_uop_op2_sel, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_div, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:565:23] output [5:0] io_alu_resp_bits_uop_rob_idx, // @[execution-unit.scala:565:23] output [3:0] io_alu_resp_bits_uop_ldq_idx, // @[execution-unit.scala:565:23] output [3:0] io_alu_resp_bits_uop_stq_idx, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_rxq_idx, // @[execution-unit.scala:565:23] output [6:0] io_alu_resp_bits_uop_pdst, // @[execution-unit.scala:565:23] output [6:0] io_alu_resp_bits_uop_prs1, // @[execution-unit.scala:565:23] output [6:0] io_alu_resp_bits_uop_prs2, // @[execution-unit.scala:565:23] output [6:0] io_alu_resp_bits_uop_prs3, // @[execution-unit.scala:565:23] output [4:0] io_alu_resp_bits_uop_ppred, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_prs1_busy, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_prs2_busy, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_prs3_busy, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_ppred_busy, // @[execution-unit.scala:565:23] output [6:0] io_alu_resp_bits_uop_stale_pdst, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_exception, // @[execution-unit.scala:565:23] output [63:0] io_alu_resp_bits_uop_exc_cause, // @[execution-unit.scala:565:23] output [4:0] io_alu_resp_bits_uop_mem_cmd, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_mem_size, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_mem_signed, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_uses_ldq, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_uses_stq, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_unique, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_flush_on_commit, // @[execution-unit.scala:565:23] output [2:0] io_alu_resp_bits_uop_csr_cmd, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:565:23] output [5:0] io_alu_resp_bits_uop_ldst, // @[execution-unit.scala:565:23] output [5:0] io_alu_resp_bits_uop_lrs1, // @[execution-unit.scala:565:23] output [5:0] io_alu_resp_bits_uop_lrs2, // @[execution-unit.scala:565:23] output [5:0] io_alu_resp_bits_uop_lrs3, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_dst_rtype, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_lrs1_rtype, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_lrs2_rtype, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_frs3_en, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fcn_dw, // @[execution-unit.scala:565:23] output [4:0] io_alu_resp_bits_uop_fcn_op, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_val, // @[execution-unit.scala:565:23] output [2:0] io_alu_resp_bits_uop_fp_rm, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_fp_typ, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_bp_debug_if, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:565:23] output [2:0] io_alu_resp_bits_uop_debug_fsrc, // @[execution-unit.scala:565:23] output [2:0] io_alu_resp_bits_uop_debug_tsrc, // @[execution-unit.scala:565:23] output [63:0] io_alu_resp_bits_data, // @[execution-unit.scala:565:23] output io_alu_resp_bits_predicated, // @[execution-unit.scala:565:23] output io_brinfo_valid, // @[execution-unit.scala:569:21] output [31:0] io_brinfo_bits_uop_inst, // @[execution-unit.scala:569:21] output [31:0] io_brinfo_bits_uop_debug_inst, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_rvc, // @[execution-unit.scala:569:21] output [39:0] io_brinfo_bits_uop_debug_pc, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iq_type_0, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iq_type_1, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iq_type_2, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iq_type_3, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_0, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_1, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_2, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_3, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_4, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_5, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_6, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_7, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_8, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_9, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iw_issued, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_dis_col_sel, // @[execution-unit.scala:569:21] output [11:0] io_brinfo_bits_uop_br_mask, // @[execution-unit.scala:569:21] output [3:0] io_brinfo_bits_uop_br_tag, // @[execution-unit.scala:569:21] output [3:0] io_brinfo_bits_uop_br_type, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_sfb, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_fence, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_fencei, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_sfence, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_amo, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_eret, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_rocc, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_mov, // @[execution-unit.scala:569:21] output [4:0] io_brinfo_bits_uop_ftq_idx, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_edge_inst, // @[execution-unit.scala:569:21] output [5:0] io_brinfo_bits_uop_pc_lob, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_taken, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_imm_rename, // @[execution-unit.scala:569:21] output [2:0] io_brinfo_bits_uop_imm_sel, // @[execution-unit.scala:569:21] output [4:0] io_brinfo_bits_uop_pimm, // @[execution-unit.scala:569:21] output [19:0] io_brinfo_bits_uop_imm_packed, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_op1_sel, // @[execution-unit.scala:569:21] output [2:0] io_brinfo_bits_uop_op2_sel, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_div, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:569:21] output [5:0] io_brinfo_bits_uop_rob_idx, // @[execution-unit.scala:569:21] output [3:0] io_brinfo_bits_uop_ldq_idx, // @[execution-unit.scala:569:21] output [3:0] io_brinfo_bits_uop_stq_idx, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_rxq_idx, // @[execution-unit.scala:569:21] output [6:0] io_brinfo_bits_uop_pdst, // @[execution-unit.scala:569:21] output [6:0] io_brinfo_bits_uop_prs1, // @[execution-unit.scala:569:21] output [6:0] io_brinfo_bits_uop_prs2, // @[execution-unit.scala:569:21] output [6:0] io_brinfo_bits_uop_prs3, // @[execution-unit.scala:569:21] output [4:0] io_brinfo_bits_uop_ppred, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_prs1_busy, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_prs2_busy, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_prs3_busy, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_ppred_busy, // @[execution-unit.scala:569:21] output [6:0] io_brinfo_bits_uop_stale_pdst, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_exception, // @[execution-unit.scala:569:21] output [63:0] io_brinfo_bits_uop_exc_cause, // @[execution-unit.scala:569:21] output [4:0] io_brinfo_bits_uop_mem_cmd, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_mem_size, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_mem_signed, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_uses_ldq, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_uses_stq, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_unique, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_flush_on_commit, // @[execution-unit.scala:569:21] output [2:0] io_brinfo_bits_uop_csr_cmd, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_ldst_is_rs1, // @[execution-unit.scala:569:21] output [5:0] io_brinfo_bits_uop_ldst, // @[execution-unit.scala:569:21] output [5:0] io_brinfo_bits_uop_lrs1, // @[execution-unit.scala:569:21] output [5:0] io_brinfo_bits_uop_lrs2, // @[execution-unit.scala:569:21] output [5:0] io_brinfo_bits_uop_lrs3, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_dst_rtype, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_lrs1_rtype, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_lrs2_rtype, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_frs3_en, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fcn_dw, // @[execution-unit.scala:569:21] output [4:0] io_brinfo_bits_uop_fcn_op, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_val, // @[execution-unit.scala:569:21] output [2:0] io_brinfo_bits_uop_fp_rm, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_fp_typ, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_xcpt_pf_if, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_xcpt_ae_if, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_xcpt_ma_if, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_bp_debug_if, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_bp_xcpt_if, // @[execution-unit.scala:569:21] output [2:0] io_brinfo_bits_uop_debug_fsrc, // @[execution-unit.scala:569:21] output [2:0] io_brinfo_bits_uop_debug_tsrc, // @[execution-unit.scala:569:21] output io_brinfo_bits_mispredict, // @[execution-unit.scala:569:21] output io_brinfo_bits_taken, // @[execution-unit.scala:569:21] output [2:0] io_brinfo_bits_cfi_type, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_pc_sel, // @[execution-unit.scala:569:21] output [39:0] io_brinfo_bits_jalr_target, // @[execution-unit.scala:569:21] output [20:0] io_brinfo_bits_target_offset // @[execution-unit.scala:569:21] ); wire [1:0] _io_child_rebusy_output; // @[execution-unit.scala:529:19, :530:40, :531:21] reg [2:0] rrd_uop_bits_debug_tsrc; // @[execution-unit.scala:95:20] reg [2:0] rrd_uop_bits_debug_fsrc; // @[execution-unit.scala:95:20] reg rrd_uop_bits_bp_xcpt_if; // @[execution-unit.scala:95:20] reg rrd_uop_bits_bp_debug_if; // @[execution-unit.scala:95:20] reg rrd_uop_bits_xcpt_ma_if; // @[execution-unit.scala:95:20] reg rrd_uop_bits_xcpt_ae_if; // @[execution-unit.scala:95:20] reg rrd_uop_bits_xcpt_pf_if; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_fp_typ; // @[execution-unit.scala:95:20] reg [2:0] rrd_uop_bits_fp_rm; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_val; // @[execution-unit.scala:95:20] reg [4:0] rrd_uop_bits_fcn_op; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fcn_dw; // @[execution-unit.scala:95:20] reg rrd_uop_bits_frs3_en; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_lrs2_rtype; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_lrs1_rtype; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_dst_rtype; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_lrs3; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_lrs2; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_lrs1; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_ldst; // @[execution-unit.scala:95:20] reg rrd_uop_bits_ldst_is_rs1; // @[execution-unit.scala:95:20] reg [2:0] rrd_uop_bits_csr_cmd; // @[execution-unit.scala:95:20] reg rrd_uop_bits_flush_on_commit; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_unique; // @[execution-unit.scala:95:20] reg rrd_uop_bits_uses_stq; // @[execution-unit.scala:95:20] reg rrd_uop_bits_uses_ldq; // @[execution-unit.scala:95:20] reg rrd_uop_bits_mem_signed; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_mem_size; // @[execution-unit.scala:95:20] reg [4:0] rrd_uop_bits_mem_cmd; // @[execution-unit.scala:95:20] reg [63:0] rrd_uop_bits_exc_cause; // @[execution-unit.scala:95:20] reg rrd_uop_bits_exception; // @[execution-unit.scala:95:20] reg [6:0] rrd_uop_bits_stale_pdst; // @[execution-unit.scala:95:20] reg rrd_uop_bits_ppred_busy; // @[execution-unit.scala:95:20] reg rrd_uop_bits_prs3_busy; // @[execution-unit.scala:95:20] reg rrd_uop_bits_prs2_busy; // @[execution-unit.scala:95:20] reg rrd_uop_bits_prs1_busy; // @[execution-unit.scala:95:20] reg [4:0] rrd_uop_bits_ppred; // @[execution-unit.scala:95:20] reg [6:0] rrd_uop_bits_prs3; // @[execution-unit.scala:95:20] reg [6:0] rrd_uop_bits_prs2; // @[execution-unit.scala:95:20] reg [6:0] rrd_uop_bits_prs1; // @[execution-unit.scala:95:20] reg [6:0] rrd_uop_bits_pdst; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_rxq_idx; // @[execution-unit.scala:95:20] reg [3:0] rrd_uop_bits_stq_idx; // @[execution-unit.scala:95:20] reg [3:0] rrd_uop_bits_ldq_idx; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_rob_idx; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_div; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:95:20] reg [2:0] rrd_uop_bits_op2_sel; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_op1_sel; // @[execution-unit.scala:95:20] reg [19:0] rrd_uop_bits_imm_packed; // @[execution-unit.scala:95:20] reg [4:0] rrd_uop_bits_pimm; // @[execution-unit.scala:95:20] reg [2:0] rrd_uop_bits_imm_sel; // @[execution-unit.scala:95:20] reg rrd_uop_bits_imm_rename; // @[execution-unit.scala:95:20] reg rrd_uop_bits_taken; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_pc_lob; // @[execution-unit.scala:95:20] reg rrd_uop_bits_edge_inst; // @[execution-unit.scala:95:20] reg [4:0] rrd_uop_bits_ftq_idx; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_mov; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_rocc; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_eret; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_amo; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_sfence; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_fencei; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_fence; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_sfb; // @[execution-unit.scala:95:20] reg [3:0] rrd_uop_bits_br_type; // @[execution-unit.scala:95:20] reg [3:0] rrd_uop_bits_br_tag; // @[execution-unit.scala:95:20] reg [11:0] rrd_uop_bits_br_mask; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_dis_col_sel; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_issued; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_9; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_8; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_7; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_6; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_5; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_4; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_3; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_2; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_1; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_0; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iq_type_3; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iq_type_2; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iq_type_1; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iq_type_0; // @[execution-unit.scala:95:20] reg [39:0] rrd_uop_bits_debug_pc; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_rvc; // @[execution-unit.scala:95:20] reg [31:0] rrd_uop_bits_debug_inst; // @[execution-unit.scala:95:20] reg [31:0] rrd_uop_bits_inst; // @[execution-unit.scala:95:20] wire _alu_io_resp_valid; // @[execution-unit.scala:558:19] wire [31:0] _alu_io_resp_bits_uop_inst; // @[execution-unit.scala:558:19] wire [31:0] _alu_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:558:19] wire [39:0] _alu_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iq_type_0; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iq_type_1; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iq_type_2; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iq_type_3; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_0; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_1; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_2; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_3; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_4; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_5; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_6; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_7; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_8; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_9; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iw_issued; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iw_issued_partial_agen; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iw_issued_partial_dgen; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_iw_p1_speculative_child; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_iw_p2_speculative_child; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iw_p1_bypass_hint; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iw_p2_bypass_hint; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iw_p3_bypass_hint; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_dis_col_sel; // @[execution-unit.scala:558:19] wire [11:0] _alu_io_resp_bits_uop_br_mask; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_resp_bits_uop_br_tag; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_resp_bits_uop_br_type; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_fence; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_sfence; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_amo; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_eret; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_rocc; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_mov; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_taken; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_imm_rename; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_resp_bits_uop_imm_sel; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_resp_bits_uop_pimm; // @[execution-unit.scala:558:19] wire [19:0] _alu_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_op1_sel; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_resp_bits_uop_op2_sel; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_ldst; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_wen; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_ren1; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_ren2; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_ren3; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_swap12; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_swap23; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_fromint; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_toint; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_fastpipe; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_fma; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_div; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_sqrt; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_wflags; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_vec; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_resp_bits_uop_pdst; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_resp_bits_uop_prs1; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_resp_bits_uop_prs2; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_resp_bits_uop_prs3; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_resp_bits_uop_ppred; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_exception; // @[execution-unit.scala:558:19] wire [63:0] _alu_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_mem_size; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_unique; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_resp_bits_uop_csr_cmd; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_resp_bits_uop_ldst; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_resp_bits_uop_lrs1; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_resp_bits_uop_lrs2; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_resp_bits_uop_lrs3; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fcn_dw; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_resp_bits_uop_fcn_op; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_val; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_resp_bits_uop_fp_rm; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_fp_typ; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:558:19] wire [63:0] _alu_io_resp_bits_data; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_predicated; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_valid; // @[execution-unit.scala:558:19] wire [31:0] _alu_io_brinfo_bits_uop_inst; // @[execution-unit.scala:558:19] wire [31:0] _alu_io_brinfo_bits_uop_debug_inst; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_rvc; // @[execution-unit.scala:558:19] wire [39:0] _alu_io_brinfo_bits_uop_debug_pc; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iq_type_0; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iq_type_1; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iq_type_2; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iq_type_3; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_0; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_1; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_2; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_3; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_4; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_5; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_6; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_7; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_8; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_9; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iw_issued; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iw_issued_partial_agen; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iw_issued_partial_dgen; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_iw_p1_speculative_child; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_iw_p2_speculative_child; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iw_p1_bypass_hint; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iw_p2_bypass_hint; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iw_p3_bypass_hint; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_dis_col_sel; // @[execution-unit.scala:558:19] wire [11:0] _alu_io_brinfo_bits_uop_br_mask; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_brinfo_bits_uop_br_tag; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_brinfo_bits_uop_br_type; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_sfb; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_fence; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_fencei; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_sfence; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_amo; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_eret; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_rocc; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_mov; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_brinfo_bits_uop_ftq_idx; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_edge_inst; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_brinfo_bits_uop_pc_lob; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_taken; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_imm_rename; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_brinfo_bits_uop_imm_sel; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_brinfo_bits_uop_pimm; // @[execution-unit.scala:558:19] wire [19:0] _alu_io_brinfo_bits_uop_imm_packed; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_op1_sel; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_brinfo_bits_uop_op2_sel; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_ldst; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_wen; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_ren1; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_ren2; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_ren3; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_swap12; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_swap23; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_fp_ctrl_typeTagIn; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_fp_ctrl_typeTagOut; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_fromint; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_toint; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_fastpipe; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_fma; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_div; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_sqrt; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_wflags; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_vec; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_brinfo_bits_uop_rob_idx; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_brinfo_bits_uop_ldq_idx; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_brinfo_bits_uop_stq_idx; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_rxq_idx; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_brinfo_bits_uop_pdst; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_brinfo_bits_uop_prs1; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_brinfo_bits_uop_prs2; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_brinfo_bits_uop_prs3; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_brinfo_bits_uop_ppred; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_prs1_busy; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_prs2_busy; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_prs3_busy; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_ppred_busy; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_brinfo_bits_uop_stale_pdst; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_exception; // @[execution-unit.scala:558:19] wire [63:0] _alu_io_brinfo_bits_uop_exc_cause; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_brinfo_bits_uop_mem_cmd; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_mem_size; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_mem_signed; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_uses_ldq; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_uses_stq; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_unique; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_flush_on_commit; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_brinfo_bits_uop_csr_cmd; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_ldst_is_rs1; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_brinfo_bits_uop_ldst; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_brinfo_bits_uop_lrs1; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_brinfo_bits_uop_lrs2; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_brinfo_bits_uop_lrs3; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_dst_rtype; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_lrs1_rtype; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_lrs2_rtype; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_frs3_en; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fcn_dw; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_brinfo_bits_uop_fcn_op; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_val; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_brinfo_bits_uop_fp_rm; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_fp_typ; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_xcpt_pf_if; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_xcpt_ae_if; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_xcpt_ma_if; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_bp_debug_if; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_bp_xcpt_if; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_brinfo_bits_uop_debug_fsrc; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_brinfo_bits_uop_debug_tsrc; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_mispredict; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_taken; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_brinfo_bits_cfi_type; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_pc_sel; // @[execution-unit.scala:558:19] wire [39:0] _alu_io_brinfo_bits_jalr_target; // @[execution-unit.scala:558:19] wire [20:0] _alu_io_brinfo_bits_target_offset; // @[execution-unit.scala:558:19] wire io_arb_irf_reqs_0_ready_0 = io_arb_irf_reqs_0_ready; // @[execution-unit.scala:492:7] wire io_arb_irf_reqs_1_ready_0 = io_arb_irf_reqs_1_ready; // @[execution-unit.scala:492:7] wire io_arb_ftq_reqs_0_ready_0 = io_arb_ftq_reqs_0_ready; // @[execution-unit.scala:492:7] wire io_arb_ftq_reqs_1_ready_0 = io_arb_ftq_reqs_1_ready; // @[execution-unit.scala:492:7] wire [31:0] arb_uop_bits_out_inst = io_iss_uop_bits_inst; // @[util.scala:104:23] wire [31:0] arb_uop_bits_out_debug_inst = io_iss_uop_bits_debug_inst; // @[util.scala:104:23] wire arb_uop_bits_out_is_rvc = io_iss_uop_bits_is_rvc; // @[util.scala:104:23] wire [39:0] arb_uop_bits_out_debug_pc = io_iss_uop_bits_debug_pc; // @[util.scala:104:23] wire arb_uop_bits_out_iq_type_0 = io_iss_uop_bits_iq_type_0; // @[util.scala:104:23] wire arb_uop_bits_out_iq_type_1 = io_iss_uop_bits_iq_type_1; // @[util.scala:104:23] wire arb_uop_bits_out_iq_type_2 = io_iss_uop_bits_iq_type_2; // @[util.scala:104:23] wire arb_uop_bits_out_iq_type_3 = io_iss_uop_bits_iq_type_3; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_0 = io_iss_uop_bits_fu_code_0; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_1 = io_iss_uop_bits_fu_code_1; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_2 = io_iss_uop_bits_fu_code_2; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_3 = io_iss_uop_bits_fu_code_3; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_4 = io_iss_uop_bits_fu_code_4; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_5 = io_iss_uop_bits_fu_code_5; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_6 = io_iss_uop_bits_fu_code_6; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_7 = io_iss_uop_bits_fu_code_7; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_8 = io_iss_uop_bits_fu_code_8; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_9 = io_iss_uop_bits_fu_code_9; // @[util.scala:104:23] wire arb_uop_bits_out_iw_issued = io_iss_uop_bits_iw_issued; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_iw_p1_speculative_child = io_iss_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_iw_p2_speculative_child = io_iss_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire arb_uop_bits_out_iw_p1_bypass_hint = io_iss_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire arb_uop_bits_out_iw_p2_bypass_hint = io_iss_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire arb_uop_bits_out_iw_p3_bypass_hint = io_iss_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_dis_col_sel = io_iss_uop_bits_dis_col_sel; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_br_tag = io_iss_uop_bits_br_tag; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_br_type = io_iss_uop_bits_br_type; // @[util.scala:104:23] wire arb_uop_bits_out_is_sfb = io_iss_uop_bits_is_sfb; // @[util.scala:104:23] wire arb_uop_bits_out_is_fence = io_iss_uop_bits_is_fence; // @[util.scala:104:23] wire arb_uop_bits_out_is_fencei = io_iss_uop_bits_is_fencei; // @[util.scala:104:23] wire arb_uop_bits_out_is_sfence = io_iss_uop_bits_is_sfence; // @[util.scala:104:23] wire arb_uop_bits_out_is_amo = io_iss_uop_bits_is_amo; // @[util.scala:104:23] wire arb_uop_bits_out_is_eret = io_iss_uop_bits_is_eret; // @[util.scala:104:23] wire arb_uop_bits_out_is_sys_pc2epc = io_iss_uop_bits_is_sys_pc2epc; // @[util.scala:104:23] wire arb_uop_bits_out_is_rocc = io_iss_uop_bits_is_rocc; // @[util.scala:104:23] wire arb_uop_bits_out_is_mov = io_iss_uop_bits_is_mov; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_ftq_idx = io_iss_uop_bits_ftq_idx; // @[util.scala:104:23] wire arb_uop_bits_out_edge_inst = io_iss_uop_bits_edge_inst; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_pc_lob = io_iss_uop_bits_pc_lob; // @[util.scala:104:23] wire arb_uop_bits_out_taken = io_iss_uop_bits_taken; // @[util.scala:104:23] wire arb_uop_bits_out_imm_rename = io_iss_uop_bits_imm_rename; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_imm_sel = io_iss_uop_bits_imm_sel; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_pimm = io_iss_uop_bits_pimm; // @[util.scala:104:23] wire [19:0] arb_uop_bits_out_imm_packed = io_iss_uop_bits_imm_packed; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_op1_sel = io_iss_uop_bits_op1_sel; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_op2_sel = io_iss_uop_bits_op2_sel; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_ldst = io_iss_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_wen = io_iss_uop_bits_fp_ctrl_wen; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_ren1 = io_iss_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_ren2 = io_iss_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_ren3 = io_iss_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_swap12 = io_iss_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_swap23 = io_iss_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_fp_ctrl_typeTagIn = io_iss_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_fp_ctrl_typeTagOut = io_iss_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_fromint = io_iss_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_toint = io_iss_uop_bits_fp_ctrl_toint; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_fastpipe = io_iss_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_fma = io_iss_uop_bits_fp_ctrl_fma; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_div = io_iss_uop_bits_fp_ctrl_div; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_sqrt = io_iss_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_wflags = io_iss_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_vec = io_iss_uop_bits_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_rob_idx = io_iss_uop_bits_rob_idx; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_ldq_idx = io_iss_uop_bits_ldq_idx; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_stq_idx = io_iss_uop_bits_stq_idx; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_rxq_idx = io_iss_uop_bits_rxq_idx; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_pdst = io_iss_uop_bits_pdst; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_prs1 = io_iss_uop_bits_prs1; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_prs2 = io_iss_uop_bits_prs2; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_prs3 = io_iss_uop_bits_prs3; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_ppred = io_iss_uop_bits_ppred; // @[util.scala:104:23] wire arb_uop_bits_out_prs1_busy = io_iss_uop_bits_prs1_busy; // @[util.scala:104:23] wire arb_uop_bits_out_prs2_busy = io_iss_uop_bits_prs2_busy; // @[util.scala:104:23] wire arb_uop_bits_out_prs3_busy = io_iss_uop_bits_prs3_busy; // @[util.scala:104:23] wire arb_uop_bits_out_ppred_busy = io_iss_uop_bits_ppred_busy; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_stale_pdst = io_iss_uop_bits_stale_pdst; // @[util.scala:104:23] wire arb_uop_bits_out_exception = io_iss_uop_bits_exception; // @[util.scala:104:23] wire [63:0] arb_uop_bits_out_exc_cause = io_iss_uop_bits_exc_cause; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_mem_cmd = io_iss_uop_bits_mem_cmd; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_mem_size = io_iss_uop_bits_mem_size; // @[util.scala:104:23] wire arb_uop_bits_out_mem_signed = io_iss_uop_bits_mem_signed; // @[util.scala:104:23] wire arb_uop_bits_out_uses_ldq = io_iss_uop_bits_uses_ldq; // @[util.scala:104:23] wire arb_uop_bits_out_uses_stq = io_iss_uop_bits_uses_stq; // @[util.scala:104:23] wire arb_uop_bits_out_is_unique = io_iss_uop_bits_is_unique; // @[util.scala:104:23] wire arb_uop_bits_out_flush_on_commit = io_iss_uop_bits_flush_on_commit; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_csr_cmd = io_iss_uop_bits_csr_cmd; // @[util.scala:104:23] wire arb_uop_bits_out_ldst_is_rs1 = io_iss_uop_bits_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_ldst = io_iss_uop_bits_ldst; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_lrs1 = io_iss_uop_bits_lrs1; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_lrs2 = io_iss_uop_bits_lrs2; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_lrs3 = io_iss_uop_bits_lrs3; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_dst_rtype = io_iss_uop_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_lrs1_rtype = io_iss_uop_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_lrs2_rtype = io_iss_uop_bits_lrs2_rtype; // @[util.scala:104:23] wire arb_uop_bits_out_frs3_en = io_iss_uop_bits_frs3_en; // @[util.scala:104:23] wire arb_uop_bits_out_fcn_dw = io_iss_uop_bits_fcn_dw; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_fcn_op = io_iss_uop_bits_fcn_op; // @[util.scala:104:23] wire arb_uop_bits_out_fp_val = io_iss_uop_bits_fp_val; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_fp_rm = io_iss_uop_bits_fp_rm; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_fp_typ = io_iss_uop_bits_fp_typ; // @[util.scala:104:23] wire arb_uop_bits_out_xcpt_pf_if = io_iss_uop_bits_xcpt_pf_if; // @[util.scala:104:23] wire arb_uop_bits_out_xcpt_ae_if = io_iss_uop_bits_xcpt_ae_if; // @[util.scala:104:23] wire arb_uop_bits_out_xcpt_ma_if = io_iss_uop_bits_xcpt_ma_if; // @[util.scala:104:23] wire arb_uop_bits_out_bp_debug_if = io_iss_uop_bits_bp_debug_if; // @[util.scala:104:23] wire arb_uop_bits_out_bp_xcpt_if = io_iss_uop_bits_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_debug_fsrc = io_iss_uop_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_debug_tsrc = io_iss_uop_bits_debug_tsrc; // @[util.scala:104:23] wire arb_uop_bits_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire arb_uop_bits_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire exe_int_req_ftq_info_0_ghist_current_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:547:25] wire exe_int_req_ftq_info_0_ghist_new_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:547:25] wire exe_int_req_ftq_info_0_ghist_new_saw_branch_taken = 1'h0; // @[execution-unit.scala:547:25] wire exe_int_req_ftq_info_1_ghist_current_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:547:25] wire exe_int_req_ftq_info_1_ghist_new_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:547:25] wire exe_int_req_ftq_info_1_ghist_new_saw_branch_taken = 1'h0; // @[execution-unit.scala:547:25] wire _r_WIRE_0 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_1 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_2 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_3 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_4 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_5 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_6 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_7 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_8 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_9 = 1'h0; // @[execution-unit.scala:74:29] wire r_1 = 1'h0; // @[execution-unit.scala:74:21] wire r_2 = 1'h0; // @[execution-unit.scala:74:21] wire r_3 = 1'h0; // @[execution-unit.scala:74:21] wire r_4 = 1'h0; // @[execution-unit.scala:74:21] wire r_5 = 1'h0; // @[execution-unit.scala:74:21] wire r_6 = 1'h0; // @[execution-unit.scala:74:21] wire r_7 = 1'h0; // @[execution-unit.scala:74:21] wire r_8 = 1'h0; // @[execution-unit.scala:74:21] wire r_9 = 1'h0; // @[execution-unit.scala:74:21] wire [4:0] exe_int_req_ftq_info_0_ghist_ras_idx = 5'h0; // @[execution-unit.scala:547:25] wire [4:0] exe_int_req_ftq_info_1_ghist_ras_idx = 5'h0; // @[execution-unit.scala:547:25] wire [63:0] exe_int_req_rs3_data = 64'h0; // @[execution-unit.scala:547:25] wire [63:0] exe_int_req_ftq_info_0_ghist_old_history = 64'h0; // @[execution-unit.scala:547:25] wire [63:0] exe_int_req_ftq_info_1_ghist_old_history = 64'h0; // @[execution-unit.scala:547:25] wire io_arb_prf_req_ready = 1'h1; // @[execution-unit.scala:492:7] wire io_arb_immrf_req_ready = 1'h1; // @[execution-unit.scala:492:7] wire io_arb_brf_req_ready = 1'h1; // @[execution-unit.scala:492:7] wire r_0 = 1'h1; // @[execution-unit.scala:74:21] wire _io_arb_irf_reqs_0_valid_T_3; // @[execution-unit.scala:121:83] wire _io_arb_irf_reqs_1_valid_T_3; // @[execution-unit.scala:125:85] wire _io_arb_immrf_req_valid_T_4; // @[execution-unit.scala:157:44] wire _io_arb_brf_req_valid_T_11; // @[execution-unit.scala:196:42] wire _io_arb_ftq_reqs_0_valid_T_5; // @[execution-unit.scala:244:45] wire _io_arb_ftq_reqs_1_valid_T_5; // @[execution-unit.scala:248:45] wire [4:0] _io_arb_ftq_reqs_1_bits_T_2; // @[util.scala:211:20] wire io_arb_irf_reqs_0_valid_0; // @[execution-unit.scala:492:7] wire [6:0] io_arb_irf_reqs_0_bits_0; // @[execution-unit.scala:492:7] wire io_arb_irf_reqs_1_valid_0; // @[execution-unit.scala:492:7] wire [6:0] io_arb_irf_reqs_1_bits_0; // @[execution-unit.scala:492:7] wire io_arb_prf_req_valid_0; // @[execution-unit.scala:492:7] wire [4:0] io_arb_prf_req_bits_0; // @[execution-unit.scala:492:7] wire io_arb_immrf_req_valid_0; // @[execution-unit.scala:492:7] wire [4:0] io_arb_immrf_req_bits_0; // @[execution-unit.scala:492:7] wire _io_rrd_immrf_wakeup_valid_T_4; // @[execution-unit.scala:162:47] wire io_arb_brf_req_valid_0; // @[execution-unit.scala:492:7] wire [3:0] io_arb_brf_req_bits_0; // @[execution-unit.scala:492:7] wire io_arb_ftq_reqs_0_valid_0; // @[execution-unit.scala:492:7] wire [4:0] io_arb_ftq_reqs_0_bits_0; // @[execution-unit.scala:492:7] wire io_arb_ftq_reqs_1_valid_0; // @[execution-unit.scala:492:7] wire [4:0] io_arb_ftq_reqs_1_bits_0; // @[execution-unit.scala:492:7] wire _io_fast_wakeup_valid_T_1; // @[execution-unit.scala:505:22] wire _io_fast_pred_wakeup_valid_T_3; // @[execution-unit.scala:514:49] wire _io_squash_iss_T_10; // @[execution-unit.scala:525:77] reg arb_uop_valid; // @[execution-unit.scala:92:20] assign io_arb_prf_req_valid_0 = arb_uop_valid; // @[execution-unit.scala:92:20, :492:7] reg [31:0] arb_uop_bits_inst; // @[execution-unit.scala:92:20] wire [31:0] rrd_uop_bits_out_inst = arb_uop_bits_inst; // @[util.scala:104:23] wire [31:0] arb_uop_bits_out_1_inst = arb_uop_bits_inst; // @[util.scala:104:23] reg [31:0] arb_uop_bits_debug_inst; // @[execution-unit.scala:92:20] wire [31:0] rrd_uop_bits_out_debug_inst = arb_uop_bits_debug_inst; // @[util.scala:104:23] wire [31:0] arb_uop_bits_out_1_debug_inst = arb_uop_bits_debug_inst; // @[util.scala:104:23] reg arb_uop_bits_is_rvc; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_rvc = arb_uop_bits_is_rvc; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_rvc = arb_uop_bits_is_rvc; // @[util.scala:104:23] reg [39:0] arb_uop_bits_debug_pc; // @[execution-unit.scala:92:20] wire [39:0] rrd_uop_bits_out_debug_pc = arb_uop_bits_debug_pc; // @[util.scala:104:23] wire [39:0] arb_uop_bits_out_1_debug_pc = arb_uop_bits_debug_pc; // @[util.scala:104:23] reg arb_uop_bits_iq_type_0; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iq_type_0 = arb_uop_bits_iq_type_0; // @[util.scala:104:23] wire arb_uop_bits_out_1_iq_type_0 = arb_uop_bits_iq_type_0; // @[util.scala:104:23] reg arb_uop_bits_iq_type_1; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iq_type_1 = arb_uop_bits_iq_type_1; // @[util.scala:104:23] wire arb_uop_bits_out_1_iq_type_1 = arb_uop_bits_iq_type_1; // @[util.scala:104:23] reg arb_uop_bits_iq_type_2; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iq_type_2 = arb_uop_bits_iq_type_2; // @[util.scala:104:23] wire arb_uop_bits_out_1_iq_type_2 = arb_uop_bits_iq_type_2; // @[util.scala:104:23] reg arb_uop_bits_iq_type_3; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iq_type_3 = arb_uop_bits_iq_type_3; // @[util.scala:104:23] wire arb_uop_bits_out_1_iq_type_3 = arb_uop_bits_iq_type_3; // @[util.scala:104:23] reg arb_uop_bits_fu_code_0; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_0 = arb_uop_bits_fu_code_0; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_0 = arb_uop_bits_fu_code_0; // @[util.scala:104:23] reg arb_uop_bits_fu_code_1; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_1 = arb_uop_bits_fu_code_1; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_1 = arb_uop_bits_fu_code_1; // @[util.scala:104:23] reg arb_uop_bits_fu_code_2; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_2 = arb_uop_bits_fu_code_2; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_2 = arb_uop_bits_fu_code_2; // @[util.scala:104:23] reg arb_uop_bits_fu_code_3; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_3 = arb_uop_bits_fu_code_3; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_3 = arb_uop_bits_fu_code_3; // @[util.scala:104:23] reg arb_uop_bits_fu_code_4; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_4 = arb_uop_bits_fu_code_4; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_4 = arb_uop_bits_fu_code_4; // @[util.scala:104:23] reg arb_uop_bits_fu_code_5; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_5 = arb_uop_bits_fu_code_5; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_5 = arb_uop_bits_fu_code_5; // @[util.scala:104:23] reg arb_uop_bits_fu_code_6; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_6 = arb_uop_bits_fu_code_6; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_6 = arb_uop_bits_fu_code_6; // @[util.scala:104:23] reg arb_uop_bits_fu_code_7; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_7 = arb_uop_bits_fu_code_7; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_7 = arb_uop_bits_fu_code_7; // @[util.scala:104:23] reg arb_uop_bits_fu_code_8; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_8 = arb_uop_bits_fu_code_8; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_8 = arb_uop_bits_fu_code_8; // @[util.scala:104:23] reg arb_uop_bits_fu_code_9; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_9 = arb_uop_bits_fu_code_9; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_9 = arb_uop_bits_fu_code_9; // @[util.scala:104:23] reg arb_uop_bits_iw_issued; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_issued = arb_uop_bits_iw_issued; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_issued = arb_uop_bits_iw_issued; // @[util.scala:104:23] reg arb_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_issued_partial_agen = arb_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_issued_partial_agen = arb_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23] reg arb_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_issued_partial_dgen = arb_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_issued_partial_dgen = arb_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23] reg [1:0] arb_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_iw_p1_speculative_child = arb_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_iw_p1_speculative_child = arb_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] arb_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_iw_p2_speculative_child = arb_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_iw_p2_speculative_child = arb_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23] reg arb_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_p1_bypass_hint = arb_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_p1_bypass_hint = arb_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23] reg arb_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_p2_bypass_hint = arb_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_p2_bypass_hint = arb_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23] reg arb_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_p3_bypass_hint = arb_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_p3_bypass_hint = arb_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] arb_uop_bits_dis_col_sel; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_dis_col_sel = arb_uop_bits_dis_col_sel; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_dis_col_sel = arb_uop_bits_dis_col_sel; // @[util.scala:104:23] reg [11:0] arb_uop_bits_br_mask; // @[execution-unit.scala:92:20] reg [3:0] arb_uop_bits_br_tag; // @[execution-unit.scala:92:20] assign io_arb_brf_req_bits_0 = arb_uop_bits_br_tag; // @[execution-unit.scala:92:20, :492:7] wire [3:0] rrd_uop_bits_out_br_tag = arb_uop_bits_br_tag; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_1_br_tag = arb_uop_bits_br_tag; // @[util.scala:104:23] reg [3:0] arb_uop_bits_br_type; // @[execution-unit.scala:92:20] wire [3:0] rrd_uop_bits_out_br_type = arb_uop_bits_br_type; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_1_br_type = arb_uop_bits_br_type; // @[util.scala:104:23] reg arb_uop_bits_is_sfb; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_sfb = arb_uop_bits_is_sfb; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_sfb = arb_uop_bits_is_sfb; // @[util.scala:104:23] reg arb_uop_bits_is_fence; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_fence = arb_uop_bits_is_fence; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_fence = arb_uop_bits_is_fence; // @[util.scala:104:23] reg arb_uop_bits_is_fencei; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_fencei = arb_uop_bits_is_fencei; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_fencei = arb_uop_bits_is_fencei; // @[util.scala:104:23] reg arb_uop_bits_is_sfence; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_sfence = arb_uop_bits_is_sfence; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_sfence = arb_uop_bits_is_sfence; // @[util.scala:104:23] reg arb_uop_bits_is_amo; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_amo = arb_uop_bits_is_amo; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_amo = arb_uop_bits_is_amo; // @[util.scala:104:23] reg arb_uop_bits_is_eret; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_eret = arb_uop_bits_is_eret; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_eret = arb_uop_bits_is_eret; // @[util.scala:104:23] reg arb_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_sys_pc2epc = arb_uop_bits_is_sys_pc2epc; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_sys_pc2epc = arb_uop_bits_is_sys_pc2epc; // @[util.scala:104:23] reg arb_uop_bits_is_rocc; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_rocc = arb_uop_bits_is_rocc; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_rocc = arb_uop_bits_is_rocc; // @[util.scala:104:23] reg arb_uop_bits_is_mov; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_mov = arb_uop_bits_is_mov; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_mov = arb_uop_bits_is_mov; // @[util.scala:104:23] reg [4:0] arb_uop_bits_ftq_idx; // @[execution-unit.scala:92:20] assign io_arb_ftq_reqs_0_bits_0 = arb_uop_bits_ftq_idx; // @[execution-unit.scala:92:20, :492:7] wire [4:0] rrd_uop_bits_out_ftq_idx = arb_uop_bits_ftq_idx; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_1_ftq_idx = arb_uop_bits_ftq_idx; // @[util.scala:104:23] reg arb_uop_bits_edge_inst; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_edge_inst = arb_uop_bits_edge_inst; // @[util.scala:104:23] wire arb_uop_bits_out_1_edge_inst = arb_uop_bits_edge_inst; // @[util.scala:104:23] reg [5:0] arb_uop_bits_pc_lob; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_pc_lob = arb_uop_bits_pc_lob; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_pc_lob = arb_uop_bits_pc_lob; // @[util.scala:104:23] reg arb_uop_bits_taken; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_taken = arb_uop_bits_taken; // @[util.scala:104:23] wire arb_uop_bits_out_1_taken = arb_uop_bits_taken; // @[util.scala:104:23] reg arb_uop_bits_imm_rename; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_imm_rename = arb_uop_bits_imm_rename; // @[util.scala:104:23] wire arb_uop_bits_out_1_imm_rename = arb_uop_bits_imm_rename; // @[util.scala:104:23] reg [2:0] arb_uop_bits_imm_sel; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_imm_sel = arb_uop_bits_imm_sel; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_imm_sel = arb_uop_bits_imm_sel; // @[util.scala:104:23] reg [4:0] arb_uop_bits_pimm; // @[execution-unit.scala:92:20] assign io_arb_immrf_req_bits_0 = arb_uop_bits_pimm; // @[execution-unit.scala:92:20, :492:7] wire [4:0] rrd_uop_bits_out_pimm = arb_uop_bits_pimm; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_1_pimm = arb_uop_bits_pimm; // @[util.scala:104:23] reg [19:0] arb_uop_bits_imm_packed; // @[execution-unit.scala:92:20] wire [19:0] rrd_uop_bits_out_imm_packed = arb_uop_bits_imm_packed; // @[util.scala:104:23] wire [19:0] arb_uop_bits_out_1_imm_packed = arb_uop_bits_imm_packed; // @[util.scala:104:23] reg [1:0] arb_uop_bits_op1_sel; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_op1_sel = arb_uop_bits_op1_sel; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_op1_sel = arb_uop_bits_op1_sel; // @[util.scala:104:23] reg [2:0] arb_uop_bits_op2_sel; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_op2_sel = arb_uop_bits_op2_sel; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_op2_sel = arb_uop_bits_op2_sel; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_ldst = arb_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_ldst = arb_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_wen = arb_uop_bits_fp_ctrl_wen; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_wen = arb_uop_bits_fp_ctrl_wen; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_ren1 = arb_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_ren1 = arb_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_ren2 = arb_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_ren2 = arb_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_ren3 = arb_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_ren3 = arb_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_swap12 = arb_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_swap12 = arb_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_swap23 = arb_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_swap23 = arb_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] arb_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_fp_ctrl_typeTagIn = arb_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_fp_ctrl_typeTagIn = arb_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] arb_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_fp_ctrl_typeTagOut = arb_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_fp_ctrl_typeTagOut = arb_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_fromint = arb_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_fromint = arb_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_toint = arb_uop_bits_fp_ctrl_toint; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_toint = arb_uop_bits_fp_ctrl_toint; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_fastpipe = arb_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_fastpipe = arb_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_fma = arb_uop_bits_fp_ctrl_fma; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_fma = arb_uop_bits_fp_ctrl_fma; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_div; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_div = arb_uop_bits_fp_ctrl_div; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_div = arb_uop_bits_fp_ctrl_div; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_sqrt = arb_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_sqrt = arb_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_wflags = arb_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_wflags = arb_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_vec = arb_uop_bits_fp_ctrl_vec; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_vec = arb_uop_bits_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] arb_uop_bits_rob_idx; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_rob_idx = arb_uop_bits_rob_idx; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_rob_idx = arb_uop_bits_rob_idx; // @[util.scala:104:23] reg [3:0] arb_uop_bits_ldq_idx; // @[execution-unit.scala:92:20] wire [3:0] rrd_uop_bits_out_ldq_idx = arb_uop_bits_ldq_idx; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_1_ldq_idx = arb_uop_bits_ldq_idx; // @[util.scala:104:23] reg [3:0] arb_uop_bits_stq_idx; // @[execution-unit.scala:92:20] wire [3:0] rrd_uop_bits_out_stq_idx = arb_uop_bits_stq_idx; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_1_stq_idx = arb_uop_bits_stq_idx; // @[util.scala:104:23] reg [1:0] arb_uop_bits_rxq_idx; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_rxq_idx = arb_uop_bits_rxq_idx; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_rxq_idx = arb_uop_bits_rxq_idx; // @[util.scala:104:23] reg [6:0] arb_uop_bits_pdst; // @[execution-unit.scala:92:20] wire [6:0] rrd_uop_bits_out_pdst = arb_uop_bits_pdst; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_1_pdst = arb_uop_bits_pdst; // @[util.scala:104:23] reg [6:0] arb_uop_bits_prs1; // @[execution-unit.scala:92:20] assign io_arb_irf_reqs_0_bits_0 = arb_uop_bits_prs1; // @[execution-unit.scala:92:20, :492:7] wire [6:0] rrd_uop_bits_out_prs1 = arb_uop_bits_prs1; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_1_prs1 = arb_uop_bits_prs1; // @[util.scala:104:23] reg [6:0] arb_uop_bits_prs2; // @[execution-unit.scala:92:20] assign io_arb_irf_reqs_1_bits_0 = arb_uop_bits_prs2; // @[execution-unit.scala:92:20, :492:7] wire [6:0] rrd_uop_bits_out_prs2 = arb_uop_bits_prs2; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_1_prs2 = arb_uop_bits_prs2; // @[util.scala:104:23] reg [6:0] arb_uop_bits_prs3; // @[execution-unit.scala:92:20] wire [6:0] rrd_uop_bits_out_prs3 = arb_uop_bits_prs3; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_1_prs3 = arb_uop_bits_prs3; // @[util.scala:104:23] reg [4:0] arb_uop_bits_ppred; // @[execution-unit.scala:92:20] assign io_arb_prf_req_bits_0 = arb_uop_bits_ppred; // @[execution-unit.scala:92:20, :492:7] wire [4:0] rrd_uop_bits_out_ppred = arb_uop_bits_ppred; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_1_ppred = arb_uop_bits_ppred; // @[util.scala:104:23] reg arb_uop_bits_prs1_busy; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_prs1_busy = arb_uop_bits_prs1_busy; // @[util.scala:104:23] wire arb_uop_bits_out_1_prs1_busy = arb_uop_bits_prs1_busy; // @[util.scala:104:23] reg arb_uop_bits_prs2_busy; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_prs2_busy = arb_uop_bits_prs2_busy; // @[util.scala:104:23] wire arb_uop_bits_out_1_prs2_busy = arb_uop_bits_prs2_busy; // @[util.scala:104:23] reg arb_uop_bits_prs3_busy; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_prs3_busy = arb_uop_bits_prs3_busy; // @[util.scala:104:23] wire arb_uop_bits_out_1_prs3_busy = arb_uop_bits_prs3_busy; // @[util.scala:104:23] reg arb_uop_bits_ppred_busy; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_ppred_busy = arb_uop_bits_ppred_busy; // @[util.scala:104:23] wire arb_uop_bits_out_1_ppred_busy = arb_uop_bits_ppred_busy; // @[util.scala:104:23] reg [6:0] arb_uop_bits_stale_pdst; // @[execution-unit.scala:92:20] wire [6:0] rrd_uop_bits_out_stale_pdst = arb_uop_bits_stale_pdst; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_1_stale_pdst = arb_uop_bits_stale_pdst; // @[util.scala:104:23] reg arb_uop_bits_exception; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_exception = arb_uop_bits_exception; // @[util.scala:104:23] wire arb_uop_bits_out_1_exception = arb_uop_bits_exception; // @[util.scala:104:23] reg [63:0] arb_uop_bits_exc_cause; // @[execution-unit.scala:92:20] wire [63:0] rrd_uop_bits_out_exc_cause = arb_uop_bits_exc_cause; // @[util.scala:104:23] wire [63:0] arb_uop_bits_out_1_exc_cause = arb_uop_bits_exc_cause; // @[util.scala:104:23] reg [4:0] arb_uop_bits_mem_cmd; // @[execution-unit.scala:92:20] wire [4:0] rrd_uop_bits_out_mem_cmd = arb_uop_bits_mem_cmd; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_1_mem_cmd = arb_uop_bits_mem_cmd; // @[util.scala:104:23] reg [1:0] arb_uop_bits_mem_size; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_mem_size = arb_uop_bits_mem_size; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_mem_size = arb_uop_bits_mem_size; // @[util.scala:104:23] reg arb_uop_bits_mem_signed; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_mem_signed = arb_uop_bits_mem_signed; // @[util.scala:104:23] wire arb_uop_bits_out_1_mem_signed = arb_uop_bits_mem_signed; // @[util.scala:104:23] reg arb_uop_bits_uses_ldq; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_uses_ldq = arb_uop_bits_uses_ldq; // @[util.scala:104:23] wire arb_uop_bits_out_1_uses_ldq = arb_uop_bits_uses_ldq; // @[util.scala:104:23] reg arb_uop_bits_uses_stq; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_uses_stq = arb_uop_bits_uses_stq; // @[util.scala:104:23] wire arb_uop_bits_out_1_uses_stq = arb_uop_bits_uses_stq; // @[util.scala:104:23] reg arb_uop_bits_is_unique; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_unique = arb_uop_bits_is_unique; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_unique = arb_uop_bits_is_unique; // @[util.scala:104:23] reg arb_uop_bits_flush_on_commit; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_flush_on_commit = arb_uop_bits_flush_on_commit; // @[util.scala:104:23] wire arb_uop_bits_out_1_flush_on_commit = arb_uop_bits_flush_on_commit; // @[util.scala:104:23] reg [2:0] arb_uop_bits_csr_cmd; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_csr_cmd = arb_uop_bits_csr_cmd; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_csr_cmd = arb_uop_bits_csr_cmd; // @[util.scala:104:23] reg arb_uop_bits_ldst_is_rs1; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_ldst_is_rs1 = arb_uop_bits_ldst_is_rs1; // @[util.scala:104:23] wire arb_uop_bits_out_1_ldst_is_rs1 = arb_uop_bits_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] arb_uop_bits_ldst; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_ldst = arb_uop_bits_ldst; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_ldst = arb_uop_bits_ldst; // @[util.scala:104:23] reg [5:0] arb_uop_bits_lrs1; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_lrs1 = arb_uop_bits_lrs1; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_lrs1 = arb_uop_bits_lrs1; // @[util.scala:104:23] reg [5:0] arb_uop_bits_lrs2; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_lrs2 = arb_uop_bits_lrs2; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_lrs2 = arb_uop_bits_lrs2; // @[util.scala:104:23] reg [5:0] arb_uop_bits_lrs3; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_lrs3 = arb_uop_bits_lrs3; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_lrs3 = arb_uop_bits_lrs3; // @[util.scala:104:23] reg [1:0] arb_uop_bits_dst_rtype; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_dst_rtype = arb_uop_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_dst_rtype = arb_uop_bits_dst_rtype; // @[util.scala:104:23] reg [1:0] arb_uop_bits_lrs1_rtype; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_lrs1_rtype = arb_uop_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_lrs1_rtype = arb_uop_bits_lrs1_rtype; // @[util.scala:104:23] reg [1:0] arb_uop_bits_lrs2_rtype; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_lrs2_rtype = arb_uop_bits_lrs2_rtype; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_lrs2_rtype = arb_uop_bits_lrs2_rtype; // @[util.scala:104:23] reg arb_uop_bits_frs3_en; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_frs3_en = arb_uop_bits_frs3_en; // @[util.scala:104:23] wire arb_uop_bits_out_1_frs3_en = arb_uop_bits_frs3_en; // @[util.scala:104:23] reg arb_uop_bits_fcn_dw; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fcn_dw = arb_uop_bits_fcn_dw; // @[util.scala:104:23] wire arb_uop_bits_out_1_fcn_dw = arb_uop_bits_fcn_dw; // @[util.scala:104:23] reg [4:0] arb_uop_bits_fcn_op; // @[execution-unit.scala:92:20] wire [4:0] rrd_uop_bits_out_fcn_op = arb_uop_bits_fcn_op; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_1_fcn_op = arb_uop_bits_fcn_op; // @[util.scala:104:23] reg arb_uop_bits_fp_val; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_val = arb_uop_bits_fp_val; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_val = arb_uop_bits_fp_val; // @[util.scala:104:23] reg [2:0] arb_uop_bits_fp_rm; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_fp_rm = arb_uop_bits_fp_rm; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_fp_rm = arb_uop_bits_fp_rm; // @[util.scala:104:23] reg [1:0] arb_uop_bits_fp_typ; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_fp_typ = arb_uop_bits_fp_typ; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_fp_typ = arb_uop_bits_fp_typ; // @[util.scala:104:23] reg arb_uop_bits_xcpt_pf_if; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_xcpt_pf_if = arb_uop_bits_xcpt_pf_if; // @[util.scala:104:23] wire arb_uop_bits_out_1_xcpt_pf_if = arb_uop_bits_xcpt_pf_if; // @[util.scala:104:23] reg arb_uop_bits_xcpt_ae_if; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_xcpt_ae_if = arb_uop_bits_xcpt_ae_if; // @[util.scala:104:23] wire arb_uop_bits_out_1_xcpt_ae_if = arb_uop_bits_xcpt_ae_if; // @[util.scala:104:23] reg arb_uop_bits_xcpt_ma_if; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_xcpt_ma_if = arb_uop_bits_xcpt_ma_if; // @[util.scala:104:23] wire arb_uop_bits_out_1_xcpt_ma_if = arb_uop_bits_xcpt_ma_if; // @[util.scala:104:23] reg arb_uop_bits_bp_debug_if; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_bp_debug_if = arb_uop_bits_bp_debug_if; // @[util.scala:104:23] wire arb_uop_bits_out_1_bp_debug_if = arb_uop_bits_bp_debug_if; // @[util.scala:104:23] reg arb_uop_bits_bp_xcpt_if; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_bp_xcpt_if = arb_uop_bits_bp_xcpt_if; // @[util.scala:104:23] wire arb_uop_bits_out_1_bp_xcpt_if = arb_uop_bits_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] arb_uop_bits_debug_fsrc; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_debug_fsrc = arb_uop_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_debug_fsrc = arb_uop_bits_debug_fsrc; // @[util.scala:104:23] reg [2:0] arb_uop_bits_debug_tsrc; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_debug_tsrc = arb_uop_bits_debug_tsrc; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_debug_tsrc = arb_uop_bits_debug_tsrc; // @[util.scala:104:23] wire [11:0] _arb_uop_valid_T = io_brupdate_b1_mispredict_mask & io_iss_uop_bits_br_mask; // @[util.scala:126:51] wire _arb_uop_valid_T_1 = \|_arb_uop_valid_T; // @[util.scala:126:{51,59}] wire _arb_uop_valid_T_2 = _arb_uop_valid_T_1 \| io_kill; // @[util.scala:61:61, :126:59] wire _arb_uop_valid_T_3 = ~_arb_uop_valid_T_2; // @[util.scala:61:61] wire _arb_uop_valid_T_4 = io_iss_uop_valid & _arb_uop_valid_T_3; // @[execution-unit.scala:93:{37,40}] wire [11:0] _arb_uop_bits_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] arb_uop_bits_out_br_mask; // @[util.scala:104:23] wire [11:0] _arb_uop_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27] assign _arb_uop_bits_out_br_mask_T_1 = io_iss_uop_bits_br_mask & _arb_uop_bits_out_br_mask_T; // @[util.scala:93:{25,27}] assign arb_uop_bits_out_br_mask = _arb_uop_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg rrd_uop_valid; // @[execution-unit.scala:95:20] wire [31:0] exe_uop_bits_out_inst = rrd_uop_bits_inst; // @[util.scala:104:23] wire [31:0] exe_uop_bits_out_debug_inst = rrd_uop_bits_debug_inst; // @[util.scala:104:23] wire exe_uop_bits_out_is_rvc = rrd_uop_bits_is_rvc; // @[util.scala:104:23] wire [39:0] exe_uop_bits_out_debug_pc = rrd_uop_bits_debug_pc; // @[util.scala:104:23] wire exe_uop_bits_out_iq_type_0 = rrd_uop_bits_iq_type_0; // @[util.scala:104:23] wire exe_uop_bits_out_iq_type_1 = rrd_uop_bits_iq_type_1; // @[util.scala:104:23] wire exe_uop_bits_out_iq_type_2 = rrd_uop_bits_iq_type_2; // @[util.scala:104:23] wire exe_uop_bits_out_iq_type_3 = rrd_uop_bits_iq_type_3; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_0 = rrd_uop_bits_fu_code_0; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_1 = rrd_uop_bits_fu_code_1; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_2 = rrd_uop_bits_fu_code_2; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_3 = rrd_uop_bits_fu_code_3; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_4 = rrd_uop_bits_fu_code_4; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_5 = rrd_uop_bits_fu_code_5; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_6 = rrd_uop_bits_fu_code_6; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_7 = rrd_uop_bits_fu_code_7; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_8 = rrd_uop_bits_fu_code_8; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_9 = rrd_uop_bits_fu_code_9; // @[util.scala:104:23] wire exe_uop_bits_out_iw_issued = rrd_uop_bits_iw_issued; // @[util.scala:104:23] wire exe_uop_bits_out_iw_issued_partial_agen = rrd_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire exe_uop_bits_out_iw_issued_partial_dgen = rrd_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_iw_p1_speculative_child = rrd_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_iw_p2_speculative_child = rrd_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire exe_uop_bits_out_iw_p1_bypass_hint = rrd_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire exe_uop_bits_out_iw_p2_bypass_hint = rrd_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire exe_uop_bits_out_iw_p3_bypass_hint = rrd_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_dis_col_sel = rrd_uop_bits_dis_col_sel; // @[util.scala:104:23] wire [3:0] exe_uop_bits_out_br_tag = rrd_uop_bits_br_tag; // @[util.scala:104:23] wire [3:0] exe_uop_bits_out_br_type = rrd_uop_bits_br_type; // @[util.scala:104:23] wire exe_uop_bits_out_is_sfb = rrd_uop_bits_is_sfb; // @[util.scala:104:23] wire exe_uop_bits_out_is_fence = rrd_uop_bits_is_fence; // @[util.scala:104:23] wire exe_uop_bits_out_is_fencei = rrd_uop_bits_is_fencei; // @[util.scala:104:23] wire exe_uop_bits_out_is_sfence = rrd_uop_bits_is_sfence; // @[util.scala:104:23] wire exe_uop_bits_out_is_amo = rrd_uop_bits_is_amo; // @[util.scala:104:23] wire exe_uop_bits_out_is_eret = rrd_uop_bits_is_eret; // @[util.scala:104:23] wire exe_uop_bits_out_is_sys_pc2epc = rrd_uop_bits_is_sys_pc2epc; // @[util.scala:104:23] wire exe_uop_bits_out_is_rocc = rrd_uop_bits_is_rocc; // @[util.scala:104:23] wire exe_uop_bits_out_is_mov = rrd_uop_bits_is_mov; // @[util.scala:104:23] wire [4:0] exe_uop_bits_out_ftq_idx = rrd_uop_bits_ftq_idx; // @[util.scala:104:23] wire exe_uop_bits_out_edge_inst = rrd_uop_bits_edge_inst; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_pc_lob = rrd_uop_bits_pc_lob; // @[util.scala:104:23] wire exe_uop_bits_out_taken = rrd_uop_bits_taken; // @[util.scala:104:23] wire exe_uop_bits_out_imm_rename = rrd_uop_bits_imm_rename; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_imm_sel = rrd_uop_bits_imm_sel; // @[util.scala:104:23] wire [4:0] exe_uop_bits_out_pimm = rrd_uop_bits_pimm; // @[util.scala:104:23] wire [19:0] exe_uop_bits_out_imm_packed = rrd_uop_bits_imm_packed; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_op1_sel = rrd_uop_bits_op1_sel; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_op2_sel = rrd_uop_bits_op2_sel; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_ldst = rrd_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_wen = rrd_uop_bits_fp_ctrl_wen; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_ren1 = rrd_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_ren2 = rrd_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_ren3 = rrd_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_swap12 = rrd_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_swap23 = rrd_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_fp_ctrl_typeTagIn = rrd_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_fp_ctrl_typeTagOut = rrd_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_fromint = rrd_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_toint = rrd_uop_bits_fp_ctrl_toint; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_fastpipe = rrd_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_fma = rrd_uop_bits_fp_ctrl_fma; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_div = rrd_uop_bits_fp_ctrl_div; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_sqrt = rrd_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_wflags = rrd_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_vec = rrd_uop_bits_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_rob_idx = rrd_uop_bits_rob_idx; // @[util.scala:104:23] wire [3:0] exe_uop_bits_out_ldq_idx = rrd_uop_bits_ldq_idx; // @[util.scala:104:23] wire [3:0] exe_uop_bits_out_stq_idx = rrd_uop_bits_stq_idx; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_rxq_idx = rrd_uop_bits_rxq_idx; // @[util.scala:104:23] wire [6:0] exe_uop_bits_out_pdst = rrd_uop_bits_pdst; // @[util.scala:104:23] wire [6:0] exe_uop_bits_out_prs1 = rrd_uop_bits_prs1; // @[util.scala:104:23] wire [6:0] exe_uop_bits_out_prs2 = rrd_uop_bits_prs2; // @[util.scala:104:23] wire [6:0] exe_uop_bits_out_prs3 = rrd_uop_bits_prs3; // @[util.scala:104:23] wire [4:0] exe_uop_bits_out_ppred = rrd_uop_bits_ppred; // @[util.scala:104:23] wire exe_uop_bits_out_prs1_busy = rrd_uop_bits_prs1_busy; // @[util.scala:104:23] wire exe_uop_bits_out_prs2_busy = rrd_uop_bits_prs2_busy; // @[util.scala:104:23] wire exe_uop_bits_out_prs3_busy = rrd_uop_bits_prs3_busy; // @[util.scala:104:23] wire exe_uop_bits_out_ppred_busy = rrd_uop_bits_ppred_busy; // @[util.scala:104:23] wire [6:0] exe_uop_bits_out_stale_pdst = rrd_uop_bits_stale_pdst; // @[util.scala:104:23] wire exe_uop_bits_out_exception = rrd_uop_bits_exception; // @[util.scala:104:23] wire [63:0] exe_uop_bits_out_exc_cause = rrd_uop_bits_exc_cause; // @[util.scala:104:23] wire [4:0] exe_uop_bits_out_mem_cmd = rrd_uop_bits_mem_cmd; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_mem_size = rrd_uop_bits_mem_size; // @[util.scala:104:23] wire exe_uop_bits_out_mem_signed = rrd_uop_bits_mem_signed; // @[util.scala:104:23] wire exe_uop_bits_out_uses_ldq = rrd_uop_bits_uses_ldq; // @[util.scala:104:23] wire exe_uop_bits_out_uses_stq = rrd_uop_bits_uses_stq; // @[util.scala:104:23] wire exe_uop_bits_out_is_unique = rrd_uop_bits_is_unique; // @[util.scala:104:23] wire exe_uop_bits_out_flush_on_commit = rrd_uop_bits_flush_on_commit; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_csr_cmd = rrd_uop_bits_csr_cmd; // @[util.scala:104:23] wire exe_uop_bits_out_ldst_is_rs1 = rrd_uop_bits_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_ldst = rrd_uop_bits_ldst; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_lrs1 = rrd_uop_bits_lrs1; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_lrs2 = rrd_uop_bits_lrs2; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_lrs3 = rrd_uop_bits_lrs3; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_dst_rtype = rrd_uop_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_lrs1_rtype = rrd_uop_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_lrs2_rtype = rrd_uop_bits_lrs2_rtype; // @[util.scala:104:23] wire exe_uop_bits_out_frs3_en = rrd_uop_bits_frs3_en; // @[util.scala:104:23] wire exe_uop_bits_out_fcn_dw = rrd_uop_bits_fcn_dw; // @[util.scala:104:23] wire [4:0] exe_uop_bits_out_fcn_op = rrd_uop_bits_fcn_op; // @[util.scala:104:23] wire exe_uop_bits_out_fp_val = rrd_uop_bits_fp_val; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_fp_rm = rrd_uop_bits_fp_rm; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_fp_typ = rrd_uop_bits_fp_typ; // @[util.scala:104:23] wire exe_uop_bits_out_xcpt_pf_if = rrd_uop_bits_xcpt_pf_if; // @[util.scala:104:23] wire exe_uop_bits_out_xcpt_ae_if = rrd_uop_bits_xcpt_ae_if; // @[util.scala:104:23] wire exe_uop_bits_out_xcpt_ma_if = rrd_uop_bits_xcpt_ma_if; // @[util.scala:104:23] wire exe_uop_bits_out_bp_debug_if = rrd_uop_bits_bp_debug_if; // @[util.scala:104:23] wire exe_uop_bits_out_bp_xcpt_if = rrd_uop_bits_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_debug_fsrc = rrd_uop_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_debug_tsrc = rrd_uop_bits_debug_tsrc; // @[util.scala:104:23] wire [11:0] _GEN = io_brupdate_b1_mispredict_mask & arb_uop_bits_br_mask; // @[util.scala:126:51] wire [11:0] _rrd_uop_valid_T; // @[util.scala:126:51] assign _rrd_uop_valid_T = _GEN; // @[util.scala:126:51] wire [11:0] _will_replay_T; // @[util.scala:126:51] assign _will_replay_T = _GEN; // @[util.scala:126:51] wire _rrd_uop_valid_T_1 = \|_rrd_uop_valid_T; // @[util.scala:126:{51,59}] wire _rrd_uop_valid_T_2 = _rrd_uop_valid_T_1 \| io_kill; // @[util.scala:61:61, :126:59] wire _rrd_uop_valid_T_3 = ~_rrd_uop_valid_T_2; // @[util.scala:61:61] wire _rrd_uop_valid_T_4 = arb_uop_valid & _rrd_uop_valid_T_3; // @[execution-unit.scala:92:20, :96:{34,37}] wire [11:0] _rrd_uop_bits_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] rrd_uop_bits_out_br_mask; // @[util.scala:104:23] wire [11:0] _rrd_uop_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27] assign _rrd_uop_bits_out_br_mask_T_1 = arb_uop_bits_br_mask & _rrd_uop_bits_out_br_mask_T; // @[util.scala:93:{25,27}] assign rrd_uop_bits_out_br_mask = _rrd_uop_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg exe_uop_valid; // @[execution-unit.scala:98:20] reg [31:0] exe_uop_bits_inst; // @[execution-unit.scala:98:20] wire [31:0] exe_int_req_uop_inst = exe_uop_bits_inst; // @[execution-unit.scala:98:20, :547:25] reg [31:0] exe_uop_bits_debug_inst; // @[execution-unit.scala:98:20] wire [31:0] exe_int_req_uop_debug_inst = exe_uop_bits_debug_inst; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_rvc; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_rvc = exe_uop_bits_is_rvc; // @[execution-unit.scala:98:20, :547:25] reg [39:0] exe_uop_bits_debug_pc; // @[execution-unit.scala:98:20] wire [39:0] exe_int_req_uop_debug_pc = exe_uop_bits_debug_pc; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iq_type_0; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iq_type_0 = exe_uop_bits_iq_type_0; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iq_type_1; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iq_type_1 = exe_uop_bits_iq_type_1; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iq_type_2; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iq_type_2 = exe_uop_bits_iq_type_2; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iq_type_3; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iq_type_3 = exe_uop_bits_iq_type_3; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_0; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_0 = exe_uop_bits_fu_code_0; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_1; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_1 = exe_uop_bits_fu_code_1; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_2; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_2 = exe_uop_bits_fu_code_2; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_3; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_3 = exe_uop_bits_fu_code_3; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_4; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_4 = exe_uop_bits_fu_code_4; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_5; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_5 = exe_uop_bits_fu_code_5; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_6; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_6 = exe_uop_bits_fu_code_6; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_7; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_7 = exe_uop_bits_fu_code_7; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_8; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_8 = exe_uop_bits_fu_code_8; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_9; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_9 = exe_uop_bits_fu_code_9; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iw_issued; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_issued = exe_uop_bits_iw_issued; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_issued_partial_agen = exe_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_issued_partial_dgen = exe_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_iw_p1_speculative_child = exe_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_iw_p2_speculative_child = exe_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_p1_bypass_hint = exe_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_p2_bypass_hint = exe_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_p3_bypass_hint = exe_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_dis_col_sel; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_dis_col_sel = exe_uop_bits_dis_col_sel; // @[execution-unit.scala:98:20, :547:25] reg [11:0] exe_uop_bits_br_mask; // @[execution-unit.scala:98:20] wire [11:0] exe_int_req_uop_br_mask = exe_uop_bits_br_mask; // @[execution-unit.scala:98:20, :547:25] reg [3:0] exe_uop_bits_br_tag; // @[execution-unit.scala:98:20] wire [3:0] exe_int_req_uop_br_tag = exe_uop_bits_br_tag; // @[execution-unit.scala:98:20, :547:25] reg [3:0] exe_uop_bits_br_type; // @[execution-unit.scala:98:20] wire [3:0] exe_int_req_uop_br_type = exe_uop_bits_br_type; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_sfb; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_sfb = exe_uop_bits_is_sfb; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_fence; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_fence = exe_uop_bits_is_fence; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_fencei; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_fencei = exe_uop_bits_is_fencei; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_sfence; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_sfence = exe_uop_bits_is_sfence; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_amo; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_amo = exe_uop_bits_is_amo; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_eret; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_eret = exe_uop_bits_is_eret; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_sys_pc2epc = exe_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_rocc; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_rocc = exe_uop_bits_is_rocc; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_mov; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_mov = exe_uop_bits_is_mov; // @[execution-unit.scala:98:20, :547:25] reg [4:0] exe_uop_bits_ftq_idx; // @[execution-unit.scala:98:20] wire [4:0] exe_int_req_uop_ftq_idx = exe_uop_bits_ftq_idx; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_edge_inst; // @[execution-unit.scala:98:20] wire exe_int_req_uop_edge_inst = exe_uop_bits_edge_inst; // @[execution-unit.scala:98:20, :547:25] reg [5:0] exe_uop_bits_pc_lob; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_pc_lob = exe_uop_bits_pc_lob; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_taken; // @[execution-unit.scala:98:20] wire exe_int_req_uop_taken = exe_uop_bits_taken; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_imm_rename; // @[execution-unit.scala:98:20] wire exe_int_req_uop_imm_rename = exe_uop_bits_imm_rename; // @[execution-unit.scala:98:20, :547:25] reg [2:0] exe_uop_bits_imm_sel; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_imm_sel = exe_uop_bits_imm_sel; // @[execution-unit.scala:98:20, :547:25] reg [4:0] exe_uop_bits_pimm; // @[execution-unit.scala:98:20] wire [4:0] exe_int_req_uop_pimm = exe_uop_bits_pimm; // @[execution-unit.scala:98:20, :547:25] reg [19:0] exe_uop_bits_imm_packed; // @[execution-unit.scala:98:20] wire [19:0] exe_int_req_uop_imm_packed = exe_uop_bits_imm_packed; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_op1_sel; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_op1_sel = exe_uop_bits_op1_sel; // @[execution-unit.scala:98:20, :547:25] reg [2:0] exe_uop_bits_op2_sel; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_op2_sel = exe_uop_bits_op2_sel; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_ldst = exe_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_wen = exe_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_ren1 = exe_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_ren2 = exe_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_ren3 = exe_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_swap12 = exe_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_swap23 = exe_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_fp_ctrl_typeTagIn = exe_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_fp_ctrl_typeTagOut = exe_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_fromint = exe_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_toint = exe_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_fastpipe = exe_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_fma = exe_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_div; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_div = exe_uop_bits_fp_ctrl_div; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_sqrt = exe_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_wflags = exe_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_vec = exe_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:98:20, :547:25] reg [5:0] exe_uop_bits_rob_idx; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_rob_idx = exe_uop_bits_rob_idx; // @[execution-unit.scala:98:20, :547:25] reg [3:0] exe_uop_bits_ldq_idx; // @[execution-unit.scala:98:20] wire [3:0] exe_int_req_uop_ldq_idx = exe_uop_bits_ldq_idx; // @[execution-unit.scala:98:20, :547:25] reg [3:0] exe_uop_bits_stq_idx; // @[execution-unit.scala:98:20] wire [3:0] exe_int_req_uop_stq_idx = exe_uop_bits_stq_idx; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_rxq_idx; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_rxq_idx = exe_uop_bits_rxq_idx; // @[execution-unit.scala:98:20, :547:25] reg [6:0] exe_uop_bits_pdst; // @[execution-unit.scala:98:20] wire [6:0] exe_int_req_uop_pdst = exe_uop_bits_pdst; // @[execution-unit.scala:98:20, :547:25] reg [6:0] exe_uop_bits_prs1; // @[execution-unit.scala:98:20] wire [6:0] exe_int_req_uop_prs1 = exe_uop_bits_prs1; // @[execution-unit.scala:98:20, :547:25] reg [6:0] exe_uop_bits_prs2; // @[execution-unit.scala:98:20] wire [6:0] exe_int_req_uop_prs2 = exe_uop_bits_prs2; // @[execution-unit.scala:98:20, :547:25] reg [6:0] exe_uop_bits_prs3; // @[execution-unit.scala:98:20] wire [6:0] exe_int_req_uop_prs3 = exe_uop_bits_prs3; // @[execution-unit.scala:98:20, :547:25] reg [4:0] exe_uop_bits_ppred; // @[execution-unit.scala:98:20] wire [4:0] exe_int_req_uop_ppred = exe_uop_bits_ppred; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_prs1_busy; // @[execution-unit.scala:98:20] wire exe_int_req_uop_prs1_busy = exe_uop_bits_prs1_busy; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_prs2_busy; // @[execution-unit.scala:98:20] wire exe_int_req_uop_prs2_busy = exe_uop_bits_prs2_busy; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_prs3_busy; // @[execution-unit.scala:98:20] wire exe_int_req_uop_prs3_busy = exe_uop_bits_prs3_busy; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_ppred_busy; // @[execution-unit.scala:98:20] wire exe_int_req_uop_ppred_busy = exe_uop_bits_ppred_busy; // @[execution-unit.scala:98:20, :547:25] reg [6:0] exe_uop_bits_stale_pdst; // @[execution-unit.scala:98:20] wire [6:0] exe_int_req_uop_stale_pdst = exe_uop_bits_stale_pdst; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_exception; // @[execution-unit.scala:98:20] wire exe_int_req_uop_exception = exe_uop_bits_exception; // @[execution-unit.scala:98:20, :547:25] reg [63:0] exe_uop_bits_exc_cause; // @[execution-unit.scala:98:20] wire [63:0] exe_int_req_uop_exc_cause = exe_uop_bits_exc_cause; // @[execution-unit.scala:98:20, :547:25] reg [4:0] exe_uop_bits_mem_cmd; // @[execution-unit.scala:98:20] wire [4:0] exe_int_req_uop_mem_cmd = exe_uop_bits_mem_cmd; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_mem_size; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_mem_size = exe_uop_bits_mem_size; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_mem_signed; // @[execution-unit.scala:98:20] wire exe_int_req_uop_mem_signed = exe_uop_bits_mem_signed; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_uses_ldq; // @[execution-unit.scala:98:20] wire exe_int_req_uop_uses_ldq = exe_uop_bits_uses_ldq; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_uses_stq; // @[execution-unit.scala:98:20] wire exe_int_req_uop_uses_stq = exe_uop_bits_uses_stq; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_unique; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_unique = exe_uop_bits_is_unique; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_flush_on_commit; // @[execution-unit.scala:98:20] wire exe_int_req_uop_flush_on_commit = exe_uop_bits_flush_on_commit; // @[execution-unit.scala:98:20, :547:25] reg [2:0] exe_uop_bits_csr_cmd; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_csr_cmd = exe_uop_bits_csr_cmd; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_ldst_is_rs1; // @[execution-unit.scala:98:20] wire exe_int_req_uop_ldst_is_rs1 = exe_uop_bits_ldst_is_rs1; // @[execution-unit.scala:98:20, :547:25] reg [5:0] exe_uop_bits_ldst; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_ldst = exe_uop_bits_ldst; // @[execution-unit.scala:98:20, :547:25] reg [5:0] exe_uop_bits_lrs1; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_lrs1 = exe_uop_bits_lrs1; // @[execution-unit.scala:98:20, :547:25] reg [5:0] exe_uop_bits_lrs2; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_lrs2 = exe_uop_bits_lrs2; // @[execution-unit.scala:98:20, :547:25] reg [5:0] exe_uop_bits_lrs3; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_lrs3 = exe_uop_bits_lrs3; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_dst_rtype; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_dst_rtype = exe_uop_bits_dst_rtype; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_lrs1_rtype; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_lrs1_rtype = exe_uop_bits_lrs1_rtype; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_lrs2_rtype; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_lrs2_rtype = exe_uop_bits_lrs2_rtype; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_frs3_en; // @[execution-unit.scala:98:20] wire exe_int_req_uop_frs3_en = exe_uop_bits_frs3_en; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fcn_dw; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fcn_dw = exe_uop_bits_fcn_dw; // @[execution-unit.scala:98:20, :547:25] reg [4:0] exe_uop_bits_fcn_op; // @[execution-unit.scala:98:20] wire [4:0] exe_int_req_uop_fcn_op = exe_uop_bits_fcn_op; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_val; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_val = exe_uop_bits_fp_val; // @[execution-unit.scala:98:20, :547:25] reg [2:0] exe_uop_bits_fp_rm; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_fp_rm = exe_uop_bits_fp_rm; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_fp_typ; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_fp_typ = exe_uop_bits_fp_typ; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_xcpt_pf_if; // @[execution-unit.scala:98:20] wire exe_int_req_uop_xcpt_pf_if = exe_uop_bits_xcpt_pf_if; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_xcpt_ae_if; // @[execution-unit.scala:98:20] wire exe_int_req_uop_xcpt_ae_if = exe_uop_bits_xcpt_ae_if; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_xcpt_ma_if; // @[execution-unit.scala:98:20] wire exe_int_req_uop_xcpt_ma_if = exe_uop_bits_xcpt_ma_if; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_bp_debug_if; // @[execution-unit.scala:98:20] wire exe_int_req_uop_bp_debug_if = exe_uop_bits_bp_debug_if; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_bp_xcpt_if; // @[execution-unit.scala:98:20] wire exe_int_req_uop_bp_xcpt_if = exe_uop_bits_bp_xcpt_if; // @[execution-unit.scala:98:20, :547:25] reg [2:0] exe_uop_bits_debug_fsrc; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_debug_fsrc = exe_uop_bits_debug_fsrc; // @[execution-unit.scala:98:20, :547:25] reg [2:0] exe_uop_bits_debug_tsrc; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_debug_tsrc = exe_uop_bits_debug_tsrc; // @[execution-unit.scala:98:20, :547:25] wire [11:0] _exe_uop_valid_T = io_brupdate_b1_mispredict_mask & rrd_uop_bits_br_mask; // @[util.scala:126:51] wire _exe_uop_valid_T_1 = \|_exe_uop_valid_T; // @[util.scala:126:{51,59}] wire _exe_uop_valid_T_2 = _exe_uop_valid_T_1 \| io_kill; // @[util.scala:61:61, :126:59] wire _exe_uop_valid_T_3 = ~_exe_uop_valid_T_2; // @[util.scala:61:61] wire _exe_uop_valid_T_4 = rrd_uop_valid & _exe_uop_valid_T_3; // @[execution-unit.scala:95:20, :99:{34,37}] wire [11:0] _exe_uop_bits_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] exe_uop_bits_out_br_mask; // @[util.scala:104:23] wire [11:0] _exe_uop_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27] assign _exe_uop_bits_out_br_mask_T_1 = rrd_uop_bits_br_mask & _exe_uop_bits_out_br_mask_T; // @[util.scala:93:{25,27}] assign exe_uop_bits_out_br_mask = _exe_uop_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire _GEN_0 = arb_uop_bits_lrs1_rtype == 2'h0; // @[execution-unit.scala:92:20, :121:72] wire _io_arb_irf_reqs_0_valid_T; // @[execution-unit.scala:121:72] assign _io_arb_irf_reqs_0_valid_T = _GEN_0; // @[execution-unit.scala:121:72] wire _arb_rebusied_prs1_T; // @[execution-unit.scala:128:51] assign _arb_rebusied_prs1_T = _GEN_0; // @[execution-unit.scala:121:72, :128:51] wire _io_arb_irf_reqs_0_valid_T_1 = arb_uop_valid & _io_arb_irf_reqs_0_valid_T; // @[execution-unit.scala:92:20, :121:{45,72}] wire _io_arb_irf_reqs_0_valid_T_2 = ~arb_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:92:20, :121:86] assign _io_arb_irf_reqs_0_valid_T_3 = _io_arb_irf_reqs_0_valid_T_1 & _io_arb_irf_reqs_0_valid_T_2; // @[execution-unit.scala:121:{45,83,86}] assign io_arb_irf_reqs_0_valid_0 = _io_arb_irf_reqs_0_valid_T_3; // @[execution-unit.scala:121:83, :492:7] wire _GEN_1 = arb_uop_bits_lrs2_rtype == 2'h0; // @[execution-unit.scala:92:20, :125:74] wire _io_arb_irf_reqs_1_valid_T; // @[execution-unit.scala:125:74] assign _io_arb_irf_reqs_1_valid_T = _GEN_1; // @[execution-unit.scala:125:74] wire _arb_rebusied_prs2_T; // @[execution-unit.scala:129:51] assign _arb_rebusied_prs2_T = _GEN_1; // @[execution-unit.scala:125:74, :129:51] wire _io_arb_irf_reqs_1_valid_T_1 = arb_uop_valid & _io_arb_irf_reqs_1_valid_T; // @[execution-unit.scala:92:20, :125:{47,74}] wire _io_arb_irf_reqs_1_valid_T_2 = ~arb_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:92:20, :125:88] assign _io_arb_irf_reqs_1_valid_T_3 = _io_arb_irf_reqs_1_valid_T_1 & _io_arb_irf_reqs_1_valid_T_2; // @[execution-unit.scala:125:{47,85,88}] assign io_arb_irf_reqs_1_valid_0 = _io_arb_irf_reqs_1_valid_T_3; // @[execution-unit.scala:125:85, :492:7] wire _GEN_2 = io_arb_rebusys_0_valid & io_arb_rebusys_0_bits_rebusy; // @[execution-unit.scala:118:39] wire _arb_rebusied_prs1_T_1; // @[execution-unit.scala:118:39] assign _arb_rebusied_prs1_T_1 = _GEN_2; // @[execution-unit.scala:118:39] wire _arb_rebusied_prs2_T_1; // @[execution-unit.scala:118:39] assign _arb_rebusied_prs2_T_1 = _GEN_2; // @[execution-unit.scala:118:39] wire _arb_rebusied_prs1_T_2 = io_arb_rebusys_0_bits_uop_pdst == arb_uop_bits_prs1; // @[execution-unit.scala:92:20, :118:75] wire _arb_rebusied_prs1_T_3 = _arb_rebusied_prs1_T_1 & _arb_rebusied_prs1_T_2; // @[execution-unit.scala:118:{39,56,75}] wire arb_rebusied_prs1 = _arb_rebusied_prs1_T & _arb_rebusied_prs1_T_3; // @[execution-unit.scala:118:56, :128:{51,62}] wire _arb_rebusied_prs2_T_2 = io_arb_rebusys_0_bits_uop_pdst == arb_uop_bits_prs2; // @[execution-unit.scala:92:20, :118:75] wire _arb_rebusied_prs2_T_3 = _arb_rebusied_prs2_T_1 & _arb_rebusied_prs2_T_2; // @[execution-unit.scala:118:{39,56,75}] wire _arb_rebusied_prs2_T_4 = _arb_rebusied_prs2_T & _arb_rebusied_prs2_T_3; // @[execution-unit.scala:118:56, :129:{51,62}] wire arb_rebusied_prs2 = _arb_rebusied_prs2_T_4; // @[execution-unit.scala:129:{62,93}] wire arb_rebusied = arb_rebusied_prs1 \| arb_rebusied_prs2; // @[execution-unit.scala:128:62, :129:93, :130:45] reg [63:0] exe_rs1_data; // @[execution-unit.scala:133:25] wire [63:0] exe_int_req_rs1_data = exe_rs1_data; // @[execution-unit.scala:133:25, :547:25] reg [63:0] exe_rs2_data; // @[execution-unit.scala:134:25] wire [63:0] exe_int_req_rs2_data = exe_rs2_data; // @[execution-unit.scala:134:25, :547:25] wire _hits_T = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_0_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_0 = io_rrd_irf_bypasses_0_valid & _hits_T; // @[execution-unit.scala:113:{55,62}] wire _hits_T_1 = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_1_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_1 = io_rrd_irf_bypasses_1_valid & _hits_T_1; // @[execution-unit.scala:113:{55,62}] wire _hits_T_2 = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_2_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_2 = io_rrd_irf_bypasses_2_valid & _hits_T_2; // @[execution-unit.scala:113:{55,62}] wire _T_1 = hits_0 \| hits_1; // @[execution-unit.scala:113:55, :114:19] wire rs1_hit = _T_1 \| hits_2; // @[execution-unit.scala:113:55, :114:19] wire [63:0] rs1_data = _T_1 \| hits_2 ? (hits_0 ? io_rrd_irf_bypasses_0_bits_data : 64'h0) \| (hits_1 ? io_rrd_irf_bypasses_1_bits_data : 64'h0) \| (hits_2 ? io_rrd_irf_bypasses_2_bits_data : 64'h0) : io_rrd_irf_resps_0; // @[Mux.scala:30:73] wire _exe_rs1_data_T = &rrd_uop_bits_lrs1_rtype; // @[execution-unit.scala:95:20, :137:47] wire [63:0] _exe_rs1_data_T_1 = _exe_rs1_data_T ? 64'h0 : rs1_data; // @[execution-unit.scala:114:28, :137:{22,47}] wire _hits_T_3 = rrd_uop_bits_prs2 == io_rrd_irf_bypasses_0_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_0_1 = io_rrd_irf_bypasses_0_valid & _hits_T_3; // @[execution-unit.scala:113:{55,62}] wire _hits_T_4 = rrd_uop_bits_prs2 == io_rrd_irf_bypasses_1_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_1_1 = io_rrd_irf_bypasses_1_valid & _hits_T_4; // @[execution-unit.scala:113:{55,62}] wire _hits_T_5 = rrd_uop_bits_prs2 == io_rrd_irf_bypasses_2_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_2_1 = io_rrd_irf_bypasses_2_valid & _hits_T_5; // @[execution-unit.scala:113:{55,62}] wire _T_18 = hits_0_1 \| hits_1_1; // @[execution-unit.scala:113:55, :114:19] wire rs2_hit = _T_18 \| hits_2_1; // @[execution-unit.scala:113:55, :114:19] wire [63:0] rs2_data = _T_18 \| hits_2_1 ? (hits_0_1 ? io_rrd_irf_bypasses_0_bits_data : 64'h0) \| (hits_1_1 ? io_rrd_irf_bypasses_1_bits_data : 64'h0) \| (hits_2_1 ? io_rrd_irf_bypasses_2_bits_data : 64'h0) : io_rrd_irf_resps_1; // @[Mux.scala:30:73]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w4_d3_i0_31( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_286 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_287 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_288 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_289 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid \|\| io.clear \|\| io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 \|\| rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_\|\|_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_\|\|_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready \|\| agen_ready \|\| dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }	module IssueSlot_22( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire rebusied_prs1 = 1'h0; // @[issue-slot.scala:92:31] wire rebusied_prs2 = 1'h0; // @[issue-slot.scala:93:31] wire rebusied = 1'h0; // @[issue-slot.scala:94:32] wire prs1_rebusys_0 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_0 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] next_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] _next_uop_iw_p1_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] wire _iss_ready_T_6 = slot_uop_prs3_busy; // @[issue-slot.scala:56:21, :136:131] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File TileClockGater.scala: package chipyard.clocking import chisel3._ import chisel3.util._ import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ /* This node adds clock gating control registers. * If deploying on a platform which does not support clock gating, deasserting the enable * flag will generate the registers, preserving the same memory map and behavior, but will not * generate any gaters / class TileClockGater(address: BigInt, beatBytes: Int)(implicit p: Parameters, valName: ValName) extends LazyModule { val device = new SimpleDevice(s"clock-gater", Nil) val clockNode = ClockGroupIdentityNode() val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes) lazy val module = new LazyModuleImp(this) { val sources = clockNode.in.head._1.member.data.toSeq val sinks = clockNode.out.head._1.member.elements.toSeq val nSinks = sinks.size val regs = (0 until nSinks).map({i => val sinkName = sinks(i)._1 val reg = withReset(sources(i).reset) { Module(new AsyncResetRegVec(w=1, init=1)) } if (sinkName.contains("tile")) { println(s"${(address+i4).toString(16)}: Tile $sinkName clock gate") sinks(i)._2.clock := ClockGate(sources(i).clock, reg.io.q.asBool) sinks(i)._2.reset := sources(i).reset } else { sinks(i)._2 := sources(i) } reg }) tlNode.regmap((0 until nSinks).map({i => i4 -> Seq(RegField.rwReg(1, regs(i).io)) }): _) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. / object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct / cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) / Filter out any cases identical to the default / val simple = cases.filter { case (k, v) => !default.isLit \|\| !v.isLit \|\| v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2simple.size) { /* The dense encoding case uses a Vec / val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { / The sparse encoding case uses switch / val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TileClockGater( // @[TileClockGater.scala:27:25] input clock, // @[TileClockGater.scala:27:25] input reset, // @[TileClockGater.scala:27:25] output auto_clock_gater_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_clock_gater_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_clock_gater_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_clock_gater_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_clock_gater_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_clock_gater_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_clock_gater_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_clock_gater_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_clock_gater_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_clock_gater_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_reset // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_clock_gater_in_1_a_valid_0 = auto_clock_gater_in_1_a_valid; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_a_bits_opcode_0 = auto_clock_gater_in_1_a_bits_opcode; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_a_bits_param_0 = auto_clock_gater_in_1_a_bits_param; // @[TileClockGater.scala:27:25] wire [1:0] auto_clock_gater_in_1_a_bits_size_0 = auto_clock_gater_in_1_a_bits_size; // @[TileClockGater.scala:27:25] wire [10:0] auto_clock_gater_in_1_a_bits_source_0 = auto_clock_gater_in_1_a_bits_source; // @[TileClockGater.scala:27:25] wire [20:0] auto_clock_gater_in_1_a_bits_address_0 = auto_clock_gater_in_1_a_bits_address; // @[TileClockGater.scala:27:25] wire [7:0] auto_clock_gater_in_1_a_bits_mask_0 = auto_clock_gater_in_1_a_bits_mask; // @[TileClockGater.scala:27:25] wire [63:0] auto_clock_gater_in_1_a_bits_data_0 = auto_clock_gater_in_1_a_bits_data; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_a_bits_corrupt_0 = auto_clock_gater_in_1_a_bits_corrupt; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_ready_0 = auto_clock_gater_in_1_d_ready; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_0_member_allClocks_uncore_clock_0 = auto_clock_gater_in_0_member_allClocks_uncore_clock; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_0_member_allClocks_uncore_reset_0 = auto_clock_gater_in_0_member_allClocks_uncore_reset; // @[TileClockGater.scala:27:25] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] clock_gaterIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] clock_gaterIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_clock_gater_in_1_d_bits_sink = 1'h0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_bits_denied = 1'h0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_bits_corrupt = 1'h0; // @[TileClockGater.scala:27:25] wire clock_gaterIn_1_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire clock_gaterIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire clock_gaterIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire clock_gaterIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_clock_gater_in_1_d_bits_param = 2'h0; // @[TileClockGater.scala:27:25] wire clock_gaterIn_1_a_ready; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire clock_gaterIn_1_a_valid = auto_clock_gater_in_1_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_a_bits_opcode = auto_clock_gater_in_1_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_a_bits_param = auto_clock_gater_in_1_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_a_bits_size = auto_clock_gater_in_1_a_bits_size_0; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_1_a_bits_source = auto_clock_gater_in_1_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] clock_gaterIn_1_a_bits_address = auto_clock_gater_in_1_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] clock_gaterIn_1_a_bits_mask = auto_clock_gater_in_1_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] clock_gaterIn_1_a_bits_data = auto_clock_gater_in_1_a_bits_data_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_a_bits_corrupt = auto_clock_gater_in_1_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_ready = auto_clock_gater_in_1_d_ready_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] clock_gaterIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire clock_gaterIn_member_allClocks_uncore_clock = auto_clock_gater_in_0_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clock_gaterOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clock_gaterIn_member_allClocks_uncore_reset = auto_clock_gater_in_0_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clock_gaterOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire auto_clock_gater_in_1_a_ready_0; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_d_bits_opcode_0; // @[TileClockGater.scala:27:25] wire [1:0] auto_clock_gater_in_1_d_bits_size_0; // @[TileClockGater.scala:27:25] wire [10:0] auto_clock_gater_in_1_d_bits_source_0; // @[TileClockGater.scala:27:25] wire [63:0] auto_clock_gater_in_1_d_bits_data_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_valid_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_out_member_allClocks_uncore_clock_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_out_member_allClocks_uncore_reset_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_clock_0 = clock_gaterOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_gater_out_member_allClocks_uncore_reset_0 = clock_gaterOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clock_gaterOut_member_allClocks_uncore_clock = clock_gaterIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clock_gaterOut_member_allClocks_uncore_reset = clock_gaterIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_clock_gater_in_1_a_ready_0 = clock_gaterIn_1_a_ready; // @[MixedNode.scala:551:17] wire in_valid = clock_gaterIn_1_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = clock_gaterIn_1_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = clock_gaterIn_1_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = clock_gaterIn_1_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = clock_gaterIn_1_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = clock_gaterIn_1_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_clock_gater_in_1_d_valid_0 = clock_gaterIn_1_d_valid; // @[MixedNode.scala:551:17] assign auto_clock_gater_in_1_d_bits_opcode_0 = clock_gaterIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_clock_gater_in_1_d_bits_size_0 = clock_gaterIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_clock_gater_in_1_d_bits_source_0 = clock_gaterIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_clock_gater_in_1_d_bits_data_0 = clock_gaterIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = clock_gaterIn_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [17:0] _in_bits_index_T = clock_gaterIn_1_a_bits_address[20:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _clock_gaterIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign clock_gaterIn_1_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] wire _out_T_8 = _out_T_7; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1_0 = _out_T_8; // @[MuxLiteral.scala:49:48] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_3 = _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_4 = _out_out_bits_data_T_1 & _out_out_bits_data_T_3; // @[MuxLiteral.scala:49:10] assign out_bits_data = {63'h0, _out_out_bits_data_T_4}; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_d_bits_size = clock_gaterIn_d_bits_d_size; // @[Edges.scala:792:17] assign clock_gaterIn_1_d_bits_source = clock_gaterIn_d_bits_d_source; // @[Edges.scala:792:17] assign clock_gaterIn_1_d_bits_opcode = {2'h0, _clock_gaterIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_61 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (clock_gaterIn_1_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (clock_gaterIn_1_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (clock_gaterIn_1_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (clock_gaterIn_1_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (clock_gaterIn_1_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (clock_gaterIn_1_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (clock_gaterIn_1_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (clock_gaterIn_1_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (clock_gaterIn_1_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (clock_gaterIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (clock_gaterIn_1_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (clock_gaterIn_1_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (clock_gaterIn_1_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (clock_gaterIn_1_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (clock_gaterIn_1_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (clock_gaterIn_1_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i1 regs_0 ( // @[TileClockGater.scala:33:53] .clock (clock), .reset (clock_gaterIn_member_allClocks_uncore_reset), // @[MixedNode.scala:551:17] .io_d (_out_T_2), // @[RegisterRouter.scala:87:24] .io_q (_out_T_7), .io_en (out_f_woready) // @[RegisterRouter.scala:87:24] ); // @[TileClockGater.scala:33:53] assign auto_clock_gater_in_1_a_ready = auto_clock_gater_in_1_a_ready_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_valid = auto_clock_gater_in_1_d_valid_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_opcode = auto_clock_gater_in_1_d_bits_opcode_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_size = auto_clock_gater_in_1_d_bits_size_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_source = auto_clock_gater_in_1_d_bits_source_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_data = auto_clock_gater_in_1_d_bits_data_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_clock = auto_clock_gater_out_member_allClocks_uncore_clock_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_reset = auto_clock_gater_out_member_allClocks_uncore_reset_0; // @[TileClockGater.scala:27:25] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) \| wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /* @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File TLB.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps case object ASIdBits extends Field[Int](0) case object VMIdBits extends Field[Int](0) /* =SFENCE= * rs1 rs2 * {{{ * 0 0 -> flush All * 0 1 -> flush by ASID * 1 1 -> flush by ADDR * 1 0 -> flush by ADDR and ASID * }}} * {{{ * If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. * If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered. * If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces. * If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. * }}} / class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { val rs1 = Bool() val rs2 = Bool() val addr = UInt(vaddrBits.W) val asid = UInt((asIdBits max 1).W) // TODO zero-width val hv = Bool() val hg = Bool() } class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) { /* request address from CPU. / val vaddr = UInt(vaddrBitsExtended.W) /* don't lookup TLB, bypass vaddr as paddr / val passthrough = Bool() /* granularity / val size = UInt(log2Ceil(lgMaxSize + 1).W) /* memory command. / val cmd = Bits(M_SZ.W) val prv = UInt(PRV.SZ.W) /* virtualization mode / val v = Bool() } class TLBExceptions extends Bundle { val ld = Bool() val st = Bool() val inst = Bool() } class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) { // lookup responses val miss = Bool() /* physical address / val paddr = UInt(paddrBits.W) val gpa = UInt(vaddrBitsExtended.W) val gpa_is_pte = Bool() /* page fault exception / val pf = new TLBExceptions /* guest page fault exception / val gf = new TLBExceptions /* access exception / val ae = new TLBExceptions /* misaligned access exception / val ma = new TLBExceptions /* if this address is cacheable / val cacheable = Bool() /* if caches must allocate this address / val must_alloc = Bool() /* if this address is prefetchable for caches/ val prefetchable = Bool() /* size/cmd of request that generated this response/ val size = UInt(log2Ceil(lgMaxSize + 1).W) val cmd = UInt(M_SZ.W) } class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) { val ppn = UInt(ppnBits.W) /* pte.u user / val u = Bool() /* pte.g global / val g = Bool() /* access exception. * D$ -> PTW -> TLB AE * Alignment failed. / val ae_ptw = Bool() val ae_final = Bool() val ae_stage2 = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* supervisor write / val sw = Bool() /* supervisor execute / val sx = Bool() /* supervisor read / val sr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor excute / val hx = Bool() /* hypervisor read / val hr = Bool() /* prot_w / val pw = Bool() /* prot_x / val px = Bool() /* prot_r / val pr = Bool() /* PutPartial / val ppp = Bool() /* AMO logical / val pal = Bool() /* AMO arithmetic / val paa = Bool() /* get/put effects / val eff = Bool() /* cacheable / val c = Bool() /* fragmented_superpage support / val fragmented_superpage = Bool() } /* basic cell for TLB data / class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) { require(nSectors == 1 \|\| !superpage) require(!superpageOnly \|\| superpage) val level = UInt(log2Ceil(pgLevels).W) /* use vpn as tag / val tag_vpn = UInt(vpnBits.W) /* tag in vitualization mode / val tag_v = Bool() /* entry data / val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W)) /* valid bit / val valid = Vec(nSectors, Bool()) /* returns all entry data in this entry / def entry_data = data.map(_.asTypeOf(new TLBEntryData)) /* returns the index of sector / private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0) /* returns the entry data matched with this vpn/ def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData)) /* returns whether a sector hits / def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual) /* returns whether tag matches vpn / def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual) /* returns hit signal / def hit(vpn: UInt, virtual: Bool): Bool = { if (superpage && usingVM) { var tagMatch = valid.head && (tag_v === virtual) for (j <- 0 until pgLevels) { val base = (pgLevels - 1 - j) pgLevelBits val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0) val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B tagMatch = tagMatch && (ignore \|\| (tag_vpn ^ vpn)(base + n - 1, base) === 0.U) } tagMatch } else { val idx = sectorIdx(vpn) valid(idx) && sectorTagMatch(vpn, virtual) } } /** returns the ppn of the input TLBEntryData / def ppn(vpn: UInt, data: TLBEntryData) = { val supervisorVPNBits = pgLevels pgLevelBits if (superpage && usingVM) { var res = data.ppn >> pgLevelBits(pgLevels - 1) for (j <- 1 until pgLevels) { val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B res = Cat(res, (Mux(ignore, vpn, 0.U) \| data.ppn)(supervisorVPNBits - jpgLevelBits - 1, supervisorVPNBits - (j + 1)pgLevelBits)) } res } else { data.ppn } } /* does the refill * * find the target entry with vpn tag * and replace the target entry with the input entry data / def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = { this.tag_vpn := vpn this.tag_v := virtual this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0) val idx = sectorIdx(vpn) valid(idx) := true.B data(idx) := entry.asUInt } def invalidate(): Unit = { valid.foreach(_ := false.B) } def invalidate(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual) { v := false.B } } def invalidateVPN(vpn: UInt, virtual: Bool): Unit = { if (superpage) { when (hit(vpn, virtual)) { invalidate() } } else { when (sectorTagMatch(vpn, virtual)) { for (((v, e), i) <- (valid zip entry_data).zipWithIndex) when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B } } } // For fragmented superpage mappings, we assume the worst (largest) // case, and zap entries whose most-significant VPNs match when (((tag_vpn ^ vpn) >> (pgLevelBits (pgLevels - 1))) === 0.U) { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && e.fragmented_superpage) { v := false.B } } } def invalidateNonGlobal(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && !e.g) { v := false.B } } } /** TLB config * * @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]] * @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]] * @param nSectors the number of ways in a single PTE TLBEntry * @param nSuperpageEntries the number of SuperpageEntries / case class TLBConfig( nSets: Int, nWays: Int, nSectors: Int = 4, nSuperpageEntries: Int = 4) /* =Overview= * [[TLB]] is a TLB template which contains PMA logic and PMP checker. * * TLB caches PTE and accelerates the address translation process. * When tlb miss happens, ask PTW(L2TLB) for Page Table Walk. * Perform PMP and PMA check during the translation and throw exception if there were any. * * ==Cache Structure== * - Sectored Entry (PTE) * - set-associative or direct-mapped * - nsets = [[TLBConfig.nSets]] * - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]] * - PTEEntry( sectors = [[TLBConfig.nSectors]] ) * - LRU(if set-associative) * * - Superpage Entry(superpage PTE) * - fully associative * - nsets = [[TLBConfig.nSuperpageEntries]] * - PTEEntry(sectors = 1) * - PseudoLRU * * - Special Entry(PTE across PMP) * - nsets = 1 * - PTEEntry(sectors = 1) * * ==Address structure== * {{{ * \|vaddr \| * \|ppn/vpn \| pgIndex \| * \| \| \| * \| \|nSets \|nSector \| \|}}} * * ==State Machine== * {{{ * s_ready: ready to accept request from CPU. * s_request: when L1TLB(this) miss, send request to PTW(L2TLB), . * s_wait: wait for PTW to refill L1TLB. * s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}} * * ==PMP== * pmp check * - special_entry: always check * - other entry: check on refill * * ==Note== * PMA consume diplomacy parameter generate physical memory address checking logic * * Boom use Rocket ITLB, and its own DTLB. * * Accelerators:{{{ * sha3: DTLB * gemmini: DTLB * hwacha: DTLB2+ITLB}}} @param instruction true for ITLB, false for DTLB * @param lgMaxSize @todo seems granularity * @param cfg [[TLBConfig]] * @param edge collect SoC metadata. / class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { override def desiredName = if (instruction) "ITLB" else "DTLB" val io = IO(new Bundle { /* request from Core / val req = Flipped(Decoupled(new TLBReq(lgMaxSize))) /* response to Core / val resp = Output(new TLBResp(lgMaxSize)) /* SFence Input / val sfence = Flipped(Valid(new SFenceReq)) /* IO to PTW / val ptw = new TLBPTWIO /* suppress a TLB refill, one cycle after a miss / val kill = Input(Bool()) }) io.ptw.customCSRs := DontCare val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits) /* index for sectored_Entry / val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) /* TLB Entry / val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) /* Superpage Entry / val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true))) /* Special Entry * * If PMP granularity is less than page size, thus need additional "special" entry manage PMP. / val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false))) def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries def all_entries = ordinary_entries ++ special_entry def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) val state = RegInit(s_ready) // use vpn as refill_tag val r_refill_tag = Reg(UInt(vpnBits.W)) val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W)) val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W)) val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W))) val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W))) val r_vstage1_en = Reg(Bool()) val r_stage2_en = Reg(Bool()) val r_need_gpa = Reg(Bool()) val r_gpa_valid = Reg(Bool()) val r_gpa = Reg(UInt(vaddrBits.W)) val r_gpa_vpn = Reg(UInt(vpnBits.W)) val r_gpa_is_pte = Reg(Bool()) /* privilege mode / val priv = io.req.bits.prv val priv_v = usingHypervisor.B && io.req.bits.v val priv_s = priv(0) // user mode and supervisor mode val priv_uses_vm = priv <= PRV.S.U val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1) /* VS-stage translation enable / val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1) /* G-stage translation enable / val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1) /* Enable Virtual Memory when: * 1. statically configured * 1. satp highest bits enabled * i. RV32: * - 0 -> Bare * - 1 -> SV32 * i. RV64: * - 0000 -> Bare * - 1000 -> SV39 * - 1001 -> SV48 * - 1010 -> SV57 * - 1011 -> SV64 * 1. In virtualization mode, vsatp highest bits enabled * 1. priv mode in U and S. * 1. in H & M mode, disable VM. * 1. no passthrough(micro-arch defined.) * * @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register * @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp) / val vm_enabled = (stage1_en \|\| stage2_en) && priv_uses_vm && !io.req.bits.passthrough // flush guest entries on vsatp.MODE Bare <-> SvXX transitions val v_entries_use_stage1 = RegInit(false.B) val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough // share a single physical memory attribute checker (unshare if critical path) val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) /* refill signal / val do_refill = usingVM.B && io.ptw.resp.valid /* sfence invalidate refill / val invalidate_refill = state.isOneOf(s_request / don't care /, s_wait_invalidate) \|\| io.sfence.valid // PMP val mpu_ppn = Mux(do_refill, refill_ppn, Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val mpu_priv = Mux[UInt](usingVM.B && (do_refill \|\| io.req.bits.passthrough / PTW /), PRV.S.U, Cat(io.ptw.status.debug, priv)) val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size pmp.io.pmp := (io.ptw.pmp: Seq[PMP]) pmp.io.prv := mpu_priv val pma = Module(new PMAChecker(edge.manager)(p)) pma.io.paddr := mpu_physaddr // todo: using DataScratchpad doesn't support cacheable. val cacheable = pma.io.resp.cacheable && (instruction \|\| !usingDataScratchpad).B val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous // In M mode, if access DM address(debug module program buffer) val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B) val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w val prot_pp = pma.io.resp.pp val prot_al = pma.io.resp.al val prot_aa = pma.io.resp.aa val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x val prot_eff = pma.io.resp.eff // hit check val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v)) val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v)) val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v)) val real_hits = hitsVec.asUInt val hits = Cat(!vm_enabled, real_hits) // use ptw response to refill // permission bit arrays when (do_refill) { val pte = io.ptw.resp.bits.pte val refill_v = r_vstage1_en \|\| r_stage2_en val newEntry = Wire(new TLBEntryData) newEntry.ppn := pte.ppn newEntry.c := cacheable newEntry.u := pte.u newEntry.g := pte.g && pte.v newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw newEntry.ae_final := io.ptw.resp.bits.ae_final newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en newEntry.pf := io.ptw.resp.bits.pf newEntry.gf := io.ptw.resp.bits.gf newEntry.hr := io.ptw.resp.bits.hr newEntry.hw := io.ptw.resp.bits.hw newEntry.hx := io.ptw.resp.bits.hx newEntry.sr := pte.sr() newEntry.sw := pte.sw() newEntry.sx := pte.sx() newEntry.pr := prot_r newEntry.pw := prot_w newEntry.px := prot_x newEntry.ppp := prot_pp newEntry.pal := prot_al newEntry.paa := prot_aa newEntry.eff := prot_eff newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage // refill special_entry when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) { special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)) }.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) { val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr) for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) { e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry) when (invalidate_refill) { e.invalidate() } } // refill sectored_hit }.otherwise { val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) { when (!r_sectored_hit.valid) { e.invalidate() } e.insert(r_refill_tag, refill_v, 0.U, newEntry) when (invalidate_refill) { e.invalidate() } } } r_gpa_valid := io.ptw.resp.bits.gpa.valid r_gpa := io.ptw.resp.bits.gpa.bits r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte } // get all entries data. val entries = all_entries.map(_.getData(vpn)) val normal_entries = entries.take(ordinary_entries.size) // parallel query PPN from [[all_entries]], if VM not enabled return VPN instead val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0)) val nPhysicalEntries = 1 + special_entry.size // generally PTW misaligned load exception. val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt) val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt) val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt) val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt) val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) // if in hypervisor/machine mode, cannot read/write user entries. // if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)" val priv_rw_ok = Mux(!priv_s \|\| sum, entries.map(_.u).asUInt, 0.U) \| Mux(priv_s, ~entries.map(_.u).asUInt, 0.U) // if in hypervisor/machine mode, other than user pages, all pages are executable. // if in superviosr/user mode, only user page can execute. val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt) val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) \| entries.map(_.ae_stage2).asUInt) val mxr = io.ptw.status.mxr \| Mux(priv_v, io.ptw.gstatus.mxr, false.B) // "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)" val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt \| Mux(mxr, entries.map(_.sx).asUInt, 0.U))) \| stage1_bypass) val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) \| stage1_bypass) val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) \| stage1_bypass) val stage2_bypass = Fill(entries.size, !stage2_en) val hr_array = Cat(true.B, entries.map(_.hr).asUInt \| Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) \| stage2_bypass) val hw_array = Cat(true.B, entries.map(_.hw).asUInt \| stage2_bypass) val hx_array = Cat(true.B, entries.map(_.hx).asUInt \| stage2_bypass) // These array is for each TLB entries. // user mode can read: PMA OK, TLB OK, AE OK val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array \| final_ae_array) // put effect val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt) // cacheable val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt) // put partial val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt) // atomic arithmetic val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt) // atomic logic val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt) val ppp_array_if_cached = ppp_array \| c_array val paa_array_if_cached = paa_array \| (if(usingAtomicsInCache) c_array else 0.U) val pal_array_if_cached = pal_array \| (if(usingAtomicsInCache) c_array else 0.U) val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt) // vaddr misaligned: vaddr[1:0]=b00 val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR def badVA(guestPA: Boolean): Bool = { val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels val extraBits = if (guestPA) hypervisorExtraAddrBits else 0 val signed = !guestPA val nPgLevelChoices = pgLevels - minPgLevels + 1 val minVAddrBits = pgIdxBits + minPgLevels pgLevelBits + extraBits (for (i <- 0 until nPgLevelChoices) yield { val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U val maskedVAddr = io.req.bits.vaddr & mask additionalPgLevels === i.U && !(maskedVAddr === 0.U \|\| signed.B && maskedVAddr === mask) }).orR } val bad_gpa = if (!usingHypervisor) false.B else vm_enabled && !stage1_en && badVA(true) val bad_va = if (!usingVM \|\| (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B else vm_enabled && stage1_en && badVA(false) val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC) val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd) val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd) val cmd_put_partial = io.req.bits.cmd === M_PWR val cmd_read = isRead(io.req.bits.cmd) val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX val cmd_write = isWrite(io.req.bits.cmd) val cmd_write_perms = cmd_write \|\| io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions val lrscAllowed = Mux((usingDataScratchpad \|\| usingAtomicsOnlyForIO).B, 0.U, c_array) val ae_array = Mux(misaligned, eff_array, 0.U) \| Mux(cmd_lrsc, ~lrscAllowed, 0.U) // access exception needs SoC information from PMA val ae_ld_array = Mux(cmd_read, ae_array \| ~pr_array, 0.U) val ae_st_array = Mux(cmd_write_perms, ae_array \| ~pw_array, 0.U) \| Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) \| Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U) val must_alloc_array = Mux(cmd_put_partial, ~ppp_array, 0.U) \| Mux(cmd_amo_logical, ~pal_array, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array, 0.U) \| Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U) val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_inst_array = ((~x_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_inst_array = Mux(priv_v, (~hx_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gpa_hits = { val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array \| gf_st_array val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) \| Fill(all_entries.size, !vstage1_en) hit_mask \| ~need_gpa_mask(all_entries.size-1, 0) } val tlb_hit_if_not_gpa_miss = real_hits.orR val tlb_hit = (real_hits & gpa_hits).orR // leads to s_request val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru") val superpage_plru = new PseudoLRU(superpage_entries.size) when (io.req.valid && vm_enabled) { // replace when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) } when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) } } // Superpages create the possibility that two entries in the TLB may match. // This corresponds to a software bug, but we can't return complete garbage; // we must return either the old translation or the new translation. This // isn't compatible with the Mux1H approach. So, flush the TLB and report // a miss on duplicate entries. val multipleHits = PopCountAtLeast(real_hits, 2) // only pull up req.ready when this is s_ready state. io.req.ready := state === s_ready // page fault io.resp.pf.ld := (bad_va && cmd_read) \|\| (pf_ld_array & hits).orR io.resp.pf.st := (bad_va && cmd_write_perms) \|\| (pf_st_array & hits).orR io.resp.pf.inst := bad_va \|\| (pf_inst_array & hits).orR // guest page fault io.resp.gf.ld := (bad_gpa && cmd_read) \|\| (gf_ld_array & hits).orR io.resp.gf.st := (bad_gpa && cmd_write_perms) \|\| (gf_st_array & hits).orR io.resp.gf.inst := bad_gpa \|\| (gf_inst_array & hits).orR // access exception io.resp.ae.ld := (ae_ld_array & hits).orR io.resp.ae.st := (ae_st_array & hits).orR io.resp.ae.inst := (~px_array & hits).orR // misaligned io.resp.ma.ld := misaligned && cmd_read io.resp.ma.st := misaligned && cmd_write io.resp.ma.inst := false.B // this is up to the pipeline to figure out io.resp.cacheable := (c_array & hits).orR io.resp.must_alloc := (must_alloc_array & hits).orR io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB \|\| m.supportsHint).B io.resp.miss := do_refill \|\| vsatp_mode_mismatch \|\| tlb_miss \|\| multipleHits io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) io.resp.size := io.req.bits.size io.resp.cmd := io.req.bits.cmd io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte io.resp.gpa := { val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits) val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0)) Cat(page, offset) } io.ptw.req.valid := state === s_request io.ptw.req.bits.valid := !io.kill io.ptw.req.bits.bits.addr := r_refill_tag io.ptw.req.bits.bits.vstage1 := r_vstage1_en io.ptw.req.bits.bits.stage2 := r_stage2_en io.ptw.req.bits.bits.need_gpa := r_need_gpa if (usingVM) { when(io.ptw.req.fire && io.ptw.req.bits.valid) { r_gpa_valid := false.B r_gpa_vpn := r_refill_tag } val sfence = io.sfence.valid // this is [[s_ready]] // handle miss/hit at the first cycle. // if miss, request PTW(L2TLB). when (io.req.fire && tlb_miss) { state := s_request r_refill_tag := vpn r_need_gpa := tlb_hit_if_not_gpa_miss r_vstage1_en := vstage1_en r_stage2_en := stage2_en r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way) r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx)) r_sectored_hit.valid := sector_hits.orR r_sectored_hit.bits := OHToUInt(sector_hits) r_superpage_hit.valid := superpage_hits.orR r_superpage_hit.bits := OHToUInt(superpage_hits) } // Handle SFENCE.VMA when send request to PTW. // SFENCE.VMA io.ptw.req.ready kill // ? ? 1 // 0 0 0 // 0 1 0 -> s_wait // 1 0 0 -> s_wait_invalidate // 1 0 0 -> s_ready when (state === s_request) { // SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle. when (sfence) { state := s_ready } // here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B) // fire -> s_wait when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) } // If CPU kills request(frontend.s2_redirect) when (io.kill) { state := s_ready } } // sfence in refill will results in invalidate when (state === s_wait && sfence) { state := s_wait_invalidate } // after CPU acquire response, go back to s_ready. when (io.ptw.resp.valid) { state := s_ready } // SFENCE processing logic. when (sfence) { assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn) for (e <- all_real_entries) { val hv = usingHypervisor.B && io.sfence.bits.hv val hg = usingHypervisor.B && io.sfence.bits.hg when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) } .elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) } .otherwise { e.invalidate(hv \|\| hg) } } } when(io.req.fire && vsatp_mode_mismatch) { all_real_entries.foreach(_.invalidate(true.B)) v_entries_use_stage1 := vstage1_en } when (multipleHits \|\| reset.asBool) { all_real_entries.foreach(_.invalidate()) } ccover(io.ptw.req.fire, "MISS", "TLB miss") ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy") ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill") ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB") ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID") ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line") ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID") ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc) /** Decides which entry to be replaced * * If there is a invalid entry, replace it with priorityencoder; * if not, replace the alt entry * * @return mask for TLBEntry replacement / def replacementEntry(set: Seq[TLBEntry], alt: UInt) = { val valids = set.map(_.valid.orR).asUInt Mux(valids.andR, alt, PriorityEncoder(~valids)) } } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r \|\| w \|\| x \|\| c \|\| a \|\| l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet \|\| m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull \|\| m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet \|\| m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull \|\| m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial \|\| m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB \|\| m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT \|\| m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical \|\| m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic \|\| m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ \|\| _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /* PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss / class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /* PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info / class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /* ptw access exception / val ae_ptw = Bool() /* final access exception / val ae_final = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* hypervisor read / val hr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor execute / val hx = Bool() /* PTE to refill L1TLB * * source: L2TLB / val pte = new PTE /* pte pglevel / val level = UInt(log2Ceil(pgLevels).W) /* fragmented_superpage support / val fragmented_superpage = Bool() /* homogeneous for both pma and pmp / val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /* IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) / class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /* PTW performance statistics / class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /* Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core / class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /* enable clock generated by ptw / val clock_enabled = Output(Bool()) } /* PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format / class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* global mapping / val g = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() /* valid bit / val v = Bool() /* return true if find a pointer to next level page table / def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /* return true if find a leaf PTE / def leaf(dummy: Int = 0) = v && (r \|\| (x && !w)) && a /* user read / def ur(dummy: Int = 0) = sr() && u /* user write/ def uw(dummy: Int = 0) = sw() && u /* user execute / def ux(dummy: Int = 0) = sx() && u /* supervisor read / def sr(dummy: Int = 0) = leaf() && r /* supervisor write / def sw(dummy: Int = 0) = leaf() && w && d /* supervisor execute / def sx(dummy: Int = 0) = leaf() && x /* full permission: writable and executable in user mode / def isFullPerm(dummy: Int = 0) = uw() && ux() } /* L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format / class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() } /* PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation / class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /* to n TLB / val requestor = Flipped(Vec(n, new TLBPTWIO)) /* to HellaCache / val mem = new HellaCacheIO /* to Core * * contains CSRs info and performance statistics / val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /* Arbiter to arbite request from n TLB / val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready \|\| l2_refill_wire \|\| arb.io.out.valid \|\| io.dpath.sfence.valid \|\| io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM \|\| !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /* current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} / val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /* tlb request / val r_req = Reg(new PTWReq) /* current selected way in arbitor / val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /* pte for 2-stage translation / val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /* 2-stage translation both enable / val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r \|\| tmp.w \|\| tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)pgLevelBits-1, (pgLevels-2-i)pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /* address send to mem for enquerry / val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) \| vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr / val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBitsi), r_req.addr(((pgLevelBitsi) min vpnBits)-1, 0).padTo(pgLevelBitsi))) } /* PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation / def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid \| UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 \|\| usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss \|\| io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /* the valid vec for the selected set(including n ways) / val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) \| mask g(way) := Mux(r_pte.g, g(way) \| mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) \|\| s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid \|\| (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req \|\| state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit \|\| (state =/= s_wait1) \|\| resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor \|\| pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous \|\| pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final \|\| !r_req.vstage1 \|\| aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa \|\| arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), aux_pte.ppn((pgLevels-i-1)pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req \|\| state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) \|\| (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 \|\| do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages \|\| aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf \|\| (pf && stage2) resp_hr := !stage2 \|\| (!pf && !gf && pte.ur()) resp_hw := !stage2 \|\| (!pf && !gf && pte.uw()) resp_hx := !stage2 \|\| (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), r_req.addr(((pgLevels-i-1)pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn / private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /* use hgatp and vpn to construct a new ppn / private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range / private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW */ trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } }	module DTLB_8( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input [1:0] io_req_bits_size, // @[TLB.scala:320:14] input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_status_zero2, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_mbe, // @[TLB.scala:320:14] input io_ptw_status_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_status_sxl, // @[TLB.scala:320:14] input [1:0] io_ptw_status_uxl, // @[TLB.scala:320:14] input io_ptw_status_sd_rv32, // @[TLB.scala:320:14] input [7:0] io_ptw_status_zero1, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_xs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_status_vs, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_ube, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_upie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_hie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_status_uie, // @[TLB.scala:320:14] input io_ptw_hstatus_spvp, // @[TLB.scala:320:14] input io_ptw_hstatus_spv, // @[TLB.scala:320:14] input io_ptw_hstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_debug, // @[TLB.scala:320:14] input io_ptw_gstatus_cease, // @[TLB.scala:320:14] input io_ptw_gstatus_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14] input io_ptw_gstatus_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14] input io_ptw_gstatus_v, // @[TLB.scala:320:14] input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14] input io_ptw_gstatus_mpv, // @[TLB.scala:320:14] input io_ptw_gstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_mbe, // @[TLB.scala:320:14] input io_ptw_gstatus_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14] input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14] input io_ptw_gstatus_tsr, // @[TLB.scala:320:14] input io_ptw_gstatus_tw, // @[TLB.scala:320:14] input io_ptw_gstatus_tvm, // @[TLB.scala:320:14] input io_ptw_gstatus_mxr, // @[TLB.scala:320:14] input io_ptw_gstatus_sum, // @[TLB.scala:320:14] input io_ptw_gstatus_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14] input io_ptw_gstatus_spp, // @[TLB.scala:320:14] input io_ptw_gstatus_mpie, // @[TLB.scala:320:14] input io_ptw_gstatus_ube, // @[TLB.scala:320:14] input io_ptw_gstatus_spie, // @[TLB.scala:320:14] input io_ptw_gstatus_upie, // @[TLB.scala:320:14] input io_ptw_gstatus_mie, // @[TLB.scala:320:14] input io_ptw_gstatus_hie, // @[TLB.scala:320:14] input io_ptw_gstatus_sie, // @[TLB.scala:320:14] input io_ptw_gstatus_uie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[TLB.scala:318:7] wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7] wire [6:0] hr_array = 7'h7F; // @[TLB.scala:524:21] wire [6:0] hw_array = 7'h7F; // @[TLB.scala:525:21] wire [6:0] hx_array = 7'h7F; // @[TLB.scala:526:21] wire [6:0] _must_alloc_array_T_8 = 7'h7F; // @[TLB.scala:596:19] wire [6:0] _gf_ld_array_T_1 = 7'h7F; // @[TLB.scala:600:50] wire [5:0] stage2_bypass = 6'h3F; // @[TLB.scala:523:27] wire [5:0] _hr_array_T_4 = 6'h3F; // @[TLB.scala:524:111] wire [5:0] _hw_array_T_1 = 6'h3F; // @[TLB.scala:525:55] wire [5:0] _hx_array_T_1 = 6'h3F; // @[TLB.scala:526:55] wire [5:0] _gpa_hits_hit_mask_T_4 = 6'h3F; // @[TLB.scala:606:88] wire [5:0] gpa_hits_hit_mask = 6'h3F; // @[TLB.scala:606:82] wire [5:0] _gpa_hits_T_1 = 6'h3F; // @[TLB.scala:607:16] wire [5:0] gpa_hits = 6'h3F; // @[TLB.scala:607:14] wire [2:0] _state_vec_WIRE_0 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_1 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_2 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_3 = 3'h0; // @[Replacement.scala:305:25] wire [6:0] _gf_ld_array_T_2 = 7'h0; // @[TLB.scala:600:46] wire [6:0] gf_ld_array = 7'h0; // @[TLB.scala:600:24] wire [6:0] _gf_st_array_T_1 = 7'h0; // @[TLB.scala:601:53] wire [6:0] gf_st_array = 7'h0; // @[TLB.scala:601:24] wire [6:0] _gf_inst_array_T = 7'h0; // @[TLB.scala:602:36] wire [6:0] gf_inst_array = 7'h0; // @[TLB.scala:602:26] wire [6:0] gpa_hits_need_gpa_mask = 7'h0; // @[TLB.scala:605:73] wire [6:0] _io_resp_gf_ld_T_1 = 7'h0; // @[TLB.scala:637:58] wire [6:0] _io_resp_gf_st_T_1 = 7'h0; // @[TLB.scala:638:65] wire [6:0] _io_resp_gf_inst_T = 7'h0; // @[TLB.scala:639:48] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr = 39'h0; // @[TLB.scala:318:7, :320:14] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h1; // @[TLB.scala:318:7] wire priv_uses_vm = 1'h1; // @[TLB.scala:372:27] wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64] wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_37 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire _priv_rw_ok_T = 1'h1; // @[TLB.scala:513:24] wire _priv_rw_ok_T_1 = 1'h1; // @[TLB.scala:513:32] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [5:0] _priv_rw_ok_T_6 = 6'h0; // @[TLB.scala:513:75] wire [5:0] _stage1_bypass_T = 6'h0; // @[TLB.scala:517:27] wire [5:0] stage1_bypass = 6'h0; // @[TLB.scala:517:61] wire [5:0] _gpa_hits_T = 6'h0; // @[TLB.scala:607:30] wire [1:0] io_req_bits_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7, :320:14] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7] wire io_req_bits_v = 1'h0; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs1 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs2 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_asid = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hv = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hg = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire priv_s = 1'h0; // @[TLB.scala:370:20] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:183:37] wire _io_req_ready_T; // @[TLB.scala:631:25] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire _r_superpage_repl_addr_T_3 = 1'h0; // @[TLB.scala:757:8] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire hv_13 = 1'h0; // @[TLB.scala:721:36] wire hg_13 = 1'h0; // @[TLB.scala:722:36] wire hv_14 = 1'h0; // @[TLB.scala:721:36] wire hg_14 = 1'h0; // @[TLB.scala:722:36] wire hv_15 = 1'h0; // @[TLB.scala:721:36] wire hg_15 = 1'h0; // @[TLB.scala:722:36] wire hv_16 = 1'h0; // @[TLB.scala:721:36] wire hg_16 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_17 = 1'h0; // @[TLB.scala:721:36] wire hg_17 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire [1:0] io_resp_size = io_req_bits_size_0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd = io_req_bits_cmd_0; // @[TLB.scala:318:7] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_ma_st_T; // @[TLB.scala:646:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld; // @[TLB.scala:318:7] wire io_resp_pf_st; // @[TLB.scala:318:7] wire io_resp_pf_inst; // @[TLB.scala:318:7] wire io_resp_ae_ld; // @[TLB.scala:318:7] wire io_resp_ae_st; // @[TLB.scala:318:7] wire io_resp_ae_inst; // @[TLB.scala:318:7] wire io_resp_ma_ld; // @[TLB.scala:318:7] wire io_resp_ma_st; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa; // @[TLB.scala:318:7] wire io_resp_cacheable; // @[TLB.scala:318:7] wire io_resp_must_alloc; // @[TLB.scala:318:7] wire io_resp_prefetchable; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [1:0] memIdx = vpn[1:0]; // @[package.scala:163:13] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_3_valid_0; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_9 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] wire _r_superpage_repl_addr_T = superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:16] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_11 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [1:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T; // @[TLB.scala:399:{31,45}] wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_25 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_25; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_25; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T \| _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 \| io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, 2'h0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 \| _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 \| _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 \| _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 \| _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 \| _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 \| _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 \| _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 \| _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 \| _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 \| _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 \| _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 \| _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 \| _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 \| _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire [3:0][26:0] _GEN_4 = {{sectored_entries_3_0_tag_vpn}, {sectored_entries_2_0_tag_vpn}, {sectored_entries_1_0_tag_vpn}, {sectored_entries_0_0_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_5 = {{sectored_entries_3_0_tag_v}, {sectored_entries_2_0_tag_v}, {sectored_entries_1_0_tag_v}, {sectored_entries_0_0_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_6 = {{sectored_entries_3_0_data_0}, {sectored_entries_2_0_data_0}, {sectored_entries_1_0_data_0}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_6[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_7 = {{sectored_entries_3_0_valid_0}, {sectored_entries_2_0_valid_0}, {sectored_entries_1_0_valid_0}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_8 = {{sectored_entries_3_1_tag_vpn}, {sectored_entries_2_1_tag_vpn}, {sectored_entries_1_1_tag_vpn}, {sectored_entries_0_1_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_9 = {{sectored_entries_3_1_tag_v}, {sectored_entries_2_1_tag_v}, {sectored_entries_1_1_tag_v}, {sectored_entries_0_1_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_10 = {{sectored_entries_3_1_data_0}, {sectored_entries_2_1_data_0}, {sectored_entries_1_1_data_0}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_10[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_11 = {{sectored_entries_3_1_valid_0}, {sectored_entries_2_1_valid_0}, {sectored_entries_1_1_valid_0}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_12 = {{sectored_entries_3_2_tag_vpn}, {sectored_entries_2_2_tag_vpn}, {sectored_entries_1_2_tag_vpn}, {sectored_entries_0_2_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_13 = {{sectored_entries_3_2_tag_v}, {sectored_entries_2_2_tag_v}, {sectored_entries_1_2_tag_v}, {sectored_entries_0_2_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_14 = {{sectored_entries_3_2_data_0}, {sectored_entries_2_2_data_0}, {sectored_entries_1_2_data_0}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_14[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_15 = {{sectored_entries_3_2_valid_0}, {sectored_entries_2_2_valid_0}, {sectored_entries_1_2_valid_0}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_16 = {{sectored_entries_3_3_tag_vpn}, {sectored_entries_2_3_tag_vpn}, {sectored_entries_1_3_tag_vpn}, {sectored_entries_0_3_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_17 = {{sectored_entries_3_3_tag_v}, {sectored_entries_2_3_tag_v}, {sectored_entries_1_3_tag_v}, {sectored_entries_0_3_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_18 = {{sectored_entries_3_3_data_0}, {sectored_entries_2_3_data_0}, {sectored_entries_1_3_data_0}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_18[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_19 = {{sectored_entries_3_3_valid_0}, {sectored_entries_2_3_valid_0}, {sectored_entries_1_3_valid_0}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [26:0] _GEN_20 = _GEN_4[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T; // @[TLB.scala:174:61] assign _sector_hits_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_1 = _sector_hits_T; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_2 = _sector_hits_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_4 = _sector_hits_T_2 & _sector_hits_T_3; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _GEN_7[memIdx] & _sector_hits_T_4; // @[package.scala:163:13] wire [26:0] _GEN_21 = _GEN_8[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_5; // @[TLB.scala:174:61] assign _sector_hits_T_5 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_6 = _sector_hits_T_5; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_7 = _sector_hits_T_6 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_8 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_9 = _sector_hits_T_7 & _sector_hits_T_8; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _GEN_11[memIdx] & _sector_hits_T_9; // @[package.scala:163:13] wire [26:0] _GEN_22 = _GEN_12[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_10; // @[TLB.scala:174:61] assign _sector_hits_T_10 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_11 = _sector_hits_T_10; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_12 = _sector_hits_T_11 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_13 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_14 = _sector_hits_T_12 & _sector_hits_T_13; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _GEN_15[memIdx] & _sector_hits_T_14; // @[package.scala:163:13] wire [26:0] _GEN_23 = _GEN_16[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_15; // @[TLB.scala:174:61] assign _sector_hits_T_15 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_16 = _sector_hits_T_15; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_17 = _sector_hits_T_16 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_18 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_19 = _sector_hits_T_17 & _sector_hits_T_18; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _GEN_19[memIdx] & _sector_hits_T_19; // @[package.scala:163:13] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_1876 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_24; // @[TLB.scala:183:52] assign _hitsVec_T_24 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_29; // @[TLB.scala:183:52] assign _hitsVec_T_29 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_34; // @[TLB.scala:183:52] assign _hitsVec_T_34 = _T_1876; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_24 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_24; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_8 = superpage_hits_ignore_1 \| _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire [26:0] _hitsVec_T_1 = _hitsVec_T; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_5 = _GEN_7[memIdx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_7 = _hitsVec_T_6; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_11 = _GEN_11[memIdx] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_13 = _hitsVec_T_12; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_17 = _GEN_15[memIdx] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_19 = _hitsVec_T_18; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_23 = _GEN_19[memIdx] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_25 = _hitsVec_T_24[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_26 = _hitsVec_T_25 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_27 = _hitsVec_T_26; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_28 = hitsVec_tagMatch & _hitsVec_T_27; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_30 = _hitsVec_T_29[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_31 = _hitsVec_T_30 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_32 = hitsVec_ignore_1 \| _hitsVec_T_31; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_33 = _hitsVec_T_28 & _hitsVec_T_32; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_38 = _hitsVec_T_33; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_35 = _hitsVec_T_34[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_36 = _hitsVec_T_35 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire hitsVec_4 = vm_enabled & _hitsVec_T_38; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_1 = special_entry_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_1974 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_39; // @[TLB.scala:183:52] assign _hitsVec_T_39 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_44; // @[TLB.scala:183:52] assign _hitsVec_T_44 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_49; // @[TLB.scala:183:52] assign _hitsVec_T_49 = _T_1974; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_40 = _hitsVec_T_39[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_41 = _hitsVec_T_40 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_42 = _hitsVec_T_41; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_43 = hitsVec_tagMatch_1 & _hitsVec_T_42; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_45 = _hitsVec_T_44[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_46 = _hitsVec_T_45 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_47 = hitsVec_ignore_4 \| _hitsVec_T_46; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_48 = _hitsVec_T_43 & _hitsVec_T_47; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_5 = _hitsVec_ignore_T_5; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_50 = _hitsVec_T_49[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_51 = _hitsVec_T_50 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_52 = hitsVec_ignore_5 \| _hitsVec_T_51; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_53 = _hitsVec_T_48 & _hitsVec_T_52; // @[TLB.scala:183:{29,40}] wire hitsVec_5 = vm_enabled & _hitsVec_T_53; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo = {real_hits_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_hi = {real_hits_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [5:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [6:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_25 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_27 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_28 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_29 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_30 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_31 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_32 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [1:0] r_memIdx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [2:0] sectored_entries_0_data_0_lo_lo_hi = {sectored_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_data_0_lo_lo = {sectored_entries_0_data_0_lo_lo_hi, sectored_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_lo_hi_lo = {sectored_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_lo_hi_hi = {sectored_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_lo_hi = {sectored_entries_0_data_0_lo_hi_hi, sectored_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_data_0_lo = {sectored_entries_0_data_0_lo_hi, sectored_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_lo_lo = {sectored_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_hi_lo_hi = {sectored_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_hi_lo = {sectored_entries_0_data_0_hi_lo_hi, sectored_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_hi_lo = {sectored_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_data_0_hi_hi_hi = {sectored_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_data_0_hi_hi = {sectored_entries_0_data_0_hi_hi_hi, sectored_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_data_0_hi = {sectored_entries_0_data_0_hi_hi, sectored_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_data_0_T = {sectored_entries_0_data_0_hi, sectored_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_lo_hi = {sectored_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_1_data_0_lo_lo = {sectored_entries_1_data_0_lo_lo_hi, sectored_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_hi_lo = {sectored_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_lo_hi_hi = {sectored_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_lo_hi = {sectored_entries_1_data_0_lo_hi_hi, sectored_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_1_data_0_lo = {sectored_entries_1_data_0_lo_hi, sectored_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_lo_lo = {sectored_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_hi_lo_hi = {sectored_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_hi_lo = {sectored_entries_1_data_0_hi_lo_hi, sectored_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_hi_lo = {sectored_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_1_data_0_hi_hi_hi = {sectored_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_1_data_0_hi_hi = {sectored_entries_1_data_0_hi_hi_hi, sectored_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_1_data_0_hi = {sectored_entries_1_data_0_hi_hi, sectored_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_1_data_0_T = {sectored_entries_1_data_0_hi, sectored_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_lo_hi = {sectored_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_2_data_0_lo_lo = {sectored_entries_2_data_0_lo_lo_hi, sectored_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_hi_lo = {sectored_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_lo_hi_hi = {sectored_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_lo_hi = {sectored_entries_2_data_0_lo_hi_hi, sectored_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_2_data_0_lo = {sectored_entries_2_data_0_lo_hi, sectored_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_lo_lo = {sectored_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_hi_lo_hi = {sectored_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_hi_lo = {sectored_entries_2_data_0_hi_lo_hi, sectored_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_hi_lo = {sectored_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_2_data_0_hi_hi_hi = {sectored_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_2_data_0_hi_hi = {sectored_entries_2_data_0_hi_hi_hi, sectored_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_2_data_0_hi = {sectored_entries_2_data_0_hi_hi, sectored_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_2_data_0_T = {sectored_entries_2_data_0_hi, sectored_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_lo_hi = {sectored_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_3_data_0_lo_lo = {sectored_entries_3_data_0_lo_lo_hi, sectored_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_hi_lo = {sectored_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_lo_hi_hi = {sectored_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_lo_hi = {sectored_entries_3_data_0_lo_hi_hi, sectored_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_3_data_0_lo = {sectored_entries_3_data_0_lo_hi, sectored_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_lo_lo = {sectored_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_hi_lo_hi = {sectored_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_hi_lo = {sectored_entries_3_data_0_hi_lo_hi, sectored_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_hi_lo = {sectored_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_3_data_0_hi_hi_hi = {sectored_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_3_data_0_hi_hi = {sectored_entries_3_data_0_hi_hi_hi, sectored_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_3_data_0_hi = {sectored_entries_3_data_0_hi_hi, sectored_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_3_data_0_T = {sectored_entries_3_data_0_hi, sectored_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire _entries_T; // @[TLB.scala:170:77] assign _entries_T = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T; // @[TLB.scala:170:77] assign _entries_T_1 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_22; // @[TLB.scala:170:77] wire [19:0] _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire _entries_T_24; // @[TLB.scala:170:77] wire _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_24 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_24; // @[TLB.scala:170:77] assign _entries_T_25 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_45; // @[TLB.scala:170:77] wire [19:0] _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire _entries_T_48; // @[TLB.scala:170:77] wire _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_47; // @[TLB.scala:170:77] assign _entries_T_48 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_48; // @[TLB.scala:170:77] assign _entries_T_49 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_68; // @[TLB.scala:170:77] wire [19:0] _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire _entries_T_72; // @[TLB.scala:170:77] wire _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_71; // @[TLB.scala:170:77] assign _entries_T_72 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_72; // @[TLB.scala:170:77] assign _entries_T_73 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_91; // @[TLB.scala:170:77] wire [19:0] _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire _entries_T_96; // @[TLB.scala:170:77] wire _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_95; // @[TLB.scala:170:77] assign _entries_T_96 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_96; // @[TLB.scala:170:77] assign _entries_T_97 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_114; // @[TLB.scala:170:77] wire [19:0] _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire _entries_T_120; // @[TLB.scala:170:77] wire _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_119; // @[TLB.scala:170:77] assign _entries_T_120 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_120; // @[TLB.scala:170:77] assign _entries_T_121 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_137; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_4_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] \| _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] \| _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_5_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] \| _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_3 = _ppn_ignore_T_3; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_13 = ppn_ignore_3 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] \| _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_17 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_18 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_19 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_20 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_21 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_22 = hitsVec_4 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_23 = hitsVec_5 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_24 = _ppn_T ? _ppn_T_17 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_25 = _ppn_T_18 \| _ppn_T_19; // @[Mux.scala:30:73] wire [19:0] _ppn_T_26 = _ppn_T_25 \| _ppn_T_20; // @[Mux.scala:30:73] wire [19:0] _ppn_T_27 = _ppn_T_26 \| _ppn_T_21; // @[Mux.scala:30:73] wire [19:0] _ppn_T_28 = _ppn_T_27 \| _ppn_T_22; // @[Mux.scala:30:73] wire [19:0] _ppn_T_29 = _ppn_T_28 \| _ppn_T_23; // @[Mux.scala:30:73] wire [19:0] _ppn_T_30 = _ppn_T_29 \| _ppn_T_24; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_30; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo = {final_ae_array_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi = {final_ae_array_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [6:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [6:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [6:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire [1:0] _GEN_33 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_34 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_2; // @[package.scala:45:27] wire [5:0] priv_rw_ok = _priv_rw_ok_T_3; // @[TLB.scala:513:{23,70}] wire [2:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo = {priv_x_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi = {priv_x_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [5:0] priv_x_ok = _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [5:0] _stage1_bypass_T_2 = {6{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo = {stage1_bypass_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi = {stage1_bypass_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [5:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 \| _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo = {r_array_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi = {r_array_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_35 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_1 = _GEN_35; // @[package.scala:45:27] wire [1:0] x_array_lo_hi; // @[package.scala:45:27] assign x_array_lo_hi = _GEN_35; // @[package.scala:45:27] wire [2:0] r_array_lo_1 = {r_array_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_36 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_1 = _GEN_36; // @[package.scala:45:27] wire [1:0] x_array_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi = _GEN_36; // @[package.scala:45:27] wire [2:0] r_array_hi_1 = {r_array_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [5:0] _r_array_T_2 = mxr ? _r_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _r_array_T_3 = _r_array_T \| _r_array_T_2; // @[package.scala:45:27] wire [5:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [5:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [6:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [6:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo = {w_array_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi = {w_array_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [5:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [5:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [6:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo = {x_array_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_hi = {x_array_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [5:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [5:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [6:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo = {hr_array_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi = {hr_array_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_37 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_1 = _GEN_37; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi; // @[package.scala:45:27] assign hx_array_lo_hi = _GEN_37; // @[package.scala:45:27] wire [2:0] hr_array_lo_1 = {hr_array_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_38 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_1 = _GEN_38; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi = _GEN_38; // @[package.scala:45:27] wire [2:0] hr_array_hi_1 = {hr_array_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [5:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _hr_array_T_3 = _hr_array_T \| _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo = {hw_array_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi = {hw_array_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo = {hx_array_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_hi = {hx_array_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo = {_entries_barrier_1_io_y_pr, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi = {_entries_barrier_4_io_y_pr, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi = {pr_array_hi_hi, _entries_barrier_2_io_y_pr}; // @[package.scala:45:27, :267:25] wire [4:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [6:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [6:0] _GEN_39 = ptw_ae_array \| final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [6:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_39; // @[TLB.scala:529:104] wire [6:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :531:104] wire [6:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :533:104] wire [6:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [6:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo = {_entries_barrier_1_io_y_pw, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi = {_entries_barrier_4_io_y_pw, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi = {pw_array_hi_hi, _entries_barrier_2_io_y_pw}; // @[package.scala:45:27, :267:25] wire [4:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [6:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [6:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [6:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo = {_entries_barrier_1_io_y_px, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi = {_entries_barrier_4_io_y_px, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi = {px_array_hi_hi, _entries_barrier_2_io_y_px}; // @[package.scala:45:27, :267:25] wire [4:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [6:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [6:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [6:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo = {_entries_barrier_1_io_y_eff, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi = {_entries_barrier_4_io_y_eff, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi = {eff_array_hi_hi, _entries_barrier_2_io_y_eff}; // @[package.scala:45:27, :267:25] wire [4:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [6:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_40 = {_entries_barrier_1_io_y_c, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo; // @[package.scala:45:27] assign c_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo; // @[package.scala:45:27] assign prefetchable_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] _GEN_41 = {_entries_barrier_4_io_y_c, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [2:0] c_array_hi = {c_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [6:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [6:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo = {_entries_barrier_1_io_y_ppp, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi = {_entries_barrier_4_io_y_ppp, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi = {ppp_array_hi_hi, _entries_barrier_2_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [4:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [6:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo = {_entries_barrier_1_io_y_paa, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi = {_entries_barrier_4_io_y_paa, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi = {paa_array_hi_hi, _entries_barrier_2_io_y_paa}; // @[package.scala:45:27, :267:25] wire [4:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [6:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo = {_entries_barrier_1_io_y_pal, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi = {_entries_barrier_4_io_y_pal, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi = {pal_array_hi_hi, _entries_barrier_2_io_y_pal}; // @[package.scala:45:27, :267:25] wire [4:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [6:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [6:0] ppp_array_if_cached = ppp_array \| c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [6:0] paa_array_if_cached = paa_array \| c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [6:0] pal_array_if_cached = pal_array \| c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_hi = {prefetchable_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [6:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}] wire misaligned = \|_misaligned_T_3; // @[TLB.scala:550:{39,77}] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:550:77, :559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 \| _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _GEN_42 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_42; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_42; // @[package.scala:16:47] wire _GEN_43 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_43; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_43; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_43; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T \| _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire cmd_lrsc = _cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_44 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_44; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_44; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_45; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_45; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_46; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_46; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_46; // @[package.scala:16:47] wire _GEN_47 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_47; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_47; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_47; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T \| _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 \| _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 \| _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire cmd_amo_logical = _cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_48 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_48; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_48; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_49; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_49; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_50; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_50; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_51; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_51; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_51; // @[package.scala:16:47] wire _GEN_52 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_52; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_52; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_52; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T \| _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 \| _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 \| _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 \| _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire cmd_amo_arithmetic = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_53 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41] wire cmd_put_partial; // @[TLB.scala:573:41] assign cmd_put_partial = _GEN_53; // @[TLB.scala:573:41] wire _cmd_write_T_1; // @[Consts.scala:90:49] assign _cmd_write_T_1 = _GEN_53; // @[TLB.scala:573:41] wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _GEN_54 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_1; // @[package.scala:16:47] assign _cmd_read_T_1 = _GEN_54; // @[package.scala:16:47] wire _cmd_readx_T; // @[TLB.scala:575:56] assign _cmd_readx_T = _GEN_54; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T \| _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 \| _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 \| _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 \| _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 \| _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 \| _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 \| _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 \| _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 \| _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 \| _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 \| _cmd_read_T_22; // @[package.scala:81:59] wire cmd_read = _cmd_read_T_6 \| _cmd_read_T_23; // @[package.scala:81:59] wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7] wire _cmd_write_T_2 = _cmd_write_T \| _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 \| _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 \| _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 \| _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 \| _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 \| _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 \| _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 \| _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 \| _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 \| _cmd_write_T_20; // @[package.scala:81:59] wire cmd_write = _cmd_write_T_4 \| _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = _cmd_write_perms_T \| _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire cmd_write_perms = cmd_write \| _cmd_write_perms_T_2; // @[package.scala:81:59] wire [6:0] _ae_array_T = misaligned ? eff_array : 7'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [6:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [6:0] _ae_array_T_2 = cmd_lrsc ? _ae_array_T_1 : 7'h0; // @[TLB.scala:570:33, :583:{8,19}] wire [6:0] ae_array = _ae_array_T \| _ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [6:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [6:0] _ae_ld_array_T_1 = ae_array \| _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [6:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 7'h0; // @[TLB.scala:586:{24,44}] wire [6:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [6:0] _ae_st_array_T_1 = ae_array \| _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [6:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 7'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [6:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [6:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 7'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [6:0] _ae_st_array_T_5 = _ae_st_array_T_2 \| _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [6:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [6:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_6 : 7'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [6:0] _ae_st_array_T_8 = _ae_st_array_T_5 \| _ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [6:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [6:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_9 : 7'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [6:0] ae_st_array = _ae_st_array_T_8 \| _ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [6:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [6:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 7'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [6:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [6:0] _must_alloc_array_T_3 = cmd_amo_logical ? _must_alloc_array_T_2 : 7'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [6:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 \| _must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [6:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [6:0] _must_alloc_array_T_6 = cmd_amo_arithmetic ? _must_alloc_array_T_5 : 7'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [6:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 \| _must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [6:0] _must_alloc_array_T_9 = {7{cmd_lrsc}}; // @[TLB.scala:570:33, :596:8] wire [6:0] must_alloc_array = _must_alloc_array_T_7 \| _must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [6:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [6:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [6:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [6:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 \| ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [6:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [6:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [6:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 7'h0; // @[TLB.scala:597:{24,104}] wire [6:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [6:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [6:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [6:0] _pf_st_array_T_3 = _pf_st_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [6:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [6:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [6:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 7'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [6:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [6:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [6:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [6:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [6:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [6:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [6:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [6:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [6:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [6:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [6:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [6:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [4:0] _gpa_hits_hit_mask_T_2 = {5{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = \|real_hits; // @[package.scala:45:27] wire tlb_hit = \|_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [2:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_vec_1; // @[Replacement.scala:305:17] reg [2:0] state_vec_2; // @[Replacement.scala:305:17] reg [2:0] state_vec_3; // @[Replacement.scala:305:17] wire [1:0] _GEN_55 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo; // @[OneHot.scala:21:45] assign lo = _GEN_55; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo = _GEN_55; // @[OneHot.scala:21:45] wire [1:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_56 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi; // @[OneHot.scala:21:45] assign hi = _GEN_56; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi = _GEN_56; // @[OneHot.scala:21:45] wire [1:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_vec_touch_way_sized = {\|hi_1, hi_1[1] \| lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_set_left_older_T = state_vec_touch_way_sized[1]; // @[package.scala:163:13] wire state_vec_set_left_older = ~_state_vec_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [3:0][2:0] _GEN_57 = {{state_vec_3}, {state_vec_2}, {state_vec_1}, {state_vec_0}}; // @[package.scala:163:13] wire state_vec_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13] wire state_vec_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13] wire _state_vec_T = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_4 = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_1 = _state_vec_T; // @[package.scala:163:13] wire _state_vec_T_2 = ~_state_vec_T_1; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_3 = state_vec_set_left_older ? state_vec_left_subtree_state : _state_vec_T_2; // @[package.scala:163:13] wire _state_vec_T_5 = _state_vec_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_vec_T_6 = ~_state_vec_T_5; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_7 = state_vec_set_left_older ? _state_vec_T_6 : state_vec_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_hi = {state_vec_set_left_older, _state_vec_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_T_8 = {state_vec_hi, _state_vec_T_7}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _multipleHits_T = real_hits[2:0]; // @[package.scala:45:27] wire _multipleHits_T_1 = _multipleHits_T[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_1; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_2 = _multipleHits_T[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_3 = _multipleHits_T_2[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_3; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_4 = _multipleHits_T_2[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_4; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 \| multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_6 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_6; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_7 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne \| multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_8 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_7 \| _multipleHits_T_8; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_9 = real_hits[5:3]; // @[package.scala:45:27] wire _multipleHits_T_10 = _multipleHits_T_9[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_10; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_11 = _multipleHits_T_9[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_12 = _multipleHits_T_11[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_12; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_13 = _multipleHits_T_11[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_13; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 \| multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_15 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_15; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_16 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 \| multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_17 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_16 \| _multipleHits_T_17; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_18 = multipleHits_leftOne_2 \| multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo \| multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_19 \| _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28] wire [6:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = \|_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T \| _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28] wire [6:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64] wire _io_resp_pf_st_T_2 = \|_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T \| _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}] assign io_resp_pf_st = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48] wire [6:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = \|_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va \| _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [6:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = \|_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [6:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33] assign _io_resp_ae_st_T_1 = \|_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign io_resp_ae_st = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41] wire [6:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [6:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = \|_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31] assign io_resp_ma_ld = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31] assign io_resp_ma_st = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31] wire [6:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = \|_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [6:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43] assign _io_resp_must_alloc_T_1 = \|_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign io_resp_must_alloc = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51] wire [6:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = \|_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T \| tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 \| multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire _r_superpage_repl_addr_T_1 = ~superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:43] wire _r_superpage_repl_addr_T_2 = _r_superpage_repl_addr_T_1; // @[OneHot.scala:48:45] wire r_sectored_repl_addr_left_subtree_older = _GEN_57[memIdx][2]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_sectored_repl_addr_valids_lo = {_GEN_11[memIdx], _GEN_7[memIdx]}; // @[package.scala:45:27, :163:13] wire [1:0] r_sectored_repl_addr_valids_hi = {_GEN_19[memIdx], _GEN_15[memIdx]}; // @[package.scala:45:27, :163:13] wire [3:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_4 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_sectored_repl_addr_T_5 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_6 = _r_sectored_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_7 = _r_sectored_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_8 = _r_sectored_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_9 = _r_sectored_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_10 = {1'h1, ~_r_sectored_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_11 = _r_sectored_repl_addr_T_7 ? 2'h1 : _r_sectored_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_6 ? 2'h0 : _r_sectored_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_4 ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_12; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 \| sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T \| sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 \| sector_hits_3; // @[package.scala:81:59] wire [3:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = \|r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 \| r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_3 = _r_sectored_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_4 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45] wire _tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire tagMatch = superpage_entries_0_valid_0 & _tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire ignore_1 = _ignore_T_1; // @[TLB.scala:182:{28,34}] wire _ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire _tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire tagMatch_1 = special_entry_valid_0 & _tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire ignore_4 = _ignore_T_4; // @[TLB.scala:182:{28,34}] wire _ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire ignore_5 = _ignore_T_5; // @[TLB.scala:182:{28,34}] wire _T_12 = io_req_valid_0 & vm_enabled; // @[TLB.scala:318:7, :399:61, :617:22] wire _T_15 = sector_hits_0 \| sector_hits_1 \| sector_hits_2 \| sector_hits_3; // @[package.scala:81:59] wire _GEN_58 = do_refill & ~io_ptw_resp_bits_homogeneous_0; // @[TLB.scala:211:18, :318:7, :346:56, :408:29, :446:20, :474:{39,70}] wire _GEN_59 = ~do_refill \| ~io_ptw_resp_bits_homogeneous_0 \| io_ptw_resp_bits_level_0[1]; // @[TLB.scala:318:7, :341:30, :408:29, :446:20, :474:70, :476:{40,58}] wire _T_4 = waddr_1 == 2'h0; // @[TLB.scala:485:22, :486:75] wire _GEN_60 = r_memIdx == 2'h0; // @[package.scala:163:13] wire _GEN_61 = r_memIdx == 2'h1; // @[package.scala:163:13] wire _GEN_62 = r_memIdx == 2'h2; // @[package.scala:163:13] wire _GEN_63 = ~io_ptw_resp_bits_homogeneous_0 \| ~(io_ptw_resp_bits_level_0[1]); // @[TLB.scala:318:7, :339:29, :474:{39,70}, :476:{40,58}, :486:84] wire _GEN_64 = ~do_refill \| _GEN_63 \| ~(_T_4 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_65 = ~do_refill \| _GEN_63 \| ~(_T_4 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_66 = ~do_refill \| _GEN_63 \| ~(_T_4 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_67 = ~do_refill \| _GEN_63 \| ~(_T_4 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_68 = invalidate_refill & _GEN_60; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_69 = ~do_refill \| _GEN_63 \| ~_T_4; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_70 = invalidate_refill & _GEN_61; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_71 = invalidate_refill & _GEN_62; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_72 = invalidate_refill & (&r_memIdx); // @[package.scala:163:13] wire _T_6 = waddr_1 == 2'h1; // @[TLB.scala:197:28, :485:22, :486:75] wire _GEN_73 = ~do_refill \| _GEN_63 \| ~(_T_6 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_74 = ~do_refill \| _GEN_63 \| ~(_T_6 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_75 = ~do_refill \| _GEN_63 \| ~(_T_6 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_76 = ~do_refill \| _GEN_63 \| ~(_T_6 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_77 = ~do_refill \| _GEN_63 \| ~_T_6; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _T_8 = waddr_1 == 2'h2; // @[TLB.scala:485:22, :486:75] wire _GEN_78 = ~do_refill \| _GEN_63 \| ~(_T_8 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_79 = ~do_refill \| _GEN_63 \| ~(_T_8 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_80 = ~do_refill \| _GEN_63 \| ~(_T_8 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_81 = ~do_refill \| _GEN_63 \| ~(_T_8 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_82 = ~do_refill \| _GEN_63 \| ~_T_8; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_83 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_84 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_85 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_86 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_87 = ~do_refill \| _GEN_63 \| ~(&waddr_1); // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _T_2491 = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] wire _T_24 = io_req_ready_0 & io_req_valid_0 & tlb_miss; // @[Decoupled.scala:51:35] wire _T_2490 = multipleHits \| reset; // @[Misc.scala:183:49] always @(posedge clock) begin // @[TLB.scala:318:7] if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_0_tag_v <= _GEN_64 & sectored_entries_0_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_0_tag_v) & (_GEN_69 ? sectored_entries_0_0_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_1_tag_v <= _GEN_73 & sectored_entries_0_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_1_tag_v) & (_GEN_77 ? sectored_entries_0_1_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_2_tag_v <= _GEN_78 & sectored_entries_0_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_2_tag_v) & (_GEN_82 ? sectored_entries_0_2_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_3_tag_v <= _GEN_83 & sectored_entries_0_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_3_tag_v) & (_GEN_87 ? sectored_entries_0_3_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_0_tag_v <= _GEN_65 & sectored_entries_1_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_0_tag_v) & (_GEN_69 ? sectored_entries_1_0_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_1_tag_v <= _GEN_74 & sectored_entries_1_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_1_tag_v) & (_GEN_77 ? sectored_entries_1_1_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_2_tag_v <= _GEN_79 & sectored_entries_1_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_2_tag_v) & (_GEN_82 ? sectored_entries_1_2_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_3_tag_v <= _GEN_84 & sectored_entries_1_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_3_tag_v) & (_GEN_87 ? sectored_entries_1_3_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_0_tag_v <= _GEN_66 & sectored_entries_2_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_0_tag_v) & (_GEN_69 ? sectored_entries_2_0_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_1_tag_v <= _GEN_75 & sectored_entries_2_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_1_tag_v) & (_GEN_77 ? sectored_entries_2_1_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_2_tag_v <= _GEN_80 & sectored_entries_2_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_2_tag_v) & (_GEN_82 ? sectored_entries_2_2_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_3_tag_v <= _GEN_85 & sectored_entries_2_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_3_tag_v) & (_GEN_87 ? sectored_entries_2_3_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_0_tag_v <= _GEN_67 & sectored_entries_3_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_0_tag_v) & (_GEN_69 ? sectored_entries_3_0_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_0_valid_0)); // @[package.scala:163:13] if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_1_tag_v <= _GEN_76 & sectored_entries_3_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_1_tag_v) & (_GEN_77 ? sectored_entries_3_1_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_1_valid_0)); // @[package.scala:163:13] if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_2_tag_v <= _GEN_81 & sectored_entries_3_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_2_tag_v) & (_GEN_82 ? sectored_entries_3_2_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_2_valid_0)); // @[package.scala:163:13] if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_3_tag_v <= _GEN_86 & sectored_entries_3_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_3_tag_v) & (_GEN_87 ? sectored_entries_3_3_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_3_valid_0)); // @[package.scala:163:13] if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_level <= {1'h0, _superpage_entries_0_level_T}; // @[package.scala:163:13] superpage_entries_0_tag_vpn <= r_refill_tag; // @[TLB.scala:341:30, :354:25] end superpage_entries_0_tag_v <= _GEN_59 & superpage_entries_0_tag_v; // @[TLB.scala:341:30, :446:20, :474:70, :476:58] if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_data_0 <= _superpage_entries_0_data_0_T; // @[TLB.scala:217:24, :341:30] superpage_entries_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~superpage_entries_0_tag_v) & (_GEN_59 ? superpage_entries_0_valid_0 : ~invalidate_refill); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :341:30, :410:88, :446:20, :474:70, :476:58, :480:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_58) begin // @[TLB.scala:211:18, :346:56, :446:20, :474:70] special_entry_level <= _special_entry_level_T; // @[package.scala:163:13] special_entry_tag_vpn <= r_refill_tag; // @[TLB.scala:346:56, :354:25] special_entry_data_0 <= _special_entry_data_0_T; // @[TLB.scala:217:24, :346:56] end special_entry_tag_v <= ~_GEN_58 & special_entry_tag_v; // @[TLB.scala:211:18, :212:16, :346:56, :446:20, :474:70] special_entry_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~special_entry_tag_v) & (_GEN_58 \| special_entry_valid_0); // @[TLB.scala:211:18, :216:16, :220:46, :223:{19,32,36}, :318:7, :346:56, :446:20, :474:70, :718:19, :723:42, :728:46, :732:{24,41}] if (_T_24) begin // @[Decoupled.scala:51:35] r_refill_tag <= vpn; // @[TLB.scala:335:30, :354:25] r_sectored_repl_addr <= _r_sectored_repl_addr_T_13; // @[TLB.scala:356:33, :757:8] r_sectored_hit_valid <= _r_sectored_hit_valid_T_2; // @[package.scala:81:59] r_sectored_hit_bits <= _r_sectored_hit_bits_T_4; // @[OneHot.scala:32:10] r_superpage_hit_valid <= superpage_hits_0; // @[TLB.scala:183:29, :358:28] r_need_gpa <= tlb_hit_if_not_gpa_miss; // @[TLB.scala:361:23, :610:43] end r_gpa_valid <= ~_T_2491 & (do_refill ? io_ptw_resp_bits_gpa_valid_0 : r_gpa_valid); // @[Decoupled.scala:51:35] if (do_refill) begin // @[TLB.scala:408:29] r_gpa <= io_ptw_resp_bits_gpa_bits_0; // @[TLB.scala:318:7, :363:18] r_gpa_is_pte <= io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :365:25] end if (_T_2491) // @[Decoupled.scala:51:35] r_gpa_vpn <= r_refill_tag; // @[TLB.scala:354:25, :364:22] if (reset) begin // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] state_vec_0 <= 3'h0; // @[Replacement.scala:305:17] state_vec_1 <= 3'h0; // @[Replacement.scala:305:17] state_vec_2 <= 3'h0; // @[Replacement.scala:305:17] state_vec_3 <= 3'h0; // @[Replacement.scala:305:17] end else begin // @[TLB.scala:318:7] if (io_ptw_resp_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (state == 2'h2 & io_sfence_valid_0) // @[TLB.scala:318:7, :352:22, :709:{17,28}] state <= 2'h3; // @[TLB.scala:352:22] else if (_T_25) begin // @[package.scala:16:47] if (io_ptw_req_ready_0) // @[TLB.scala:318:7] state <= _state_T; // @[TLB.scala:352:22, :704:45] else if (io_sfence_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] end else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] if (_T_12 & _T_15 & memIdx == 2'h0) // @[package.scala:81:59, :163:13] state_vec_0 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h1) // @[package.scala:81:59, :163:13] state_vec_1 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h2) // @[package.scala:81:59, :163:13] state_vec_2 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & (&memIdx)) // @[package.scala:81:59, :163:13] state_vec_3 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] end always @(posedge) OptimizationBarrier_TLBEntryData_70 mpu_ppn_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_mpu_ppn_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_mpu_ppn_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_mpu_ppn_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_mpu_ppn_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_mpu_ppn_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_mpu_ppn_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_mpu_ppn_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_mpu_ppn_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_mpu_ppn_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_mpu_ppn_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_mpu_ppn_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_mpu_ppn_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_mpu_ppn_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_mpu_ppn_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_mpu_ppn_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_mpu_ppn_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_mpu_ppn_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_mpu_ppn_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_mpu_ppn_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_mpu_ppn_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_mpu_ppn_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_mpu_ppn_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_mpu_ppn_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_mpu_ppn_barrier_io_y_ppn) ); // @[package.scala:267:25] PMPChecker_s3_8 pmp ( // @[TLB.scala:416:19] .clock (clock), .reset (reset), .io_prv (mpu_priv[1:0]), // @[TLB.scala:415:27, :420:14] .io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_0_addr (io_ptw_pmp_0_addr_0), // @[TLB.scala:318:7] .io_pmp_0_mask (io_ptw_pmp_0_mask_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_1_addr (io_ptw_pmp_1_addr_0), // @[TLB.scala:318:7] .io_pmp_1_mask (io_ptw_pmp_1_mask_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_2_addr (io_ptw_pmp_2_addr_0), // @[TLB.scala:318:7] .io_pmp_2_mask (io_ptw_pmp_2_mask_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_3_addr (io_ptw_pmp_3_addr_0), // @[TLB.scala:318:7] .io_pmp_3_mask (io_ptw_pmp_3_mask_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_4_addr (io_ptw_pmp_4_addr_0), // @[TLB.scala:318:7] .io_pmp_4_mask (io_ptw_pmp_4_mask_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_5_addr (io_ptw_pmp_5_addr_0), // @[TLB.scala:318:7] .io_pmp_5_mask (io_ptw_pmp_5_mask_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_6_addr (io_ptw_pmp_6_addr_0), // @[TLB.scala:318:7] .io_pmp_6_mask (io_ptw_pmp_6_mask_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_7_addr (io_ptw_pmp_7_addr_0), // @[TLB.scala:318:7] .io_pmp_7_mask (io_ptw_pmp_7_mask_0), // @[TLB.scala:318:7] .io_addr (mpu_physaddr[31:0]), // @[TLB.scala:414:25, :417:15] .io_size (io_req_bits_size_0), // @[TLB.scala:318:7] .io_r (_pmp_io_r), .io_w (_pmp_io_w), .io_x (_pmp_io_x) ); // @[TLB.scala:416:19] PMAChecker_8 pma ( // @[TLB.scala:422:19] .clock (clock), .reset (reset), .io_paddr (mpu_physaddr), // @[TLB.scala:414:25] .io_resp_cacheable (cacheable), .io_resp_r (_pma_io_resp_r), .io_resp_w (_pma_io_resp_w), .io_resp_pp (_pma_io_resp_pp), .io_resp_al (_pma_io_resp_al), .io_resp_aa (_pma_io_resp_aa), .io_resp_x (_pma_io_resp_x), .io_resp_eff (_pma_io_resp_eff) ); // @[TLB.scala:422:19] assign newEntry_ppp = _pma_io_resp_pp; // @[TLB.scala:422:19, :449:24] assign newEntry_pal = _pma_io_resp_al; // @[TLB.scala:422:19, :449:24] assign newEntry_paa = _pma_io_resp_aa; // @[TLB.scala:422:19, :449:24] assign newEntry_eff = _pma_io_resp_eff; // @[TLB.scala:422:19, :449:24] OptimizationBarrier_TLBEntryData_71 entries_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_io_y_ppn), .io_y_u (_entries_barrier_io_y_u), .io_y_ae_ptw (_entries_barrier_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_io_y_ae_stage2), .io_y_pf (_entries_barrier_io_y_pf), .io_y_gf (_entries_barrier_io_y_gf), .io_y_sw (_entries_barrier_io_y_sw), .io_y_sx (_entries_barrier_io_y_sx), .io_y_sr (_entries_barrier_io_y_sr), .io_y_hw (_entries_barrier_io_y_hw), .io_y_hx (_entries_barrier_io_y_hx), .io_y_hr (_entries_barrier_io_y_hr), .io_y_pw (_entries_barrier_io_y_pw), .io_y_px (_entries_barrier_io_y_px), .io_y_pr (_entries_barrier_io_y_pr), .io_y_ppp (_entries_barrier_io_y_ppp), .io_y_pal (_entries_barrier_io_y_pal), .io_y_paa (_entries_barrier_io_y_paa), .io_y_eff (_entries_barrier_io_y_eff), .io_y_c (_entries_barrier_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_72 entries_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_2_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_2_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_2_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_2_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_2_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_2_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_2_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_2_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_2_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_2_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_2_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_2_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_2_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_2_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_2_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_2_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_2_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_2_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_2_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_2_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_2_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_2_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_1_io_y_ppn), .io_y_u (_entries_barrier_1_io_y_u), .io_y_ae_ptw (_entries_barrier_1_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_1_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_1_io_y_ae_stage2), .io_y_pf (_entries_barrier_1_io_y_pf), .io_y_gf (_entries_barrier_1_io_y_gf), .io_y_sw (_entries_barrier_1_io_y_sw), .io_y_sx (_entries_barrier_1_io_y_sx), .io_y_sr (_entries_barrier_1_io_y_sr), .io_y_hw (_entries_barrier_1_io_y_hw), .io_y_hx (_entries_barrier_1_io_y_hx), .io_y_hr (_entries_barrier_1_io_y_hr), .io_y_pw (_entries_barrier_1_io_y_pw), .io_y_px (_entries_barrier_1_io_y_px), .io_y_pr (_entries_barrier_1_io_y_pr), .io_y_ppp (_entries_barrier_1_io_y_ppp), .io_y_pal (_entries_barrier_1_io_y_pal), .io_y_paa (_entries_barrier_1_io_y_paa), .io_y_eff (_entries_barrier_1_io_y_eff), .io_y_c (_entries_barrier_1_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_73 entries_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_4_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_4_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_4_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_4_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_4_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_4_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_4_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_4_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_4_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_4_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_4_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_4_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_4_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_4_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_4_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_4_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_4_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_4_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_4_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_4_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_4_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_4_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_2_io_y_ppn), .io_y_u (_entries_barrier_2_io_y_u), .io_y_ae_ptw (_entries_barrier_2_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_2_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_2_io_y_ae_stage2), .io_y_pf (_entries_barrier_2_io_y_pf), .io_y_gf (_entries_barrier_2_io_y_gf), .io_y_sw (_entries_barrier_2_io_y_sw), .io_y_sx (_entries_barrier_2_io_y_sx), .io_y_sr (_entries_barrier_2_io_y_sr), .io_y_hw (_entries_barrier_2_io_y_hw), .io_y_hx (_entries_barrier_2_io_y_hx), .io_y_hr (_entries_barrier_2_io_y_hr), .io_y_pw (_entries_barrier_2_io_y_pw), .io_y_px (_entries_barrier_2_io_y_px), .io_y_pr (_entries_barrier_2_io_y_pr), .io_y_ppp (_entries_barrier_2_io_y_ppp), .io_y_pal (_entries_barrier_2_io_y_pal), .io_y_paa (_entries_barrier_2_io_y_paa), .io_y_eff (_entries_barrier_2_io_y_eff), .io_y_c (_entries_barrier_2_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_74 entries_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_6_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_6_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_6_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_6_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_6_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_6_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_6_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_6_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_6_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_6_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_6_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_6_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_6_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_6_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_6_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_6_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_6_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_6_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_6_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_6_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_6_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_6_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_3_io_y_ppn), .io_y_u (_entries_barrier_3_io_y_u), .io_y_ae_ptw (_entries_barrier_3_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_3_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_3_io_y_ae_stage2), .io_y_pf (_entries_barrier_3_io_y_pf), .io_y_gf (_entries_barrier_3_io_y_gf), .io_y_sw (_entries_barrier_3_io_y_sw), .io_y_sx (_entries_barrier_3_io_y_sx), .io_y_sr (_entries_barrier_3_io_y_sr), .io_y_hw (_entries_barrier_3_io_y_hw), .io_y_hx (_entries_barrier_3_io_y_hx), .io_y_hr (_entries_barrier_3_io_y_hr), .io_y_pw (_entries_barrier_3_io_y_pw), .io_y_px (_entries_barrier_3_io_y_px), .io_y_pr (_entries_barrier_3_io_y_pr), .io_y_ppp (_entries_barrier_3_io_y_ppp), .io_y_pal (_entries_barrier_3_io_y_pal), .io_y_paa (_entries_barrier_3_io_y_paa), .io_y_eff (_entries_barrier_3_io_y_eff), .io_y_c (_entries_barrier_3_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_75 entries_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_8_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_8_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_8_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_8_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_8_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_8_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_8_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_8_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_8_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_8_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_8_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_8_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_8_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_8_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_8_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_8_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_8_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_8_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_8_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_8_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_8_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_8_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_4_io_y_ppn), .io_y_u (_entries_barrier_4_io_y_u), .io_y_ae_ptw (_entries_barrier_4_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_4_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_4_io_y_ae_stage2), .io_y_pf (_entries_barrier_4_io_y_pf), .io_y_gf (_entries_barrier_4_io_y_gf), .io_y_sw (_entries_barrier_4_io_y_sw), .io_y_sx (_entries_barrier_4_io_y_sx), .io_y_sr (_entries_barrier_4_io_y_sr), .io_y_hw (_entries_barrier_4_io_y_hw), .io_y_hx (_entries_barrier_4_io_y_hx), .io_y_hr (_entries_barrier_4_io_y_hr), .io_y_pw (_entries_barrier_4_io_y_pw), .io_y_px (_entries_barrier_4_io_y_px), .io_y_pr (_entries_barrier_4_io_y_pr), .io_y_ppp (_entries_barrier_4_io_y_ppp), .io_y_pal (_entries_barrier_4_io_y_pal), .io_y_paa (_entries_barrier_4_io_y_paa), .io_y_eff (_entries_barrier_4_io_y_eff), .io_y_c (_entries_barrier_4_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_76 entries_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_10_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_10_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_10_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_10_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_10_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_10_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_10_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_10_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_10_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_10_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_10_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_10_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_10_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_10_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_10_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_10_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_10_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_10_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_10_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_10_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_10_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_10_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_5_io_y_ppn), .io_y_u (_entries_barrier_5_io_y_u), .io_y_ae_ptw (_entries_barrier_5_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_5_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_5_io_y_ae_stage2), .io_y_pf (_entries_barrier_5_io_y_pf), .io_y_gf (_entries_barrier_5_io_y_gf), .io_y_sw (_entries_barrier_5_io_y_sw), .io_y_sx (_entries_barrier_5_io_y_sx), .io_y_sr (_entries_barrier_5_io_y_sr), .io_y_hw (_entries_barrier_5_io_y_hw), .io_y_hx (_entries_barrier_5_io_y_hx), .io_y_hr (_entries_barrier_5_io_y_hr) ); // @[package.scala:267:25] assign io_req_ready = io_req_ready_0; // @[TLB.scala:318:7] assign io_resp_miss = io_resp_miss_0; // @[TLB.scala:318:7] assign io_resp_paddr = io_resp_paddr_0; // @[TLB.scala:318:7] assign io_ptw_req_valid = io_ptw_req_valid_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_need_gpa = io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_40( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [7:0] b_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] b_first_count = 8'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1_1 = \|(io_in_b_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size_1 = mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1_1 = mask_sub_sub_sub_sub_0_1_1 \| _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1_1 = mask_sub_sub_sub_sub_0_1_1 \| _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size_1 & mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1_1 = mask_sub_sub_sub_1_1_1 \| _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size_1 & mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1_1 = mask_sub_sub_sub_1_1_1 \| _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size_1 & mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1_1 = mask_sub_sub_2_1_1 \| _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size_1 & mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1_1 = mask_sub_sub_2_1_1 \| _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size_1 & mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1_1 = mask_sub_sub_3_1_1 \| _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size_1 & mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1_1 = mask_sub_sub_3_1_1 \| _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size_1 & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_0_1_1 \| _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size_1 & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_0_1_1 \| _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size_1 & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_1_1_1 \| _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size_1 & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_1_1_1 \| _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size_1 & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_2_1_1 \| _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size_1 & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_2_1_1 \| _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size_1 & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_3_1_1 \| _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size_1 & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_3_1_1 \| _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size_1 & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_4_1_1 \| _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size_1 & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_4_1_1 \| _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size_1 & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_5_1_1 \| _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size_1 & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_5_1_1 \| _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size_1 & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_6_1_1 \| _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size_1 & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_6_1_1 \| _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size_1 & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_7_1_1 \| _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size_1 & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_7_1_1 \| _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_1 = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_1 = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_1 = {mask_lo_lo_hi_1, mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_1 = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_1 = {mask_lo_hi_hi_1, mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_1 = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_1 = {mask_hi_lo_hi_1, mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_1 = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_1 = {mask_hi_hi_hi_1, mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73] wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2399 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2399; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2399; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2473 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2473; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2473; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2473; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2473; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [7:0] b_first_counter; // @[Edges.scala:229:27] wire [8:0] _b_first_counter1_T = {1'h0, b_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] b_first_counter1 = _b_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _b_first_counter_T = b_first ? 8'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2470 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2470; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2470; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T = {1'h0, c_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1 = _c_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_21 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_22 = 2'h1 << _GEN_21; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_22; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2325 = _T_2399 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2325 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2325 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2325 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2325 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_2325 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_23 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_23; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_23; // @[Monitor.scala:673:46, :783:46] wire _T_2371 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_24 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_25 = 2'h1 << _GEN_24; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_25; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2371 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2340 = _T_2473 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2340 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2340 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2340 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1_1 = _c_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] c_set; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [15:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [1:0] _GEN_26 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_27 = 2'h1 << _GEN_26; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_27; // @[OneHot.scala:58:35] wire [1:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_27; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2412 = _T_2470 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2412 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2412 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2412 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}] assign c_opcodes_set = _T_2412 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}] assign c_sizes_set = _T_2412 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2443 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2443 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_2425 = _T_2473 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2425 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2425 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2425 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [1:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [15:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_3 = _d_first_counter1_T_3[7:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] d_set; // @[Monitor.scala:833:25] wire _T_2479 = _T_2473 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _GEN_28 = {12'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _d_set_T = 16'h1 << _GEN_28; // @[OneHot.scala:58:35] assign d_set = _T_2479 ? _d_set_T : 16'h0; // @[OneHot.scala:58:35] wire [15:0] e_clr; // @[Monitor.scala:839:25] wire _T_2488 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [15:0] _GEN_29 = {12'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _e_clr_T = 16'h1 << _GEN_29; // @[OneHot.scala:58:35] assign e_clr = _T_2488 ? _e_clr_T : 16'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first \| last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first \| last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid \|\| ((!w_releaseack \|\| !w_rprobeacklast \|\| !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst \|\| !w_pprobeackfirst \|\| !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB \|\| !io.status.bits.blockB) assert (!io.status.bits.nestC \|\| !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe \|\| !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) \|\| (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) \|\| (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid \|\| io.schedule.bits.b.valid \|\| io.schedule.bits.c.valid \|\| io.schedule.bits.d.valid \|\| io.schedule.bits.e.valid \|\| io.schedule.bits.x.valid \|\| io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock \|\| request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty \|\| request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) \|\| !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) \| Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid \|\| meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U \|\| !(request.opcode === PutFullData \|\| request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r \|\| p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c \|\| m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read \|\| clean release can lead to this state eviction(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_D, true) // MMIO write \|\| dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read \|\| clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write \|\| clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read \|\| clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done \| probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done \| probe_bit probes_toN := probes_toN \| Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT \|\| io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst \|\| last_probe w_rprobeacklast := w_rprobeacklast \|\| (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst \|\| last_probe w_pprobeacklast := w_pprobeacklast \|\| (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last \|\| request.offset === 0.U) w_pprobeack := w_pprobeack \|\| set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant \|\| io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U \|\| io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f \|\| p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read \|\| clean release can lead to this state bypass(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_D, true) // MMIO write \|\| dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid \|\| (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid \|\| (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit \|\| (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT \|\| new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock \|\| new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module MSHR_3( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [7:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [7:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [7:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [7:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [7:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [7:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [7:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [7:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 8'h40; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 8'h40; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [7:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 8'h40; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired \|\| fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module Router_9( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_3_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_3_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_3_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_3_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_4_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32] wire _vc_allocator_io_req_4_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_5_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_5_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_5_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_5_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_5_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_5_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_4_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_5_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_5_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_5_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_5_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_5_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_5_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_5_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_5_0_valid; // @[Router.scala:131:24] wire _switch_io_out_5_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_5_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_5_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_5_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_5_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_4_0_valid; // @[Router.scala:131:24] wire _switch_io_out_4_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_4_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_4_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_4_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_4_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_3_0_valid; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_3_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_5_to_20_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_5_to_20_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_5_to_20_io_out_valid; // @[Router.scala:125:13] wire _egress_unit_4_to_19_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_4_to_19_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_4_to_19_io_out_valid; // @[Router.scala:125:13] wire _output_unit_3_to_13_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_3_to_13_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_10_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_2_to_10_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_2_to_10_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_2_to_10_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_10_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_10_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_8_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_1_to_8_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_1_to_8_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_8_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_2_occupied; // @[Router.scala:122:13] wire [3:0] _ingress_unit_4_from_29_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_29_io_router_req_bits_flow_egress_node_id; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [144:0] _ingress_unit_4_from_29_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_29_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_4_from_29_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [2:0] _ingress_unit_4_from_29_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_4_from_29_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_29_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_29_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_in_ready; // @[Router.scala:116:13] wire [1:0] _input_unit_3_from_13_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_13_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_3_from_13_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_13_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_3_from_13_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_13_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_3_from_13_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_13_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_3_from_13_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_13_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_3_from_13_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_13_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_13_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_10_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_10_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_10_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_10_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_10_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_10_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_2_from_10_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_10_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_10_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_10_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_10_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_10_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_10_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_8_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_1_from_8_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_0_from_5_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_5_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_8_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_10_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _input_unit_3_from_13_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_4_ready & _ingress_unit_4_from_29_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_5; // @[Router.scala:203:29] reg fired_5; // @[Router.scala:204:26] wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_6; // @[Router.scala:203:29] reg fired_6; // @[Router.scala:204:26] wire _GEN_7 = _GEN_0 & fired_6; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module InputBuffer_33( // @[InputUnit.scala:49:7] input clock, // @[InputUnit.scala:49:7] input reset, // @[InputUnit.scala:49:7] input io_enq_0_valid, // @[InputUnit.scala:51:14] input io_enq_0_bits_head, // @[InputUnit.scala:51:14] input io_enq_0_bits_tail, // @[InputUnit.scala:51:14] input [72:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14] input [4:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14] output io_deq_0_bits_head, // @[InputUnit.scala:51:14] output io_deq_0_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14] output io_deq_1_bits_head, // @[InputUnit.scala:51:14] output io_deq_1_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14] input io_deq_2_ready, // @[InputUnit.scala:51:14] output io_deq_2_valid, // @[InputUnit.scala:51:14] output io_deq_2_bits_head, // @[InputUnit.scala:51:14] output io_deq_2_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14] input io_deq_3_ready, // @[InputUnit.scala:51:14] output io_deq_3_valid, // @[InputUnit.scala:51:14] output io_deq_3_bits_head, // @[InputUnit.scala:51:14] output io_deq_3_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_3_bits_payload, // @[InputUnit.scala:51:14] output io_deq_4_bits_head, // @[InputUnit.scala:51:14] output io_deq_4_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_4_bits_payload, // @[InputUnit.scala:51:14] output io_deq_5_bits_head, // @[InputUnit.scala:51:14] output io_deq_5_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_5_bits_payload, // @[InputUnit.scala:51:14] output io_deq_6_bits_head, // @[InputUnit.scala:51:14] output io_deq_6_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_6_bits_payload, // @[InputUnit.scala:51:14] output io_deq_7_bits_head, // @[InputUnit.scala:51:14] output io_deq_7_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_7_bits_payload, // @[InputUnit.scala:51:14] output io_deq_8_bits_head, // @[InputUnit.scala:51:14] output io_deq_8_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_8_bits_payload, // @[InputUnit.scala:51:14] output io_deq_9_bits_head, // @[InputUnit.scala:51:14] output io_deq_9_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_9_bits_payload, // @[InputUnit.scala:51:14] output io_deq_10_bits_head, // @[InputUnit.scala:51:14] output io_deq_10_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_10_bits_payload, // @[InputUnit.scala:51:14] output io_deq_11_bits_head, // @[InputUnit.scala:51:14] output io_deq_11_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_11_bits_payload, // @[InputUnit.scala:51:14] output io_deq_12_bits_head, // @[InputUnit.scala:51:14] output io_deq_12_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_12_bits_payload, // @[InputUnit.scala:51:14] output io_deq_13_bits_head, // @[InputUnit.scala:51:14] output io_deq_13_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_13_bits_payload, // @[InputUnit.scala:51:14] output io_deq_14_bits_head, // @[InputUnit.scala:51:14] output io_deq_14_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_14_bits_payload, // @[InputUnit.scala:51:14] output io_deq_15_bits_head, // @[InputUnit.scala:51:14] output io_deq_15_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_15_bits_payload, // @[InputUnit.scala:51:14] output io_deq_16_bits_head, // @[InputUnit.scala:51:14] output io_deq_16_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_16_bits_payload, // @[InputUnit.scala:51:14] output io_deq_17_bits_head, // @[InputUnit.scala:51:14] output io_deq_17_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_17_bits_payload, // @[InputUnit.scala:51:14] input io_deq_18_ready, // @[InputUnit.scala:51:14] output io_deq_18_valid, // @[InputUnit.scala:51:14] output io_deq_18_bits_head, // @[InputUnit.scala:51:14] output io_deq_18_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_18_bits_payload, // @[InputUnit.scala:51:14] input io_deq_19_ready, // @[InputUnit.scala:51:14] output io_deq_19_valid, // @[InputUnit.scala:51:14] output io_deq_19_bits_head, // @[InputUnit.scala:51:14] output io_deq_19_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_19_bits_payload, // @[InputUnit.scala:51:14] input io_deq_20_ready, // @[InputUnit.scala:51:14] output io_deq_20_valid, // @[InputUnit.scala:51:14] output io_deq_20_bits_head, // @[InputUnit.scala:51:14] output io_deq_20_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_20_bits_payload, // @[InputUnit.scala:51:14] input io_deq_21_ready, // @[InputUnit.scala:51:14] output io_deq_21_valid, // @[InputUnit.scala:51:14] output io_deq_21_bits_head, // @[InputUnit.scala:51:14] output io_deq_21_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_21_bits_payload // @[InputUnit.scala:51:14] ); wire _qs_21_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_20_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_19_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_18_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_17_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_16_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_15_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_14_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_13_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_12_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_11_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_10_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_9_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_8_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_7_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_6_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_5_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_4_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49] wire [74:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R4_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R5_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R6_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R7_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R8_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R9_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R10_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R11_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R12_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R13_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R14_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R15_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R16_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R17_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R18_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R19_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R20_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R21_data; // @[InputUnit.scala:85:18] reg [4:0] heads_0; // @[InputUnit.scala:86:24] reg [4:0] heads_1; // @[InputUnit.scala:86:24] reg [4:0] heads_2; // @[InputUnit.scala:86:24] reg [4:0] heads_3; // @[InputUnit.scala:86:24] reg [4:0] heads_4; // @[InputUnit.scala:86:24] reg [4:0] heads_5; // @[InputUnit.scala:86:24] reg [4:0] heads_6; // @[InputUnit.scala:86:24] reg [4:0] heads_7; // @[InputUnit.scala:86:24] reg [4:0] heads_8; // @[InputUnit.scala:86:24] reg [4:0] heads_9; // @[InputUnit.scala:86:24] reg [4:0] heads_10; // @[InputUnit.scala:86:24] reg [4:0] heads_11; // @[InputUnit.scala:86:24] reg [4:0] heads_12; // @[InputUnit.scala:86:24] reg [4:0] heads_13; // @[InputUnit.scala:86:24] reg [4:0] heads_14; // @[InputUnit.scala:86:24] reg [4:0] heads_15; // @[InputUnit.scala:86:24] reg [4:0] heads_16; // @[InputUnit.scala:86:24] reg [4:0] heads_17; // @[InputUnit.scala:86:24] reg [4:0] heads_18; // @[InputUnit.scala:86:24] reg [4:0] heads_19; // @[InputUnit.scala:86:24] reg [4:0] heads_20; // @[InputUnit.scala:86:24] reg [4:0] heads_21; // @[InputUnit.scala:86:24] reg [4:0] tails_0; // @[InputUnit.scala:87:24] reg [4:0] tails_1; // @[InputUnit.scala:87:24] reg [4:0] tails_2; // @[InputUnit.scala:87:24] reg [4:0] tails_3; // @[InputUnit.scala:87:24] reg [4:0] tails_4; // @[InputUnit.scala:87:24] reg [4:0] tails_5; // @[InputUnit.scala:87:24] reg [4:0] tails_6; // @[InputUnit.scala:87:24] reg [4:0] tails_7; // @[InputUnit.scala:87:24] reg [4:0] tails_8; // @[InputUnit.scala:87:24] reg [4:0] tails_9; // @[InputUnit.scala:87:24] reg [4:0] tails_10; // @[InputUnit.scala:87:24] reg [4:0] tails_11; // @[InputUnit.scala:87:24] reg [4:0] tails_12; // @[InputUnit.scala:87:24] reg [4:0] tails_13; // @[InputUnit.scala:87:24] reg [4:0] tails_14; // @[InputUnit.scala:87:24] reg [4:0] tails_15; // @[InputUnit.scala:87:24] reg [4:0] tails_16; // @[InputUnit.scala:87:24] reg [4:0] tails_17; // @[InputUnit.scala:87:24] reg [4:0] tails_18; // @[InputUnit.scala:87:24] reg [4:0] tails_19; // @[InputUnit.scala:87:24] reg [4:0] tails_20; // @[InputUnit.scala:87:24] reg [4:0] tails_21; // @[InputUnit.scala:87:24] wire _tails_T_66 = io_enq_0_bits_virt_channel_id == 5'h0; // @[Mux.scala:32:36] wire _tails_T_67 = io_enq_0_bits_virt_channel_id == 5'h1; // @[Mux.scala:32:36] wire _tails_T_68 = io_enq_0_bits_virt_channel_id == 5'h2; // @[Mux.scala:32:36] wire _tails_T_69 = io_enq_0_bits_virt_channel_id == 5'h3; // @[Mux.scala:32:36] wire _tails_T_70 = io_enq_0_bits_virt_channel_id == 5'h4; // @[Mux.scala:32:36] wire _tails_T_71 = io_enq_0_bits_virt_channel_id == 5'h5; // @[Mux.scala:32:36] wire _tails_T_72 = io_enq_0_bits_virt_channel_id == 5'h6; // @[Mux.scala:32:36] wire _tails_T_73 = io_enq_0_bits_virt_channel_id == 5'h7; // @[Mux.scala:32:36] wire _tails_T_74 = io_enq_0_bits_virt_channel_id == 5'h8; // @[Mux.scala:32:36] wire _tails_T_75 = io_enq_0_bits_virt_channel_id == 5'h9; // @[Mux.scala:32:36] wire _tails_T_76 = io_enq_0_bits_virt_channel_id == 5'hA; // @[Mux.scala:32:36] wire _tails_T_77 = io_enq_0_bits_virt_channel_id == 5'hB; // @[Mux.scala:32:36] wire _tails_T_78 = io_enq_0_bits_virt_channel_id == 5'hC; // @[Mux.scala:32:36] wire _tails_T_79 = io_enq_0_bits_virt_channel_id == 5'hD; // @[Mux.scala:32:36] wire _tails_T_80 = io_enq_0_bits_virt_channel_id == 5'hE; // @[Mux.scala:32:36] wire _tails_T_81 = io_enq_0_bits_virt_channel_id == 5'hF; // @[Mux.scala:32:36] wire _tails_T_82 = io_enq_0_bits_virt_channel_id == 5'h10; // @[Mux.scala:32:36] wire _tails_T_83 = io_enq_0_bits_virt_channel_id == 5'h11; // @[Mux.scala:32:36] wire _tails_T_84 = io_enq_0_bits_virt_channel_id == 5'h12; // @[Mux.scala:32:36] wire _tails_T_85 = io_enq_0_bits_virt_channel_id == 5'h13; // @[Mux.scala:32:36] wire _tails_T_86 = io_enq_0_bits_virt_channel_id == 5'h14; // @[Mux.scala:32:36] wire _tails_T_87 = io_enq_0_bits_virt_channel_id == 5'h15; // @[Mux.scala:32:36] wire direct_to_q = (_tails_T_66 & _qs_0_io_enq_ready \| _tails_T_67 & _qs_1_io_enq_ready \| _tails_T_68 & _qs_2_io_enq_ready \| _tails_T_69 & _qs_3_io_enq_ready \| _tails_T_70 & _qs_4_io_enq_ready \| _tails_T_71 & _qs_5_io_enq_ready \| _tails_T_72 & _qs_6_io_enq_ready \| _tails_T_73 & _qs_7_io_enq_ready \| _tails_T_74 & _qs_8_io_enq_ready \| _tails_T_75 & _qs_9_io_enq_ready \| _tails_T_76 & _qs_10_io_enq_ready \| _tails_T_77 & _qs_11_io_enq_ready \| _tails_T_78 & _qs_12_io_enq_ready \| _tails_T_79 & _qs_13_io_enq_ready \| _tails_T_80 & _qs_14_io_enq_ready \| _tails_T_81 & _qs_15_io_enq_ready \| _tails_T_82 & _qs_16_io_enq_ready \| _tails_T_83 & _qs_17_io_enq_ready \| _tails_T_84 & _qs_18_io_enq_ready \| _tails_T_85 & _qs_19_io_enq_ready \| _tails_T_86 & _qs_20_io_enq_ready \| _tails_T_87 & _qs_21_io_enq_ready) & (_tails_T_66 & heads_0 == tails_0 \| _tails_T_67 & heads_1 == tails_1 \| _tails_T_68 & heads_2 == tails_2 \| _tails_T_69 & heads_3 == tails_3 \| _tails_T_70 & heads_4 == tails_4 \| _tails_T_71 & heads_5 == tails_5 \| _tails_T_72 & heads_6 == tails_6 \| _tails_T_73 & heads_7 == tails_7 \| _tails_T_74 & heads_8 == tails_8 \| _tails_T_75 & heads_9 == tails_9 \| _tails_T_76 & heads_10 == tails_10 \| _tails_T_77 & heads_11 == tails_11 \| _tails_T_78 & heads_12 == tails_12 \| _tails_T_79 & heads_13 == tails_13 \| _tails_T_80 & heads_14 == tails_14 \| _tails_T_81 & heads_15 == tails_15 \| _tails_T_82 & heads_16 == tails_16 \| _tails_T_83 & heads_17 == tails_17 \| _tails_T_84 & heads_18 == tails_18 \| _tails_T_85 & heads_19 == tails_19 \| _tails_T_86 & heads_20 == tails_20 \| _tails_T_87 & heads_21 == tails_21); // @[Mux.scala:30:73, :32:36] wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}] wire [31:0][4:0] _GEN = {{tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_21}, {tails_20}, {tails_19}, {tails_18}, {tails_17}, {tails_16}, {tails_15}, {tails_14}, {tails_13}, {tails_12}, {tails_11}, {tails_10}, {tails_9}, {tails_8}, {tails_7}, {tails_6}, {tails_5}, {tails_4}, {tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16] wire _GEN_0 = io_enq_0_bits_virt_channel_id == 5'h0; // @[InputUnit.scala:103:45] wire _GEN_1 = io_enq_0_bits_virt_channel_id == 5'h1; // @[InputUnit.scala:103:45] wire _GEN_2 = io_enq_0_bits_virt_channel_id == 5'h2; // @[InputUnit.scala:103:45] wire _GEN_3 = io_enq_0_bits_virt_channel_id == 5'h3; // @[InputUnit.scala:103:45] wire _GEN_4 = io_enq_0_bits_virt_channel_id == 5'h4; // @[InputUnit.scala:103:45] wire _GEN_5 = io_enq_0_bits_virt_channel_id == 5'h5; // @[InputUnit.scala:103:45] wire _GEN_6 = io_enq_0_bits_virt_channel_id == 5'h6; // @[InputUnit.scala:103:45] wire _GEN_7 = io_enq_0_bits_virt_channel_id == 5'h7; // @[InputUnit.scala:103:45] wire _GEN_8 = io_enq_0_bits_virt_channel_id == 5'h8; // @[InputUnit.scala:103:45] wire _GEN_9 = io_enq_0_bits_virt_channel_id == 5'h9; // @[InputUnit.scala:103:45] wire _GEN_10 = io_enq_0_bits_virt_channel_id == 5'hA; // @[InputUnit.scala:103:45] wire _GEN_11 = io_enq_0_bits_virt_channel_id == 5'hB; // @[InputUnit.scala:103:45] wire _GEN_12 = io_enq_0_bits_virt_channel_id == 5'hC; // @[InputUnit.scala:103:45] wire _GEN_13 = io_enq_0_bits_virt_channel_id == 5'hD; // @[InputUnit.scala:103:45] wire _GEN_14 = io_enq_0_bits_virt_channel_id == 5'hE; // @[InputUnit.scala:103:45] wire _GEN_15 = io_enq_0_bits_virt_channel_id == 5'hF; // @[InputUnit.scala:103:45] wire _GEN_16 = io_enq_0_bits_virt_channel_id == 5'h10; // @[InputUnit.scala:103:45] wire _GEN_17 = io_enq_0_bits_virt_channel_id == 5'h11; // @[InputUnit.scala:103:45] wire _GEN_18 = io_enq_0_bits_virt_channel_id == 5'h12; // @[InputUnit.scala:103:45] wire _GEN_19 = io_enq_0_bits_virt_channel_id == 5'h13; // @[InputUnit.scala:103:45] wire _GEN_20 = io_enq_0_bits_virt_channel_id == 5'h14; // @[InputUnit.scala:103:45] wire _GEN_21 = io_enq_0_bits_virt_channel_id == 5'h15; // @[InputUnit.scala:103:45] wire _GEN_22 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34] wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_4 = heads_4 != tails_4 & _qs_4_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_5 = heads_5 != tails_5 & _qs_5_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_6 = heads_6 != tails_6 & _qs_6_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_7 = heads_7 != tails_7 & _qs_7_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_8 = heads_8 != tails_8 & _qs_8_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_9 = heads_9 != tails_9 & _qs_9_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_10 = heads_10 != tails_10 & _qs_10_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_11 = heads_11 != tails_11 & _qs_11_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_12 = heads_12 != tails_12 & _qs_12_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_13 = heads_13 != tails_13 & _qs_13_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_14 = heads_14 != tails_14 & _qs_14_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_15 = heads_15 != tails_15 & _qs_15_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_16 = heads_16 != tails_16 & _qs_16_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_17 = heads_17 != tails_17 & _qs_17_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_18 = heads_18 != tails_18 & _qs_18_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_19 = heads_19 != tails_19 & _qs_19_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_20 = heads_20 != tails_20 & _qs_20_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_21 = heads_21 != tails_21 & _qs_21_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire [21:0] to_q_oh_enc = can_to_q_0 ? 22'h1 : can_to_q_1 ? 22'h2 : can_to_q_2 ? 22'h4 : can_to_q_3 ? 22'h8 : can_to_q_4 ? 22'h10 : can_to_q_5 ? 22'h20 : can_to_q_6 ? 22'h40 : can_to_q_7 ? 22'h80 : can_to_q_8 ? 22'h100 : can_to_q_9 ? 22'h200 : can_to_q_10 ? 22'h400 : can_to_q_11 ? 22'h800 : can_to_q_12 ? 22'h1000 : can_to_q_13 ? 22'h2000 : can_to_q_14 ? 22'h4000 : can_to_q_15 ? 22'h8000 : can_to_q_16 ? 22'h10000 : can_to_q_17 ? 22'h20000 : can_to_q_18 ? 22'h40000 : can_to_q_19 ? 22'h80000 : can_to_q_20 ? 22'h100000 : {can_to_q_21, 21'h0}; // @[Mux.scala:50:70] wire _GEN_23 = can_to_q_0 \| can_to_q_1 \| can_to_q_2 \| can_to_q_3 \| can_to_q_4 \| can_to_q_5 \| can_to_q_6 \| can_to_q_7 \| can_to_q_8 \| can_to_q_9 \| can_to_q_10 \| can_to_q_11 \| can_to_q_12 \| can_to_q_13 \| can_to_q_14 \| can_to_q_15 \| can_to_q_16 \| can_to_q_17 \| can_to_q_18 \| can_to_q_19 \| can_to_q_20 \| can_to_q_21; // @[package.scala:81:59] wire [4:0] head = (to_q_oh_enc[0] ? heads_0 : 5'h0) \| (to_q_oh_enc[1] ? heads_1 : 5'h0) \| (to_q_oh_enc[2] ? heads_2 : 5'h0) \| (to_q_oh_enc[3] ? heads_3 : 5'h0) \| (to_q_oh_enc[4] ? heads_4 : 5'h0) \| (to_q_oh_enc[5] ? heads_5 : 5'h0) \| (to_q_oh_enc[6] ? heads_6 : 5'h0) \| (to_q_oh_enc[7] ? heads_7 : 5'h0) \| (to_q_oh_enc[8] ? heads_8 : 5'h0) \| (to_q_oh_enc[9] ? heads_9 : 5'h0) \| (to_q_oh_enc[10] ? heads_10 : 5'h0) \| (to_q_oh_enc[11] ? heads_11 : 5'h0) \| (to_q_oh_enc[12] ? heads_12 : 5'h0) \| (to_q_oh_enc[13] ? heads_13 : 5'h0) \| (to_q_oh_enc[14] ? heads_14 : 5'h0) \| (to_q_oh_enc[15] ? heads_15 : 5'h0) \| (to_q_oh_enc[16] ? heads_16 : 5'h0) \| (to_q_oh_enc[17] ? heads_17 : 5'h0) \| (to_q_oh_enc[18] ? heads_18 : 5'h0) \| (to_q_oh_enc[19] ? heads_19 : 5'h0) \| (to_q_oh_enc[20] ? heads_20 : 5'h0) \| (to_q_oh_enc[21] ? heads_21 : 5'h0); // @[OneHot.scala:83:30] wire _GEN_24 = _GEN_23 & to_q_oh_enc[0]; // @[OneHot.scala:83:30] wire _GEN_25 = _GEN_23 & to_q_oh_enc[1]; // @[OneHot.scala:83:30] wire _GEN_26 = _GEN_23 & to_q_oh_enc[2]; // @[OneHot.scala:83:30] wire _GEN_27 = _GEN_23 & to_q_oh_enc[3]; // @[OneHot.scala:83:30] wire _GEN_28 = _GEN_23 & to_q_oh_enc[4]; // @[OneHot.scala:83:30] wire _GEN_29 = _GEN_23 & to_q_oh_enc[5]; // @[OneHot.scala:83:30] wire _GEN_30 = _GEN_23 & to_q_oh_enc[6]; // @[OneHot.scala:83:30] wire _GEN_31 = _GEN_23 & to_q_oh_enc[7]; // @[OneHot.scala:83:30] wire _GEN_32 = _GEN_23 & to_q_oh_enc[8]; // @[OneHot.scala:83:30] wire _GEN_33 = _GEN_23 & to_q_oh_enc[9]; // @[OneHot.scala:83:30] wire _GEN_34 = _GEN_23 & to_q_oh_enc[10]; // @[OneHot.scala:83:30] wire _GEN_35 = _GEN_23 & to_q_oh_enc[11]; // @[OneHot.scala:83:30] wire _GEN_36 = _GEN_23 & to_q_oh_enc[12]; // @[OneHot.scala:83:30] wire _GEN_37 = _GEN_23 & to_q_oh_enc[13]; // @[OneHot.scala:83:30] wire _GEN_38 = _GEN_23 & to_q_oh_enc[14]; // @[OneHot.scala:83:30] wire _GEN_39 = _GEN_23 & to_q_oh_enc[15]; // @[OneHot.scala:83:30] wire _GEN_40 = _GEN_23 & to_q_oh_enc[16]; // @[OneHot.scala:83:30] wire _GEN_41 = _GEN_23 & to_q_oh_enc[17]; // @[OneHot.scala:83:30] wire _GEN_42 = _GEN_23 & to_q_oh_enc[18]; // @[OneHot.scala:83:30] wire _GEN_43 = _GEN_23 & to_q_oh_enc[19]; // @[OneHot.scala:83:30] wire _GEN_44 = _GEN_23 & to_q_oh_enc[20]; // @[OneHot.scala:83:30] wire _GEN_45 = _GEN_23 & to_q_oh_enc[21]; // @[OneHot.scala:83:30] wire [4:0] _tails_T_133 = _GEN[io_enq_0_bits_virt_channel_id] == ({1'h0, {1'h0, {1'h0, {2{_tails_T_68}}} \| {3{_tails_T_69}}} \| (_tails_T_84 ? 4'hB : 4'h0) \| {4{_tails_T_85}}} \| (_tails_T_86 ? 5'h13 : 5'h0) \| (_tails_T_87 ? 5'h17 : 5'h0)) ? {_tails_T_86, {_tails_T_84, _tails_T_69, 2'h0} \| (_tails_T_85 ? 4'hC : 4'h0)} \| (_tails_T_87 ? 5'h14 : 5'h0) : _GEN[io_enq_0_bits_virt_channel_id] + 5'h1; // @[Mux.scala:30:73, :32:36] wire [14:0] _to_q_T_2 = {10'h0, to_q_oh_enc[21:17]} \| to_q_oh_enc[15:1]; // @[OneHot.scala:31:18, :32:28] wire [6:0] _to_q_T_4 = _to_q_T_2[14:8] \| _to_q_T_2[6:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] _to_q_T_6 = _to_q_T_4[6:4] \| _to_q_T_4[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire _to_q_T_8 = _to_q_T_6[2] \| _to_q_T_6[0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [4:0] to_q = {\|(to_q_oh_enc[21:16]), \|(_to_q_T_2[14:7]), \|(_to_q_T_4[6:3]), \|(_to_q_T_6[2:1]), _to_q_T_8}; // @[OneHot.scala:30:18, :32:{10,14,28}] wire [4:0] _heads_T_89 = head == ({1'h0, {1'h0, {1'h0, {2{to_q_oh_enc[2]}}} \| {3{to_q_oh_enc[3]}}} \| (to_q_oh_enc[18] ? 4'hB : 4'h0) \| {4{to_q_oh_enc[19]}}} \| (to_q_oh_enc[20] ? 5'h13 : 5'h0) \| (to_q_oh_enc[21] ? 5'h17 : 5'h0)) ? {to_q_oh_enc[20], {to_q_oh_enc[18], to_q_oh_enc[3], 2'h0} \| (to_q_oh_enc[19] ? 4'hC : 4'h0)} \| (to_q_oh_enc[21] ? 5'h14 : 5'h0) : head + 5'h1; // @[OneHot.scala:83:30] always @(posedge clock) begin // @[InputUnit.scala:49:7] if (reset) begin // @[InputUnit.scala:49:7] heads_0 <= 5'h0; // @[InputUnit.scala:86:24] heads_1 <= 5'h0; // @[InputUnit.scala:86:24] heads_2 <= 5'h0; // @[InputUnit.scala:86:24] heads_3 <= 5'h4; // @[InputUnit.scala:86:24] heads_4 <= 5'h0; // @[InputUnit.scala:86:24] heads_5 <= 5'h0; // @[InputUnit.scala:86:24] heads_6 <= 5'h0; // @[InputUnit.scala:86:24] heads_7 <= 5'h0; // @[InputUnit.scala:86:24] heads_8 <= 5'h0; // @[InputUnit.scala:86:24] heads_9 <= 5'h0; // @[InputUnit.scala:86:24] heads_10 <= 5'h0; // @[InputUnit.scala:86:24] heads_11 <= 5'h0; // @[InputUnit.scala:86:24] heads_12 <= 5'h0; // @[InputUnit.scala:86:24] heads_13 <= 5'h0; // @[InputUnit.scala:86:24] heads_14 <= 5'h0; // @[InputUnit.scala:86:24] heads_15 <= 5'h0; // @[InputUnit.scala:86:24] heads_16 <= 5'h0; // @[InputUnit.scala:86:24] heads_17 <= 5'h0; // @[InputUnit.scala:86:24] heads_18 <= 5'h8; // @[InputUnit.scala:86:24] heads_19 <= 5'hC; // @[InputUnit.scala:86:24] heads_20 <= 5'h10; // @[InputUnit.scala:86:24] heads_21 <= 5'h14; // @[InputUnit.scala:86:24] tails_0 <= 5'h0; // @[InputUnit.scala:87:24] tails_1 <= 5'h0; // @[InputUnit.scala:87:24] tails_2 <= 5'h0; // @[InputUnit.scala:87:24] tails_3 <= 5'h4; // @[InputUnit.scala:87:24] tails_4 <= 5'h0; // @[InputUnit.scala:87:24] tails_5 <= 5'h0; // @[InputUnit.scala:87:24] tails_6 <= 5'h0; // @[InputUnit.scala:87:24] tails_7 <= 5'h0; // @[InputUnit.scala:87:24] tails_8 <= 5'h0; // @[InputUnit.scala:87:24] tails_9 <= 5'h0; // @[InputUnit.scala:87:24] tails_10 <= 5'h0; // @[InputUnit.scala:87:24] tails_11 <= 5'h0; // @[InputUnit.scala:87:24] tails_12 <= 5'h0; // @[InputUnit.scala:87:24] tails_13 <= 5'h0; // @[InputUnit.scala:87:24] tails_14 <= 5'h0; // @[InputUnit.scala:87:24] tails_15 <= 5'h0; // @[InputUnit.scala:87:24] tails_16 <= 5'h0; // @[InputUnit.scala:87:24] tails_17 <= 5'h0; // @[InputUnit.scala:87:24] tails_18 <= 5'h8; // @[InputUnit.scala:87:24] tails_19 <= 5'hC; // @[InputUnit.scala:87:24] tails_20 <= 5'h10; // @[InputUnit.scala:87:24] tails_21 <= 5'h14; // @[InputUnit.scala:87:24] end else begin // @[InputUnit.scala:49:7] if (_GEN_23 & {to_q_oh_enc[21:16], \|(_to_q_T_2[14:7]), \|(_to_q_T_4[6:3]), \|(_to_q_T_6[2:1]), _to_q_T_8} == 10'h0) // @[OneHot.scala:30:18, :32:{10,14,28}] heads_0 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h1) // @[OneHot.scala:32:10] heads_1 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h2) // @[OneHot.scala:32:10] heads_2 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h3) // @[OneHot.scala:32:10] heads_3 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h4) // @[OneHot.scala:32:10] heads_4 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h5) // @[OneHot.scala:32:10] heads_5 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h6) // @[OneHot.scala:32:10] heads_6 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h7) // @[OneHot.scala:32:10] heads_7 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h8) // @[OneHot.scala:32:10] heads_8 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h9) // @[OneHot.scala:32:10] heads_9 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hA) // @[OneHot.scala:32:10] heads_10 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hB) // @[OneHot.scala:32:10] heads_11 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hC) // @[OneHot.scala:32:10] heads_12 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hD) // @[OneHot.scala:32:10] heads_13 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hE) // @[OneHot.scala:32:10] heads_14 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hF) // @[OneHot.scala:32:10] heads_15 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h10) // @[OneHot.scala:32:10] heads_16 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h11) // @[OneHot.scala:32:10] heads_17 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h12) // @[OneHot.scala:32:10] heads_18 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h13) // @[OneHot.scala:32:10] heads_19 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h14) // @[OneHot.scala:32:10] heads_20 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h15) // @[OneHot.scala:32:10] heads_21 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_0 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_1 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_2 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_3) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_3 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_4) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_4 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_5) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_5 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_6) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_6 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_7) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_7 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_8) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_8 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_9) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_9 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_10) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_10 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_11) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_11 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_12) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_12 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_13) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_13 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_14) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_14 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_15) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_15 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_16) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_16 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_17) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_17 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_18) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_18 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_19) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_19 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_20) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_20 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_21) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_21 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Multiplier.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe} import freechips.rocketchip.util._ import ALU._ class MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle { val fn = Bits(SZ_ALU_FN.W) val dw = Bits(SZ_DW.W) val in1 = Bits(dataBits.W) val in2 = Bits(dataBits.W) val tag = UInt(tagBits.W) } class MultiplierResp(dataBits: Int, tagBits: Int) extends Bundle { val data = Bits(dataBits.W) val full_data = Bits((2dataBits).W) val tag = UInt(tagBits.W) } class MultiplierIO(val dataBits: Int, val tagBits: Int) extends Bundle { val req = Flipped(Decoupled(new MultiplierReq(dataBits, tagBits))) val kill = Input(Bool()) val resp = Decoupled(new MultiplierResp(dataBits, tagBits)) } case class MulDivParams( mulUnroll: Int = 1, divUnroll: Int = 1, mulEarlyOut: Boolean = false, divEarlyOut: Boolean = false, divEarlyOutGranularity: Int = 1 ) class MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module { private def minDivLatency = (cfg.divUnroll > 0).option(if (cfg.divEarlyOut) 3 else 1 + w/cfg.divUnroll) private def minMulLatency = (cfg.mulUnroll > 0).option(if (cfg.mulEarlyOut) 2 else w/cfg.mulUnroll) def minLatency: Int = (minDivLatency ++ minMulLatency).min val io = IO(new MultiplierIO(width, log2Up(nXpr))) val w = io.req.bits.in1.getWidth val mulw = if (cfg.mulUnroll == 0) w else (w + cfg.mulUnroll - 1) / cfg.mulUnroll cfg.mulUnroll val fastMulW = if (cfg.mulUnroll == 0) false else w/2 > cfg.mulUnroll && w % (2cfg.mulUnroll) == 0 val s_ready :: s_neg_inputs :: s_mul :: s_div :: s_dummy :: s_neg_output :: s_done_mul :: s_done_div :: Nil = Enum(8) val state = RegInit(s_ready) val req = Reg(chiselTypeOf(io.req.bits)) val count = Reg(UInt(log2Ceil( ((cfg.divUnroll != 0).option(w/cfg.divUnroll + 1).toSeq ++ (cfg.mulUnroll != 0).option(mulw/cfg.mulUnroll)).reduce(_ max _)).W)) val neg_out = Reg(Bool()) val isHi = Reg(Bool()) val resHi = Reg(Bool()) val divisor = Reg(Bits((w+1).W)) // div only needs w bits val remainder = Reg(Bits((2mulw+2).W)) // div only needs 2w+1 bits val mulDecode = List( FN_MUL -> List(Y, N, X, X), FN_MULH -> List(Y, Y, Y, Y), FN_MULHU -> List(Y, Y, N, N), FN_MULHSU -> List(Y, Y, Y, N)) val divDecode = List( FN_DIV -> List(N, N, Y, Y), FN_REM -> List(N, Y, Y, Y), FN_DIVU -> List(N, N, N, N), FN_REMU -> List(N, Y, N, N)) val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil = DecodeLogic(io.req.bits.fn, List(X, X, X, X), (if (cfg.divUnroll != 0) divDecode else Nil) ++ (if (cfg.mulUnroll != 0) mulDecode else Nil)).map(_.asBool) require(w == 32 \|\| w == 64) def halfWidth(req: MultiplierReq) = (w > 32).B && req.dw === DW_32 def sext(x: Bits, halfW: Bool, signed: Bool) = { val sign = signed && Mux(halfW, x(w/2-1), x(w-1)) val hi = Mux(halfW, Fill(w/2, sign), x(w-1,w/2)) (Cat(hi, x(w/2-1,0)), sign) } val (lhs_in, lhs_sign) = sext(io.req.bits.in1, halfWidth(io.req.bits), lhsSigned) val (rhs_in, rhs_sign) = sext(io.req.bits.in2, halfWidth(io.req.bits), rhsSigned) val subtractor = remainder(2w,w) - divisor val result = Mux(resHi, remainder(2w, w+1), remainder(w-1, 0)) val negated_remainder = -result if (cfg.divUnroll != 0) when (state === s_neg_inputs) { when (remainder(w-1)) { remainder := negated_remainder } when (divisor(w-1)) { divisor := subtractor } state := s_div } if (cfg.divUnroll != 0) when (state === s_neg_output) { remainder := negated_remainder state := s_done_div resHi := false.B } if (cfg.mulUnroll != 0) when (state === s_mul) { val mulReg = Cat(remainder(2mulw+1,w+1),remainder(w-1,0)) val mplierSign = remainder(w) val mplier = mulReg(mulw-1,0) val accum = mulReg(2mulw,mulw).asSInt val mpcand = divisor.asSInt val prod = Cat(mplierSign, mplier(cfg.mulUnroll-1, 0)).asSInt mpcand + accum val nextMulReg = Cat(prod, mplier(mulw-1, cfg.mulUnroll)) val nextMplierSign = count === (mulw/cfg.mulUnroll-2).U && neg_out val eOutMask = ((BigInt(-1) << mulw).S >> (count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))(mulw-1,0) val eOut = (cfg.mulEarlyOut).B && count =/= (mulw/cfg.mulUnroll-1).U && count =/= 0.U && !isHi && (mplier & ~eOutMask) === 0.U val eOutRes = (mulReg >> (mulw.U - count * cfg.mulUnroll.U)(log2Up(mulw)-1,0)) val nextMulReg1 = Cat(nextMulReg(2mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0)) remainder := Cat(nextMulReg1 >> w, nextMplierSign, nextMulReg1(w-1,0)) count := count + 1.U when (eOut \|\| count === (mulw/cfg.mulUnroll-1).U) { state := s_done_mul resHi := isHi } } if (cfg.divUnroll != 0) when (state === s_div) { val unrolls = ((0 until cfg.divUnroll) scanLeft remainder) { case (rem, i) => // the special case for iteration 0 is to save HW, not for correctness val difference = if (i == 0) subtractor else rem(2w,w) - divisor(w-1,0) val less = difference(w) Cat(Mux(less, rem(2w-1,w), difference(w-1,0)), rem(w-1,0), !less) }.tail remainder := unrolls.last when (count === (w/cfg.divUnroll).U) { state := Mux(neg_out, s_neg_output, s_done_div) resHi := isHi if (w % cfg.divUnroll < cfg.divUnroll - 1) remainder := unrolls(w % cfg.divUnroll) } count := count + 1.U val divby0 = count === 0.U && !subtractor(w) if (cfg.divEarlyOut) { val align = 1 << log2Floor(cfg.divUnroll max cfg.divEarlyOutGranularity) val alignMask = ~((align-1).U(log2Ceil(w).W)) val divisorMSB = Log2(divisor(w-1,0), w) & alignMask val dividendMSB = Log2(remainder(w-1,0), w) \| ~alignMask val eOutPos = ~(dividendMSB - divisorMSB) val eOut = count === 0.U && !divby0 && eOutPos >= align.U when (eOut) { remainder := remainder(w-1,0) << eOutPos count := eOutPos >> log2Floor(cfg.divUnroll) } } when (divby0 && !isHi) { neg_out := false.B } } when (io.resp.fire \|\| io.kill) { state := s_ready } when (io.req.fire) { state := Mux(cmdMul, s_mul, Mux(lhs_sign \|\| rhs_sign, s_neg_inputs, s_div)) isHi := cmdHi resHi := false.B count := (if (fastMulW) Mux[UInt](cmdMul && halfWidth(io.req.bits), (w/cfg.mulUnroll/2).U, 0.U) else 0.U) neg_out := Mux(cmdHi, lhs_sign, lhs_sign =/= rhs_sign) divisor := Cat(rhs_sign, rhs_in) remainder := lhs_in req := io.req.bits } val outMul = (state & (s_done_mul ^ s_done_div)) === (s_done_mul & ~s_done_div) val loOut = Mux(fastMulW.B && halfWidth(req) && outMul, result(w-1,w/2), result(w/2-1,0)) val hiOut = Mux(halfWidth(req), Fill(w/2, loOut(w/2-1)), result(w-1,w/2)) io.resp.bits.tag := req.tag io.resp.bits.data := Cat(hiOut, loOut) io.resp.bits.full_data := Cat(remainder(2w, w+1), remainder(w-1, 0)) io.resp.valid := (state === s_done_mul \|\| state === s_done_div) io.req.ready := state === s_ready } class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module with ShouldBeRetimed { val io = IO(new Bundle { val req = Flipped(Valid(new MultiplierReq(width, log2Ceil(nXpr)))) val resp = Valid(new MultiplierResp(width, log2Ceil(nXpr))) }) val in = Pipe(io.req) val decode = List( FN_MUL -> List(N, X, X), FN_MULH -> List(Y, Y, Y), FN_MULHU -> List(Y, N, N), FN_MULHSU -> List(Y, Y, N)) val cmdHi :: lhsSigned :: rhsSigned :: Nil = DecodeLogic(in.bits.fn, List(X, X, X), decode).map(_.asBool) val cmdHalf = (width > 32).B && in.bits.dw === DW_32 val lhs = Cat(lhsSigned && in.bits.in1(width-1), in.bits.in1).asSInt val rhs = Cat(rhsSigned && in.bits.in2(width-1), in.bits.in2).asSInt val prod = lhs * rhs val muxed = Mux(cmdHi, prod(2*width-1, width), Mux(cmdHalf, prod(width/2-1, 0).sextTo(width), prod(width-1, 0))) val resp = Pipe(in, latency-1) io.resp.valid := resp.valid io.resp.bits.tag := resp.bits.tag io.resp.bits.data := Pipe(in.valid, muxed, latency-1).bits io.resp.bits.full_data := Pipe(in.valid, prod, latency-1).bits.asUInt }	module MulDiv_2( // @[Multiplier.scala:40:7] input clock, // @[Multiplier.scala:40:7] input reset, // @[Multiplier.scala:40:7] output io_req_ready, // @[Multiplier.scala:45:14] input io_req_valid, // @[Multiplier.scala:45:14] input [4:0] io_req_bits_fn, // @[Multiplier.scala:45:14] input io_req_bits_dw, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in1, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in2, // @[Multiplier.scala:45:14] input [4:0] io_req_bits_tag, // @[Multiplier.scala:45:14] input io_kill, // @[Multiplier.scala:45:14] input io_resp_ready, // @[Multiplier.scala:45:14] output io_resp_valid, // @[Multiplier.scala:45:14] output [63:0] io_resp_bits_data, // @[Multiplier.scala:45:14] output [4:0] io_resp_bits_tag // @[Multiplier.scala:45:14] ); wire io_req_valid_0 = io_req_valid; // @[Multiplier.scala:40:7] wire [4:0] io_req_bits_fn_0 = io_req_bits_fn; // @[Multiplier.scala:40:7] wire io_req_bits_dw_0 = io_req_bits_dw; // @[Multiplier.scala:40:7] wire [63:0] io_req_bits_in1_0 = io_req_bits_in1; // @[Multiplier.scala:40:7] wire [63:0] io_req_bits_in2_0 = io_req_bits_in2; // @[Multiplier.scala:40:7] wire [4:0] io_req_bits_tag_0 = io_req_bits_tag; // @[Multiplier.scala:40:7] wire io_kill_0 = io_kill; // @[Multiplier.scala:40:7] wire io_resp_ready_0 = io_resp_ready; // @[Multiplier.scala:40:7] wire [5:0] alignMask = 6'h3F; // @[Multiplier.scala:149:23] wire [5:0] _dividendMSB_T_111 = 6'h0; // @[Multiplier.scala:151:53] wire [2:0] _outMul_T = 3'h1; // @[Multiplier.scala:175:37] wire [2:0] _outMul_T_2 = 3'h0; // @[Multiplier.scala:175:70] wire [2:0] _outMul_T_3 = 3'h0; // @[Multiplier.scala:175:68] wire _io_req_ready_T; // @[Multiplier.scala:183:25] wire _io_resp_valid_T_2; // @[Multiplier.scala:182:42] wire [63:0] _io_resp_bits_data_T; // @[Multiplier.scala:180:27] wire [127:0] _io_resp_bits_full_data_T_2; // @[Multiplier.scala:181:32] wire io_req_ready_0; // @[Multiplier.scala:40:7] wire [63:0] io_resp_bits_data_0; // @[Multiplier.scala:40:7] wire [127:0] io_resp_bits_full_data; // @[Multiplier.scala:40:7] wire [4:0] io_resp_bits_tag_0; // @[Multiplier.scala:40:7] wire io_resp_valid_0; // @[Multiplier.scala:40:7] reg [2:0] state; // @[Multiplier.scala:51:22] reg [4:0] req_fn; // @[Multiplier.scala:53:16] reg req_dw; // @[Multiplier.scala:53:16] reg [63:0] req_in1; // @[Multiplier.scala:53:16] reg [63:0] req_in2; // @[Multiplier.scala:53:16] reg [4:0] req_tag; // @[Multiplier.scala:53:16] assign io_resp_bits_tag_0 = req_tag; // @[Multiplier.scala:40:7, :53:16] reg [6:0] count; // @[Multiplier.scala:54:18] reg neg_out; // @[Multiplier.scala:57:20] reg isHi; // @[Multiplier.scala:58:17] reg resHi; // @[Multiplier.scala:59:18] reg [64:0] divisor; // @[Multiplier.scala:60:20] wire [64:0] mpcand = divisor; // @[Multiplier.scala:60:20, :111:26] reg [129:0] remainder; // @[Multiplier.scala:61:22] wire [2:0] decoded_plaInput; // @[pla.scala:77:22] wire [2:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [3:0] decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [3:0] decoded; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_3_2 = decoded_andMatrixOutputs_andMatrixInput_0; // @[pla.scala:91:29, :98:70] wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_4_2 = decoded_andMatrixOutputs_andMatrixInput_0_1; // @[pla.scala:91:29, :98:70] wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire [1:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_1_2 = decoded_andMatrixOutputs_andMatrixInput_0_4; // @[pla.scala:90:45, :98:70] wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T = {decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_1 = \|_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _decoded_orMatrixOutputs_T_2 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_3 = \|_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] _decoded_orMatrixOutputs_T_4 = {decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_5 = \|_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo = {_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoded_plaInput = io_req_bits_fn_0[2:0]; // @[pla.scala:77:22] wire cmdMul = decoded[3]; // @[pla.scala:81:23] wire cmdHi = decoded[2]; // @[pla.scala:81:23] wire lhsSigned = decoded[1]; // @[pla.scala:81:23] wire rhsSigned = decoded[0]; // @[pla.scala:81:23] wire _count_T_5 = ~io_req_bits_dw_0; // @[Multiplier.scala:40:7, :78:60] wire _sign_T = io_req_bits_in1_0[31]; // @[Multiplier.scala:40:7, :81:38] wire _sign_T_1 = io_req_bits_in1_0[63]; // @[Multiplier.scala:40:7, :81:48] wire _sign_T_2 = io_req_bits_dw_0 ? _sign_T_1 : _sign_T; // @[Multiplier.scala:40:7, :81:{29,38,48}] wire lhs_sign = lhsSigned & _sign_T_2; // @[Multiplier.scala:75:107, :81:{23,29}] wire [31:0] _hi_T = {32{lhs_sign}}; // @[Multiplier.scala:81:23, :82:29] wire [31:0] _hi_T_1 = io_req_bits_in1_0[63:32]; // @[Multiplier.scala:40:7, :82:43] wire [31:0] hi = io_req_bits_dw_0 ? _hi_T_1 : _hi_T; // @[Multiplier.scala:40:7, :82:{17,29,43}] wire [63:0] lhs_in = {hi, io_req_bits_in1_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}] wire _sign_T_3 = io_req_bits_in2_0[31]; // @[Multiplier.scala:40:7, :81:38] wire _sign_T_4 = io_req_bits_in2_0[63]; // @[Multiplier.scala:40:7, :81:48] wire _sign_T_5 = io_req_bits_dw_0 ? _sign_T_4 : _sign_T_3; // @[Multiplier.scala:40:7, :81:{29,38,48}] wire rhs_sign = rhsSigned & _sign_T_5; // @[Multiplier.scala:75:107, :81:{23,29}] wire [31:0] _hi_T_2 = {32{rhs_sign}}; // @[Multiplier.scala:81:23, :82:29] wire [31:0] _hi_T_3 = io_req_bits_in2_0[63:32]; // @[Multiplier.scala:40:7, :82:43] wire [31:0] hi_1 = io_req_bits_dw_0 ? _hi_T_3 : _hi_T_2; // @[Multiplier.scala:40:7, :82:{17,29,43}] wire [63:0] rhs_in = {hi_1, io_req_bits_in2_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}] wire [64:0] _subtractor_T = remainder[128:64]; // @[Multiplier.scala:61:22, :88:29] wire [65:0] _subtractor_T_1 = {1'h0, _subtractor_T} - {1'h0, divisor}; // @[Multiplier.scala:60:20, :88:{29,37}] wire [64:0] subtractor = _subtractor_T_1[64:0]; // @[Multiplier.scala:88:37] wire [63:0] _result_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36] wire [63:0] _io_resp_bits_full_data_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36, :181:42] wire [63:0] _result_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57] wire [63:0] _mulReg_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :107:55] wire [63:0] _unrolls_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :134:58] wire [63:0] _dividendMSB_T = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :151:39] wire [63:0] _remainder_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :155:31] wire [63:0] _io_resp_bits_full_data_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :181:63] wire [63:0] result = resHi ? _result_T : _result_T_1; // @[Multiplier.scala:59:18, :89:{19,36,57}] wire [64:0] _negated_remainder_T = 65'h0 - {1'h0, result}; // @[Multiplier.scala:89:19, :90:27] wire [63:0] negated_remainder = _negated_remainder_T[63:0]; // @[Multiplier.scala:90:27] wire [64:0] _mulReg_T = remainder[129:65]; // @[Multiplier.scala:61:22, :107:31] wire [128:0] mulReg = {_mulReg_T, _mulReg_T_1}; // @[Multiplier.scala:107:{21,31,55}] wire mplierSign = remainder[64]; // @[Multiplier.scala:61:22, :108:31] wire [63:0] mplier = mulReg[63:0]; // @[Multiplier.scala:107:21, :109:24] wire [64:0] _accum_T = mulReg[128:64]; // @[Multiplier.scala:107:21, :110:23] wire [64:0] accum = _accum_T; // @[Multiplier.scala:110:{23,37}] wire [7:0] _prod_T = mplier[7:0]; // @[Multiplier.scala:109:24, :112:38] wire [8:0] _prod_T_1 = {mplierSign, _prod_T}; // @[Multiplier.scala:108:31, :112:{19,38}] wire [8:0] _prod_T_2 = _prod_T_1; // @[Multiplier.scala:112:{19,60}] wire [73:0] _prod_T_3 = {{65{_prod_T_2[8]}}, _prod_T_2} * {{9{mpcand[64]}}, mpcand}; // @[Multiplier.scala:111:26, :112:{60,67}] wire [74:0] _prod_T_4 = {_prod_T_3[73], _prod_T_3} + {{10{accum[64]}}, accum}; // @[Multiplier.scala:110:37, :112:{67,76}] wire [73:0] _prod_T_5 = _prod_T_4[73:0]; // @[Multiplier.scala:112:76] wire [73:0] prod = _prod_T_5; // @[Multiplier.scala:112:76] wire [73:0] nextMulReg_hi = prod; // @[Multiplier.scala:112:76, :113:25] wire [55:0] _nextMulReg_T = mplier[63:8]; // @[Multiplier.scala:109:24, :113:38] wire [129:0] nextMulReg = {nextMulReg_hi, _nextMulReg_T}; // @[Multiplier.scala:113:{25,38}] wire _nextMplierSign_T = count == 7'h6; // @[Multiplier.scala:54:18, :114:32] wire nextMplierSign = _nextMplierSign_T & neg_out; // @[Multiplier.scala:57:20, :114:{32,61}] wire [10:0] _GEN = {1'h0, count, 3'h0}; // @[Multiplier.scala:54:18, :116:54] wire [10:0] _eOutMask_T; // @[Multiplier.scala:116:54] assign _eOutMask_T = _GEN; // @[Multiplier.scala:116:54] wire [10:0] _eOutRes_T; // @[Multiplier.scala:119:46] assign _eOutRes_T = _GEN; // @[Multiplier.scala:116:54, :119:46] wire [5:0] _eOutMask_T_1 = _eOutMask_T[5:0]; // @[Multiplier.scala:116:{54,72}] wire [64:0] _eOutMask_T_2 = $signed(65'sh10000000000000000 >>> _eOutMask_T_1); // @[Multiplier.scala:116:{44,72}] wire [63:0] eOutMask = _eOutMask_T_2[63:0]; // @[Multiplier.scala:116:{44,91}] wire _eOut_T = count != 7'h7; // @[Multiplier.scala:54:18, :117:45] wire _eOut_T_1 = _eOut_T; // @[Multiplier.scala:117:{36,45}] wire _eOut_T_2 = \|count; // @[Multiplier.scala:54:18, :117:83] wire _eOut_T_3 = _eOut_T_1 & _eOut_T_2; // @[Multiplier.scala:117:{36,74,83}] wire _eOut_T_4 = ~isHi; // @[Multiplier.scala:58:17, :118:7] wire _eOut_T_5 = _eOut_T_3 & _eOut_T_4; // @[Multiplier.scala:117:{74,91}, :118:7] wire [63:0] _eOut_T_6 = ~eOutMask; // @[Multiplier.scala:116:91, :118:26] wire [63:0] _eOut_T_7 = mplier & _eOut_T_6; // @[Multiplier.scala:109:24, :118:{24,26}] wire _eOut_T_8 = _eOut_T_7 == 64'h0; // @[Multiplier.scala:118:{24,37}] wire eOut = _eOut_T_5 & _eOut_T_8; // @[Multiplier.scala:117:91, :118:{13,37}] wire [11:0] _eOutRes_T_1 = 12'h40 - {1'h0, _eOutRes_T}; // @[Multiplier.scala:119:{38,46}] wire [10:0] _eOutRes_T_2 = _eOutRes_T_1[10:0]; // @[Multiplier.scala:119:38] wire [5:0] _eOutRes_T_3 = _eOutRes_T_2[5:0]; // @[Multiplier.scala:119:{38,64}] wire [128:0] eOutRes = mulReg >> _eOutRes_T_3; // @[Multiplier.scala:107:21, :119:{27,64}] wire [64:0] _nextMulReg1_T = nextMulReg[128:64]; // @[Multiplier.scala:113:25, :120:37] wire [129:0] _nextMulReg1_T_1 = eOut ? {1'h0, eOutRes} : nextMulReg; // @[Multiplier.scala:113:25, :118:13, :119:27, :120:55] wire [63:0] _nextMulReg1_T_2 = _nextMulReg1_T_1[63:0]; // @[Multiplier.scala:120:{55,82}] wire [128:0] nextMulReg1 = {_nextMulReg1_T, _nextMulReg1_T_2}; // @[Multiplier.scala:120:{26,37,82}] wire [64:0] _remainder_T = nextMulReg1[128:64]; // @[Multiplier.scala:120:26, :121:34] wire [63:0] _remainder_T_1 = nextMulReg1[63:0]; // @[Multiplier.scala:120:26, :121:67] wire [65:0] remainder_hi = {_remainder_T, nextMplierSign}; // @[Multiplier.scala:114:61, :121:{21,34}] wire [129:0] _remainder_T_2 = {remainder_hi, _remainder_T_1}; // @[Multiplier.scala:121:{21,67}] wire [7:0] _GEN_0 = {1'h0, count} + 8'h1; // @[Multiplier.scala:54:18, :123:20] wire [7:0] _count_T; // @[Multiplier.scala:123:20] assign _count_T = _GEN_0; // @[Multiplier.scala:123:20] wire [7:0] _count_T_2; // @[Multiplier.scala:144:20] assign _count_T_2 = _GEN_0; // @[Multiplier.scala:123:20, :144:20] wire [6:0] _count_T_1 = _count_T[6:0]; // @[Multiplier.scala:123:20] wire unrolls_less = subtractor[64]; // @[Multiplier.scala:88:37, :133:28] wire _divby0_T_1 = subtractor[64]; // @[Multiplier.scala:88:37, :133:28, :146:46] wire [63:0] _unrolls_T = remainder[127:64]; // @[Multiplier.scala:61:22, :134:24] wire [63:0] _unrolls_T_1 = subtractor[63:0]; // @[Multiplier.scala:88:37, :134:45] wire [63:0] _unrolls_T_2 = unrolls_less ? _unrolls_T : _unrolls_T_1; // @[Multiplier.scala:133:28, :134:{14,24,45}] wire _unrolls_T_4 = ~unrolls_less; // @[Multiplier.scala:133:28, :134:67] wire [127:0] unrolls_hi = {_unrolls_T_2, _unrolls_T_3}; // @[Multiplier.scala:134:{10,14,58}] wire [128:0] unrolls_0 = {unrolls_hi, _unrolls_T_4}; // @[Multiplier.scala:134:{10,67}] wire [2:0] _state_T = {1'h1, ~neg_out, 1'h1}; // @[Multiplier.scala:57:20, :139:19] wire [6:0] _count_T_3 = _count_T_2[6:0]; // @[Multiplier.scala:144:20] wire _divby0_T = ~(\|count); // @[Multiplier.scala:54:18, :117:83, :146:24] wire _divby0_T_2 = ~_divby0_T_1; // @[Multiplier.scala:146:{35,46}] wire divby0 = _divby0_T & _divby0_T_2; // @[Multiplier.scala:146:{24,32,35}] wire [63:0] _divisorMSB_T = divisor[63:0]; // @[Multiplier.scala:60:20, :150:36] wire [31:0] divisorMSB_hi = _divisorMSB_T[63:32]; // @[CircuitMath.scala:33:17] wire [31:0] divisorMSB_lo = _divisorMSB_T[31:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi = \|divisorMSB_hi; // @[CircuitMath.scala:33:17, :35:22] wire [15:0] divisorMSB_hi_1 = divisorMSB_hi[31:16]; // @[CircuitMath.scala:33:17] wire [15:0] divisorMSB_lo_1 = divisorMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_1 = \|divisorMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] divisorMSB_hi_2 = divisorMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] divisorMSB_lo_2 = divisorMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_2 = \|divisorMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_3 = divisorMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_3 = divisorMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_3 = \|divisorMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_1 = divisorMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_2 = divisorMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_3 = divisorMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_4 = _divisorMSB_T_2 ? 2'h2 : {1'h0, _divisorMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_5 = _divisorMSB_T_1 ? 2'h3 : _divisorMSB_T_4; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_6 = divisorMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_7 = divisorMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_8 = divisorMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_9 = _divisorMSB_T_7 ? 2'h2 : {1'h0, _divisorMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_10 = _divisorMSB_T_6 ? 2'h3 : _divisorMSB_T_9; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_11 = divisorMSB_useHi_3 ? _divisorMSB_T_5 : _divisorMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_12 = {divisorMSB_useHi_3, _divisorMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_4 = divisorMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_4 = divisorMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_4 = \|divisorMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_13 = divisorMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_14 = divisorMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_15 = divisorMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_16 = _divisorMSB_T_14 ? 2'h2 : {1'h0, _divisorMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_17 = _divisorMSB_T_13 ? 2'h3 : _divisorMSB_T_16; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_18 = divisorMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_19 = divisorMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_20 = divisorMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_21 = _divisorMSB_T_19 ? 2'h2 : {1'h0, _divisorMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_22 = _divisorMSB_T_18 ? 2'h3 : _divisorMSB_T_21; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_23 = divisorMSB_useHi_4 ? _divisorMSB_T_17 : _divisorMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_24 = {divisorMSB_useHi_4, _divisorMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_25 = divisorMSB_useHi_2 ? _divisorMSB_T_12 : _divisorMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_26 = {divisorMSB_useHi_2, _divisorMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] divisorMSB_hi_5 = divisorMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] divisorMSB_lo_5 = divisorMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_5 = \|divisorMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_6 = divisorMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_6 = divisorMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_6 = \|divisorMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_27 = divisorMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_28 = divisorMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_29 = divisorMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_30 = _divisorMSB_T_28 ? 2'h2 : {1'h0, _divisorMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_31 = _divisorMSB_T_27 ? 2'h3 : _divisorMSB_T_30; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_32 = divisorMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_33 = divisorMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_34 = divisorMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_35 = _divisorMSB_T_33 ? 2'h2 : {1'h0, _divisorMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_36 = _divisorMSB_T_32 ? 2'h3 : _divisorMSB_T_35; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_37 = divisorMSB_useHi_6 ? _divisorMSB_T_31 : _divisorMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_38 = {divisorMSB_useHi_6, _divisorMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_7 = divisorMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_7 = divisorMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_7 = \|divisorMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_39 = divisorMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_40 = divisorMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_41 = divisorMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_42 = _divisorMSB_T_40 ? 2'h2 : {1'h0, _divisorMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_43 = _divisorMSB_T_39 ? 2'h3 : _divisorMSB_T_42; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_44 = divisorMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_45 = divisorMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_46 = divisorMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_47 = _divisorMSB_T_45 ? 2'h2 : {1'h0, _divisorMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_48 = _divisorMSB_T_44 ? 2'h3 : _divisorMSB_T_47; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_49 = divisorMSB_useHi_7 ? _divisorMSB_T_43 : _divisorMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_50 = {divisorMSB_useHi_7, _divisorMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_51 = divisorMSB_useHi_5 ? _divisorMSB_T_38 : _divisorMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_52 = {divisorMSB_useHi_5, _divisorMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_53 = divisorMSB_useHi_1 ? _divisorMSB_T_26 : _divisorMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_54 = {divisorMSB_useHi_1, _divisorMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [15:0] divisorMSB_hi_8 = divisorMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17] wire [15:0] divisorMSB_lo_8 = divisorMSB_lo[15:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_8 = \|divisorMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] divisorMSB_hi_9 = divisorMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] divisorMSB_lo_9 = divisorMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_9 = \|divisorMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_10 = divisorMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_10 = divisorMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_10 = \|divisorMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_55 = divisorMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_56 = divisorMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_57 = divisorMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_58 = _divisorMSB_T_56 ? 2'h2 : {1'h0, _divisorMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_59 = _divisorMSB_T_55 ? 2'h3 : _divisorMSB_T_58; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_60 = divisorMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_61 = divisorMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_62 = divisorMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_63 = _divisorMSB_T_61 ? 2'h2 : {1'h0, _divisorMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_64 = _divisorMSB_T_60 ? 2'h3 : _divisorMSB_T_63; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_65 = divisorMSB_useHi_10 ? _divisorMSB_T_59 : _divisorMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_66 = {divisorMSB_useHi_10, _divisorMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_11 = divisorMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_11 = divisorMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_11 = \|divisorMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_67 = divisorMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_68 = divisorMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_69 = divisorMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_70 = _divisorMSB_T_68 ? 2'h2 : {1'h0, _divisorMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_71 = _divisorMSB_T_67 ? 2'h3 : _divisorMSB_T_70; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_72 = divisorMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_73 = divisorMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_74 = divisorMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_75 = _divisorMSB_T_73 ? 2'h2 : {1'h0, _divisorMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_76 = _divisorMSB_T_72 ? 2'h3 : _divisorMSB_T_75; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_77 = divisorMSB_useHi_11 ? _divisorMSB_T_71 : _divisorMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_78 = {divisorMSB_useHi_11, _divisorMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_79 = divisorMSB_useHi_9 ? _divisorMSB_T_66 : _divisorMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_80 = {divisorMSB_useHi_9, _divisorMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] divisorMSB_hi_12 = divisorMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] divisorMSB_lo_12 = divisorMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_12 = \|divisorMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_13 = divisorMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_13 = divisorMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_13 = \|divisorMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_81 = divisorMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_82 = divisorMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_83 = divisorMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_84 = _divisorMSB_T_82 ? 2'h2 : {1'h0, _divisorMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_85 = _divisorMSB_T_81 ? 2'h3 : _divisorMSB_T_84; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_86 = divisorMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_87 = divisorMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_88 = divisorMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_89 = _divisorMSB_T_87 ? 2'h2 : {1'h0, _divisorMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_90 = _divisorMSB_T_86 ? 2'h3 : _divisorMSB_T_89; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_91 = divisorMSB_useHi_13 ? _divisorMSB_T_85 : _divisorMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_92 = {divisorMSB_useHi_13, _divisorMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_14 = divisorMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_14 = divisorMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_14 = \|divisorMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_93 = divisorMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_94 = divisorMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_95 = divisorMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_96 = _divisorMSB_T_94 ? 2'h2 : {1'h0, _divisorMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_97 = _divisorMSB_T_93 ? 2'h3 : _divisorMSB_T_96; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_98 = divisorMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_99 = divisorMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_100 = divisorMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_101 = _divisorMSB_T_99 ? 2'h2 : {1'h0, _divisorMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_102 = _divisorMSB_T_98 ? 2'h3 : _divisorMSB_T_101; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_103 = divisorMSB_useHi_14 ? _divisorMSB_T_97 : _divisorMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_104 = {divisorMSB_useHi_14, _divisorMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_105 = divisorMSB_useHi_12 ? _divisorMSB_T_92 : _divisorMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_106 = {divisorMSB_useHi_12, _divisorMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_107 = divisorMSB_useHi_8 ? _divisorMSB_T_80 : _divisorMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_108 = {divisorMSB_useHi_8, _divisorMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_109 = divisorMSB_useHi ? _divisorMSB_T_54 : _divisorMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] _divisorMSB_T_110 = {divisorMSB_useHi, _divisorMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] divisorMSB = _divisorMSB_T_110; // @[CircuitMath.scala:36:10] wire [31:0] dividendMSB_hi = _dividendMSB_T[63:32]; // @[CircuitMath.scala:33:17] wire [31:0] dividendMSB_lo = _dividendMSB_T[31:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi = \|dividendMSB_hi; // @[CircuitMath.scala:33:17, :35:22] wire [15:0] dividendMSB_hi_1 = dividendMSB_hi[31:16]; // @[CircuitMath.scala:33:17] wire [15:0] dividendMSB_lo_1 = dividendMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_1 = \|dividendMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] dividendMSB_hi_2 = dividendMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] dividendMSB_lo_2 = dividendMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_2 = \|dividendMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_3 = dividendMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_3 = dividendMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_3 = \|dividendMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_1 = dividendMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_2 = dividendMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_3 = dividendMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_4 = _dividendMSB_T_2 ? 2'h2 : {1'h0, _dividendMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_5 = _dividendMSB_T_1 ? 2'h3 : _dividendMSB_T_4; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_6 = dividendMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_7 = dividendMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_8 = dividendMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_9 = _dividendMSB_T_7 ? 2'h2 : {1'h0, _dividendMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_10 = _dividendMSB_T_6 ? 2'h3 : _dividendMSB_T_9; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_11 = dividendMSB_useHi_3 ? _dividendMSB_T_5 : _dividendMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_12 = {dividendMSB_useHi_3, _dividendMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_4 = dividendMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_4 = dividendMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_4 = \|dividendMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_13 = dividendMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_14 = dividendMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_15 = dividendMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_16 = _dividendMSB_T_14 ? 2'h2 : {1'h0, _dividendMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_17 = _dividendMSB_T_13 ? 2'h3 : _dividendMSB_T_16; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_18 = dividendMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_19 = dividendMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_20 = dividendMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_21 = _dividendMSB_T_19 ? 2'h2 : {1'h0, _dividendMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_22 = _dividendMSB_T_18 ? 2'h3 : _dividendMSB_T_21; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_23 = dividendMSB_useHi_4 ? _dividendMSB_T_17 : _dividendMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_24 = {dividendMSB_useHi_4, _dividendMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_25 = dividendMSB_useHi_2 ? _dividendMSB_T_12 : _dividendMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_26 = {dividendMSB_useHi_2, _dividendMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] dividendMSB_hi_5 = dividendMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] dividendMSB_lo_5 = dividendMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_5 = \|dividendMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_6 = dividendMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_6 = dividendMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_6 = \|dividendMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_27 = dividendMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_28 = dividendMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_29 = dividendMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_30 = _dividendMSB_T_28 ? 2'h2 : {1'h0, _dividendMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_31 = _dividendMSB_T_27 ? 2'h3 : _dividendMSB_T_30; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_32 = dividendMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_33 = dividendMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_34 = dividendMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_35 = _dividendMSB_T_33 ? 2'h2 : {1'h0, _dividendMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_36 = _dividendMSB_T_32 ? 2'h3 : _dividendMSB_T_35; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_37 = dividendMSB_useHi_6 ? _dividendMSB_T_31 : _dividendMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_38 = {dividendMSB_useHi_6, _dividendMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_7 = dividendMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_7 = dividendMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_7 = \|dividendMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_39 = dividendMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_40 = dividendMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_41 = dividendMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_42 = _dividendMSB_T_40 ? 2'h2 : {1'h0, _dividendMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_43 = _dividendMSB_T_39 ? 2'h3 : _dividendMSB_T_42; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_44 = dividendMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_45 = dividendMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_46 = dividendMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_47 = _dividendMSB_T_45 ? 2'h2 : {1'h0, _dividendMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_48 = _dividendMSB_T_44 ? 2'h3 : _dividendMSB_T_47; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_49 = dividendMSB_useHi_7 ? _dividendMSB_T_43 : _dividendMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_50 = {dividendMSB_useHi_7, _dividendMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_51 = dividendMSB_useHi_5 ? _dividendMSB_T_38 : _dividendMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_52 = {dividendMSB_useHi_5, _dividendMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_53 = dividendMSB_useHi_1 ? _dividendMSB_T_26 : _dividendMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_54 = {dividendMSB_useHi_1, _dividendMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [15:0] dividendMSB_hi_8 = dividendMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17] wire [15:0] dividendMSB_lo_8 = dividendMSB_lo[15:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_8 = \|dividendMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] dividendMSB_hi_9 = dividendMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] dividendMSB_lo_9 = dividendMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_9 = \|dividendMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_10 = dividendMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_10 = dividendMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_10 = \|dividendMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_55 = dividendMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_56 = dividendMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_57 = dividendMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_58 = _dividendMSB_T_56 ? 2'h2 : {1'h0, _dividendMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_59 = _dividendMSB_T_55 ? 2'h3 : _dividendMSB_T_58; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_60 = dividendMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_61 = dividendMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_62 = dividendMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_63 = _dividendMSB_T_61 ? 2'h2 : {1'h0, _dividendMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_64 = _dividendMSB_T_60 ? 2'h3 : _dividendMSB_T_63; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_65 = dividendMSB_useHi_10 ? _dividendMSB_T_59 : _dividendMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_66 = {dividendMSB_useHi_10, _dividendMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_11 = dividendMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_11 = dividendMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_11 = \|dividendMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_67 = dividendMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_68 = dividendMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_69 = dividendMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_70 = _dividendMSB_T_68 ? 2'h2 : {1'h0, _dividendMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_71 = _dividendMSB_T_67 ? 2'h3 : _dividendMSB_T_70; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_72 = dividendMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_73 = dividendMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_74 = dividendMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_75 = _dividendMSB_T_73 ? 2'h2 : {1'h0, _dividendMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_76 = _dividendMSB_T_72 ? 2'h3 : _dividendMSB_T_75; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_77 = dividendMSB_useHi_11 ? _dividendMSB_T_71 : _dividendMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_78 = {dividendMSB_useHi_11, _dividendMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_79 = dividendMSB_useHi_9 ? _dividendMSB_T_66 : _dividendMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_80 = {dividendMSB_useHi_9, _dividendMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] dividendMSB_hi_12 = dividendMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] dividendMSB_lo_12 = dividendMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_12 = \|dividendMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_13 = dividendMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_13 = dividendMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_13 = \|dividendMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_81 = dividendMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_82 = dividendMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_83 = dividendMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_84 = _dividendMSB_T_82 ? 2'h2 : {1'h0, _dividendMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_85 = _dividendMSB_T_81 ? 2'h3 : _dividendMSB_T_84; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_86 = dividendMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_87 = dividendMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_88 = dividendMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_89 = _dividendMSB_T_87 ? 2'h2 : {1'h0, _dividendMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_90 = _dividendMSB_T_86 ? 2'h3 : _dividendMSB_T_89; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_91 = dividendMSB_useHi_13 ? _dividendMSB_T_85 : _dividendMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_92 = {dividendMSB_useHi_13, _dividendMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_14 = dividendMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_14 = dividendMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_14 = \|dividendMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_93 = dividendMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_94 = dividendMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_95 = dividendMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_96 = _dividendMSB_T_94 ? 2'h2 : {1'h0, _dividendMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_97 = _dividendMSB_T_93 ? 2'h3 : _dividendMSB_T_96; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_98 = dividendMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_99 = dividendMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_100 = dividendMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_101 = _dividendMSB_T_99 ? 2'h2 : {1'h0, _dividendMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_102 = _dividendMSB_T_98 ? 2'h3 : _dividendMSB_T_101; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_103 = dividendMSB_useHi_14 ? _dividendMSB_T_97 : _dividendMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_104 = {dividendMSB_useHi_14, _dividendMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_105 = dividendMSB_useHi_12 ? _dividendMSB_T_92 : _dividendMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_106 = {dividendMSB_useHi_12, _dividendMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_107 = dividendMSB_useHi_8 ? _dividendMSB_T_80 : _dividendMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_108 = {dividendMSB_useHi_8, _dividendMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_109 = dividendMSB_useHi ? _dividendMSB_T_54 : _dividendMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] _dividendMSB_T_110 = {dividendMSB_useHi, _dividendMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] dividendMSB = _dividendMSB_T_110; // @[CircuitMath.scala:36:10] wire [6:0] _eOutPos_T = {1'h0, dividendMSB} - {1'h0, divisorMSB}; // @[Multiplier.scala:150:48, :151:51, :152:35] wire [5:0] _eOutPos_T_1 = _eOutPos_T[5:0]; // @[Multiplier.scala:152:35] wire [5:0] eOutPos = ~_eOutPos_T_1; // @[Multiplier.scala:152:{21,35}] wire [5:0] _count_T_4 = eOutPos; // @[Multiplier.scala:152:21, :156:26] wire _eOut_T_9 = ~(\|count); // @[Multiplier.scala:54:18, :117:83, :146:24, :153:24] wire _eOut_T_10 = ~divby0; // @[Multiplier.scala:146:32, :153:35] wire _eOut_T_11 = _eOut_T_9 & _eOut_T_10; // @[Multiplier.scala:153:{24,32,35}] wire _eOut_T_12 = \|eOutPos; // @[Multiplier.scala:152:21, :153:54] wire eOut_1 = _eOut_T_11 & _eOut_T_12; // @[Multiplier.scala:153:{32,43,54}] wire [126:0] _remainder_T_4 = {63'h0, _remainder_T_3} << eOutPos; // @[Multiplier.scala:152:21, :155:{31,39}] wire _state_T_1 = lhs_sign \| rhs_sign; // @[Multiplier.scala:81:23, :165:46] wire [2:0] _state_T_2 = {1'h0, ~_state_T_1, 1'h1}; // @[Multiplier.scala:165:{36,46}] wire [2:0] _state_T_3 = cmdMul ? 3'h2 : _state_T_2; // @[Multiplier.scala:75:107, :165:{17,36}] wire _count_T_6 = _count_T_5; // @[Multiplier.scala:78:{50,60}] wire _count_T_7 = cmdMul & _count_T_6; // @[Multiplier.scala:75:107, :78:50, :168:46] wire [2:0] _count_T_8 = {_count_T_7, 2'h0}; // @[Multiplier.scala:168:{38,46}] wire _neg_out_T = lhs_sign != rhs_sign; // @[Multiplier.scala:81:23, :169:46] wire _neg_out_T_1 = cmdHi ? lhs_sign : _neg_out_T; // @[Multiplier.scala:75:107, :81:23, :169:{19,46}] wire [64:0] _divisor_T = {rhs_sign, rhs_in}; // @[Multiplier.scala:81:23, :83:9, :170:19] wire [2:0] _outMul_T_1 = state & 3'h1; // @[Multiplier.scala:51:22, :175:23] wire outMul = _outMul_T_1 == 3'h0; // @[Multiplier.scala:175:{23,52}] wire _loOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60] wire _loOut_T_1 = _loOut_T; // @[Multiplier.scala:78:{50,60}] wire _loOut_T_2 = _loOut_T_1; // @[Multiplier.scala:78:50, :176:30] wire _loOut_T_3 = _loOut_T_2 & outMul; // @[Multiplier.scala:175:52, :176:{30,48}] wire [31:0] _loOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65] wire [31:0] _hiOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65, :177:66] wire [31:0] _loOut_T_5 = result[31:0]; // @[Multiplier.scala:89:19, :176:82] wire [31:0] loOut = _loOut_T_3 ? _loOut_T_4 : _loOut_T_5; // @[Multiplier.scala:176:{18,48,65,82}] wire _hiOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60] wire _hiOut_T_1 = _hiOut_T; // @[Multiplier.scala:78:{50,60}] wire _hiOut_T_2 = loOut[31]; // @[Multiplier.scala:176:18, :177:50] wire [31:0] _hiOut_T_3 = {32{_hiOut_T_2}}; // @[Multiplier.scala:177:{39,50}] wire [31:0] hiOut = _hiOut_T_1 ? _hiOut_T_3 : _hiOut_T_4; // @[Multiplier.scala:78:50, :177:{18,39,66}] assign _io_resp_bits_data_T = {hiOut, loOut}; // @[Multiplier.scala:176:18, :177:18, :180:27] assign io_resp_bits_data_0 = _io_resp_bits_data_T; // @[Multiplier.scala:40:7, :180:27] assign _io_resp_bits_full_data_T_2 = {_io_resp_bits_full_data_T, _io_resp_bits_full_data_T_1}; // @[Multiplier.scala:181:{32,42,63}] assign io_resp_bits_full_data = _io_resp_bits_full_data_T_2; // @[Multiplier.scala:40:7, :181:32] wire _io_resp_valid_T = state == 3'h6; // @[Multiplier.scala:51:22, :182:27] wire _io_resp_valid_T_1 = &state; // @[Multiplier.scala:51:22, :182:51] assign _io_resp_valid_T_2 = _io_resp_valid_T \| _io_resp_valid_T_1; // @[Multiplier.scala:182:{27,42,51}] assign io_resp_valid_0 = _io_resp_valid_T_2; // @[Multiplier.scala:40:7, :182:42] assign _io_req_ready_T = state == 3'h0; // @[Multiplier.scala:51:22, :183:25] assign io_req_ready_0 = _io_req_ready_T; // @[Multiplier.scala:40:7, :183:25] wire _T_10 = state == 3'h1; // @[Multiplier.scala:51:22, :92:39] wire _T_13 = state == 3'h5; // @[Multiplier.scala:51:22, :101:39] wire _T_14 = state == 3'h2; // @[Multiplier.scala:51:22, :106:39] wire _GEN_1 = _T_14 & (eOut \| count == 7'h7); // @[Multiplier.scala:54:18, :101:57, :106:{39,50}, :118:13, :124:{16,25,55}, :125:13] wire _T_17 = state == 3'h3; // @[Multiplier.scala:51:22, :129:39] wire _T_18 = count == 7'h40; // @[Multiplier.scala:54:18, :138:17] wire _T_23 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Multiplier.scala:40:7] if (reset) // @[Multiplier.scala:40:7] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_T_23) // @[Decoupled.scala:51:35] state <= _state_T_3; // @[Multiplier.scala:51:22, :165:17] else if (io_resp_ready_0 & io_resp_valid_0 \| io_kill_0) // @[Decoupled.scala:51:35] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_T_17 & _T_18) // @[Multiplier.scala:106:50, :129:{39,50}, :138:{17,42}, :139:13] state <= _state_T; // @[Multiplier.scala:51:22, :139:19] else if (_GEN_1) // @[Multiplier.scala:101:57, :106:50, :124:55, :125:13] state <= 3'h6; // @[Multiplier.scala:51:22] else if (_T_13) // @[Multiplier.scala:101:39] state <= 3'h7; // @[Multiplier.scala:51:22] else if (_T_10) // @[Multiplier.scala:92:39] state <= 3'h3; // @[Multiplier.scala:51:22] if (_T_23) begin // @[Decoupled.scala:51:35] req_fn <= io_req_bits_fn_0; // @[Multiplier.scala:40:7, :53:16] req_dw <= io_req_bits_dw_0; // @[Multiplier.scala:40:7, :53:16] req_in1 <= io_req_bits_in1_0; // @[Multiplier.scala:40:7, :53:16] req_in2 <= io_req_bits_in2_0; // @[Multiplier.scala:40:7, :53:16] req_tag <= io_req_bits_tag_0; // @[Multiplier.scala:40:7, :53:16] count <= {4'h0, _count_T_8}; // @[Multiplier.scala:54:18, :114:32, :168:{11,38}] isHi <= cmdHi; // @[Multiplier.scala:58:17, :75:107] divisor <= _divisor_T; // @[Multiplier.scala:60:20, :170:19] remainder <= {66'h0, lhs_in}; // @[Multiplier.scala:61:22, :83:9, :94:17, :171:15] end else begin // @[Decoupled.scala:51:35] if (_T_17) begin // @[Multiplier.scala:129:39] count <= eOut_1 ? {1'h0, _count_T_4} : _count_T_3; // @[Multiplier.scala:54:18, :144:{11,20}, :153:43, :154:19, :156:{15,26}] remainder <= eOut_1 ? {3'h0, _remainder_T_4} : {1'h0, unrolls_0}; // @[Multiplier.scala:61:22, :134:10, :137:15, :153:43, :154:19, :155:{19,39}] end else if (_T_14) begin // @[Multiplier.scala:106:39] count <= _count_T_1; // @[Multiplier.scala:54:18, :123:20] remainder <= _remainder_T_2; // @[Multiplier.scala:61:22, :121:21] end else if (_T_13 \| _T_10 & remainder[63]) // @[Multiplier.scala:61:22, :92:{39,57}, :93:{20,27}, :94:17, :101:{39,57}, :102:15] remainder <= {66'h0, negated_remainder}; // @[Multiplier.scala:61:22, :90:27, :94:17] if (_T_10 & divisor[63]) // @[Multiplier.scala:60:20, :92:{39,57}, :96:{18,25}, :97:15] divisor <= subtractor; // @[Multiplier.scala:60:20, :88:37] end neg_out <= _T_23 ? _neg_out_T_1 : ~(_T_17 & divby0 & ~isHi) & neg_out; // @[Decoupled.scala:51:35] resHi <= ~_T_23 & (_T_17 & _T_18 \| _GEN_1 ? isHi : ~_T_13 & resHi); // @[Decoupled.scala:51:35] always @(posedge) assign io_req_ready = io_req_ready_0; // @[Multiplier.scala:40:7] assign io_resp_valid = io_resp_valid_0; // @[Multiplier.scala:40:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[Multiplier.scala:40:7] assign io_resp_bits_tag = io_resp_bits_tag_0; // @[Multiplier.scala:40:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_21(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /* This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }	module IntSyncCrossingSource_n1x1_2( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset // @[Crossing.scala:41:9] ); wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9] wire auto_out_sync_0 = 1'h0; // @[Crossing.scala:41:9] wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17] AsyncResetRegVec_w1_i0_2 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset) ); // @[AsyncResetReg.scala:86:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_36(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_69( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module RecFNToRecFN_206( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_4( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1502 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1502; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1502; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1575 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1575; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1428 = _T_1502 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1428 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1428 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1428 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1428 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1428 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1474 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1474 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1443 = _T_1575 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1443 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1443 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1443 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1546 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1546 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1528 = _T_1575 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1528 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1528 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1528 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels / // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /* Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) \| t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }	module NoCMonitor_28( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /* This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }	module IntSyncCrossingSource_n1x5_5( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] output auto_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_1, // @[LazyModuleImp.scala:107:25] output auto_out_sync_2, // @[LazyModuleImp.scala:107:25] output auto_out_sync_3, // @[LazyModuleImp.scala:107:25] output auto_out_sync_4 // @[LazyModuleImp.scala:107:25] ); wire [4:0] _reg_io_q; // @[AsyncResetReg.scala:86:21] wire [1:0] lo = 2'h0; // @[Crossing.scala:45:36] wire [1:0] hi_hi = 2'h0; // @[Crossing.scala:45:36] wire [2:0] hi = 3'h0; // @[Crossing.scala:45:36] wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_1 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_2 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_3 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_4 = 1'h0; // @[Crossing.scala:41:9] wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_1 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_2 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_3 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_4 = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire nodeOut_sync_1; // @[MixedNode.scala:542:17] wire nodeOut_sync_2; // @[MixedNode.scala:542:17] wire nodeOut_sync_3; // @[MixedNode.scala:542:17] wire nodeOut_sync_4; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] wire auto_out_sync_1_0; // @[Crossing.scala:41:9] wire auto_out_sync_2_0; // @[Crossing.scala:41:9] wire auto_out_sync_3_0; // @[Crossing.scala:41:9] wire auto_out_sync_4_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] assign auto_out_sync_1_0 = nodeOut_sync_1; // @[Crossing.scala:41:9] assign auto_out_sync_2_0 = nodeOut_sync_2; // @[Crossing.scala:41:9] assign auto_out_sync_3_0 = nodeOut_sync_3; // @[Crossing.scala:41:9] assign auto_out_sync_4_0 = nodeOut_sync_4; // @[Crossing.scala:41:9] assign nodeOut_sync_0 = _reg_io_q[0]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_1 = _reg_io_q[1]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_2 = _reg_io_q[2]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_3 = _reg_io_q[3]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_4 = _reg_io_q[4]; // @[AsyncResetReg.scala:86:21] AsyncResetRegVec_w5_i0_5 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_q (_reg_io_q) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_1 = auto_out_sync_1_0; // @[Crossing.scala:41:9] assign auto_out_sync_2 = auto_out_sync_2_0; // @[Crossing.scala:41:9] assign auto_out_sync_3 = auto_out_sync_3_0; // @[Crossing.scala:41:9] assign auto_out_sync_4 = auto_out_sync_4_0; // @[Crossing.scala:41:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_94( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_104 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module TLFragmenter_UART( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30] wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [9:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [28:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71] wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49] wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18] wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} \| ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] dFirst_size = {\|dFirst_size_hi, \|(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] \| _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (\|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}] wire anonOut_d_ready = auto_anon_in_d_ready \| drop; // @[Fragmenter.scala:234:30, :235:35] wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}] wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}] reg aToggle_r; // @[Fragmenter.scala:309:54]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_49( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_428( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_172 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_6( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1339 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1339; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1339; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1412 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1412; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1412; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1412; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1265 = _T_1339 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1265 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1265 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1265 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1265 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1265 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1311 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1311 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1280 = _T_1412 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1280 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1280 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1280 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1383 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1383 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1365 = _T_1412 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1365 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1365 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1365 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_63( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_5 = 2'h1 << _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1184 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1153 = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1153 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1153 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1153 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1238 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1238 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1238 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1238 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_34( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [2:0] b_first_counter; // @[Edges.scala:229:27] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [2:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [34:0] inflight; // @[Monitor.scala:614:27] reg [139:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [139:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [63:0] _GEN_1 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [63:0] _GEN_4 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [34:0] inflight_1; // @[Monitor.scala:726:35] reg [139:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [63:0] _GEN_6 = {58'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [6:0] inflight_2; // @[Monitor.scala:828:27] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35] wire [6:0] d_set = _GEN_8 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLBuffer_a29d64s9k1z3u_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [8:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [8:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_8 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a29d64s9k1z3u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a29d64s9k1z3u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /* This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }	module IntSyncCrossingSource_n1x1_9( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset // @[Crossing.scala:41:9] ); wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9] wire auto_out_sync_0 = 1'h0; // @[Crossing.scala:41:9] wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17] AsyncResetRegVec_w1_i0_9 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset) ); // @[AsyncResetReg.scala:86:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_34( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_732; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_732; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_805; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_805; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_805; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_658 = _T_732 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_658 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_704 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_673 = _T_805 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_673 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_776 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_758 = _T_805 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_758 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Tilelink.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} trait TLFieldHelper { def getBodyFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.mask, b.data, b.corrupt) case b: TLBundleB => Seq(b.mask, b.data, b.corrupt) case b: TLBundleC => Seq( b.data, b.corrupt) case b: TLBundleD => Seq( b.data, b.corrupt) case b: TLBundleE => Seq() } def getConstFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address ) case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied) case b: TLBundleE => Seq( b.sink ) } def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits)) } class TLMasterToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2)) a.io.protocol <> io.tilelink.a io.tilelink.b <> b.io.protocol c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol e.io.protocol <> io.tilelink.e io.flits.a <> a.io.flit b.io.flit <> io.flits.b io.flits.c <> c.io.flit d.io.flit <> io.flits.d io.flits.e <> e.io.flit } class TLMasterACDToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) a.io.protocol <> io.tilelink.a c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol io.flits.a <> a.io.flit io.flits.c <> c.io.flit d.io.flit <> io.flits.d } class TLMasterBEToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0)) io.tilelink.b <> b.io.protocol e.io.protocol <> io.tilelink.e b.io.flit <> io.flits.b io.flits.e <> e.io.flit } class TLSlaveToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val b = Decoupled(new IngressFlit(flitWidth)) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) io.tilelink.a <> a.io.protocol b.io.protocol <> io.tilelink.b io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d io.tilelink.e <> e.io.protocol a.io.flit <> io.flits.a io.flits.b <> b.io.flit c.io.flit <> io.flits.c io.flits.d <> d.io.flit e.io.flit <> io.flits.e } class TLSlaveACDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart)) io.tilelink.a <> a.io.protocol io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d a.io.flit <> io.flits.a c.io.flit <> io.flits.c io.flits.d <> d.io.flit } class TLSlaveBEToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val b = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) b.io.protocol <> io.tilelink.b io.tilelink.e <> e.io.protocol io.flits.b <> b.io.flit e.io.flit <> io.flits.e } class TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle { val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) }) val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) }) } trait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper { def edgesIn: Seq[TLEdge] def edgesOut: Seq[TLEdge] def edgeInNodes: Seq[Int] def edgeOutNodes: Seq[Int] require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size) def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle)) def genBundle = new TLBundle(wideBundle) def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut) } object TLConnect { def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = { l.valid := r.valid r.ready := l.ready l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll } } // BEGIN: TileLinkProtocolParams case class TileLinkABCDEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int] ) extends TileLinkProtocolParams { // END: TileLinkProtocolParams val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten val nVirtualNetworks = 5 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A (if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B (if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D (if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { edgesIn.zipWithIndex.map { case (e,i) => val nif_master = Module(new TLMasterToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 3 + edgesIn.size * 2 + egressOffset, minPayloadWidth )) nif_master.io.tilelink := DontCare nif_master.io.tilelink.a.valid := false.B nif_master.io.tilelink.c.valid := false.B nif_master.io.tilelink.e.valid := false.B TLConnect(nif_master.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master.io.tilelink.b) TLConnect(nif_master.io.tilelink.c, protocol.in(i).c) TLConnect(nif_master.io.tilelink.e, protocol.in(i).e) } ingresses(i * 3 + 0).flit <> nif_master.io.flits.a ingresses(i * 3 + 1).flit <> nif_master.io.flits.c ingresses(i * 3 + 2).flit <> nif_master.io.flits.e nif_master.io.flits.b <> egresses(i * 2 + 0).flit nif_master.io.flits.d <> egresses(i * 2 + 1).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave = Module(new TLSlaveToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 2 + egressOffset, minPayloadWidth )) nif_slave.io.tilelink := DontCare nif_slave.io.tilelink.b.valid := false.B nif_slave.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a) TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b) TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c) TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e) } ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit } } } } } case class TileLinkACDProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val nVirtualNetworks = 3 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A (if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_acd = Module(new TLMasterACDToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 2 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_acd.io.tilelink := DontCare nif_master_acd.io.tilelink.a.valid := false.B nif_master_acd.io.tilelink.c.valid := false.B nif_master_acd.io.tilelink.e.valid := false.B TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c) } ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_acd = Module(new TLSlaveACDToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_acd.io.tilelink := DontCare nif_slave_acd.io.tilelink.b.valid := false.B nif_slave_acd.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a) TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c) } ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit } }} } } case class TileLinkBEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val nVirtualNetworks = 2 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B (if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_be = Module(new TLMasterBEToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 1 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_be.io.tilelink := DontCare nif_master_be.io.tilelink.a.valid := false.B nif_master_be.io.tilelink.c.valid := false.B nif_master_be.io.tilelink.e.valid := false.B if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b) TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e) } ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_be = Module(new TLSlaveBEToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_be.io.tilelink := DontCare nif_slave_be.io.tilelink.b.valid := false.B nif_slave_be.io.tilelink.d.valid := false.B if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e) TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b) } ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit } }} } } abstract class TLNoCLike(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") // TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers port.managers map { manager => manager.v1copy(fifoId = None) } } ) } ) } abstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) { val edgesIn: Seq[TLEdge] val edgesOut: Seq[TLEdge] val nodeMapping: DiplomaticNetworkNodeMapping val nocName: String lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name))) lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name))) lazy val edgeInNodes = nodeMapping.getNodesIn(inNames) lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames) def printNodeMappings() { println(s"Constellation: TLNoC $nocName inwards mapping:") for ((n, i) <- inNames zip edgeInNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } println(s"Constellation: TLNoC $nocName outwards mapping:") for ((n, i) <- outNames zip edgeOutNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } } } trait TLNoCParams // Instantiates a private TLNoC. Replaces the TLXbar // BEGIN: TLNoCParams case class SimpleTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, nocParams: NoCParams = NoCParams(), ) extends TLNoCParams class TLNoC(params: SimpleTLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { // END: TLNoCParams override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val noc = Module(new ProtocolNoC(ProtocolNoCParams( params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC), Seq(protocolParams), inlineNoC = inlineNoC ))) noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } } case class SplitACDxBETLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, acdNoCParams: NoCParams = NoCParams(), beNoCParams: NoCParams = NoCParams(), beDivision: Int = 2 ) extends TLNoCParams class TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val acdProtocolParams = TileLinkACDProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val beProtocolParams = TileLinkBEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.acdNoCParams.copy(hasCtrl = false, nocName=s"${name}_acd", inlineNoC = inlineNoC), Seq(acdProtocolParams), inlineNoC = inlineNoC ))) val be_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.beNoCParams.copy(hasCtrl = false, nocName=s"${name}_be", inlineNoC = inlineNoC), Seq(beProtocolParams), widthDivision = params.beDivision, inlineNoC = inlineNoC ))) acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } }} be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.b <> r.b l.e <> r.e } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.b <> r.b l.e <> r.e } }} } } case class GlobalTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping ) extends TLNoCParams // Maps this interconnect onto a global NoC class TLGlobalNoC(params: GlobalTLNoCParams, name: String = "test")(implicit p: Parameters) extends TLNoCLike { lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) printNodeMappings() val io_global = IO(Flipped(protocolParams.genIO())) io_global match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } }	module TLMasterToNoC_2( // @[Tilelink.scala:37:7] input clock, // @[Tilelink.scala:37:7] input reset, // @[Tilelink.scala:37:7] output io_tilelink_a_ready, // @[Tilelink.scala:44:14] input io_tilelink_a_valid, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:44:14] input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:44:14] input [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:44:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:44:14] input [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:44:14] input [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:44:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:44:14] input io_tilelink_b_ready, // @[Tilelink.scala:44:14] output io_tilelink_b_valid, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_b_bits_opcode, // @[Tilelink.scala:44:14] output [1:0] io_tilelink_b_bits_param, // @[Tilelink.scala:44:14] output [3:0] io_tilelink_b_bits_size, // @[Tilelink.scala:44:14] output [5:0] io_tilelink_b_bits_source, // @[Tilelink.scala:44:14] output [31:0] io_tilelink_b_bits_address, // @[Tilelink.scala:44:14] output [7:0] io_tilelink_b_bits_mask, // @[Tilelink.scala:44:14] output [63:0] io_tilelink_b_bits_data, // @[Tilelink.scala:44:14] output io_tilelink_b_bits_corrupt, // @[Tilelink.scala:44:14] output io_tilelink_c_ready, // @[Tilelink.scala:44:14] input io_tilelink_c_valid, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:44:14] input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:44:14] input [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:44:14] input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:44:14] input [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:44:14] input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:44:14] input io_tilelink_d_ready, // @[Tilelink.scala:44:14] output io_tilelink_d_valid, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:44:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:44:14] output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:44:14] output [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:44:14] output [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:44:14] output [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:44:14] output io_tilelink_e_ready, // @[Tilelink.scala:44:14] input io_tilelink_e_valid, // @[Tilelink.scala:44:14] input [4:0] io_tilelink_e_bits_sink, // @[Tilelink.scala:44:14] input io_flits_a_ready, // @[Tilelink.scala:44:14] output io_flits_a_valid, // @[Tilelink.scala:44:14] output io_flits_a_bits_head, // @[Tilelink.scala:44:14] output io_flits_a_bits_tail, // @[Tilelink.scala:44:14] output [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:44:14] output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:44:14] output io_flits_b_ready, // @[Tilelink.scala:44:14] input io_flits_b_valid, // @[Tilelink.scala:44:14] input io_flits_b_bits_head, // @[Tilelink.scala:44:14] input io_flits_b_bits_tail, // @[Tilelink.scala:44:14] input [72:0] io_flits_b_bits_payload, // @[Tilelink.scala:44:14] input io_flits_c_ready, // @[Tilelink.scala:44:14] output io_flits_c_valid, // @[Tilelink.scala:44:14] output io_flits_c_bits_head, // @[Tilelink.scala:44:14] output io_flits_c_bits_tail, // @[Tilelink.scala:44:14] output [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:44:14] output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:44:14] output io_flits_d_ready, // @[Tilelink.scala:44:14] input io_flits_d_valid, // @[Tilelink.scala:44:14] input io_flits_d_bits_head, // @[Tilelink.scala:44:14] input io_flits_d_bits_tail, // @[Tilelink.scala:44:14] input [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:44:14] input io_flits_e_ready, // @[Tilelink.scala:44:14] output io_flits_e_valid, // @[Tilelink.scala:44:14] output io_flits_e_bits_head, // @[Tilelink.scala:44:14] output [72:0] io_flits_e_bits_payload, // @[Tilelink.scala:44:14] output [4:0] io_flits_e_bits_egress_id // @[Tilelink.scala:44:14] ); wire [4:0] _e_io_flit_bits_payload; // @[Tilelink.scala:58:17] wire [64:0] _c_io_flit_bits_payload; // @[Tilelink.scala:56:17] TLAToNoC_2 a ( // @[Tilelink.scala:54:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:54:17] TLBFromNoC_1 b ( // @[Tilelink.scala:55:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_b_ready), .io_protocol_valid (io_tilelink_b_valid), .io_protocol_bits_opcode (io_tilelink_b_bits_opcode), .io_protocol_bits_param (io_tilelink_b_bits_param), .io_protocol_bits_size (io_tilelink_b_bits_size), .io_protocol_bits_source (io_tilelink_b_bits_source), .io_protocol_bits_address (io_tilelink_b_bits_address), .io_protocol_bits_mask (io_tilelink_b_bits_mask), .io_protocol_bits_data (io_tilelink_b_bits_data), .io_protocol_bits_corrupt (io_tilelink_b_bits_corrupt), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail), .io_flit_bits_payload (io_flits_b_bits_payload) ); // @[Tilelink.scala:55:17] TLCToNoC_2 c ( // @[Tilelink.scala:56:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (_c_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_c_bits_egress_id) ); // @[Tilelink.scala:56:17] TLDFromNoC_1 d ( // @[Tilelink.scala:57:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[64:0]) // @[Tilelink.scala:68:14] ); // @[Tilelink.scala:57:17] TLEToNoC e ( // @[Tilelink.scala:58:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_e_ready), .io_protocol_valid (io_tilelink_e_valid), .io_protocol_bits_sink (io_tilelink_e_bits_sink), .io_flit_ready (io_flits_e_ready), .io_flit_valid (io_flits_e_valid), .io_flit_bits_head (io_flits_e_bits_head), .io_flit_bits_payload (_e_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_e_bits_egress_id) ); // @[Tilelink.scala:58:17] assign io_flits_c_bits_payload = {8'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :56:17, :67:14] assign io_flits_e_bits_payload = {68'h0, _e_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :58:17, :69:14] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_60( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_237( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }	module dataArrayB1Way_0_0( // @[DescribedSRAM.scala:17:26] input [7:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [63:0] RW0_wdata, output [63:0] RW0_rdata ); dataArrayB0Way_0_ext dataArrayB0Way_0_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File CustomCSRs.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import org.chipsalliance.cde.config.Parameters case class CustomCSR(id: Int, mask: BigInt, init: Option[BigInt]) object CustomCSR { def constant(id: Int, value: BigInt): CustomCSR = CustomCSR(id, BigInt(0), Some(value)) } class CustomCSRIO(implicit p: Parameters) extends CoreBundle { val ren = Output(Bool()) // set by CSRFile, indicates an instruction is reading the CSR val wen = Output(Bool()) // set by CSRFile, indicates an instruction is writing the CSR val wdata = Output(UInt(xLen.W)) // wdata provided by instruction writing CSR val value = Output(UInt(xLen.W)) // current value of CSR in CSRFile val stall = Input(Bool()) // reads and writes to this CSR should stall (must be bounded) val set = Input(Bool()) // set/sdata enables external agents to set the value of this CSR val sdata = Input(UInt(xLen.W)) } class CustomCSRs(implicit p: Parameters) extends CoreBundle { // Not all cores have these CSRs, but those that do should follow the same // numbering conventions. So we list them here but default them to None. protected def bpmCSRId = 0x7c0 protected def bpmCSR: Option[CustomCSR] = None protected def chickenCSRId = 0x7c1 protected def chickenCSR: Option[CustomCSR] = None // If you override this, you'll want to concatenate super.decls def decls: Seq[CustomCSR] = bpmCSR.toSeq ++ chickenCSR val csrs = Vec(decls.size, new CustomCSRIO) def flushBTB = getOrElse(bpmCSR, _.wen, false.B) def bpmStatic = getOrElse(bpmCSR, _.value(0), false.B) def disableDCacheClockGate = getOrElse(chickenCSR, _.value(0), false.B) def disableICacheClockGate = getOrElse(chickenCSR, _.value(1), false.B) def disableCoreClockGate = getOrElse(chickenCSR, _.value(2), false.B) def disableSpeculativeICacheRefill = getOrElse(chickenCSR, _.value(3), false.B) def suppressCorruptOnGrantData = getOrElse(chickenCSR, _.value(9), false.B) protected def getByIdOrElse[T](id: Int, f: CustomCSRIO => T, alt: T): T = { val idx = decls.indexWhere(_.id == id) if (idx < 0) alt else f(csrs(idx)) } protected def getOrElse[T](csr: Option[CustomCSR], f: CustomCSRIO => T, alt: T): T = csr.map(c => getByIdOrElse(c.id, f, alt)).getOrElse(alt) } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File Events.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.log2Ceil import freechips.rocketchip.util._ import freechips.rocketchip.util.property class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bool)]) { def size = events.size val hits = WireDefault(VecInit(Seq.fill(size)(false.B))) def check(mask: UInt) = { hits := events.map(_._2()) gate(mask, hits.asUInt) } def dump(): Unit = { for (((name, _), i) <- events.zipWithIndex) when (check(1.U << i)) { printf(s"Event $name\n") } } def withCovers: Unit = { events.zipWithIndex.foreach { case ((name, func), i) => property.cover(gate((1.U << i), (func() << i)), name) } } } class EventSets(val eventSets: Seq[EventSet]) { def maskEventSelector(eventSel: UInt): UInt = { // allow full associativity between counters and event sets (for now?) val setMask = (BigInt(1) << eventSetIdBits) - 1 val maskMask = ((BigInt(1) << eventSets.map(_.size).max) - 1) << maxEventSetIdBits eventSel & (setMask \| maskMask).U } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } def evaluate(eventSel: UInt): Bool = { val (set, mask) = decode(eventSel) val sets = for (e <- eventSets) yield { require(e.hits.getWidth <= mask.getWidth, s"too many events ${e.hits.getWidth} wider than mask ${mask.getWidth}") e check mask } sets(set) } def cover() = eventSets.foreach { _.withCovers } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSetIdBits <= maxEventSetIdBits) } class SuperscalarEventSets(val eventSets: Seq[(Seq[EventSet], (UInt, UInt) => UInt)]) { def evaluate(eventSel: UInt): UInt = { val (set, mask) = decode(eventSel) val sets = for ((sets, reducer) <- eventSets) yield { sets.map { set => require(set.hits.getWidth <= mask.getWidth, s"too many events ${set.hits.getWidth} wider than mask ${mask.getWidth}") set.check(mask) }.reduce(reducer) } val zeroPadded = sets.padTo(1 << eventSetIdBits, 0.U) zeroPadded(set) } def toScalarEventSets: EventSets = new EventSets(eventSets.map(_._1.head)) def cover(): Unit = { eventSets.foreach(_._1.foreach(_.withCovers)) } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSets.forall(s => s._1.forall(_.size == s._1.head.size))) require(eventSetIdBits <= maxEventSetIdBits) } File RocketCore.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.withClock import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ArrayBuffer case class RocketCoreParams( xLen: Int = 64, pgLevels: Int = 3, // sv39 default bootFreqHz: BigInt = 0, useVM: Boolean = true, useUser: Boolean = false, useSupervisor: Boolean = false, useHypervisor: Boolean = false, useDebug: Boolean = true, useAtomics: Boolean = true, useAtomicsOnlyForIO: Boolean = false, useCompressed: Boolean = true, useRVE: Boolean = false, useConditionalZero: Boolean = false, useZba: Boolean = false, useZbb: Boolean = false, useZbs: Boolean = false, nLocalInterrupts: Int = 0, useNMI: Boolean = false, nBreakpoints: Int = 1, useBPWatch: Boolean = false, mcontextWidth: Int = 0, scontextWidth: Int = 0, nPMPs: Int = 8, nPerfCounters: Int = 0, haveBasicCounters: Boolean = true, haveCFlush: Boolean = false, misaWritable: Boolean = true, nL2TLBEntries: Int = 0, nL2TLBWays: Int = 1, nPTECacheEntries: Int = 8, mtvecInit: Option[BigInt] = Some(BigInt(0)), mtvecWritable: Boolean = true, fastLoadWord: Boolean = true, fastLoadByte: Boolean = false, branchPredictionModeCSR: Boolean = false, clockGate: Boolean = false, mvendorid: Int = 0, // 0 means non-commercial implementation mimpid: Int = 0x20181004, // release date in BCD mulDiv: Option[MulDivParams] = Some(MulDivParams()), fpu: Option[FPUParams] = Some(FPUParams()), debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB haveCease: Boolean = true, // non-standard CEASE instruction haveSimTimeout: Boolean = true, // add plusarg for simulation timeout vector: Option[RocketCoreVectorParams] = None ) extends CoreParams { val lgPauseCycles = 5 val haveFSDirty = false val pmpGranularity: Int = if (useHypervisor) 4096 else 4 val fetchWidth: Int = if (useCompressed) 2 else 1 // fetchWidth doubled, but coreInstBytes halved, for RVC: val decodeWidth: Int = fetchWidth / (if (useCompressed) 2 else 1) val retireWidth: Int = 1 val instBits: Int = if (useCompressed) 16 else 32 val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace override val useVector = vector.isDefined override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false) override def vLen = vector.map(_.vLen).getOrElse(0) override def eLen = vector.map(_.eLen).getOrElse(0) override def vfLen = vector.map(_.vfLen).getOrElse(0) override def vfh = vector.map(_.vfh).getOrElse(false) override def vExts = vector.map(_.vExts).getOrElse(Nil) override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0) override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32) override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs } trait HasRocketCoreParameters extends HasCoreParameters { lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams] val fastLoadWord = rocketParams.fastLoadWord val fastLoadByte = rocketParams.fastLoadByte val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this require(!fastLoadByte \|\| fastLoadWord) require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty") } class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters { override def bpmCSR = { rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0)))) } private def haveDCache = tileParams.dcache.get.scratch.isEmpty override def chickenCSR = { val mask = BigInt( tileParams.dcache.get.clockGate.toInt << 0 \| rocketParams.clockGate.toInt << 1 \| rocketParams.clockGate.toInt << 2 \| 1 << 3 \| // disableSpeculativeICacheRefill haveDCache.toInt << 9 \| // suppressCorruptOnGrantData tileParams.icache.get.prefetch.toInt << 17 ) Some(CustomCSR(chickenCSRId, mask, Some(mask))) } def disableICachePrefetch = getOrElse(chickenCSR, _.value(17), true.B) def marchid = CustomCSR.constant(CSRs.marchid, BigInt(1)) def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid)) // mimpid encodes a release version in the form of a BCD-encoded datestamp. def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid)) override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid } class CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) { val buserror = Option.when(hasBeu)(Bool()) } trait HasRocketCoreIO extends HasRocketCoreParameters { implicit val p: Parameters def nTotalRoCCCSRs: Int val io = IO(new CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val reset_vector = Input(UInt(resetVectorLen.W)) val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParams].beuAddr.isDefined)) val imem = new FrontendIO val dmem = new HellaCacheIO val ptw = Flipped(new DatapathPTWIO()) val fpu = Flipped(new FPUCoreIO()) val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs)) val trace = Output(new TraceBundle) val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth))) val cease = Output(Bool()) val wfi = Output(Bool()) val traceStall = Input(Bool()) val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None }) } class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) with HasRocketCoreParameters with HasRocketCoreIO { def nTotalRoCCCSRs = tile.roccCSRs.flatten.size import ALU._ val clock_en_reg = RegInit(true.B) val long_latency_stall = Reg(Bool()) val id_reg_pause = Reg(Bool()) val imem_might_request_reg = Reg(Bool()) val clock_en = WireDefault(true.B) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "rocket_clock_gate") class RocketImpl { // entering gated-clock domain // performance counters def pipelineIDToWB[T <: Data](x: T): T = RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid) val perfEvents = new EventSets(Seq( new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq( ("exception", () => false.B), ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp), ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp), ("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) \|\| id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))), ("system", () => id_ctrl.csr =/= CSR.N), ("arith", () => id_ctrl.wxd && !(id_ctrl.jal \|\| id_ctrl.jalr \|\| id_ctrl.mem \|\| id_ctrl.fp \|\| id_ctrl.mul \|\| id_ctrl.div \|\| id_ctrl.csr =/= CSR.N)), ("branch", () => id_ctrl.branch), ("jal", () => id_ctrl.jal), ("jalr", () => id_ctrl.jalr)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV), ("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV))) ++ (if (!usingFPU) Seq() else Seq( ("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen), ("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen), ("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23), ("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3), ("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3), ("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div \|\| io.fpu.dec.sqrt)), ("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst \|\| io.fpu.dec.fma \|\| io.fpu.dec.div \|\| io.fpu.dec.sqrt))))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("load-use interlock", () => id_ex_hazard && ex_ctrl.mem \|\| id_mem_hazard && mem_ctrl.mem \|\| id_wb_hazard && wb_ctrl.mem), ("long-latency interlock", () => id_sboard_hazard), ("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N \|\| id_mem_hazard && mem_ctrl.csr =/= CSR.N \|\| id_wb_hazard && wb_ctrl.csr =/= CSR.N), ("I$ blocked", () => icache_blocked), ("D$ blocked", () => id_ctrl.mem && dcache_blocked), ("branch misprediction", () => take_pc_mem && mem_direction_misprediction), ("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked), ("flush", () => wb_reg_flush_pipe), ("replay", () => replay_wb)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul \|\| ex_ctrl.div) \|\| id_mem_hazard && (mem_ctrl.mul \|\| mem_ctrl.div) \|\| id_wb_hazard && wb_ctrl.div))) ++ (if (!usingFPU) Seq() else Seq( ("fp interlock", () => id_ex_hazard && ex_ctrl.fp \|\| id_mem_hazard && mem_ctrl.fp \|\| id_wb_hazard && wb_ctrl.fp \|\| id_ctrl.fp && id_stall_fpu)))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("I$ miss", () => io.imem.perf.acquire), ("D$ miss", () => io.dmem.perf.acquire), ("D$ release", () => io.dmem.perf.release), ("ITLB miss", () => io.imem.perf.tlbMiss), ("DTLB miss", () => io.dmem.perf.tlbMiss), ("L2 TLB miss", () => io.ptw.perf.l2miss))))) val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen val decode_table = { (if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++: (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: (if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++: (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++: (if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++: (usingRoCC.option(new RoCCDecode)) ++: (if (xLen == 32) new I32Decode else new I64Decode) +: (usingVM.option(new SVMDecode)) ++: (usingSupervisor.option(new SDecode)) ++: (usingHypervisor.option(new HypervisorDecode)) ++: ((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++: (usingDebug.option(new DebugDecode)) ++: (usingNMI.option(new NMIDecode)) ++: (usingConditionalZero.option(new ConditionalZeroDecode)) ++: Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++: coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++: rocketParams.haveCease.option(new CeaseDecode) ++: usingVector.option(new VCFGDecode) ++: (if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++: (if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++: coreParams.useZbs.option(new ZbsDecode) ++: Seq(new IDecode) } flatMap(_.table) val ex_ctrl = Reg(new IntCtrlSigs) val mem_ctrl = Reg(new IntCtrlSigs) val wb_ctrl = Reg(new IntCtrlSigs) val ex_reg_xcpt_interrupt = Reg(Bool()) val ex_reg_valid = Reg(Bool()) val ex_reg_rvc = Reg(Bool()) val ex_reg_btb_resp = Reg(new BTBResp) val ex_reg_xcpt = Reg(Bool()) val ex_reg_flush_pipe = Reg(Bool()) val ex_reg_load_use = Reg(Bool()) val ex_reg_cause = Reg(UInt()) val ex_reg_replay = Reg(Bool()) val ex_reg_pc = Reg(UInt()) val ex_reg_mem_size = Reg(UInt()) val ex_reg_hls = Reg(Bool()) val ex_reg_inst = Reg(Bits()) val ex_reg_raw_inst = Reg(UInt()) val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val ex_reg_set_vconfig = Reg(Bool()) val mem_reg_xcpt_interrupt = Reg(Bool()) val mem_reg_valid = Reg(Bool()) val mem_reg_rvc = Reg(Bool()) val mem_reg_btb_resp = Reg(new BTBResp) val mem_reg_xcpt = Reg(Bool()) val mem_reg_replay = Reg(Bool()) val mem_reg_flush_pipe = Reg(Bool()) val mem_reg_cause = Reg(UInt()) val mem_reg_slow_bypass = Reg(Bool()) val mem_reg_load = Reg(Bool()) val mem_reg_store = Reg(Bool()) val mem_reg_set_vconfig = Reg(Bool()) val mem_reg_sfence = Reg(Bool()) val mem_reg_pc = Reg(UInt()) val mem_reg_inst = Reg(Bits()) val mem_reg_mem_size = Reg(UInt()) val mem_reg_hls_or_dv = Reg(Bool()) val mem_reg_raw_inst = Reg(UInt()) val mem_reg_wdata = Reg(Bits()) val mem_reg_rs2 = Reg(Bits()) val mem_br_taken = Reg(Bool()) val take_pc_mem = Wire(Bool()) val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val wb_reg_valid = Reg(Bool()) val wb_reg_xcpt = Reg(Bool()) val wb_reg_replay = Reg(Bool()) val wb_reg_flush_pipe = Reg(Bool()) val wb_reg_cause = Reg(UInt()) val wb_reg_set_vconfig = Reg(Bool()) val wb_reg_sfence = Reg(Bool()) val wb_reg_pc = Reg(UInt()) val wb_reg_mem_size = Reg(UInt()) val wb_reg_hls_or_dv = Reg(Bool()) val wb_reg_hfence_v = Reg(Bool()) val wb_reg_hfence_g = Reg(Bool()) val wb_reg_inst = Reg(Bits()) val wb_reg_raw_inst = Reg(UInt()) val wb_reg_wdata = Reg(Bits()) val wb_reg_rs2 = Reg(Bits()) val take_pc_wb = Wire(Bool()) val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val take_pc_mem_wb = take_pc_wb \|\| take_pc_mem val take_pc = take_pc_mem_wb // decode stage val ibuf = Module(new IBuf) val id_expanded_inst = ibuf.io.inst.map(_.bits.inst) val id_raw_inst = ibuf.io.inst.map(_.bits.raw) val id_inst = id_expanded_inst.map(_.bits) ibuf.io.imem <> io.imem.resp ibuf.io.kill := take_pc require(decodeWidth == 1 / TODO / && retireWidth == decodeWidth) require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point") require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor") val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table) val lgNXRegs = if (coreParams.useRVE) 4 else 5 val regAddrMask = (1 << lgNXRegs) - 1 def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0)) val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3) val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2) val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1) val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd) val id_load_use = Wire(Bool()) val id_reg_fence = RegInit(false.B) val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2) val id_raddr = IndexedSeq(id_raddr1, id_raddr2) val rf = new RegFile(regAddrMask, xLen) val id_rs = id_raddr.map(rf.read _) val ctrl_killd = Wire(Bool()) val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined)) val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W) val id_system_insn = id_ctrl.csr === CSR.I val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr)) val id_csr_flush = id_system_insn \|\| (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush) val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B id_ctrl.vec := false.B if (usingVector) { val v_decode = rocketParams.vector.get.decoder(p) v_decode.io.inst := id_inst(0) v_decode.io.vconfig := csr.io.vector.get.vconfig when (v_decode.io.legal) { id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill id_ctrl.fp := v_decode.io.fp id_ctrl.rocc := false.B id_ctrl.branch := false.B id_ctrl.jal := false.B id_ctrl.jalr := false.B id_ctrl.rxs2 := v_decode.io.read_rs2 id_ctrl.rxs1 := v_decode.io.read_rs1 id_ctrl.mem := false.B id_ctrl.rfs1 := v_decode.io.read_frs1 id_ctrl.rfs2 := false.B id_ctrl.rfs3 := false.B id_ctrl.wfd := v_decode.io.write_frd id_ctrl.mul := false.B id_ctrl.div := false.B id_ctrl.wxd := v_decode.io.write_rd id_ctrl.csr := CSR.N id_ctrl.fence_i := false.B id_ctrl.fence := false.B id_ctrl.amo := false.B id_ctrl.dp := false.B id_ctrl.vec := true.B } } val id_illegal_insn = !id_ctrl.legal \|\| (id_ctrl.mul \|\| id_ctrl.div) && !csr.io.status.isa('m'-'a') \|\| id_ctrl.amo && !csr.io.status.isa('a'-'a') \|\| id_ctrl.fp && (csr.io.decode(0).fp_illegal \|\| (io.fpu.illegal_rm && !id_ctrl.vec)) \|\| (id_ctrl.vec) && (csr.io.decode(0).vector_illegal \|\| csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) \|\| id_ctrl.dp && !csr.io.status.isa('d'-'a') \|\| ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') \|\| id_raddr2_illegal && id_ctrl.rxs2 \|\| id_raddr1_illegal && id_ctrl.rxs1 \|\| id_waddr_illegal && id_ctrl.wxd \|\| id_ctrl.rocc && csr.io.decode(0).rocc_illegal \|\| id_csr_en && (csr.io.decode(0).read_illegal \|\| !id_csr_ren && csr.io.decode(0).write_illegal) \|\| !ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal) val id_virtual_insn = id_ctrl.legal && ((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) \|\| (!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal)) // stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE) val id_amo_aq = id_inst(0)(26) val id_amo_rl = id_inst(0)(25) val id_fence_pred = id_inst(0)(27,24) val id_fence_succ = id_inst(0)(23,20) val id_fence_next = id_ctrl.fence \|\| id_ctrl.amo && id_amo_aq val id_mem_busy = !io.dmem.ordered \|\| io.dmem.req.valid when (!id_mem_busy) { id_reg_fence := false.B } val id_rocc_busy = usingRoCC.B && (io.rocc.busy \|\| ex_reg_valid && ex_ctrl.rocc \|\| mem_reg_valid && mem_ctrl.rocc \|\| wb_reg_valid && wb_ctrl.rocc) val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren val id_vec_busy = io.vector.map(v => v.backend_busy \|\| v.trap_check_busy).getOrElse(false.B) val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence \|\| id_csr_rocc_write) \|\| id_vec_busy && id_ctrl.fence \|\| id_mem_busy && (id_ctrl.amo && id_amo_rl \|\| id_ctrl.fence_i \|\| id_reg_fence && (id_ctrl.mem \|\| id_ctrl.rocc))) val bpu = Module(new BreakpointUnit(nBreakpoints)) bpu.io.status := csr.io.status bpu.io.bp := csr.io.bp bpu.io.pc := ibuf.io.pc bpu.io.ea := mem_reg_wdata bpu.io.mcontext := csr.io.mcontext bpu.io.scontext := csr.io.scontext val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0 val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1 val (id_xcpt, id_cause) = checkExceptions(List( (csr.io.interrupt, csr.io.interrupt_cause), (bpu.io.debug_if, CSR.debugTriggerCause.U), (bpu.io.xcpt_if, Causes.breakpoint.U), (id_xcpt0.pf.inst, Causes.fetch_page_fault.U), (id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt0.ae.inst, Causes.fetch_access.U), (id_xcpt1.pf.inst, Causes.fetch_page_fault.U), (id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt1.ae.inst, Causes.fetch_access.U), (id_virtual_insn, Causes.virtual_instruction.U), (id_illegal_insn, Causes.illegal_instruction.U))) val idCoverCauses = List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.fetch_access, "FETCH_ACCESS"), (Causes.illegal_instruction, "ILLEGAL_INSTRUCTION") ) ++ (if (usingVM) List( (Causes.fetch_page_fault, "FETCH_PAGE_FAULT") ) else Nil) coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses) val dcache_bypass_data = if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0) else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0) else wb_reg_wdata // detect bypass opportunities val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U val bypass_sources = IndexedSeq( (true.B, 0.U, 0.U), // treat reading x0 as a bypass (ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata), (mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata), (mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data)) val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr)) // execute stage val bypass_mux = bypass_sources.map(_._3) val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool())) val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W))) val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt())) val ex_rs = for (i <- 0 until id_raddr.size) yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i))) val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst) val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13) val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq( A1_RS1 -> ex_rs(0).asSInt, A1_PC -> ex_reg_pc.asSInt, A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S) )) val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq( A2_RS2 -> ex_rs(1).asSInt, A2_IMM -> ex_imm, A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S), ) ++ (if (coreParams.useZbs) Seq( A2_RS2OH -> ex_op2_oh, A2_IMMOH -> ex_op2_oh, ) else Nil)) val (ex_new_vl, ex_new_vconfig) = if (usingVector) { val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq( ex_reg_inst(31,30).andR -> ex_reg_inst(29,20), !ex_reg_inst(31) -> ex_reg_inst(30,20)))) val ex_avl = Mux(ex_ctrl.rxs1, Mux(ex_reg_inst(19,15) === 0.U, Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax), ex_rs(0) ), ex_reg_inst(19,15)) val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B) val ex_new_vconfig = Wire(new VConfig) ex_new_vconfig.vtype := ex_new_vtype ex_new_vconfig.vl := ex_new_vl (Some(ex_new_vl), Some(ex_new_vconfig)) } else { (None, None) } val alu = Module(new ALU) alu.io.dw := ex_ctrl.alu_dw alu.io.fn := ex_ctrl.alu_fn alu.io.in2 := ex_op2.asUInt alu.io.in1 := ex_op1.asUInt // multiplier and divider val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen)) div.io.req.valid := ex_reg_valid && ex_ctrl.div div.io.req.bits.dw := ex_ctrl.alu_dw div.io.req.bits.fn := ex_ctrl.alu_fn div.io.req.bits.in1 := ex_rs(0) div.io.req.bits.in2 := ex_rs(1) div.io.req.bits.tag := ex_waddr val mul = pipelinedMul.option { val m = Module(new PipelinedMultiplier(xLen, 2)) m.io.req.valid := ex_reg_valid && ex_ctrl.mul m.io.req.bits := div.io.req.bits m } ex_reg_valid := !ctrl_killd ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay ex_reg_xcpt := !ctrl_killd && id_xcpt ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt when (!ctrl_killd) { ex_ctrl := id_ctrl ex_reg_rvc := ibuf.io.inst(0).bits.rvc ex_ctrl.csr := id_csr when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B } when (id_fence_next) { id_reg_fence := true.B } when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr ex_ctrl.alu_fn := FN_ADD ex_ctrl.alu_dw := DW_XPR ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction ex_ctrl.sel_alu2 := A2_ZERO when (id_xcpt1.asUInt.orR) { // badaddr := PC+2 ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_SIZE ex_reg_rvc := true.B } when (bpu.io.xcpt_if \|\| id_xcpt0.asUInt.orR) { // badaddr := PC ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_ZERO } } ex_reg_flush_pipe := id_ctrl.fence_i \|\| id_csr_flush ex_reg_load_use := id_load_use ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX) ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12)) when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) { ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U) } when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) { ex_ctrl.mem_cmd := M_HFENCEV } if (tile.dcache.flushOnFenceI) { when (id_ctrl.fence_i) { ex_reg_mem_size := 0.U } } for (i <- 0 until id_raddr.size) { val do_bypass = id_bypass_src(i).reduce(_\|\|_) val bypass_src = PriorityEncoder(id_bypass_src(i)) ex_reg_rs_bypass(i) := do_bypass ex_reg_rs_lsb(i) := bypass_src when (id_ren(i) && !do_bypass) { ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size) } } when (id_illegal_insn \|\| id_virtual_insn) { val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0)) ex_reg_rs_bypass(0) := false.B ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size) } } when (!ctrl_killd \|\| csr.io.interrupt \|\| ibuf.io.inst(0).bits.replay) { ex_reg_cause := id_cause ex_reg_inst := id_inst(0) ex_reg_raw_inst := id_raw_inst(0) ex_reg_pc := ibuf.io.pc ex_reg_btb_resp := ibuf.io.btb_resp ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) } ex_reg_set_vconfig := id_set_vconfig && !id_xcpt } // replay inst in ex stage? val ex_pc_valid = ex_reg_valid \|\| ex_reg_replay \|\| ex_reg_xcpt_interrupt val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready \|\| ex_ctrl.div && !div.io.req.ready \|\| ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B) val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use val replay_ex = ex_reg_replay \|\| (ex_reg_valid && (replay_ex_structural \|\| replay_ex_load_use)) val ctrl_killx = take_pc_mem_wb \|\| replay_ex \|\| !ex_reg_valid // detect 2-cycle load-use delay for LB/LH/SC val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC \|\| ex_reg_mem_size < 2.U val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE \|\| ex_ctrl.mem_cmd === M_HFENCEV \|\| ex_ctrl.mem_cmd === M_HFENCEG) val (ex_xcpt, ex_cause) = checkExceptions(List( (ex_reg_xcpt_interrupt \|\| ex_reg_xcpt, ex_reg_cause))) val exCoverCauses = idCoverCauses coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses) // memory stage val mem_pc_valid = mem_reg_valid \|\| mem_reg_replay \|\| mem_reg_xcpt_interrupt val mem_br_target = mem_reg_pc.asSInt + Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst), Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), Mux(mem_reg_rvc, 2.S, 4.S))) val mem_npc = (Mux(mem_ctrl.jalr \|\| mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt val mem_wrong_npc = Mux(ex_pc_valid, mem_npc =/= ex_reg_pc, Mux(ibuf.io.inst(0).valid \|\| ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B)) val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt val mem_cfi = mem_ctrl.branch \|\| mem_ctrl.jalr \|\| mem_ctrl.jal val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) \|\| mem_ctrl.jalr \|\| mem_ctrl.jal val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken) val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction \|\| mem_reg_sfence) mem_reg_valid := !ctrl_killx mem_reg_replay := !take_pc_mem_wb && replay_ex mem_reg_xcpt := !ctrl_killx && ex_xcpt mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt // on pipeline flushes, cause mem_npc to hold the sequential npc, which // will drive the W-stage npc mux when (mem_reg_valid && mem_reg_flush_pipe) { mem_reg_sfence := false.B }.elsewhen (ex_pc_valid) { mem_ctrl := ex_ctrl mem_reg_rvc := ex_reg_rvc mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd) mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd) mem_reg_sfence := ex_sfence mem_reg_btb_resp := ex_reg_btb_resp mem_reg_flush_pipe := ex_reg_flush_pipe mem_reg_slow_bypass := ex_slow_bypass mem_reg_wphit := ex_reg_wphit mem_reg_set_vconfig := ex_reg_set_vconfig mem_reg_cause := ex_cause mem_reg_inst := ex_reg_inst mem_reg_raw_inst := ex_reg_raw_inst mem_reg_mem_size := ex_reg_mem_size mem_reg_hls_or_dv := io.dmem.req.bits.dv mem_reg_pc := ex_reg_pc // IDecode ensured they are 1H mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out) mem_br_taken := alu.io.cmp_out when (ex_ctrl.rxs2 && (ex_ctrl.mem \|\| ex_ctrl.rocc \|\| ex_sfence)) { val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size) mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data } if (usingVector) { when (ex_reg_set_vconfig) { mem_reg_rs2 := ex_new_vconfig.get.asUInt } } when (ex_ctrl.jalr && csr.io.status.debug) { // flush I$ on D-mode JALR to effect uncached fetch without D$ flush mem_ctrl.fence_i := true.B mem_reg_flush_pipe := true.B } } val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) \|\| (mem_reg_store && bpu.io.xcpt_st) val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) \|\| (mem_reg_store && bpu.io.debug_st) val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List( (mem_debug_breakpoint, CSR.debugTriggerCause.U), (mem_breakpoint, Causes.breakpoint.U))) val (mem_xcpt, mem_cause) = checkExceptions(List( (mem_reg_xcpt_interrupt \|\| mem_reg_xcpt, mem_reg_cause), (mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U), (mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause))) val memCoverCauses = (exCoverCauses ++ List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.misaligned_fetch, "MISALIGNED_FETCH") )).distinct coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses) val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B) val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B) val replay_mem = dcache_kill_mem \|\| mem_reg_replay \|\| fpu_kill_mem \|\| vec_kill_mem \|\| vec_kill_all val killm_common = dcache_kill_mem \|\| take_pc_wb \|\| mem_reg_xcpt \|\| !mem_reg_valid div.io.kill := killm_common && RegNext(div.io.req.fire) val ctrl_killm = killm_common \|\| mem_xcpt \|\| fpu_kill_mem \|\| vec_kill_mem // writeback stage wb_reg_valid := !ctrl_killm wb_reg_replay := replay_mem && !take_pc_wb wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B) wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe when (mem_pc_valid) { wb_ctrl := mem_ctrl wb_reg_sfence := mem_reg_sfence wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata) when (mem_ctrl.rocc \|\| mem_reg_sfence \|\| mem_reg_set_vconfig) { wb_reg_rs2 := mem_reg_rs2 } wb_reg_cause := mem_cause wb_reg_inst := mem_reg_inst wb_reg_raw_inst := mem_reg_raw_inst wb_reg_mem_size := mem_reg_mem_size wb_reg_hls_or_dv := mem_reg_hls_or_dv wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG wb_reg_pc := mem_reg_pc wb_reg_wphit := mem_reg_wphit \| bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) \|\| (bpw.wvalid(0) && mem_reg_store) } wb_reg_set_vconfig := mem_reg_set_vconfig } val (wb_xcpt, wb_cause) = checkExceptions(List( (wb_reg_xcpt, wb_reg_cause), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U) )) val wbCoverCauses = List( (Causes.misaligned_store, "MISALIGNED_STORE"), (Causes.misaligned_load, "MISALIGNED_LOAD"), (Causes.store_access, "STORE_ACCESS"), (Causes.load_access, "LOAD_ACCESS") ) ++ (if(usingVM) List( (Causes.store_page_fault, "STORE_PAGE_FAULT"), (Causes.load_page_fault, "LOAD_PAGE_FAULT") ) else Nil) ++ (if (usingHypervisor) List( (Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"), (Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT"), ) else Nil) coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses) val wb_pc_valid = wb_reg_valid \|\| wb_reg_replay \|\| wb_reg_xcpt val wb_wxd = wb_reg_valid && wb_ctrl.wxd val wb_set_sboard = wb_ctrl.div \|\| wb_dcache_miss \|\| wb_ctrl.rocc \|\| wb_ctrl.vec val replay_wb_common = io.dmem.s2_nack \|\| wb_reg_replay val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B) val replay_wb = replay_wb_common \|\| replay_wb_rocc \|\| replay_wb_csr \|\| replay_wb_vec take_pc_wb := replay_wb \|\| wb_xcpt \|\| csr.io.eret \|\| wb_reg_flush_pipe // writeback arbitration val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1) val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay class LLWB extends Bundle { val data = UInt(xLen.W) val tag = UInt(5.W) } val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec ll_arb.io.in.foreach(_.valid := false.B) ll_arb.io.in.foreach(_.bits := DontCare) val ll_wdata = WireInit(ll_arb.io.out.bits.data) val ll_waddr = WireInit(ll_arb.io.out.bits.tag) val ll_wen = WireInit(ll_arb.io.out.fire) ll_arb.io.out.ready := !wb_wxd div.io.resp.ready := ll_arb.io.in(0).ready ll_arb.io.in(0).valid := div.io.resp.valid ll_arb.io.in(0).bits.data := div.io.resp.bits.data ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag if (usingRoCC) { io.rocc.resp.ready := ll_arb.io.in(1).ready ll_arb.io.in(1).valid := io.rocc.resp.valid ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd } else { // tie off RoCC io.rocc.resp.ready := false.B io.rocc.mem.req.ready := false.B } io.vector.map { v => v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready) ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp ll_arb.io.in(2).bits.data := v.resp.bits.data ll_arb.io.in(2).bits.tag := v.resp.bits.rd } // Dont care mem since not all RoCC need accessing memory io.rocc.mem := DontCare when (dmem_resp_replay && dmem_resp_xpu) { ll_arb.io.out.ready := false.B ll_waddr := dmem_resp_waddr ll_wen := true.B } val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt val wb_wen = wb_valid && wb_ctrl.wxd val rf_wen = wb_wen \|\| ll_wen val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr) val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0), Mux(ll_wen, ll_wdata, Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata, Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata), wb_reg_wdata)))) when (rf_wen) { rf.write(rf_waddr, rf_wdata) } // hook up control/status regfile csr.io.ungated_clock := clock csr.io.decode(0).inst := id_inst(0) csr.io.exception := wb_xcpt csr.io.cause := wb_cause csr.io.retire := wb_valid csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst) csr.io.interrupts := io.interrupts csr.io.hartid := io.hartid io.fpu.fcsr_rm := csr.io.fcsr_rm val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W)) val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B) csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid \| vector_fcsr_flags_valid csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) \| (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid)) io.fpu.time := csr.io.time(31,0) io.fpu.hartid := io.hartid csr.io.rocc_interrupt := io.rocc.interrupt csr.io.pc := wb_reg_pc val tval_dmem_addr = !wb_reg_xcpt val tval_any_addr = tval_dmem_addr \|\| wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U) val tval_inst = wb_reg_cause === Causes.illegal_instruction.U val tval_valid = wb_xcpt && (tval_any_addr \|\| tval_inst) csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v \|\| tval_dmem_addr && wb_reg_hls_or_dv) csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U) val (htval, mhtinst_read_pseudo) = { val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U) assert(!htval_valid_imem \|\| io.imem.gpa.valid) val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U) val htval = (htval_dmem \| htval_imem) >> hypervisorExtraAddrBits // read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) \|\| (io.dmem.s2_gpa_is_pte && htval_valid_dmem) (htval, mhtinst_read_pseudo) } csr.io.vector.foreach { v => v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig) v.set_vs_dirty := wb_valid && wb_ctrl.vec v.set_vstart.valid := wb_valid && wb_reg_set_vconfig v.set_vstart.bits := 0.U } io.vector.foreach { v => when (v.wb.retire \|\| v.wb.xcpt \|\| wb_ctrl.vec) { csr.io.pc := v.wb.pc csr.io.retire := v.wb.retire csr.io.inst(0) := v.wb.inst when (v.wb.xcpt && !wb_reg_xcpt) { wb_xcpt := true.B wb_cause := v.wb.cause csr.io.tval := v.wb.tval } } v.wb.store_pending := io.dmem.store_pending v.wb.vxrm := csr.io.vector.get.vxrm v.wb.frm := csr.io.fcsr_rm csr.io.vector.get.set_vxsat := v.set_vxsat when (v.set_vconfig.valid) { csr.io.vector.get.set_vconfig.valid := true.B csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits } when (v.set_vstart.valid) { csr.io.vector.get.set_vstart.valid := true.B csr.io.vector.get.set_vstart.bits := v.set_vstart.bits } } csr.io.htval := htval csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo io.ptw.ptbr := csr.io.ptbr io.ptw.hgatp := csr.io.hgatp io.ptw.vsatp := csr.io.vsatp (io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs } io.ptw.status := csr.io.status io.ptw.hstatus := csr.io.hstatus io.ptw.gstatus := csr.io.gstatus io.ptw.pmp := csr.io.pmp csr.io.rw.addr := wb_reg_inst(31,20) csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr) csr.io.rw.wdata := wb_reg_wdata io.rocc.csrs <> csr.io.roccCSRs io.trace.time := csr.io.time io.trace.insns := csr.io.trace if (rocketParams.debugROB.isDefined) { val sz = rocketParams.debugROB.get.size if (sz < 1) { // use unsynthesizable ROB val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val should_wb = WireInit((wb_ctrl.wfd \|\| (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception) val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard) val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)) io.vector.foreach { v => when (v.wb.retire) { should_wb := v.wb.rob_should_wb has_wb := false.B wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7)) }} DebugROB.pushTrace(clock, reset, io.hartid, csr_trace_with_wdata, should_wb, has_wb, wb_addr) io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid) DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata) } else { // synthesizable ROB (no FPRs) require(!usingVector, "Synthesizable ROB does not support vector implementations") val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val debug_rob = Module(new HardDebugROB(sz, 32)) debug_rob.io.i_insn := csr_trace_with_wdata debug_rob.io.should_wb := (wb_ctrl.wfd \|\| (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U) debug_rob.io.wb_val := ll_wen debug_rob.io.wb_tag := rf_waddr debug_rob.io.wb_data := rf_wdata io.trace.insns(0) := debug_rob.io.o_insn } } else { io.trace.insns := csr.io.trace } for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) { iobpw.valid(0) := wphit iobpw.action := bp.control.action // tie off bpwatch valids iobpw.rvalid.foreach(_ := false.B) iobpw.wvalid.foreach(_ := false.B) iobpw.ivalid.foreach(_ := false.B) } val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1), (id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2), (id_ctrl.wxd && id_waddr =/= 0.U, id_waddr)) val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1), (io.fpu.dec.ren2, id_raddr2), (io.fpu.dec.ren3, id_raddr3), (io.fpu.dec.wen, id_waddr)) val sboard = new Scoreboard(32, true) sboard.clear(ll_wen, ll_waddr) def id_sboard_clear_bypass(r: UInt) = { // ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r else div.io.resp.fire && div.io.resp.bits.tag === r \|\| dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r } val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd)) sboard.set(wb_set_sboard && wb_wen, wb_waddr) // stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage. val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N \|\| ex_ctrl.jalr \|\| ex_ctrl.mem \|\| ex_ctrl.mul \|\| ex_ctrl.div \|\| ex_ctrl.fp \|\| ex_ctrl.rocc \|\| ex_ctrl.vec val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr) val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr) val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass \|\| fp_data_hazard_ex) // stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage. val mem_mem_cmd_bh = if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass else true.B val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N \|\| mem_ctrl.mem && mem_mem_cmd_bh \|\| mem_ctrl.mul \|\| mem_ctrl.div \|\| mem_ctrl.fp \|\| mem_ctrl.rocc \|\| mem_ctrl.vec val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr) val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr) val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass \|\| fp_data_hazard_mem) id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem val id_vconfig_hazard = id_ctrl.vec && ( (ex_reg_valid && ex_reg_set_vconfig) \|\| (mem_reg_valid && mem_reg_set_vconfig) \|\| (wb_reg_valid && wb_reg_set_vconfig)) // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback. val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr) val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr) val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard \|\| fp_data_hazard_wb) val id_stall_fpu = if (usingFPU) { val fp_sboard = new Scoreboard(32) fp_sboard.set(((wb_dcache_miss \|\| wb_ctrl.vec) && wb_ctrl.wfd \|\| io.fpu.sboard_set) && wb_valid, wb_waddr) val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B) fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) \|\| v_ll, io.fpu.ll_resp_tag) fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) checkHazards(fp_hazard_targets, fp_sboard.read _) } else false.B val dcache_blocked = { // speculate that a blocked D$ will unblock the cycle after a Grant val blocked = Reg(Bool()) blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked \|\| io.dmem.req.valid \|\| io.dmem.s2_nack) blocked && !io.dmem.perf.grant } val rocc_blocked = Reg(Bool()) rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid \|\| rocc_blocked) val ctrl_stalld = id_ex_hazard \|\| id_mem_hazard \|\| id_wb_hazard \|\| id_sboard_hazard \|\| id_vconfig_hazard \|\| csr.io.singleStep && (ex_reg_valid \|\| mem_reg_valid \|\| wb_reg_valid) \|\| id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy \|\| id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy \|\| id_ctrl.fp && id_stall_fpu \|\| id_ctrl.mem && dcache_blocked \|\| // reduce activity during D$ misses id_ctrl.rocc && rocc_blocked \|\| // reduce activity while RoCC is busy id_ctrl.div && (!(div.io.req.ready \|\| (div.io.resp.valid && !wb_wxd)) \|\| div.io.req.valid) \|\| // reduce odds of replay !clock_en \|\| id_do_fence \|\| csr.io.csr_stall \|\| id_reg_pause \|\| io.traceStall ctrl_killd := !ibuf.io.inst(0).valid \|\| ibuf.io.inst(0).bits.replay \|\| take_pc_mem_wb \|\| ctrl_stalld \|\| csr.io.interrupt io.imem.req.valid := take_pc io.imem.req.bits.speculative := !take_pc_wb io.imem.req.bits.pc := Mux(wb_xcpt \|\| csr.io.eret, csr.io.evec, // exception or [m\|s]ret Mux(replay_wb, wb_reg_pc, // replay mem_npc)) // flush or branch misprediction io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack io.imem.might_request := { imem_might_request_reg := ex_pc_valid \|\| mem_pc_valid \|\| io.ptw.customCSRs.disableICacheClockGate \|\| io.vector.map(_.trap_check_busy).getOrElse(false.B) imem_might_request_reg } io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common) io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence io.imem.sfence.bits.rs1 := wb_reg_mem_size(0) io.imem.sfence.bits.rs2 := wb_reg_mem_size(1) io.imem.sfence.bits.addr := wb_reg_wdata io.imem.sfence.bits.asid := wb_reg_rs2 io.imem.sfence.bits.hv := wb_reg_hfence_v io.imem.sfence.bits.hg := wb_reg_hfence_g io.ptw.sfence := io.imem.sfence ibuf.io.inst(0).ready := !ctrl_stalld io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi \|\| mem_cfi_taken) io.imem.btb_update.bits.isValid := mem_cfi io.imem.btb_update.bits.cfiType := Mux((mem_ctrl.jal \|\| mem_ctrl.jalr) && mem_waddr(0), CFIType.call, Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat("b00?01"), CFIType.ret, Mux(mem_ctrl.jal \|\| mem_ctrl.jalr, CFIType.jump, CFIType.branch))) io.imem.btb_update.bits.target := io.imem.req.bits.pc io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc) io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc \| (coreInstBytesfetchWidth-1).U) io.imem.btb_update.bits.prediction := mem_reg_btb_resp io.imem.btb_update.bits.taken := DontCare io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc io.imem.bht_update.bits.taken := mem_br_taken io.imem.bht_update.bits.mispredict := mem_wrong_npc io.imem.bht_update.bits.branch := mem_ctrl.branch io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht // Connect RAS in Frontend io.imem.ras_update := DontCare io.fpu.valid := !ctrl_killd && id_ctrl.fp io.fpu.killx := ctrl_killx io.fpu.killm := killm_common io.fpu.inst := id_inst(0) io.fpu.fromint_data := ex_rs(0) io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data) io.fpu.ll_resp_type := io.dmem.resp.bits.size io.fpu.ll_resp_tag := dmem_resp_waddr io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U) io.vector.map { v => when (!(dmem_resp_valid && dmem_resp_fpu)) { io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp io.fpu.ll_resp_data := v.resp.bits.data io.fpu.ll_resp_type := v.resp.bits.size io.fpu.ll_resp_tag := v.resp.bits.rd } } io.vector.foreach { v => v.ex.valid := ex_reg_valid && (ex_ctrl.vec \|\| rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx v.ex.inst := ex_reg_inst v.ex.vconfig := csr.io.vector.get.vconfig v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec \|\| wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart) v.ex.rs1 := ex_rs(0) v.ex.rs2 := ex_rs(1) v.ex.pc := ex_reg_pc v.mem.frs1 := io.fpu.store_data v.killm := killm_common v.status := csr.io.status } io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp) require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth) io.dmem.req.bits.tag := ex_dcache_tag io.dmem.req.bits.cmd := ex_ctrl.mem_cmd io.dmem.req.bits.size := ex_reg_mem_size io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14)) io.dmem.req.bits.phys := false.B io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out) io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr) io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv) io.dmem.req.bits.dv := ex_reg_hls \|\| csr.io.status.dv io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) \|\| (!ex_ctrl.fp && ex_waddr === 0.U) io.dmem.req.bits.no_alloc := DontCare io.dmem.req.bits.no_xcpt := DontCare io.dmem.req.bits.data := DontCare io.dmem.req.bits.mask := DontCare io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2)) io.dmem.s1_data.mask := DontCare io.dmem.s1_kill := killm_common \|\| mem_ldst_xcpt \|\| fpu_kill_mem \|\| vec_kill_mem io.dmem.s2_kill := false.B // don't let D$ go to sleep if we're probably going to use it soon io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common io.rocc.exception := wb_xcpt && csr.io.status.xs.orR io.rocc.cmd.bits.status := csr.io.status io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction()) io.rocc.cmd.bits.rs1 := wb_reg_wdata io.rocc.cmd.bits.rs2 := wb_reg_rs2 // gate the clock val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U \|\| csr.io.inhibit_cycle \|\| io.dmem.perf.release \|\| take_pc when (unpause) { id_reg_pause := false.B } io.cease := csr.io.status.cease && !clock_en_reg io.wfi := csr.io.status.wfi if (rocketParams.clockGate) { long_latency_stall := csr.io.csr_stall \|\| io.dmem.perf.blocked \|\| id_reg_pause && !unpause clock_en := clock_en_reg \|\| ex_pc_valid \|\| (!long_latency_stall && io.imem.resp.valid) clock_en_reg := ex_pc_valid \|\| mem_pc_valid \|\| wb_pc_valid \|\| // instruction in flight io.ptw.customCSRs.disableCoreClockGate \|\| // chicken bit !div.io.req.ready \|\| // mul/div in flight usingFPU.B && !io.fpu.fcsr_rdy \|\| // long-latency FPU in flight io.dmem.replay_next \|\| // long-latency load replaying (!long_latency_stall && (ibuf.io.inst(0).valid \|\| io.imem.resp.valid)) // instruction pending assert(!(ex_pc_valid \|\| mem_pc_valid \|\| wb_pc_valid) \|\| clock_en) } // evaluate performance counters val icache_blocked = !(io.imem.resp.valid \|\| RegNext(io.imem.resp.valid)) csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) } val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen)) coreMonitorBundle.clock := clock coreMonitorBundle.reset := reset coreMonitorBundle.hartid := io.hartid coreMonitorBundle.timer := csr.io.time(31,0) coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen) coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard coreMonitorBundle.wrenf := false.B coreMonitorBundle.wrdst := wb_waddr coreMonitorBundle.wrdata := rf_wdata coreMonitorBundle.rd0src := wb_reg_inst(19,15) coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0))) coreMonitorBundle.rd1src := wb_reg_inst(24,20) coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1))) coreMonitorBundle.inst := csr.io.trace(0).insn coreMonitorBundle.excpt := csr.io.trace(0).exception coreMonitorBundle.priv_mode := csr.io.trace(0).priv if (enableCommitLog) { val t = csr.io.trace(0) val rd = wb_waddr val wfd = wb_ctrl.wfd val wxd = wb_ctrl.wxd val has_data = wb_wen && !wb_set_sboard when (t.valid && !t.exception) { when (wfd) { printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+32.U) } .elsewhen (wxd && rd =/= 0.U && has_data) { printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata) } .elsewhen (wxd && rd =/= 0.U && !has_data) { printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd) } .otherwise { printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn) } } when (ll_wen && rf_waddr =/= 0.U) { printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata) } } else { when (csr.io.trace(0).valid) { printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid, coreMonitorBundle.pc, Mux(wb_ctrl.wxd \|\| wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U), Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U), coreMonitorBundle.wrenx, Mux(wb_ctrl.rxs1 \|\| wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U), Mux(wb_ctrl.rxs1 \|\| wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U), Mux(wb_ctrl.rxs2 \|\| wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U), Mux(wb_ctrl.rxs2 \|\| wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U), coreMonitorBundle.inst, coreMonitorBundle.inst) } } // CoreMonitorBundle for late latency writes val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen)) xrfWriteBundle.clock := clock xrfWriteBundle.reset := reset xrfWriteBundle.hartid := io.hartid xrfWriteBundle.timer := csr.io.time(31,0) xrfWriteBundle.valid := false.B xrfWriteBundle.pc := 0.U xrfWriteBundle.wrdst := rf_waddr xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr)) xrfWriteBundle.wrenf := false.B xrfWriteBundle.wrdata := rf_wdata xrfWriteBundle.rd0src := 0.U xrfWriteBundle.rd0val := 0.U xrfWriteBundle.rd1src := 0.U xrfWriteBundle.rd1val := 0.U xrfWriteBundle.inst := 0.U xrfWriteBundle.excpt := false.B xrfWriteBundle.priv_mode := csr.io.trace(0).priv if (rocketParams.haveSimTimeout) PlusArg.timeout( name = "max_core_cycles", docstring = "Kill the emulation after INT rdtime cycles. Off if 0." )(csr.io.time) } // leaving gated-clock domain val rocketImpl = withClock (gated_clock) { new RocketImpl } def checkExceptions(x: Seq[(Bool, UInt)]) = (WireInit(x.map(_._1).reduce(_\|\|_)), WireInit(PriorityMux(x))) def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = { for ((coverCause, label) <- coverCausesLabels) { property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_${label}") } } def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) = targets.map(h => h._1 && cond(h._2)).reduce(_\|\|_) def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else { // efficient means to compress 64-bit VA into vaddrBits+1 bits // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) val b = vaddrBitsExtended-1 val a = (a0 >> b).asSInt val msb = Mux(a === 0.S \|\| a === -1.S, ea(b), !ea(b-1)) Cat(msb, ea(b-1, 0)) } class Scoreboard(n: Int, zero: Boolean = false) { def set(en: Bool, addr: UInt): Unit = update(en, _next \| mask(en, addr)) def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr)) def read(addr: UInt): Bool = r(addr) def readBypassed(addr: UInt): Bool = _next(addr) private val _r = RegInit(0.U(n.W)) private val r = if (zero) (_r >> 1 << 1) else _r private var _next = r private var ens = false.B private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U) private def update(en: Bool, update: UInt) = { _next = update ens = ens \|\| en when (ens) { _r := _next } } } } class RegFile(n: Int, w: Int, zero: Boolean = false) { val rf = Mem(n, UInt(w.W)) private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0)) private val reads = ArrayBuffer[(UInt,UInt)]() private var canRead = true def read(addr: UInt) = { require(canRead) reads += addr -> Wire(UInt()) reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr)) reads.last._2 } def write(addr: UInt, data: UInt) = { canRead = false when (addr =/= 0.U) { access(addr) := data for ((raddr, rdata) <- reads) when (addr === raddr) { rdata := data } } } } object ImmGen { def apply(sel: UInt, inst: UInt) = { val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt) val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign) val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt) val b11 = Mux(sel === IMM_U \|\| sel === IMM_Z, 0.S, Mux(sel === IMM_UJ, inst(20).asSInt, Mux(sel === IMM_SB, inst(7).asSInt, sign))) val b10_5 = Mux(sel === IMM_U \|\| sel === IMM_Z, 0.U, inst(30,25)) val b4_1 = Mux(sel === IMM_U, 0.U, Mux(sel === IMM_S \|\| sel === IMM_SB, inst(11,8), Mux(sel === IMM_Z, inst(19,16), inst(24,21)))) val b0 = Mux(sel === IMM_S, inst(7), Mux(sel === IMM_I, inst(20), Mux(sel === IMM_Z, inst(15), 0.U))) Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt } } File Configs.scala: package ara import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.tile._ import freechips.rocketchip.subsystem._ import shuttle.common.{ShuttleTileAttachParams, ShuttleCoreVectorParams} class WithAraRocketVectorUnit(vLen: Int = 4096, nLanes: Int = 2, axiIdBits: Int = 4, cores: Option[Seq[Int]] = None, enableDelay: Boolean = false) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => { val buildVector = cores.map(_.contains(tp.tileParams.tileId)).getOrElse(true) require(nLanes >= 2) if (buildVector) tp.copy(tileParams = tp.tileParams.copy( core = tp.tileParams.core.copy( vector = Some(RocketCoreVectorParams( build = ((p: Parameters) => new AraRocketUnit(nLanes, axiIdBits, enableDelay)(p)), vLen = vLen, eLen = 64, vfLen = 64, vfh = false, vMemDataBits = 0, decoder = ((p: Parameters) => { val decoder = Module(new AraEarlyVectorDecode()(p)) decoder }), useDCache = false, issueVConfig = true, vExts = Nil )), ) )) else tp } case other => other } }) class WithAraShuttleVectorUnit(vLen: Int = 4096, nLanes: Int = 2, axiIdBits: Int = 4, cores: Option[Seq[Int]] = None, enableDelay: Boolean = false) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: ShuttleTileAttachParams => { val buildVector = cores.map(_.contains(tp.tileParams.tileId)).getOrElse(true) if (buildVector) tp.copy(tileParams = tp.tileParams.copy( core = tp.tileParams.core.copy( vector = Some(ShuttleCoreVectorParams( build = ((p: Parameters) => new AraShuttleUnit(nLanes, axiIdBits, enableDelay)(p)), vLen = vLen, vfLen = 64, vfh = false, decoder = ((p: Parameters) => { val decoder = Module(new AraEarlyVectorDecode()(p)) decoder }), issueVConfig = true, vExts = Nil )), ) )) else tp } case other => other } }) File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out } File CSR.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.LinkedHashMap import Instructions._ import CustomInstructions._ class MStatus extends Bundle { // not truly part of mstatus, but convenient val debug = Bool() val cease = Bool() val wfi = Bool() val isa = UInt(32.W) val dprv = UInt(PRV.SZ.W) // effective prv for data accesses val dv = Bool() // effective v for data accesses val prv = UInt(PRV.SZ.W) val v = Bool() val sd = Bool() val zero2 = UInt(23.W) val mpv = Bool() val gva = Bool() val mbe = Bool() val sbe = Bool() val sxl = UInt(2.W) val uxl = UInt(2.W) val sd_rv32 = Bool() val zero1 = UInt(8.W) val tsr = Bool() val tw = Bool() val tvm = Bool() val mxr = Bool() val sum = Bool() val mprv = Bool() val xs = UInt(2.W) val fs = UInt(2.W) val mpp = UInt(2.W) val vs = UInt(2.W) val spp = UInt(1.W) val mpie = Bool() val ube = Bool() val spie = Bool() val upie = Bool() val mie = Bool() val hie = Bool() val sie = Bool() val uie = Bool() } class MNStatus extends Bundle { val mpp = UInt(2.W) val zero3 = UInt(3.W) val mpv = Bool() val zero2 = UInt(3.W) val mie = Bool() val zero1 = UInt(3.W) } class HStatus extends Bundle { val zero6 = UInt(30.W) val vsxl = UInt(2.W) val zero5 = UInt(9.W) val vtsr = Bool() val vtw = Bool() val vtvm = Bool() val zero3 = UInt(2.W) val vgein = UInt(6.W) val zero2 = UInt(2.W) val hu = Bool() val spvp = Bool() val spv = Bool() val gva = Bool() val vsbe = Bool() val zero1 = UInt(5.W) } class DCSR extends Bundle { val xdebugver = UInt(2.W) val zero4 = UInt(2.W) val zero3 = UInt(12.W) val ebreakm = Bool() val ebreakh = Bool() val ebreaks = Bool() val ebreaku = Bool() val zero2 = Bool() val stopcycle = Bool() val stoptime = Bool() val cause = UInt(3.W) val v = Bool() val zero1 = UInt(2.W) val step = Bool() val prv = UInt(PRV.SZ.W) } class MIP(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val lip = Vec(coreParams.nLocalInterrupts, Bool()) val zero1 = Bool() val debug = Bool() // keep in sync with CSR.debugIntCause val rocc = Bool() val sgeip = Bool() val meip = Bool() val vseip = Bool() val seip = Bool() val ueip = Bool() val mtip = Bool() val vstip = Bool() val stip = Bool() val utip = Bool() val msip = Bool() val vssip = Bool() val ssip = Bool() val usip = Bool() } class Envcfg extends Bundle { val stce = Bool() // only for menvcfg/henvcfg val pbmte = Bool() // only for menvcfg/henvcfg val zero54 = UInt(54.W) val cbze = Bool() val cbcfe = Bool() val cbie = UInt(2.W) val zero3 = UInt(3.W) val fiom = Bool() def write(wdata: UInt) { val new_envcfg = wdata.asTypeOf(new Envcfg) fiom := new_envcfg.fiom // only FIOM is writable currently } } class PTBR(implicit p: Parameters) extends CoreBundle()(p) { def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0) def pgLevelsToMode(i: Int) = (xLen, i) match { case (32, 2) => 1 case (64, x) if x >= 3 && x <= 6 => x + 5 } val (modeBits, maxASIdBits) = xLen match { case 32 => (1, 9) case 64 => (4, 16) } require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen) val mode = UInt(modeBits.W) val asid = UInt(maxASIdBits.W) val ppn = UInt((maxPAddrBits - pgIdxBits).W) } object PRV { val SZ = 2 val U = 0 val S = 1 val H = 2 val M = 3 } object CSR { // commands val SZ = 3 def X = BitPat.dontCare(SZ) def N = 0.U(SZ.W) def R = 2.U(SZ.W) def I = 4.U(SZ.W) def W = 5.U(SZ.W) def S = 6.U(SZ.W) def C = 7.U(SZ.W) // mask a CSR cmd with a valid bit def maskCmd(valid: Bool, cmd: UInt): UInt = { // all commands less than CSR.I are treated by CSRFile as NOPs cmd & ~Mux(valid, 0.U, CSR.I) } val ADDRSZ = 12 def modeLSB: Int = 8 def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ) def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB) def busErrorIntCause = 128 def debugIntCause = 14 // keep in sync with MIP.debug def debugTriggerCause = { val res = debugIntCause require(!(Causes.all contains res)) res } def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause def rnmiBEUCause = 12 val firstCtr = CSRs.cycle val firstCtrH = CSRs.cycleh val firstHPC = CSRs.hpmcounter3 val firstHPCH = CSRs.hpmcounter3h val firstHPE = CSRs.mhpmevent3 val firstMHPC = CSRs.mhpmcounter3 val firstMHPCH = CSRs.mhpmcounter3h val firstHPM = 3 val nCtr = 32 val nHPM = nCtr - firstHPM val hpmWidth = 40 val maxPMPs = 16 } class PerfCounterIO(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val eventSel = Output(UInt(xLen.W)) val inc = Input(UInt(log2Ceil(1+retireWidth).W)) } class TracedInstruction(implicit p: Parameters) extends CoreBundle { val valid = Bool() val iaddr = UInt(coreMaxAddrBits.W) val insn = UInt(iLen.W) val priv = UInt(3.W) val exception = Bool() val interrupt = Bool() val cause = UInt(xLen.W) val tval = UInt((coreMaxAddrBits max iLen).W) val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W)) } class TraceAux extends Bundle { val enable = Bool() val stall = Bool() } class CSRDecodeIO(implicit p: Parameters) extends CoreBundle { val inst = Input(UInt(iLen.W)) def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0) val fp_illegal = Output(Bool()) val vector_illegal = Output(Bool()) val fp_csr = Output(Bool()) val vector_csr = Output(Bool()) val rocc_illegal = Output(Bool()) val read_illegal = Output(Bool()) val write_illegal = Output(Bool()) val write_flush = Output(Bool()) val system_illegal = Output(Bool()) val virtual_access_illegal = Output(Bool()) val virtual_system_illegal = Output(Bool()) } class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val ungated_clock = Input(Clock()) val interrupts = Input(new CoreInterrupts(hasBeu)) val hartid = Input(UInt(hartIdLen.W)) val rw = new Bundle { val addr = Input(UInt(CSR.ADDRSZ.W)) val cmd = Input(Bits(CSR.SZ.W)) val rdata = Output(Bits(xLen.W)) val wdata = Input(Bits(xLen.W)) } val decode = Vec(decodeWidth, new CSRDecodeIO) val csr_stall = Output(Bool()) // stall retire for wfi val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall val eret = Output(Bool()) val singleStep = Output(Bool()) val status = Output(new MStatus()) val hstatus = Output(new HStatus()) val gstatus = Output(new MStatus()) val ptbr = Output(new PTBR()) val hgatp = Output(new PTBR()) val vsatp = Output(new PTBR()) val evec = Output(UInt(vaddrBitsExtended.W)) val exception = Input(Bool()) val retire = Input(UInt(log2Up(1+retireWidth).W)) val cause = Input(UInt(xLen.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val tval = Input(UInt(vaddrBitsExtended.W)) val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W)) val mhtinst_read_pseudo = Input(Bool()) val gva = Input(Bool()) val time = Output(UInt(xLen.W)) val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W))) val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool())) val rocc_interrupt = Input(Bool()) val interrupt = Output(Bool()) val interrupt_cause = Output(UInt(xLen.W)) val bp = Output(Vec(nBreakpoints, new BP)) val pmp = Output(Vec(nPMPs, new PMP)) val counters = Vec(nPerfCounters, new PerfCounterIO) val csrw_counter = Output(UInt(CSR.nCtr.W)) val inhibit_cycle = Output(Bool()) val inst = Input(Vec(retireWidth, UInt(iLen.W))) val trace = Output(Vec(retireWidth, new TracedInstruction)) val mcontext = Output(UInt(coreParams.mcontextWidth.W)) val scontext = Output(UInt(coreParams.scontextWidth.W)) val fiom = Output(Bool()) val vector = usingVector.option(new Bundle { val vconfig = Output(new VConfig()) val vstart = Output(UInt(maxVLMax.log2.W)) val vxrm = Output(UInt(2.W)) val set_vs_dirty = Input(Bool()) val set_vconfig = Flipped(Valid(new VConfig)) val set_vstart = Flipped(Valid(vstart)) val set_vxsat = Input(Bool()) }) } class VConfig(implicit p: Parameters) extends CoreBundle { val vl = UInt((maxVLMax.log2 + 1).W) val vtype = new VType } object VType { def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = { val res = 0.U.asTypeOf(new VType) val in = that.asTypeOf(res) val vill = (in.max_vsew.U < in.vsew) \|\| !in.lmul_ok \|\| in.reserved =/= 0.U \|\| in.vill when (!vill \|\| ignore_vill.B) { res := in res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0) } res.reserved := 0.U res.vill := vill res } def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt = VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero) } class VType(implicit p: Parameters) extends CoreBundle { val vill = Bool() val reserved = UInt((xLen - 9).W) val vma = Bool() val vta = Bool() val vsew = UInt(3.W) val vlmul_sign = Bool() val vlmul_mag = UInt(2.W) def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt @deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9") def vlmul: UInt = vlmul_mag def max_vsew = log2Ceil(eLen/8) def max_vlmul = (1 << vlmul_mag.getWidth) - 1 def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B) def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1 def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U) def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = { val atLeastMaxVLMax = useMax \|\| Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U) val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0) val atLeastVLMax = atLeastMaxVLMax \|\| (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR val isZero = vill \|\| useZero Mux(!isZero && atLeastVLMax, vlMax, 0.U) \| Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U) } } class CSRFile( perfEventSets: EventSets = new EventSets(Seq()), customCSRs: Seq[CustomCSR] = Nil, roccCSRs: Seq[CustomCSR] = Nil, hasBeu: Boolean = false)(implicit p: Parameters) extends CoreModule()(p) with HasCoreParameters { val io = IO(new CSRFileIO(hasBeu) { val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO) val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO) }) io.rw_stall := false.B val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := PRV.M.U reset_mstatus.prv := PRV.M.U reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U) val reg_mstatus = RegInit(reset_mstatus) val new_prv = WireDefault(reg_mstatus.prv) reg_mstatus.prv := legalizePrivilege(new_prv) val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR())) reset_dcsr.xdebugver := 1.U reset_dcsr.prv := PRV.M.U val reg_dcsr = RegInit(reset_dcsr) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) sup.usip := false.B sup.ssip := usingSupervisor.B sup.vssip := usingHypervisor.B sup.msip := true.B sup.utip := false.B sup.stip := usingSupervisor.B sup.vstip := usingHypervisor.B sup.mtip := true.B sup.ueip := false.B sup.seip := usingSupervisor.B sup.vseip := usingHypervisor.B sup.meip := true.B sup.sgeip := false.B sup.rocc := usingRoCC.B sup.debug := false.B sup.zero1 := false.B sup.lip foreach { _ := true.B } val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U val del = WireDefault(sup) del.msip := false.B del.mtip := false.B del.meip := false.B (sup.asUInt \| supported_high_interrupts, del.asUInt) } val delegable_base_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_page_fault, Causes.breakpoint, Causes.load_page_fault, Causes.store_page_fault, Causes.misaligned_load, Causes.misaligned_store, Causes.illegal_instruction, Causes.user_ecall, ) val delegable_hypervisor_exceptions = Seq( Causes.virtual_supervisor_ecall, Causes.fetch_guest_page_fault, Causes.load_guest_page_fault, Causes.virtual_instruction, Causes.store_guest_page_fault, ) val delegable_exceptions = ( delegable_base_exceptions ++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq()) ).map(1 << _).sum.U val hs_delegable_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_access, Causes.illegal_instruction, Causes.breakpoint, Causes.misaligned_load, Causes.load_access, Causes.misaligned_store, Causes.store_access, Causes.user_ecall, Causes.fetch_page_fault, Causes.load_page_fault, Causes.store_page_fault).map(1 << _).sum.U val (hs_delegable_interrupts, mideleg_always_hs) = { val always = WireDefault(0.U.asTypeOf(new MIP())) always.vssip := usingHypervisor.B always.vstip := usingHypervisor.B always.vseip := usingHypervisor.B val deleg = WireDefault(always) deleg.lip.foreach { _ := usingHypervisor.B } (deleg.asUInt, always.asUInt) } val reg_debug = RegInit(false.B) val reg_dpc = Reg(UInt(vaddrBitsExtended.W)) val reg_dscratch0 = Reg(UInt(xLen.W)) val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W))) val reg_singleStepped = Reg(Bool()) val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W))) val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W))) val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W)) val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP)) val reg_pmp = Reg(Vec(nPMPs, new PMPReg)) val reg_mie = Reg(UInt(xLen.W)) val (reg_mideleg, read_mideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_interrupts \| mideleg_always_hs, 0.U)) } val (reg_medeleg, read_medeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U)) } val reg_mip = Reg(new MIP) val reg_mepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mcause = RegInit(0.U(xLen.W)) val reg_mtval = Reg(UInt(vaddrBitsExtended.W)) val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W)) val reg_mscratch = Reg(Bits(xLen.W)) val mtvecWidth = paddrBits min xLen val reg_mtvec = mtvecInit match { case Some(addr) => RegInit(addr.U(mtvecWidth.W)) case None => Reg(UInt(mtvecWidth.W)) } val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus())) reset_mnstatus.mpp := PRV.M.U val reg_mnscratch = Reg(Bits(xLen.W)) val reg_mnepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mncause = RegInit(0.U(xLen.W)) val reg_mnstatus = RegInit(reset_mnstatus) val reg_rnmie = RegInit(true.B) val nmie = reg_rnmie val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U val (reg_mcounteren, read_mcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingUser.B, reg & delegable_counters, 0.U)) } val (reg_scounteren, read_scounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U)) } val (reg_hideleg, read_hideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U)) } val (reg_hedeleg, read_hedeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U)) } val hs_delegable_counters = delegable_counters val (reg_hcounteren, read_hcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U)) } val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus)) val reg_hgatp = Reg(new PTBR) val reg_htval = Reg(reg_mtval2.cloneType) val read_hvip = reg_mip.asUInt & hs_delegable_interrupts val read_hie = reg_mie & hs_delegable_interrupts val (reg_vstvec, read_vstvec) = { val reg = Reg(UInt(vaddrBitsExtended.W)) (reg, formTVec(reg).sextTo(xLen)) } val reg_vsstatus = Reg(new MStatus) val reg_vsscratch = Reg(Bits(xLen.W)) val reg_vsepc = Reg(UInt(vaddrBitsExtended.W)) val reg_vscause = Reg(Bits(xLen.W)) val reg_vstval = Reg(UInt(vaddrBitsExtended.W)) val reg_vsatp = Reg(new PTBR) val reg_sepc = Reg(UInt(vaddrBitsExtended.W)) val reg_scause = Reg(Bits(xLen.W)) val reg_stval = Reg(UInt(vaddrBitsExtended.W)) val reg_sscratch = Reg(Bits(xLen.W)) val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W)) val reg_satp = Reg(new PTBR) val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) } val reg_fflags = Reg(UInt(5.W)) val reg_frm = Reg(UInt(3.W)) val reg_vconfig = usingVector.option(Reg(new VConfig)) val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W))) val reg_vxsat = usingVector.option(Reg(Bool())) val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W))) val reg_mtinst_read_pseudo = Reg(Bool()) val reg_htinst_read_pseudo = Reg(Bool()) // XLEN=32: 0x00002000 // XLEN=64: 0x00003000 val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W))) val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W)) io.inhibit_cycle := reg_mcountinhibit(0) val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2)) val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0)) else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) } val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W))) (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e } val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) => WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) } val mip = WireDefault(reg_mip) mip.lip := (io.interrupts.lip: Seq[Bool]) mip.mtip := io.interrupts.mtip mip.msip := io.interrupts.msip mip.meip := io.interrupts.meip // seip is the OR of reg_mip.seip and the actual line from the PLIC io.interrupts.seip.foreach { mip.seip := reg_mip.seip \|\| _ } // Simimlar sort of thing would apply if the PLIC had a VSEIP line: //io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip \|\| _ } mip.rocc := io.rocc_interrupt val read_mip = mip.asUInt & supported_interrupts val read_hip = read_mip & hs_delegable_interrupts val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U)) val pending_interrupts = high_interrupts \| (read_mip & reg_mie) val d_interrupts = io.interrupts.debug << CSR.debugIntCause val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi => (((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) \| io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U), !io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B) val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U \|\| reg_mstatus.mie), ~(~pending_interrupts \| read_mideleg), 0.U) val s_interrupts = Mux(nmie && (reg_mstatus.v \|\| reg_mstatus.prv < PRV.S.U \|\| (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U) val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U \|\| reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U) val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts)) val interruptMSB = BigInt(1) << (xLen-1) val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt io.interrupt := (anyInterrupt && !io.singleStep \|\| reg_singleStepped) && !(reg_debug \|\| io.status.cease) io.interrupt_cause := interruptCause io.bp := reg_bp take nBreakpoints io.mcontext := reg_mcontext.getOrElse(0.U) io.scontext := reg_scontext.getOrElse(0.U) io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) \|\| (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) \|\| (reg_mstatus.v && reg_henvcfg.fiom) io.pmp := reg_pmp.map(PMP(_)) val isaMaskString = (if (usingMulDiv) "M" else "") + (if (usingAtomics) "A" else "") + (if (fLen >= 32) "F" else "") + (if (fLen >= 64) "D" else "") + (if (coreParams.hasV) "V" else "") + (if (usingCompressed) "C" else "") val isaString = (if (coreParams.useRVE) "E" else "I") + isaMaskString + (if (customIsaExt.isDefined \|\| usingRoCC) "X" else "") + (if (usingSupervisor) "S" else "") + (if (usingHypervisor) "H" else "") + (if (usingUser) "U" else "") val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) \| isaStringToMask(isaString) val reg_misa = RegInit(isaMax.U) val read_mstatus = io.status.asUInt.extract(xLen-1,0) val read_mtvec = formTVec(reg_mtvec).padTo(xLen) val read_stvec = formTVec(reg_stvec).sextTo(xLen) val read_mapping = LinkedHashMap[Int,Bits]( CSRs.tselect -> reg_tselect, CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt, CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen), CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt, CSRs.misa -> reg_misa, CSRs.mstatus -> read_mstatus, CSRs.mtvec -> read_mtvec, CSRs.mip -> read_mip, CSRs.mie -> reg_mie, CSRs.mscratch -> reg_mscratch, CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen), CSRs.mtval -> reg_mtval.sextTo(xLen), CSRs.mcause -> reg_mcause, CSRs.mhartid -> io.hartid) val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.dcsr -> reg_dcsr.asUInt, CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen), CSRs.dscratch0 -> reg_dscratch0.asUInt) ++ reg_dscratch1.map(r => CSRs.dscratch1 -> r) val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus())) read_mnstatus.mpp := reg_mnstatus.mpp read_mnstatus.mpv := reg_mnstatus.mpv read_mnstatus.mie := reg_rnmie val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits]( CustomCSRs.mnscratch -> reg_mnscratch, CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen), CustomCSRs.mncause -> reg_mncause, CustomCSRs.mnstatus -> read_mnstatus.asUInt) val context_csrs = LinkedHashMap[Int,Bits]() ++ reg_mcontext.map(r => CSRs.mcontext -> r) ++ reg_scontext.map(r => CSRs.scontext -> r) val read_fcsr = Cat(reg_frm, reg_fflags) val fp_csrs = LinkedHashMap[Int,Bits]() ++ usingFPU.option(CSRs.fflags -> reg_fflags) ++ usingFPU.option(CSRs.frm -> reg_frm) ++ (usingFPU \|\| usingVector).option(CSRs.fcsr -> read_fcsr) val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U)) val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.vxsat -> reg_vxsat.get, CSRs.vxrm -> reg_vxrm.get, CSRs.vcsr -> read_vcsr, CSRs.vstart -> reg_vstart.get, CSRs.vtype -> reg_vconfig.get.vtype.asUInt, CSRs.vl -> reg_vconfig.get.vl, CSRs.vlenb -> (vLen / 8).U) read_mapping ++= debug_csrs read_mapping ++= nmi_csrs read_mapping ++= context_csrs read_mapping ++= fp_csrs read_mapping ++= vector_csrs if (coreParams.haveBasicCounters) { read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit read_mapping += CSRs.mcycle -> reg_cycle read_mapping += CSRs.minstret -> reg_instret for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U) zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) { read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN if (xLen == 32) { read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh } } if (usingUser) { read_mapping += CSRs.mcounteren -> read_mcounteren } read_mapping += CSRs.cycle -> reg_cycle read_mapping += CSRs.instret -> reg_instret if (xLen == 32) { read_mapping += CSRs.mcycleh -> (reg_cycle >> 32) read_mapping += CSRs.minstreth -> (reg_instret >> 32) read_mapping += CSRs.cycleh -> (reg_cycle >> 32) read_mapping += CSRs.instreth -> (reg_instret >> 32) } } if (usingUser) { read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt if (xLen == 32) read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32) } val sie_mask = { val sgeip_mask = WireInit(0.U.asTypeOf(new MIP)) sgeip_mask.sgeip := true.B read_mideleg & ~(hs_delegable_interrupts \| sgeip_mask.asUInt) } if (usingSupervisor) { val read_sie = reg_mie & sie_mask val read_sip = read_mip & sie_mask val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus)) read_sstatus.sd := io.status.sd read_sstatus.uxl := io.status.uxl read_sstatus.sd_rv32 := io.status.sd_rv32 read_sstatus.mxr := io.status.mxr read_sstatus.sum := io.status.sum read_sstatus.xs := io.status.xs read_sstatus.fs := io.status.fs read_sstatus.vs := io.status.vs read_sstatus.spp := io.status.spp read_sstatus.spie := io.status.spie read_sstatus.sie := io.status.sie read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0) read_mapping += CSRs.sip -> read_sip.asUInt read_mapping += CSRs.sie -> read_sie.asUInt read_mapping += CSRs.sscratch -> reg_sscratch read_mapping += CSRs.scause -> reg_scause read_mapping += CSRs.stval -> reg_stval.sextTo(xLen) read_mapping += CSRs.satp -> reg_satp.asUInt read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen) read_mapping += CSRs.stvec -> read_stvec read_mapping += CSRs.scounteren -> read_scounteren read_mapping += CSRs.mideleg -> read_mideleg read_mapping += CSRs.medeleg -> read_medeleg read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt } val pmpCfgPerCSR = xLen / new PMPConfig().getWidth def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR) if (reg_pmp.nonEmpty) { require(reg_pmp.size <= CSR.maxPMPs) val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP)) for (i <- 0 until read_pmp.size by pmpCfgPerCSR) read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt for ((pmp, i) <- read_pmp.zipWithIndex) read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr } // implementation-defined CSRs def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = { require(csr.mask >= 0 && csr.mask.bitLength <= xLen) require(!read_mapping.contains(csr.id)) val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W))) val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U csr_io.ren := read when (read && csr_io.stall) { io.rw_stall := true.B } read_mapping += csr.id -> reg reg } val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2)) val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2)) if (usingHypervisor) { read_mapping += CSRs.mtinst -> read_mtinst read_mapping += CSRs.mtval2 -> reg_mtval2 val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.hstatus -> read_hstatus read_mapping += CSRs.hedeleg -> read_hedeleg read_mapping += CSRs.hideleg -> read_hideleg read_mapping += CSRs.hcounteren-> read_hcounteren read_mapping += CSRs.hgatp -> reg_hgatp.asUInt read_mapping += CSRs.hip -> read_hip read_mapping += CSRs.hie -> read_hie read_mapping += CSRs.hvip -> read_hvip read_mapping += CSRs.hgeie -> 0.U read_mapping += CSRs.hgeip -> 0.U read_mapping += CSRs.htval -> reg_htval read_mapping += CSRs.htinst -> read_htinst read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt if (xLen == 32) read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32) val read_vsie = (read_hie & read_hideleg) >> 1 val read_vsip = (read_hip & read_hideleg) >> 1 val read_vsepc = readEPC(reg_vsepc).sextTo(xLen) val read_vstval = reg_vstval.sextTo(xLen) val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.vsstatus -> read_vsstatus read_mapping += CSRs.vsip -> read_vsip read_mapping += CSRs.vsie -> read_vsie read_mapping += CSRs.vsscratch -> reg_vsscratch read_mapping += CSRs.vscause -> reg_vscause read_mapping += CSRs.vstval -> read_vstval read_mapping += CSRs.vsatp -> reg_vsatp.asUInt read_mapping += CSRs.vsepc -> read_vsepc read_mapping += CSRs.vstvec -> read_vstvec } // mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U)) val decoded_addr = { val addr = Cat(io.status.v, io.rw.addr) val pats = for (((k, _), i) <- read_mapping.zipWithIndex) yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B))) val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats) val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap for ((k, v) <- unvirtualized_mapping) yield k -> { val alt: Option[Bool] = CSR.mode(k) match { // hcontext was assigned an unfortunate address; it lives where a // hypothetical vscontext will live. Exclude them from the S/VS remapping. // (on separate lines so scala-lint doesnt do something stupid) case _ if k == CSRs.scontext => None case _ if k == CSRs.hcontext => None // When V=1, if a corresponding VS CSR exists, access it instead... case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB)) // ...and don't access the original S-mode version. case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B) case _ => None } alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v) } } val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata) val system_insn = io.rw.cmd === CSR.I val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU) val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N), EBREAK-> List(N,Y,N,N,N,N,N,N,N), MRET-> List(N,N,Y,N,N,N,N,N,N), CEASE-> List(N,N,N,Y,N,N,N,N,N), WFI-> List(N,N,N,N,Y,N,N,N,N)) ++ usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++ coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++ usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++ usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++ usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++ (if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq()) val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = { val insn = ECALL.value.U \| (io.rw.addr << 20) DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool) } for (io_dec <- io.decode) { val addr = io_dec.inst(31, 20) def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_\|\|_) def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U)) val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil = DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool) val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) \|\| addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U)) val allow_wfi = (!usingSupervisor).B \|\| reg_mstatus.prv > PRV.S.U \|\| !reg_mstatus.tw && (!reg_mstatus.v \|\| !reg_hstatus.vtw) val allow_sfence_vma = (!usingVM).B \|\| reg_mstatus.prv > PRV.S.U \|\| !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) val allow_hfence_vvma = (!usingHypervisor).B \|\| !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U) val allow_hlsv = (!usingHypervisor).B \|\| !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U \|\| reg_hstatus.hu) val allow_sret = (!usingSupervisor).B \|\| reg_mstatus.prv > PRV.S.U \|\| !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0) val allow_counter = (reg_mstatus.prv > PRV.S.U \|\| read_mcounteren(counter_addr)) && (!usingSupervisor.B \|\| reg_mstatus.prv >= PRV.S.U \|\| read_scounteren(counter_addr)) && (!usingHypervisor.B \|\| !reg_mstatus.v \|\| read_hcounteren(counter_addr)) io_dec.fp_illegal := io.status.fs === 0.U \|\| reg_mstatus.v && reg_vsstatus.fs === 0.U \|\| !reg_misa('f'-'a') io_dec.vector_illegal := io.status.vs === 0.U \|\| reg_mstatus.v && reg_vsstatus.vs === 0.U \|\| !reg_misa('v'-'a') io_dec.fp_csr := decodeFast(fp_csrs.keys.toList) io_dec.vector_csr := decodeFast(vector_csrs.keys.toList) io_dec.rocc_illegal := io.status.xs === 0.U \|\| reg_mstatus.v && reg_vsstatus.xs === 0.U \|\| !reg_misa('x'-'a') val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) \|\| usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U val csr_exists = decodeAny(read_mapping) io_dec.read_illegal := !csr_addr_legal \|\| !csr_exists \|\| ((addr === CSRs.satp.U \|\| addr === CSRs.hgatp.U) && !allow_sfence_vma) \|\| is_counter && !allow_counter \|\| decodeFast(debug_csrs.keys.toList) && !reg_debug \|\| decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal \|\| io_dec.fp_csr && io_dec.fp_illegal io_dec.write_illegal := addr(11,10).andR io_dec.write_flush := { val addr_m = addr \| (PRV.M.U << CSR.modeLSB) !(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U) } io_dec.system_illegal := !csr_addr_legal && !is_hlsv \|\| is_wfi && !allow_wfi \|\| is_ret && !allow_sret \|\| is_ret && addr(10) && addr(7) && !reg_debug \|\| (is_sfence \|\| is_hfence_gvma) && !allow_sfence_vma \|\| is_hfence_vvma && !allow_hfence_vvma \|\| is_hlsv && !allow_hlsv io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && ( CSR.mode(addr) === PRV.H.U \|\| is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) \|\| !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) \|\| CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) \|\| addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm) io_dec.virtual_system_illegal := reg_mstatus.v && ( is_hfence_vvma \|\| is_hfence_gvma \|\| is_hlsv \|\| is_wfi && (!reg_mstatus.prv(0) \|\| !reg_mstatus.tw && reg_hstatus.vtw) \|\| is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) \|\| reg_hstatus.vtsr) \|\| is_sfence && (!reg_mstatus.prv(0) \|\| reg_hstatus.vtvm)) } val cause = Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv), Mux[UInt](insn_break, Causes.breakpoint.U, io.cause)) val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0) val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0) val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv) val trapToDebug = usingDebug.B && (reg_singleStepped \|\| causeIsDebugInt \|\| causeIsDebugTrigger \|\| causeIsDebugBreak \|\| reg_debug) val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800)) val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808)) val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U) val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs)) val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs)) def mtvecBaseAlign = 2 def mtvecInterruptAlign = { require(reg_mip.getWidth <= xLen) log2Ceil(xLen) } val notDebugTVec = { val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec) val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset) val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign) } val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U \|\| cause_lsbs === CSR.rnmiBEUCause.U) val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U val causeIsNmi = causeIsRnmiInt val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U) val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U) val trapToNmiInt = usingNMI.B && causeIsNmi val trapToNmiXcpt = usingNMI.B && !nmie val trapToNmi = trapToNmiInt \|\| trapToNmiXcpt val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1 val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec)) io.evec := tvec io.ptbr := reg_satp io.hgatp := reg_hgatp io.vsatp := reg_vsatp io.eret := insn_call \|\| insn_break \|\| insn_ret io.singleStep := reg_dcsr.step && !reg_debug io.status := reg_mstatus io.status.sd := io.status.fs.andR \|\| io.status.xs.andR \|\| io.status.vs.andR io.status.debug := reg_debug io.status.isa := reg_misa io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv) io.status.dv := reg_mstatus.v \|\| Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B) io.status.sd_rv32 := (xLen == 32).B && io.status.sd io.status.mpv := reg_mstatus.mpv io.status.gva := reg_mstatus.gva io.hstatus := reg_hstatus io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.gstatus := reg_vsstatus io.gstatus.sd := io.gstatus.fs.andR \|\| io.gstatus.xs.andR \|\| io.gstatus.vs.andR io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd val exception = insn_call \|\| insn_break \|\| io.exception assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive") when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B } when (pending_interrupts.orR \|\| io.interrupts.debug \|\| exception) { reg_wfi := false.B } io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } ) when (io.retire(0) \|\| exception) { reg_singleStepped := true.B } when (!io.singleStep) { reg_singleStepped := false.B } assert(!io.singleStep \|\| io.retire <= 1.U) assert(!reg_singleStepped \|\| io.retire === 0.U) val epc = formEPC(io.pc) val tval = Mux(insn_break, epc, io.tval) when (exception) { when (trapToDebug) { when (!reg_debug) { reg_mstatus.v := false.B reg_debug := true.B reg_dpc := epc reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U))) reg_dcsr.prv := trimPrivilege(reg_mstatus.prv) reg_dcsr.v := reg_mstatus.v new_prv := PRV.M.U } }.elsewhen (trapToNmiInt) { when (reg_rnmie) { reg_mstatus.v := false.B reg_mnstatus.mpv := reg_mstatus.v reg_rnmie := false.B reg_mnepc := epc reg_mncause := (BigInt(1) << (xLen-1)).U \| Mux(causeIsRnmiBEU, 3.U, 2.U) reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv) new_prv := PRV.M.U } }.elsewhen (delegateVS && nmie) { reg_mstatus.v := true.B reg_vsstatus.spp := reg_mstatus.prv reg_vsepc := epc reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause) reg_vstval := tval reg_vsstatus.spie := reg_vsstatus.sie reg_vsstatus.sie := false.B new_prv := PRV.S.U }.elsewhen (delegate && nmie) { reg_mstatus.v := false.B reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp) reg_hstatus.gva := io.gva reg_hstatus.spv := reg_mstatus.v reg_sepc := epc reg_scause := cause reg_stval := tval reg_htval := io.htval reg_htinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.spie := reg_mstatus.sie reg_mstatus.spp := reg_mstatus.prv reg_mstatus.sie := false.B new_prv := PRV.S.U }.otherwise { reg_mstatus.v := false.B reg_mstatus.mpv := reg_mstatus.v reg_mstatus.gva := io.gva reg_mepc := epc reg_mcause := cause reg_mtval := tval reg_mtval2 := io.htval reg_mtinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.mpie := reg_mstatus.mie reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv) reg_mstatus.mie := false.B new_prv := PRV.M.U } } for (i <- 0 until supported_interrupts.getWidth) { val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"INTERRUPT_M_$i") property.cover(en && delegable && delegate, s"INTERRUPT_S_$i") } for (i <- 0 until xLen) { val supported_exceptions: BigInt = 0x8fe \| (if (usingCompressed && !coreParams.misaWritable) 0 else 1) \| (if (usingUser) 0x100 else 0) \| (if (usingSupervisor) 0x200 else 0) \| (if (usingVM) 0xb000 else 0) if (((supported_exceptions >> i) & 1) != 0) { val en = exception && cause === i.U val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"EXCEPTION_M_$i") property.cover(en && delegable && delegate, s"EXCEPTION_S_$i") } } when (insn_ret) { val ret_prv = WireInit(UInt(), DontCare) when (usingSupervisor.B && !io.rw.addr(9)) { when (!reg_mstatus.v) { reg_mstatus.sie := reg_mstatus.spie reg_mstatus.spie := true.B reg_mstatus.spp := PRV.U.U ret_prv := reg_mstatus.spp reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv io.evec := readEPC(reg_sepc) reg_hstatus.spv := false.B }.otherwise { reg_vsstatus.sie := reg_vsstatus.spie reg_vsstatus.spie := true.B reg_vsstatus.spp := PRV.U.U ret_prv := reg_vsstatus.spp reg_mstatus.v := usingHypervisor.B io.evec := readEPC(reg_vsepc) } }.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) { ret_prv := reg_dcsr.prv reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U reg_debug := false.B io.evec := readEPC(reg_dpc) }.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) { ret_prv := reg_mnstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U reg_rnmie := true.B io.evec := readEPC(reg_mnepc) }.otherwise { reg_mstatus.mie := reg_mstatus.mpie reg_mstatus.mpie := true.B reg_mstatus.mpp := legalizePrivilege(PRV.U.U) reg_mstatus.mpv := false.B ret_prv := reg_mstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U io.evec := readEPC(reg_mepc) } new_prv := ret_prv when (usingUser.B && ret_prv <= PRV.S.U) { reg_mstatus.mprv := false.B } } io.time := reg_cycle io.csr_stall := reg_wfi \|\| io.status.cease io.status.cease := RegEnable(true.B, false.B, insn_cease) io.status.wfi := reg_wfi for ((io, reg) <- io.customCSRs zip reg_custom) { io.wen := false.B io.wdata := wdata io.value := reg } for ((io, reg) <- io.roccCSRs zip reg_rocc) { io.wen := false.B io.wdata := wdata io.value := reg } io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) // cover access to register val coverable_counters = read_mapping.filterNot { case (k, _) => k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM } coverable_counters.foreach( {case (k, v) => { when (!k.U(11,10).andR) { // Cover points for RW CSR registers property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } .otherwise { // Cover points for RO CSR registers property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } }}) val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B)) io.vector.foreach { vio => when (set_vs_dirty) { assert(reg_mstatus.vs > 0.U) when (reg_mstatus.v) { reg_vsstatus.vs := 3.U } reg_mstatus.vs := 3.U } } val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B)) if (coreParams.haveFSDirty) { when (set_fs_dirty) { assert(reg_mstatus.fs > 0.U) when (reg_mstatus.v) { reg_vsstatus.fs := 3.U } reg_mstatus.fs := 3.U } } io.fcsr_rm := reg_frm when (io.fcsr_flags.valid) { reg_fflags := reg_fflags \| io.fcsr_flags.bits set_fs_dirty := true.B } io.vector.foreach { vio => when (vio.set_vxsat) { reg_vxsat.get := true.B set_vs_dirty := true.B } } val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) \|\| io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U) when (csr_wen) { val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB / val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_)) when (decoded_addr(CSRs.mstatus)) { val new_mstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.mie := new_mstatus.mie reg_mstatus.mpie := new_mstatus.mpie if (usingUser) { reg_mstatus.mprv := new_mstatus.mprv reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp) if (usingSupervisor) { reg_mstatus.spp := new_mstatus.spp reg_mstatus.spie := new_mstatus.spie reg_mstatus.sie := new_mstatus.sie reg_mstatus.tw := new_mstatus.tw reg_mstatus.tsr := new_mstatus.tsr } if (usingVM) { reg_mstatus.mxr := new_mstatus.mxr reg_mstatus.sum := new_mstatus.sum reg_mstatus.tvm := new_mstatus.tvm } if (usingHypervisor) { reg_mstatus.mpv := new_mstatus.mpv reg_mstatus.gva := new_mstatus.gva } } if (usingSupervisor \|\| usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs) reg_mstatus.vs := formVS(new_mstatus.vs) } when (decoded_addr(CSRs.misa)) { val mask = isaStringToMask(isaMaskString).U(xLen.W) val f = wdata('f' - 'a') // suppress write if it would cause the next fetch to be misaligned when (!usingCompressed.B \|\| !io.pc(1) \|\| wdata('c' - 'a')) { if (coreParams.misaWritable) reg_misa := ~(~wdata \| (!f << ('d' - 'a'))) & mask \| reg_misa & ~mask } } when (decoded_addr(CSRs.mip)) { // MIP should be modified based on the value in reg_mip, not the value // in read_mip, since read_mip.seip is the OR of reg_mip.seip and // io.interrupts.seip. We don't want the value on the PLIC line to // inadvertently be OR'd into read_mip.seip. val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP) if (usingSupervisor) { reg_mip.ssip := new_mip.ssip reg_mip.stip := new_mip.stip reg_mip.seip := new_mip.seip } if (usingHypervisor) { reg_mip.vssip := new_mip.vssip } } when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts } when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) } when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata } if (mtvecWritable) when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata } when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U } when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata } if (usingNMI) { val new_mnstatus = wdata.asTypeOf(new MNStatus()) when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata } when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) } when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U } when (decoded_addr(CustomCSRs.mnstatus)) { reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp) reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv reg_rnmie := reg_rnmie \| new_mnstatus.mie // mnie bit settable but not clearable from software } } for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) { writeCounter(i + CSR.firstMHPC, c, wdata) when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) } } if (coreParams.haveBasicCounters) { when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero writeCounter(CSRs.mcycle, reg_cycle, wdata) writeCounter(CSRs.minstret, reg_instret, wdata) } if (usingFPU) { when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata } when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata } when (decoded_addr(CSRs.fcsr)) { set_fs_dirty := true.B reg_fflags := wdata reg_frm := wdata >> reg_fflags.getWidth } } if (usingDebug) { when (decoded_addr(CSRs.dcsr)) { val new_dcsr = wdata.asTypeOf(new DCSR()) reg_dcsr.step := new_dcsr.step reg_dcsr.ebreakm := new_dcsr.ebreakm if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv) if (usingHypervisor) reg_dcsr.v := new_dcsr.v } when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) } when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata } reg_dscratch1.foreach { r => when (decoded_addr(CSRs.dscratch1)) { r := wdata } } } if (usingSupervisor) { when (decoded_addr(CSRs.sstatus)) { val new_sstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.sie := new_sstatus.sie reg_mstatus.spie := new_sstatus.spie reg_mstatus.spp := new_sstatus.spp reg_mstatus.fs := formFS(new_sstatus.fs) reg_mstatus.vs := formVS(new_sstatus.vs) if (usingVM) { reg_mstatus.mxr := new_sstatus.mxr reg_mstatus.sum := new_sstatus.sum } } when (decoded_addr(CSRs.sip)) { val new_sip = ((read_mip & ~read_mideleg) \| (wdata & read_mideleg)).asTypeOf(new MIP()) reg_mip.ssip := new_sip.ssip } when (decoded_addr(CSRs.satp)) { if (usingVM) { val new_satp = wdata.asTypeOf(new PTBR()) when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) { reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_\|_).U reg_satp.ppn := new_satp.ppn(ppnBits-1,0) if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0) } } } when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) \| (wdata & sie_mask) } when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata } when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) } when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata } when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask } when (decoded_addr(CSRs.stval)) { reg_stval := wdata } when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata } when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata } when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata } when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) } } if (usingHypervisor) { when (decoded_addr(CSRs.hstatus)) { val new_hstatus = wdata.asTypeOf(new HStatus()) reg_hstatus.gva := new_hstatus.gva reg_hstatus.spv := new_hstatus.spv reg_hstatus.spvp := new_hstatus.spvp reg_hstatus.hu := new_hstatus.hu reg_hstatus.vtvm := new_hstatus.vtvm reg_hstatus.vtw := new_hstatus.vtw reg_hstatus.vtsr := new_hstatus.vtsr reg_hstatus.vsxl := new_hstatus.vsxl } when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata } when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata } when (decoded_addr(CSRs.hgatp)) { val new_hgatp = wdata.asTypeOf(new PTBR()) val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_)) when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) { reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_\|_).U } reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W)) if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0) } when (decoded_addr(CSRs.hip)) { val new_hip = ((read_mip & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_hip.vssip } when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts) } when (decoded_addr(CSRs.hvip)) { val new_sip = ((read_mip & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_sip.vssip reg_mip.vstip := new_sip.vstip reg_mip.vseip := new_sip.vseip } when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata } when (decoded_addr(CSRs.htval)) { reg_htval := wdata } when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata } val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12)) when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo } when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo } when (decoded_addr(CSRs.vsstatus)) { val new_vsstatus = wdata.asTypeOf(new MStatus()) reg_vsstatus.sie := new_vsstatus.sie reg_vsstatus.spie := new_vsstatus.spie reg_vsstatus.spp := new_vsstatus.spp reg_vsstatus.mxr := new_vsstatus.mxr reg_vsstatus.sum := new_vsstatus.sum reg_vsstatus.fs := formFS(new_vsstatus.fs) reg_vsstatus.vs := formVS(new_vsstatus.vs) } when (decoded_addr(CSRs.vsip)) { val new_vsip = ((read_hip & ~read_hideleg) \| ((wdata << 1) & read_hideleg)).asTypeOf(new MIP()) reg_mip.vssip := new_vsip.vssip } when (decoded_addr(CSRs.vsatp)) { val new_vsatp = wdata.asTypeOf(new PTBR()) val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U)) when (mode_ok) { reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_\|_).U } when (mode_ok \|\| !reg_mstatus.v) { reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0) if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0) } } when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) \| ((wdata << 1) & read_hideleg) } when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata } when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) } when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata } when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask } when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata } when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) } } if (usingUser) { when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata } when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) } } if (nBreakpoints > 0) { when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata } for ((bp, i) <- reg_bp.zipWithIndex) { when (i.U === reg_tselect && (!bp.control.dmode \|\| reg_debug)) { when (decoded_addr(CSRs.tdata2)) { bp.address := wdata } when (decoded_addr(CSRs.tdata3)) { if (coreParams.mcontextWidth > 0) { bp.textra.mselect := wdata(bp.textra.mselectPos) bp.textra.mvalue := wdata >> bp.textra.mvaluePos } if (coreParams.scontextWidth > 0) { bp.textra.sselect := wdata(bp.textra.sselectPos) bp.textra.svalue := wdata >> bp.textra.svaluePos } } when (decoded_addr(CSRs.tdata1)) { bp.control := wdata.asTypeOf(bp.control) val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control) val dMode = newBPC.dmode && reg_debug && (prevDMode \|\| !prevChain) bp.control.dmode := dMode when (dMode \|\| (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U } bp.control.chain := newBPC.chain && !(prevChain \|\| nextChain) && (dMode \|\| !nextDMode) } } } } reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }} reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }} if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) { require(xLen % pmp.cfg.getWidth == 0) when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) { val newCfg = (wdata >> ((i pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig()) pmp.cfg := newCfg // disallow unreadable but writable PMPs pmp.cfg.w := newCfg.w && newCfg.r // can't select a=NA4 with coarse-grained PMPs if (pmpGranularity.log2 > PMP.lgAlign) pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR) } when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) { pmp.addr := wdata } } def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (decoded_addr(csr.id)) { reg := (wdata & mask) \| (reg & ~mask) io.wen := true.B } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { writeCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { writeCustomCSR(io, csr, reg) } if (usingVector) { when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata } when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata } when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata } when (decoded_addr(CSRs.vcsr)) { set_vs_dirty := true.B reg_vxsat.get := wdata reg_vxrm.get := wdata >> 1 } } } def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (io.set) { reg := (io.sdata & mask) \| (reg & ~mask) } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { setCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { setCustomCSR(io, csr, reg) } io.vector.map { vio => when (vio.set_vconfig.valid) { // user of CSRFile is responsible for set_vs_dirty in this case assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax) reg_vconfig.get := vio.set_vconfig.bits } when (vio.set_vstart.valid) { set_vs_dirty := true.B reg_vstart.get := vio.set_vstart.bits } vio.vstart := reg_vstart.get vio.vconfig := reg_vconfig.get vio.vxrm := reg_vxrm.get when (reset.asBool) { reg_vconfig.get.vl := 0.U reg_vconfig.get.vtype := 0.U.asTypeOf(new VType) reg_vconfig.get.vtype.vill := true.B } } when(reset.asBool) { reg_satp.mode := 0.U reg_vsatp.mode := 0.U reg_hgatp.mode := 0.U } if (!usingVM) { reg_satp.mode := 0.U reg_satp.ppn := 0.U reg_satp.asid := 0.U } if (!usingHypervisor) { reg_vsatp.mode := 0.U reg_vsatp.ppn := 0.U reg_vsatp.asid := 0.U reg_hgatp.mode := 0.U reg_hgatp.ppn := 0.U reg_hgatp.asid := 0.U } if (!(asIdBits > 0)) { reg_satp.asid := 0.U reg_vsatp.asid := 0.U } if (!(vmIdBits > 0)) { reg_hgatp.asid := 0.U } reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U) if (nBreakpoints <= 1) reg_tselect := 0.U for (bpc <- reg_bp map {_.control}) { bpc.ttype := bpc.tType.U bpc.maskmax := bpc.maskMax.U bpc.reserved := 0.U bpc.zero := 0.U bpc.h := false.B if (!usingSupervisor) bpc.s := false.B if (!usingUser) bpc.u := false.B if (!usingSupervisor && !usingUser) bpc.m := true.B when (reset.asBool) { bpc.action := 0.U bpc.dmode := false.B bpc.chain := false.B bpc.r := false.B bpc.w := false.B bpc.x := false.B } } for (bpx <- reg_bp map {_.textra}) { if (coreParams.mcontextWidth == 0) bpx.mselect := false.B if (coreParams.scontextWidth == 0) bpx.sselect := false.B } for (bp <- reg_bp drop nBreakpoints) bp := 0.U.asTypeOf(new BP()) for (pmp <- reg_pmp) { pmp.cfg.res := 0.U when (reset.asBool) { pmp.reset() } } for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) { t.exception := io.retire >= i.U && exception t.valid := io.retire > i.U \|\| t.exception t.insn := insn t.iaddr := io.pc t.priv := Cat(reg_debug, reg_mstatus.prv) t.cause := cause t.interrupt := cause(xLen-1) t.tval := io.tval t.wdata.foreach(_ := DontCare) } def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = { val nonstandard = supported_interrupts.getWidth-1 to 12 by -1 // MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4) val priority = nonstandard ++ standard val masks = masksIn.reverse val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_\|\|_) val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U)))) (any, which) } def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = { (Mux(cmd(1), rdata, 0.U) \| wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U) } def legalizePrivilege(priv: UInt): UInt = if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv) else if (usingUser) Fill(2, priv(0)) else PRV.M.U def trimPrivilege(priv: UInt): UInt = if (usingSupervisor) priv else legalizePrivilege(priv) def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { if (xLen == 32) { val hi = lo + CSRs.mcycleh - CSRs.mcycle when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } } else { when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) } } } def formEPC(x: UInt) = ~(~x \| (if (usingCompressed) 1.U else 3.U)) def readEPC(x: UInt) = ~(~x \| Mux(reg_misa('c' - 'a'), 1.U, 3.U)) def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) \| 2).U, 2.U) def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_\|_) def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR) def formVS(vs: UInt) = if (usingVector) vs else 0.U }	module Rocket( // @[RocketCore.scala:153:7] input clock, // @[RocketCore.scala:153:7] input reset, // @[RocketCore.scala:153:7] input io_hartid, // @[RocketCore.scala:134:14] input io_interrupts_debug, // @[RocketCore.scala:134:14] input io_interrupts_mtip, // @[RocketCore.scala:134:14] input io_interrupts_msip, // @[RocketCore.scala:134:14] input io_interrupts_meip, // @[RocketCore.scala:134:14] input io_interrupts_seip, // @[RocketCore.scala:134:14] output io_imem_might_request, // @[RocketCore.scala:134:14] output io_imem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_imem_req_bits_pc, // @[RocketCore.scala:134:14] output io_imem_req_bits_speculative, // @[RocketCore.scala:134:14] output io_imem_sfence_valid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_imem_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_asid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_hv, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_hg, // @[RocketCore.scala:134:14] output io_imem_resp_ready, // @[RocketCore.scala:134:14] input io_imem_resp_valid, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_btb_cfiType, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_taken, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_btb_mask, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bridx, // @[RocketCore.scala:134:14] input [38:0] io_imem_resp_bits_btb_target, // @[RocketCore.scala:134:14] input [4:0] io_imem_resp_bits_btb_entry, // @[RocketCore.scala:134:14] input [7:0] io_imem_resp_bits_btb_bht_history, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bht_value, // @[RocketCore.scala:134:14] input [39:0] io_imem_resp_bits_pc, // @[RocketCore.scala:134:14] input [31:0] io_imem_resp_bits_data, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_mask, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_pf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_gf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_ae_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_imem_gpa_valid, // @[RocketCore.scala:134:14] input [39:0] io_imem_gpa_bits, // @[RocketCore.scala:134:14] input io_imem_gpa_is_pte, // @[RocketCore.scala:134:14] output io_imem_btb_update_valid, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_prediction_cfiType, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_taken, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_prediction_mask, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_bridx, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_prediction_target, // @[RocketCore.scala:134:14] output [4:0] io_imem_btb_update_bits_prediction_entry, // @[RocketCore.scala:134:14] output [7:0] io_imem_btb_update_bits_prediction_bht_history, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_bht_value, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_pc, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_target, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_isValid, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_br_pc, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_cfiType, // @[RocketCore.scala:134:14] output io_imem_bht_update_valid, // @[RocketCore.scala:134:14] output [7:0] io_imem_bht_update_bits_prediction_history, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_prediction_value, // @[RocketCore.scala:134:14] output [38:0] io_imem_bht_update_bits_pc, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_branch, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_taken, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_mispredict, // @[RocketCore.scala:134:14] output io_imem_flush_icache, // @[RocketCore.scala:134:14] input [39:0] io_imem_npc, // @[RocketCore.scala:134:14] input io_imem_perf_acquire, // @[RocketCore.scala:134:14] input io_imem_perf_tlbMiss, // @[RocketCore.scala:134:14] output io_imem_progress, // @[RocketCore.scala:134:14] input io_dmem_req_ready, // @[RocketCore.scala:134:14] output io_dmem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_dmem_req_bits_addr, // @[RocketCore.scala:134:14] output [6:0] io_dmem_req_bits_tag, // @[RocketCore.scala:134:14] output [4:0] io_dmem_req_bits_cmd, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_size, // @[RocketCore.scala:134:14] output io_dmem_req_bits_signed, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_dprv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_dv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_no_resp, // @[RocketCore.scala:134:14] output io_dmem_s1_kill, // @[RocketCore.scala:134:14] output [63:0] io_dmem_s1_data_data, // @[RocketCore.scala:134:14] input io_dmem_s2_nack, // @[RocketCore.scala:134:14] input io_dmem_s2_nack_cause_raw, // @[RocketCore.scala:134:14] input io_dmem_s2_uncached, // @[RocketCore.scala:134:14] input [31:0] io_dmem_s2_paddr, // @[RocketCore.scala:134:14] input io_dmem_resp_valid, // @[RocketCore.scala:134:14] input [39:0] io_dmem_resp_bits_addr, // @[RocketCore.scala:134:14] input [6:0] io_dmem_resp_bits_tag, // @[RocketCore.scala:134:14] input [4:0] io_dmem_resp_bits_cmd, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_size, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_signed, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_dprv, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_dv, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data, // @[RocketCore.scala:134:14] input [7:0] io_dmem_resp_bits_mask, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_has_data, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_word_bypass, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_raw, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_store_data, // @[RocketCore.scala:134:14] input io_dmem_replay_next, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_st, // @[RocketCore.scala:134:14] input [39:0] io_dmem_s2_gpa, // @[RocketCore.scala:134:14] input io_dmem_ordered, // @[RocketCore.scala:134:14] input io_dmem_store_pending, // @[RocketCore.scala:134:14] input io_dmem_perf_acquire, // @[RocketCore.scala:134:14] input io_dmem_perf_release, // @[RocketCore.scala:134:14] input io_dmem_perf_grant, // @[RocketCore.scala:134:14] input io_dmem_perf_tlbMiss, // @[RocketCore.scala:134:14] input io_dmem_perf_blocked, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptStoreThenLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptStoreThenRMW, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptLoadThenLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_storeBufferEmptyAfterLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_storeBufferEmptyAfterStore, // @[RocketCore.scala:134:14] output io_dmem_keep_clock_enabled, // @[RocketCore.scala:134:14] output [3:0] io_ptw_ptbr_mode, // @[RocketCore.scala:134:14] output [43:0] io_ptw_ptbr_ppn, // @[RocketCore.scala:134:14] output io_ptw_sfence_valid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_ptw_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_asid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_hv, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_hg, // @[RocketCore.scala:134:14] output io_ptw_status_debug, // @[RocketCore.scala:134:14] output io_ptw_status_cease, // @[RocketCore.scala:134:14] output io_ptw_status_wfi, // @[RocketCore.scala:134:14] output [31:0] io_ptw_status_isa, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_dprv, // @[RocketCore.scala:134:14] output io_ptw_status_dv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_prv, // @[RocketCore.scala:134:14] output io_ptw_status_v, // @[RocketCore.scala:134:14] output io_ptw_status_sd, // @[RocketCore.scala:134:14] output io_ptw_status_mpv, // @[RocketCore.scala:134:14] output io_ptw_status_gva, // @[RocketCore.scala:134:14] output io_ptw_status_tsr, // @[RocketCore.scala:134:14] output io_ptw_status_tw, // @[RocketCore.scala:134:14] output io_ptw_status_tvm, // @[RocketCore.scala:134:14] output io_ptw_status_mxr, // @[RocketCore.scala:134:14] output io_ptw_status_sum, // @[RocketCore.scala:134:14] output io_ptw_status_mprv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_fs, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_mpp, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_vs, // @[RocketCore.scala:134:14] output io_ptw_status_spp, // @[RocketCore.scala:134:14] output io_ptw_status_mpie, // @[RocketCore.scala:134:14] output io_ptw_status_spie, // @[RocketCore.scala:134:14] output io_ptw_status_mie, // @[RocketCore.scala:134:14] output io_ptw_status_sie, // @[RocketCore.scala:134:14] output io_ptw_hstatus_spvp, // @[RocketCore.scala:134:14] output io_ptw_hstatus_spv, // @[RocketCore.scala:134:14] output io_ptw_hstatus_gva, // @[RocketCore.scala:134:14] output io_ptw_gstatus_debug, // @[RocketCore.scala:134:14] output io_ptw_gstatus_cease, // @[RocketCore.scala:134:14] output io_ptw_gstatus_wfi, // @[RocketCore.scala:134:14] output [31:0] io_ptw_gstatus_isa, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_dprv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_dv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_prv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_v, // @[RocketCore.scala:134:14] output [22:0] io_ptw_gstatus_zero2, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mpv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_gva, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mbe, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sbe, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_sxl, // @[RocketCore.scala:134:14] output [7:0] io_ptw_gstatus_zero1, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tsr, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tw, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tvm, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mxr, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sum, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mprv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_fs, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_mpp, // @[RocketCore.scala:134:14] output io_ptw_gstatus_spp, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mpie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_ube, // @[RocketCore.scala:134:14] output io_ptw_gstatus_spie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_upie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_hie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_uie, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_0_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_0_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_0_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_1_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_1_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_1_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_2_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_2_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_2_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_3_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_3_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_3_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_4_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_4_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_4_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_5_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_5_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_5_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_6_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_6_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_6_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_7_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_7_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_7_mask, // @[RocketCore.scala:134:14] input io_ptw_perf_pte_miss, // @[RocketCore.scala:134:14] input io_ptw_perf_pte_hit, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_0_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_0_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_1_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_1_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_1_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_2_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_2_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_2_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_3_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_3_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_3_value, // @[RocketCore.scala:134:14] input io_ptw_clock_enabled, // @[RocketCore.scala:134:14] output io_fpu_hartid, // @[RocketCore.scala:134:14] output [63:0] io_fpu_time, // @[RocketCore.scala:134:14] output [31:0] io_fpu_inst, // @[RocketCore.scala:134:14] output [63:0] io_fpu_fromint_data, // @[RocketCore.scala:134:14] output [2:0] io_fpu_fcsr_rm, // @[RocketCore.scala:134:14] input io_fpu_fcsr_flags_valid, // @[RocketCore.scala:134:14] input [4:0] io_fpu_fcsr_flags_bits, // @[RocketCore.scala:134:14] output [2:0] io_fpu_v_sew, // @[RocketCore.scala:134:14] input [63:0] io_fpu_store_data, // @[RocketCore.scala:134:14] input [63:0] io_fpu_toint_data, // @[RocketCore.scala:134:14] output io_fpu_ll_resp_val, // @[RocketCore.scala:134:14] output [2:0] io_fpu_ll_resp_type, // @[RocketCore.scala:134:14] output [4:0] io_fpu_ll_resp_tag, // @[RocketCore.scala:134:14] output [63:0] io_fpu_ll_resp_data, // @[RocketCore.scala:134:14] output io_fpu_valid, // @[RocketCore.scala:134:14] input io_fpu_fcsr_rdy, // @[RocketCore.scala:134:14] input io_fpu_nack_mem, // @[RocketCore.scala:134:14] input io_fpu_illegal_rm, // @[RocketCore.scala:134:14] output io_fpu_killx, // @[RocketCore.scala:134:14] output io_fpu_killm, // @[RocketCore.scala:134:14] input io_fpu_dec_ldst, // @[RocketCore.scala:134:14] input io_fpu_dec_wen, // @[RocketCore.scala:134:14] input io_fpu_dec_ren1, // @[RocketCore.scala:134:14] input io_fpu_dec_ren2, // @[RocketCore.scala:134:14] input io_fpu_dec_ren3, // @[RocketCore.scala:134:14] input io_fpu_dec_swap12, // @[RocketCore.scala:134:14] input io_fpu_dec_swap23, // @[RocketCore.scala:134:14] input [1:0] io_fpu_dec_typeTagIn, // @[RocketCore.scala:134:14] input [1:0] io_fpu_dec_typeTagOut, // @[RocketCore.scala:134:14] input io_fpu_dec_fromint, // @[RocketCore.scala:134:14] input io_fpu_dec_toint, // @[RocketCore.scala:134:14] input io_fpu_dec_fastpipe, // @[RocketCore.scala:134:14] input io_fpu_dec_fma, // @[RocketCore.scala:134:14] input io_fpu_dec_div, // @[RocketCore.scala:134:14] input io_fpu_dec_sqrt, // @[RocketCore.scala:134:14] input io_fpu_dec_wflags, // @[RocketCore.scala:134:14] input io_fpu_dec_vec, // @[RocketCore.scala:134:14] input io_fpu_sboard_set, // @[RocketCore.scala:134:14] input io_fpu_sboard_clr, // @[RocketCore.scala:134:14] input [4:0] io_fpu_sboard_clra, // @[RocketCore.scala:134:14] output io_fpu_keep_clock_enabled, // @[RocketCore.scala:134:14] output io_trace_insns_0_valid, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_iaddr, // @[RocketCore.scala:134:14] output [31:0] io_trace_insns_0_insn, // @[RocketCore.scala:134:14] output [2:0] io_trace_insns_0_priv, // @[RocketCore.scala:134:14] output io_trace_insns_0_exception, // @[RocketCore.scala:134:14] output io_trace_insns_0_interrupt, // @[RocketCore.scala:134:14] output [63:0] io_trace_insns_0_cause, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_tval, // @[RocketCore.scala:134:14] output [63:0] io_trace_time, // @[RocketCore.scala:134:14] output io_bpwatch_0_valid_0, // @[RocketCore.scala:134:14] output [2:0] io_bpwatch_0_action, // @[RocketCore.scala:134:14] output io_wfi, // @[RocketCore.scala:134:14] output io_vector_status_debug, // @[RocketCore.scala:134:14] output io_vector_status_cease, // @[RocketCore.scala:134:14] output io_vector_status_wfi, // @[RocketCore.scala:134:14] output [31:0] io_vector_status_isa, // @[RocketCore.scala:134:14] output [1:0] io_vector_status_dprv, // @[RocketCore.scala:134:14] output io_vector_status_dv, // @[RocketCore.scala:134:14] output [1:0] io_vector_status_prv, // @[RocketCore.scala:134:14] output io_vector_status_v, // @[RocketCore.scala:134:14] output io_vector_status_sd, // @[RocketCore.scala:134:14] output io_vector_status_mpv, // @[RocketCore.scala:134:14] output io_vector_status_gva, // @[RocketCore.scala:134:14] output io_vector_status_tsr, // @[RocketCore.scala:134:14] output io_vector_status_tw, // @[RocketCore.scala:134:14] output io_vector_status_tvm, // @[RocketCore.scala:134:14] output io_vector_status_mxr, // @[RocketCore.scala:134:14] output io_vector_status_sum, // @[RocketCore.scala:134:14] output io_vector_status_mprv, // @[RocketCore.scala:134:14] output [1:0] io_vector_status_fs, // @[RocketCore.scala:134:14] output [1:0] io_vector_status_mpp, // @[RocketCore.scala:134:14] output [1:0] io_vector_status_vs, // @[RocketCore.scala:134:14] output io_vector_status_spp, // @[RocketCore.scala:134:14] output io_vector_status_mpie, // @[RocketCore.scala:134:14] output io_vector_status_spie, // @[RocketCore.scala:134:14] output io_vector_status_mie, // @[RocketCore.scala:134:14] output io_vector_status_sie, // @[RocketCore.scala:134:14] output io_vector_ex_valid, // @[RocketCore.scala:134:14] output [31:0] io_vector_ex_inst, // @[RocketCore.scala:134:14] output [39:0] io_vector_ex_pc, // @[RocketCore.scala:134:14] output [12:0] io_vector_ex_vconfig_vl, // @[RocketCore.scala:134:14] output io_vector_ex_vconfig_vtype_vill, // @[RocketCore.scala:134:14] output [54:0] io_vector_ex_vconfig_vtype_reserved, // @[RocketCore.scala:134:14] output io_vector_ex_vconfig_vtype_vma, // @[RocketCore.scala:134:14] output io_vector_ex_vconfig_vtype_vta, // @[RocketCore.scala:134:14] output [2:0] io_vector_ex_vconfig_vtype_vsew, // @[RocketCore.scala:134:14] output io_vector_ex_vconfig_vtype_vlmul_sign, // @[RocketCore.scala:134:14] output [1:0] io_vector_ex_vconfig_vtype_vlmul_mag, // @[RocketCore.scala:134:14] output [11:0] io_vector_ex_vstart, // @[RocketCore.scala:134:14] output [63:0] io_vector_ex_rs1, // @[RocketCore.scala:134:14] output [63:0] io_vector_ex_rs2, // @[RocketCore.scala:134:14] output io_vector_killm, // @[RocketCore.scala:134:14] output [63:0] io_vector_mem_frs1, // @[RocketCore.scala:134:14] input io_vector_mem_block_mem, // @[RocketCore.scala:134:14] output io_vector_wb_store_pending, // @[RocketCore.scala:134:14] input io_vector_wb_replay, // @[RocketCore.scala:134:14] input io_vector_wb_retire, // @[RocketCore.scala:134:14] input [31:0] io_vector_wb_inst, // @[RocketCore.scala:134:14] input io_vector_wb_rob_should_wb, // @[RocketCore.scala:134:14] input io_vector_wb_rob_should_wb_fp, // @[RocketCore.scala:134:14] input [39:0] io_vector_wb_pc, // @[RocketCore.scala:134:14] output [1:0] io_vector_wb_vxrm, // @[RocketCore.scala:134:14] output [2:0] io_vector_wb_frm, // @[RocketCore.scala:134:14] output io_vector_resp_ready, // @[RocketCore.scala:134:14] input io_vector_resp_valid, // @[RocketCore.scala:134:14] input io_vector_resp_bits_fp, // @[RocketCore.scala:134:14] input [1:0] io_vector_resp_bits_size, // @[RocketCore.scala:134:14] input [4:0] io_vector_resp_bits_rd, // @[RocketCore.scala:134:14] input [63:0] io_vector_resp_bits_data, // @[RocketCore.scala:134:14] input io_vector_set_vstart_valid, // @[RocketCore.scala:134:14] input io_vector_set_fflags_valid, // @[RocketCore.scala:134:14] input [4:0] io_vector_set_fflags_bits, // @[RocketCore.scala:134:14] input io_vector_backend_busy // @[RocketCore.scala:134:14] ); wire ll_arb_io_out_ready; // @[RocketCore.scala:782:23, :809:44, :810:25] wire ex_new_vtype_vlmul_sign; // @[CSR.scala:328:27] wire [2:0] ex_new_vtype_vsew; // @[CSR.scala:328:27] wire ex_new_vtype_vta; // @[CSR.scala:328:27] wire ex_new_vtype_vma; // @[CSR.scala:328:27] wire ex_new_vtype_vill; // @[CSR.scala:328:27] wire id_ctrl_fence; // @[RocketCore.scala:321:21] wire id_ctrl_rocc; // @[RocketCore.scala:321:21] wire io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_valid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7] wire _ll_arb_io_in_0_ready; // @[RocketCore.scala:776:22] wire _ll_arb_io_in_2_ready; // @[RocketCore.scala:776:22] wire _ll_arb_io_out_valid; // @[RocketCore.scala:776:22] wire [4:0] _ll_arb_io_out_bits_tag; // @[RocketCore.scala:776:22] wire _div_io_req_ready; // @[RocketCore.scala:511:19] wire _div_io_resp_valid; // @[RocketCore.scala:511:19] wire [63:0] _div_io_resp_bits_data; // @[RocketCore.scala:511:19] wire [4:0] _div_io_resp_bits_tag; // @[RocketCore.scala:511:19] wire [63:0] _alu_io_out; // @[RocketCore.scala:504:19] wire [63:0] _alu_io_adder_out; // @[RocketCore.scala:504:19] wire _alu_io_cmp_out; // @[RocketCore.scala:504:19] wire _bpu_io_xcpt_if; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_ld; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_st; // @[RocketCore.scala:414:19] wire _bpu_io_debug_if; // @[RocketCore.scala:414:19] wire _bpu_io_debug_ld; // @[RocketCore.scala:414:19] wire _bpu_io_debug_st; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_rvalid_0; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_wvalid_0; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_ivalid_0; // @[RocketCore.scala:414:19] wire _v_decode_io_legal; // @[Configs.scala:26:35] wire _v_decode_io_fp; // @[Configs.scala:26:35] wire _v_decode_io_read_rs1; // @[Configs.scala:26:35] wire _v_decode_io_read_rs2; // @[Configs.scala:26:35] wire _v_decode_io_read_frs1; // @[Configs.scala:26:35] wire _v_decode_io_write_rd; // @[Configs.scala:26:35] wire _v_decode_io_write_frd; // @[Configs.scala:26:35] wire [63:0] _csr_io_rw_rdata; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_vector_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_csr; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_vector_csr; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_read_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_csr_stall; // @[RocketCore.scala:341:19] wire _csr_io_eret; // @[RocketCore.scala:341:19] wire _csr_io_singleStep; // @[RocketCore.scala:341:19] wire _csr_io_status_debug; // @[RocketCore.scala:341:19] wire _csr_io_status_cease; // @[RocketCore.scala:341:19] wire _csr_io_status_wfi; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_status_isa; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_dprv; // @[RocketCore.scala:341:19] wire _csr_io_status_dv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_prv; // @[RocketCore.scala:341:19] wire _csr_io_status_v; // @[RocketCore.scala:341:19] wire _csr_io_status_sd; // @[RocketCore.scala:341:19] wire _csr_io_status_mpv; // @[RocketCore.scala:341:19] wire _csr_io_status_gva; // @[RocketCore.scala:341:19] wire _csr_io_status_tsr; // @[RocketCore.scala:341:19] wire _csr_io_status_tw; // @[RocketCore.scala:341:19] wire _csr_io_status_tvm; // @[RocketCore.scala:341:19] wire _csr_io_status_mxr; // @[RocketCore.scala:341:19] wire _csr_io_status_sum; // @[RocketCore.scala:341:19] wire _csr_io_status_mprv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_fs; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_mpp; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_vs; // @[RocketCore.scala:341:19] wire _csr_io_status_spp; // @[RocketCore.scala:341:19] wire _csr_io_status_mpie; // @[RocketCore.scala:341:19] wire _csr_io_status_spie; // @[RocketCore.scala:341:19] wire _csr_io_status_mie; // @[RocketCore.scala:341:19] wire _csr_io_status_sie; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_evec; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_time; // @[RocketCore.scala:341:19] wire [2:0] _csr_io_fcsr_rm; // @[RocketCore.scala:341:19] wire _csr_io_interrupt; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_interrupt_cause; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_dmode; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_action; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_bp_0_control_tmatch; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_m; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_s; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_u; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_x; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_w; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_r; // @[RocketCore.scala:341:19] wire [38:0] _csr_io_bp_0_address; // @[RocketCore.scala:341:19] wire [47:0] _csr_io_bp_0_textra_pad2; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_textra_pad1; // @[RocketCore.scala:341:19] wire _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_valid; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_trace_0_iaddr; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_trace_0_insn; // @[RocketCore.scala:341:19] wire [2:0] _csr_io_trace_0_priv; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_exception; // @[RocketCore.scala:341:19] wire [12:0] _csr_io_vector_vconfig_vl; // @[RocketCore.scala:341:19] wire _csr_io_vector_vconfig_vtype_vill; // @[RocketCore.scala:341:19] wire [54:0] _csr_io_vector_vconfig_vtype_reserved; // @[RocketCore.scala:341:19] wire _csr_io_vector_vconfig_vtype_vma; // @[RocketCore.scala:341:19] wire _csr_io_vector_vconfig_vtype_vta; // @[RocketCore.scala:341:19] wire [2:0] _csr_io_vector_vconfig_vtype_vsew; // @[RocketCore.scala:341:19] wire _csr_io_vector_vconfig_vtype_vlmul_sign; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_vector_vconfig_vtype_vlmul_mag; // @[RocketCore.scala:341:19] wire [11:0] _csr_io_vector_vstart; // @[RocketCore.scala:341:19] wire [39:0] _ibuf_io_pc; // @[RocketCore.scala:311:20] wire [1:0] _ibuf_io_btb_resp_cfiType; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_taken; // @[RocketCore.scala:311:20] wire [1:0] _ibuf_io_btb_resp_mask; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_bridx; // @[RocketCore.scala:311:20] wire [38:0] _ibuf_io_btb_resp_target; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_btb_resp_entry; // @[RocketCore.scala:311:20] wire [7:0] _ibuf_io_btb_resp_bht_history; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_bht_value; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20] wire io_hartid_0 = io_hartid; // @[RocketCore.scala:153:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[RocketCore.scala:153:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[RocketCore.scala:153:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[RocketCore.scala:153:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[RocketCore.scala:153:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[RocketCore.scala:153:7] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_btb_cfiType_0 = io_imem_resp_bits_btb_cfiType; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_taken_0 = io_imem_resp_bits_btb_taken; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_btb_mask_0 = io_imem_resp_bits_btb_mask; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_bridx_0 = io_imem_resp_bits_btb_bridx; // @[RocketCore.scala:153:7] wire [38:0] io_imem_resp_bits_btb_target_0 = io_imem_resp_bits_btb_target; // @[RocketCore.scala:153:7] wire [4:0] io_imem_resp_bits_btb_entry_0 = io_imem_resp_bits_btb_entry; // @[RocketCore.scala:153:7] wire [7:0] io_imem_resp_bits_btb_bht_history_0 = io_imem_resp_bits_btb_bht_history; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_bht_value_0 = io_imem_resp_bits_btb_bht_value; // @[RocketCore.scala:153:7] wire [39:0] io_imem_resp_bits_pc_0 = io_imem_resp_bits_pc; // @[RocketCore.scala:153:7] wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_mask_0 = io_imem_resp_bits_mask; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_pf_inst_0 = io_imem_resp_bits_xcpt_pf_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_gf_inst_0 = io_imem_resp_bits_xcpt_gf_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_ae_inst_0 = io_imem_resp_bits_xcpt_ae_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_replay_0 = io_imem_resp_bits_replay; // @[RocketCore.scala:153:7] wire io_imem_gpa_valid_0 = io_imem_gpa_valid; // @[RocketCore.scala:153:7] wire [39:0] io_imem_gpa_bits_0 = io_imem_gpa_bits; // @[RocketCore.scala:153:7] wire io_imem_gpa_is_pte_0 = io_imem_gpa_is_pte; // @[RocketCore.scala:153:7] wire [39:0] io_imem_npc_0 = io_imem_npc; // @[RocketCore.scala:153:7] wire io_imem_perf_acquire_0 = io_imem_perf_acquire; // @[RocketCore.scala:153:7] wire io_imem_perf_tlbMiss_0 = io_imem_perf_tlbMiss; // @[RocketCore.scala:153:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[RocketCore.scala:153:7] wire io_dmem_s2_nack_0 = io_dmem_s2_nack; // @[RocketCore.scala:153:7] wire io_dmem_s2_nack_cause_raw_0 = io_dmem_s2_nack_cause_raw; // @[RocketCore.scala:153:7] wire io_dmem_s2_uncached_0 = io_dmem_s2_uncached; // @[RocketCore.scala:153:7] wire [31:0] io_dmem_s2_paddr_0 = io_dmem_s2_paddr; // @[RocketCore.scala:153:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_resp_bits_addr_0 = io_dmem_resp_bits_addr; // @[RocketCore.scala:153:7] wire [6:0] io_dmem_resp_bits_tag_0 = io_dmem_resp_bits_tag; // @[RocketCore.scala:153:7] wire [4:0] io_dmem_resp_bits_cmd_0 = io_dmem_resp_bits_cmd; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_resp_bits_size_0 = io_dmem_resp_bits_size; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_signed_0 = io_dmem_resp_bits_signed; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_resp_bits_dprv_0 = io_dmem_resp_bits_dprv; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_dv_0 = io_dmem_resp_bits_dv; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_resp_bits_mask_0 = io_dmem_resp_bits_mask; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_replay_0 = io_dmem_resp_bits_replay; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_has_data_0 = io_dmem_resp_bits_has_data; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_word_bypass_0 = io_dmem_resp_bits_data_word_bypass; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_raw_0 = io_dmem_resp_bits_data_raw; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_store_data_0 = io_dmem_resp_bits_store_data; // @[RocketCore.scala:153:7] wire io_dmem_replay_next_0 = io_dmem_replay_next; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ma_ld_0 = io_dmem_s2_xcpt_ma_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ma_st_0 = io_dmem_s2_xcpt_ma_st; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_pf_ld_0 = io_dmem_s2_xcpt_pf_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_pf_st_0 = io_dmem_s2_xcpt_pf_st; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ae_ld_0 = io_dmem_s2_xcpt_ae_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ae_st_0 = io_dmem_s2_xcpt_ae_st; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_s2_gpa_0 = io_dmem_s2_gpa; // @[RocketCore.scala:153:7] wire io_dmem_ordered_0 = io_dmem_ordered; // @[RocketCore.scala:153:7] wire io_dmem_store_pending_0 = io_dmem_store_pending; // @[RocketCore.scala:153:7] wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[RocketCore.scala:153:7] wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[RocketCore.scala:153:7] wire io_dmem_perf_grant_0 = io_dmem_perf_grant; // @[RocketCore.scala:153:7] wire io_dmem_perf_tlbMiss_0 = io_dmem_perf_tlbMiss; // @[RocketCore.scala:153:7] wire io_dmem_perf_blocked_0 = io_dmem_perf_blocked; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptStoreThenLoad_0 = io_dmem_perf_canAcceptStoreThenLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptStoreThenRMW_0 = io_dmem_perf_canAcceptStoreThenRMW; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptLoadThenLoad_0 = io_dmem_perf_canAcceptLoadThenLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_storeBufferEmptyAfterLoad_0 = io_dmem_perf_storeBufferEmptyAfterLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_storeBufferEmptyAfterStore_0 = io_dmem_perf_storeBufferEmptyAfterStore; // @[RocketCore.scala:153:7] wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[RocketCore.scala:153:7] wire io_ptw_perf_pte_hit_0 = io_ptw_perf_pte_hit; // @[RocketCore.scala:153:7] wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[RocketCore.scala:153:7] wire io_fpu_fcsr_flags_valid_0 = io_fpu_fcsr_flags_valid; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_fcsr_flags_bits_0 = io_fpu_fcsr_flags_bits; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_store_data_0 = io_fpu_store_data; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_toint_data_0 = io_fpu_toint_data; // @[RocketCore.scala:153:7] wire io_fpu_fcsr_rdy_0 = io_fpu_fcsr_rdy; // @[RocketCore.scala:153:7] wire io_fpu_nack_mem_0 = io_fpu_nack_mem; // @[RocketCore.scala:153:7] wire io_fpu_illegal_rm_0 = io_fpu_illegal_rm; // @[RocketCore.scala:153:7] wire io_fpu_dec_ldst_0 = io_fpu_dec_ldst; // @[RocketCore.scala:153:7] wire io_fpu_dec_wen_0 = io_fpu_dec_wen; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren1_0 = io_fpu_dec_ren1; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren2_0 = io_fpu_dec_ren2; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren3_0 = io_fpu_dec_ren3; // @[RocketCore.scala:153:7] wire io_fpu_dec_swap12_0 = io_fpu_dec_swap12; // @[RocketCore.scala:153:7] wire io_fpu_dec_swap23_0 = io_fpu_dec_swap23; // @[RocketCore.scala:153:7] wire [1:0] io_fpu_dec_typeTagIn_0 = io_fpu_dec_typeTagIn; // @[RocketCore.scala:153:7] wire [1:0] io_fpu_dec_typeTagOut_0 = io_fpu_dec_typeTagOut; // @[RocketCore.scala:153:7] wire io_fpu_dec_fromint_0 = io_fpu_dec_fromint; // @[RocketCore.scala:153:7] wire io_fpu_dec_toint_0 = io_fpu_dec_toint; // @[RocketCore.scala:153:7] wire io_fpu_dec_fastpipe_0 = io_fpu_dec_fastpipe; // @[RocketCore.scala:153:7] wire io_fpu_dec_fma_0 = io_fpu_dec_fma; // @[RocketCore.scala:153:7] wire io_fpu_dec_div_0 = io_fpu_dec_div; // @[RocketCore.scala:153:7] wire io_fpu_dec_sqrt_0 = io_fpu_dec_sqrt; // @[RocketCore.scala:153:7] wire io_fpu_dec_wflags_0 = io_fpu_dec_wflags; // @[RocketCore.scala:153:7] wire io_fpu_dec_vec_0 = io_fpu_dec_vec; // @[RocketCore.scala:153:7] wire io_fpu_sboard_set_0 = io_fpu_sboard_set; // @[RocketCore.scala:153:7] wire io_fpu_sboard_clr_0 = io_fpu_sboard_clr; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_sboard_clra_0 = io_fpu_sboard_clra; // @[RocketCore.scala:153:7] wire io_vector_mem_block_mem_0 = io_vector_mem_block_mem; // @[RocketCore.scala:153:7] wire io_vector_wb_replay_0 = io_vector_wb_replay; // @[RocketCore.scala:153:7] wire io_vector_wb_retire_0 = io_vector_wb_retire; // @[RocketCore.scala:153:7] wire [31:0] io_vector_wb_inst_0 = io_vector_wb_inst; // @[RocketCore.scala:153:7] wire io_vector_wb_rob_should_wb_0 = io_vector_wb_rob_should_wb; // @[RocketCore.scala:153:7] wire io_vector_wb_rob_should_wb_fp_0 = io_vector_wb_rob_should_wb_fp; // @[RocketCore.scala:153:7] wire [39:0] io_vector_wb_pc_0 = io_vector_wb_pc; // @[RocketCore.scala:153:7] wire io_vector_resp_valid_0 = io_vector_resp_valid; // @[RocketCore.scala:153:7] wire io_vector_resp_bits_fp_0 = io_vector_resp_bits_fp; // @[RocketCore.scala:153:7] wire [1:0] io_vector_resp_bits_size_0 = io_vector_resp_bits_size; // @[RocketCore.scala:153:7] wire [4:0] io_vector_resp_bits_rd_0 = io_vector_resp_bits_rd; // @[RocketCore.scala:153:7] wire [63:0] io_vector_resp_bits_data_0 = io_vector_resp_bits_data; // @[RocketCore.scala:153:7] wire io_vector_set_vstart_valid_0 = io_vector_set_vstart_valid; // @[RocketCore.scala:153:7] wire io_vector_set_fflags_valid_0 = io_vector_set_fflags_valid; // @[RocketCore.scala:153:7] wire [4:0] io_vector_set_fflags_bits_0 = io_vector_set_fflags_bits; // @[RocketCore.scala:153:7] wire io_vector_backend_busy_0 = io_vector_backend_busy; // @[RocketCore.scala:153:7] wire coreMonitorBundle_clock = clock; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_reset = reset; // @[RocketCore.scala:1186:31] wire xrfWriteBundle_clock = clock; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_reset = reset; // @[RocketCore.scala:1249:28] wire io_imem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7] wire io_dmem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sd = 1'h1; // @[RocketCore.scala:153:7] wire io_vector_ex_ready = 1'h1; // @[RocketCore.scala:153:7] wire clock_en = 1'h1; // @[RocketCore.scala:153:7, :163:29] wire _id_npc_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _id_npc_b11_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1345:23] wire _mem_br_target_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _mem_br_target_b19_12_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1343:43] wire _mem_br_target_b19_12_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1343:36] wire _mem_br_target_b11_T_6 = 1'h1; // @[RocketCore.scala:153:7, :1346:23] wire _mem_br_target_b4_1_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1349:41] wire _mem_br_target_b4_1_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1349:34] wire _mem_br_target_b19_12_T_5 = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _mem_br_target_b11_T_14 = 1'h1; // @[RocketCore.scala:153:7, :1345:23] wire _wb_reg_xcpt_T_2 = 1'h1; // @[RocketCore.scala:153:7, :707:45] wire _replay_wb_rocc_T_1 = 1'h1; // @[RocketCore.scala:153:7, :758:56] wire _rocc_blocked_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1029:31] wire io_imem_btb_update_bits_taken = 1'h0; // @[RocketCore.scala:153:7] wire io_imem_ras_update_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtw = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_hu = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_perf_l2miss = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_perf_l2hit = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_resp_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_resp_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_signed = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_dv = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_resp = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s1_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_nack = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_nack_cause_raw = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_uncached = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_signed = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_dv = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_replay = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_has_data = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_replay_next = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ma_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_pf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ae_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_ordered = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_store_pending = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_acquire = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_release = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_grant = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_tlbMiss = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_blocked = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_keep_clock_enabled = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_clock_enabled = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_busy = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_interrupt = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_exception = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_rvalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_wvalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_ivalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_cease = 1'h0; // @[RocketCore.scala:153:7] wire io_traceStall = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_mem_block_all = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_wb_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_set_vxsat = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_set_vconfig_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_set_vconfig_bits_vtype_vill = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_set_vconfig_bits_vtype_vma = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_set_vconfig_bits_vtype_vta = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_set_vconfig_bits_vtype_vlmul_sign = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_trap_check_busy = 1'h0; // @[RocketCore.scala:153:7] wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_5 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_6 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_7 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_8 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_9 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_10 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_11 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_12 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_13 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_14 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_15 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_16 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_17 = 1'h0; // @[Events.scala:13:33] wire hits_0 = 1'h0; // @[Events.scala:13:25] wire hits_1 = 1'h0; // @[Events.scala:13:25] wire hits_2 = 1'h0; // @[Events.scala:13:25] wire hits_3 = 1'h0; // @[Events.scala:13:25] wire hits_4 = 1'h0; // @[Events.scala:13:25] wire hits_5 = 1'h0; // @[Events.scala:13:25] wire hits_6 = 1'h0; // @[Events.scala:13:25] wire hits_7 = 1'h0; // @[Events.scala:13:25] wire hits_8 = 1'h0; // @[Events.scala:13:25] wire hits_9 = 1'h0; // @[Events.scala:13:25] wire hits_10 = 1'h0; // @[Events.scala:13:25] wire hits_11 = 1'h0; // @[Events.scala:13:25] wire hits_12 = 1'h0; // @[Events.scala:13:25] wire hits_13 = 1'h0; // @[Events.scala:13:25] wire hits_14 = 1'h0; // @[Events.scala:13:25] wire hits_15 = 1'h0; // @[Events.scala:13:25] wire hits_16 = 1'h0; // @[Events.scala:13:25] wire hits_17 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_1_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_5 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_6 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_7 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_8 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_9 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_10 = 1'h0; // @[Events.scala:13:33] wire hits_1_0 = 1'h0; // @[Events.scala:13:25] wire hits_1_1 = 1'h0; // @[Events.scala:13:25] wire hits_1_2 = 1'h0; // @[Events.scala:13:25] wire hits_1_3 = 1'h0; // @[Events.scala:13:25] wire hits_1_4 = 1'h0; // @[Events.scala:13:25] wire hits_1_5 = 1'h0; // @[Events.scala:13:25] wire hits_1_6 = 1'h0; // @[Events.scala:13:25] wire hits_1_7 = 1'h0; // @[Events.scala:13:25] wire hits_1_8 = 1'h0; // @[Events.scala:13:25] wire hits_1_9 = 1'h0; // @[Events.scala:13:25] wire hits_1_10 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_2_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_5 = 1'h0; // @[Events.scala:13:33] wire hits_2_0 = 1'h0; // @[Events.scala:13:25] wire hits_2_1 = 1'h0; // @[Events.scala:13:25] wire hits_2_2 = 1'h0; // @[Events.scala:13:25] wire hits_2_3 = 1'h0; // @[Events.scala:13:25] wire hits_2_4 = 1'h0; // @[Events.scala:13:25] wire hits_2_5 = 1'h0; // @[Events.scala:13:25] wire _id_rs_T_1 = 1'h0; // @[RocketCore.scala:1326:33] wire _id_rs_T_6 = 1'h0; // @[RocketCore.scala:1326:33] wire _id_npc_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _id_npc_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _id_npc_b19_12_T_1 = 1'h0; // @[RocketCore.scala:1343:43] wire _id_npc_b19_12_T_2 = 1'h0; // @[RocketCore.scala:1343:36] wire _id_npc_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _id_npc_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _id_npc_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _id_npc_b11_T_6 = 1'h0; // @[RocketCore.scala:1346:23] wire _id_npc_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _id_npc_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _id_npc_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _id_npc_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _id_npc_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _id_npc_b4_1_T_2 = 1'h0; // @[RocketCore.scala:1349:41] wire _id_npc_b4_1_T_3 = 1'h0; // @[RocketCore.scala:1349:34] wire _id_npc_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _id_npc_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _id_npc_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _id_npc_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _id_npc_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _id_npc_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire id_npc_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _id_illegal_insn_T_26 = 1'h0; // @[RocketCore.scala:388:23] wire _id_illegal_insn_T_28 = 1'h0; // @[RocketCore.scala:389:23] wire _id_illegal_insn_T_30 = 1'h0; // @[RocketCore.scala:390:22] wire id_rocc_busy = 1'h0; // @[RocketCore.scala:405:34] wire _id_csr_rocc_write_T = 1'h0; // @[RocketCore.scala:408:87] wire id_csr_rocc_write = 1'h0; // @[RocketCore.scala:408:100] wire _id_do_fence_T_1 = 1'h0; // @[RocketCore.scala:410:46] wire _ex_reg_hls_T = 1'h0; // @[RocketCore.scala:553:37] wire _ex_reg_hls_T_6 = 1'h0; // @[RocketCore.scala:553:55] wire _ex_reg_mem_size_T = 1'h0; // @[RocketCore.scala:554:46] wire _replay_ex_structural_T_5 = 1'h0; // @[RocketCore.scala:599:45] wire _replay_ex_structural_T_6 = 1'h0; // @[RocketCore.scala:599:42] wire _mem_br_target_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_br_target_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_br_target_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_br_target_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_br_target_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_br_target_b11_T_3 = 1'h0; // @[RocketCore.scala:1345:23] wire _mem_br_target_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_br_target_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_br_target_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_br_target_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_br_target_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_br_target_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_br_target_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_br_target_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_br_target_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_br_target_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_br_target_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_br_target_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _mem_br_target_sign_T_3 = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_br_target_b30_20_T_3 = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_br_target_b19_12_T_6 = 1'h0; // @[RocketCore.scala:1343:43] wire _mem_br_target_b19_12_T_7 = 1'h0; // @[RocketCore.scala:1343:36] wire _mem_br_target_b11_T_11 = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_br_target_b11_T_12 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_br_target_b11_T_13 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_br_target_b11_T_17 = 1'h0; // @[RocketCore.scala:1346:23] wire _mem_br_target_b10_5_T_4 = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_br_target_b10_5_T_5 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_br_target_b10_5_T_6 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_br_target_b4_1_T_10 = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_br_target_b4_1_T_11 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_br_target_b4_1_T_12 = 1'h0; // @[RocketCore.scala:1349:41] wire _mem_br_target_b4_1_T_13 = 1'h0; // @[RocketCore.scala:1349:34] wire _mem_br_target_b4_1_T_15 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_br_target_b0_T_8 = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_br_target_b0_T_10 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_br_target_b0_T_12 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_br_target_b0_T_14 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_br_target_b0_T_15 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_br_target_b0_1 = 1'h0; // @[RocketCore.scala:1351:17] wire vec_kill_all = 1'h0; // @[RocketCore.scala:698:36] wire replay_wb_csr = 1'h0; // @[RocketCore.scala:759:42] wire _htval_valid_dmem_T_2 = 1'h0; // @[RocketCore.scala:857:83] wire _htval_valid_dmem_T_3 = 1'h0; // @[RocketCore.scala:857:54] wire htval_valid_dmem = 1'h0; // @[RocketCore.scala:857:87] wire _mhtinst_read_pseudo_T_1 = 1'h0; // @[RocketCore.scala:862:98] wire _ctrl_stalld_T_28 = 1'h0; // @[RocketCore.scala:1041:5] wire _io_rocc_exception_T = 1'h0; // @[RocketCore.scala:1157:52] wire _io_rocc_exception_T_1 = 1'h0; // @[RocketCore.scala:1157:32] wire _io_cease_T = 1'h0; // @[RocketCore.scala:1166:38] wire _io_cease_T_1 = 1'h0; // @[RocketCore.scala:1166:35] wire coreMonitorBundle_wrenf = 1'h0; // @[RocketCore.scala:1186:31] wire xrfWriteBundle_excpt = 1'h0; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_valid = 1'h0; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_wrenf = 1'h0; // @[RocketCore.scala:1249:28] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[RocketCore.scala:153:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[RocketCore.scala:153:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[RocketCore.scala:153:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [22:0] io_vector_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_vector_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_ras_update_bits_cfiType = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_req_bits_size = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_resp_bits_size = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_set_vconfig_bits_vtype_vlmul_mag = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] _htval_valid_dmem_T_1 = 2'h0; // @[RocketCore.scala:857:76] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[RocketCore.scala:153:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[RocketCore.scala:153:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[RocketCore.scala:153:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_resp_bits_rd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_vector_wb_cause = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] xrfWriteBundle_rd0src = 5'h0; // @[RocketCore.scala:1249:28] wire [4:0] xrfWriteBundle_rd1src = 5'h0; // @[RocketCore.scala:1249:28] wire [1:0] io_ptw_gstatus_vs = 2'h3; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_req_bits_addr = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_s2_gpa = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_vector_wb_tval = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] htval_dmem = 40'h0; // @[RocketCore.scala:858:25] wire [31:0] io_reset_vector = 32'h0; // @[RocketCore.scala:153:7] wire [31:0] io_rocc_mem_s2_paddr = 32'h0; // @[RocketCore.scala:153:7] wire [31:0] xrfWriteBundle_inst = 32'h0; // @[RocketCore.scala:1249:28] wire [38:0] io_imem_ras_update_bits_returnAddr = 39'h0; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_s1_data_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] xrfWriteBundle_pc = 64'h0; // @[RocketCore.scala:1249:28] wire [63:0] xrfWriteBundle_rd0val = 64'h0; // @[RocketCore.scala:1249:28] wire [63:0] xrfWriteBundle_rd1val = 64'h0; // @[RocketCore.scala:1249:28] wire [1:0] io_ptw_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_mem_req_bits_tag = 7'h0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0; // @[RocketCore.scala:153:7] wire [11:0] io_vector_set_vstart_bits = 12'h0; // @[RocketCore.scala:153:7] wire [12:0] io_vector_set_vconfig_bits_vl = 13'h0; // @[RocketCore.scala:153:7] wire [12:0] _ex_avl_T_8 = 13'h0; // @[package.scala:174:46] wire [12:0] _ex_new_vl_T_6 = 13'h0; // @[package.scala:174:46] wire [54:0] io_vector_set_vconfig_bits_vtype_reserved = 55'h0; // @[RocketCore.scala:153:7] wire [54:0] ex_new_vtype_reserved = 55'h0; // @[CSR.scala:328:27] wire [54:0] ex_new_vconfig_vtype_reserved = 55'h0; // @[RocketCore.scala:498:30] wire [2:0] io_vector_set_vconfig_bits_vtype_vsew = 3'h0; // @[RocketCore.scala:153:7] wire [12:0] _ex_avl_T_10 = 13'h1FF8; // @[package.scala:174:37] wire [12:0] _ex_new_vl_T_8 = 13'h1FF8; // @[package.scala:174:37] wire [12:0] _ex_avl_T_9 = 13'h7; // @[package.scala:174:41] wire [12:0] _ex_new_vl_T_7 = 13'h7; // @[package.scala:174:41] wire [13:0] _ex_new_vl_atLeastVLMax_T_10 = 14'h3FF8; // @[package.scala:174:37] wire [13:0] _ex_new_vl_atLeastVLMax_T_9 = 14'h7; // @[package.scala:174:41] wire [13:0] _ex_new_vl_atLeastVLMax_T_1 = 14'h3000; // @[CSR.scala:371:56] wire [13:0] _ex_new_vl_atLeastVLMax_T_2 = 14'h3000; // @[CSR.scala:371:56] wire [13:0] _ex_new_vl_atLeastVLMax_T_8 = 14'h0; // @[package.scala:174:46] wire [14:0] _ex_new_vl_atLeastVLMax_T = 15'h7000; // @[CSR.scala:371:56] wire io_fpu_hartid_0 = io_hartid_0; // @[RocketCore.scala:153:7] wire take_pc_mem_wb; // @[RocketCore.scala:307:35] wire [39:0] _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:1051:8] wire _io_imem_req_bits_speculative_T; // @[RocketCore.scala:1049:35] wire _io_imem_sfence_valid_T; // @[RocketCore.scala:1060:40] wire io_ptw_sfence_valid_0 = io_imem_sfence_valid_0; // @[RocketCore.scala:153:7] wire _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:1061:45] wire io_ptw_sfence_bits_rs1_0 = io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7] wire _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:1062:45] wire io_ptw_sfence_bits_rs2_0 = io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7] wire [38:0] io_ptw_sfence_bits_addr_0 = io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_asid_0 = io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_hv_0 = io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_hg_0 = io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7] wire _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:1071:77] wire [38:0] _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:1080:33] wire [38:0] io_imem_bht_update_bits_pc_0 = io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7] wire mem_cfi; // @[RocketCore.scala:625:50] wire [1:0] _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:1074:8] wire _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:1084:45] wire mem_wrong_npc; // @[RocketCore.scala:621:8] wire _io_imem_flush_icache_T_2; // @[RocketCore.scala:1054:59] wire _io_dmem_req_valid_T; // @[RocketCore.scala:1130:41] wire [39:0] _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:1295:8] wire _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:1136:30] wire [1:0] _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:1140:31] wire _io_dmem_req_bits_dv_T; // @[RocketCore.scala:1141:37] wire _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:1142:56] wire _io_dmem_s1_kill_T_2; // @[RocketCore.scala:1151:68] wire [63:0] _rf_wdata_T_1 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7, :819:78] wire [63:0] dcache_bypass_data = io_dmem_resp_bits_data_word_bypass_0; // @[RocketCore.scala:153:7, :449:62] wire io_vector_wb_store_pending_0 = io_dmem_store_pending_0; // @[RocketCore.scala:153:7] wire _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:1154:70] wire [63:0] ex_rs_0; // @[RocketCore.scala:469:14] wire [63:0] io_vector_mem_frs1_0 = io_fpu_store_data_0; // @[RocketCore.scala:153:7] wire _io_fpu_valid_T_1; // @[RocketCore.scala:1094:31] wire ctrl_killx; // @[RocketCore.scala:602:48] wire killm_common; // @[RocketCore.scala:700:68] wire _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59] wire _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:1156:53] wire [6:0] _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:1159:48] wire [6:0] _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:1159:48] wire _io_vector_ex_valid_T_4; // @[RocketCore.scala:1117:113] wire [11:0] _io_vector_ex_vstart_T_3; // @[RocketCore.scala:1120:23] wire [63:0] ex_rs_1; // @[RocketCore.scala:469:14] wire _io_vector_resp_ready_T_2; // @[RocketCore.scala:801:24] wire id_vec_busy = io_vector_backend_busy_0; // @[RocketCore.scala:153:7, :409:55] wire [39:0] io_imem_req_bits_pc_0; // @[RocketCore.scala:153:7] wire io_imem_req_bits_speculative_0; // @[RocketCore.scala:153:7] wire io_imem_req_valid_0; // @[RocketCore.scala:153:7] wire io_imem_resp_ready_0; // @[RocketCore.scala:153:7] wire [7:0] io_imem_btb_update_bits_prediction_bht_history_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_bht_value_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_prediction_cfiType_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_taken_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_prediction_mask_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_bridx_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_prediction_target_0; // @[RocketCore.scala:153:7] wire [4:0] io_imem_btb_update_bits_prediction_entry_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_target_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_isValid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_cfiType_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_valid_0; // @[RocketCore.scala:153:7] wire [7:0] io_imem_bht_update_bits_prediction_history_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_prediction_value_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_branch_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_taken_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_mispredict_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_valid_0; // @[RocketCore.scala:153:7] wire io_imem_might_request_0; // @[RocketCore.scala:153:7] wire io_imem_flush_icache_0; // @[RocketCore.scala:153:7] wire io_imem_progress_0; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_req_bits_addr_0; // @[RocketCore.scala:153:7] wire [6:0] io_dmem_req_bits_tag_0; // @[RocketCore.scala:153:7] wire [4:0] io_dmem_req_bits_cmd_0; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_req_bits_size_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_signed_0; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_req_bits_dprv_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_dv_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_resp_0; // @[RocketCore.scala:153:7] wire io_dmem_req_valid_0; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_s1_data_data_0; // @[RocketCore.scala:153:7] wire io_dmem_s1_kill_0; // @[RocketCore.scala:153:7] wire io_dmem_keep_clock_enabled_0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_ptbr_mode_0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_ptbr_ppn_0; // @[RocketCore.scala:153:7] wire io_ptw_status_debug_0; // @[RocketCore.scala:153:7] wire io_ptw_status_cease_0; // @[RocketCore.scala:153:7] wire io_ptw_status_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_status_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_dprv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_prv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_v_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sd_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mpv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tsr_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tw_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tvm_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mxr_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sum_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_mpp_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_vs_0; // @[RocketCore.scala:153:7] wire io_ptw_status_spp_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mpie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_spie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sie_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_spvp_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_spv_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_debug_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_cease_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_gstatus_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_dprv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_prv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_v_0; // @[RocketCore.scala:153:7] wire [22:0] io_ptw_gstatus_zero2_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mpv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mbe_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sbe_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_sxl_0; // @[RocketCore.scala:153:7] wire [7:0] io_ptw_gstatus_zero1_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tsr_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tw_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tvm_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mxr_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sum_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_mpp_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_spp_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mpie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_ube_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_spie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_upie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_hie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_uie_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_0_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_0_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_0_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_1_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_1_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_1_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_2_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_2_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_2_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_3_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_3_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_3_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_4_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_4_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_4_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_5_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_5_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_5_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_6_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_6_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_6_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_7_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_7_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_7_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_time_0; // @[RocketCore.scala:153:7] wire [31:0] io_fpu_inst_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_fromint_data_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_fcsr_rm_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_v_sew_0; // @[RocketCore.scala:153:7] wire io_fpu_ll_resp_val_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_ll_resp_type_0; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_ll_resp_data_0; // @[RocketCore.scala:153:7] wire io_fpu_valid_0; // @[RocketCore.scala:153:7] wire io_fpu_killx_0; // @[RocketCore.scala:153:7] wire io_fpu_killm_0; // @[RocketCore.scala:153:7] wire io_fpu_keep_clock_enabled_0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_cmd_bits_inst_funct; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rs2; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rs1; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xd; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xs1; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xs2; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rd; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_cmd_bits_inst_opcode; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_debug; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_cease; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_wfi; // @[RocketCore.scala:153:7] wire [31:0] io_rocc_cmd_bits_status_isa; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_dprv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_dv; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_prv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_v; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sd; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mpv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_gva; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tsr; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tw; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tvm; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mxr; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sum; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mprv; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_fs; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_mpp; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_vs; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_spp; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mpie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_spie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sie; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_cmd_bits_rs1; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_cmd_bits_rs2; // @[RocketCore.scala:153:7] wire io_rocc_cmd_valid; // @[RocketCore.scala:153:7] wire io_trace_insns_0_valid_0; // @[RocketCore.scala:153:7] wire [39:0] io_trace_insns_0_iaddr_0; // @[RocketCore.scala:153:7] wire [31:0] io_trace_insns_0_insn_0; // @[RocketCore.scala:153:7] wire [2:0] io_trace_insns_0_priv_0; // @[RocketCore.scala:153:7] wire io_trace_insns_0_exception_0; // @[RocketCore.scala:153:7] wire io_trace_insns_0_interrupt_0; // @[RocketCore.scala:153:7] wire [63:0] io_trace_insns_0_cause_0; // @[RocketCore.scala:153:7] wire [39:0] io_trace_insns_0_tval_0; // @[RocketCore.scala:153:7] wire [63:0] io_trace_time_0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_valid_0_0; // @[RocketCore.scala:153:7] wire [2:0] io_bpwatch_0_action_0; // @[RocketCore.scala:153:7] wire io_vector_status_debug_0; // @[RocketCore.scala:153:7] wire io_vector_status_cease_0; // @[RocketCore.scala:153:7] wire io_vector_status_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_vector_status_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_dprv_0; // @[RocketCore.scala:153:7] wire io_vector_status_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_prv_0; // @[RocketCore.scala:153:7] wire io_vector_status_v_0; // @[RocketCore.scala:153:7] wire io_vector_status_sd_0; // @[RocketCore.scala:153:7] wire io_vector_status_mpv_0; // @[RocketCore.scala:153:7] wire io_vector_status_gva_0; // @[RocketCore.scala:153:7] wire io_vector_status_tsr_0; // @[RocketCore.scala:153:7] wire io_vector_status_tw_0; // @[RocketCore.scala:153:7] wire io_vector_status_tvm_0; // @[RocketCore.scala:153:7] wire io_vector_status_mxr_0; // @[RocketCore.scala:153:7] wire io_vector_status_sum_0; // @[RocketCore.scala:153:7] wire io_vector_status_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_mpp_0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_vs_0; // @[RocketCore.scala:153:7] wire io_vector_status_spp_0; // @[RocketCore.scala:153:7] wire io_vector_status_mpie_0; // @[RocketCore.scala:153:7] wire io_vector_status_spie_0; // @[RocketCore.scala:153:7] wire io_vector_status_mie_0; // @[RocketCore.scala:153:7] wire io_vector_status_sie_0; // @[RocketCore.scala:153:7] wire io_vector_ex_vconfig_vtype_vill_0; // @[RocketCore.scala:153:7] wire [54:0] io_vector_ex_vconfig_vtype_reserved_0; // @[RocketCore.scala:153:7] wire io_vector_ex_vconfig_vtype_vma_0; // @[RocketCore.scala:153:7] wire io_vector_ex_vconfig_vtype_vta_0; // @[RocketCore.scala:153:7] wire [2:0] io_vector_ex_vconfig_vtype_vsew_0; // @[RocketCore.scala:153:7] wire io_vector_ex_vconfig_vtype_vlmul_sign_0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_ex_vconfig_vtype_vlmul_mag_0; // @[RocketCore.scala:153:7] wire [12:0] io_vector_ex_vconfig_vl_0; // @[RocketCore.scala:153:7] wire io_vector_ex_valid_0; // @[RocketCore.scala:153:7] wire [31:0] io_vector_ex_inst_0; // @[RocketCore.scala:153:7] wire [39:0] io_vector_ex_pc_0; // @[RocketCore.scala:153:7] wire [11:0] io_vector_ex_vstart_0; // @[RocketCore.scala:153:7] wire [63:0] io_vector_ex_rs1_0; // @[RocketCore.scala:153:7] wire [63:0] io_vector_ex_rs2_0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_wb_vxrm_0; // @[RocketCore.scala:153:7] wire [2:0] io_vector_wb_frm_0; // @[RocketCore.scala:153:7] wire io_vector_resp_ready_0; // @[RocketCore.scala:153:7] wire io_vector_killm_0; // @[RocketCore.scala:153:7] wire io_wfi_0; // @[RocketCore.scala:153:7] reg id_reg_pause; // @[RocketCore.scala:161:25] reg imem_might_request_reg; // @[RocketCore.scala:162:35] assign io_imem_might_request_0 = imem_might_request_reg; // @[RocketCore.scala:153:7, :162:35] reg ex_ctrl_legal; // @[RocketCore.scala:243:20] reg ex_ctrl_fp; // @[RocketCore.scala:243:20] reg ex_ctrl_rocc; // @[RocketCore.scala:243:20] reg ex_ctrl_branch; // @[RocketCore.scala:243:20] reg ex_ctrl_jal; // @[RocketCore.scala:243:20] reg ex_ctrl_jalr; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_alu2; // @[RocketCore.scala:243:20] reg [1:0] ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_imm; // @[RocketCore.scala:243:20] reg ex_ctrl_alu_dw; // @[RocketCore.scala:243:20] reg [4:0] ex_ctrl_alu_fn; // @[RocketCore.scala:243:20] reg ex_ctrl_mem; // @[RocketCore.scala:243:20] wire _ex_sfence_T = ex_ctrl_mem; // @[RocketCore.scala:243:20, :605:29] reg [4:0] ex_ctrl_mem_cmd; // @[RocketCore.scala:243:20] assign io_dmem_req_bits_cmd_0 = ex_ctrl_mem_cmd; // @[RocketCore.scala:153:7, :243:20] reg ex_ctrl_rfs1; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs3; // @[RocketCore.scala:243:20] reg ex_ctrl_wfd; // @[RocketCore.scala:243:20] reg ex_ctrl_mul; // @[RocketCore.scala:243:20] reg ex_ctrl_div; // @[RocketCore.scala:243:20] reg ex_ctrl_wxd; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_csr; // @[RocketCore.scala:243:20] reg ex_ctrl_fence_i; // @[RocketCore.scala:243:20] reg ex_ctrl_fence; // @[RocketCore.scala:243:20] reg ex_ctrl_amo; // @[RocketCore.scala:243:20] reg ex_ctrl_dp; // @[RocketCore.scala:243:20] reg ex_ctrl_vec; // @[RocketCore.scala:243:20] reg mem_ctrl_legal; // @[RocketCore.scala:244:21] reg mem_ctrl_fp; // @[RocketCore.scala:244:21] reg mem_ctrl_rocc; // @[RocketCore.scala:244:21] reg mem_ctrl_branch; // @[RocketCore.scala:244:21] assign io_imem_bht_update_bits_branch_0 = mem_ctrl_branch; // @[RocketCore.scala:153:7, :244:21] reg mem_ctrl_jal; // @[RocketCore.scala:244:21] reg mem_ctrl_jalr; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs1; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_sel_alu2; // @[RocketCore.scala:244:21] reg [1:0] mem_ctrl_sel_alu1; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_sel_imm; // @[RocketCore.scala:244:21] reg mem_ctrl_alu_dw; // @[RocketCore.scala:244:21] reg [4:0] mem_ctrl_alu_fn; // @[RocketCore.scala:244:21] reg mem_ctrl_mem; // @[RocketCore.scala:244:21] reg [4:0] mem_ctrl_mem_cmd; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs1; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs3; // @[RocketCore.scala:244:21] reg mem_ctrl_wfd; // @[RocketCore.scala:244:21] reg mem_ctrl_mul; // @[RocketCore.scala:244:21] reg mem_ctrl_div; // @[RocketCore.scala:244:21] reg mem_ctrl_wxd; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_csr; // @[RocketCore.scala:244:21] reg mem_ctrl_fence_i; // @[RocketCore.scala:244:21] reg mem_ctrl_fence; // @[RocketCore.scala:244:21] reg mem_ctrl_amo; // @[RocketCore.scala:244:21] reg mem_ctrl_dp; // @[RocketCore.scala:244:21] reg mem_ctrl_vec; // @[RocketCore.scala:244:21] reg wb_ctrl_legal; // @[RocketCore.scala:245:20] reg wb_ctrl_fp; // @[RocketCore.scala:245:20] reg wb_ctrl_rocc; // @[RocketCore.scala:245:20] reg wb_ctrl_branch; // @[RocketCore.scala:245:20] reg wb_ctrl_jal; // @[RocketCore.scala:245:20] reg wb_ctrl_jalr; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs1; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_sel_alu2; // @[RocketCore.scala:245:20] reg [1:0] wb_ctrl_sel_alu1; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_sel_imm; // @[RocketCore.scala:245:20] reg wb_ctrl_alu_dw; // @[RocketCore.scala:245:20] reg [4:0] wb_ctrl_alu_fn; // @[RocketCore.scala:245:20] reg wb_ctrl_mem; // @[RocketCore.scala:245:20] reg [4:0] wb_ctrl_mem_cmd; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs1; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs3; // @[RocketCore.scala:245:20] reg wb_ctrl_wfd; // @[RocketCore.scala:245:20] reg wb_ctrl_mul; // @[RocketCore.scala:245:20] reg wb_ctrl_div; // @[RocketCore.scala:245:20] reg wb_ctrl_wxd; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_csr; // @[RocketCore.scala:245:20] reg wb_ctrl_fence_i; // @[RocketCore.scala:245:20] reg wb_ctrl_fence; // @[RocketCore.scala:245:20] reg wb_ctrl_amo; // @[RocketCore.scala:245:20] reg wb_ctrl_dp; // @[RocketCore.scala:245:20] reg wb_ctrl_vec; // @[RocketCore.scala:245:20] reg ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35] reg ex_reg_valid; // @[RocketCore.scala:248:35] reg ex_reg_rvc; // @[RocketCore.scala:249:35] reg [1:0] ex_reg_btb_resp_cfiType; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_taken; // @[RocketCore.scala:250:35] reg [1:0] ex_reg_btb_resp_mask; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_bridx; // @[RocketCore.scala:250:35] reg [38:0] ex_reg_btb_resp_target; // @[RocketCore.scala:250:35] reg [4:0] ex_reg_btb_resp_entry; // @[RocketCore.scala:250:35] reg [7:0] ex_reg_btb_resp_bht_history; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_bht_value; // @[RocketCore.scala:250:35] reg ex_reg_xcpt; // @[RocketCore.scala:251:35] reg ex_reg_flush_pipe; // @[RocketCore.scala:252:35] reg ex_reg_load_use; // @[RocketCore.scala:253:35] reg [63:0] ex_reg_cause; // @[RocketCore.scala:254:35] wire [63:0] ex_cause = ex_reg_cause; // @[RocketCore.scala:254:35, :1278:50] reg ex_reg_replay; // @[RocketCore.scala:255:26] reg [39:0] ex_reg_pc; // @[RocketCore.scala:256:22] assign io_vector_ex_pc_0 = ex_reg_pc; // @[RocketCore.scala:153:7, :256:22] wire [39:0] _ex_op1_T_1 = ex_reg_pc; // @[RocketCore.scala:256:22, :474:24] reg [1:0] ex_reg_mem_size; // @[RocketCore.scala:257:28] assign io_dmem_req_bits_size_0 = ex_reg_mem_size; // @[RocketCore.scala:153:7, :257:28] reg [31:0] ex_reg_inst; // @[RocketCore.scala:259:24] assign io_vector_ex_inst_0 = ex_reg_inst; // @[RocketCore.scala:153:7, :259:24] reg [31:0] ex_reg_raw_inst; // @[RocketCore.scala:260:28] reg ex_reg_wphit_0; // @[RocketCore.scala:261:36] reg ex_reg_set_vconfig; // @[RocketCore.scala:262:36] wire _io_vector_ex_valid_T = ex_reg_set_vconfig; // @[RocketCore.scala:262:36, :1117:90] reg mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36] reg mem_reg_valid; // @[RocketCore.scala:265:36] reg mem_reg_rvc; // @[RocketCore.scala:266:36] reg [1:0] mem_reg_btb_resp_cfiType; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_cfiType_0 = mem_reg_btb_resp_cfiType; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_taken_0 = mem_reg_btb_resp_taken; // @[RocketCore.scala:153:7, :267:36] wire _mem_direction_misprediction_T = mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36, :627:85] reg [1:0] mem_reg_btb_resp_mask; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_mask_0 = mem_reg_btb_resp_mask; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_bridx; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bridx_0 = mem_reg_btb_resp_bridx; // @[RocketCore.scala:153:7, :267:36] reg [38:0] mem_reg_btb_resp_target; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_target_0 = mem_reg_btb_resp_target; // @[RocketCore.scala:153:7, :267:36] reg [4:0] mem_reg_btb_resp_entry; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_entry_0 = mem_reg_btb_resp_entry; // @[RocketCore.scala:153:7, :267:36] reg [7:0] mem_reg_btb_resp_bht_history; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bht_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36] assign io_imem_bht_update_bits_prediction_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_bht_value; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bht_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36] assign io_imem_bht_update_bits_prediction_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_xcpt; // @[RocketCore.scala:268:36] reg mem_reg_replay; // @[RocketCore.scala:269:36] reg mem_reg_flush_pipe; // @[RocketCore.scala:270:36] reg [63:0] mem_reg_cause; // @[RocketCore.scala:271:36] reg mem_reg_slow_bypass; // @[RocketCore.scala:272:36] wire mem_mem_cmd_bh = mem_reg_slow_bypass; // @[RocketCore.scala:272:36, :995:41] reg mem_reg_load; // @[RocketCore.scala:273:36] reg mem_reg_store; // @[RocketCore.scala:274:36] reg mem_reg_set_vconfig; // @[RocketCore.scala:275:36] reg mem_reg_sfence; // @[RocketCore.scala:276:27] reg [39:0] mem_reg_pc; // @[RocketCore.scala:277:23] wire [39:0] _mem_br_target_T = mem_reg_pc; // @[RocketCore.scala:277:23, :615:34] reg [31:0] mem_reg_inst; // @[RocketCore.scala:278:25] reg [1:0] mem_reg_mem_size; // @[RocketCore.scala:279:29] reg mem_reg_hls_or_dv; // @[RocketCore.scala:280:30] reg [31:0] mem_reg_raw_inst; // @[RocketCore.scala:281:29] reg [63:0] mem_reg_wdata; // @[RocketCore.scala:282:26] wire [63:0] _mem_int_wdata_T_3 = mem_reg_wdata; // @[RocketCore.scala:282:26, :624:111] reg [76:0] mem_reg_rs2; // @[RocketCore.scala:283:24] reg mem_br_taken; // @[RocketCore.scala:284:25] assign io_imem_bht_update_bits_taken_0 = mem_br_taken; // @[RocketCore.scala:153:7, :284:25] wire _take_pc_mem_T_3; // @[RocketCore.scala:629:49] wire take_pc_mem; // @[RocketCore.scala:285:25] reg mem_reg_wphit_0; // @[RocketCore.scala:286:35] reg wb_reg_valid; // @[RocketCore.scala:288:35] reg wb_reg_xcpt; // @[RocketCore.scala:289:35] reg wb_reg_replay; // @[RocketCore.scala:290:35] reg wb_reg_flush_pipe; // @[RocketCore.scala:291:35] reg [63:0] wb_reg_cause; // @[RocketCore.scala:292:35] reg wb_reg_set_vconfig; // @[RocketCore.scala:293:35] reg wb_reg_sfence; // @[RocketCore.scala:294:26] reg [39:0] wb_reg_pc; // @[RocketCore.scala:295:22] reg [1:0] wb_reg_mem_size; // @[RocketCore.scala:296:28] reg wb_reg_hls_or_dv; // @[RocketCore.scala:297:29] reg wb_reg_hfence_v; // @[RocketCore.scala:298:28] assign io_imem_sfence_bits_hv_0 = wb_reg_hfence_v; // @[RocketCore.scala:153:7, :298:28] reg wb_reg_hfence_g; // @[RocketCore.scala:299:28] assign io_imem_sfence_bits_hg_0 = wb_reg_hfence_g; // @[RocketCore.scala:153:7, :299:28] reg [31:0] wb_reg_inst; // @[RocketCore.scala:300:24] wire [31:0] _io_rocc_cmd_bits_inst_WIRE_1 = wb_reg_inst; // @[RocketCore.scala:300:24, :1159:48] reg [31:0] wb_reg_raw_inst; // @[RocketCore.scala:301:28] reg [63:0] wb_reg_wdata; // @[RocketCore.scala:302:25] assign io_rocc_cmd_bits_rs1 = wb_reg_wdata; // @[RocketCore.scala:153:7, :302:25] wire [63:0] _rf_wdata_T_3 = wb_reg_wdata; // @[RocketCore.scala:302:25, :822:21] reg [76:0] wb_reg_rs2; // @[RocketCore.scala:303:23] wire [76:0] _csr_io_vector_set_vconfig_bits_WIRE_1 = wb_reg_rs2; // @[RocketCore.scala:303:23, :868:46] wire _take_pc_wb_T_2; // @[RocketCore.scala:762:53] wire take_pc_wb; // @[RocketCore.scala:304:24] reg wb_reg_wphit_0; // @[RocketCore.scala:305:35] assign io_bpwatch_0_valid_0_0 = wb_reg_wphit_0; // @[RocketCore.scala:153:7, :305:35] assign take_pc_mem_wb = take_pc_wb \| take_pc_mem; // @[RocketCore.scala:285:25, :304:24, :307:35] assign io_imem_req_valid_0 = take_pc_mem_wb; // @[RocketCore.scala:153:7, :307:35] wire _id_illegal_insn_T_32 = id_ctrl_rocc; // @[RocketCore.scala:321:21, :391:18] wire [2:0] id_ctrl_decoder_8; // @[Decode.scala:50:77] wire [1:0] id_ctrl_decoder_9; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_10; // @[Decode.scala:50:77] wire id_ctrl_decoder_11; // @[Decode.scala:50:77] wire [4:0] id_ctrl_decoder_12; // @[Decode.scala:50:77] wire [4:0] id_ctrl_decoder_14; // @[Decode.scala:50:77] wire _id_do_fence_T = id_ctrl_fence; // @[RocketCore.scala:321:21, :410:64] wire id_ctrl_legal; // @[RocketCore.scala:321:21] wire id_ctrl_fp; // @[RocketCore.scala:321:21] wire id_ctrl_branch; // @[RocketCore.scala:321:21] wire id_ctrl_jal; // @[RocketCore.scala:321:21] wire id_ctrl_jalr; // @[RocketCore.scala:321:21] wire id_ctrl_rxs2; // @[RocketCore.scala:321:21] wire id_ctrl_rxs1; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_sel_alu2; // @[RocketCore.scala:321:21] wire [1:0] id_ctrl_sel_alu1; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_sel_imm; // @[RocketCore.scala:321:21] wire id_ctrl_alu_dw; // @[RocketCore.scala:321:21] wire [4:0] id_ctrl_alu_fn; // @[RocketCore.scala:321:21] wire id_ctrl_mem; // @[RocketCore.scala:321:21] wire [4:0] id_ctrl_mem_cmd; // @[RocketCore.scala:321:21] wire id_ctrl_rfs1; // @[RocketCore.scala:321:21] wire id_ctrl_rfs2; // @[RocketCore.scala:321:21] wire id_ctrl_rfs3; // @[RocketCore.scala:321:21] wire id_ctrl_wfd; // @[RocketCore.scala:321:21] wire id_ctrl_mul; // @[RocketCore.scala:321:21] wire id_ctrl_div; // @[RocketCore.scala:321:21] wire id_ctrl_wxd; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_csr; // @[RocketCore.scala:321:21] wire id_ctrl_fence_i; // @[RocketCore.scala:321:21] wire id_ctrl_amo; // @[RocketCore.scala:321:21] wire id_ctrl_dp; // @[RocketCore.scala:321:21] wire id_ctrl_vec; // @[RocketCore.scala:321:21] wire [31:0] id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22] wire [31:0] id_ctrl_decoder_decoded_invInputs = ~id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [41:0] id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [41:0] id_ctrl_decoder_decoded; // @[pla.scala:81:23] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_194 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_195 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_196 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_194 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_195 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_196 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_194 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_195 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_196 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_194 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_195 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_196 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_193 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_194 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_195 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_184 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_185 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T = {id_ctrl_decoder_decoded_andMatrixOutputs_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_100_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_103_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_183 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_165 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_166 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_9_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_164 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_145 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_146 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_29_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_140_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_118_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_4 = id_ctrl_decoder_decoded_andMatrixOutputs_118_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_194 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_195 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_196 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_97_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_35_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_185_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_129_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_67_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_47 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_78_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_193_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_7_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_99_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_32_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_71_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_190 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_191 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_192 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [4:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_184_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_16 = id_ctrl_decoder_decoded_andMatrixOutputs_184_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_146_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_144_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_20_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_22_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_98_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_39_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_132_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_194_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_63 = id_ctrl_decoder_decoded_andMatrixOutputs_194_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_165_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_64 = id_ctrl_decoder_decoded_andMatrixOutputs_165_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_141 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_138 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_139 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_134 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_132 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_119 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_55_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_91_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_30_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_26_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_178_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_77_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_21_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_5 = id_ctrl_decoder_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_122_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_61_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_106_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_24_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_166_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_161_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_96_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_56_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_16_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_188_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_6 = id_ctrl_decoder_decoded_andMatrixOutputs_188_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_141_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_53_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_196_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_93_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_17_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_130_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_180_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_124_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_14_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_27 = id_ctrl_decoder_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_133_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_49_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_156_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_7 = id_ctrl_decoder_decoded_andMatrixOutputs_156_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_187_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_149_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_116_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_163_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_44_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_127_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_151_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_162_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_134_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_182_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_5_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_89_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_95_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_66_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_126_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_92_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_113_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_171_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_147_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_170_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_2_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_15_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_169_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_179_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_173_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_76_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_88_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_145_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_36_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_41_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_8_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_105_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_73_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_192_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_28_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_0_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_144 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_142 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_143 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_60_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_48_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_168_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_164_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_138_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_74_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_59_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_153_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_47_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_104_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_84_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_28 = id_ctrl_decoder_decoded_andMatrixOutputs_84_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_31_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_13_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_112_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_65_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_125_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_50_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_6_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_135_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_154_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_110_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_190_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_45_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_79_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_160_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_34_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_87_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_10_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_94_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_183_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_43_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_136_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_3_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_191_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_4_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_25_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_58_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_148_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_27_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_52_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_139_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_181_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_176_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_121_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_19_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_64_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_143_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_11_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_46_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_142_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_115_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_70_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_72_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_177_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_81_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_131_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_158_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_68_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_42_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_54_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_63_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_69_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_186_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_51_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_137_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_128_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_152_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_1_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_101_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_107_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_189_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_18_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_109_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_90_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_62_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_150_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_172_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_169}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_37_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_169; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = id_ctrl_decoder_decoded_plaInput[23]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_170}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_123_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_170; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_171}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_83_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_171; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168}; // @[pla.scala:98:53] wire [31:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_172}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_120_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_172; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_173}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_174_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_173; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_174}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_82_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_174; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_175}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_57_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_175; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_176}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_80_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_176; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_177}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_167_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_177; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_178}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_155_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_178; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_179}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_195_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_179; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_180}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_38_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_180; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_181}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_159_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_181; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_182}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_111_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_182; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_183}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_23_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_183; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_184}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_102_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_184; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_185}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_175_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_185; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_186}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_119_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_186; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_187}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_117_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_187; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_188}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_157_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_188; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_189}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_114_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_189; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_190}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_108_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_190; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_191}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_85_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_191; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_192}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_33_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_192; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_lo_193}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_86_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_193; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_194 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_183}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_141}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_164}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_194, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_194}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_193}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_194, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_194}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_194}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_194 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_194 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_194, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_190}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_194 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_194, id_ctrl_decoder_decoded_andMatrixOutputs_lo_194}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_40_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_194; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_194 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_195 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_194, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_184}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_142}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_165}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_195, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_195}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_194}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_195, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_195}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_195}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_195 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_195 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_195, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_191}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_195 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_195, id_ctrl_decoder_decoded_andMatrixOutputs_lo_195}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_12_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_195; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_78}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_134}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_132}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_195 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_132}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_196 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_195, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_185}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_143}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_166}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_196, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_196}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_195}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_196, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_196}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_196}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_196 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_134}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_196 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_196, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_192}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_196 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_196, id_ctrl_decoder_decoded_andMatrixOutputs_lo_196}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_75_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_196; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_119_2, id_ctrl_decoder_decoded_andMatrixOutputs_86_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_115_2, id_ctrl_decoder_decoded_andMatrixOutputs_177_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_128_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_87_2, id_ctrl_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_94_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_149_2, id_ctrl_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [11:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T = {id_ctrl_decoder_decoded_orMatrixOutputs_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_1 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _GEN = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_1 = _GEN; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6 = _GEN; // @[pla.scala:114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_3 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_47_2, id_ctrl_decoder_decoded_andMatrixOutputs_84_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_156_2, id_ctrl_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_55_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_9 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_175_2, id_ctrl_decoder_decoded_andMatrixOutputs_85_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_102_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_57_2, id_ctrl_decoder_decoded_andMatrixOutputs_80_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_0 = {id_ctrl_decoder_decoded_andMatrixOutputs_90_2, id_ctrl_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = _GEN_0; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_152_2, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_176_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_136_2, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = _GEN_1; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = _GEN_1; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_160_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = _GEN_2; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_183_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [23:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = _GEN_3; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = _GEN_3; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4 = _GEN_3; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_156_2, id_ctrl_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = _GEN_4; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = _GEN_4; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_169_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_165_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = _GEN_5; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = _GEN_5; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = _GEN_5; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = _GEN_5; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_194_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_193_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_6; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3 = _GEN_6; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_140_2, id_ctrl_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = _GEN_7; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [12:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [24:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [48:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_11 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_179_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_13 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_117_2, id_ctrl_decoder_decoded_andMatrixOutputs_157_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_72_2, id_ctrl_decoder_decoded_andMatrixOutputs_81_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_45_2, id_ctrl_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_154_2, id_ctrl_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3 = _GEN_10; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_77_2, id_ctrl_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_184_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = _GEN_11; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_15 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_110_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = _GEN_12; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_154_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_124_2, id_ctrl_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_22_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [12:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_18 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_85_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_13; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = _GEN_13; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_102_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_70_2, id_ctrl_decoder_decoded_andMatrixOutputs_177_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_110_2, id_ctrl_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_154_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_125_2, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_20 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_65_2, id_ctrl_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_129_2, id_ctrl_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_22 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_138_2, id_ctrl_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_24 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_23; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_26 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_25; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_74_2, id_ctrl_decoder_decoded_andMatrixOutputs_112_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_103_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [8:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_30 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_143_2, id_ctrl_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_150_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_168_2, id_ctrl_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_95_2, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_56_2, id_ctrl_decoder_decoded_andMatrixOutputs_182_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = _GEN_14; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = _GEN_14; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = _GEN_14; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19] wire [14:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_32 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_64_2, id_ctrl_decoder_decoded_andMatrixOutputs_143_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_139_2, id_ctrl_decoder_decoded_andMatrixOutputs_176_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = _GEN_15; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = _GEN_15; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_43_2, id_ctrl_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_73_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_170_2, id_ctrl_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_113_2, id_ctrl_decoder_decoded_andMatrixOutputs_171_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_39_2, id_ctrl_decoder_decoded_andMatrixOutputs_116_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19] wire [17:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_34 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_183_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_24; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_24 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_5_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_151_2, id_ctrl_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19] wire [10:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_36 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_54_2, id_ctrl_decoder_decoded_andMatrixOutputs_186_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_148_2, id_ctrl_decoder_decoded_andMatrixOutputs_181_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_48_2, id_ctrl_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19] wire [9:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_38 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_37; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_172_2, id_ctrl_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_107_2, id_ctrl_decoder_decoded_andMatrixOutputs_189_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_11_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19] wire [13:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_40 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_62_2, id_ctrl_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_152_2, id_ctrl_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = _GEN_17; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = _GEN_17; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = _GEN_17; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_34_2, id_ctrl_decoder_decoded_andMatrixOutputs_183_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_192_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_162_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = _GEN_18; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = _GEN_18; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_165_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_78_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19] wire [35:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_42 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_66_2, id_ctrl_decoder_decoded_andMatrixOutputs_147_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_44 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}] wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_46 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_101_2, id_ctrl_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] _GEN_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = _GEN_19; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN_19; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = _GEN_20; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_183_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_92_2, id_ctrl_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_24_2, id_ctrl_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_194_2, id_ctrl_decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19] wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_48 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_123_2, id_ctrl_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_157_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = _GEN_21; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] _GEN_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_176_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = _GEN_22; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = _GEN_22; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = _GEN_22; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_31_2, id_ctrl_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = _GEN_23; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = _GEN_23; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] _GEN_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = _GEN_24; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = _GEN_24; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = _GEN_24; // @[pla.scala:114:19] wire [1:0] _GEN_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_127_2, id_ctrl_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = _GEN_25; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_187_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_106_2, id_ctrl_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] _GEN_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = _GEN_26; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = _GEN_26; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_193_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = _GEN_27; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = _GEN_27; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19] wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_50 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_49; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_185_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_192_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_52 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_183_2, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19] wire [1:0] _GEN_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_141_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = _GEN_28; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = _GEN_28; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = _GEN_28; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_194_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_29_2, id_ctrl_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:114:19] wire [12:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19] wire [24:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_54 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_143_2, id_ctrl_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_147_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_127_2, id_ctrl_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_193_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19] wire [34:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_56 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_68_2, id_ctrl_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_24, id_ctrl_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_58 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_82_2, id_ctrl_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_157_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_101_2, id_ctrl_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:114:19] wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_162_2, id_ctrl_decoder_decoded_andMatrixOutputs_169_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_187_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_16_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:114:19] wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19] wire [45:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_25, id_ctrl_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_60 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_59; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_90_2, id_ctrl_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_34_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_138_2, id_ctrl_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_162_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] _GEN_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = _GEN_29; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = _GEN_29; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_129_2, id_ctrl_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_193_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19] wire [22:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_26, id_ctrl_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_62 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_61; // @[pla.scala:114:{19,36}] wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_66 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_65; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_159_2, id_ctrl_decoder_decoded_andMatrixOutputs_111_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_195_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_131_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = _GEN_30; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2 = _GEN_30; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_177_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_50_2, id_ctrl_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_178_2, id_ctrl_decoder_decoded_andMatrixOutputs_196_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19] wire [20:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_27, id_ctrl_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_68 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_67; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_114_2, id_ctrl_decoder_decoded_andMatrixOutputs_108_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_111_2, id_ctrl_decoder_decoded_andMatrixOutputs_175_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_120_2, id_ctrl_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_189_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_107_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_177_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_112_2, id_ctrl_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:114:19] wire [35:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_153_2, id_ctrl_decoder_decoded_andMatrixOutputs_104_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_169_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_91_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_132_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_146_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_118_2, id_ctrl_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:114:19] wire [35:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19] wire [71:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_28, id_ctrl_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_70 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_69; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_3, _id_ctrl_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_9, _id_ctrl_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5 = {1'h0, _id_ctrl_decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5, _id_ctrl_decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_16, _id_ctrl_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_22, _id_ctrl_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_27, _id_ctrl_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_32, _id_ctrl_decoder_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:102:36] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:102:36] wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_36, _id_ctrl_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_42, _id_ctrl_decoder_decoded_orMatrixOutputs_T_40}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_38}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_46, _id_ctrl_decoder_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_52, _id_ctrl_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_56, _id_ctrl_decoder_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_62, _id_ctrl_decoder_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_66, _id_ctrl_decoder_decoded_orMatrixOutputs_T_64}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_70, _id_ctrl_decoder_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6, 1'h0}; // @[pla.scala:102:36] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:102:36] wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:102:36] wire [41:0] id_ctrl_decoder_decoded_orMatrixOutputs = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_29, id_ctrl_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:102:36] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T = id_ctrl_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_1 = id_ctrl_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_2 = id_ctrl_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_3 = id_ctrl_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_4 = id_ctrl_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_5 = id_ctrl_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_6 = id_ctrl_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_7 = id_ctrl_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_8 = id_ctrl_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_9 = id_ctrl_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_10 = id_ctrl_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_11 = id_ctrl_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_12 = id_ctrl_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_13 = id_ctrl_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_14 = id_ctrl_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_15 = id_ctrl_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_16 = id_ctrl_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_17 = id_ctrl_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_18 = id_ctrl_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_19 = id_ctrl_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_20 = id_ctrl_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_21 = id_ctrl_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_22 = id_ctrl_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_23 = id_ctrl_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_24 = id_ctrl_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_25 = id_ctrl_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_26 = id_ctrl_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_27 = id_ctrl_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_28 = id_ctrl_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_29 = id_ctrl_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_30 = id_ctrl_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_31 = id_ctrl_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_32 = id_ctrl_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_33 = id_ctrl_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_34 = id_ctrl_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_35 = id_ctrl_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_36 = id_ctrl_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_37 = id_ctrl_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_38 = id_ctrl_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_39 = id_ctrl_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_40 = id_ctrl_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_41 = id_ctrl_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_1, _id_ctrl_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_4, _id_ctrl_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_6, _id_ctrl_decoder_decoded_invMatrixOutputs_T_5}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_9, _id_ctrl_decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_11, _id_ctrl_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_14, _id_ctrl_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_17, _id_ctrl_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_20, _id_ctrl_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_22, _id_ctrl_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_25, _id_ctrl_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_27, _id_ctrl_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_30, _id_ctrl_decoder_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_32, _id_ctrl_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_35, _id_ctrl_decoder_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_38, _id_ctrl_decoder_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_41, _id_ctrl_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign id_ctrl_decoder_decoded_invMatrixOutputs = {id_ctrl_decoder_decoded_invMatrixOutputs_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign id_ctrl_decoder_decoded = id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire id_ctrl_decoder_0 = id_ctrl_decoder_decoded[41]; // @[pla.scala:81:23] wire id_ctrl_decoder_1 = id_ctrl_decoder_decoded[40]; // @[pla.scala:81:23] wire id_ctrl_decoder_2 = id_ctrl_decoder_decoded[39]; // @[pla.scala:81:23] wire id_ctrl_decoder_3 = id_ctrl_decoder_decoded[38]; // @[pla.scala:81:23] wire id_ctrl_decoder_4 = id_ctrl_decoder_decoded[37]; // @[pla.scala:81:23] wire id_ctrl_decoder_5 = id_ctrl_decoder_decoded[36]; // @[pla.scala:81:23] wire id_ctrl_decoder_6 = id_ctrl_decoder_decoded[35]; // @[pla.scala:81:23] wire id_ctrl_decoder_7 = id_ctrl_decoder_decoded[34]; // @[pla.scala:81:23] assign id_ctrl_decoder_8 = id_ctrl_decoder_decoded[33:31]; // @[pla.scala:81:23] assign id_ctrl_sel_alu2 = id_ctrl_decoder_8; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_9 = id_ctrl_decoder_decoded[30:29]; // @[pla.scala:81:23] assign id_ctrl_sel_alu1 = id_ctrl_decoder_9; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_10 = id_ctrl_decoder_decoded[28:26]; // @[pla.scala:81:23] assign id_ctrl_sel_imm = id_ctrl_decoder_10; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_11 = id_ctrl_decoder_decoded[25]; // @[pla.scala:81:23] assign id_ctrl_alu_dw = id_ctrl_decoder_11; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_12 = id_ctrl_decoder_decoded[24:20]; // @[pla.scala:81:23] assign id_ctrl_alu_fn = id_ctrl_decoder_12; // @[RocketCore.scala:321:21] wire id_ctrl_decoder_13 = id_ctrl_decoder_decoded[19]; // @[pla.scala:81:23] assign id_ctrl_decoder_14 = id_ctrl_decoder_decoded[18:14]; // @[pla.scala:81:23] assign id_ctrl_mem_cmd = id_ctrl_decoder_14; // @[RocketCore.scala:321:21] wire id_ctrl_decoder_15 = id_ctrl_decoder_decoded[13]; // @[pla.scala:81:23] wire id_ctrl_decoder_16 = id_ctrl_decoder_decoded[12]; // @[pla.scala:81:23] wire id_ctrl_decoder_17 = id_ctrl_decoder_decoded[11]; // @[pla.scala:81:23] wire id_ctrl_decoder_18 = id_ctrl_decoder_decoded[10]; // @[pla.scala:81:23] wire id_ctrl_decoder_19 = id_ctrl_decoder_decoded[9]; // @[pla.scala:81:23] wire id_ctrl_decoder_20 = id_ctrl_decoder_decoded[8]; // @[pla.scala:81:23] wire id_ctrl_decoder_21 = id_ctrl_decoder_decoded[7]; // @[pla.scala:81:23] wire [2:0] id_ctrl_decoder_22 = id_ctrl_decoder_decoded[6:4]; // @[pla.scala:81:23] wire id_ctrl_decoder_23 = id_ctrl_decoder_decoded[3]; // @[pla.scala:81:23] wire id_ctrl_decoder_24 = id_ctrl_decoder_decoded[2]; // @[pla.scala:81:23] wire id_ctrl_decoder_25 = id_ctrl_decoder_decoded[1]; // @[pla.scala:81:23] wire id_ctrl_decoder_26 = id_ctrl_decoder_decoded[0]; // @[pla.scala:81:23] wire [4:0] id_raddr3; // @[RocketCore.scala:326:72] wire [4:0] id_raddr2; // @[RocketCore.scala:326:72] wire [4:0] _id_rs_T_7 = id_raddr2; // @[RocketCore.scala:326:72, :1320:44] wire [4:0] id_raddr1; // @[RocketCore.scala:326:72] wire [4:0] _id_rs_T_2 = id_raddr1; // @[RocketCore.scala:326:72, :1320:44] wire [4:0] id_waddr; // @[RocketCore.scala:326:72] wire _id_load_use_T_1; // @[RocketCore.scala:1001:51] wire id_load_use; // @[RocketCore.scala:332:25] reg id_reg_fence; // @[RocketCore.scala:333:29] wire [63:0] id_rs_0; // @[RocketCore.scala:1325:26] wire _id_rs_T = ~(\|id_raddr1); // @[RocketCore.scala:326:72, :1326:41] wire [4:0] _id_rs_T_3 = ~_id_rs_T_2; // @[RocketCore.scala:1320:{39,44}] wire [63:0] id_rs_1; // @[RocketCore.scala:1325:26] wire _id_rs_T_5 = ~(\|id_raddr2); // @[RocketCore.scala:326:72, :1326:41] wire [4:0] _id_rs_T_8 = ~_id_rs_T_7; // @[RocketCore.scala:1320:{39,44}] wire _ctrl_killd_T_4; // @[RocketCore.scala:1046:104] wire ctrl_killd; // @[RocketCore.scala:338:24] wire _id_npc_sign_T_1 = _ibuf_io_inst_0_bits_inst_bits[31]; // @[RocketCore.scala:311:20, :1341:44] wire _id_npc_sign_T_2 = _id_npc_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire id_npc_sign = _id_npc_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire _id_npc_b11_T_9 = id_npc_sign; // @[RocketCore.scala:1341:19, :1346:18] wire id_npc_hi_hi_hi = id_npc_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _id_npc_b30_20_T_1 = _ibuf_io_inst_0_bits_inst_bits[30:20]; // @[RocketCore.scala:311:20, :1342:41] wire [10:0] _id_npc_b30_20_T_2 = _id_npc_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] id_npc_b30_20 = {11{id_npc_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] id_npc_hi_hi_lo = id_npc_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _id_npc_b19_12_T_3 = _ibuf_io_inst_0_bits_inst_bits[19:12]; // @[RocketCore.scala:311:20, :1343:65] wire [7:0] _id_npc_b19_12_T_4 = _id_npc_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] id_npc_b19_12 = _id_npc_b19_12_T_4; // @[RocketCore.scala:1343:{21,73}] wire [7:0] id_npc_hi_lo_hi = id_npc_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _id_npc_b11_T_4 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39] wire _id_npc_b0_T_3 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39, :1352:37] wire _id_npc_b11_T_5 = _id_npc_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _id_npc_b11_T_10 = _id_npc_b11_T_5; // @[RocketCore.scala:1345:{18,44}] wire _id_npc_b11_T_7 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39] wire _id_npc_b0_T_1 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39, :1351:37] wire _id_npc_b11_T_8 = _id_npc_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire id_npc_b11 = _id_npc_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire id_npc_hi_lo_lo = id_npc_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _id_npc_b10_5_T_3 = _ibuf_io_inst_0_bits_inst_bits[30:25]; // @[RocketCore.scala:311:20, :1347:62] wire [5:0] id_npc_b10_5 = _id_npc_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _id_npc_b4_1_T_4 = _ibuf_io_inst_0_bits_inst_bits[11:8]; // @[RocketCore.scala:311:20, :1349:57] wire [3:0] _id_npc_b4_1_T_6 = _ibuf_io_inst_0_bits_inst_bits[19:16]; // @[RocketCore.scala:311:20, :1350:39] wire [3:0] _id_npc_b4_1_T_7 = _ibuf_io_inst_0_bits_inst_bits[24:21]; // @[RocketCore.scala:311:20, :1350:52] wire [3:0] _id_npc_b4_1_T_8 = _id_npc_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _id_npc_b4_1_T_9 = _id_npc_b4_1_T_8; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] id_npc_b4_1 = _id_npc_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _id_npc_b0_T_5 = _ibuf_io_inst_0_bits_inst_bits[15]; // @[RocketCore.scala:311:20, :1353:37] wire [9:0] id_npc_lo_hi = {id_npc_b10_5, id_npc_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] id_npc_lo = {id_npc_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] id_npc_hi_lo = {id_npc_hi_lo_hi, id_npc_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] id_npc_hi_hi = {id_npc_hi_hi_hi, id_npc_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] id_npc_hi = {id_npc_hi_hi, id_npc_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _id_npc_T_1 = {id_npc_hi, id_npc_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _id_npc_T_2 = _id_npc_T_1; // @[RocketCore.scala:1355:{8,53}] wire [39:0] _id_npc_T; // @[RocketCore.scala:339:28] wire [40:0] _id_npc_T_3 = {_id_npc_T[39], _id_npc_T} + {{9{_id_npc_T_2[31]}}, _id_npc_T_2}; // @[RocketCore.scala:339:{28,35}, :1355:53] wire [39:0] _id_npc_T_4 = _id_npc_T_3[39:0]; // @[RocketCore.scala:339:35] wire [39:0] _id_npc_T_5 = _id_npc_T_4; // @[RocketCore.scala:339:35] wire [39:0] id_npc = _id_npc_T_5; // @[RocketCore.scala:339:{35,65}] wire _GEN_31 = id_ctrl_csr == 3'h6; // @[package.scala:16:47] wire _id_csr_en_T; // @[package.scala:16:47] assign _id_csr_en_T = _GEN_31; // @[package.scala:16:47] wire _id_csr_ren_T; // @[package.scala:16:47] assign _id_csr_ren_T = _GEN_31; // @[package.scala:16:47] wire _id_csr_en_T_1 = &id_ctrl_csr; // @[package.scala:16:47] wire _id_csr_en_T_2 = id_ctrl_csr == 3'h5; // @[package.scala:16:47] wire _id_csr_en_T_3 = _id_csr_en_T \| _id_csr_en_T_1; // @[package.scala:16:47, :81:59] wire id_csr_en = _id_csr_en_T_3 \| _id_csr_en_T_2; // @[package.scala:16:47, :81:59] wire id_system_insn = id_ctrl_csr == 3'h4; // @[RocketCore.scala:321:21, :343:36] wire _id_csr_ren_T_1 = &id_ctrl_csr; // @[package.scala:16:47] wire _id_csr_ren_T_2 = _id_csr_ren_T \| _id_csr_ren_T_1; // @[package.scala:16:47, :81:59] wire _id_csr_ren_T_3 = _ibuf_io_inst_0_bits_inst_rs1 == 5'h0; // @[RocketCore.scala:311:20, :344:81] wire id_csr_ren = _id_csr_ren_T_2 & _id_csr_ren_T_3; // @[package.scala:81:59] wire _id_csr_T = id_system_insn & id_ctrl_mem; // @[RocketCore.scala:321:21, :343:36, :345:35] wire [2:0] _id_csr_T_1 = id_csr_ren ? 3'h2 : id_ctrl_csr; // @[RocketCore.scala:321:21, :344:54, :345:61] wire [2:0] id_csr = _id_csr_T ? 3'h0 : _id_csr_T_1; // @[RocketCore.scala:345:{19,35,61}] wire _id_csr_flush_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54] wire _id_csr_flush_T_1 = id_csr_en & _id_csr_flush_T; // @[package.scala:81:59] wire _id_csr_flush_T_2 = _id_csr_flush_T_1 & _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19, :346:{51,66}] wire id_csr_flush = id_system_insn \| _id_csr_flush_T_2; // @[RocketCore.scala:343:36, :346:{37,66}] wire [31:0] _id_set_vconfig_T = _ibuf_io_inst_0_bits_inst_bits & 32'h8000707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_1 = _id_set_vconfig_T == 32'h7057; // @[RocketCore.scala:347:100] wire [31:0] _id_set_vconfig_T_2 = _ibuf_io_inst_0_bits_inst_bits & 32'hC000707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_3 = _id_set_vconfig_T_2 == 32'hC0007057; // @[RocketCore.scala:347:100] wire [31:0] _id_set_vconfig_T_4 = _ibuf_io_inst_0_bits_inst_bits & 32'hFE00707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_5 = _id_set_vconfig_T_4 == 32'h80007057; // @[RocketCore.scala:347:100] wire _id_set_vconfig_T_6 = _id_set_vconfig_T_1 \| _id_set_vconfig_T_3; // @[package.scala:81:59] wire _id_set_vconfig_T_7 = _id_set_vconfig_T_6 \| _id_set_vconfig_T_5; // @[package.scala:81:59] wire id_set_vconfig = _id_set_vconfig_T_7; // @[package.scala:81:59] wire _id_ctrl_legal_T = ~_csr_io_vector_vconfig_vtype_vill; // @[RocketCore.scala:341:19, :355:24] assign id_ctrl_legal = _v_decode_io_legal ? _id_ctrl_legal_T : id_ctrl_decoder_0; // @[RocketCore.scala:321:21, :354:30, :355:{21,24}] assign id_ctrl_fp = _v_decode_io_legal ? _v_decode_io_fp : id_ctrl_decoder_1; // @[RocketCore.scala:321:21, :354:30, :356:18] assign id_ctrl_rocc = ~_v_decode_io_legal & id_ctrl_decoder_2; // @[RocketCore.scala:321:21, :354:30, :357:20] assign id_ctrl_branch = ~_v_decode_io_legal & id_ctrl_decoder_3; // @[RocketCore.scala:321:21, :354:30, :357:20, :358:22] assign id_ctrl_jal = ~_v_decode_io_legal & id_ctrl_decoder_4; // @[RocketCore.scala:321:21, :354:30, :357:20, :359:19] assign id_ctrl_jalr = ~_v_decode_io_legal & id_ctrl_decoder_5; // @[RocketCore.scala:321:21, :354:30, :357:20, :360:20] assign id_ctrl_rxs2 = _v_decode_io_legal ? _v_decode_io_read_rs2 : id_ctrl_decoder_6; // @[RocketCore.scala:321:21, :354:30, :361:20] assign id_ctrl_rxs1 = _v_decode_io_legal ? _v_decode_io_read_rs1 : id_ctrl_decoder_7; // @[RocketCore.scala:321:21, :354:30, :362:20] assign id_ctrl_mem = ~_v_decode_io_legal & id_ctrl_decoder_13; // @[RocketCore.scala:321:21, :354:30, :357:20, :363:19] assign id_ctrl_rfs1 = _v_decode_io_legal ? _v_decode_io_read_frs1 : id_ctrl_decoder_15; // @[RocketCore.scala:321:21, :354:30, :364:20] assign id_ctrl_rfs2 = ~_v_decode_io_legal & id_ctrl_decoder_16; // @[RocketCore.scala:321:21, :354:30, :357:20, :365:20] assign id_ctrl_rfs3 = ~_v_decode_io_legal & id_ctrl_decoder_17; // @[RocketCore.scala:321:21, :354:30, :357:20, :366:20] assign id_ctrl_wfd = _v_decode_io_legal ? _v_decode_io_write_frd : id_ctrl_decoder_18; // @[RocketCore.scala:321:21, :354:30, :367:19] assign id_ctrl_mul = ~_v_decode_io_legal & id_ctrl_decoder_19; // @[RocketCore.scala:321:21, :354:30, :357:20, :368:19] assign id_ctrl_div = ~_v_decode_io_legal & id_ctrl_decoder_20; // @[RocketCore.scala:321:21, :354:30, :357:20, :369:19] assign id_ctrl_wxd = _v_decode_io_legal ? _v_decode_io_write_rd : id_ctrl_decoder_21; // @[RocketCore.scala:321:21, :354:30, :370:19] assign id_ctrl_csr = _v_decode_io_legal ? 3'h0 : id_ctrl_decoder_22; // @[RocketCore.scala:321:21, :354:30, :371:19] assign id_ctrl_fence_i = ~_v_decode_io_legal & id_ctrl_decoder_23; // @[RocketCore.scala:321:21, :354:30, :357:20, :372:23] assign id_ctrl_fence = ~_v_decode_io_legal & id_ctrl_decoder_24; // @[RocketCore.scala:321:21, :354:30, :357:20, :373:21] assign id_ctrl_amo = ~_v_decode_io_legal & id_ctrl_decoder_25; // @[RocketCore.scala:321:21, :354:30, :357:20, :374:19] assign id_ctrl_dp = ~_v_decode_io_legal & id_ctrl_decoder_26; // @[RocketCore.scala:321:21, :354:30, :357:20, :375:18] wire _id_illegal_insn_T = ~id_ctrl_legal; // @[RocketCore.scala:321:21, :381:25] wire _id_illegal_insn_T_1 = id_ctrl_mul \| id_ctrl_div; // @[RocketCore.scala:321:21, :382:18] wire _id_illegal_insn_T_2 = _csr_io_status_isa[12]; // @[RocketCore.scala:341:19, :382:55] wire _id_illegal_insn_T_3 = ~_id_illegal_insn_T_2; // @[RocketCore.scala:382:{37,55}] wire _id_illegal_insn_T_4 = _id_illegal_insn_T_1 & _id_illegal_insn_T_3; // @[RocketCore.scala:382:{18,34,37}] wire _id_illegal_insn_T_5 = _id_illegal_insn_T \| _id_illegal_insn_T_4; // @[RocketCore.scala:381:{25,40}, :382:34] wire _id_illegal_insn_T_6 = _csr_io_status_isa[0]; // @[RocketCore.scala:341:19, :383:38] wire _id_illegal_insn_T_7 = ~_id_illegal_insn_T_6; // @[RocketCore.scala:383:{20,38}] wire _id_illegal_insn_T_8 = id_ctrl_amo & _id_illegal_insn_T_7; // @[RocketCore.scala:321:21, :383:{17,20}] wire _id_illegal_insn_T_9 = _id_illegal_insn_T_5 \| _id_illegal_insn_T_8; // @[RocketCore.scala:381:40, :382:65, :383:17] wire _id_illegal_insn_T_10 = ~id_ctrl_vec; // @[RocketCore.scala:321:21, :384:73] wire _id_illegal_insn_T_11 = io_fpu_illegal_rm_0 & _id_illegal_insn_T_10; // @[RocketCore.scala:153:7, :384:{70,73}] wire _id_illegal_insn_T_12 = _csr_io_decode_0_fp_illegal \| _id_illegal_insn_T_11; // @[RocketCore.scala:341:19, :384:{48,70}] wire _id_illegal_insn_T_13 = id_ctrl_fp & _id_illegal_insn_T_12; // @[RocketCore.scala:321:21, :384:{16,48}] wire _id_illegal_insn_T_14 = _id_illegal_insn_T_9 \| _id_illegal_insn_T_13; // @[RocketCore.scala:382:65, :383:48, :384:16] wire _id_illegal_insn_T_15 = _csr_io_decode_0_vector_illegal \| _csr_io_vector_vconfig_vtype_vill; // @[RocketCore.scala:341:19, :385:55] wire _id_illegal_insn_T_16 = id_ctrl_vec & _id_illegal_insn_T_15; // @[RocketCore.scala:321:21, :385:{19,55}] wire _id_illegal_insn_T_17 = _id_illegal_insn_T_14 \| _id_illegal_insn_T_16; // @[RocketCore.scala:383:48, :384:88, :385:19] wire _id_illegal_insn_T_18 = _csr_io_status_isa[3]; // @[RocketCore.scala:341:19, :386:37] wire _id_illegal_insn_T_19 = ~_id_illegal_insn_T_18; // @[RocketCore.scala:386:{19,37}] wire _id_illegal_insn_T_20 = id_ctrl_dp & _id_illegal_insn_T_19; // @[RocketCore.scala:321:21, :386:{16,19}] wire _id_illegal_insn_T_21 = _id_illegal_insn_T_17 \| _id_illegal_insn_T_20; // @[RocketCore.scala:384:88, :385:118, :386:16] wire _id_illegal_insn_T_22 = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51] wire _mem_npc_misaligned_T = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51, :623:46] wire _id_illegal_insn_T_23 = ~_id_illegal_insn_T_22; // @[RocketCore.scala:387:{33,51}] wire _id_illegal_insn_T_24 = _ibuf_io_inst_0_bits_rvc & _id_illegal_insn_T_23; // @[RocketCore.scala:311:20, :387:{30,33}] wire _id_illegal_insn_T_25 = _id_illegal_insn_T_21 \| _id_illegal_insn_T_24; // @[RocketCore.scala:385:118, :386:47, :387:30] wire _id_illegal_insn_T_27 = _id_illegal_insn_T_25; // @[RocketCore.scala:386:47, :387:61] wire _id_illegal_insn_T_29 = _id_illegal_insn_T_27; // @[RocketCore.scala:387:61, :388:39] wire _id_illegal_insn_T_31 = _id_illegal_insn_T_29; // @[RocketCore.scala:388:39, :389:39] wire _id_illegal_insn_T_33 = _id_illegal_insn_T_31 \| _id_illegal_insn_T_32; // @[RocketCore.scala:389:39, :390:37, :391:18] wire _id_illegal_insn_T_34 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :392:52] wire _id_illegal_insn_T_35 = _id_illegal_insn_T_34 & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :392:{52,64}] wire _id_illegal_insn_T_36 = _csr_io_decode_0_read_illegal \| _id_illegal_insn_T_35; // @[RocketCore.scala:341:19, :392:{49,64}] wire _id_illegal_insn_T_37 = id_csr_en & _id_illegal_insn_T_36; // @[package.scala:81:59] wire _id_illegal_insn_T_38 = _id_illegal_insn_T_33 \| _id_illegal_insn_T_37; // @[RocketCore.scala:390:37, :391:51, :392:15] wire _id_illegal_insn_T_39 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5] wire _id_illegal_insn_T_40 = id_system_insn & _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19, :343:36, :393:50] wire _id_illegal_insn_T_41 = _id_illegal_insn_T_39 & _id_illegal_insn_T_40; // @[RocketCore.scala:393:{5,31,50}] wire id_illegal_insn = _id_illegal_insn_T_38 \| _id_illegal_insn_T_41; // @[RocketCore.scala:391:51, :392:99, :393:31] wire _id_virtual_insn_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :395:22] wire _id_virtual_insn_T_1 = _id_virtual_insn_T & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :395:{22,34}] wire _id_virtual_insn_T_2 = ~_id_virtual_insn_T_1; // @[RocketCore.scala:395:{20,34}] wire _id_virtual_insn_T_3 = id_csr_en & _id_virtual_insn_T_2; // @[package.scala:81:59] wire _id_virtual_insn_T_4 = _id_virtual_insn_T_3 & _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19, :395:{17,69}] wire _id_virtual_insn_T_5 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5, :396:7] wire _id_virtual_insn_T_6 = _id_virtual_insn_T_5 & id_system_insn; // @[RocketCore.scala:343:36, :396:{7,33}] wire _id_virtual_insn_T_7 = _id_virtual_insn_T_6 & _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19, :396:{33,51}] wire _id_virtual_insn_T_8 = _id_virtual_insn_T_4 \| _id_virtual_insn_T_7; // @[RocketCore.scala:395:{69,113}, :396:51] wire id_virtual_insn = id_ctrl_legal & _id_virtual_insn_T_8; // @[RocketCore.scala:321:21, :394:39, :395:113] wire id_amo_aq = _ibuf_io_inst_0_bits_inst_bits[26]; // @[RocketCore.scala:311:20, :398:29] wire id_amo_rl = _ibuf_io_inst_0_bits_inst_bits[25]; // @[RocketCore.scala:311:20, :399:29] wire [3:0] id_fence_pred = _ibuf_io_inst_0_bits_inst_bits[27:24]; // @[RocketCore.scala:311:20, :400:33] wire [3:0] id_fence_succ = _ibuf_io_inst_0_bits_inst_bits[23:20]; // @[RocketCore.scala:311:20, :401:33] wire _id_fence_next_T = id_ctrl_amo & id_amo_aq; // @[RocketCore.scala:321:21, :398:29, :402:52] wire id_fence_next = id_ctrl_fence \| _id_fence_next_T; // @[RocketCore.scala:321:21, :402:{37,52}] wire _id_mem_busy_T = ~io_dmem_ordered_0; // @[RocketCore.scala:153:7, :403:21] wire id_mem_busy = _id_mem_busy_T \| io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :403:{21,38}] wire _id_rocc_busy_T = ex_reg_valid & ex_ctrl_rocc; // @[RocketCore.scala:243:20, :248:35, :406:35] wire _id_rocc_busy_T_1 = _id_rocc_busy_T; // @[RocketCore.scala:406:{19,35}] wire _id_rocc_busy_T_2 = mem_reg_valid & mem_ctrl_rocc; // @[RocketCore.scala:244:21, :265:36, :407:20] wire _id_rocc_busy_T_3 = _id_rocc_busy_T_1 \| _id_rocc_busy_T_2; // @[RocketCore.scala:406:{19,51}, :407:20] wire _GEN_32 = wb_reg_valid & wb_ctrl_rocc; // @[RocketCore.scala:245:20, :288:35, :407:53] wire _id_rocc_busy_T_4; // @[RocketCore.scala:407:53] assign _id_rocc_busy_T_4 = _GEN_32; // @[RocketCore.scala:407:53] wire _replay_wb_rocc_T; // @[RocketCore.scala:758:37] assign _replay_wb_rocc_T = _GEN_32; // @[RocketCore.scala:407:53, :758:37] wire _io_rocc_cmd_valid_T; // @[RocketCore.scala:1156:37] assign _io_rocc_cmd_valid_T = _GEN_32; // @[RocketCore.scala:407:53, :1156:37] wire _id_rocc_busy_T_5 = _id_rocc_busy_T_3 \| _id_rocc_busy_T_4; // @[RocketCore.scala:406:51, :407:{37,53}] wire _id_csr_rocc_write_T_1 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :408:103] wire _id_do_fence_T_2 = id_vec_busy & id_ctrl_fence; // @[RocketCore.scala:321:21, :409:55, :411:17] wire _id_do_fence_T_3 = _id_do_fence_T_2; // @[RocketCore.scala:410:86, :411:17] wire _id_do_fence_T_4 = id_ctrl_amo & id_amo_rl; // @[RocketCore.scala:321:21, :399:29, :412:33] wire _id_do_fence_T_5 = _id_do_fence_T_4 \| id_ctrl_fence_i; // @[RocketCore.scala:321:21, :412:{33,46}] wire _id_do_fence_T_6 = id_ctrl_mem \| id_ctrl_rocc; // @[RocketCore.scala:321:21, :412:97] wire _id_do_fence_T_7 = id_reg_fence & _id_do_fence_T_6; // @[RocketCore.scala:333:29, :412:{81,97}] wire _id_do_fence_T_8 = _id_do_fence_T_5 \| _id_do_fence_T_7; // @[RocketCore.scala:412:{46,65,81}] wire _id_do_fence_T_9 = id_mem_busy & _id_do_fence_T_8; // @[RocketCore.scala:403:38, :412:{17,65}] wire _id_do_fence_T_10 = _id_do_fence_T_3 \| _id_do_fence_T_9; // @[RocketCore.scala:410:86, :411:34, :412:17] wire id_do_fence = _id_do_fence_T_10; // @[RocketCore.scala:410:32, :411:34] wire [38:0] _mem_npc_T_1 = mem_reg_wdata[38:0]; // @[RocketCore.scala:282:26, :418:13, :1295:16] wire id_xcpt = _csr_io_interrupt \| _bpu_io_debug_if \| _bpu_io_xcpt_if \| _ibuf_io_inst_0_bits_xcpt0_pf_inst \| _ibuf_io_inst_0_bits_xcpt0_gf_inst \| _ibuf_io_inst_0_bits_xcpt0_ae_inst \| _ibuf_io_inst_0_bits_xcpt1_pf_inst \| _ibuf_io_inst_0_bits_xcpt1_gf_inst \| _ibuf_io_inst_0_bits_xcpt1_ae_inst \| id_virtual_insn \| id_illegal_insn; // @[RocketCore.scala:311:20, :341:19, :392:99, :394:39, :414:19, :1278:{14,35}] wire [63:0] id_cause = _csr_io_interrupt ? _csr_io_interrupt_cause : {59'h0, _bpu_io_debug_if ? 5'hE : _bpu_io_xcpt_if ? 5'h3 : _ibuf_io_inst_0_bits_xcpt0_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt0_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt0_ae_inst ? 5'h1 : _ibuf_io_inst_0_bits_xcpt1_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt1_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt1_ae_inst ? 5'h1 : id_virtual_insn ? 5'h16 : 5'h2}; // @[Mux.scala:50:70] wire [4:0] _ex_waddr_T = ex_reg_inst[11:7]; // @[RocketCore.scala:259:24, :453:29] wire [4:0] _ex_avl_T_2 = ex_reg_inst[11:7]; // @[RocketCore.scala:259:24, :453:29, :493:24] wire [4:0] ex_waddr = _ex_waddr_T; // @[RocketCore.scala:453:{29,36}] wire [4:0] _mem_waddr_T = mem_reg_inst[11:7]; // @[RocketCore.scala:278:25, :454:31] wire [4:0] mem_waddr = _mem_waddr_T; // @[RocketCore.scala:454:{31,38}] wire [4:0] _wb_waddr_T = wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :455:29] wire [4:0] wb_waddr = _wb_waddr_T; // @[RocketCore.scala:455:{29,36}] wire [4:0] coreMonitorBundle_wrdst = wb_waddr; // @[RocketCore.scala:455:36, :1186:31] wire bypass_sources_1_1 = ex_reg_valid & ex_ctrl_wxd; // @[RocketCore.scala:243:20, :248:35, :458:19] wire _GEN_33 = mem_reg_valid & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :265:36, :459:20] wire _bypass_sources_T; // @[RocketCore.scala:459:20] assign _bypass_sources_T = _GEN_33; // @[RocketCore.scala:459:20] wire bypass_sources_3_1; // @[RocketCore.scala:460:20] assign bypass_sources_3_1 = _GEN_33; // @[RocketCore.scala:459:20, :460:20] wire _dcache_kill_mem_T; // @[RocketCore.scala:695:39] assign _dcache_kill_mem_T = _GEN_33; // @[RocketCore.scala:459:20, :695:39] wire _bypass_sources_T_1 = ~mem_ctrl_mem; // @[RocketCore.scala:244:21, :459:39] wire bypass_sources_2_1 = _bypass_sources_T & _bypass_sources_T_1; // @[RocketCore.scala:459:{20,36,39}] wire _id_bypass_src_T = ~(\|id_raddr1); // @[RocketCore.scala:326:72, :461:82, :1326:41] wire id_bypass_src_0_0 = _id_bypass_src_T; // @[RocketCore.scala:461:{74,82}] wire _GEN_34 = ex_waddr == id_raddr1; // @[RocketCore.scala:326:72, :453:36, :461:82] wire _id_bypass_src_T_1; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_1 = _GEN_34; // @[RocketCore.scala:461:82] wire _data_hazard_ex_T; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T = _GEN_34; // @[RocketCore.scala:461:82, :989:70] wire _fp_data_hazard_ex_T_1; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_1 = _GEN_34; // @[RocketCore.scala:461:82, :990:90] wire id_bypass_src_0_1 = bypass_sources_1_1 & _id_bypass_src_T_1; // @[RocketCore.scala:458:19, :461:{74,82}] wire _GEN_35 = mem_waddr == id_raddr1; // @[RocketCore.scala:326:72, :454:38, :461:82] wire _id_bypass_src_T_2; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_2 = _GEN_35; // @[RocketCore.scala:461:82] wire _id_bypass_src_T_3; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_3 = _GEN_35; // @[RocketCore.scala:461:82] wire _data_hazard_mem_T; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T = _GEN_35; // @[RocketCore.scala:461:82, :998:72] wire _fp_data_hazard_mem_T_1; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_1 = _GEN_35; // @[RocketCore.scala:461:82, :999:92] wire id_bypass_src_0_2 = bypass_sources_2_1 & _id_bypass_src_T_2; // @[RocketCore.scala:459:36, :461:{74,82}] wire id_bypass_src_0_3 = bypass_sources_3_1 & _id_bypass_src_T_3; // @[RocketCore.scala:460:20, :461:{74,82}] wire _id_bypass_src_T_4 = ~(\|id_raddr2); // @[RocketCore.scala:326:72, :461:82, :1326:41] wire id_bypass_src_1_0 = _id_bypass_src_T_4; // @[RocketCore.scala:461:{74,82}] wire _GEN_36 = ex_waddr == id_raddr2; // @[RocketCore.scala:326:72, :453:36, :461:82] wire _id_bypass_src_T_5; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_5 = _GEN_36; // @[RocketCore.scala:461:82] wire _data_hazard_ex_T_2; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T_2 = _GEN_36; // @[RocketCore.scala:461:82, :989:70] wire _fp_data_hazard_ex_T_3; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_3 = _GEN_36; // @[RocketCore.scala:461:82, :990:90] wire id_bypass_src_1_1 = bypass_sources_1_1 & _id_bypass_src_T_5; // @[RocketCore.scala:458:19, :461:{74,82}] wire _GEN_37 = mem_waddr == id_raddr2; // @[RocketCore.scala:326:72, :454:38, :461:82] wire _id_bypass_src_T_6; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_6 = _GEN_37; // @[RocketCore.scala:461:82] wire _id_bypass_src_T_7; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_7 = _GEN_37; // @[RocketCore.scala:461:82] wire _data_hazard_mem_T_2; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T_2 = _GEN_37; // @[RocketCore.scala:461:82, :998:72] wire _fp_data_hazard_mem_T_3; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_3 = _GEN_37; // @[RocketCore.scala:461:82, :999:92] wire id_bypass_src_1_2 = bypass_sources_2_1 & _id_bypass_src_T_6; // @[RocketCore.scala:459:36, :461:{74,82}] wire id_bypass_src_1_3 = bypass_sources_3_1 & _id_bypass_src_T_7; // @[RocketCore.scala:460:20, :461:{74,82}] reg ex_reg_rs_bypass_0; // @[RocketCore.scala:465:29] reg ex_reg_rs_bypass_1; // @[RocketCore.scala:465:29] reg [1:0] ex_reg_rs_lsb_0; // @[RocketCore.scala:466:26] reg [1:0] ex_reg_rs_lsb_1; // @[RocketCore.scala:466:26] reg [61:0] ex_reg_rs_msb_0; // @[RocketCore.scala:467:26] reg [61:0] ex_reg_rs_msb_1; // @[RocketCore.scala:467:26] wire _ex_rs_T = ex_reg_rs_lsb_0 == 2'h1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_1 = _ex_rs_T ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}] wire _ex_rs_T_2 = ex_reg_rs_lsb_0 == 2'h2; // @[package.scala:39:86] wire [63:0] _ex_rs_T_3 = _ex_rs_T_2 ? wb_reg_wdata : _ex_rs_T_1; // @[package.scala:39:{76,86}] wire _ex_rs_T_4 = &ex_reg_rs_lsb_0; // @[package.scala:39:86] wire [63:0] _ex_rs_T_5 = _ex_rs_T_4 ? dcache_bypass_data : _ex_rs_T_3; // @[package.scala:39:{76,86}] wire [63:0] _ex_rs_T_6 = {ex_reg_rs_msb_0, ex_reg_rs_lsb_0}; // @[RocketCore.scala:466:26, :467:26, :469:69] assign ex_rs_0 = ex_reg_rs_bypass_0 ? _ex_rs_T_5 : _ex_rs_T_6; // @[package.scala:39:76] assign io_fpu_fromint_data_0 = ex_rs_0; // @[RocketCore.scala:153:7, :469:14] assign io_vector_ex_rs1_0 = ex_rs_0; // @[RocketCore.scala:153:7, :469:14] wire [63:0] _ex_op1_T = ex_rs_0; // @[RocketCore.scala:469:14, :473:24] wire _ex_rs_T_7 = ex_reg_rs_lsb_1 == 2'h1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_8 = _ex_rs_T_7 ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}] wire _ex_rs_T_9 = ex_reg_rs_lsb_1 == 2'h2; // @[package.scala:39:86] wire [63:0] _ex_rs_T_10 = _ex_rs_T_9 ? wb_reg_wdata : _ex_rs_T_8; // @[package.scala:39:{76,86}] wire _ex_rs_T_11 = &ex_reg_rs_lsb_1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_12 = _ex_rs_T_11 ? dcache_bypass_data : _ex_rs_T_10; // @[package.scala:39:{76,86}] wire [63:0] _ex_rs_T_13 = {ex_reg_rs_msb_1, ex_reg_rs_lsb_1}; // @[RocketCore.scala:466:26, :467:26, :469:69] assign ex_rs_1 = ex_reg_rs_bypass_1 ? _ex_rs_T_12 : _ex_rs_T_13; // @[package.scala:39:76] assign io_vector_ex_rs2_0 = ex_rs_1; // @[RocketCore.scala:153:7, :469:14] wire [63:0] _ex_op2_T = ex_rs_1; // @[RocketCore.scala:469:14, :479:24] wire [63:0] mem_reg_rs2_dat_padded = ex_rs_1; // @[RocketCore.scala:469:14] wire _GEN_38 = ex_ctrl_sel_imm == 3'h5; // @[RocketCore.scala:243:20, :1341:24] wire _ex_imm_sign_T; // @[RocketCore.scala:1341:24] assign _ex_imm_sign_T = _GEN_38; // @[RocketCore.scala:1341:24] wire _ex_imm_b11_T_1; // @[RocketCore.scala:1344:40] assign _ex_imm_b11_T_1 = _GEN_38; // @[RocketCore.scala:1341:24, :1344:40] wire _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:42] assign _ex_imm_b10_5_T_1 = _GEN_38; // @[RocketCore.scala:1341:24, :1347:42] wire _ex_imm_b4_1_T_5; // @[RocketCore.scala:1350:24] assign _ex_imm_b4_1_T_5 = _GEN_38; // @[RocketCore.scala:1341:24, :1350:24] wire _ex_imm_b0_T_4; // @[RocketCore.scala:1353:22] assign _ex_imm_b0_T_4 = _GEN_38; // @[RocketCore.scala:1341:24, :1353:22] wire _ex_imm_sign_T_1 = ex_reg_inst[31]; // @[RocketCore.scala:259:24, :1341:44] wire _ex_new_vtype_T_3 = ex_reg_inst[31]; // @[RocketCore.scala:259:24, :490:19, :1341:44] wire _ex_imm_sign_T_2 = _ex_imm_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire ex_imm_sign = ~_ex_imm_sign_T & _ex_imm_sign_T_2; // @[RocketCore.scala:1341:{19,24,49}] wire ex_imm_hi_hi_hi = ex_imm_sign; // @[RocketCore.scala:1341:19, :1355:8] wire _GEN_39 = ex_ctrl_sel_imm == 3'h2; // @[RocketCore.scala:243:20, :1342:26] wire _ex_imm_b30_20_T; // @[RocketCore.scala:1342:26] assign _ex_imm_b30_20_T = _GEN_39; // @[RocketCore.scala:1342:26] wire _ex_imm_b11_T; // @[RocketCore.scala:1344:23] assign _ex_imm_b11_T = _GEN_39; // @[RocketCore.scala:1342:26, :1344:23] wire _ex_imm_b10_5_T; // @[RocketCore.scala:1347:25] assign _ex_imm_b10_5_T = _GEN_39; // @[RocketCore.scala:1342:26, :1347:25] wire _ex_imm_b4_1_T; // @[RocketCore.scala:1348:24] assign _ex_imm_b4_1_T = _GEN_39; // @[RocketCore.scala:1342:26, :1348:24] wire [10:0] _ex_imm_b30_20_T_1 = ex_reg_inst[30:20]; // @[RocketCore.scala:259:24, :1342:41] wire [10:0] _ex_new_vtype_T_5 = ex_reg_inst[30:20]; // @[RocketCore.scala:259:24, :490:45, :1342:41] wire [10:0] _ex_imm_b30_20_T_2 = _ex_imm_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] ex_imm_b30_20 = _ex_imm_b30_20_T ? _ex_imm_b30_20_T_2 : {11{ex_imm_sign}}; // @[RocketCore.scala:1341:19, :1342:{21,26,49}] wire [10:0] ex_imm_hi_hi_lo = ex_imm_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire _ex_imm_b19_12_T = ex_ctrl_sel_imm != 3'h2; // @[RocketCore.scala:243:20, :1343:26] wire _ex_imm_b19_12_T_1 = ex_ctrl_sel_imm != 3'h3; // @[RocketCore.scala:243:20, :1343:43] wire _ex_imm_b19_12_T_2 = _ex_imm_b19_12_T & _ex_imm_b19_12_T_1; // @[RocketCore.scala:1343:{26,36,43}] wire [7:0] _ex_imm_b19_12_T_3 = ex_reg_inst[19:12]; // @[RocketCore.scala:259:24, :1343:65] wire [7:0] _ex_imm_b19_12_T_4 = _ex_imm_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] ex_imm_b19_12 = _ex_imm_b19_12_T_2 ? {8{ex_imm_sign}} : _ex_imm_b19_12_T_4; // @[RocketCore.scala:1341:19, :1343:{21,36,73}] wire [7:0] ex_imm_hi_lo_hi = ex_imm_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _ex_imm_b11_T_2 = _ex_imm_b11_T \| _ex_imm_b11_T_1; // @[RocketCore.scala:1344:{23,33,40}] wire _ex_imm_b11_T_3 = ex_ctrl_sel_imm == 3'h3; // @[RocketCore.scala:243:20, :1345:23] wire _ex_imm_b11_T_4 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39] wire _ex_imm_b0_T_3 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39, :1352:37] wire _io_dmem_req_bits_signed_T = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1136:58, :1345:39] wire _ex_imm_b11_T_5 = _ex_imm_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _GEN_40 = ex_ctrl_sel_imm == 3'h1; // @[RocketCore.scala:243:20, :1346:23] wire _ex_imm_b11_T_6; // @[RocketCore.scala:1346:23] assign _ex_imm_b11_T_6 = _GEN_40; // @[RocketCore.scala:1346:23] wire _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:41] assign _ex_imm_b4_1_T_2 = _GEN_40; // @[RocketCore.scala:1346:23, :1349:41] wire _ex_imm_b11_T_7 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39] wire _ex_imm_b0_T_1 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39, :1351:37] wire _ex_imm_b11_T_8 = _ex_imm_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _ex_imm_b11_T_9 = _ex_imm_b11_T_6 ? _ex_imm_b11_T_8 : ex_imm_sign; // @[RocketCore.scala:1341:19, :1346:{18,23,43}] wire _ex_imm_b11_T_10 = _ex_imm_b11_T_3 ? _ex_imm_b11_T_5 : _ex_imm_b11_T_9; // @[RocketCore.scala:1345:{18,23,44}, :1346:18] wire ex_imm_b11 = ~_ex_imm_b11_T_2 & _ex_imm_b11_T_10; // @[RocketCore.scala:1344:{18,33}, :1345:18] wire ex_imm_hi_lo_lo = ex_imm_b11; // @[RocketCore.scala:1344:18, :1355:8] wire _ex_imm_b10_5_T_2 = _ex_imm_b10_5_T \| _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:{25,35,42}] wire [5:0] _ex_imm_b10_5_T_3 = ex_reg_inst[30:25]; // @[RocketCore.scala:259:24, :1347:62] wire [5:0] ex_imm_b10_5 = _ex_imm_b10_5_T_2 ? 6'h0 : _ex_imm_b10_5_T_3; // @[RocketCore.scala:1347:{20,35,62}] wire _GEN_41 = ex_ctrl_sel_imm == 3'h0; // @[RocketCore.scala:243:20, :1349:24] wire _ex_imm_b4_1_T_1; // @[RocketCore.scala:1349:24] assign _ex_imm_b4_1_T_1 = _GEN_41; // @[RocketCore.scala:1349:24] wire _ex_imm_b0_T; // @[RocketCore.scala:1351:22] assign _ex_imm_b0_T = _GEN_41; // @[RocketCore.scala:1349:24, :1351:22] wire _ex_imm_b4_1_T_3 = _ex_imm_b4_1_T_1 \| _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:{24,34,41}] wire [3:0] _ex_imm_b4_1_T_4 = ex_reg_inst[11:8]; // @[RocketCore.scala:259:24, :1349:57] wire [3:0] _ex_imm_b4_1_T_6 = ex_reg_inst[19:16]; // @[RocketCore.scala:259:24, :1350:39] wire [3:0] _ex_imm_b4_1_T_7 = ex_reg_inst[24:21]; // @[RocketCore.scala:259:24, :1350:52] wire [3:0] _ex_imm_b4_1_T_8 = _ex_imm_b4_1_T_5 ? _ex_imm_b4_1_T_6 : _ex_imm_b4_1_T_7; // @[RocketCore.scala:1350:{19,24,39,52}] wire [3:0] _ex_imm_b4_1_T_9 = _ex_imm_b4_1_T_3 ? _ex_imm_b4_1_T_4 : _ex_imm_b4_1_T_8; // @[RocketCore.scala:1349:{19,34,57}, :1350:19] wire [3:0] ex_imm_b4_1 = _ex_imm_b4_1_T ? 4'h0 : _ex_imm_b4_1_T_9; // @[RocketCore.scala:1348:{19,24}, :1349:19] wire _ex_imm_b0_T_2 = ex_ctrl_sel_imm == 3'h4; // @[RocketCore.scala:243:20, :1352:22] wire _ex_imm_b0_T_5 = ex_reg_inst[15]; // @[RocketCore.scala:259:24, :1353:37] wire _ex_imm_b0_T_6 = _ex_imm_b0_T_4 & _ex_imm_b0_T_5; // @[RocketCore.scala:1353:{17,22,37}] wire _ex_imm_b0_T_7 = _ex_imm_b0_T_2 ? _ex_imm_b0_T_3 : _ex_imm_b0_T_6; // @[RocketCore.scala:1352:{17,22,37}, :1353:17] wire ex_imm_b0 = _ex_imm_b0_T ? _ex_imm_b0_T_1 : _ex_imm_b0_T_7; // @[RocketCore.scala:1351:{17,22,37}, :1352:17] wire [9:0] ex_imm_lo_hi = {ex_imm_b10_5, ex_imm_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] ex_imm_lo = {ex_imm_lo_hi, ex_imm_b0}; // @[RocketCore.scala:1351:17, :1355:8] wire [8:0] ex_imm_hi_lo = {ex_imm_hi_lo_hi, ex_imm_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] ex_imm_hi_hi = {ex_imm_hi_hi_hi, ex_imm_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] ex_imm_hi = {ex_imm_hi_hi, ex_imm_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _ex_imm_T = {ex_imm_hi, ex_imm_lo}; // @[RocketCore.scala:1355:8] wire [31:0] ex_imm = _ex_imm_T; // @[RocketCore.scala:1355:{8,53}] wire _ex_rs1shl_T = ex_reg_inst[3]; // @[RocketCore.scala:259:24, :471:34] wire [31:0] _ex_rs1shl_T_1 = ex_rs_0[31:0]; // @[RocketCore.scala:469:14, :471:47] wire [63:0] _ex_rs1shl_T_2 = _ex_rs1shl_T ? {32'h0, _ex_rs1shl_T_1} : ex_rs_0; // @[RocketCore.scala:469:14, :471:{22,34,47}] wire [1:0] _ex_rs1shl_T_3 = ex_reg_inst[14:13]; // @[RocketCore.scala:259:24, :471:79] wire [66:0] ex_rs1shl = {3'h0, _ex_rs1shl_T_2} << _ex_rs1shl_T_3; // @[RocketCore.scala:471:{22,65,79}] wire [66:0] _ex_op1_T_2 = ex_rs1shl; // @[RocketCore.scala:471:65, :475:54] wire _ex_op1_T_3 = ex_ctrl_sel_alu1 == 2'h1; // @[RocketCore.scala:243:20, :472:48] wire [63:0] _ex_op1_T_4 = _ex_op1_T_3 ? _ex_op1_T : 64'h0; // @[RocketCore.scala:472:48, :473:24] wire _ex_op1_T_5 = ex_ctrl_sel_alu1 == 2'h2; // @[RocketCore.scala:243:20, :472:48] wire [63:0] _ex_op1_T_6 = _ex_op1_T_5 ? {{24{_ex_op1_T_1[39]}}, _ex_op1_T_1} : _ex_op1_T_4; // @[RocketCore.scala:472:48, :474:24] wire _ex_op1_T_7 = &ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20, :472:48] wire [66:0] ex_op1 = _ex_op1_T_7 ? _ex_op1_T_2 : {{3{_ex_op1_T_6[63]}}, _ex_op1_T_6}; // @[RocketCore.scala:472:48, :475:54] wire [66:0] _alu_io_in1_T = ex_op1; // @[RocketCore.scala:472:48, :508:24] wire _ex_op2_oh_T = ex_ctrl_sel_alu2[0]; // @[RocketCore.scala:243:20, :477:48] wire [11:0] _ex_op2_oh_T_1 = ex_reg_inst[31:20]; // @[RocketCore.scala:259:24, :477:66] wire [63:0] _ex_op2_oh_T_2 = _ex_op2_oh_T ? {52'h0, _ex_op2_oh_T_1} : ex_rs_1; // @[RocketCore.scala:469:14, :477:{31,48,66}] wire [5:0] _ex_op2_oh_T_3 = _ex_op2_oh_T_2[5:0]; // @[RocketCore.scala:477:{31,90}] wire [63:0] _ex_op2_oh_T_4 = 64'h1 << _ex_op2_oh_T_3; // @[OneHot.scala:58:35] wire [63:0] ex_op2_oh = _ex_op2_oh_T_4; // @[OneHot.scala:58:35] wire [3:0] _ex_op2_T_1 = ex_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:249:35, :481:19] wire _ex_op2_T_2 = ex_ctrl_sel_alu2 == 3'h2; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_3 = _ex_op2_T_2 ? _ex_op2_T : 64'h0; // @[RocketCore.scala:478:48, :479:24] wire _ex_op2_T_4 = ex_ctrl_sel_alu2 == 3'h3; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_5 = _ex_op2_T_4 ? {{32{ex_imm[31]}}, ex_imm} : _ex_op2_T_3; // @[RocketCore.scala:478:48, :1355:53] wire _ex_op2_T_6 = ex_ctrl_sel_alu2 == 3'h1; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_7 = _ex_op2_T_6 ? {{60{_ex_op2_T_1[3]}}, _ex_op2_T_1} : _ex_op2_T_5; // @[RocketCore.scala:478:48, :481:19] wire _ex_op2_T_8 = ex_ctrl_sel_alu2 == 3'h4; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_9 = _ex_op2_T_8 ? ex_op2_oh : _ex_op2_T_7; // @[RocketCore.scala:477:112, :478:48] wire _ex_op2_T_10 = ex_ctrl_sel_alu2 == 3'h5; // @[RocketCore.scala:243:20, :478:48] wire [63:0] ex_op2 = _ex_op2_T_10 ? ex_op2_oh : _ex_op2_T_9; // @[RocketCore.scala:477:112, :478:48] wire [63:0] _alu_io_in2_T = ex_op2; // @[RocketCore.scala:478:48, :507:24] wire [1:0] _ex_new_vtype_T = ex_reg_inst[31:30]; // @[RocketCore.scala:259:24, :489:18] wire _ex_new_vtype_T_1 = &_ex_new_vtype_T; // @[RocketCore.scala:489:{18,26}] wire [9:0] _ex_new_vtype_T_2 = ex_reg_inst[29:20]; // @[RocketCore.scala:259:24, :489:45] wire _ex_new_vtype_T_4 = ~_ex_new_vtype_T_3; // @[RocketCore.scala:490:{7,19}] wire [63:0] _ex_new_vtype_T_6 = _ex_new_vtype_T_4 ? {53'h0, _ex_new_vtype_T_5} : ex_rs_1; // @[Mux.scala:126:16] wire [63:0] _ex_new_vtype_T_7 = _ex_new_vtype_T_1 ? {54'h0, _ex_new_vtype_T_2} : _ex_new_vtype_T_6; // @[Mux.scala:126:16] wire [63:0] _ex_new_vtype_in_WIRE = _ex_new_vtype_T_7; // @[Mux.scala:126:16] wire ex_new_vtype_vill_0; // @[CSR.scala:330:80] wire ex_new_vl_isZero = ex_new_vtype_vill; // @[CSR.scala:328:27, :372:23] wire ex_new_vconfig_vtype_vill = ex_new_vtype_vill; // @[RocketCore.scala:498:30] wire ex_new_vconfig_vtype_vma = ex_new_vtype_vma; // @[RocketCore.scala:498:30] wire ex_new_vconfig_vtype_vta = ex_new_vtype_vta; // @[RocketCore.scala:498:30] wire [2:0] ex_new_vconfig_vtype_vsew = ex_new_vtype_vsew; // @[RocketCore.scala:498:30] wire ex_new_vconfig_vtype_vlmul_sign = ex_new_vtype_vlmul_sign; // @[RocketCore.scala:498:30] wire [1:0] ex_new_vtype_vlmul_mag; // @[CSR.scala:328:27] wire [1:0] ex_new_vconfig_vtype_vlmul_mag = ex_new_vtype_vlmul_mag; // @[RocketCore.scala:498:30] wire _ex_new_vtype_in_T_6; // @[CSR.scala:329:27] wire [54:0] _ex_new_vtype_in_T_5; // @[CSR.scala:329:27] wire _ex_new_vtype_in_T_4; // @[CSR.scala:329:27] wire _ex_new_vtype_in_T_3; // @[CSR.scala:329:27] wire [2:0] _ex_new_vtype_in_T_2; // @[CSR.scala:329:27] wire _ex_new_vtype_in_T_1; // @[CSR.scala:329:27] wire [1:0] _ex_new_vtype_in_T; // @[CSR.scala:329:27] wire ex_new_vtype_in_vill; // @[CSR.scala:329:27] wire [54:0] ex_new_vtype_in_reserved; // @[CSR.scala:329:27] wire ex_new_vtype_in_vma; // @[CSR.scala:329:27] wire ex_new_vtype_in_vta; // @[CSR.scala:329:27] wire [2:0] ex_new_vtype_in_vsew; // @[CSR.scala:329:27] wire ex_new_vtype_in_vlmul_sign; // @[CSR.scala:329:27] wire [1:0] ex_new_vtype_in_vlmul_mag; // @[CSR.scala:329:27] assign _ex_new_vtype_in_T = _ex_new_vtype_in_WIRE[1:0]; // @[CSR.scala:329:27] assign ex_new_vtype_in_vlmul_mag = _ex_new_vtype_in_T; // @[CSR.scala:329:27] assign _ex_new_vtype_in_T_1 = _ex_new_vtype_in_WIRE[2]; // @[CSR.scala:329:27] assign ex_new_vtype_in_vlmul_sign = _ex_new_vtype_in_T_1; // @[CSR.scala:329:27] assign _ex_new_vtype_in_T_2 = _ex_new_vtype_in_WIRE[5:3]; // @[CSR.scala:329:27] assign ex_new_vtype_in_vsew = _ex_new_vtype_in_T_2; // @[CSR.scala:329:27] assign _ex_new_vtype_in_T_3 = _ex_new_vtype_in_WIRE[6]; // @[CSR.scala:329:27] assign ex_new_vtype_in_vta = _ex_new_vtype_in_T_3; // @[CSR.scala:329:27] assign _ex_new_vtype_in_T_4 = _ex_new_vtype_in_WIRE[7]; // @[CSR.scala:329:27] assign ex_new_vtype_in_vma = _ex_new_vtype_in_T_4; // @[CSR.scala:329:27] assign _ex_new_vtype_in_T_5 = _ex_new_vtype_in_WIRE[62:8]; // @[CSR.scala:329:27] assign ex_new_vtype_in_reserved = _ex_new_vtype_in_T_5; // @[CSR.scala:329:27] assign _ex_new_vtype_in_T_6 = _ex_new_vtype_in_WIRE[63]; // @[CSR.scala:329:27] assign ex_new_vtype_in_vill = _ex_new_vtype_in_T_6; // @[CSR.scala:329:27] wire _ex_new_vtype_vill_T = ex_new_vtype_in_vsew[2]; // @[CSR.scala:329:27, :330:31] wire _ex_new_vtype_vill_T_1 = \|ex_new_vtype_in_vlmul_mag; // @[CSR.scala:329:27, :361:59] wire [1:0] _ex_new_vtype_vill_T_2 = ~ex_new_vtype_in_vlmul_mag; // @[CSR.scala:329:27, :361:70] wire [3:0] _ex_new_vtype_vill_T_3 = 4'h3 - {1'h0, ex_new_vtype_in_vsew}; // @[CSR.scala:329:27, :361:99] wire [2:0] _ex_new_vtype_vill_T_4 = _ex_new_vtype_vill_T_3[2:0]; // @[CSR.scala:361:99] wire _ex_new_vtype_vill_T_5 = {1'h0, _ex_new_vtype_vill_T_2} < _ex_new_vtype_vill_T_4; // @[CSR.scala:361:{70,86,99}] wire _ex_new_vtype_vill_T_6 = _ex_new_vtype_vill_T_1 & _ex_new_vtype_vill_T_5; // @[CSR.scala:361:{59,67,86}] wire _ex_new_vtype_vill_T_7 = ~ex_new_vtype_in_vlmul_sign \| _ex_new_vtype_vill_T_6; // @[CSR.scala:329:27, :361:{26,67}] wire _ex_new_vtype_vill_T_8 = ~_ex_new_vtype_vill_T_7; // @[CSR.scala:330:45, :361:26] wire _ex_new_vtype_vill_T_9 = _ex_new_vtype_vill_T \| _ex_new_vtype_vill_T_8; // @[CSR.scala:330:{31,42,45}] wire _ex_new_vtype_vill_T_10 = \|ex_new_vtype_in_reserved; // @[CSR.scala:329:27, :330:72] wire _ex_new_vtype_vill_T_11 = _ex_new_vtype_vill_T_9 \| _ex_new_vtype_vill_T_10; // @[CSR.scala:330:{42,57,72}] assign ex_new_vtype_vill_0 = _ex_new_vtype_vill_T_11 \| ex_new_vtype_in_vill; // @[CSR.scala:329:27, :330:{57,80}] assign ex_new_vtype_vill = ex_new_vtype_vill_0; // @[CSR.scala:328:27, :330:80] wire _ex_new_vtype_T_8 = ~ex_new_vtype_vill_0; // @[CSR.scala:330:80, :331:11] wire _ex_new_vtype_T_9 = _ex_new_vtype_T_8; // @[CSR.scala:331:{11,17}] assign ex_new_vtype_vma = _ex_new_vtype_T_9 & ex_new_vtype_in_vma; // @[CSR.scala:328:27, :329:27, :331:{17,35}, :332:11] assign ex_new_vtype_vta = _ex_new_vtype_T_9 & ex_new_vtype_in_vta; // @[CSR.scala:328:27, :329:27, :331:{17,35}, :332:11] assign ex_new_vtype_vlmul_sign = _ex_new_vtype_T_9 & ex_new_vtype_in_vlmul_sign; // @[CSR.scala:328:27, :329:27, :331:{17,35}, :332:11] assign ex_new_vtype_vlmul_mag = _ex_new_vtype_T_9 ? ex_new_vtype_in_vlmul_mag : 2'h0; // @[CSR.scala:328:27, :329:27, :331:{17,35}, :332:11] wire [1:0] _ex_new_vtype_view__vsew_T = ex_new_vtype_in_vsew[1:0]; // @[CSR.scala:329:27, :333:26] assign ex_new_vtype_vsew = _ex_new_vtype_T_9 ? {1'h0, _ex_new_vtype_view__vsew_T} : 3'h0; // @[CSR.scala:328:27, :331:{17,35}, :333:{16,26}] wire [4:0] _ex_avl_T = ex_reg_inst[19:15]; // @[RocketCore.scala:259:24, :492:22] wire [4:0] _ex_avl_T_14 = ex_reg_inst[19:15]; // @[RocketCore.scala:259:24, :492:22, :496:18] wire _ex_avl_T_1 = _ex_avl_T == 5'h0; // @[RocketCore.scala:492:{22,30}] wire _ex_avl_T_3 = _ex_avl_T_2 == 5'h0; // @[RocketCore.scala:493:{24,31}] wire [1:0] _ex_avl_T_4 = ~ex_new_vtype_vlmul_mag; // @[CSR.scala:328:27, :365:71] wire [2:0] _ex_avl_T_5 = {ex_new_vtype_vlmul_sign, _ex_avl_T_4}; // @[CSR.scala:328:27, :365:{53,71}] wire [3:0] _GEN_42 = {1'h0, ex_new_vtype_vsew}; // @[CSR.scala:328:27, :365:47] wire [3:0] _ex_avl_T_6 = _GEN_42 + {1'h0, _ex_avl_T_5}; // @[CSR.scala:365:{47,53}] wire [12:0] _ex_avl_T_7 = 13'h1000 >> _ex_avl_T_6; // @[CSR.scala:365:{33,47}] wire [12:0] _ex_avl_T_11 = _ex_avl_T_7 & 13'h1FF8; // @[package.scala:174:35] wire [12:0] _ex_avl_T_12 = _ex_avl_T_3 ? _csr_io_vector_vconfig_vl : _ex_avl_T_11; // @[package.scala:174:35] wire [63:0] _ex_avl_T_13 = _ex_avl_T_1 ? {51'h0, _ex_avl_T_12} : ex_rs_0; // @[RocketCore.scala:469:14, :492:{10,30}, :493:12] wire [63:0] ex_avl = ex_ctrl_rxs1 ? _ex_avl_T_13 : {59'h0, _ex_avl_T_14}; // @[RocketCore.scala:243:20, :491:21, :492:10, :496:18] wire [63:0] _ex_new_vl_avl_lsbs_T = ex_avl; // @[RocketCore.scala:491:21] wire _ex_new_vl_atLeastMaxVLMax_T = _csr_io_vector_vconfig_vl[12]; // @[RocketCore.scala:341:19] wire _ex_new_vl_atLeastMaxVLMax_T_1 = \|(ex_avl[63:12]); // @[RocketCore.scala:491:21] wire _ex_new_vl_atLeastMaxVLMax_T_2 = _ex_new_vl_atLeastMaxVLMax_T_1; // @[CSR.scala:368:{40,84}] wire ex_new_vl_atLeastMaxVLMax = _ex_new_vl_atLeastMaxVLMax_T_2; // @[CSR.scala:368:{34,40}] wire [11:0] ex_new_vl_avl_lsbs = _ex_new_vl_avl_lsbs_T[11:0]; // @[CSR.scala:369:{23,53}] wire [1:0] _ex_new_vl_atLeastVLMax_T_3 = ~ex_new_vtype_vlmul_mag; // @[CSR.scala:328:27, :365:71, :371:106] wire [2:0] _ex_new_vl_atLeastVLMax_T_4 = {ex_new_vtype_vlmul_sign, _ex_new_vl_atLeastVLMax_T_3}; // @[CSR.scala:328:27, :371:{88,106}] wire [3:0] _ex_new_vl_atLeastVLMax_T_5 = _GEN_42 + {1'h0, _ex_new_vl_atLeastVLMax_T_4}; // @[CSR.scala:365:47, :371:{82,88}] wire [13:0] _ex_new_vl_atLeastVLMax_T_6 = $signed(-14'sh1000 >>> _ex_new_vl_atLeastVLMax_T_5); // @[CSR.scala:371:{68,82}] wire [13:0] _ex_new_vl_atLeastVLMax_T_7 = _ex_new_vl_atLeastVLMax_T_6; // @[CSR.scala:371:{68,125}] wire [13:0] _ex_new_vl_atLeastVLMax_T_11 = _ex_new_vl_atLeastVLMax_T_7 & 14'h3FF8; // @[package.scala:174:35] wire [13:0] _ex_new_vl_atLeastVLMax_T_12 = {2'h0, _ex_new_vl_atLeastVLMax_T_11[11:0] & ex_new_vl_avl_lsbs}; // @[package.scala:174:35] wire _ex_new_vl_atLeastVLMax_T_13 = \|_ex_new_vl_atLeastVLMax_T_12; // @[CSR.scala:371:{53,156}] wire ex_new_vl_atLeastVLMax = ex_new_vl_atLeastMaxVLMax \| _ex_new_vl_atLeastVLMax_T_13; // @[CSR.scala:368:34, :371:{40,156}] wire _ex_new_vl_T = ~ex_new_vl_isZero; // @[CSR.scala:372:23, :373:9] wire _ex_new_vl_T_1 = _ex_new_vl_T & ex_new_vl_atLeastVLMax; // @[CSR.scala:371:40, :373:{9,17}] wire [1:0] _ex_new_vl_T_2 = ~ex_new_vtype_vlmul_mag; // @[CSR.scala:328:27, :365:71] wire [2:0] _ex_new_vl_T_3 = {ex_new_vtype_vlmul_sign, _ex_new_vl_T_2}; // @[CSR.scala:328:27, :365:{53,71}] wire [3:0] _ex_new_vl_T_4 = _GEN_42 + {1'h0, _ex_new_vl_T_3}; // @[CSR.scala:365:{47,53}] wire [12:0] _ex_new_vl_T_5 = 13'h1000 >> _ex_new_vl_T_4; // @[CSR.scala:365:{33,47}] wire [12:0] _ex_new_vl_T_9 = _ex_new_vl_T_5 & 13'h1FF8; // @[package.scala:174:35] wire [12:0] _ex_new_vl_T_10 = _ex_new_vl_T_1 ? _ex_new_vl_T_9 : 13'h0; // @[package.scala:174:35] wire _ex_new_vl_T_11 = ~ex_new_vl_isZero; // @[CSR.scala:372:23, :373:{9,52}] wire _ex_new_vl_T_12 = ~ex_new_vl_atLeastVLMax; // @[CSR.scala:371:40, :373:63] wire _ex_new_vl_T_13 = _ex_new_vl_T_11 & _ex_new_vl_T_12; // @[CSR.scala:373:{52,60,63}] wire [11:0] _ex_new_vl_T_14 = _ex_new_vl_T_13 ? ex_new_vl_avl_lsbs : 12'h0; // @[CSR.scala:369:53, :373:{51,60}] wire [12:0] ex_new_vl = {_ex_new_vl_T_10[12], _ex_new_vl_T_10[11:0] \| _ex_new_vl_T_14}; // @[CSR.scala:373:{8,46,51}] wire [12:0] ex_new_vconfig_vl = ex_new_vl; // @[RocketCore.scala:498:30] wire _div_io_req_valid_T = ex_reg_valid & ex_ctrl_div; // @[RocketCore.scala:243:20, :248:35, :512:36] wire _ex_reg_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19] wire _ex_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20] wire _ex_reg_replay_T_1 = _ex_reg_replay_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :526:{20,29}] wire _ex_reg_replay_T_2 = _ex_reg_replay_T_1 & _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :526:{29,54}] wire _ex_reg_xcpt_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :527:18] wire _ex_reg_xcpt_T_1 = _ex_reg_xcpt_T & id_xcpt; // @[RocketCore.scala:527:{18,30}, :1278:14] wire _ex_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :528:28] wire _ex_reg_xcpt_interrupt_T_1 = _ex_reg_xcpt_interrupt_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :528:{28,37}] wire _ex_reg_xcpt_interrupt_T_2 = _ex_reg_xcpt_interrupt_T_1 & _csr_io_interrupt; // @[RocketCore.scala:341:19, :528:{37,62}] wire [1:0] hi = {_ibuf_io_inst_0_bits_xcpt1_pf_inst, _ibuf_io_inst_0_bits_xcpt1_gf_inst}; // @[RocketCore.scala:311:20, :541:22] wire [1:0] hi_1 = {_ibuf_io_inst_0_bits_xcpt0_pf_inst, _ibuf_io_inst_0_bits_xcpt0_gf_inst}; // @[RocketCore.scala:311:20, :546:40] wire _ex_reg_flush_pipe_T = id_ctrl_fence_i \| id_csr_flush; // @[RocketCore.scala:321:21, :346:37, :551:42] wire _ex_reg_hls_T_1 = id_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47] wire _ex_reg_hls_T_2 = id_ctrl_mem_cmd == 5'h1; // @[package.scala:16:47] wire _ex_reg_hls_T_3 = id_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47] wire _ex_reg_hls_T_4 = _ex_reg_hls_T_1 \| _ex_reg_hls_T_2; // @[package.scala:16:47, :81:59] wire _ex_reg_hls_T_5 = _ex_reg_hls_T_4 \| _ex_reg_hls_T_3; // @[package.scala:16:47, :81:59] wire [1:0] _ex_reg_mem_size_T_1 = _ibuf_io_inst_0_bits_inst_bits[27:26]; // @[RocketCore.scala:311:20, :554:75] wire [1:0] _ex_reg_mem_size_T_2 = _ibuf_io_inst_0_bits_inst_bits[13:12]; // @[RocketCore.scala:311:20, :554:95] wire [1:0] _ex_reg_mem_size_T_3 = _ex_reg_mem_size_T_2; // @[RocketCore.scala:554:{27,95}] wire _ex_reg_mem_size_T_4 = \|id_raddr2; // @[RocketCore.scala:326:72, :556:40, :1326:41] wire _ex_reg_mem_size_T_5 = \|id_raddr1; // @[RocketCore.scala:326:72, :556:59, :1326:41] wire [1:0] _ex_reg_mem_size_T_6 = {_ex_reg_mem_size_T_4, _ex_reg_mem_size_T_5}; // @[RocketCore.scala:556:{29,40,59}] wire _do_bypass_T = id_bypass_src_0_0 \| id_bypass_src_0_1; // @[RocketCore.scala:461:74, :568:48] wire _do_bypass_T_1 = _do_bypass_T \| id_bypass_src_0_2; // @[RocketCore.scala:461:74, :568:48] wire do_bypass = _do_bypass_T_1 \| id_bypass_src_0_3; // @[RocketCore.scala:461:74, :568:48] wire [1:0] _bypass_src_T = {1'h1, ~id_bypass_src_0_2}; // @[Mux.scala:50:70] wire [1:0] _bypass_src_T_1 = id_bypass_src_0_1 ? 2'h1 : _bypass_src_T; // @[Mux.scala:50:70] wire [1:0] bypass_src = id_bypass_src_0_0 ? 2'h0 : _bypass_src_T_1; // @[Mux.scala:50:70] wire [1:0] _ex_reg_rs_lsb_0_T = id_rs_0[1:0]; // @[RocketCore.scala:573:37, :1325:26] wire [61:0] _ex_reg_rs_msb_0_T = id_rs_0[63:2]; // @[RocketCore.scala:574:38, :1325:26] wire _do_bypass_T_2 = id_bypass_src_1_0 \| id_bypass_src_1_1; // @[RocketCore.scala:461:74, :568:48] wire _do_bypass_T_3 = _do_bypass_T_2 \| id_bypass_src_1_2; // @[RocketCore.scala:461:74, :568:48] wire do_bypass_1 = _do_bypass_T_3 \| id_bypass_src_1_3; // @[RocketCore.scala:461:74, :568:48] wire [1:0] _bypass_src_T_2 = {1'h1, ~id_bypass_src_1_2}; // @[Mux.scala:50:70] wire [1:0] _bypass_src_T_3 = id_bypass_src_1_1 ? 2'h1 : _bypass_src_T_2; // @[Mux.scala:50:70] wire [1:0] bypass_src_1 = id_bypass_src_1_0 ? 2'h0 : _bypass_src_T_3; // @[Mux.scala:50:70] wire [1:0] _ex_reg_rs_lsb_1_T = id_rs_1[1:0]; // @[RocketCore.scala:573:37, :1325:26] wire [61:0] _ex_reg_rs_msb_1_T = id_rs_1[63:2]; // @[RocketCore.scala:574:38, :1325:26] wire [15:0] _inst_T = _ibuf_io_inst_0_bits_raw[15:0]; // @[RocketCore.scala:311:20, :578:62] wire [31:0] inst = _ibuf_io_inst_0_bits_rvc ? {16'h0, _inst_T} : _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20, :578:{21,62}] wire [1:0] _ex_reg_rs_lsb_0_T_1 = inst[1:0]; // @[RocketCore.scala:578:21, :580:31] wire [29:0] _ex_reg_rs_msb_0_T_1 = inst[31:2]; // @[RocketCore.scala:578:21, :581:32] wire _ex_reg_set_vconfig_T = ~id_xcpt; // @[RocketCore.scala:591:45, :1278:14] wire _ex_reg_set_vconfig_T_1 = id_set_vconfig & _ex_reg_set_vconfig_T; // @[RocketCore.scala:347:120, :591:{42,45}] wire _ex_pc_valid_T = ex_reg_valid \| ex_reg_replay; // @[RocketCore.scala:248:35, :255:26, :595:34] wire ex_pc_valid = _ex_pc_valid_T \| ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :595:{34,51}] wire _wb_dcache_miss_T = ~io_dmem_resp_valid_0; // @[RocketCore.scala:153:7, :596:39] wire wb_dcache_miss = wb_ctrl_mem & _wb_dcache_miss_T; // @[RocketCore.scala:245:20, :596:{36,39}] wire _replay_ex_structural_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45] wire _replay_ex_structural_T_1 = ex_ctrl_mem & _replay_ex_structural_T; // @[RocketCore.scala:243:20, :597:{42,45}] wire _replay_ex_structural_T_2 = ~_div_io_req_ready; // @[RocketCore.scala:511:19, :598:45] wire _replay_ex_structural_T_3 = ex_ctrl_div & _replay_ex_structural_T_2; // @[RocketCore.scala:243:20, :598:{42,45}] wire _replay_ex_structural_T_4 = _replay_ex_structural_T_1 \| _replay_ex_structural_T_3; // @[RocketCore.scala:597:{42,64}, :598:42] wire replay_ex_structural = _replay_ex_structural_T_4; // @[RocketCore.scala:597:64, :598:63] wire replay_ex_load_use = wb_dcache_miss & ex_reg_load_use; // @[RocketCore.scala:253:35, :596:36, :600:43] wire _replay_ex_T = replay_ex_structural \| replay_ex_load_use; // @[RocketCore.scala:598:63, :600:43, :601:75] wire _replay_ex_T_1 = ex_reg_valid & _replay_ex_T; // @[RocketCore.scala:248:35, :601:{50,75}] wire replay_ex = ex_reg_replay \| _replay_ex_T_1; // @[RocketCore.scala:255:26, :601:{33,50}] wire _ctrl_killx_T = take_pc_mem_wb \| replay_ex; // @[RocketCore.scala:307:35, :601:33, :602:35] wire _ctrl_killx_T_1 = ~ex_reg_valid; // @[RocketCore.scala:248:35, :602:51] assign ctrl_killx = _ctrl_killx_T \| _ctrl_killx_T_1; // @[RocketCore.scala:602:{35,48,51}] assign io_fpu_killx_0 = ctrl_killx; // @[RocketCore.scala:153:7, :602:48] wire _GEN_43 = ex_ctrl_mem_cmd == 5'h7; // @[RocketCore.scala:243:20, :604:40] wire _ex_slow_bypass_T; // @[RocketCore.scala:604:40] assign _ex_slow_bypass_T = _GEN_43; // @[RocketCore.scala:604:40] wire _mem_reg_load_T_3; // @[package.scala:16:47] assign _mem_reg_load_T_3 = _GEN_43; // @[package.scala:16:47] wire _mem_reg_store_T_3; // @[Consts.scala:90:66] assign _mem_reg_store_T_3 = _GEN_43; // @[RocketCore.scala:604:40] wire _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_3 = _GEN_43; // @[package.scala:16:47] wire _ex_slow_bypass_T_1 = ~(ex_reg_mem_size[1]); // @[RocketCore.scala:257:28, :604:69] wire ex_slow_bypass = _ex_slow_bypass_T \| _ex_slow_bypass_T_1; // @[RocketCore.scala:604:{40,50,69}] wire _ex_sfence_T_1 = ex_ctrl_mem_cmd == 5'h14; // @[RocketCore.scala:243:20, :605:64] wire _ex_sfence_T_2 = ex_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:243:20, :605:96] wire _ex_sfence_T_3 = _ex_sfence_T_1 \| _ex_sfence_T_2; // @[RocketCore.scala:605:{64,77,96}] wire _ex_sfence_T_4 = ex_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:243:20, :605:129] wire _ex_sfence_T_5 = _ex_sfence_T_3 \| _ex_sfence_T_4; // @[RocketCore.scala:605:{77,110,129}] wire ex_sfence = _ex_sfence_T & _ex_sfence_T_5; // @[RocketCore.scala:605:{29,44,110}] wire ex_xcpt = ex_reg_xcpt_interrupt \| ex_reg_xcpt; // @[RocketCore.scala:247:35, :251:35, :608:28, :1278:14] wire _mem_pc_valid_T = mem_reg_valid \| mem_reg_replay; // @[RocketCore.scala:265:36, :269:36, :614:36] wire mem_pc_valid = _mem_pc_valid_T \| mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36, :614:{36,54}] wire _GEN_44 = mem_ctrl_branch & mem_br_taken; // @[RocketCore.scala:244:21, :284:25, :616:25] wire _mem_br_target_T_1; // @[RocketCore.scala:616:25] assign _mem_br_target_T_1 = _GEN_44; // @[RocketCore.scala:616:25] wire _mem_cfi_taken_T; // @[RocketCore.scala:626:40] assign _mem_cfi_taken_T = _GEN_44; // @[RocketCore.scala:616:25, :626:40] wire _mem_br_target_sign_T_1 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44] wire _mem_br_target_sign_T_4 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44] wire _mem_br_target_sign_T_2 = _mem_br_target_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire mem_br_target_sign = _mem_br_target_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire mem_br_target_hi_hi_hi = mem_br_target_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_br_target_b30_20_T_1 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41] wire [10:0] _mem_br_target_b30_20_T_4 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41] wire [10:0] _mem_br_target_b30_20_T_2 = _mem_br_target_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_br_target_b30_20 = {11{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_br_target_hi_hi_lo = mem_br_target_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_br_target_b19_12_T_3 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65] wire [7:0] _mem_br_target_b19_12_T_8 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65] wire [7:0] _mem_br_target_b19_12_T_4 = _mem_br_target_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_br_target_b19_12 = {8{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] mem_br_target_hi_lo_hi = mem_br_target_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_br_target_b11_T_4 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39] wire _mem_br_target_b0_T_3 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37] wire _mem_br_target_b11_T_15 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39] wire _mem_br_target_b0_T_11 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37] wire _mem_br_target_b11_T_5 = _mem_br_target_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _mem_br_target_b11_T_7 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39] wire _mem_br_target_b0_T_1 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37] wire _mem_br_target_b11_T_18 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39] wire _mem_br_target_b0_T_9 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37] wire _mem_br_target_b11_T_8 = _mem_br_target_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _mem_br_target_b11_T_9 = _mem_br_target_b11_T_8; // @[RocketCore.scala:1346:{18,43}] wire _mem_br_target_b11_T_10 = _mem_br_target_b11_T_9; // @[RocketCore.scala:1345:18, :1346:18] wire mem_br_target_b11 = _mem_br_target_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire mem_br_target_hi_lo_lo = mem_br_target_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _mem_br_target_b10_5_T_3 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62] wire [5:0] _mem_br_target_b10_5_T_7 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62] wire [5:0] mem_br_target_b10_5 = _mem_br_target_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_br_target_b4_1_T_4 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57] wire [3:0] _mem_br_target_b4_1_T_14 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57] wire [3:0] _mem_br_target_b4_1_T_9 = _mem_br_target_b4_1_T_4; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _mem_br_target_b4_1_T_6 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39] wire [3:0] _mem_br_target_b4_1_T_16 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39] wire [3:0] _mem_br_target_b4_1_T_7 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52] wire [3:0] _mem_br_target_b4_1_T_17 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52] wire [3:0] _mem_br_target_b4_1_T_8 = _mem_br_target_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] mem_br_target_b4_1 = _mem_br_target_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _mem_br_target_b0_T_5 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37] wire _mem_br_target_b0_T_13 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37] wire [9:0] mem_br_target_lo_hi = {mem_br_target_b10_5, mem_br_target_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_br_target_lo = {mem_br_target_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_br_target_hi_lo = {mem_br_target_hi_lo_hi, mem_br_target_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] mem_br_target_hi_hi = {mem_br_target_hi_hi_hi, mem_br_target_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] mem_br_target_hi = {mem_br_target_hi_hi, mem_br_target_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_2 = {mem_br_target_hi, mem_br_target_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_3 = _mem_br_target_T_2; // @[RocketCore.scala:1355:{8,53}] wire _mem_br_target_sign_T_5 = _mem_br_target_sign_T_4; // @[RocketCore.scala:1341:{44,49}] wire mem_br_target_sign_1 = _mem_br_target_sign_T_5; // @[RocketCore.scala:1341:{19,49}] wire _mem_br_target_b11_T_20 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1346:18] wire mem_br_target_hi_hi_hi_1 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_br_target_b30_20_T_5 = _mem_br_target_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_br_target_b30_20_1 = {11{mem_br_target_sign_1}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_br_target_hi_hi_lo_1 = mem_br_target_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_br_target_b19_12_T_9 = _mem_br_target_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_br_target_b19_12_1 = _mem_br_target_b19_12_T_9; // @[RocketCore.scala:1343:{21,73}] wire [7:0] mem_br_target_hi_lo_hi_1 = mem_br_target_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_br_target_b11_T_16 = _mem_br_target_b11_T_15; // @[RocketCore.scala:1345:{39,44}] wire _mem_br_target_b11_T_21 = _mem_br_target_b11_T_16; // @[RocketCore.scala:1345:{18,44}] wire _mem_br_target_b11_T_19 = _mem_br_target_b11_T_18; // @[RocketCore.scala:1346:{39,43}] wire mem_br_target_b11_1 = _mem_br_target_b11_T_21; // @[RocketCore.scala:1344:18, :1345:18] wire mem_br_target_hi_lo_lo_1 = mem_br_target_b11_1; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] mem_br_target_b10_5_1 = _mem_br_target_b10_5_T_7; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_br_target_b4_1_T_18 = _mem_br_target_b4_1_T_17; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _mem_br_target_b4_1_T_19 = _mem_br_target_b4_1_T_18; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] mem_br_target_b4_1_1 = _mem_br_target_b4_1_T_19; // @[RocketCore.scala:1348:19, :1349:19] wire [9:0] mem_br_target_lo_hi_1 = {mem_br_target_b10_5_1, mem_br_target_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_br_target_lo_1 = {mem_br_target_lo_hi_1, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_br_target_hi_lo_1 = {mem_br_target_hi_lo_hi_1, mem_br_target_hi_lo_lo_1}; // @[RocketCore.scala:1355:8] wire [11:0] mem_br_target_hi_hi_1 = {mem_br_target_hi_hi_hi_1, mem_br_target_hi_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [20:0] mem_br_target_hi_1 = {mem_br_target_hi_hi_1, mem_br_target_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_4 = {mem_br_target_hi_1, mem_br_target_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_5 = _mem_br_target_T_4; // @[RocketCore.scala:1355:{8,53}] wire [3:0] _mem_br_target_T_6 = mem_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:266:36, :618:8] wire [31:0] _mem_br_target_T_7 = mem_ctrl_jal ? _mem_br_target_T_5 : {{28{_mem_br_target_T_6[3]}}, _mem_br_target_T_6}; // @[RocketCore.scala:244:21, :617:8, :618:8, :1355:53] wire [31:0] _mem_br_target_T_8 = _mem_br_target_T_1 ? _mem_br_target_T_3 : _mem_br_target_T_7; // @[RocketCore.scala:616:{8,25}, :617:8, :1355:53] wire [40:0] _mem_br_target_T_9 = {_mem_br_target_T[39], _mem_br_target_T} + {{9{_mem_br_target_T_8[31]}}, _mem_br_target_T_8}; // @[RocketCore.scala:615:{34,41}, :616:8] wire [39:0] _mem_br_target_T_10 = _mem_br_target_T_9[39:0]; // @[RocketCore.scala:615:41] wire [39:0] mem_br_target = _mem_br_target_T_10; // @[RocketCore.scala:615:41] wire _mem_npc_T = mem_ctrl_jalr \| mem_reg_sfence; // @[RocketCore.scala:244:21, :276:27, :619:36] wire [24:0] _mem_npc_a_T = mem_reg_wdata[63:39]; // @[RocketCore.scala:282:26, :1293:17] wire [24:0] mem_npc_a = _mem_npc_a_T; // @[RocketCore.scala:1293:{17,23}] wire _mem_npc_msb_T = mem_npc_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _mem_npc_msb_T_1 = &mem_npc_a; // @[RocketCore.scala:1293:23, :1294:34] wire _mem_npc_msb_T_2 = _mem_npc_msb_T \| _mem_npc_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _mem_npc_msb_T_3 = mem_reg_wdata[39]; // @[RocketCore.scala:282:26, :1294:46] wire _mem_npc_msb_T_4 = mem_reg_wdata[38]; // @[RocketCore.scala:282:26, :1294:54] wire _mem_npc_msb_T_5 = ~_mem_npc_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire mem_npc_msb = _mem_npc_msb_T_2 ? _mem_npc_msb_T_3 : _mem_npc_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] wire [39:0] _mem_npc_T_2 = {mem_npc_msb, _mem_npc_T_1}; // @[RocketCore.scala:1294:18, :1295:{8,16}] wire [39:0] _mem_npc_T_3 = _mem_npc_T_2; // @[RocketCore.scala:619:106, :1295:8] wire [39:0] _mem_npc_T_4 = _mem_npc_T ? _mem_npc_T_3 : mem_br_target; // @[RocketCore.scala:615:41, :619:{21,36,106}] wire [39:0] _mem_npc_T_5 = _mem_npc_T_4 & 40'hFFFFFFFFFE; // @[RocketCore.scala:619:{21,129}] wire [39:0] _mem_npc_T_6 = _mem_npc_T_5; // @[RocketCore.scala:619:129] wire [39:0] mem_npc = _mem_npc_T_6; // @[RocketCore.scala:619:{129,139}] wire _mem_wrong_npc_T = mem_npc != ex_reg_pc; // @[RocketCore.scala:256:22, :619:139, :621:30] wire _mem_wrong_npc_T_1 = _ibuf_io_inst_0_valid \| io_imem_resp_valid_0; // @[RocketCore.scala:153:7, :311:20, :622:31] wire _mem_wrong_npc_T_2 = mem_npc != _ibuf_io_pc; // @[RocketCore.scala:311:20, :619:139, :622:62] wire _mem_wrong_npc_T_3 = ~_mem_wrong_npc_T_1 \| _mem_wrong_npc_T_2; // @[RocketCore.scala:622:{8,31,62}] assign mem_wrong_npc = ex_pc_valid ? _mem_wrong_npc_T : _mem_wrong_npc_T_3; // @[RocketCore.scala:595:51, :621:{8,30}, :622:8] assign io_imem_bht_update_bits_mispredict_0 = mem_wrong_npc; // @[RocketCore.scala:153:7, :621:8] wire _mem_npc_misaligned_T_1 = ~_mem_npc_misaligned_T; // @[RocketCore.scala:623:{28,46}] wire _mem_npc_misaligned_T_2 = mem_npc[1]; // @[RocketCore.scala:619:139, :623:66] wire _mem_npc_misaligned_T_3 = _mem_npc_misaligned_T_1 & _mem_npc_misaligned_T_2; // @[RocketCore.scala:623:{28,56,66}] wire _mem_npc_misaligned_T_4 = ~mem_reg_sfence; // @[RocketCore.scala:276:27, :623:73] wire mem_npc_misaligned = _mem_npc_misaligned_T_3 & _mem_npc_misaligned_T_4; // @[RocketCore.scala:623:{56,70,73}] wire _mem_int_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27] wire _mem_int_wdata_T_1 = mem_ctrl_jalr ^ mem_npc_misaligned; // @[RocketCore.scala:244:21, :623:70, :624:59] wire _mem_int_wdata_T_2 = _mem_int_wdata_T & _mem_int_wdata_T_1; // @[RocketCore.scala:624:{27,41,59}] wire [63:0] _mem_int_wdata_T_4 = _mem_int_wdata_T_2 ? {{24{mem_br_target[39]}}, mem_br_target} : _mem_int_wdata_T_3; // @[RocketCore.scala:615:41, :624:{26,41,111}] wire [63:0] mem_int_wdata = _mem_int_wdata_T_4; // @[RocketCore.scala:624:{26,119}] wire _mem_cfi_T = mem_ctrl_branch \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :625:33] assign mem_cfi = _mem_cfi_T \| mem_ctrl_jal; // @[RocketCore.scala:244:21, :625:{33,50}] assign io_imem_btb_update_bits_isValid_0 = mem_cfi; // @[RocketCore.scala:153:7, :625:50] wire _mem_cfi_taken_T_1 = _mem_cfi_taken_T \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :626:{40,57}] wire mem_cfi_taken = _mem_cfi_taken_T_1 \| mem_ctrl_jal; // @[RocketCore.scala:244:21, :626:{57,74}] wire _mem_direction_misprediction_T_1 = mem_br_taken != _mem_direction_misprediction_T; // @[RocketCore.scala:284:25, :627:{69,85}] wire mem_direction_misprediction = mem_ctrl_branch & _mem_direction_misprediction_T_1; // @[RocketCore.scala:244:21, :627:{53,69}] wire _take_pc_mem_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :629:35] wire _take_pc_mem_T_1 = mem_reg_valid & _take_pc_mem_T; // @[RocketCore.scala:265:36, :629:{32,35}] wire _take_pc_mem_T_2 = mem_wrong_npc \| mem_reg_sfence; // @[RocketCore.scala:276:27, :621:8, :629:71] assign _take_pc_mem_T_3 = _take_pc_mem_T_1 & _take_pc_mem_T_2; // @[RocketCore.scala:629:{32,49,71}] assign take_pc_mem = _take_pc_mem_T_3; // @[RocketCore.scala:285:25, :629:49] wire _mem_reg_valid_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20] wire _mem_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :632:21] wire _mem_reg_replay_T_1 = _mem_reg_replay_T & replay_ex; // @[RocketCore.scala:601:33, :632:{21,37}] wire _mem_reg_xcpt_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20, :633:19] wire _mem_reg_xcpt_T_1 = _mem_reg_xcpt_T & ex_xcpt; // @[RocketCore.scala:633:{19,31}, :1278:14] wire _mem_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :634:29] wire _mem_reg_xcpt_interrupt_T_1 = _mem_reg_xcpt_interrupt_T & ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :634:{29,45}] wire _GEN_45 = ex_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47] wire _mem_reg_load_T; // @[package.scala:16:47] assign _mem_reg_load_T = _GEN_45; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = ex_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47] wire _mem_reg_load_T_1; // @[package.scala:16:47] assign _mem_reg_load_T_1 = _GEN_46; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_1 = _GEN_46; // @[package.scala:16:47] wire _GEN_47 = ex_ctrl_mem_cmd == 5'h6; // @[package.scala:16:47] wire _mem_reg_load_T_2; // @[package.scala:16:47] assign _mem_reg_load_T_2 = _GEN_47; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_2 = _GEN_47; // @[package.scala:16:47] wire _mem_reg_load_T_4 = _mem_reg_load_T \| _mem_reg_load_T_1; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_5 = _mem_reg_load_T_4 \| _mem_reg_load_T_2; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_6 = _mem_reg_load_T_5 \| _mem_reg_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_48 = ex_ctrl_mem_cmd == 5'h4; // @[package.scala:16:47] wire _mem_reg_load_T_7; // @[package.scala:16:47] assign _mem_reg_load_T_7 = _GEN_48; // @[package.scala:16:47] wire _mem_reg_store_T_5; // @[package.scala:16:47] assign _mem_reg_store_T_5 = _GEN_48; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_7; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_7 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = ex_ctrl_mem_cmd == 5'h9; // @[package.scala:16:47] wire _mem_reg_load_T_8; // @[package.scala:16:47] assign _mem_reg_load_T_8 = _GEN_49; // @[package.scala:16:47] wire _mem_reg_store_T_6; // @[package.scala:16:47] assign _mem_reg_store_T_6 = _GEN_49; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_8 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = ex_ctrl_mem_cmd == 5'hA; // @[package.scala:16:47] wire _mem_reg_load_T_9; // @[package.scala:16:47] assign _mem_reg_load_T_9 = _GEN_50; // @[package.scala:16:47] wire _mem_reg_store_T_7; // @[package.scala:16:47] assign _mem_reg_store_T_7 = _GEN_50; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_9 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = ex_ctrl_mem_cmd == 5'hB; // @[package.scala:16:47] wire _mem_reg_load_T_10; // @[package.scala:16:47] assign _mem_reg_load_T_10 = _GEN_51; // @[package.scala:16:47] wire _mem_reg_store_T_8; // @[package.scala:16:47] assign _mem_reg_store_T_8 = _GEN_51; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_10 = _GEN_51; // @[package.scala:16:47] wire _mem_reg_load_T_11 = _mem_reg_load_T_7 \| _mem_reg_load_T_8; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_12 = _mem_reg_load_T_11 \| _mem_reg_load_T_9; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_13 = _mem_reg_load_T_12 \| _mem_reg_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_52 = ex_ctrl_mem_cmd == 5'h8; // @[package.scala:16:47] wire _mem_reg_load_T_14; // @[package.scala:16:47] assign _mem_reg_load_T_14 = _GEN_52; // @[package.scala:16:47] wire _mem_reg_store_T_12; // @[package.scala:16:47] assign _mem_reg_store_T_12 = _GEN_52; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_14; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_14 = _GEN_52; // @[package.scala:16:47] wire _GEN_53 = ex_ctrl_mem_cmd == 5'hC; // @[package.scala:16:47] wire _mem_reg_load_T_15; // @[package.scala:16:47] assign _mem_reg_load_T_15 = _GEN_53; // @[package.scala:16:47] wire _mem_reg_store_T_13; // @[package.scala:16:47] assign _mem_reg_store_T_13 = _GEN_53; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_15 = _GEN_53; // @[package.scala:16:47] wire _GEN_54 = ex_ctrl_mem_cmd == 5'hD; // @[package.scala:16:47] wire _mem_reg_load_T_16; // @[package.scala:16:47] assign _mem_reg_load_T_16 = _GEN_54; // @[package.scala:16:47] wire _mem_reg_store_T_14; // @[package.scala:16:47] assign _mem_reg_store_T_14 = _GEN_54; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_16 = _GEN_54; // @[package.scala:16:47] wire _GEN_55 = ex_ctrl_mem_cmd == 5'hE; // @[package.scala:16:47] wire _mem_reg_load_T_17; // @[package.scala:16:47] assign _mem_reg_load_T_17 = _GEN_55; // @[package.scala:16:47] wire _mem_reg_store_T_15; // @[package.scala:16:47] assign _mem_reg_store_T_15 = _GEN_55; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_17 = _GEN_55; // @[package.scala:16:47] wire _GEN_56 = ex_ctrl_mem_cmd == 5'hF; // @[package.scala:16:47] wire _mem_reg_load_T_18; // @[package.scala:16:47] assign _mem_reg_load_T_18 = _GEN_56; // @[package.scala:16:47] wire _mem_reg_store_T_16; // @[package.scala:16:47] assign _mem_reg_store_T_16 = _GEN_56; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_18 = _GEN_56; // @[package.scala:16:47] wire _mem_reg_load_T_19 = _mem_reg_load_T_14 \| _mem_reg_load_T_15; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_20 = _mem_reg_load_T_19 \| _mem_reg_load_T_16; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_21 = _mem_reg_load_T_20 \| _mem_reg_load_T_17; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_22 = _mem_reg_load_T_21 \| _mem_reg_load_T_18; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_23 = _mem_reg_load_T_13 \| _mem_reg_load_T_22; // @[package.scala:81:59] wire _mem_reg_load_T_24 = _mem_reg_load_T_6 \| _mem_reg_load_T_23; // @[package.scala:81:59] wire _mem_reg_load_T_25 = ex_ctrl_mem & _mem_reg_load_T_24; // @[RocketCore.scala:243:20, :643:33] wire _mem_reg_store_T = ex_ctrl_mem_cmd == 5'h1; // @[RocketCore.scala:243:20] wire _mem_reg_store_T_1 = ex_ctrl_mem_cmd == 5'h11; // @[RocketCore.scala:243:20] wire _mem_reg_store_T_2 = _mem_reg_store_T \| _mem_reg_store_T_1; // @[Consts.scala:90:{32,42,49}] wire _mem_reg_store_T_4 = _mem_reg_store_T_2 \| _mem_reg_store_T_3; // @[Consts.scala:90:{42,59,66}] wire _mem_reg_store_T_9 = _mem_reg_store_T_5 \| _mem_reg_store_T_6; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_10 = _mem_reg_store_T_9 \| _mem_reg_store_T_7; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_11 = _mem_reg_store_T_10 \| _mem_reg_store_T_8; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_17 = _mem_reg_store_T_12 \| _mem_reg_store_T_13; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_18 = _mem_reg_store_T_17 \| _mem_reg_store_T_14; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_19 = _mem_reg_store_T_18 \| _mem_reg_store_T_15; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_20 = _mem_reg_store_T_19 \| _mem_reg_store_T_16; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_21 = _mem_reg_store_T_11 \| _mem_reg_store_T_20; // @[package.scala:81:59] wire _mem_reg_store_T_22 = _mem_reg_store_T_4 \| _mem_reg_store_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _mem_reg_store_T_23 = ex_ctrl_mem & _mem_reg_store_T_22; // @[RocketCore.scala:243:20, :644:34] wire [63:0] _mem_reg_wdata_T = ex_reg_set_vconfig ? {51'h0, ex_new_vl} : _alu_io_out; // @[RocketCore.scala:262:36, :504:19, :659:25] wire [1:0] size = ex_ctrl_rocc ? 2'h3 : ex_reg_mem_size; // @[RocketCore.scala:243:20, :257:28, :664:21] wire [1:0] mem_reg_rs2_size = size; // @[RocketCore.scala:664:21] wire _mem_reg_rs2_T = mem_reg_rs2_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _mem_reg_rs2_T_1 = mem_reg_rs2_dat_padded[7:0]; // @[AMOALU.scala:13:27, :29:69] wire [15:0] _mem_reg_rs2_T_2 = {2{_mem_reg_rs2_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _mem_reg_rs2_T_3 = {2{_mem_reg_rs2_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _mem_reg_rs2_T_4 = {2{_mem_reg_rs2_T_3}}; // @[AMOALU.scala:29:32] wire _mem_reg_rs2_T_5 = mem_reg_rs2_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _mem_reg_rs2_T_6 = mem_reg_rs2_dat_padded[15:0]; // @[AMOALU.scala:13:27, :29:69] wire [31:0] _mem_reg_rs2_T_7 = {2{_mem_reg_rs2_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_reg_rs2_T_8 = {2{_mem_reg_rs2_T_7}}; // @[AMOALU.scala:29:32] wire _mem_reg_rs2_T_9 = mem_reg_rs2_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _mem_reg_rs2_T_10 = mem_reg_rs2_dat_padded[31:0]; // @[AMOALU.scala:13:27, :29:69] wire [63:0] _mem_reg_rs2_T_11 = {2{_mem_reg_rs2_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_reg_rs2_T_12 = _mem_reg_rs2_T_9 ? _mem_reg_rs2_T_11 : mem_reg_rs2_dat_padded; // @[AMOALU.scala:13:27, :29:{13,19,32}] wire [63:0] _mem_reg_rs2_T_13 = _mem_reg_rs2_T_5 ? _mem_reg_rs2_T_8 : _mem_reg_rs2_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _mem_reg_rs2_T_14 = _mem_reg_rs2_T ? _mem_reg_rs2_T_4 : _mem_reg_rs2_T_13; // @[AMOALU.scala:29:{13,19,32}] wire [3:0] mem_reg_rs2_lo_hi = {ex_new_vconfig_vtype_vsew, ex_new_vconfig_vtype_vlmul_sign}; // @[RocketCore.scala:498:30, :668:41] wire [5:0] mem_reg_rs2_lo = {mem_reg_rs2_lo_hi, ex_new_vconfig_vtype_vlmul_mag}; // @[RocketCore.scala:498:30, :668:41] wire [1:0] mem_reg_rs2_hi_lo = {ex_new_vconfig_vtype_vma, ex_new_vconfig_vtype_vta}; // @[RocketCore.scala:498:30, :668:41] wire [55:0] mem_reg_rs2_hi_hi = {ex_new_vconfig_vtype_vill, 55'h0}; // @[RocketCore.scala:498:30, :668:41] wire [57:0] mem_reg_rs2_hi = {mem_reg_rs2_hi_hi, mem_reg_rs2_hi_lo}; // @[RocketCore.scala:668:41] wire [63:0] _mem_reg_rs2_T_15 = {mem_reg_rs2_hi, mem_reg_rs2_lo}; // @[RocketCore.scala:668:41] wire [76:0] _mem_reg_rs2_T_16 = {ex_new_vconfig_vl, _mem_reg_rs2_T_15}; // @[RocketCore.scala:498:30, :668:41] wire _mem_breakpoint_T = mem_reg_load & _bpu_io_xcpt_ld; // @[RocketCore.scala:273:36, :414:19, :677:38] wire _mem_breakpoint_T_1 = mem_reg_store & _bpu_io_xcpt_st; // @[RocketCore.scala:274:36, :414:19, :677:75] wire mem_breakpoint = _mem_breakpoint_T \| _mem_breakpoint_T_1; // @[RocketCore.scala:677:{38,57,75}] wire _mem_debug_breakpoint_T = mem_reg_load & _bpu_io_debug_ld; // @[RocketCore.scala:273:36, :414:19, :678:44] wire _mem_debug_breakpoint_T_1 = mem_reg_store & _bpu_io_debug_st; // @[RocketCore.scala:274:36, :414:19, :678:82] wire mem_debug_breakpoint = _mem_debug_breakpoint_T \| _mem_debug_breakpoint_T_1; // @[RocketCore.scala:678:{44,64,82}] wire mem_ldst_xcpt = mem_debug_breakpoint \| mem_breakpoint; // @[RocketCore.scala:677:57, :678:64, :1278:{14,35}] wire [3:0] mem_ldst_cause = mem_debug_breakpoint ? 4'hE : 4'h3; // @[Mux.scala:50:70] wire _T_74 = mem_reg_xcpt_interrupt \| mem_reg_xcpt; // @[RocketCore.scala:264:36, :268:36, :684:29] wire _T_75 = mem_reg_valid & mem_npc_misaligned; // @[RocketCore.scala:265:36, :623:70, :685:20] wire mem_xcpt = _T_74 \| _T_75 \| mem_reg_valid & mem_ldst_xcpt; // @[RocketCore.scala:265:36, :684:29, :685:20, :686:20, :1278:{14,35}] wire [63:0] mem_cause = _T_74 ? mem_reg_cause : {60'h0, _T_75 ? 4'h0 : mem_ldst_cause}; // @[Mux.scala:50:70] wire dcache_kill_mem = _dcache_kill_mem_T & io_dmem_replay_next_0; // @[RocketCore.scala:153:7, :695:{39,55}] wire _fpu_kill_mem_T = mem_reg_valid & mem_ctrl_fp; // @[RocketCore.scala:244:21, :265:36, :696:36] wire fpu_kill_mem = _fpu_kill_mem_T & io_fpu_nack_mem_0; // @[RocketCore.scala:153:7, :696:{36,51}] wire _vec_kill_mem_T = mem_reg_valid & mem_ctrl_mem; // @[RocketCore.scala:244:21, :265:36, :697:36] wire vec_kill_mem = _vec_kill_mem_T & io_vector_mem_block_mem_0; // @[RocketCore.scala:153:7, :697:{36,52}] wire _replay_mem_T = dcache_kill_mem \| mem_reg_replay; // @[RocketCore.scala:269:36, :695:55, :699:37] wire _replay_mem_T_1 = _replay_mem_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :699:{37,55}] wire _replay_mem_T_2 = _replay_mem_T_1 \| vec_kill_mem; // @[RocketCore.scala:697:52, :699:{55,71}] wire replay_mem = _replay_mem_T_2; // @[RocketCore.scala:699:{71,87}] wire _killm_common_T = dcache_kill_mem \| take_pc_wb; // @[RocketCore.scala:304:24, :695:55, :700:38] wire _killm_common_T_1 = _killm_common_T \| mem_reg_xcpt; // @[RocketCore.scala:268:36, :700:{38,52}] wire _killm_common_T_2 = ~mem_reg_valid; // @[RocketCore.scala:265:36, :700:71] assign killm_common = _killm_common_T_1 \| _killm_common_T_2; // @[RocketCore.scala:700:{52,68,71}] assign io_fpu_killm_0 = killm_common; // @[RocketCore.scala:153:7, :700:68] assign io_vector_killm_0 = killm_common; // @[RocketCore.scala:153:7, :700:68] wire _div_io_kill_T = _div_io_req_ready & _div_io_req_valid_T; // @[Decoupled.scala:51:35] reg div_io_kill_REG; // @[RocketCore.scala:701:41] wire _div_io_kill_T_1 = killm_common & div_io_kill_REG; // @[RocketCore.scala:700:68, :701:{31,41}] wire _ctrl_killm_T = killm_common \| mem_xcpt; // @[RocketCore.scala:700:68, :702:33, :1278:14] wire _ctrl_killm_T_1 = _ctrl_killm_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :702:{33,45}] wire ctrl_killm = _ctrl_killm_T_1 \| vec_kill_mem; // @[RocketCore.scala:697:52, :702:{45,61}] wire _wb_reg_valid_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19] wire _wb_reg_replay_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34] wire _wb_reg_replay_T_1 = replay_mem & _wb_reg_replay_T; // @[RocketCore.scala:699:87, :706:{31,34}] wire _wb_reg_xcpt_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :707:30] wire _wb_reg_xcpt_T_1 = mem_xcpt & _wb_reg_xcpt_T; // @[RocketCore.scala:707:{27,30}, :1278:14] wire _wb_reg_xcpt_T_3 = _wb_reg_xcpt_T_1; // @[RocketCore.scala:707:{27,42}] wire _wb_reg_flush_pipe_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19, :708:24] wire _wb_reg_flush_pipe_T_1 = _wb_reg_flush_pipe_T & mem_reg_flush_pipe; // @[RocketCore.scala:270:36, :708:{24,36}] wire _wb_reg_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :712:25] wire _wb_reg_wdata_T_1 = _wb_reg_wdata_T & mem_ctrl_fp; // @[RocketCore.scala:244:21, :712:{25,39}] wire _wb_reg_wdata_T_2 = _wb_reg_wdata_T_1 & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :712:{39,54}] wire [63:0] _wb_reg_wdata_T_3 = _wb_reg_wdata_T_2 ? io_fpu_toint_data_0 : mem_int_wdata; // @[RocketCore.scala:153:7, :624:119, :712:{24,54}] wire _wb_reg_hfence_v_T = mem_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:244:21, :721:41] wire _wb_reg_hfence_g_T = mem_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:244:21, :722:41] wire _T_113 = wb_reg_valid & wb_ctrl_mem; // @[RocketCore.scala:245:20, :288:35, :730:19] wire _T_100 = _T_113 & io_dmem_s2_xcpt_pf_st_0; // @[RocketCore.scala:153:7, :730:{19,34}] wire _T_102 = _T_113 & io_dmem_s2_xcpt_pf_ld_0; // @[RocketCore.scala:153:7, :730:19, :731:34] wire _T_108 = _T_113 & io_dmem_s2_xcpt_ae_st_0; // @[RocketCore.scala:153:7, :730:19, :734:34] wire _T_110 = _T_113 & io_dmem_s2_xcpt_ae_ld_0; // @[RocketCore.scala:153:7, :730:19, :735:34] wire _T_112 = _T_113 & io_dmem_s2_xcpt_ma_st_0; // @[RocketCore.scala:153:7, :730:19, :736:34] wire wb_xcpt = wb_reg_xcpt \| _T_100 \| _T_102 \| _T_108 \| _T_110 \| _T_112 \| _T_113 & io_dmem_s2_xcpt_ma_ld_0; // @[RocketCore.scala:153:7, :289:35, :730:{19,34}, :731:34, :734:34, :735:34, :736:34, :737:34, :1278:{14,35}] wire [63:0] wb_cause = wb_reg_xcpt ? wb_reg_cause : {59'h0, _T_100 ? 5'hF : _T_102 ? 5'hD : {2'h0, _T_108 ? 3'h7 : _T_110 ? 3'h5 : {1'h1, _T_112, 1'h0}}}; // @[Mux.scala:50:70] wire _wb_pc_valid_T = wb_reg_valid \| wb_reg_replay; // @[RocketCore.scala:288:35, :290:35, :754:34] wire wb_pc_valid = _wb_pc_valid_T \| wb_reg_xcpt; // @[RocketCore.scala:289:35, :754:{34,51}] wire wb_wxd = wb_reg_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :288:35, :755:29] wire _wb_set_sboard_T = wb_ctrl_div \| wb_dcache_miss; // @[RocketCore.scala:245:20, :596:36, :756:35] wire _wb_set_sboard_T_1 = _wb_set_sboard_T \| wb_ctrl_rocc; // @[RocketCore.scala:245:20, :756:{35,53}] wire wb_set_sboard = _wb_set_sboard_T_1 \| wb_ctrl_vec; // @[RocketCore.scala:245:20, :756:{53,69}] wire replay_wb_common = io_dmem_s2_nack_0 \| wb_reg_replay; // @[RocketCore.scala:153:7, :290:35, :757:42] wire replay_wb_rocc = _replay_wb_rocc_T; // @[RocketCore.scala:758:{37,53}] wire replay_wb_vec = wb_reg_valid & io_vector_wb_replay_0; // @[RocketCore.scala:153:7, :288:35, :760:36] wire _replay_wb_T = replay_wb_common \| replay_wb_rocc; // @[RocketCore.scala:757:42, :758:53, :761:36] wire _replay_wb_T_1 = _replay_wb_T; // @[RocketCore.scala:761:{36,54}] wire replay_wb = _replay_wb_T_1 \| replay_wb_vec; // @[RocketCore.scala:760:36, :761:{54,71}] wire _take_pc_wb_T = replay_wb \| wb_xcpt; // @[RocketCore.scala:761:71, :762:27, :1278:14] wire _take_pc_wb_T_1 = _take_pc_wb_T \| _csr_io_eret; // @[RocketCore.scala:341:19, :762:{27,38}] assign _take_pc_wb_T_2 = _take_pc_wb_T_1 \| wb_reg_flush_pipe; // @[RocketCore.scala:291:35, :762:{38,53}] assign take_pc_wb = _take_pc_wb_T_2; // @[RocketCore.scala:304:24, :762:53] wire _dmem_resp_xpu_T = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45] wire dmem_resp_fpu = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45, :766:45] wire dmem_resp_xpu = ~_dmem_resp_xpu_T; // @[RocketCore.scala:765:{23,45}] wire [4:0] dmem_resp_waddr = io_dmem_resp_bits_tag_0[5:1]; // @[RocketCore.scala:153:7, :767:46] wire dmem_resp_valid = io_dmem_resp_valid_0 & io_dmem_resp_bits_has_data_0; // @[RocketCore.scala:153:7, :768:44] wire dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay_0; // @[RocketCore.scala:153:7, :768:44, :769:42] wire [63:0] ll_wdata; // @[RocketCore.scala:779:26] wire [4:0] ll_waddr; // @[RocketCore.scala:780:26] wire _ll_wen_T = ll_arb_io_out_ready & _ll_arb_io_out_valid; // @[Decoupled.scala:51:35] wire ll_wen; // @[RocketCore.scala:781:24] wire _ll_arb_io_out_ready_T = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26] wire _T_168 = dmem_resp_valid & dmem_resp_fpu; // @[RocketCore.scala:766:45, :768:44, :801:59] wire _io_vector_resp_ready_T; // @[RocketCore.scala:801:59] assign _io_vector_resp_ready_T = _T_168; // @[RocketCore.scala:801:59] wire _io_fpu_ll_resp_val_T; // @[RocketCore.scala:1099:41] assign _io_fpu_ll_resp_val_T = _T_168; // @[RocketCore.scala:801:59, :1099:41] wire _io_vector_resp_ready_T_1 = ~_io_vector_resp_ready_T; // @[RocketCore.scala:801:{41,59}] assign _io_vector_resp_ready_T_2 = io_vector_resp_bits_fp_0 ? _io_vector_resp_ready_T_1 : _ll_arb_io_in_2_ready; // @[RocketCore.scala:153:7, :776:22, :801:{24,41}] assign io_vector_resp_ready_0 = _io_vector_resp_ready_T_2; // @[RocketCore.scala:153:7, :801:24] wire _ll_arb_io_in_2_valid_T = ~io_vector_resp_bits_fp_0; // @[RocketCore.scala:153:7, :802:46] wire _ll_arb_io_in_2_valid_T_1 = io_vector_resp_valid_0 & _ll_arb_io_in_2_valid_T; // @[RocketCore.scala:153:7, :802:{43,46}] wire _T_143 = dmem_resp_replay & dmem_resp_xpu; // @[RocketCore.scala:765:23, :769:42, :809:26] assign ll_arb_io_out_ready = ~_T_143 & _ll_arb_io_out_ready_T; // @[RocketCore.scala:782:{23,26}, :809:{26,44}, :810:25] assign ll_waddr = _T_143 ? dmem_resp_waddr : _ll_arb_io_out_bits_tag; // @[RocketCore.scala:767:46, :776:22, :780:26, :809:{26,44}, :811:14] assign ll_wen = _T_143 \| _ll_wen_T; // @[Decoupled.scala:51:35] wire _wb_valid_T = ~replay_wb; // @[RocketCore.scala:761:71, :815:34] wire _wb_valid_T_1 = wb_reg_valid & _wb_valid_T; // @[RocketCore.scala:288:35, :815:{31,34}] wire _wb_valid_T_2 = ~wb_xcpt; // @[RocketCore.scala:815:48, :1278:14] wire wb_valid = _wb_valid_T_1 & _wb_valid_T_2; // @[RocketCore.scala:815:{31,45,48}] wire wb_wen = wb_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :815:45, :816:25] wire rf_wen = wb_wen \| ll_wen; // @[RocketCore.scala:781:24, :816:25, :817:23] wire [4:0] rf_waddr = ll_wen ? ll_waddr : wb_waddr; // @[RocketCore.scala:455:36, :780:26, :781:24, :818:21] wire [4:0] xrfWriteBundle_wrdst = rf_waddr; // @[RocketCore.scala:818:21, :1249:28] wire _rf_wdata_T = dmem_resp_valid & dmem_resp_xpu; // @[RocketCore.scala:765:23, :768:44, :819:38] wire _rf_wdata_T_2 = \|wb_ctrl_csr; // @[RocketCore.scala:245:20, :821:34] wire [63:0] _rf_wdata_T_4 = _rf_wdata_T_2 ? _csr_io_rw_rdata : _rf_wdata_T_3; // @[RocketCore.scala:341:19, :821:{21,34}, :822:21] wire [63:0] _rf_wdata_T_5 = ll_wen ? ll_wdata : _rf_wdata_T_4; // @[RocketCore.scala:779:26, :781:24, :820:21, :821:21] wire [63:0] rf_wdata = _rf_wdata_T ? _rf_wdata_T_1 : _rf_wdata_T_5; // @[RocketCore.scala:819:{21,38,78}, :820:21] wire [63:0] coreMonitorBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1186:31] wire [63:0] xrfWriteBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1249:28] wire [63:0] _id_rs_T_4; // @[RocketCore.scala:1326:25] assign id_rs_0 = rf_wen & (\|rf_waddr) & rf_waddr == id_raddr1 ? rf_wdata : _id_rs_T_4; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}] wire [63:0] _id_rs_T_9; // @[RocketCore.scala:1326:25] assign id_rs_1 = rf_wen & (\|rf_waddr) & rf_waddr == id_raddr2 ? rf_wdata : _id_rs_T_9; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}] wire [1:0] _csr_io_inst_0_T = wb_reg_raw_inst[1:0]; // @[RocketCore.scala:301:28, :832:66] wire _csr_io_inst_0_T_1 = &_csr_io_inst_0_T; // @[RocketCore.scala:832:{66,73}] wire [15:0] _csr_io_inst_0_T_2 = wb_reg_inst[31:16]; // @[RocketCore.scala:300:24, :832:91] wire [15:0] _csr_io_inst_0_T_3 = _csr_io_inst_0_T_1 ? _csr_io_inst_0_T_2 : 16'h0; // @[RocketCore.scala:832:{50,73,91}] wire [15:0] _csr_io_inst_0_T_4 = wb_reg_raw_inst[15:0]; // @[RocketCore.scala:301:28, :832:119] wire [31:0] _csr_io_inst_0_T_5 = {_csr_io_inst_0_T_3, _csr_io_inst_0_T_4}; // @[RocketCore.scala:832:{46,50,119}] wire _csr_io_fcsr_flags_valid_T = io_fpu_fcsr_flags_valid_0 \| io_vector_set_fflags_valid_0; // @[RocketCore.scala:153:7, :838:54] wire [4:0] _csr_io_fcsr_flags_bits_T = {5{io_fpu_fcsr_flags_valid_0}}; // @[RocketCore.scala:153:7, :839:59] wire [4:0] _csr_io_fcsr_flags_bits_T_1 = io_fpu_fcsr_flags_bits_0 & _csr_io_fcsr_flags_bits_T; // @[RocketCore.scala:153:7, :839:{53,59}] wire [4:0] _csr_io_fcsr_flags_bits_T_2 = {5{io_vector_set_fflags_valid_0}}; // @[RocketCore.scala:153:7, :839:116] wire [4:0] _csr_io_fcsr_flags_bits_T_3 = io_vector_set_fflags_bits_0 & _csr_io_fcsr_flags_bits_T_2; // @[RocketCore.scala:153:7, :839:{110,116}] wire [4:0] _csr_io_fcsr_flags_bits_T_4 = _csr_io_fcsr_flags_bits_T_1 \| _csr_io_fcsr_flags_bits_T_3; // @[RocketCore.scala:839:{53,89,110}] wire [31:0] _io_fpu_time_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29] wire [31:0] _coreMonitorBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1191:41] wire [31:0] _xrfWriteBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1254:38] assign io_fpu_time_0 = {32'h0, _io_fpu_time_T}; // @[RocketCore.scala:153:7, :840:{15,29}] wire tval_dmem_addr = ~wb_reg_xcpt; // @[RocketCore.scala:289:35, :845:24] wire _tval_any_addr_T = wb_reg_cause == 64'h3; // @[package.scala:16:47] wire _tval_any_addr_T_1 = wb_reg_cause == 64'h1; // @[package.scala:16:47] wire _tval_any_addr_T_2 = wb_reg_cause == 64'hC; // @[package.scala:16:47] wire _GEN_57 = wb_reg_cause == 64'h14; // @[package.scala:16:47] wire _tval_any_addr_T_3; // @[package.scala:16:47] assign _tval_any_addr_T_3 = _GEN_57; // @[package.scala:16:47] wire _htval_valid_imem_T; // @[RocketCore.scala:853:56] assign _htval_valid_imem_T = _GEN_57; // @[package.scala:16:47] wire _tval_any_addr_T_4 = _tval_any_addr_T \| _tval_any_addr_T_1; // @[package.scala:16:47, :81:59] wire _tval_any_addr_T_5 = _tval_any_addr_T_4 \| _tval_any_addr_T_2; // @[package.scala:16:47, :81:59] wire _tval_any_addr_T_6 = _tval_any_addr_T_5 \| _tval_any_addr_T_3; // @[package.scala:16:47, :81:59] wire tval_any_addr = tval_dmem_addr \| _tval_any_addr_T_6; // @[package.scala:81:59] wire tval_inst = wb_reg_cause == 64'h2; // @[RocketCore.scala:292:35, :848:32] wire _tval_valid_T = tval_any_addr \| tval_inst; // @[RocketCore.scala:846:38, :848:32, :849:46] wire tval_valid = wb_xcpt & _tval_valid_T; // @[RocketCore.scala:849:{28,46}, :1278:14] wire _csr_io_gva_T = tval_any_addr & _csr_io_status_v; // @[RocketCore.scala:341:19, :846:38, :850:43] wire _csr_io_gva_T_1 = tval_dmem_addr & wb_reg_hls_or_dv; // @[RocketCore.scala:297:29, :845:24, :850:80] wire _csr_io_gva_T_2 = _csr_io_gva_T \| _csr_io_gva_T_1; // @[RocketCore.scala:850:{43,62,80}] wire _csr_io_gva_T_3 = wb_xcpt & _csr_io_gva_T_2; // @[RocketCore.scala:850:{25,62}, :1278:14] wire [24:0] _csr_io_tval_a_T = wb_reg_wdata[63:39]; // @[RocketCore.scala:302:25, :1293:17] wire [24:0] csr_io_tval_a = _csr_io_tval_a_T; // @[RocketCore.scala:1293:{17,23}] wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _csr_io_tval_msb_T_1 = &csr_io_tval_a; // @[RocketCore.scala:1293:23, :1294:34] wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T \| _csr_io_tval_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _csr_io_tval_msb_T_3 = wb_reg_wdata[39]; // @[RocketCore.scala:302:25, :1294:46] wire _csr_io_tval_msb_T_4 = wb_reg_wdata[38]; // @[RocketCore.scala:302:25, :1294:54] wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] assign io_imem_sfence_bits_addr_0 = wb_reg_wdata[38:0]; // @[RocketCore.scala:153:7, :302:25, :1295:16] wire [38:0] _csr_io_tval_T = wb_reg_wdata[38:0]; // @[RocketCore.scala:302:25, :1295:16] wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}] wire [39:0] _csr_io_tval_T_2 = tval_valid ? _csr_io_tval_T_1 : 40'h0; // @[RocketCore.scala:849:28, :851:21, :1295:8] wire htval_valid_imem = wb_reg_xcpt & _htval_valid_imem_T; // @[RocketCore.scala:289:35, :853:{40,56}] wire [39:0] htval_imem = htval_valid_imem ? io_imem_gpa_bits_0 : 40'h0; // @[RocketCore.scala:153:7, :853:40, :854:25] wire [39:0] _htval_T = htval_imem; // @[RocketCore.scala:854:25, :860:29] wire _htval_valid_dmem_T = wb_xcpt & tval_dmem_addr; // @[RocketCore.scala:845:24, :857:36, :1278:14] wire [1:0] _htval_valid_dmem_T_4 = {io_dmem_s2_xcpt_pf_ld_0, io_dmem_s2_xcpt_pf_st_0}; // @[RocketCore.scala:153:7, :857:110] wire _htval_valid_dmem_T_5 = \|_htval_valid_dmem_T_4; // @[RocketCore.scala:857:{110,117}] wire _htval_valid_dmem_T_6 = ~_htval_valid_dmem_T_5; // @[RocketCore.scala:857:{90,117}] wire [39:0] htval = _htval_T; // @[RocketCore.scala:860:{29,43}] wire _mhtinst_read_pseudo_T = io_imem_gpa_is_pte_0 & htval_valid_imem; // @[RocketCore.scala:153:7, :853:40, :862:51] wire mhtinst_read_pseudo = _mhtinst_read_pseudo_T; // @[RocketCore.scala:862:{51,72}] wire _GEN_58 = wb_reg_set_vconfig & wb_reg_valid; // @[RocketCore.scala:288:35, :293:35, :867:47] wire _csr_io_vector_set_vconfig_valid_T; // @[RocketCore.scala:867:47] assign _csr_io_vector_set_vconfig_valid_T = _GEN_58; // @[RocketCore.scala:867:47] wire _id_vconfig_hazard_T_3; // @[RocketCore.scala:1005:19] assign _id_vconfig_hazard_T_3 = _GEN_58; // @[RocketCore.scala:867:47, :1005:19] wire [12:0] _csr_io_vector_set_vconfig_bits_T_7; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_T_6; // @[RocketCore.scala:868:46] wire [54:0] _csr_io_vector_set_vconfig_bits_T_5; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_T_4; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_T_3; // @[RocketCore.scala:868:46] wire [2:0] _csr_io_vector_set_vconfig_bits_T_2; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_T_1; // @[RocketCore.scala:868:46] wire [1:0] _csr_io_vector_set_vconfig_bits_T; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T = _csr_io_vector_set_vconfig_bits_WIRE_1[1:0]; // @[RocketCore.scala:868:46] wire [1:0] _csr_io_vector_set_vconfig_bits_WIRE_vtype_vlmul_mag = _csr_io_vector_set_vconfig_bits_T; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T_1 = _csr_io_vector_set_vconfig_bits_WIRE_1[2]; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_WIRE_vtype_vlmul_sign = _csr_io_vector_set_vconfig_bits_T_1; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T_2 = _csr_io_vector_set_vconfig_bits_WIRE_1[5:3]; // @[RocketCore.scala:868:46] wire [2:0] _csr_io_vector_set_vconfig_bits_WIRE_vtype_vsew = _csr_io_vector_set_vconfig_bits_T_2; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T_3 = _csr_io_vector_set_vconfig_bits_WIRE_1[6]; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_WIRE_vtype_vta = _csr_io_vector_set_vconfig_bits_T_3; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T_4 = _csr_io_vector_set_vconfig_bits_WIRE_1[7]; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_WIRE_vtype_vma = _csr_io_vector_set_vconfig_bits_T_4; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T_5 = _csr_io_vector_set_vconfig_bits_WIRE_1[62:8]; // @[RocketCore.scala:868:46] wire [54:0] _csr_io_vector_set_vconfig_bits_WIRE_vtype_reserved = _csr_io_vector_set_vconfig_bits_T_5; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T_6 = _csr_io_vector_set_vconfig_bits_WIRE_1[63]; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_WIRE_vtype_vill = _csr_io_vector_set_vconfig_bits_T_6; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T_7 = _csr_io_vector_set_vconfig_bits_WIRE_1[76:64]; // @[RocketCore.scala:868:46] wire [12:0] _csr_io_vector_set_vconfig_bits_WIRE_vl = _csr_io_vector_set_vconfig_bits_T_7; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vs_dirty_T = wb_valid & wb_ctrl_vec; // @[RocketCore.scala:245:20, :815:45, :869:32] wire _csr_io_vector_set_vstart_valid_T = wb_valid & wb_reg_set_vconfig; // @[RocketCore.scala:293:35, :815:45, :870:36] wire _T_155 = io_vector_wb_retire_0 \| wb_ctrl_vec; // @[RocketCore.scala:153:7, :245:20, :875:36] wire [11:0] _csr_io_rw_addr_T = wb_reg_inst[31:20]; // @[RocketCore.scala:300:24, :909:32] wire [2:0] _csr_io_rw_cmd_T = {~wb_reg_valid, 2'h0}; // @[RocketCore.scala:288:35] wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala:183:{11,15}] wire [2:0] _csr_io_rw_cmd_T_2 = wb_ctrl_csr & _csr_io_rw_cmd_T_1; // @[RocketCore.scala:245:20] assign io_bpwatch_0_action_0 = {2'h0, _csr_io_bp_0_control_action}; // @[RocketCore.scala:153:7, :341:19, :962:18] wire _hazard_targets_T = \|id_raddr1; // @[RocketCore.scala:326:72, :969:55, :1326:41] wire hazard_targets_0_1 = id_ctrl_rxs1 & _hazard_targets_T; // @[RocketCore.scala:321:21, :969:{42,55}] wire _hazard_targets_T_1 = \|id_raddr2; // @[RocketCore.scala:326:72, :970:55, :1326:41] wire hazard_targets_1_1 = id_ctrl_rxs2 & _hazard_targets_T_1; // @[RocketCore.scala:321:21, :970:{42,55}] wire _hazard_targets_T_2 = \|id_waddr; // @[RocketCore.scala:326:72, :971:55] wire hazard_targets_2_1 = id_ctrl_wxd & _hazard_targets_T_2; // @[RocketCore.scala:321:21, :971:{42,55}] reg [31:0] _r; // @[RocketCore.scala:1305:29] wire [30:0] _r_T = _r[31:1]; // @[RocketCore.scala:1305:29, :1306:35] wire [31:0] r = {_r_T, 1'h0}; // @[RocketCore.scala:1306:{35,40}] wire [31:0] _GEN_59 = {27'h0, id_raddr1}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T = r >> _GEN_59; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_1 = _id_sboard_hazard_T[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_2 = ll_waddr == id_raddr1; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_3 = ll_wen & _id_sboard_hazard_T_2; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_4 = ~_id_sboard_hazard_T_3; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_5 = _id_sboard_hazard_T_1 & _id_sboard_hazard_T_4; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_6 = hazard_targets_0_1 & _id_sboard_hazard_T_5; // @[RocketCore.scala:969:42, :984:77, :1287:27] wire [31:0] _GEN_60 = {27'h0, id_raddr2}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_7 = r >> _GEN_60; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_8 = _id_sboard_hazard_T_7[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_9 = ll_waddr == id_raddr2; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_10 = ll_wen & _id_sboard_hazard_T_9; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_11 = ~_id_sboard_hazard_T_10; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_12 = _id_sboard_hazard_T_8 & _id_sboard_hazard_T_11; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_13 = hazard_targets_1_1 & _id_sboard_hazard_T_12; // @[RocketCore.scala:970:42, :984:77, :1287:27] wire [31:0] _GEN_61 = {27'h0, id_waddr}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_14 = r >> _GEN_61; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_15 = _id_sboard_hazard_T_14[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_16 = ll_waddr == id_waddr; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_17 = ll_wen & _id_sboard_hazard_T_16; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_18 = ~_id_sboard_hazard_T_17; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_19 = _id_sboard_hazard_T_15 & _id_sboard_hazard_T_18; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_20 = hazard_targets_2_1 & _id_sboard_hazard_T_19; // @[RocketCore.scala:971:42, :984:77, :1287:27] wire _id_sboard_hazard_T_21 = _id_sboard_hazard_T_6 \| _id_sboard_hazard_T_13; // @[RocketCore.scala:1287:{27,50}] wire id_sboard_hazard = _id_sboard_hazard_T_21 \| _id_sboard_hazard_T_20; // @[RocketCore.scala:1287:{27,50}] wire [31:0] _id_stall_fpu_T_4 = 32'h1 << wb_waddr; // @[RocketCore.scala:455:36, :1309:58] wire _ex_cannot_bypass_T = \|ex_ctrl_csr; // @[RocketCore.scala:243:20, :988:38] wire _ex_cannot_bypass_T_1 = _ex_cannot_bypass_T \| ex_ctrl_jalr; // @[RocketCore.scala:243:20, :988:{38,48}] wire _ex_cannot_bypass_T_2 = _ex_cannot_bypass_T_1 \| ex_ctrl_mem; // @[RocketCore.scala:243:20, :988:{48,64}] wire _ex_cannot_bypass_T_3 = _ex_cannot_bypass_T_2 \| ex_ctrl_mul; // @[RocketCore.scala:243:20, :988:{64,79}] wire _ex_cannot_bypass_T_4 = _ex_cannot_bypass_T_3 \| ex_ctrl_div; // @[RocketCore.scala:243:20, :988:{79,94}] wire _ex_cannot_bypass_T_5 = _ex_cannot_bypass_T_4 \| ex_ctrl_fp; // @[RocketCore.scala:243:20, :988:{94,109}] wire _ex_cannot_bypass_T_6 = _ex_cannot_bypass_T_5 \| ex_ctrl_rocc; // @[RocketCore.scala:243:20, :988:{109,123}] wire ex_cannot_bypass = _ex_cannot_bypass_T_6 \| ex_ctrl_vec; // @[RocketCore.scala:243:20, :988:{123,139}] wire _data_hazard_ex_T_1 = hazard_targets_0_1 & _data_hazard_ex_T; // @[RocketCore.scala:969:42, :989:70, :1287:27] wire _data_hazard_ex_T_3 = hazard_targets_1_1 & _data_hazard_ex_T_2; // @[RocketCore.scala:970:42, :989:70, :1287:27] wire _GEN_62 = id_waddr == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :989:70] wire _data_hazard_ex_T_4; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T_4 = _GEN_62; // @[RocketCore.scala:989:70] wire _fp_data_hazard_ex_T_7; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_7 = _GEN_62; // @[RocketCore.scala:989:70, :990:90] wire _data_hazard_ex_T_5 = hazard_targets_2_1 & _data_hazard_ex_T_4; // @[RocketCore.scala:971:42, :989:70, :1287:27] wire _data_hazard_ex_T_6 = _data_hazard_ex_T_1 \| _data_hazard_ex_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_ex_T_7 = _data_hazard_ex_T_6 \| _data_hazard_ex_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_ex = ex_ctrl_wxd & _data_hazard_ex_T_7; // @[RocketCore.scala:243:20, :989:36, :1287:50] wire _fp_data_hazard_ex_T = id_ctrl_fp & ex_ctrl_wfd; // @[RocketCore.scala:243:20, :321:21, :990:38] wire _fp_data_hazard_ex_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_ex_T_1; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_ex_T_3; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_5 = id_raddr3 == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :990:90] wire _fp_data_hazard_ex_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_ex_T_5; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_ex_T_7; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_9 = _fp_data_hazard_ex_T_2 \| _fp_data_hazard_ex_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_ex_T_10 = _fp_data_hazard_ex_T_9 \| _fp_data_hazard_ex_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_ex_T_11 = _fp_data_hazard_ex_T_10 \| _fp_data_hazard_ex_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_ex = _fp_data_hazard_ex_T & _fp_data_hazard_ex_T_11; // @[RocketCore.scala:990:{38,53}, :1287:50] wire _id_ex_hazard_T = data_hazard_ex & ex_cannot_bypass; // @[RocketCore.scala:988:139, :989:36, :991:54] wire _id_ex_hazard_T_1 = _id_ex_hazard_T \| fp_data_hazard_ex; // @[RocketCore.scala:990:53, :991:{54,74}] wire id_ex_hazard = ex_reg_valid & _id_ex_hazard_T_1; // @[RocketCore.scala:248:35, :991:{35,74}] wire _mem_cannot_bypass_T = \|mem_ctrl_csr; // @[RocketCore.scala:244:21, :997:40] wire _mem_cannot_bypass_T_1 = mem_ctrl_mem & mem_mem_cmd_bh; // @[RocketCore.scala:244:21, :995:41, :997:66] wire _mem_cannot_bypass_T_2 = _mem_cannot_bypass_T \| _mem_cannot_bypass_T_1; // @[RocketCore.scala:997:{40,50,66}] wire _mem_cannot_bypass_T_3 = _mem_cannot_bypass_T_2 \| mem_ctrl_mul; // @[RocketCore.scala:244:21, :997:{50,84}] wire _mem_cannot_bypass_T_4 = _mem_cannot_bypass_T_3 \| mem_ctrl_div; // @[RocketCore.scala:244:21, :997:{84,100}] wire _mem_cannot_bypass_T_5 = _mem_cannot_bypass_T_4 \| mem_ctrl_fp; // @[RocketCore.scala:244:21, :997:{100,116}] wire _mem_cannot_bypass_T_6 = _mem_cannot_bypass_T_5 \| mem_ctrl_rocc; // @[RocketCore.scala:244:21, :997:{116,131}] wire mem_cannot_bypass = _mem_cannot_bypass_T_6 \| mem_ctrl_vec; // @[RocketCore.scala:244:21, :997:{131,148}] wire _data_hazard_mem_T_1 = hazard_targets_0_1 & _data_hazard_mem_T; // @[RocketCore.scala:969:42, :998:72, :1287:27] wire _data_hazard_mem_T_3 = hazard_targets_1_1 & _data_hazard_mem_T_2; // @[RocketCore.scala:970:42, :998:72, :1287:27] wire _GEN_63 = id_waddr == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :998:72] wire _data_hazard_mem_T_4; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T_4 = _GEN_63; // @[RocketCore.scala:998:72] wire _fp_data_hazard_mem_T_7; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_7 = _GEN_63; // @[RocketCore.scala:998:72, :999:92] wire _data_hazard_mem_T_5 = hazard_targets_2_1 & _data_hazard_mem_T_4; // @[RocketCore.scala:971:42, :998:72, :1287:27] wire _data_hazard_mem_T_6 = _data_hazard_mem_T_1 \| _data_hazard_mem_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_mem_T_7 = _data_hazard_mem_T_6 \| _data_hazard_mem_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_mem = mem_ctrl_wxd & _data_hazard_mem_T_7; // @[RocketCore.scala:244:21, :998:38, :1287:50] wire _fp_data_hazard_mem_T = id_ctrl_fp & mem_ctrl_wfd; // @[RocketCore.scala:244:21, :321:21, :999:39] wire _fp_data_hazard_mem_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_mem_T_1; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_mem_T_3; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_5 = id_raddr3 == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :999:92] wire _fp_data_hazard_mem_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_mem_T_5; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_mem_T_7; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_9 = _fp_data_hazard_mem_T_2 \| _fp_data_hazard_mem_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_mem_T_10 = _fp_data_hazard_mem_T_9 \| _fp_data_hazard_mem_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_mem_T_11 = _fp_data_hazard_mem_T_10 \| _fp_data_hazard_mem_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_mem = _fp_data_hazard_mem_T & _fp_data_hazard_mem_T_11; // @[RocketCore.scala:999:{39,55}, :1287:50] wire _id_mem_hazard_T = data_hazard_mem & mem_cannot_bypass; // @[RocketCore.scala:997:148, :998:38, :1000:57] wire _id_mem_hazard_T_1 = _id_mem_hazard_T \| fp_data_hazard_mem; // @[RocketCore.scala:999:55, :1000:{57,78}] wire id_mem_hazard = mem_reg_valid & _id_mem_hazard_T_1; // @[RocketCore.scala:265:36, :1000:{37,78}] wire _id_load_use_T = mem_reg_valid & data_hazard_mem; // @[RocketCore.scala:265:36, :998:38, :1001:32] assign _id_load_use_T_1 = _id_load_use_T & mem_ctrl_mem; // @[RocketCore.scala:244:21, :1001:{32,51}] assign id_load_use = _id_load_use_T_1; // @[RocketCore.scala:332:25, :1001:51] wire _id_vconfig_hazard_T = ex_reg_valid & ex_reg_set_vconfig; // @[RocketCore.scala:248:35, :262:36, :1003:19] wire _id_vconfig_hazard_T_1 = mem_reg_valid & mem_reg_set_vconfig; // @[RocketCore.scala:265:36, :275:36, :1004:20] wire _id_vconfig_hazard_T_2 = _id_vconfig_hazard_T \| _id_vconfig_hazard_T_1; // @[RocketCore.scala:1003:{19,42}, :1004:20] wire _id_vconfig_hazard_T_4 = _id_vconfig_hazard_T_2 \| _id_vconfig_hazard_T_3; // @[RocketCore.scala:1003:42, :1004:44, :1005:19] wire id_vconfig_hazard = id_ctrl_vec & _id_vconfig_hazard_T_4; // @[RocketCore.scala:321:21, :1002:39, :1004:44] wire _GEN_64 = id_raddr1 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T = _GEN_64; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_1; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_1 = _GEN_64; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_1 = hazard_targets_0_1 & _data_hazard_wb_T; // @[RocketCore.scala:969:42, :1008:70, :1287:27] wire _GEN_65 = id_raddr2 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T_2; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T_2 = _GEN_65; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_3; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_3 = _GEN_65; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_3 = hazard_targets_1_1 & _data_hazard_wb_T_2; // @[RocketCore.scala:970:42, :1008:70, :1287:27] wire _GEN_66 = id_waddr == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T_4; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T_4 = _GEN_66; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_7; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_7 = _GEN_66; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_5 = hazard_targets_2_1 & _data_hazard_wb_T_4; // @[RocketCore.scala:971:42, :1008:70, :1287:27] wire _data_hazard_wb_T_6 = _data_hazard_wb_T_1 \| _data_hazard_wb_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_wb_T_7 = _data_hazard_wb_T_6 \| _data_hazard_wb_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_wb = wb_ctrl_wxd & _data_hazard_wb_T_7; // @[RocketCore.scala:245:20, :1008:36, :1287:50] wire _fp_data_hazard_wb_T = id_ctrl_fp & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :321:21, :1009:38] wire _fp_data_hazard_wb_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_wb_T_1; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_wb_T_3; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_5 = id_raddr3 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1009:90] wire _fp_data_hazard_wb_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_wb_T_5; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_wb_T_7; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_9 = _fp_data_hazard_wb_T_2 \| _fp_data_hazard_wb_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_wb_T_10 = _fp_data_hazard_wb_T_9 \| _fp_data_hazard_wb_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_wb_T_11 = _fp_data_hazard_wb_T_10 \| _fp_data_hazard_wb_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_wb = _fp_data_hazard_wb_T & _fp_data_hazard_wb_T_11; // @[RocketCore.scala:1009:{38,53}, :1287:50] wire _id_wb_hazard_T = data_hazard_wb & wb_set_sboard; // @[RocketCore.scala:756:69, :1008:36, :1010:54] wire _id_wb_hazard_T_1 = _id_wb_hazard_T \| fp_data_hazard_wb; // @[RocketCore.scala:1009:53, :1010:{54,71}] wire id_wb_hazard = wb_reg_valid & _id_wb_hazard_T_1; // @[RocketCore.scala:288:35, :1010:{35,71}] reg [31:0] _id_stall_fpu_r; // @[RocketCore.scala:1305:29] wire _id_stall_fpu_T = wb_dcache_miss \| wb_ctrl_vec; // @[RocketCore.scala:245:20, :596:36, :1014:36] wire _id_stall_fpu_T_1 = _id_stall_fpu_T & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :1014:{36,52}] wire _id_stall_fpu_T_2 = _id_stall_fpu_T_1 \| io_fpu_sboard_set_0; // @[RocketCore.scala:153:7, :1014:{52,67}] wire _id_stall_fpu_T_3 = _id_stall_fpu_T_2 & wb_valid; // @[RocketCore.scala:815:45, :1014:{67,89}] wire _id_stall_fpu_T_7 = _id_stall_fpu_T_3; // @[RocketCore.scala:1014:89, :1312:17] wire [31:0] _id_stall_fpu_T_5 = _id_stall_fpu_T_3 ? _id_stall_fpu_T_4 : 32'h0; // @[RocketCore.scala:1014:89, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_6 = _id_stall_fpu_r \| _id_stall_fpu_T_5; // @[RocketCore.scala:1300:60, :1305:29, :1309:49] wire _id_stall_fpu_v_ll_T = io_vector_resp_ready_0 & io_vector_resp_valid_0; // @[Decoupled.scala:51:35] wire id_stall_fpu_v_ll = _id_stall_fpu_v_ll_T & io_vector_resp_bits_fp_0; // @[Decoupled.scala:51:35] wire _id_stall_fpu_T_8 = dmem_resp_replay & dmem_resp_fpu; // @[RocketCore.scala:766:45, :769:42, :1016:39] wire _id_stall_fpu_T_9 = _id_stall_fpu_T_8 \| id_stall_fpu_v_ll; // @[RocketCore.scala:1015:47, :1016:{39,57}] wire [31:0] _id_stall_fpu_T_10 = 32'h1 << io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7, :1309:58] wire [31:0] _id_stall_fpu_T_11 = _id_stall_fpu_T_9 ? _id_stall_fpu_T_10 : 32'h0; // @[RocketCore.scala:1016:57, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_12 = ~_id_stall_fpu_T_11; // @[RocketCore.scala:1301:64, :1309:49] wire [31:0] _id_stall_fpu_T_13 = _id_stall_fpu_T_6 & _id_stall_fpu_T_12; // @[RocketCore.scala:1300:60, :1301:{62,64}] wire _id_stall_fpu_T_14 = _id_stall_fpu_T_7 \| _id_stall_fpu_T_9; // @[RocketCore.scala:1016:57, :1312:17] wire [31:0] _id_stall_fpu_T_15 = 32'h1 << io_fpu_sboard_clra_0; // @[RocketCore.scala:153:7, :1309:58] wire [31:0] _id_stall_fpu_T_16 = io_fpu_sboard_clr_0 ? _id_stall_fpu_T_15 : 32'h0; // @[RocketCore.scala:153:7, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_17 = ~_id_stall_fpu_T_16; // @[RocketCore.scala:1301:64, :1309:49] wire [31:0] _id_stall_fpu_T_18 = _id_stall_fpu_T_13 & _id_stall_fpu_T_17; // @[RocketCore.scala:1301:{62,64}] wire _id_stall_fpu_T_19 = _id_stall_fpu_T_14 \| io_fpu_sboard_clr_0; // @[RocketCore.scala:153:7, :1312:17] wire [31:0] _id_stall_fpu_T_20 = _id_stall_fpu_r >> _GEN_59; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_21 = _id_stall_fpu_T_20[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_22 = io_fpu_dec_ren1_0 & _id_stall_fpu_T_21; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_23 = _id_stall_fpu_r >> _GEN_60; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_24 = _id_stall_fpu_T_23[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_25 = io_fpu_dec_ren2_0 & _id_stall_fpu_T_24; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_26 = _id_stall_fpu_r >> id_raddr3; // @[RocketCore.scala:326:72, :1302:35, :1305:29] wire _id_stall_fpu_T_27 = _id_stall_fpu_T_26[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_28 = io_fpu_dec_ren3_0 & _id_stall_fpu_T_27; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_29 = _id_stall_fpu_r >> _GEN_61; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_30 = _id_stall_fpu_T_29[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_31 = io_fpu_dec_wen_0 & _id_stall_fpu_T_30; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire _id_stall_fpu_T_32 = _id_stall_fpu_T_22 \| _id_stall_fpu_T_25; // @[RocketCore.scala:1287:{27,50}] wire _id_stall_fpu_T_33 = _id_stall_fpu_T_32 \| _id_stall_fpu_T_28; // @[RocketCore.scala:1287:{27,50}] wire id_stall_fpu = _id_stall_fpu_T_33 \| _id_stall_fpu_T_31; // @[RocketCore.scala:1287:{27,50}] reg dcache_blocked_blocked; // @[RocketCore.scala:1024:22] wire _dcache_blocked_blocked_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45, :1025:16] wire _dcache_blocked_blocked_T_1 = _dcache_blocked_blocked_T; // @[RocketCore.scala:1025:{16,35}] wire _dcache_blocked_blocked_T_2 = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63] wire _dcache_blocked_blocked_T_3 = _dcache_blocked_blocked_T_1 & _dcache_blocked_blocked_T_2; // @[RocketCore.scala:1025:{35,60,63}] wire _dcache_blocked_blocked_T_4 = dcache_blocked_blocked \| io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :1024:22, :1025:95] wire _dcache_blocked_blocked_T_5 = _dcache_blocked_blocked_T_4 \| io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1025:{95,116}] wire _dcache_blocked_blocked_T_6 = _dcache_blocked_blocked_T_3 & _dcache_blocked_blocked_T_5; // @[RocketCore.scala:1025:{60,83,116}] wire _dcache_blocked_T = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63, :1026:16] wire dcache_blocked = dcache_blocked_blocked & _dcache_blocked_T; // @[RocketCore.scala:1024:22, :1026:{13,16}] reg rocc_blocked; // @[RocketCore.scala:1028:25] wire _rocc_blocked_T = ~wb_xcpt; // @[RocketCore.scala:815:48, :1029:19, :1278:14] wire _rocc_blocked_T_2 = _rocc_blocked_T; // @[RocketCore.scala:1029:{19,28}] wire _rocc_blocked_T_3 = io_rocc_cmd_valid \| rocc_blocked; // @[RocketCore.scala:153:7, :1028:25, :1029:72] wire _rocc_blocked_T_4 = _rocc_blocked_T_2 & _rocc_blocked_T_3; // @[RocketCore.scala:1029:{28,50,72}] wire _ctrl_stalld_T = id_ex_hazard \| id_mem_hazard; // @[RocketCore.scala:991:35, :1000:37, :1032:18] wire _ctrl_stalld_T_1 = _ctrl_stalld_T \| id_wb_hazard; // @[RocketCore.scala:1010:35, :1032:{18,35}] wire _ctrl_stalld_T_2 = _ctrl_stalld_T_1 \| id_sboard_hazard; // @[RocketCore.scala:1032:{35,51}, :1287:50] wire _ctrl_stalld_T_3 = _ctrl_stalld_T_2 \| id_vconfig_hazard; // @[RocketCore.scala:1002:39, :1032:{51,71}] wire _ctrl_stalld_T_4 = ex_reg_valid \| mem_reg_valid; // @[RocketCore.scala:248:35, :265:36, :1034:40] wire _ctrl_stalld_T_5 = _ctrl_stalld_T_4 \| wb_reg_valid; // @[RocketCore.scala:288:35, :1034:{40,57}] wire _ctrl_stalld_T_6 = _csr_io_singleStep & _ctrl_stalld_T_5; // @[RocketCore.scala:341:19, :1034:{23,57}] wire _ctrl_stalld_T_7 = _ctrl_stalld_T_3 \| _ctrl_stalld_T_6; // @[RocketCore.scala:1032:71, :1033:23, :1034:23] wire _ctrl_stalld_T_8 = id_csr_en & _csr_io_decode_0_fp_csr; // @[package.scala:81:59] wire _ctrl_stalld_T_9 = ~io_fpu_fcsr_rdy_0; // @[RocketCore.scala:153:7, :1035:45] wire _ctrl_stalld_T_10 = _ctrl_stalld_T_8 & _ctrl_stalld_T_9; // @[RocketCore.scala:1035:{15,42,45}] wire _ctrl_stalld_T_11 = _ctrl_stalld_T_7 \| _ctrl_stalld_T_10; // @[RocketCore.scala:1033:23, :1034:74, :1035:42] wire _ctrl_stalld_T_12 = id_csr_en & _csr_io_decode_0_vector_csr; // @[package.scala:81:59] wire _ctrl_stalld_T_13 = _ctrl_stalld_T_12 & id_vec_busy; // @[RocketCore.scala:409:55, :1036:{15,46}] wire _ctrl_stalld_T_14 = _ctrl_stalld_T_11 \| _ctrl_stalld_T_13; // @[RocketCore.scala:1034:74, :1035:62, :1036:46] wire _ctrl_stalld_T_15 = id_ctrl_fp & id_stall_fpu; // @[RocketCore.scala:321:21, :1037:16, :1287:50] wire _ctrl_stalld_T_16 = _ctrl_stalld_T_14 \| _ctrl_stalld_T_15; // @[RocketCore.scala:1035:62, :1036:61, :1037:16] wire _ctrl_stalld_T_17 = id_ctrl_mem & dcache_blocked; // @[RocketCore.scala:321:21, :1026:13, :1038:17] wire _ctrl_stalld_T_18 = _ctrl_stalld_T_16 \| _ctrl_stalld_T_17; // @[RocketCore.scala:1036:61, :1037:32, :1038:17] wire _ctrl_stalld_T_19 = id_ctrl_rocc & rocc_blocked; // @[RocketCore.scala:321:21, :1028:25, :1039:18] wire _ctrl_stalld_T_20 = _ctrl_stalld_T_18 \| _ctrl_stalld_T_19; // @[RocketCore.scala:1037:32, :1038:35, :1039:18] wire _ctrl_stalld_T_21 = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26, :1040:65] wire _ctrl_stalld_T_22 = _div_io_resp_valid & _ctrl_stalld_T_21; // @[RocketCore.scala:511:19, :1040:{62,65}] wire _ctrl_stalld_T_23 = _div_io_req_ready \| _ctrl_stalld_T_22; // @[RocketCore.scala:511:19, :1040:{40,62}] wire _ctrl_stalld_T_24 = ~_ctrl_stalld_T_23; // @[RocketCore.scala:1040:{21,40}] wire _ctrl_stalld_T_25 = _ctrl_stalld_T_24 \| _div_io_req_valid_T; // @[RocketCore.scala:512:36, :1040:{21,75}] wire _ctrl_stalld_T_26 = id_ctrl_div & _ctrl_stalld_T_25; // @[RocketCore.scala:321:21, :1040:{17,75}] wire _ctrl_stalld_T_27 = _ctrl_stalld_T_20 \| _ctrl_stalld_T_26; // @[RocketCore.scala:1038:35, :1039:34, :1040:17] wire _ctrl_stalld_T_29 = _ctrl_stalld_T_27; // @[RocketCore.scala:1039:34, :1040:96] wire _ctrl_stalld_T_30 = _ctrl_stalld_T_29 \| id_do_fence; // @[RocketCore.scala:410:32, :1040:96, :1041:15] wire _ctrl_stalld_T_31 = _ctrl_stalld_T_30 \| _csr_io_csr_stall; // @[RocketCore.scala:341:19, :1041:15, :1042:17] wire _ctrl_stalld_T_32 = _ctrl_stalld_T_31 \| id_reg_pause; // @[RocketCore.scala:161:25, :1042:17, :1043:22] wire ctrl_stalld = _ctrl_stalld_T_32; // @[RocketCore.scala:1043:22, :1044:18] wire _ctrl_killd_T = ~_ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :1046:17] wire _ctrl_killd_T_1 = _ctrl_killd_T \| _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :1046:{17,40}] wire _ctrl_killd_T_2 = _ctrl_killd_T_1 \| take_pc_mem_wb; // @[RocketCore.scala:307:35, :1046:{40,71}] wire _ctrl_killd_T_3 = _ctrl_killd_T_2 \| ctrl_stalld; // @[RocketCore.scala:1044:18, :1046:{71,89}] assign _ctrl_killd_T_4 = _ctrl_killd_T_3 \| _csr_io_interrupt; // @[RocketCore.scala:341:19, :1046:{89,104}] assign ctrl_killd = _ctrl_killd_T_4; // @[RocketCore.scala:338:24, :1046:104] assign _io_imem_req_bits_speculative_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1049:35] assign io_imem_req_bits_speculative_0 = _io_imem_req_bits_speculative_T; // @[RocketCore.scala:153:7, :1049:35] wire _io_imem_req_bits_pc_T = wb_xcpt \| _csr_io_eret; // @[RocketCore.scala:341:19, :1051:17, :1278:14] wire [39:0] _io_imem_req_bits_pc_T_1 = replay_wb ? wb_reg_pc : mem_npc; // @[RocketCore.scala:295:22, :619:139, :761:71, :1052:8] assign _io_imem_req_bits_pc_T_2 = _io_imem_req_bits_pc_T ? _csr_io_evec : _io_imem_req_bits_pc_T_1; // @[RocketCore.scala:341:19, :1051:{8,17}, :1052:8] assign io_imem_req_bits_pc_0 = _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:153:7, :1051:8] wire _io_imem_flush_icache_T = wb_reg_valid & wb_ctrl_fence_i; // @[RocketCore.scala:245:20, :288:35, :1054:40] wire _io_imem_flush_icache_T_1 = ~io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1054:62] assign _io_imem_flush_icache_T_2 = _io_imem_flush_icache_T & _io_imem_flush_icache_T_1; // @[RocketCore.scala:1054:{40,59,62}] assign io_imem_flush_icache_0 = _io_imem_flush_icache_T_2; // @[RocketCore.scala:153:7, :1054:59] wire _io_imem_might_request_imem_might_request_reg_T = ex_pc_valid \| mem_pc_valid; // @[RocketCore.scala:595:51, :614:54, :1056:43] wire _io_imem_might_request_imem_might_request_reg_T_1 = io_ptw_customCSRs_csrs_0_value_0[1]; // @[CustomCSRs.scala:44:61] wire _io_imem_might_request_imem_might_request_reg_T_2 = _io_imem_might_request_imem_might_request_reg_T \| _io_imem_might_request_imem_might_request_reg_T_1; // @[CustomCSRs.scala:44:61] wire _io_imem_might_request_imem_might_request_reg_T_3 = _io_imem_might_request_imem_might_request_reg_T_2; // @[RocketCore.scala:1056:{59,103}] wire _io_imem_progress_T = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47] wire _io_imem_progress_T_1 = wb_reg_valid & _io_imem_progress_T; // @[RocketCore.scala:288:35, :1059:{44,47}] reg io_imem_progress_REG; // @[RocketCore.scala:1059:30] assign io_imem_progress_0 = io_imem_progress_REG; // @[RocketCore.scala:153:7, :1059:30] assign _io_imem_sfence_valid_T = wb_reg_valid & wb_reg_sfence; // @[RocketCore.scala:288:35, :294:26, :1060:40] assign io_imem_sfence_valid_0 = _io_imem_sfence_valid_T; // @[RocketCore.scala:153:7, :1060:40] assign _io_imem_sfence_bits_rs1_T = wb_reg_mem_size[0]; // @[RocketCore.scala:296:28, :1061:45] assign io_imem_sfence_bits_rs1_0 = _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:153:7, :1061:45] assign _io_imem_sfence_bits_rs2_T = wb_reg_mem_size[1]; // @[RocketCore.scala:296:28, :1062:45] assign io_imem_sfence_bits_rs2_0 = _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:153:7, :1062:45] assign io_imem_sfence_bits_asid_0 = wb_reg_rs2[0]; // @[RocketCore.scala:153:7, :303:23, :1064:28] wire _ibuf_io_inst_0_ready_T = ~ctrl_stalld; // @[RocketCore.scala:1044:18, :1069:28] wire _io_imem_btb_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1071:48] wire _io_imem_btb_update_valid_T_1 = mem_reg_valid & _io_imem_btb_update_valid_T; // @[RocketCore.scala:265:36, :1071:{45,48}] wire _io_imem_btb_update_valid_T_2 = _io_imem_btb_update_valid_T_1 & mem_wrong_npc; // @[RocketCore.scala:621:8, :1071:{45,60}] wire _io_imem_btb_update_valid_T_3 = ~mem_cfi; // @[RocketCore.scala:625:50, :1071:81] wire _io_imem_btb_update_valid_T_4 = _io_imem_btb_update_valid_T_3 \| mem_cfi_taken; // @[RocketCore.scala:626:74, :1071:{81,90}] assign _io_imem_btb_update_valid_T_5 = _io_imem_btb_update_valid_T_2 & _io_imem_btb_update_valid_T_4; // @[RocketCore.scala:1071:{60,77,90}] assign io_imem_btb_update_valid_0 = _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:153:7, :1071:77] wire _GEN_67 = mem_ctrl_jal \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :1074:23] wire _io_imem_btb_update_bits_cfiType_T; // @[RocketCore.scala:1074:23] assign _io_imem_btb_update_bits_cfiType_T = _GEN_67; // @[RocketCore.scala:1074:23] wire _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:22] assign _io_imem_btb_update_bits_cfiType_T_8 = _GEN_67; // @[RocketCore.scala:1074:23, :1076:22] wire _io_imem_btb_update_bits_cfiType_T_1 = mem_waddr[0]; // @[RocketCore.scala:454:38, :1074:53] wire _io_imem_btb_update_bits_cfiType_T_2 = _io_imem_btb_update_bits_cfiType_T & _io_imem_btb_update_bits_cfiType_T_1; // @[RocketCore.scala:1074:{23,41,53}] wire [4:0] _io_imem_btb_update_bits_cfiType_T_3 = mem_reg_inst[19:15]; // @[RocketCore.scala:278:25, :1075:39] wire [4:0] _io_imem_btb_update_bits_cfiType_T_4 = _io_imem_btb_update_bits_cfiType_T_3; // @[RocketCore.scala:1075:{39,47}] wire [4:0] _io_imem_btb_update_bits_cfiType_T_5 = _io_imem_btb_update_bits_cfiType_T_4 & 5'h1B; // @[RocketCore.scala:1075:{47,64}] wire _io_imem_btb_update_bits_cfiType_T_6 = _io_imem_btb_update_bits_cfiType_T_5 == 5'h1; // @[RocketCore.scala:1075:64] wire _io_imem_btb_update_bits_cfiType_T_7 = mem_ctrl_jalr & _io_imem_btb_update_bits_cfiType_T_6; // @[RocketCore.scala:244:21, :1075:{23,64}] wire _io_imem_btb_update_bits_cfiType_T_9 = _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:{8,22}] wire [1:0] _io_imem_btb_update_bits_cfiType_T_10 = _io_imem_btb_update_bits_cfiType_T_7 ? 2'h3 : {1'h0, _io_imem_btb_update_bits_cfiType_T_9}; // @[RocketCore.scala:1075:{8,23}, :1076:8] assign _io_imem_btb_update_bits_cfiType_T_11 = _io_imem_btb_update_bits_cfiType_T_2 ? 2'h2 : _io_imem_btb_update_bits_cfiType_T_10; // @[RocketCore.scala:1074:{8,41}, :1075:8] assign io_imem_btb_update_bits_cfiType_0 = _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:153:7, :1074:8] assign io_imem_btb_update_bits_target_0 = io_imem_req_bits_pc_0[38:0]; // @[RocketCore.scala:153:7, :1078:34] wire [1:0] _io_imem_btb_update_bits_br_pc_T = {~mem_reg_rvc, 1'h0}; // @[RocketCore.scala:266:36, :1079:74] wire [40:0] _io_imem_btb_update_bits_br_pc_T_1 = {1'h0, mem_reg_pc} + {39'h0, _io_imem_btb_update_bits_br_pc_T}; // @[RocketCore.scala:277:23, :1079:{69,74}] wire [39:0] _io_imem_btb_update_bits_br_pc_T_2 = _io_imem_btb_update_bits_br_pc_T_1[39:0]; // @[RocketCore.scala:1079:69] assign io_imem_btb_update_bits_br_pc_0 = _io_imem_btb_update_bits_br_pc_T_2[38:0]; // @[RocketCore.scala:153:7, :1079:{33,69}] wire [38:0] _io_imem_btb_update_bits_pc_T = ~io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7, :1080:35] wire [38:0] _io_imem_btb_update_bits_pc_T_1 = {_io_imem_btb_update_bits_pc_T[38:2], 2'h3}; // @[RocketCore.scala:1080:{35,66}] assign _io_imem_btb_update_bits_pc_T_2 = ~_io_imem_btb_update_bits_pc_T_1; // @[RocketCore.scala:1080:{33,66}] assign io_imem_btb_update_bits_pc_0 = _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:153:7, :1080:33] wire _io_imem_bht_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1084:48] assign _io_imem_bht_update_valid_T_1 = mem_reg_valid & _io_imem_bht_update_valid_T; // @[RocketCore.scala:265:36, :1084:{45,48}] assign io_imem_bht_update_valid_0 = _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:153:7, :1084:45] wire _io_fpu_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :1094:19] assign _io_fpu_valid_T_1 = _io_fpu_valid_T & id_ctrl_fp; // @[RocketCore.scala:321:21, :1094:{19,31}] assign io_fpu_valid_0 = _io_fpu_valid_T_1; // @[RocketCore.scala:153:7, :1094:31] assign _io_fpu_keep_clock_enabled_T = io_ptw_customCSRs_csrs_0_value_0[2]; // @[CustomCSRs.scala:45:59] assign io_fpu_keep_clock_enabled_0 = _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59] wire _io_fpu_ll_resp_val_T_1 = io_vector_resp_valid_0 & io_vector_resp_bits_fp_0; // @[RocketCore.scala:153:7, :1109:42] assign io_fpu_ll_resp_val_0 = _T_168 ? _io_fpu_ll_resp_val_T : _io_fpu_ll_resp_val_T_1; // @[RocketCore.scala:153:7, :801:59, :1099:{22,41}, :1108:48, :1109:{26,42}] assign io_fpu_ll_resp_data_0 = _T_168 ? io_dmem_resp_bits_data_0 : io_vector_resp_bits_data_0; // @[RocketCore.scala:153:7, :801:59, :1100:23, :1108:48, :1110:27] assign io_fpu_ll_resp_type_0 = {1'h0, _T_168 ? io_dmem_resp_bits_size_0 : io_vector_resp_bits_size_0}; // @[RocketCore.scala:153:7, :801:59, :1101:23, :1108:48, :1111:27] assign io_fpu_ll_resp_tag_0 = _T_168 ? dmem_resp_waddr : io_vector_resp_bits_rd_0; // @[RocketCore.scala:153:7, :767:46, :801:59, :1102:22, :1108:48, :1112:26] wire _io_vector_ex_valid_T_1 = ex_ctrl_vec \| _io_vector_ex_valid_T; // @[RocketCore.scala:243:20, :1117:{48,90}] wire _io_vector_ex_valid_T_2 = ex_reg_valid & _io_vector_ex_valid_T_1; // @[RocketCore.scala:248:35, :1117:{32,48}] wire _io_vector_ex_valid_T_3 = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20, :1117:116] assign _io_vector_ex_valid_T_4 = _io_vector_ex_valid_T_2 & _io_vector_ex_valid_T_3; // @[RocketCore.scala:1117:{32,113,116}] assign io_vector_ex_valid_0 = _io_vector_ex_valid_T_4; // @[RocketCore.scala:153:7, :1117:113] wire _io_vector_ex_vstart_T = mem_reg_valid & mem_ctrl_vec; // @[RocketCore.scala:244:21, :265:36, :1120:38] wire _io_vector_ex_vstart_T_1 = wb_reg_valid & wb_ctrl_vec; // @[RocketCore.scala:245:20, :288:35, :1120:70] wire _io_vector_ex_vstart_T_2 = _io_vector_ex_vstart_T \| _io_vector_ex_vstart_T_1; // @[RocketCore.scala:1120:{38,54,70}] assign _io_vector_ex_vstart_T_3 = _io_vector_ex_vstart_T_2 ? 12'h0 : _csr_io_vector_vstart; // @[RocketCore.scala:341:19, :1120:{23,54}] assign io_vector_ex_vstart_0 = _io_vector_ex_vstart_T_3; // @[RocketCore.scala:153:7, :1120:23] assign _io_dmem_req_valid_T = ex_reg_valid & ex_ctrl_mem; // @[RocketCore.scala:243:20, :248:35, :1130:41] assign io_dmem_req_valid_0 = _io_dmem_req_valid_T; // @[RocketCore.scala:153:7, :1130:41] wire [5:0] ex_dcache_tag = {ex_waddr, ex_ctrl_fp}; // @[RocketCore.scala:243:20, :453:36, :1131:26] assign io_dmem_req_bits_tag_0 = {1'h0, ex_dcache_tag}; // @[RocketCore.scala:153:7, :1131:26, :1133:25] wire _io_dmem_req_bits_signed_T_1 = ex_reg_inst[14]; // @[RocketCore.scala:259:24, :1136:75] wire _io_dmem_req_bits_signed_T_2 = _io_dmem_req_bits_signed_T_1; // @[RocketCore.scala:1136:{34,75}] assign _io_dmem_req_bits_signed_T_3 = ~_io_dmem_req_bits_signed_T_2; // @[RocketCore.scala:1136:{30,34}] assign io_dmem_req_bits_signed_0 = _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:153:7, :1136:30] wire [24:0] _io_dmem_req_bits_addr_a_T = ex_rs_0[63:39]; // @[RocketCore.scala:469:14, :1293:17] wire [24:0] io_dmem_req_bits_addr_a = _io_dmem_req_bits_addr_a_T; // @[RocketCore.scala:1293:{17,23}] wire _io_dmem_req_bits_addr_msb_T = io_dmem_req_bits_addr_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _io_dmem_req_bits_addr_msb_T_1 = &io_dmem_req_bits_addr_a; // @[RocketCore.scala:1293:23, :1294:34] wire _io_dmem_req_bits_addr_msb_T_2 = _io_dmem_req_bits_addr_msb_T \| _io_dmem_req_bits_addr_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _io_dmem_req_bits_addr_msb_T_3 = _alu_io_adder_out[39]; // @[RocketCore.scala:504:19, :1294:46] wire _io_dmem_req_bits_addr_msb_T_4 = _alu_io_adder_out[38]; // @[RocketCore.scala:504:19, :1294:54] wire _io_dmem_req_bits_addr_msb_T_5 = ~_io_dmem_req_bits_addr_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire io_dmem_req_bits_addr_msb = _io_dmem_req_bits_addr_msb_T_2 ? _io_dmem_req_bits_addr_msb_T_3 : _io_dmem_req_bits_addr_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] wire [38:0] _io_dmem_req_bits_addr_T = _alu_io_adder_out[38:0]; // @[RocketCore.scala:504:19, :1295:16] assign _io_dmem_req_bits_addr_T_1 = {io_dmem_req_bits_addr_msb, _io_dmem_req_bits_addr_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}] assign io_dmem_req_bits_addr_0 = _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:153:7, :1295:8] assign io_dmem_req_bits_dprv_0 = _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:153:7, :1140:31] assign io_dmem_req_bits_dv_0 = _io_dmem_req_bits_dv_T; // @[RocketCore.scala:153:7, :1141:37] wire _io_dmem_req_bits_no_resp_T_4 = _io_dmem_req_bits_no_resp_T \| _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_5 = _io_dmem_req_bits_no_resp_T_4 \| _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_6 = _io_dmem_req_bits_no_resp_T_5 \| _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_11 = _io_dmem_req_bits_no_resp_T_7 \| _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_12 = _io_dmem_req_bits_no_resp_T_11 \| _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_13 = _io_dmem_req_bits_no_resp_T_12 \| _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_19 = _io_dmem_req_bits_no_resp_T_14 \| _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_20 = _io_dmem_req_bits_no_resp_T_19 \| _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_21 = _io_dmem_req_bits_no_resp_T_20 \| _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_22 = _io_dmem_req_bits_no_resp_T_21 \| _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_23 = _io_dmem_req_bits_no_resp_T_13 \| _io_dmem_req_bits_no_resp_T_22; // @[package.scala:81:59] wire _io_dmem_req_bits_no_resp_T_24 = _io_dmem_req_bits_no_resp_T_6 \| _io_dmem_req_bits_no_resp_T_23; // @[package.scala:81:59] wire _io_dmem_req_bits_no_resp_T_25 = ~_io_dmem_req_bits_no_resp_T_24; // @[RocketCore.scala:1142:31] wire _io_dmem_req_bits_no_resp_T_26 = ~ex_ctrl_fp; // @[RocketCore.scala:243:20, :1142:60] wire _io_dmem_req_bits_no_resp_T_27 = ex_waddr == 5'h0; // @[RocketCore.scala:453:36, :1142:84] wire _io_dmem_req_bits_no_resp_T_28 = _io_dmem_req_bits_no_resp_T_26 & _io_dmem_req_bits_no_resp_T_27; // @[RocketCore.scala:1142:{60,72,84}] assign _io_dmem_req_bits_no_resp_T_29 = _io_dmem_req_bits_no_resp_T_25 \| _io_dmem_req_bits_no_resp_T_28; // @[RocketCore.scala:1142:{31,56,72}] assign io_dmem_req_bits_no_resp_0 = _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:153:7, :1142:56] wire [76:0] _io_dmem_s1_data_data_T = mem_ctrl_fp ? {13'h0, io_fpu_store_data_0} : mem_reg_rs2; // @[RocketCore.scala:153:7, :244:21, :283:24, :1148:63] assign io_dmem_s1_data_data_0 = _io_dmem_s1_data_data_T[63:0]; // @[RocketCore.scala:153:7, :1148:{24,63}] wire _io_dmem_s1_kill_T = killm_common \| mem_ldst_xcpt; // @[RocketCore.scala:700:68, :1151:35, :1278:14] wire _io_dmem_s1_kill_T_1 = _io_dmem_s1_kill_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :1151:{35,52}] assign _io_dmem_s1_kill_T_2 = _io_dmem_s1_kill_T_1 \| vec_kill_mem; // @[RocketCore.scala:697:52, :1151:{52,68}] assign io_dmem_s1_kill_0 = _io_dmem_s1_kill_T_2; // @[RocketCore.scala:153:7, :1151:68] wire _io_dmem_keep_clock_enabled_T = _ibuf_io_inst_0_valid & id_ctrl_mem; // @[RocketCore.scala:311:20, :321:21, :1154:55] wire _io_dmem_keep_clock_enabled_T_1 = ~_csr_io_csr_stall; // @[RocketCore.scala:341:19, :1154:73] assign _io_dmem_keep_clock_enabled_T_2 = _io_dmem_keep_clock_enabled_T & _io_dmem_keep_clock_enabled_T_1; // @[RocketCore.scala:1154:{55,70,73}] assign io_dmem_keep_clock_enabled_0 = _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:153:7, :1154:70] wire _io_rocc_cmd_valid_T_1 = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47, :1156:56] assign _io_rocc_cmd_valid_T_2 = _io_rocc_cmd_valid_T & _io_rocc_cmd_valid_T_1; // @[RocketCore.scala:1156:{37,53,56}] assign io_rocc_cmd_valid = _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:153:7, :1156:53] wire [6:0] _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_funct = _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rs2 = _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rs1 = _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xd = _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xs1 = _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xs2 = _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rd = _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:153:7, :1159:48] wire [6:0] _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_opcode = _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:153:7, :1159:48] assign _io_rocc_cmd_bits_inst_T = _io_rocc_cmd_bits_inst_WIRE_1[6:0]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_opcode = _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_1 = _io_rocc_cmd_bits_inst_WIRE_1[11:7]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rd = _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_2 = _io_rocc_cmd_bits_inst_WIRE_1[12]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xs2 = _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_3 = _io_rocc_cmd_bits_inst_WIRE_1[13]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xs1 = _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_4 = _io_rocc_cmd_bits_inst_WIRE_1[14]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xd = _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_5 = _io_rocc_cmd_bits_inst_WIRE_1[19:15]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rs1 = _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_6 = _io_rocc_cmd_bits_inst_WIRE_1[24:20]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rs2 = _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_7 = _io_rocc_cmd_bits_inst_WIRE_1[31:25]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_funct = _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_rs2 = wb_reg_rs2[63:0]; // @[RocketCore.scala:153:7, :303:23, :1161:24] wire [4:0] _unpause_T = _csr_io_time[4:0]; // @[RocketCore.scala:341:19, :1164:28] wire _unpause_T_1 = _unpause_T == 5'h0; // @[RocketCore.scala:1164:{28,62}] wire _unpause_T_2 = _unpause_T_1 \| _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19, :1164:{62,70}] wire _unpause_T_3 = _unpause_T_2 \| io_dmem_perf_release_0; // @[RocketCore.scala:153:7, :1164:{70,94}] wire unpause = _unpause_T_3 \| take_pc_mem_wb; // @[RocketCore.scala:307:35, :1164:{94,118}] reg icache_blocked_REG; // @[RocketCore.scala:1183:55] wire _icache_blocked_T = io_imem_resp_valid_0 \| icache_blocked_REG; // @[RocketCore.scala:153:7, :1183:{45,55}] wire icache_blocked = ~_icache_blocked_T; // @[RocketCore.scala:1183:{24,45}] wire _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1192:52] wire [63:0] _coreMonitorBundle_pc_T_3; // @[package.scala:132:15] wire _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1194:37] wire [4:0] _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1198:42] wire [4:0] _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1200:42] wire coreMonitorBundle_excpt; // @[RocketCore.scala:1186:31] wire [2:0] coreMonitorBundle_priv_mode; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_hartid; // @[RocketCore.scala:1186:31] wire [31:0] coreMonitorBundle_timer; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_valid; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_pc; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_wrenx; // @[RocketCore.scala:1186:31] wire [4:0] coreMonitorBundle_rd0src; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_rd0val; // @[RocketCore.scala:1186:31] wire [4:0] coreMonitorBundle_rd1src; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_rd1val; // @[RocketCore.scala:1186:31] wire [31:0] coreMonitorBundle_inst; // @[RocketCore.scala:1186:31] wire [63:0] _GEN_68 = {63'h0, io_hartid_0}; // @[RocketCore.scala:153:7, :1190:28] assign coreMonitorBundle_hartid = _GEN_68; // @[RocketCore.scala:1186:31, :1190:28] wire [63:0] xrfWriteBundle_hartid; // @[RocketCore.scala:1249:28] assign xrfWriteBundle_hartid = _GEN_68; // @[RocketCore.scala:1190:28, :1249:28] assign coreMonitorBundle_timer = _coreMonitorBundle_timer_T; // @[RocketCore.scala:1186:31, :1191:41] wire _coreMonitorBundle_valid_T = ~_csr_io_trace_0_exception; // @[RocketCore.scala:341:19, :1192:55] assign _coreMonitorBundle_valid_T_1 = _csr_io_trace_0_valid & _coreMonitorBundle_valid_T; // @[RocketCore.scala:341:19, :1192:{52,55}] assign coreMonitorBundle_valid = _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1186:31, :1192:52] wire [39:0] _coreMonitorBundle_pc_T; // @[RocketCore.scala:1193:48] wire _coreMonitorBundle_pc_T_1 = _coreMonitorBundle_pc_T[39]; // @[package.scala:132:38] wire [23:0] _coreMonitorBundle_pc_T_2 = {24{_coreMonitorBundle_pc_T_1}}; // @[package.scala:132:{20,38}] assign _coreMonitorBundle_pc_T_3 = {_coreMonitorBundle_pc_T_2, _coreMonitorBundle_pc_T}; // @[package.scala:132:{15,20}] assign coreMonitorBundle_pc = _coreMonitorBundle_pc_T_3; // @[package.scala:132:15] wire _coreMonitorBundle_wrenx_T = ~wb_set_sboard; // @[RocketCore.scala:756:69, :1194:40] assign _coreMonitorBundle_wrenx_T_1 = wb_wen & _coreMonitorBundle_wrenx_T; // @[RocketCore.scala:816:25, :1194:{37,40}] assign coreMonitorBundle_wrenx = _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1186:31, :1194:37] assign _coreMonitorBundle_rd0src_T = wb_reg_inst[19:15]; // @[RocketCore.scala:300:24, :1198:42] assign coreMonitorBundle_rd0src = _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1186:31, :1198:42] reg [63:0] coreMonitorBundle_rd0val_REG; // @[RocketCore.scala:1199:46] reg [63:0] coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1199:38] assign coreMonitorBundle_rd0val = coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1186:31, :1199:38] assign _coreMonitorBundle_rd1src_T = wb_reg_inst[24:20]; // @[RocketCore.scala:300:24, :1200:42] assign coreMonitorBundle_rd1src = _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1186:31, :1200:42] reg [63:0] coreMonitorBundle_rd1val_REG; // @[RocketCore.scala:1201:46] reg [63:0] coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1201:38] assign coreMonitorBundle_rd1val = coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1186:31, :1201:38]
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_220( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_476 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_139( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_153 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_511( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_255 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_32( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File BaseTile.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util.{log2Ceil, log2Up} import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.bundlebridge._ import freechips.rocketchip.resources.{PropertyMap, PropertyOption, ResourceReference, DTSTimebase} import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode} import freechips.rocketchip.rocket.{ICacheParams, DCacheParams, BTBParams, ASIdBits, VMIdBits, TraceAux, BPWatch} import freechips.rocketchip.subsystem.{ HierarchicalElementParams, InstantiableHierarchicalElementParams, HierarchicalElementCrossingParamsLike, CacheBlockBytes, SystemBusKey, BaseHierarchicalElement, InsertTimingClosureRegistersOnHartIds, BaseHierarchicalElementModuleImp } import freechips.rocketchip.tilelink.{TLEphemeralNode, TLOutwardNode, TLNode, TLFragmenter, EarlyAck, TLWidthWidget, TLManagerParameters, ManagerUnification} import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters} import freechips.rocketchip.util.{TraceCoreParams, TraceCoreInterface} import freechips.rocketchip.resources.{BigIntToProperty, IntToProperty, StringToProperty} import freechips.rocketchip.util.BooleanToAugmentedBoolean case object TileVisibilityNodeKey extends Field[TLEphemeralNode] case object TileKey extends Field[TileParams] case object LookupByHartId extends Field[LookupByHartIdImpl] trait TileParams extends HierarchicalElementParams { val core: CoreParams val icache: Option[ICacheParams] val dcache: Option[DCacheParams] val btb: Option[BTBParams] val tileId: Int // may not be hartid val blockerCtrlAddr: Option[BigInt] } abstract class InstantiableTileParams[TileType <: BaseTile] extends InstantiableHierarchicalElementParams[TileType] with TileParams { def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl) (implicit p: Parameters): TileType } /** These parameters values are not computed based on diplomacy negotiation * and so are safe to use while diplomacy itself is running. / trait HasNonDiplomaticTileParameters { implicit val p: Parameters def tileParams: TileParams = p(TileKey) def usingVM: Boolean = tileParams.core.useVM def usingUser: Boolean = tileParams.core.useUser \|\| usingSupervisor def usingSupervisor: Boolean = tileParams.core.hasSupervisorMode def usingHypervisor: Boolean = usingVM && tileParams.core.useHypervisor def usingDebug: Boolean = tileParams.core.useDebug def usingRoCC: Boolean = !p(BuildRoCC).isEmpty def usingBTB: Boolean = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0 def usingPTW: Boolean = usingVM def usingDataScratchpad: Boolean = tileParams.dcache.flatMap(_.scratch).isDefined def xLen: Int = tileParams.core.xLen def xBytes: Int = xLen / 8 def iLen: Int = 32 def pgIdxBits: Int = 12 def pgLevelBits: Int = 10 - log2Ceil(xLen / 32) def pgLevels: Int = tileParams.core.pgLevels def maxSVAddrBits: Int = pgIdxBits + pgLevels pgLevelBits def maxHypervisorExtraAddrBits: Int = 2 def hypervisorExtraAddrBits: Int = { if (usingHypervisor) maxHypervisorExtraAddrBits else 0 } def maxHVAddrBits: Int = maxSVAddrBits + hypervisorExtraAddrBits def minPgLevels: Int = { val res = xLen match { case 32 => 2; case 64 => 3 } require(pgLevels >= res) res } def asIdBits: Int = p(ASIdBits) def vmIdBits: Int = p(VMIdBits) lazy val maxPAddrBits: Int = { require(xLen == 32 \|\| xLen == 64, s"Only XLENs of 32 or 64 are supported, but got $xLen") xLen match { case 32 => 34; case 64 => 56 } } def tileId: Int = tileParams.tileId def cacheBlockBytes = p(CacheBlockBytes) def lgCacheBlockBytes = log2Up(cacheBlockBytes) def masterPortBeatBytes = p(SystemBusKey).beatBytes // TODO make HellaCacheIO diplomatic and remove this brittle collection of hacks // Core PTW DTIM coprocessors def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size + (tileParams.core.useVector && tileParams.core.vectorUseDCache).toInt // TODO merge with isaString in CSR.scala def isaDTS: String = { val ie = if (tileParams.core.useRVE) "e" else "i" val m = if (tileParams.core.mulDiv.nonEmpty) "m" else "" val a = if (tileParams.core.useAtomics) "a" else "" val f = if (tileParams.core.fpu.nonEmpty) "f" else "" val d = if (tileParams.core.fpu.nonEmpty && tileParams.core.fpu.get.fLen > 32) "d" else "" val c = if (tileParams.core.useCompressed) "c" else "" val b = if (tileParams.core.useBitmanip) "b" else "" val v = if (tileParams.core.useVector && tileParams.core.vLen >= 128 && tileParams.core.eLen == 64 && tileParams.core.vfLen == 64) "v" else "" val h = if (usingHypervisor) "h" else "" val ext_strs = Seq( (tileParams.core.useVector) -> s"zvl${tileParams.core.vLen}b", (tileParams.core.useVector) -> { val c = tileParams.core.vfLen match { case 64 => "d" case 32 => "f" case 0 => "x" } s"zve${tileParams.core.eLen}$c" }, (tileParams.core.useVector && tileParams.core.vfh) -> "zvfh", (tileParams.core.fpu.map(_.fLen >= 16).getOrElse(false) && tileParams.core.minFLen <= 16) -> "zfh", (tileParams.core.useZba) -> "zba", (tileParams.core.useZbb) -> "zbb", (tileParams.core.useZbs) -> "zbs", (tileParams.core.useConditionalZero) -> "zicond" ).filter(_._1).map(_._2) val multiLetterExt = ( // rdcycle[h], rdinstret[h] is implemented // rdtime[h] is not implemented, and could be provided by software emulation // see https://github.com/chipsalliance/rocket-chip/issues/3207 //Some(Seq("zicntr")) ++ Some(Seq("zicsr", "zifencei", "zihpm")) ++ Some(ext_strs) ++ Some(tileParams.core.vExts) ++ tileParams.core.customIsaExt.map(Seq(_)) ).flatten val multiLetterString = multiLetterExt.mkString("_") s"rv$xLen$ie$m$a$f$d$c$b$v$h$multiLetterString" } def tileProperties: PropertyMap = { val dcache = tileParams.dcache.filter(!_.scratch.isDefined).map(d => Map( "d-cache-block-size" -> cacheBlockBytes.asProperty, "d-cache-sets" -> d.nSets.asProperty, "d-cache-size" -> (d.nSets * d.nWays * cacheBlockBytes).asProperty) ).getOrElse(Nil) val incoherent = if (!tileParams.core.useAtomicsOnlyForIO) Nil else Map( "sifive,d-cache-incoherent" -> Nil) val icache = tileParams.icache.map(i => Map( "i-cache-block-size" -> cacheBlockBytes.asProperty, "i-cache-sets" -> i.nSets.asProperty, "i-cache-size" -> (i.nSets * i.nWays * cacheBlockBytes).asProperty) ).getOrElse(Nil) val dtlb = tileParams.dcache.filter(_ => tileParams.core.useVM).map(d => Map( "d-tlb-size" -> (d.nTLBWays * d.nTLBSets).asProperty, "d-tlb-sets" -> d.nTLBSets.asProperty)).getOrElse(Nil) val itlb = tileParams.icache.filter(_ => tileParams.core.useVM).map(i => Map( "i-tlb-size" -> (i.nTLBWays * i.nTLBSets).asProperty, "i-tlb-sets" -> i.nTLBSets.asProperty)).getOrElse(Nil) val mmu = if (tileParams.core.useVM) { if (tileParams.core.useHypervisor) { Map("tlb-split" -> Nil, "mmu-type" -> s"riscv,sv${maxSVAddrBits},sv${maxSVAddrBits}x4".asProperty) } else { Map("tlb-split" -> Nil, "mmu-type" -> s"riscv,sv$maxSVAddrBits".asProperty) } } else { Nil } val pmp = if (tileParams.core.nPMPs > 0) Map( "riscv,pmpregions" -> tileParams.core.nPMPs.asProperty, "riscv,pmpgranularity" -> tileParams.core.pmpGranularity.asProperty) else Nil dcache ++ icache ++ dtlb ++ itlb ++ mmu ++ pmp ++ incoherent } } /** These parameters values are computed based on diplomacy negotiations * and so are NOT safe to use while diplomacy itself is running. * Only mix this trait into LazyModuleImps, Modules, Bundles, Data, etc. / trait HasTileParameters extends HasNonDiplomaticTileParameters { protected def tlBundleParams = p(TileVisibilityNodeKey).edges.out.head.bundle lazy val paddrBits: Int = { val bits = tlBundleParams.addressBits require(bits <= maxPAddrBits, s"Requested $bits paddr bits, but since xLen is $xLen only $maxPAddrBits will fit") bits } def vaddrBits: Int = if (usingVM) { val v = maxHVAddrBits require(v == xLen \|\| xLen > v && v > paddrBits) v } else { // since virtual addresses sign-extend but physical addresses // zero-extend, make room for a zero sign bit for physical addresses (paddrBits + 1) min xLen } def vpnBits: Int = vaddrBits - pgIdxBits def ppnBits: Int = paddrBits - pgIdxBits def vpnBitsExtended: Int = vpnBits + (if (vaddrBits < xLen) 1 + usingHypervisor.toInt else 0) def vaddrBitsExtended: Int = vpnBitsExtended + pgIdxBits } /* Base class for all Tiles that use TileLink / abstract class BaseTile private (crossing: ClockCrossingType, q: Parameters) extends BaseHierarchicalElement(crossing)(q) with HasNonDiplomaticTileParameters { // Public constructor alters Parameters to supply some legacy compatibility keys def this(tileParams: TileParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, p: Parameters) = { this(crossing, p.alterMap(Map( TileKey -> tileParams, TileVisibilityNodeKey -> TLEphemeralNode()(ValName("tile_master")), LookupByHartId -> lookup ))) } def intInwardNode: IntInwardNode // Interrupts to the core from external devices def intOutwardNode: Option[IntOutwardNode] // Interrupts from tile-internal devices (e.g. BEU) def haltNode: IntOutwardNode // Unrecoverable error has occurred; suggest reset def ceaseNode: IntOutwardNode // Tile has ceased to retire instructions def wfiNode: IntOutwardNode // Tile is waiting for an interrupt def module: BaseTileModuleImp[BaseTile] /* Node for broadcasting a hart id to diplomatic consumers within the tile. / val hartIdNexusNode: BundleBridgeNode[UInt] = BundleBroadcast[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) /* Node for consuming the hart id input in tile-layer Chisel logic. / val hartIdSinkNode = BundleBridgeSink[UInt]() /* Node for driving a hart id input, which is to be broadcast to units within the tile. * * Making this id value an IO and then using it to do lookups of information * that would make otherwise-homogeneous tiles heterogeneous is a useful trick * to enable deduplication of tiles for hierarchical P&R flows. / val hartIdNode: BundleBridgeInwardNode[UInt] = hartIdSinkNode := hartIdNexusNode := BundleBridgeNameNode("hartid") /* Node for broadcasting a reset vector to diplomatic consumers within the tile. / val resetVectorNexusNode: BundleBridgeNode[UInt] = BundleBroadcast[UInt]() /* Node for consuming the reset vector input in tile-layer Chisel logic. * * Its width is sized by looking at the size of the address space visible * on the tile's master ports, but this lookup is not evaluated until * diplomacy has completed and Chisel elaboration has begun. / val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(visiblePhysAddrBits.W))) /* Node for supplying a reset vector that processors in this tile might begin fetching instructions from as they come out of reset. / val resetVectorNode: BundleBridgeInwardNode[UInt] = resetVectorSinkNode := resetVectorNexusNode := BundleBridgeNameNode("reset_vector") /* Nodes for connecting NMI interrupt sources and vectors into the tile / val nmiSinkNode = Option.when(tileParams.core.useNMI) { BundleBridgeSink[NMI](Some(() => new NMI(visiblePhysAddrBits))) } val nmiNode: Option[BundleBridgeInwardNode[NMI]] = nmiSinkNode.map(_ := BundleBridgeNameNode("nmi")) /* Node for broadcasting an address prefix to diplomatic consumers within the tile. * * The prefix should be applied by consumers by or-ing ouputs of this node * with a static base address (which is looked up based on the driven hartid value). / val mmioAddressPrefixNexusNode = BundleBridgeNexus[UInt]( inputFn = BundleBridgeNexus.orReduction[UInt](registered = false) _, outputFn = BundleBridgeNexus.fillN[UInt](registered = false) _, default = Some(() => 0.U(1.W)) ) /* Node for external drivers to prefix base addresses of MMIO devices to which the core has a direct access path. / val mmioAddressPrefixNode: BundleBridgeInwardNode[UInt] = mmioAddressPrefixNexusNode := BundleBridgeNameNode("mmio_address_prefix") // TODO: Any node marked "consumed by the core" or "driven by the core" // should be moved to either be: a member of a specific BaseTile subclass, // or actually just a member of the core's LazyModule itself, // assuming the core itself is diplomatic. // Then these nodes should just become IdentityNodes of their respective type protected def traceRetireWidth = tileParams.core.retireWidth /** Node for the core to drive legacy "raw" instruction trace. / val traceSourceNode = BundleBridgeSource(() => new TraceBundle) /* Node for external consumers to source a legacy instruction trace from the core. / val traceNode = traceSourceNode def traceCoreParams = new TraceCoreParams() /* Node for core to drive instruction trace conforming to RISC-V Processor Trace spec V1.0 / val traceCoreSourceNode = BundleBridgeSource(() => new TraceCoreInterface(traceCoreParams)) /* Node for external consumers to source a V1.0 instruction trace from the core. / val traceCoreNode = traceCoreSourceNode /* Node to broadcast collected trace sideband signals into the tile. / val traceAuxNexusNode = BundleBridgeNexus[TraceAux](default = Some(() => { val aux = Wire(new TraceAux) aux.stall := false.B aux.enable := false.B aux })) /* Trace sideband signals to be consumed by the core. / val traceAuxSinkNode = BundleBridgeSink[TraceAux]() /* Trace sideband signals collected here to be driven into the tile. / val traceAuxNode: BundleBridgeInwardNode[TraceAux] = traceAuxSinkNode := traceAuxNexusNode := BundleBridgeNameNode("trace_aux") /** Node for watchpoints to control trace driven by core. / val bpwatchSourceNode = BundleBridgeSource(() => Vec(tileParams.core.nBreakpoints, new BPWatch(traceRetireWidth))) /* Node to broadcast watchpoints to control trace. / val bpwatchNexusNode = BundleBroadcast[Vec[BPWatch]]() /* Node for external consumers to source watchpoints to control trace. / val bpwatchNode: BundleBridgeOutwardNode[Vec[BPWatch]] = BundleBridgeNameNode("bpwatch") := bpwatchNexusNode := bpwatchSourceNode /** Helper function for connecting MMIO devices inside the tile to an xbar that will make them visible to external masters. / def connectTLSlave(xbarNode: TLOutwardNode, node: TLNode, bytes: Int): Unit = { DisableMonitors { implicit p => (Seq(node, TLFragmenter(bytes, cacheBlockBytes, earlyAck=EarlyAck.PutFulls)) ++ (xBytes != bytes).option(TLWidthWidget(xBytes))) .foldRight(xbarNode)(_ := _) } } def connectTLSlave(node: TLNode, bytes: Int): Unit = { connectTLSlave(tlSlaveXbar.node, node, bytes) } /** TileLink node which represents the view that the intra-tile masters have of the rest of the system. / val visibilityNode = p(TileVisibilityNodeKey) protected def visibleManagers = visibilityNode.edges.out.flatMap(_.manager.managers) protected def visiblePhysAddrBits = visibilityNode.edges.out.head.bundle.addressBits def unifyManagers: List[TLManagerParameters] = ManagerUnification(visibleManagers) /* Finds resource labels for all the outward caches. / def nextLevelCacheProperty: PropertyOption = { val outer = visibleManagers .filter(_.supportsAcquireB) .flatMap(_.resources.headOption) .map(_.owner.label) .distinct if (outer.isEmpty) None else Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList) } /* Create a DTS representation of this "cpu". / def cpuProperties: PropertyMap = Map( "device_type" -> "cpu".asProperty, "status" -> "okay".asProperty, "clock-frequency" -> tileParams.core.bootFreqHz.asProperty, "riscv,isa" -> isaDTS.asProperty, "timebase-frequency" -> p(DTSTimebase).asProperty, "hardware-exec-breakpoint-count" -> tileParams.core.nBreakpoints.asProperty ) /* Can be used to access derived params calculated by HasCoreParameters * * However, callers must ensure they do not access a diplomatically-determined parameter * before the graph in question has been fully connected. / protected lazy val lazyCoreParamsView: HasCoreParameters = { class C(implicit val p: Parameters) extends HasCoreParameters new C } this.suggestName(tileParams.baseName) } abstract class BaseTileModuleImp[+L <: BaseTile](outer: L) extends BaseHierarchicalElementModuleImp[L](outer) File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSetsblockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined \|\| nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined \|\| nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBitsrowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /* Bundle definitions for HellaCache interfaces / trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /* Base classes for Diplomatic TL2 HellaCaches / abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB \|\| !m.executable \|\| m.regionType >= RegionType.TRACKED \|\| m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM \|\| cfg.blockBytes cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush \|\| cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated / case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /* Mix-ins for constructing tiles that have a HellaCache / trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /* Metadata array used for all HellaCaches / class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst \|\| io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst } File Interrupts.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.resources.{Device, DeviceSnippet, Description, ResourceBinding, ResourceInt} import freechips.rocketchip.interrupts.{IntIdentityNode, IntSinkNode, IntSinkPortSimple, IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.util.CanHaveErrors import freechips.rocketchip.resources.{IntToProperty, StringToProperty} import freechips.rocketchip.util.BooleanToAugmentedBoolean class NMI(val w: Int) extends Bundle { val rnmi = Bool() val rnmi_interrupt_vector = UInt(w.W) val rnmi_exception_vector = UInt(w.W) } class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) { val debug = Bool() val mtip = Bool() val msip = Bool() val meip = Bool() val seip = usingSupervisor.option(Bool()) val lip = Vec(coreParams.nLocalInterrupts, Bool()) val nmi = usingNMI.option(new NMI(resetVectorLen)) } // Use diplomatic interrupts to external interrupts from the subsystem into the tile trait SinksExternalInterrupts { this: BaseTile => val intInwardNode = intXbar.intnode := IntIdentityNode()(ValName("int_local")) protected val intSinkNode = IntSinkNode(IntSinkPortSimple()) intSinkNode := intXbar.intnode def cpuDevice: Device val intcDevice = new DeviceSnippet { override def parent = Some(cpuDevice) def describe(): Description = { Description("interrupt-controller", Map( "compatible" -> "riscv,cpu-intc".asProperty, "interrupt-controller" -> Nil, "#interrupt-cells" -> 1.asProperty)) } } ResourceBinding { intSinkNode.edges.in.flatMap(_.source.sources).map { case s => for (i <- s.range.start until s.range.end) { csrIntMap.lift(i).foreach { j => s.resources.foreach { r => r.bind(intcDevice, ResourceInt(j)) } } } } } // TODO: the order of the following two functions must match, and // also match the order which things are connected to the // per-tile crossbar in subsystem.HasTiles.connectInterrupts // debug, msip, mtip, meip, seip, lip offsets in CSRs def csrIntMap: List[Int] = { val nlips = tileParams.core.nLocalInterrupts val seip = if (usingSupervisor) Seq(9) else Nil List(65535, 3, 7, 11) ++ seip ++ List.tabulate(nlips)(_ + 16) } // go from flat diplomatic Interrupts to bundled TileInterrupts def decodeCoreInterrupts(core: TileInterrupts): Unit = { val async_ips = Seq(core.debug) val periph_ips = Seq( core.msip, core.mtip, core.meip) val seip = if (core.seip.isDefined) Seq(core.seip.get) else Nil val core_ips = core.lip val (interrupts, _) = intSinkNode.in(0) (async_ips ++ periph_ips ++ seip ++ core_ips).zip(interrupts).foreach { case(c, i) => c := i } } } trait SourcesExternalNotifications { this: BaseTile => // Report unrecoverable error conditions val haltNode = IntSourceNode(IntSourcePortSimple()) def reportHalt(could_halt: Option[Bool]): Unit = { val (halt_and_catch_fire, _) = haltNode.out(0) halt_and_catch_fire(0) := could_halt.map(RegEnable(true.B, false.B, _)).getOrElse(false.B) } def reportHalt(errors: Seq[CanHaveErrors]): Unit = { reportHalt(errors.flatMap(_.uncorrectable).map(_.valid).reduceOption(_\|\|_)) } // Report when the tile has ceased to retire instructions val ceaseNode = IntSourceNode(IntSourcePortSimple()) def reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8): Unit = { def waitForQuiescence(cease: Bool): Bool = { // don't report cease until signal is stable for longer than any pipeline depth val count = RegInit(0.U(log2Ceil(quiescenceCycles + 1).W)) val saturated = count >= quiescenceCycles.U when (!cease) { count := 0.U } when (cease && !saturated) { count := count + 1.U } saturated } val (cease, _) = ceaseNode.out(0) cease(0) := could_cease.map{ c => val cease = (waitForQuiescence(c)) // Test-Only Code -- val prev_cease = RegNext(cease, false.B) assert(!(prev_cease & !cease), "CEASE line can not glitch once raised") cease }.getOrElse(false.B) } // Report when the tile is waiting for an interrupt val wfiNode = IntSourceNode(IntSourcePortSimple()) def reportWFI(could_wfi: Option[Bool]): Unit = { val (wfi, _) = wfiNode.out(0) wfi(0) := could_wfi.map(RegNext(_, init=false.B)).getOrElse(false.B) } } File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in \|\| corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ \|\| !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready \|\| !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel \| count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)outByteswidth-1, ioutByteswidth) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes8-1, edgeOut.manager.beatBytes8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File Frontend.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.tile.{CoreBundle, BaseTile} import freechips.rocketchip.tilelink.{TLWidthWidget, TLEdgeOut} import freechips.rocketchip.util.{ClockGate, ShiftQueue, property} import freechips.rocketchip.util.UIntToAugmentedUInt class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) { val pc = UInt(vaddrBitsExtended.W) val speculative = Bool() } class FrontendExceptions extends Bundle { val pf = new Bundle { val inst = Bool() } val gf = new Bundle { val inst = Bool() } val ae = new Bundle { val inst = Bool() } } class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) { val btb = new BTBResp val pc = UInt(vaddrBitsExtended.W) // ID stage PC val data = UInt((fetchWidth coreInstBits).W) val mask = Bits(fetchWidth.W) val xcpt = new FrontendExceptions val replay = Bool() } class FrontendPerfEvents extends Bundle { val acquire = Bool() val tlbMiss = Bool() } class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) { val might_request = Output(Bool()) val clock_enabled = Input(Bool()) val req = Valid(new FrontendReq) val sfence = Valid(new SFenceReq) val resp = Flipped(Decoupled(new FrontendResp)) val gpa = Flipped(Valid(UInt(vaddrBitsExtended.W))) val gpa_is_pte = Input(Bool()) val btb_update = Valid(new BTBUpdate) val bht_update = Valid(new BHTUpdate) val ras_update = Valid(new RASUpdate) val flush_icache = Output(Bool()) val npc = Input(UInt(vaddrBitsExtended.W)) val perf = Input(new FrontendPerfEvents()) val progress = Output(Bool()) } class Frontend(val icacheParams: ICacheParams, tileId: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new FrontendModule(this) val icache = LazyModule(new ICache(icacheParams, tileId)) val masterNode = icache.masterNode val slaveNode = icache.slaveNode val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(masterNode.edges.out.head.bundle.addressBits.W))) } class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p) { val cpu = Flipped(new FrontendIO()) val ptw = new TLBPTWIO() val errors = new ICacheErrors } class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) with HasRocketCoreParameters with HasL1ICacheParameters { val io = IO(new FrontendBundle(outer)) val io_reset_vector = outer.resetVectorSinkNode.bundle implicit val edge: TLEdgeOut = outer.masterNode.edges.out(0) val icache = outer.icache.module require(fetchWidthcoreInstBytes == outer.icacheParams.fetchBytes) val fq = withReset(reset.asBool \|\| io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cpu.might_request io.cpu.clock_enabled := clock_en assert(!(io.cpu.req.valid \|\| io.cpu.sfence.valid \|\| io.cpu.flush_icache \|\| io.cpu.bht_update.valid \|\| io.cpu.btb_update.valid) \|\| io.cpu.might_request) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "icache_clock_gate") icache.clock := gated_clock icache.io.clock_enabled := clock_en withClock (gated_clock) { // entering gated-clock domain val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays, outer.icacheParams.nTLBBasePageSectors, outer.icacheParams.nTLBSuperpages))) val s1_valid = Reg(Bool()) val s2_valid = RegInit(false.B) val s0_fq_has_space = !fq.io.mask(fq.io.mask.getWidth-3) \|\| (!fq.io.mask(fq.io.mask.getWidth-2) && (!s1_valid \|\| !s2_valid)) \|\| (!fq.io.mask(fq.io.mask.getWidth-1) && (!s1_valid && !s2_valid)) val s0_valid = io.cpu.req.valid \|\| s0_fq_has_space s1_valid := s0_valid val s1_pc = Reg(UInt(vaddrBitsExtended.W)) val s1_speculative = Reg(Bool()) val s2_pc = RegInit(t = UInt(vaddrBitsExtended.W), alignPC(io_reset_vector)) val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B val s2_btb_resp_bits = Reg(new BTBResp) val s2_btb_taken = s2_btb_resp_valid && s2_btb_resp_bits.taken val s2_tlb_resp = Reg(tlb.io.resp.cloneType) val s2_xcpt = s2_tlb_resp.ae.inst \|\| s2_tlb_resp.pf.inst \|\| s2_tlb_resp.gf.inst val s2_speculative = RegInit(false.B) val s2_partial_insn_valid = RegInit(false.B) val s2_partial_insn = Reg(UInt(coreInstBits.W)) val wrong_path = RegInit(false.B) val s1_base_pc = ~(~s1_pc \| (fetchBytes - 1).U) val ntpc = s1_base_pc + fetchBytes.U val predicted_npc = WireDefault(ntpc) val predicted_taken = WireDefault(false.B) val s2_replay = Wire(Bool()) s2_replay := (s2_valid && !fq.io.enq.fire) \|\| RegNext(s2_replay && !s0_valid, true.B) val npc = Mux(s2_replay, s2_pc, predicted_npc) s1_pc := io.cpu.npc // consider RVC fetches across blocks to be non-speculative if the first // part was non-speculative val s0_speculative = if (usingCompressed) s1_speculative \|\| s2_valid && !s2_speculative \|\| predicted_taken else true.B s1_speculative := Mux(io.cpu.req.valid, io.cpu.req.bits.speculative, Mux(s2_replay, s2_speculative, s0_speculative)) val s2_redirect = WireDefault(io.cpu.req.valid) s2_valid := false.B when (!s2_replay) { s2_valid := !s2_redirect s2_pc := s1_pc s2_speculative := s1_speculative s2_tlb_resp := tlb.io.resp } val recent_progress_counter_init = 3.U val recent_progress_counter = RegInit(recent_progress_counter_init) val recent_progress = recent_progress_counter > 0.U when(io.ptw.req.fire && recent_progress) { recent_progress_counter := recent_progress_counter - 1.U } when(io.cpu.progress) { recent_progress_counter := recent_progress_counter_init } val s2_kill_speculative_tlb_refill = s2_speculative && !recent_progress io.ptw <> tlb.io.ptw tlb.io.req.valid := s1_valid && !s2_replay tlb.io.req.bits.cmd := M_XRD // Frontend only reads tlb.io.req.bits.vaddr := s1_pc tlb.io.req.bits.passthrough := false.B tlb.io.req.bits.size := log2Ceil(coreInstBytesfetchWidth).U tlb.io.req.bits.prv := io.ptw.status.prv tlb.io.req.bits.v := io.ptw.status.v tlb.io.sfence := io.cpu.sfence tlb.io.kill := !s2_valid \|\| s2_kill_speculative_tlb_refill icache.io.req.valid := s0_valid icache.io.req.bits.addr := io.cpu.npc icache.io.invalidate := io.cpu.flush_icache icache.io.s1_paddr := tlb.io.resp.paddr icache.io.s2_vaddr := s2_pc icache.io.s1_kill := s2_redirect \|\| tlb.io.resp.miss \|\| s2_replay val s2_can_speculatively_refill = s2_tlb_resp.cacheable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill icache.io.s2_kill := s2_speculative && !s2_can_speculatively_refill \|\| s2_xcpt icache.io.s2_cacheable := s2_tlb_resp.cacheable icache.io.s2_prefetch := s2_tlb_resp.prefetchable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableICachePrefetch fq.io.enq.valid := RegNext(s1_valid) && s2_valid && (icache.io.resp.valid \|\| (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) \|\| (!s2_tlb_resp.miss && icache.io.s2_kill)) fq.io.enq.bits.pc := s2_pc io.cpu.npc := alignPC(Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)) fq.io.enq.bits.data := icache.io.resp.bits.data fq.io.enq.bits.mask := ((1 << fetchWidth)-1).U << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes)) fq.io.enq.bits.replay := (icache.io.resp.bits.replay \|\| icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt) \|\| (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) fq.io.enq.bits.btb := s2_btb_resp_bits fq.io.enq.bits.btb.taken := s2_btb_taken fq.io.enq.bits.xcpt := s2_tlb_resp assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill)) when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true.B } if (usingBTB) { val btb = Module(new BTB) btb.io.flush := false.B btb.io.req.valid := false.B btb.io.req.bits.addr := s1_pc btb.io.btb_update := io.cpu.btb_update btb.io.bht_update := io.cpu.bht_update btb.io.ras_update.valid := false.B btb.io.ras_update.bits := DontCare btb.io.bht_advance.valid := false.B btb.io.bht_advance.bits := DontCare when (!s2_replay) { btb.io.req.valid := !s2_redirect s2_btb_resp_valid := btb.io.resp.valid s2_btb_resp_bits := btb.io.resp.bits } when (btb.io.resp.valid && btb.io.resp.bits.taken) { predicted_npc := btb.io.resp.bits.target.sextTo(vaddrBitsExtended) predicted_taken := true.B } val force_taken = io.ptw.customCSRs.bpmStatic when (io.ptw.customCSRs.flushBTB) { btb.io.flush := true.B } when (force_taken) { btb.io.bht_update.valid := false.B } val s2_base_pc = ~(~s2_pc \| (fetchBytes-1).U) val taken_idx = Wire(UInt()) val after_idx = Wire(UInt()) val useRAS = WireDefault(false.B) val updateBTB = WireDefault(false.B) // If !prevTaken, ras_update / bht_update is always invalid. taken_idx := DontCare after_idx := DontCare def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = { def insnIsRVC(bits: UInt) = bits(1,0) =/= 3.U val prevRVI = prevValid && !insnIsRVC(prevBits) val valid = fq.io.enq.bits.mask(idx) && !prevRVI val bits = fq.io.enq.bits.data(coreInstBits(idx+1)-1, coreInstBitsidx) val rvc = insnIsRVC(bits) val rviBits = Cat(bits, prevBits) val rviBranch = rviBits(6,0) === Instructions.BEQ.value.U.extract(6,0) val rviJump = rviBits(6,0) === Instructions.JAL.value.U.extract(6,0) val rviJALR = rviBits(6,0) === Instructions.JALR.value.U.extract(6,0) val rviReturn = rviJALR && !rviBits(7) && BitPat("b00?01") === rviBits(19,15) val rviCall = (rviJALR \|\| rviJump) && rviBits(7) val rvcBranch = bits === Instructions.C_BEQZ \|\| bits === Instructions.C_BNEZ val rvcJAL = (xLen == 32).B && bits === Instructions32.C_JAL val rvcJump = bits === Instructions.C_J \|\| rvcJAL val rvcImm = Mux(bits(14), new RVCDecoder(bits, xLen, fLen).bImm.asSInt, new RVCDecoder(bits, xLen, fLen).jImm.asSInt) val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0.U val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7) val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0.U val rvcCall = rvcJAL \|\| rvcJALR val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), ImmGen(IMM_SB, rviBits)) val predict_taken = s2_btb_resp_bits.bht.taken \|\| force_taken val taken = prevRVI && (rviJump \|\| rviJALR \|\| rviBranch && predict_taken) \|\| valid && (rvcJump \|\| rvcJALR \|\| rvcJR \|\| rvcBranch && predict_taken) val predictReturn = btb.io.ras_head.valid && (prevRVI && rviReturn \|\| valid && rvcReturn) val predictJump = prevRVI && rviJump \|\| valid && rvcJump val predictBranch = predict_taken && (prevRVI && rviBranch \|\| valid && rvcBranch) when (s2_valid && s2_btb_resp_valid && s2_btb_resp_bits.bridx === idx.U && valid && !rvc) { // The BTB has predicted that the middle of an RVI instruction is // a branch! Flush the BTB and the pipeline. btb.io.flush := true.B fq.io.enq.bits.replay := true.B wrong_path := true.B ccover(wrong_path, "BTB_NON_CFI_ON_WRONG_PATH", "BTB predicted a non-branch was taken while on the wrong path") } when (!prevTaken) { taken_idx := idx.U after_idx := (idx + 1).U btb.io.ras_update.valid := fq.io.enq.fire && !wrong_path && (prevRVI && (rviCall \|\| rviReturn) \|\| valid && (rvcCall \|\| rvcReturn)) btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret, Mux(Mux(prevRVI, rviCall, rvcCall), CFIType.call, Mux(Mux(prevRVI, rviBranch, rvcBranch) && !force_taken, CFIType.branch, CFIType.jump))) when (!s2_btb_taken) { when (fq.io.enq.fire && taken && !predictBranch && !predictJump && !predictReturn) { wrong_path := true.B } when (s2_valid && predictReturn) { useRAS := true.B } when (s2_valid && (predictBranch \|\| predictJump)) { val pc = s2_base_pc \| (idxcoreInstBytes).U val npc = if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm) else Mux(prevRVI, pc - coreInstBytes.U, pc).asSInt + Mux(prevRVI, rviImm, rvcImm) predicted_npc := npc.asUInt } } when (prevRVI && rviBranch \|\| valid && rvcBranch) { btb.io.bht_advance.valid := fq.io.enq.fire && !wrong_path btb.io.bht_advance.bits := s2_btb_resp_bits } when (!s2_btb_resp_valid && (predictBranch && s2_btb_resp_bits.bht.strongly_taken \|\| predictJump \|\| predictReturn)) { updateBTB := true.B } } if (idx == fetchWidth-1) { when (fq.io.enq.fire) { s2_partial_insn_valid := false.B when (valid && !prevTaken && !rvc) { s2_partial_insn_valid := true.B s2_partial_insn := bits \| 0x3.U } } prevTaken \|\| taken } else { scanInsns(idx + 1, valid, bits, prevTaken \|\| taken) } } when (!io.cpu.btb_update.valid) { val fetch_bubble_likely = !fq.io.mask(1) btb.io.btb_update.valid := fq.io.enq.fire && !wrong_path && fetch_bubble_likely && updateBTB btb.io.btb_update.bits.prediction.entry := tileParams.btb.get.nEntries.U btb.io.btb_update.bits.isValid := true.B btb.io.btb_update.bits.cfiType := btb.io.ras_update.bits.cfiType btb.io.btb_update.bits.br_pc := s2_base_pc \| (taken_idx << log2Ceil(coreInstBytes)) btb.io.btb_update.bits.pc := s2_base_pc } btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes)) val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B) when (useRAS) { predicted_npc := btb.io.ras_head.bits } when (fq.io.enq.fire && (s2_btb_taken \|\| taken)) { s2_partial_insn_valid := false.B } when (!s2_btb_taken) { when (taken) { fq.io.enq.bits.btb.bridx := taken_idx fq.io.enq.bits.btb.taken := true.B fq.io.enq.bits.btb.entry := tileParams.btb.get.nEntries.U when (fq.io.enq.fire) { s2_redirect := true.B } } } assert(!s2_partial_insn_valid \|\| fq.io.enq.bits.mask(0)) when (s2_redirect) { s2_partial_insn_valid := false.B } when (io.cpu.req.valid) { wrong_path := false.B } } io.cpu.resp <> fq.io.deq // supply guest physical address to commit stage val gpa_valid = Reg(Bool()) val gpa = Reg(UInt(vaddrBitsExtended.W)) val gpa_is_pte = Reg(Bool()) when (fq.io.enq.fire && s2_tlb_resp.gf.inst) { when (!gpa_valid) { gpa := s2_tlb_resp.gpa gpa_is_pte := s2_tlb_resp.gpa_is_pte } gpa_valid := true.B } when (io.cpu.req.valid) { gpa_valid := false.B } io.cpu.gpa.valid := gpa_valid io.cpu.gpa.bits := gpa io.cpu.gpa_is_pte := gpa_is_pte // performance events io.cpu.perf.acquire := icache.io.perf.acquire io.cpu.perf.tlbMiss := io.ptw.req.fire io.errors := icache.io.errors // gate the clock clock_en_reg := !rocketParams.clockGate.B \|\| io.cpu.might_request \|\| // chicken bit icache.io.keep_clock_enabled \|\| // I$ miss or ITIM access s1_valid \|\| s2_valid \|\| // some fetch in flight !tlb.io.req.ready \|\| // handling TLB miss !fq.io.mask(fq.io.mask.getWidth-1) // queue not full } // leaving gated-clock domain def alignPC(pc: UInt) = ~(~pc \| (coreInstBytes - 1).U) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FRONTEND_$label", "Rocket;;" + desc) } /* Mix-ins for constructing tiles that have an ICache-based pipeline frontend / trait HasICacheFrontend extends CanHavePTW { this: BaseTile => val module: HasICacheFrontendModule val frontend = LazyModule(new Frontend(tileParams.icache.get, tileId)) tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.masterNode connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes) frontend.icache.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode } frontend.icache.mmioAddressPrefixSinkNodeOpt.foreach { _ := mmioAddressPrefixNexusNode } frontend.resetVectorSinkNode := resetVectorNexusNode nPTWPorts += 1 // This should be a None in the case of not having an ITIM address, when we // don't actually use the device that is instantiated in the frontend. private val deviceOpt = if (tileParams.icache.get.itimAddr.isDefined) Some(frontend.icache.device) else None } trait HasICacheFrontendModule extends CanHavePTWModule { val outer: HasICacheFrontend ptwPorts += outer.frontend.module.io.ptw } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /* PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss / class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /* PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info / class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /* ptw access exception / val ae_ptw = Bool() /* final access exception / val ae_final = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* hypervisor read / val hr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor execute / val hx = Bool() /* PTE to refill L1TLB * * source: L2TLB / val pte = new PTE /* pte pglevel / val level = UInt(log2Ceil(pgLevels).W) /* fragmented_superpage support / val fragmented_superpage = Bool() /* homogeneous for both pma and pmp / val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /* IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) / class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /* PTW performance statistics / class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /* Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core / class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /* enable clock generated by ptw / val clock_enabled = Output(Bool()) } /* PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format / class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* global mapping / val g = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() /* valid bit / val v = Bool() /* return true if find a pointer to next level page table / def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /* return true if find a leaf PTE / def leaf(dummy: Int = 0) = v && (r \|\| (x && !w)) && a /* user read / def ur(dummy: Int = 0) = sr() && u /* user write/ def uw(dummy: Int = 0) = sw() && u /* user execute / def ux(dummy: Int = 0) = sx() && u /* supervisor read / def sr(dummy: Int = 0) = leaf() && r /* supervisor write / def sw(dummy: Int = 0) = leaf() && w && d /* supervisor execute / def sx(dummy: Int = 0) = leaf() && x /* full permission: writable and executable in user mode / def isFullPerm(dummy: Int = 0) = uw() && ux() } /* L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format / class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() } /* PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation / class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /* to n TLB / val requestor = Flipped(Vec(n, new TLBPTWIO)) /* to HellaCache / val mem = new HellaCacheIO /* to Core * * contains CSRs info and performance statistics / val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /* Arbiter to arbite request from n TLB / val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready \|\| l2_refill_wire \|\| arb.io.out.valid \|\| io.dpath.sfence.valid \|\| io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM \|\| !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /* current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} / val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /* tlb request / val r_req = Reg(new PTWReq) /* current selected way in arbitor / val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /* pte for 2-stage translation / val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /* 2-stage translation both enable / val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r \|\| tmp.w \|\| tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)pgLevelBits-1, (pgLevels-2-i)pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /* address send to mem for enquerry / val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) \| vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr / val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBitsi), r_req.addr(((pgLevelBitsi) min vpnBits)-1, 0).padTo(pgLevelBitsi))) } /* PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation / def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid \| UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 \|\| usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss \|\| io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /* the valid vec for the selected set(including n ways) / val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) \| mask g(way) := Mux(r_pte.g, g(way) \| mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) \|\| s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid \|\| (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req \|\| state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit \|\| (state =/= s_wait1) \|\| resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor \|\| pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous \|\| pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final \|\| !r_req.vstage1 \|\| aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa \|\| arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), aux_pte.ppn((pgLevels-i-1)pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req \|\| state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) \|\| (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 \|\| do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages \|\| aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf \|\| (pf && stage2) resp_hr := !stage2 \|\| (!pf && !gf && pte.ur()) resp_hw := !stage2 \|\| (!pf && !gf && pte.uw()) resp_hx := !stage2 \|\| (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), r_req.addr(((pgLevels-i-1)pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn / private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /* use hgatp and vpn to construct a new ppn / private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range / private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW / trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File HierarchicalElement.scala: package freechips.rocketchip.subsystem import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.debug.TLDebugModule import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.interrupts.IntXbar import freechips.rocketchip.prci.{ClockSinkParameters, ResetCrossingType, ClockCrossingType} import freechips.rocketchip.tile.{LookupByHartIdImpl, TraceBundle} import freechips.rocketchip.tilelink.{TLNode, TLIdentityNode, TLXbar, TLBuffer, TLInwardNode, TLOutwardNode} trait HierarchicalElementParams { val baseName: String // duplicated instances shouuld share a base name val uniqueName: String val clockSinkParams: ClockSinkParameters } abstract class InstantiableHierarchicalElementParams[ElementType <: BaseHierarchicalElement] extends HierarchicalElementParams /* An interface for describing the parameteization of how HierarchicalElements are connected to interconnects / trait HierarchicalElementCrossingParamsLike { /* The type of clock crossing that should be inserted at the element boundary. / def crossingType: ClockCrossingType /* Parameters describing the contents and behavior of the point where the element is attached as an interconnect master. / def master: HierarchicalElementPortParamsLike /* Parameters describing the contents and behavior of the point where the element is attached as an interconnect slave. / def slave: HierarchicalElementPortParamsLike /* The subnetwork location of the device selecting the apparent base address of MMIO devices inside the element / def mmioBaseAddressPrefixWhere: TLBusWrapperLocation /* Inject a reset management subgraph that effects the element child reset only / def resetCrossingType: ResetCrossingType /* Keep the element clock separate from the interconnect clock (e.g. even if they are synchronous to one another) / def forceSeparateClockReset: Boolean } /* An interface for describing the parameterization of how a particular element port is connected to an interconnect / trait HierarchicalElementPortParamsLike { /* The subnetwork location of the interconnect to which this element port should be connected. / def where: TLBusWrapperLocation /* Allows port-specific adapters to be injected into the interconnect side of the attachment point. / def injectNode(context: Attachable)(implicit p: Parameters): TLNode } abstract class BaseHierarchicalElement (val crossing: ClockCrossingType)(implicit p: Parameters) extends LazyModule()(p) with CrossesToOnlyOneClockDomain { def module: BaseHierarchicalElementModuleImp[BaseHierarchicalElement] protected val tlOtherMastersNode = TLIdentityNode() protected val tlMasterXbar = LazyModule(new TLXbar(nameSuffix = Some(s"MasterXbar_$desiredName"))) protected val tlSlaveXbar = LazyModule(new TLXbar(nameSuffix = Some(s"SlaveXbar_$desiredName"))) protected val intXbar = LazyModule(new IntXbar) def masterNode: TLOutwardNode def slaveNode: TLInwardNode /* Helper function to insert additional buffers on master ports at the boundary of the tile. * * The boundary buffering needed to cut feed-through paths is * microarchitecture specific, so this may need to be overridden * in subclasses of this class. / def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) /* Helper function to insert additional buffers on slave ports at the boundary of the tile. * * The boundary buffering needed to cut feed-through paths is * microarchitecture specific, so this may need to be overridden * in subclasses of this class. / def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) } abstract class BaseHierarchicalElementModuleImp[+L <: BaseHierarchicalElement](val outer: L) extends LazyModuleImp(outer) File RocketTile.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tile import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BasicBusBlockerParams, BasicBusBlocker} import freechips.rocketchip.diplomacy.{ AddressSet, DisableMonitors, BufferParams } import freechips.rocketchip.resources.{ SimpleDevice, Description, ResourceAnchors, ResourceBindings, ResourceBinding, Resource, ResourceAddress, } import freechips.rocketchip.interrupts.IntIdentityNode import freechips.rocketchip.tilelink.{TLIdentityNode, TLBuffer} import freechips.rocketchip.rocket.{ RocketCoreParams, ICacheParams, DCacheParams, BTBParams, HasHellaCache, HasICacheFrontend, ScratchpadSlavePort, HasICacheFrontendModule, Rocket } import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike import freechips.rocketchip.prci.{ClockSinkParameters, RationalCrossing, ClockCrossingType} import freechips.rocketchip.util.{Annotated, InOrderArbiter} import freechips.rocketchip.util.BooleanToAugmentedBoolean case class RocketTileBoundaryBufferParams(force: Boolean = false) case class RocketTileParams( core: RocketCoreParams = RocketCoreParams(), icache: Option[ICacheParams] = Some(ICacheParams()), dcache: Option[DCacheParams] = Some(DCacheParams()), btb: Option[BTBParams] = Some(BTBParams()), dataScratchpadBytes: Int = 0, tileId: Int = 0, beuAddr: Option[BigInt] = None, blockerCtrlAddr: Option[BigInt] = None, clockSinkParams: ClockSinkParameters = ClockSinkParameters(), boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None ) extends InstantiableTileParams[RocketTile] { require(icache.isDefined) require(dcache.isDefined) val baseName = "rockettile" val uniqueName = s"${baseName}_$tileId" def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): RocketTile = { new RocketTile(this, crossing, lookup) } } class RocketTile private( val rocketParams: RocketTileParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, q: Parameters) extends BaseTile(rocketParams, crossing, lookup, q) with SinksExternalInterrupts with SourcesExternalNotifications with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache with HasHellaCache with HasICacheFrontend { // Private constructor ensures altered LazyModule.p is used implicitly def this(params: RocketTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) val intOutwardNode = rocketParams.beuAddr map { _ => IntIdentityNode() } val slaveNode = TLIdentityNode() val masterNode = visibilityNode val dtim_adapter = tileParams.dcache.flatMap { d => d.scratch.map { s => LazyModule(new ScratchpadSlavePort(AddressSet.misaligned(s, d.dataScratchpadBytes), lazyCoreParamsView.coreDataBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO)) }} dtim_adapter.foreach(lm => connectTLSlave(lm.node, lm.node.portParams.head.beatBytes)) val bus_error_unit = rocketParams.beuAddr map { a => val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a), xLen/8)) intOutwardNode.get := beu.intNode connectTLSlave(beu.node, xBytes) beu } val tile_master_blocker = tileParams.blockerCtrlAddr .map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true)) .map(bp => LazyModule(new BasicBusBlocker(bp))) tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes)) // TODO: this doesn't block other masters, e.g. RoCCs tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node } masterNode := tlOtherMastersNode DisableMonitors { implicit p => tlSlaveXbar.node := slaveNode } nDCachePorts += 1 /core / + (dtim_adapter.isDefined).toInt + rocketParams.core.vector.map(_.useDCache.toInt).getOrElse(0) val dtimProperty = dtim_adapter.map(d => Map( "sifive,dtim" -> d.device.asProperty)).getOrElse(Nil) val itimProperty = frontend.icache.itimProperty.toSeq.flatMap(p => Map("sifive,itim" -> p)) val beuProperty = bus_error_unit.map(d => Map( "sifive,buserror" -> d.device.asProperty)).getOrElse(Nil) val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("sifive,rocket0", "riscv")) { override def parent = Some(ResourceAnchors.cpus) override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty ++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty) } } val vector_unit = rocketParams.core.vector.map(v => LazyModule(v.build(p))) vector_unit.foreach(vu => tlMasterXbar.node := vu.atlNode) vector_unit.foreach(vu => tlOtherMastersNode :=* vu.tlNode) ResourceBinding { Resource(cpuDevice, "reg").bind(ResourceAddress(tileId)) } override lazy val module = new RocketTileModuleImp(this) override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer() case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)) case _ => TLBuffer(BufferParams.none) } override def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer() case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none) case _ => TLBuffer(BufferParams.none) } } class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer) with HasFpuOpt with HasLazyRoCCModule with HasICacheFrontendModule { Annotated.params(this, outer.rocketParams) val core = Module(new Rocket(outer)(outer.p)) outer.vector_unit.foreach { v => core.io.vector.get <> v.module.io.core v.module.io.tlb <> outer.dcache.module.io.tlb_port } // reset vector is connected in the Frontend to s2_pc core.io.reset_vector := DontCare // Report unrecoverable error conditions; for now the only cause is cache ECC errors outer.reportHalt(List(outer.dcache.module.io.errors)) // Report when the tile has ceased to retire instructions; for now the only cause is clock gating outer.reportCease(outer.rocketParams.core.clockGate.option( !outer.dcache.module.io.cpu.clock_enabled && !outer.frontend.module.io.cpu.clock_enabled && !ptw.io.dpath.clock_enabled && core.io.cease)) outer.reportWFI(Some(core.io.wfi)) outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector outer.bus_error_unit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt beu.module.io.errors.dcache := outer.dcache.module.io.errors beu.module.io.errors.icache := outer.frontend.module.io.errors } core.io.interrupts.nmi.foreach { nmi => nmi := outer.nmiSinkNode.get.bundle } // Pass through various external constants and reports that were bundle-bridged into the tile outer.traceSourceNode.bundle <> core.io.trace core.io.traceStall := outer.traceAuxSinkNode.bundle.stall outer.bpwatchSourceNode.bundle <> core.io.bpwatch core.io.hartid := outer.hartIdSinkNode.bundle require(core.io.hartid.getWidth >= outer.hartIdSinkNode.bundle.getWidth, s"core hartid wire (${core.io.hartid.getWidth}b) truncates external hartid wire (${outer.hartIdSinkNode.bundle.getWidth}b)") // Connect the core pipeline to other intra-tile modules outer.frontend.module.io.cpu <> core.io.imem dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ?? fpuOpt foreach { fpu => core.io.fpu :<>= fpu.io.waiveAs[FPUCoreIO](_.cp_req, _.cp_resp) } if (fpuOpt.isEmpty) { core.io.fpu := DontCare } outer.vector_unit foreach { v => if (outer.rocketParams.core.vector.get.useDCache) { dcachePorts += v.module.io.dmem } else { v.module.io.dmem := DontCare } } core.io.ptw <> ptw.io.dpath // Connect the coprocessor interfaces if (outer.roccs.size > 0) { cmdRouter.get.io.in <> core.io.rocc.cmd outer.roccs.foreach{ lm => lm.module.io.exception := core.io.rocc.exception lm.module.io.fpu_req.ready := DontCare lm.module.io.fpu_resp.valid := DontCare lm.module.io.fpu_resp.bits.data := DontCare lm.module.io.fpu_resp.bits.exc := DontCare } core.io.rocc.resp <> respArb.get.io.out core.io.rocc.busy <> (cmdRouter.get.io.busy \|\| outer.roccs.map(_.module.io.busy).reduce(_ \|\| _)) core.io.rocc.interrupt := outer.roccs.map(_.module.io.interrupt).reduce(_ \|\| _) (core.io.rocc.csrs zip roccCSRIOs.flatten).foreach { t => t._2 <> t._1 } } else { // tie off core.io.rocc.cmd.ready := false.B core.io.rocc.resp.valid := false.B core.io.rocc.resp.bits := DontCare core.io.rocc.busy := DontCare core.io.rocc.interrupt := DontCare } // Dont care mem since not all RoCC need accessing memory core.io.rocc.mem := DontCare // Rocket has higher priority to DTIM than other TileLink clients outer.dtim_adapter.foreach { lm => dcachePorts += lm.module.io.dmem } // TODO eliminate this redundancy val h = dcachePorts.size val c = core.dcacheArbPorts val o = outer.nDCachePorts require(h == c, s"port list size was $h, core expected $c") require(h == o, s"port list size was $h, outer counted $o") // TODO figure out how to move the below into their respective mix-ins dcacheArb.io.requestor <> dcachePorts.toSeq ptw.io.requestor <> ptwPorts.toSeq } trait HasFpuOpt { this: RocketTileModuleImp => val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p))) fpuOpt.foreach { fpu => val nRoCCFPUPorts = outer.roccs.count(_.usesFPU) val nFPUPorts = nRoCCFPUPorts + outer.rocketParams.core.useVector.toInt if (nFPUPorts > 0) { val fpArb = Module(new InOrderArbiter(new FPInput()(outer.p), new FPResult()(outer.p), nFPUPorts)) fpu.io.cp_req <> fpArb.io.out_req fpArb.io.out_resp <> fpu.io.cp_resp val fp_rocc_ios = outer.roccs.filter(_.usesFPU).map(_.module.io) for (i <- 0 until nRoCCFPUPorts) { fpArb.io.in_req(i) <> fp_rocc_ios(i).fpu_req fp_rocc_ios(i).fpu_resp <> fpArb.io.in_resp(i) } outer.vector_unit.foreach(vu => { fpArb.io.in_req(nRoCCFPUPorts) <> vu.module.io.fp_req vu.module.io.fp_resp <> fpArb.io.in_resp(nRoCCFPUPorts) }) } else { fpu.io.cp_req.valid := false.B fpu.io.cp_req.bits := DontCare fpu.io.cp_resp.ready := false.B } } } File BundleBridgeNexus.scala: package org.chipsalliance.diplomacy.bundlebridge import chisel3.{chiselTypeOf, ActualDirection, Data, Reg} import chisel3.reflect.DataMirror import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyRawModuleImp} class BundleBridgeNexus[T <: Data]( inputFn: Seq[T] => T, outputFn: (T, Int) => Seq[T], default: Option[() => T] = None, inputRequiresOutput: Boolean = false, override val shouldBeInlined: Boolean = true )( implicit p: Parameters) extends LazyModule { val node = BundleBridgeNexusNode[T](default, inputRequiresOutput) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val defaultWireOpt = default.map(_()) val inputs: Seq[T] = node.in.map(_._1) inputs.foreach { i => require( DataMirror.checkTypeEquivalence(i, inputs.head), s"${node.context} requires all inputs have equivalent Chisel Data types, but got\n$i\nvs\n${inputs.head}" ) } inputs.flatMap(getElements).foreach { elt => DataMirror.directionOf(elt) match { case ActualDirection.Output => () case ActualDirection.Unspecified => () case _ => require(false, s"${node.context} can only be used with Output-directed Bundles") } } val outputs: Seq[T] = if (node.out.size > 0) { val broadcast: T = if (inputs.size >= 1) inputFn(inputs) else defaultWireOpt.get outputFn(broadcast, node.out.size) } else { Nil } val typeName = outputs.headOption.map(_.typeName).getOrElse("NoOutput") override def desiredName = s"BundleBridgeNexus_$typeName" node.out.map(_._1).foreach { o => require( DataMirror.checkTypeEquivalence(o, outputs.head), s"${node.context} requires all outputs have equivalent Chisel Data types, but got\n$o\nvs\n${outputs.head}" ) } require( outputs.size == node.out.size, s"${node.context} outputFn must generate one output wire per edgeOut, but got ${outputs.size} vs ${node.out.size}" ) node.out.zip(outputs).foreach { case ((out, _), bcast) => out := bcast } } } object BundleBridgeNexus { def safeRegNext[T <: Data](x: T): T = { val reg = Reg(chiselTypeOf(x)) reg := x reg } def requireOne[T <: Data](registered: Boolean)(seq: Seq[T]): T = { require(seq.size == 1, "BundleBroadcast default requires one input") if (registered) safeRegNext(seq.head) else seq.head } def orReduction[T <: Data](registered: Boolean)(seq: Seq[T]): T = { val x = seq.reduce((a, b) => (a.asUInt \| b.asUInt).asTypeOf(seq.head)) if (registered) safeRegNext(x) else x } def fillN[T <: Data](registered: Boolean)(x: T, n: Int): Seq[T] = Seq.fill(n) { if (registered) safeRegNext(x) else x } def apply[T <: Data]( inputFn: Seq[T] => T = orReduction[T](false) _, outputFn: (T, Int) => Seq[T] = fillN[T](false) _, default: Option[() => T] = None, inputRequiresOutput: Boolean = false, shouldBeInlined: Boolean = true )( implicit p: Parameters ): BundleBridgeNexusNode[T] = { val nexus = LazyModule(new BundleBridgeNexus[T](inputFn, outputFn, default, inputRequiresOutput, shouldBeInlined)) nexus.node } }	module RocketTile_1( // @[RocketTile.scala:141:7] input clock, // @[RocketTile.scala:141:7] input reset, // @[RocketTile.scala:141:7] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_wfi_out_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25] output [39:0] auto_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25] output [31:0] auto_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25] output [2:0] auto_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25] output [39:0] auto_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_time, // @[LazyModuleImp.scala:107:25] input [1:0] auto_hartid_in // @[LazyModuleImp.scala:107:25] ); wire buffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_e_ready; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_b_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire [15:0] buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [15:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [127:0] widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire [15:0] widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire [15:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] broadcast_2_auto_in_0_action; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_valid_0; // @[BundleBridgeNexus.scala:20:9] wire [1:0] broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9] wire _core_io_imem_might_request; // @[RocketTile.scala:147:20] wire _core_io_imem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_imem_req_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_req_bits_speculative; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_asid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_hv; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_hg; // @[RocketTile.scala:147:20] wire _core_io_imem_resp_ready; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_valid; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_prediction_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_taken; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_prediction_mask; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_bridx; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_prediction_target; // @[RocketTile.scala:147:20] wire [4:0] _core_io_imem_btb_update_bits_prediction_entry; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_btb_update_bits_prediction_bht_history; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_bht_value; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_pc; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_target; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_isValid; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_br_pc; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_valid; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_bht_update_bits_prediction_history; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_prediction_value; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_bht_update_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_branch; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_taken; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_mispredict; // @[RocketTile.scala:147:20] wire _core_io_imem_flush_icache; // @[RocketTile.scala:147:20] wire _core_io_imem_progress; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_dmem_req_bits_addr; // @[RocketTile.scala:147:20] wire [6:0] _core_io_dmem_req_bits_tag; // @[RocketTile.scala:147:20] wire [4:0] _core_io_dmem_req_bits_cmd; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_size; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_signed; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_dprv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_dv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_no_resp; // @[RocketTile.scala:147:20] wire _core_io_dmem_s1_kill; // @[RocketTile.scala:147:20] wire [63:0] _core_io_dmem_s1_data_data; // @[RocketTile.scala:147:20] wire _core_io_dmem_keep_clock_enabled; // @[RocketTile.scala:147:20] wire [3:0] _core_io_ptw_ptbr_mode; // @[RocketTile.scala:147:20] wire [43:0] _core_io_ptw_ptbr_ppn; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_ptw_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_asid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_hv; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_hg; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_debug; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_cease; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_status_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_dprv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_v; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sd; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mpv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tsr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tw; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tvm; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_mpp; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_spp; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mpie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_spie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sie; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_spvp; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_spv; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_debug; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_cease; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_gstatus_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_dprv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_v; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sd; // @[RocketTile.scala:147:20] wire [22:0] _core_io_ptw_gstatus_zero2; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mpv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mbe; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sbe; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_sxl; // @[RocketTile.scala:147:20] wire [7:0] _core_io_ptw_gstatus_zero1; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tsr; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tw; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tvm; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_mpp; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_vs; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_spp; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mpie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_ube; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_spie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_upie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_hie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_uie; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_0_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_0_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_1_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_1_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_2_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_2_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_3_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_3_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_4_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_4_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_5_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_5_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_6_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_6_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_7_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_7_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_0_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_0_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_1_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_1_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_1_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_1_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_2_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_2_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_2_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_2_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_3_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_3_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_3_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_3_value; // @[RocketTile.scala:147:20] wire [1:0] _core_io_fpu_hartid; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_time; // @[RocketTile.scala:147:20] wire [31:0] _core_io_fpu_inst; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_fromint_data; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_fcsr_rm; // @[RocketTile.scala:147:20] wire _core_io_fpu_ll_resp_val; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_ll_resp_type; // @[RocketTile.scala:147:20] wire [4:0] _core_io_fpu_ll_resp_tag; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_ll_resp_data; // @[RocketTile.scala:147:20] wire _core_io_fpu_valid; // @[RocketTile.scala:147:20] wire _core_io_fpu_killx; // @[RocketTile.scala:147:20] wire _core_io_fpu_killm; // @[RocketTile.scala:147:20] wire _core_io_fpu_keep_clock_enabled; // @[RocketTile.scala:147:20] wire _core_io_wfi; // @[RocketTile.scala:147:20] wire _ptw_io_requestor_0_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sd; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sd; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_0_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_0_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_1_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sd; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sd; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_1_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_1_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_mem_req_valid; // @[PTW.scala:802:19] wire [39:0] _ptw_io_mem_req_bits_addr; // @[PTW.scala:802:19] wire _ptw_io_mem_req_bits_dv; // @[PTW.scala:802:19] wire _ptw_io_mem_s1_kill; // @[PTW.scala:802:19] wire _ptw_io_dpath_perf_pte_miss; // @[PTW.scala:802:19] wire _ptw_io_dpath_perf_pte_hit; // @[PTW.scala:802:19] wire _ptw_io_dpath_clock_enabled; // @[PTW.scala:802:19] wire _dcacheArb_io_requestor_0_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_nack_cause_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_uncached; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_0_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_0_resp_bits_addr; // @[HellaCache.scala:292:25] wire [6:0] _dcacheArb_io_requestor_0_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_0_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_0_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_0_s2_gpa; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_blocked; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_nack_cause_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_uncached; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_1_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_1_resp_bits_addr; // @[HellaCache.scala:292:25] wire [6:0] _dcacheArb_io_requestor_1_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_1_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_1_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_1_s2_gpa; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_blocked; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala:292:25] wire [6:0] _dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_dv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_phys; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_no_resp; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_s1_kill; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_keep_clock_enabled; // @[HellaCache.scala:292:25] wire _fpuOpt_io_fcsr_flags_valid; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_fcsr_flags_bits; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_store_data; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_toint_data; // @[RocketTile.scala:242:62] wire _fpuOpt_io_fcsr_rdy; // @[RocketTile.scala:242:62] wire _fpuOpt_io_nack_mem; // @[RocketTile.scala:242:62] wire _fpuOpt_io_illegal_rm; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ldst; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wen; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren1; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren2; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren3; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_swap12; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_swap23; // @[RocketTile.scala:242:62] wire [1:0] _fpuOpt_io_dec_typeTagIn; // @[RocketTile.scala:242:62] wire [1:0] _fpuOpt_io_dec_typeTagOut; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fromint; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_toint; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fastpipe; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fma; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_div; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_sqrt; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wflags; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_vec; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_set; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_clr; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_sboard_clra; // @[RocketTile.scala:242:62] wire _frontend_io_cpu_resp_valid; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_btb_cfiType; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_taken; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_btb_mask; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bridx; // @[Frontend.scala:393:28] wire [38:0] _frontend_io_cpu_resp_bits_btb_target; // @[Frontend.scala:393:28] wire [4:0] _frontend_io_cpu_resp_bits_btb_entry; // @[Frontend.scala:393:28] wire [7:0] _frontend_io_cpu_resp_bits_btb_bht_history; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bht_value; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_resp_bits_pc; // @[Frontend.scala:393:28] wire [31:0] _frontend_io_cpu_resp_bits_data; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_mask; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_pf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_gf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_replay; // @[Frontend.scala:393:28] wire _frontend_io_cpu_gpa_valid; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_gpa_bits; // @[Frontend.scala:393:28] wire _frontend_io_cpu_gpa_is_pte; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_npc; // @[Frontend.scala:393:28] wire _frontend_io_cpu_perf_acquire; // @[Frontend.scala:393:28] wire _frontend_io_cpu_perf_tlbMiss; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_valid; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_valid; // @[Frontend.scala:393:28] wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[Frontend.scala:393:28] wire _dcache_io_cpu_req_ready; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_nack; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_nack_cause_raw; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_uncached; // @[HellaCache.scala:278:43] wire [31:0] _dcache_io_cpu_s2_paddr; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_valid; // @[HellaCache.scala:278:43] wire [39:0] _dcache_io_cpu_resp_bits_addr; // @[HellaCache.scala:278:43] wire [6:0] _dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala:278:43] wire [4:0] _dcache_io_cpu_resp_bits_cmd; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_size; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_signed; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_dprv; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_dv; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data; // @[HellaCache.scala:278:43] wire [7:0] _dcache_io_cpu_resp_bits_mask; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_store_data; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_replay_next; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala:278:43] wire [39:0] _dcache_io_cpu_s2_gpa; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_ordered; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_store_pending; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_acquire; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_release; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_grant; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_tlbMiss; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_blocked; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_valid; // @[HellaCache.scala:278:43] wire [26:0] _dcache_io_ptw_req_bits_bits_addr; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_bits_bits_need_gpa; // @[HellaCache.scala:278:43] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[RocketTile.scala:141:7] wire [15:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[RocketTile.scala:141:7] wire [127:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[RocketTile.scala:141:7] wire [127:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[RocketTile.scala:141:7] wire auto_int_local_in_3_0_0 = auto_int_local_in_3_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_2_0_0 = auto_int_local_in_2_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_1_0_0 = auto_int_local_in_1_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_1_1_0 = auto_int_local_in_1_1; // @[RocketTile.scala:141:7] wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[RocketTile.scala:141:7] wire [1:0] auto_hartid_in_0 = auto_hartid_in; // @[RocketTile.scala:141:7] wire auto_buffer_out_a_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7] wire auto_buffer_out_c_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7] wire auto_cease_out_0 = 1'h0; // @[RocketTile.scala:141:7] wire auto_halt_out_0 = 1'h0; // @[RocketTile.scala:141:7] wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[RocketTile.scala:141:7] wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[RocketTile.scala:141:7] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire broadcast_2_auto_in_0_rvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_wvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_ivalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_2_nodeIn_0_rvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_wvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_ivalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire buffer_auto_in_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17] wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17] wire bpwatchSourceNodeOut_0_rvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_wvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_ivalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire haltNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire ceaseNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire [2:0] widget_1_auto_anon_in_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonIn_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [15:0] widget_1_auto_anon_in_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] widget_1_auto_anon_out_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] widget_1_anonOut_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] widget_1_anonIn_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [127:0] widget_1_auto_anon_in_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] widget_1_auto_anon_out_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] widget_1_anonOut_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] widget_1_anonIn_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [31:0] auto_reset_vector_in = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_in = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_out_1 = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_out_0 = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_nodeIn = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_x1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] reset_vectorOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] reset_vectorIn = 32'h10000; // @[RocketTile.scala:141:7] wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[RocketTile.scala:141:7] wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[RocketTile.scala:141:7] wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire widget_1_auto_anon_in_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire buffer_auto_out_a_ready = auto_buffer_out_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_b_valid = auto_buffer_out_b_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_b_bits_opcode = auto_buffer_out_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_b_bits_param = auto_buffer_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_b_bits_size = auto_buffer_out_b_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_b_bits_source = auto_buffer_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_b_bits_address = auto_buffer_out_b_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] buffer_auto_out_b_bits_mask = auto_buffer_out_b_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_out_b_bits_data = auto_buffer_out_b_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_b_bits_corrupt = auto_buffer_out_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_ready = auto_buffer_out_c_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_d_valid = auto_buffer_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_param = auto_buffer_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_e_ready = auto_buffer_out_e_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_e_valid; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] wire wfiNodeOut_0; // @[MixedNode.scala:542:17] wire x1_int_localIn_2_0 = auto_int_local_in_3_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_1_0 = auto_int_local_in_2_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_0 = auto_int_local_in_1_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_1 = auto_int_local_in_1_1_0; // @[RocketTile.scala:141:7] wire int_localIn_0 = auto_int_local_in_0_0_0; // @[RocketTile.scala:141:7] wire traceSourceNodeOut_insns_0_valid; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_0_insn; // @[MixedNode.scala:542:17] wire [2:0] traceSourceNodeOut_insns_0_priv; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_exception; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_insns_0_cause; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_tval; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_time; // @[MixedNode.scala:542:17] wire [1:0] hartidIn = auto_hartid_in_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_a_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_a_bits_address_0; // @[RocketTile.scala:141:7] wire [15:0] auto_buffer_out_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [127:0] auto_buffer_out_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_b_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_c_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_c_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_c_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_c_bits_address_0; // @[RocketTile.scala:141:7] wire [127:0] auto_buffer_out_c_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_c_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_ready_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_e_bits_sink_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_e_valid_0; // @[RocketTile.scala:141:7] wire auto_wfi_out_0_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7] wire [39:0] auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7] wire [2:0] auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7] wire [63:0] auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7] wire [39:0] auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7] wire [63:0] auto_trace_source_out_time_0; // @[RocketTile.scala:141:7] wire [1:0] hartidOut; // @[MixedNode.scala:542:17] wire [1:0] broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17] wire [1:0] broadcast_nodeOut; // @[MixedNode.scala:542:17] wire [1:0] broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9] wire [1:0] hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17] assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17] wire broadcast_2_nodeIn_0_valid_0 = broadcast_2_auto_in_0_valid_0; // @[MixedNode.scala:551:17] wire [2:0] bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17] wire [2:0] broadcast_2_nodeIn_0_action = broadcast_2_auto_in_0_action; // @[MixedNode.scala:551:17] wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [15:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [127:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9] assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire widget_1_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_valid = widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_anonIn_a_bits_address = widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_1_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_1_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] widget_1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] widget_1_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_1_anonOut_a_ready = widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] widget_1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_valid = widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_opcode = widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_anonOut_d_bits_param = widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_d_bits_size = widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_d_bits_sink = widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_denied = widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] widget_1_anonOut_d_bits_data = widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_corrupt = widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_a_ready = widget_1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_out_a_valid = widget_1_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_out_a_bits_address = widget_1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_d_valid = widget_1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_opcode = widget_1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_param = widget_1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_size = widget_1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_sink = widget_1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_denied = widget_1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_data = widget_1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_corrupt = widget_1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_a_ready = widget_1_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_1_anonOut_a_valid = widget_1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonOut_a_bits_address = widget_1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_d_valid = widget_1_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_opcode = widget_1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_param = widget_1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_size = widget_1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_sink = widget_1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_denied = widget_1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_data = widget_1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_corrupt = widget_1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [15:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [127:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_b_ready = buffer_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_b_valid = buffer_auto_in_b_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_b_bits_opcode = buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_b_bits_param = buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeOut_b_bits_size = buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_b_bits_source = buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [15:0] buffer_nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] tlOtherMastersNodeOut_b_bits_address = buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [127:0] buffer_nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire [15:0] tlOtherMastersNodeOut_b_bits_mask = buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire buffer_nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [127:0] tlOtherMastersNodeOut_b_bits_data = buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_c_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_b_bits_corrupt = buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_c_ready = buffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_c_valid = buffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_c_bits_opcode = buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_c_bits_param = buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_c_bits_size = buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_c_bits_source = buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_c_bits_address = buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire [127:0] buffer_nodeIn_c_bits_data = buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_d_bits_param = buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeOut_d_bits_sink = buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [127:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_bits_denied = buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [127:0] tlOtherMastersNodeOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_e_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_e_ready = buffer_auto_in_e_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_e_valid = buffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_e_bits_sink = buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_valid_0 = buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_opcode_0 = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_param_0 = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_size_0 = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_source_0 = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_address_0 = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_mask_0 = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_data_0 = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_b_ready_0 = buffer_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_valid = buffer_auto_out_b_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_b_bits_opcode = buffer_auto_out_b_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_b_bits_param = buffer_auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_b_bits_size = buffer_auto_out_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_b_bits_source = buffer_auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_b_bits_address = buffer_auto_out_b_bits_address; // @[Buffer.scala:40:9] wire [15:0] buffer_nodeOut_b_bits_mask = buffer_auto_out_b_bits_mask; // @[Buffer.scala:40:9] wire [127:0] buffer_nodeOut_b_bits_data = buffer_auto_out_b_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_bits_corrupt = buffer_auto_out_b_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_c_ready = buffer_auto_out_c_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_c_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_valid_0 = buffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_opcode_0 = buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_param_0 = buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_size_0 = buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_source_0 = buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_address_0 = buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] buffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_data_0 = buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_d_ready_0 = buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_d_bits_sink = buffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_denied = buffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [127:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_e_ready = buffer_auto_out_e_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_e_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_valid_0 = buffer_auto_out_e_valid; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_bits_sink_0 = buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_b_ready = buffer_nodeOut_b_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_b_valid = buffer_nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_opcode = buffer_nodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_param = buffer_nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_size = buffer_nodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_source = buffer_nodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_address = buffer_nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_mask = buffer_nodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_data = buffer_nodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_corrupt = buffer_nodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_c_ready = buffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_c_valid = buffer_nodeOut_c_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_opcode = buffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_param = buffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_size = buffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_source = buffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_address = buffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_data = buffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_e_ready = buffer_nodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_e_valid = buffer_nodeOut_e_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_e_bits_sink = buffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_b_ready = buffer_nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_b_valid = buffer_nodeIn_b_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_opcode = buffer_nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_param = buffer_nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_size = buffer_nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_source = buffer_nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_address = buffer_nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_mask = buffer_nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_data = buffer_nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_corrupt = buffer_nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_c_ready = buffer_nodeIn_c_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_c_valid = buffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_opcode = buffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_param = buffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_size = buffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_source = buffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_address = buffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_data = buffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_e_ready = buffer_nodeIn_e_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_e_valid = buffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_e_bits_sink = buffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_ready = tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_valid = tlOtherMastersNodeOut_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_opcode = tlOtherMastersNodeOut_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_param = tlOtherMastersNodeOut_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_size = tlOtherMastersNodeOut_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_source = tlOtherMastersNodeOut_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_address = tlOtherMastersNodeOut_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_mask = tlOtherMastersNodeOut_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_data = tlOtherMastersNodeOut_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_b_ready = tlOtherMastersNodeOut_b_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_b_valid = tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_b_bits_opcode = tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_b_bits_param = tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_b_bits_size = tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_b_bits_source = tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] tlOtherMastersNodeIn_b_bits_address = tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [15:0] tlOtherMastersNodeIn_b_bits_mask = tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [127:0] tlOtherMastersNodeIn_b_bits_data = tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_b_bits_corrupt = tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_c_ready = tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_valid = tlOtherMastersNodeOut_c_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_opcode = tlOtherMastersNodeOut_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_param = tlOtherMastersNodeOut_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_size = tlOtherMastersNodeOut_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_source = tlOtherMastersNodeOut_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_address = tlOtherMastersNodeOut_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_data = tlOtherMastersNodeOut_c_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_d_ready = tlOtherMastersNodeOut_d_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_valid = tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_opcode = tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_param = tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_d_bits_size = tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_source = tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_d_bits_sink = tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_denied = tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [127:0] tlOtherMastersNodeIn_d_bits_data = tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_corrupt = tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_e_ready = tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_e_valid = tlOtherMastersNodeOut_e_valid; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:551:17] assign buffer_auto_in_e_bits_sink = tlOtherMastersNodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign tlOtherMastersNodeOut_a_valid = tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_opcode = tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_param = tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_size = tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_source = tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_address = tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_mask = tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_data = tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_ready = tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_valid = tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_opcode = tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_param = tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_size = tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_source = tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_address = tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_data = tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_ready = tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_valid = tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_bits_sink = tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17] assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17] assign auto_trace_source_out_insns_0_valid_0 = traceSourceNodeOut_insns_0_valid; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_iaddr_0 = traceSourceNodeOut_insns_0_iaddr; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_insn_0 = traceSourceNodeOut_insns_0_insn; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_priv_0 = traceSourceNodeOut_insns_0_priv; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_exception_0 = traceSourceNodeOut_insns_0_exception; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_interrupt_0 = traceSourceNodeOut_insns_0_interrupt; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_cause_0 = traceSourceNodeOut_insns_0_cause; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_tval_0 = traceSourceNodeOut_insns_0_tval; // @[RocketTile.scala:141:7] assign auto_trace_source_out_time_0 = traceSourceNodeOut_time; // @[RocketTile.scala:141:7] assign broadcast_2_auto_in_0_valid_0 = bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17] assign broadcast_2_auto_in_0_action = bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17] wire int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_1; // @[MixedNode.scala:542:17] wire x1_int_localOut_1_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_2_0; // @[MixedNode.scala:542:17] assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_0 = x1_int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1 = x1_int_localIn_1; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1_0 = x1_int_localIn_1_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_2_0 = x1_int_localIn_2_0; // @[MixedNode.scala:542:17, :551:17] wire intSinkNodeIn_0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_1; // @[MixedNode.scala:551:17] wire intSinkNodeIn_2; // @[MixedNode.scala:551:17] wire intSinkNodeIn_3; // @[MixedNode.scala:551:17] wire intSinkNodeIn_4; // @[MixedNode.scala:551:17] assign auto_wfi_out_0_0 = wfiNodeOut_0; // @[RocketTile.scala:141:7] reg wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] assign wfiNodeOut_0 = wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] always @(posedge clock) begin // @[RocketTile.scala:141:7] if (reset) // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= 1'h0; // @[Interrupts.scala:131:36] else // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= _core_io_wfi; // @[RocketTile.scala:147:20] always @(posedge) TLXbar_MasterXbar_RocketTile_i2_o1_a32d128s2k4z4c_1 tlMasterXbar ( // @[HierarchicalElement.scala:55:42] .clock (clock), .reset (reset), .auto_anon_in_1_a_ready (widget_1_auto_anon_out_a_ready), .auto_anon_in_1_a_valid (widget_1_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_1_a_bits_address (widget_1_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_1_d_valid (widget_1_auto_anon_out_d_valid), .auto_anon_in_1_d_bits_opcode (widget_1_auto_anon_out_d_bits_opcode), .auto_anon_in_1_d_bits_param (widget_1_auto_anon_out_d_bits_param), .auto_anon_in_1_d_bits_size (widget_1_auto_anon_out_d_bits_size), .auto_anon_in_1_d_bits_sink (widget_1_auto_anon_out_d_bits_sink), .auto_anon_in_1_d_bits_denied (widget_1_auto_anon_out_d_bits_denied), .auto_anon_in_1_d_bits_data (widget_1_auto_anon_out_d_bits_data), .auto_anon_in_1_d_bits_corrupt (widget_1_auto_anon_out_d_bits_corrupt), .auto_anon_in_0_a_ready (widget_auto_anon_out_a_ready), .auto_anon_in_0_a_valid (widget_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_opcode (widget_auto_anon_out_a_bits_opcode), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_param (widget_auto_anon_out_a_bits_param), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_size (widget_auto_anon_out_a_bits_size), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_source (widget_auto_anon_out_a_bits_source), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_address (widget_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_mask (widget_auto_anon_out_a_bits_mask), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_data (widget_auto_anon_out_a_bits_data), // @[WidthWidget.scala:27:9] .auto_anon_in_0_b_ready (widget_auto_anon_out_b_ready), // @[WidthWidget.scala:27:9] .auto_anon_in_0_b_valid (widget_auto_anon_out_b_valid), .auto_anon_in_0_b_bits_opcode (widget_auto_anon_out_b_bits_opcode), .auto_anon_in_0_b_bits_param (widget_auto_anon_out_b_bits_param), .auto_anon_in_0_b_bits_size (widget_auto_anon_out_b_bits_size), .auto_anon_in_0_b_bits_source (widget_auto_anon_out_b_bits_source), .auto_anon_in_0_b_bits_address (widget_auto_anon_out_b_bits_address), .auto_anon_in_0_b_bits_mask (widget_auto_anon_out_b_bits_mask), .auto_anon_in_0_b_bits_data (widget_auto_anon_out_b_bits_data), .auto_anon_in_0_b_bits_corrupt (widget_auto_anon_out_b_bits_corrupt), .auto_anon_in_0_c_ready (widget_auto_anon_out_c_ready), .auto_anon_in_0_c_valid (widget_auto_anon_out_c_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_opcode (widget_auto_anon_out_c_bits_opcode), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_param (widget_auto_anon_out_c_bits_param), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_size (widget_auto_anon_out_c_bits_size), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_source (widget_auto_anon_out_c_bits_source), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_address (widget_auto_anon_out_c_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_data (widget_auto_anon_out_c_bits_data), // @[WidthWidget.scala:27:9] .auto_anon_in_0_d_ready (widget_auto_anon_out_d_ready), // @[WidthWidget.scala:27:9] .auto_anon_in_0_d_valid (widget_auto_anon_out_d_valid), .auto_anon_in_0_d_bits_opcode (widget_auto_anon_out_d_bits_opcode), .auto_anon_in_0_d_bits_param (widget_auto_anon_out_d_bits_param), .auto_anon_in_0_d_bits_size (widget_auto_anon_out_d_bits_size), .auto_anon_in_0_d_bits_source (widget_auto_anon_out_d_bits_source), .auto_anon_in_0_d_bits_sink (widget_auto_anon_out_d_bits_sink), .auto_anon_in_0_d_bits_denied (widget_auto_anon_out_d_bits_denied), .auto_anon_in_0_d_bits_data (widget_auto_anon_out_d_bits_data), .auto_anon_in_0_d_bits_corrupt (widget_auto_anon_out_d_bits_corrupt), .auto_anon_in_0_e_ready (widget_auto_anon_out_e_ready), .auto_anon_in_0_e_valid (widget_auto_anon_out_e_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_e_bits_sink (widget_auto_anon_out_e_bits_sink), // @[WidthWidget.scala:27:9] .auto_anon_out_a_ready (tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_anon_out_a_valid (tlOtherMastersNodeIn_a_valid), .auto_anon_out_a_bits_opcode (tlOtherMastersNodeIn_a_bits_opcode), .auto_anon_out_a_bits_param (tlOtherMastersNodeIn_a_bits_param), .auto_anon_out_a_bits_size (tlOtherMastersNodeIn_a_bits_size), .auto_anon_out_a_bits_source (tlOtherMastersNodeIn_a_bits_source), .auto_anon_out_a_bits_address (tlOtherMastersNodeIn_a_bits_address), .auto_anon_out_a_bits_mask (tlOtherMastersNodeIn_a_bits_mask), .auto_anon_out_a_bits_data (tlOtherMastersNodeIn_a_bits_data), .auto_anon_out_b_ready (tlOtherMastersNodeIn_b_ready), .auto_anon_out_b_valid (tlOtherMastersNodeIn_b_valid), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_opcode (tlOtherMastersNodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_param (tlOtherMastersNodeIn_b_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_size (tlOtherMastersNodeIn_b_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_source (tlOtherMastersNodeIn_b_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_address (tlOtherMastersNodeIn_b_bits_address), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_mask (tlOtherMastersNodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_data (tlOtherMastersNodeIn_b_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_corrupt (tlOtherMastersNodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .auto_anon_out_c_ready (tlOtherMastersNodeIn_c_ready), // @[MixedNode.scala:551:17] .auto_anon_out_c_valid (tlOtherMastersNodeIn_c_valid), .auto_anon_out_c_bits_opcode (tlOtherMastersNodeIn_c_bits_opcode), .auto_anon_out_c_bits_param (tlOtherMastersNodeIn_c_bits_param), .auto_anon_out_c_bits_size (tlOtherMastersNodeIn_c_bits_size), .auto_anon_out_c_bits_source (tlOtherMastersNodeIn_c_bits_source), .auto_anon_out_c_bits_address (tlOtherMastersNodeIn_c_bits_address), .auto_anon_out_c_bits_data (tlOtherMastersNodeIn_c_bits_data), .auto_anon_out_d_ready (tlOtherMastersNodeIn_d_ready), .auto_anon_out_d_valid (tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_opcode (tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_param (tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_size (tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_source (tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_sink (tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_denied (tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_data (tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_corrupt (tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_anon_out_e_ready (tlOtherMastersNodeIn_e_ready), // @[MixedNode.scala:551:17] .auto_anon_out_e_valid (tlOtherMastersNodeIn_e_valid), .auto_anon_out_e_bits_sink (tlOtherMastersNodeIn_e_bits_sink) ); // @[HierarchicalElement.scala:55:42] TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u_1 tlSlaveXbar ( // @[HierarchicalElement.scala:56:41] .clock (clock), .reset (reset) ); // @[HierarchicalElement.scala:56:41] IntXbar_i4_o1_1 intXbar ( // @[HierarchicalElement.scala:57:37] .auto_anon_in_3_0 (x1_int_localOut_2_0), // @[MixedNode.scala:542:17] .auto_anon_in_2_0 (x1_int_localOut_1_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_0 (x1_int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_1 (x1_int_localOut_1), // @[MixedNode.scala:542:17] .auto_anon_in_0_0 (int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_out_0 (intSinkNodeIn_0), .auto_anon_out_1 (intSinkNodeIn_1), .auto_anon_out_2 (intSinkNodeIn_2), .auto_anon_out_3 (intSinkNodeIn_3), .auto_anon_out_4 (intSinkNodeIn_4) ); // @[HierarchicalElement.scala:57:37] DCache_1 dcache ( // @[HellaCache.scala:278:43] .clock (clock), .reset (reset), .auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_out_a_valid (widget_auto_anon_in_a_valid), .auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (widget_auto_anon_in_a_bits_param), .auto_out_a_bits_size (widget_auto_anon_in_a_bits_size), .auto_out_a_bits_source (widget_auto_anon_in_a_bits_source), .auto_out_a_bits_address (widget_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (widget_auto_anon_in_a_bits_data), .auto_out_b_ready (widget_auto_anon_in_b_ready), .auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9] .auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9] .auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9] .auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9] .auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9] .auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9] .auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9] .auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9] .auto_out_c_valid (widget_auto_anon_in_c_valid), .auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode), .auto_out_c_bits_param (widget_auto_anon_in_c_bits_param), .auto_out_c_bits_size (widget_auto_anon_in_c_bits_size), .auto_out_c_bits_source (widget_auto_anon_in_c_bits_source), .auto_out_c_bits_address (widget_auto_anon_in_c_bits_address), .auto_out_c_bits_data (widget_auto_anon_in_c_bits_data), .auto_out_d_ready (widget_auto_anon_in_d_ready), .auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9] .auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9] .auto_out_e_valid (widget_auto_anon_in_e_valid), .auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink), .io_cpu_req_ready (_dcache_io_cpu_req_ready), .io_cpu_req_valid (_dcacheArb_io_mem_req_valid), // @[HellaCache.scala:292:25] .io_cpu_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), // @[HellaCache.scala:292:25] .io_cpu_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), // @[HellaCache.scala:292:25] .io_cpu_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), // @[HellaCache.scala:292:25] .io_cpu_req_bits_size (_dcacheArb_io_mem_req_bits_size), // @[HellaCache.scala:292:25] .io_cpu_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), // @[HellaCache.scala:292:25] .io_cpu_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), // @[HellaCache.scala:292:25] .io_cpu_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), // @[HellaCache.scala:292:25] .io_cpu_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), // @[HellaCache.scala:292:25] .io_cpu_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), // @[HellaCache.scala:292:25] .io_cpu_s1_kill (_dcacheArb_io_mem_s1_kill), // @[HellaCache.scala:292:25] .io_cpu_s1_data_data (_dcacheArb_io_mem_s1_data_data), // @[HellaCache.scala:292:25] .io_cpu_s1_data_mask (8'h0), // @[RocketTile.scala:147:20] .io_cpu_s2_nack (_dcache_io_cpu_s2_nack), .io_cpu_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), .io_cpu_s2_uncached (_dcache_io_cpu_s2_uncached), .io_cpu_s2_paddr (_dcache_io_cpu_s2_paddr), .io_cpu_resp_valid (_dcache_io_cpu_resp_valid), .io_cpu_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), .io_cpu_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), .io_cpu_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), .io_cpu_resp_bits_size (_dcache_io_cpu_resp_bits_size), .io_cpu_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), .io_cpu_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), .io_cpu_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), .io_cpu_resp_bits_data (_dcache_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), .io_cpu_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), .io_cpu_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), .io_cpu_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), .io_cpu_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), .io_cpu_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), .io_cpu_replay_next (_dcache_io_cpu_replay_next), .io_cpu_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), .io_cpu_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), .io_cpu_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), .io_cpu_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), .io_cpu_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), .io_cpu_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), .io_cpu_s2_gpa (_dcache_io_cpu_s2_gpa), .io_cpu_ordered (_dcache_io_cpu_ordered), .io_cpu_store_pending (_dcache_io_cpu_store_pending), .io_cpu_perf_acquire (_dcache_io_cpu_perf_acquire), .io_cpu_perf_release (_dcache_io_cpu_perf_release), .io_cpu_perf_grant (_dcache_io_cpu_perf_grant), .io_cpu_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), .io_cpu_perf_blocked (_dcache_io_cpu_perf_blocked), .io_cpu_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), .io_cpu_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), .io_cpu_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), .io_cpu_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), .io_cpu_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), .io_cpu_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled), // @[HellaCache.scala:292:25] .io_ptw_req_ready (_ptw_io_requestor_0_req_ready), // @[PTW.scala:802:19] .io_ptw_req_valid (_dcache_io_ptw_req_valid), .io_ptw_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_0_resp_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_status_debug (_ptw_io_requestor_0_status_debug), // @[PTW.scala:802:19] .io_ptw_status_cease (_ptw_io_requestor_0_status_cease), // @[PTW.scala:802:19] .io_ptw_status_wfi (_ptw_io_requestor_0_status_wfi), // @[PTW.scala:802:19] .io_ptw_status_isa (_ptw_io_requestor_0_status_isa), // @[PTW.scala:802:19] .io_ptw_status_dprv (_ptw_io_requestor_0_status_dprv), // @[PTW.scala:802:19] .io_ptw_status_dv (_ptw_io_requestor_0_status_dv), // @[PTW.scala:802:19] .io_ptw_status_prv (_ptw_io_requestor_0_status_prv), // @[PTW.scala:802:19] .io_ptw_status_v (_ptw_io_requestor_0_status_v), // @[PTW.scala:802:19] .io_ptw_status_sd (_ptw_io_requestor_0_status_sd), // @[PTW.scala:802:19] .io_ptw_status_mpv (_ptw_io_requestor_0_status_mpv), // @[PTW.scala:802:19] .io_ptw_status_gva (_ptw_io_requestor_0_status_gva), // @[PTW.scala:802:19] .io_ptw_status_tsr (_ptw_io_requestor_0_status_tsr), // @[PTW.scala:802:19] .io_ptw_status_tw (_ptw_io_requestor_0_status_tw), // @[PTW.scala:802:19] .io_ptw_status_tvm (_ptw_io_requestor_0_status_tvm), // @[PTW.scala:802:19] .io_ptw_status_mxr (_ptw_io_requestor_0_status_mxr), // @[PTW.scala:802:19] .io_ptw_status_sum (_ptw_io_requestor_0_status_sum), // @[PTW.scala:802:19] .io_ptw_status_mprv (_ptw_io_requestor_0_status_mprv), // @[PTW.scala:802:19] .io_ptw_status_fs (_ptw_io_requestor_0_status_fs), // @[PTW.scala:802:19] .io_ptw_status_mpp (_ptw_io_requestor_0_status_mpp), // @[PTW.scala:802:19] .io_ptw_status_spp (_ptw_io_requestor_0_status_spp), // @[PTW.scala:802:19] .io_ptw_status_mpie (_ptw_io_requestor_0_status_mpie), // @[PTW.scala:802:19] .io_ptw_status_spie (_ptw_io_requestor_0_status_spie), // @[PTW.scala:802:19] .io_ptw_status_mie (_ptw_io_requestor_0_status_mie), // @[PTW.scala:802:19] .io_ptw_status_sie (_ptw_io_requestor_0_status_sie), // @[PTW.scala:802:19] .io_ptw_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_gstatus_v (_ptw_io_requestor_0_gstatus_v), // @[PTW.scala:802:19] .io_ptw_gstatus_sd (_ptw_io_requestor_0_gstatus_sd), // @[PTW.scala:802:19] .io_ptw_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[HellaCache.scala:278:43] Frontend_1 frontend ( // @[Frontend.scala:393:28] .clock (clock), .reset (reset), .auto_icache_master_out_a_ready (widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_icache_master_out_a_valid (widget_1_auto_anon_in_a_valid), .auto_icache_master_out_a_bits_address (widget_1_auto_anon_in_a_bits_address), .auto_icache_master_out_d_valid (widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_opcode (widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_param (widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_size (widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_sink (widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_denied (widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_data (widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_corrupt (widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .io_cpu_might_request (_core_io_imem_might_request), // @[RocketTile.scala:147:20] .io_cpu_req_valid (_core_io_imem_req_valid), // @[RocketTile.scala:147:20] .io_cpu_req_bits_pc (_core_io_imem_req_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_req_bits_speculative (_core_io_imem_req_bits_speculative), // @[RocketTile.scala:147:20] .io_cpu_sfence_valid (_core_io_imem_sfence_valid), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_addr (_core_io_imem_sfence_bits_addr), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_asid (_core_io_imem_sfence_bits_asid), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_hv (_core_io_imem_sfence_bits_hv), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_hg (_core_io_imem_sfence_bits_hg), // @[RocketTile.scala:147:20] .io_cpu_resp_ready (_core_io_imem_resp_ready), // @[RocketTile.scala:147:20] .io_cpu_resp_valid (_frontend_io_cpu_resp_valid), .io_cpu_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), .io_cpu_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), .io_cpu_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), .io_cpu_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), .io_cpu_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), .io_cpu_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), .io_cpu_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), .io_cpu_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), .io_cpu_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), .io_cpu_resp_bits_data (_frontend_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), .io_cpu_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), .io_cpu_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), .io_cpu_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), .io_cpu_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), .io_cpu_gpa_valid (_frontend_io_cpu_gpa_valid), .io_cpu_gpa_bits (_frontend_io_cpu_gpa_bits), .io_cpu_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), .io_cpu_btb_update_valid (_core_io_imem_btb_update_valid), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_target (_core_io_imem_btb_update_bits_target), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), // @[RocketTile.scala:147:20] .io_cpu_bht_update_valid (_core_io_imem_bht_update_valid), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), // @[RocketTile.scala:147:20] .io_cpu_flush_icache (_core_io_imem_flush_icache), // @[RocketTile.scala:147:20] .io_cpu_npc (_frontend_io_cpu_npc), .io_cpu_perf_acquire (_frontend_io_cpu_perf_acquire), .io_cpu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), .io_cpu_progress (_core_io_imem_progress), // @[RocketTile.scala:147:20] .io_ptw_req_ready (_ptw_io_requestor_1_req_ready), // @[PTW.scala:802:19] .io_ptw_req_valid (_frontend_io_ptw_req_valid), .io_ptw_req_bits_valid (_frontend_io_ptw_req_bits_valid), .io_ptw_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_1_resp_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_status_debug (_ptw_io_requestor_1_status_debug), // @[PTW.scala:802:19] .io_ptw_status_cease (_ptw_io_requestor_1_status_cease), // @[PTW.scala:802:19] .io_ptw_status_wfi (_ptw_io_requestor_1_status_wfi), // @[PTW.scala:802:19] .io_ptw_status_isa (_ptw_io_requestor_1_status_isa), // @[PTW.scala:802:19] .io_ptw_status_dprv (_ptw_io_requestor_1_status_dprv), // @[PTW.scala:802:19] .io_ptw_status_dv (_ptw_io_requestor_1_status_dv), // @[PTW.scala:802:19] .io_ptw_status_prv (_ptw_io_requestor_1_status_prv), // @[PTW.scala:802:19] .io_ptw_status_v (_ptw_io_requestor_1_status_v), // @[PTW.scala:802:19] .io_ptw_status_sd (_ptw_io_requestor_1_status_sd), // @[PTW.scala:802:19] .io_ptw_status_mpv (_ptw_io_requestor_1_status_mpv), // @[PTW.scala:802:19] .io_ptw_status_gva (_ptw_io_requestor_1_status_gva), // @[PTW.scala:802:19] .io_ptw_status_tsr (_ptw_io_requestor_1_status_tsr), // @[PTW.scala:802:19] .io_ptw_status_tw (_ptw_io_requestor_1_status_tw), // @[PTW.scala:802:19] .io_ptw_status_tvm (_ptw_io_requestor_1_status_tvm), // @[PTW.scala:802:19] .io_ptw_status_mxr (_ptw_io_requestor_1_status_mxr), // @[PTW.scala:802:19] .io_ptw_status_sum (_ptw_io_requestor_1_status_sum), // @[PTW.scala:802:19] .io_ptw_status_mprv (_ptw_io_requestor_1_status_mprv), // @[PTW.scala:802:19] .io_ptw_status_fs (_ptw_io_requestor_1_status_fs), // @[PTW.scala:802:19] .io_ptw_status_mpp (_ptw_io_requestor_1_status_mpp), // @[PTW.scala:802:19] .io_ptw_status_spp (_ptw_io_requestor_1_status_spp), // @[PTW.scala:802:19] .io_ptw_status_mpie (_ptw_io_requestor_1_status_mpie), // @[PTW.scala:802:19] .io_ptw_status_spie (_ptw_io_requestor_1_status_spie), // @[PTW.scala:802:19] .io_ptw_status_mie (_ptw_io_requestor_1_status_mie), // @[PTW.scala:802:19] .io_ptw_status_sie (_ptw_io_requestor_1_status_sie), // @[PTW.scala:802:19] .io_ptw_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_gstatus_v (_ptw_io_requestor_1_gstatus_v), // @[PTW.scala:802:19] .io_ptw_gstatus_sd (_ptw_io_requestor_1_gstatus_sd), // @[PTW.scala:802:19] .io_ptw_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[Frontend.scala:393:28] TLFragmenter_1 fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset) ); // @[Fragmenter.scala:345:34] FPU_1 fpuOpt ( // @[RocketTile.scala:242:62] .clock (clock), .reset (reset), .io_hartid (_core_io_fpu_hartid), // @[RocketTile.scala:147:20] .io_time (_core_io_fpu_time), // @[RocketTile.scala:147:20] .io_inst (_core_io_fpu_inst), // @[RocketTile.scala:147:20] .io_fromint_data (_core_io_fpu_fromint_data), // @[RocketTile.scala:147:20] .io_fcsr_rm (_core_io_fpu_fcsr_rm), // @[RocketTile.scala:147:20] .io_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), .io_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), .io_store_data (_fpuOpt_io_store_data), .io_toint_data (_fpuOpt_io_toint_data), .io_ll_resp_val (_core_io_fpu_ll_resp_val), // @[RocketTile.scala:147:20] .io_ll_resp_type (_core_io_fpu_ll_resp_type), // @[RocketTile.scala:147:20] .io_ll_resp_tag (_core_io_fpu_ll_resp_tag), // @[RocketTile.scala:147:20] .io_ll_resp_data (_core_io_fpu_ll_resp_data), // @[RocketTile.scala:147:20] .io_valid (_core_io_fpu_valid), // @[RocketTile.scala:147:20] .io_fcsr_rdy (_fpuOpt_io_fcsr_rdy), .io_nack_mem (_fpuOpt_io_nack_mem), .io_illegal_rm (_fpuOpt_io_illegal_rm), .io_killx (_core_io_fpu_killx), // @[RocketTile.scala:147:20] .io_killm (_core_io_fpu_killm), // @[RocketTile.scala:147:20] .io_dec_ldst (_fpuOpt_io_dec_ldst), .io_dec_wen (_fpuOpt_io_dec_wen), .io_dec_ren1 (_fpuOpt_io_dec_ren1), .io_dec_ren2 (_fpuOpt_io_dec_ren2), .io_dec_ren3 (_fpuOpt_io_dec_ren3), .io_dec_swap12 (_fpuOpt_io_dec_swap12), .io_dec_swap23 (_fpuOpt_io_dec_swap23), .io_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), .io_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), .io_dec_fromint (_fpuOpt_io_dec_fromint), .io_dec_toint (_fpuOpt_io_dec_toint), .io_dec_fastpipe (_fpuOpt_io_dec_fastpipe), .io_dec_fma (_fpuOpt_io_dec_fma), .io_dec_div (_fpuOpt_io_dec_div), .io_dec_sqrt (_fpuOpt_io_dec_sqrt), .io_dec_wflags (_fpuOpt_io_dec_wflags), .io_dec_vec (_fpuOpt_io_dec_vec), .io_sboard_set (_fpuOpt_io_sboard_set), .io_sboard_clr (_fpuOpt_io_sboard_clr), .io_sboard_clra (_fpuOpt_io_sboard_clra), .io_keep_clock_enabled (_core_io_fpu_keep_clock_enabled) // @[RocketTile.scala:147:20] ); // @[RocketTile.scala:242:62] HellaCacheArbiter_1 dcacheArb ( // @[HellaCache.scala:292:25] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_dcacheArb_io_requestor_0_req_ready), .io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[PTW.scala:802:19] .io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[PTW.scala:802:19] .io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[PTW.scala:802:19] .io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[PTW.scala:802:19] .io_requestor_0_s2_nack (_dcacheArb_io_requestor_0_s2_nack), .io_requestor_0_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), .io_requestor_0_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), .io_requestor_0_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), .io_requestor_0_resp_valid (_dcacheArb_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), .io_requestor_0_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), .io_requestor_0_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), .io_requestor_0_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), .io_requestor_0_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), .io_requestor_0_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), .io_requestor_0_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), .io_requestor_0_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), .io_requestor_0_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), .io_requestor_0_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), .io_requestor_0_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), .io_requestor_0_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), .io_requestor_0_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), .io_requestor_0_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), .io_requestor_0_replay_next (_dcacheArb_io_requestor_0_replay_next), .io_requestor_0_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), .io_requestor_0_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), .io_requestor_0_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), .io_requestor_0_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), .io_requestor_0_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), .io_requestor_0_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), .io_requestor_0_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), .io_requestor_0_ordered (_dcacheArb_io_requestor_0_ordered), .io_requestor_0_store_pending (_dcacheArb_io_requestor_0_store_pending), .io_requestor_0_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), .io_requestor_0_perf_release (_dcacheArb_io_requestor_0_perf_release), .io_requestor_0_perf_grant (_dcacheArb_io_requestor_0_perf_grant), .io_requestor_0_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), .io_requestor_0_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), .io_requestor_0_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), .io_requestor_0_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), .io_requestor_0_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), .io_requestor_0_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), .io_requestor_0_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), .io_requestor_1_req_ready (_dcacheArb_io_requestor_1_req_ready), .io_requestor_1_req_valid (_core_io_dmem_req_valid), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_addr (_core_io_dmem_req_bits_addr), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_tag (_core_io_dmem_req_bits_tag), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_cmd (_core_io_dmem_req_bits_cmd), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_size (_core_io_dmem_req_bits_size), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_signed (_core_io_dmem_req_bits_signed), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_dprv (_core_io_dmem_req_bits_dprv), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_dv (_core_io_dmem_req_bits_dv), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), // @[RocketTile.scala:147:20] .io_requestor_1_s1_kill (_core_io_dmem_s1_kill), // @[RocketTile.scala:147:20] .io_requestor_1_s1_data_data (_core_io_dmem_s1_data_data), // @[RocketTile.scala:147:20] .io_requestor_1_s2_nack (_dcacheArb_io_requestor_1_s2_nack), .io_requestor_1_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), .io_requestor_1_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), .io_requestor_1_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), .io_requestor_1_resp_valid (_dcacheArb_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), .io_requestor_1_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), .io_requestor_1_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), .io_requestor_1_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), .io_requestor_1_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), .io_requestor_1_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), .io_requestor_1_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), .io_requestor_1_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), .io_requestor_1_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), .io_requestor_1_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), .io_requestor_1_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), .io_requestor_1_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), .io_requestor_1_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), .io_requestor_1_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), .io_requestor_1_replay_next (_dcacheArb_io_requestor_1_replay_next), .io_requestor_1_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), .io_requestor_1_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), .io_requestor_1_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), .io_requestor_1_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), .io_requestor_1_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), .io_requestor_1_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), .io_requestor_1_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), .io_requestor_1_ordered (_dcacheArb_io_requestor_1_ordered), .io_requestor_1_store_pending (_dcacheArb_io_requestor_1_store_pending), .io_requestor_1_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), .io_requestor_1_perf_release (_dcacheArb_io_requestor_1_perf_release), .io_requestor_1_perf_grant (_dcacheArb_io_requestor_1_perf_grant), .io_requestor_1_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), .io_requestor_1_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), .io_requestor_1_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), .io_requestor_1_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), .io_requestor_1_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), .io_requestor_1_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), .io_requestor_1_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore), .io_requestor_1_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), // @[RocketTile.scala:147:20] .io_mem_req_ready (_dcache_io_cpu_req_ready), // @[HellaCache.scala:278:43] .io_mem_req_valid (_dcacheArb_io_mem_req_valid), .io_mem_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), .io_mem_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), .io_mem_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), .io_mem_req_bits_size (_dcacheArb_io_mem_req_bits_size), .io_mem_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), .io_mem_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), .io_mem_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), .io_mem_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), .io_mem_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), .io_mem_s1_kill (_dcacheArb_io_mem_s1_kill), .io_mem_s1_data_data (_dcacheArb_io_mem_s1_data_data), .io_mem_s2_nack (_dcache_io_cpu_s2_nack), // @[HellaCache.scala:278:43] .io_mem_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), // @[HellaCache.scala:278:43] .io_mem_s2_uncached (_dcache_io_cpu_s2_uncached), // @[HellaCache.scala:278:43] .io_mem_s2_paddr (_dcache_io_cpu_s2_paddr), // @[HellaCache.scala:278:43] .io_mem_resp_valid (_dcache_io_cpu_resp_valid), // @[HellaCache.scala:278:43] .io_mem_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), // @[HellaCache.scala:278:43] .io_mem_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), // @[HellaCache.scala:278:43] .io_mem_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), // @[HellaCache.scala:278:43] .io_mem_resp_bits_size (_dcache_io_cpu_resp_bits_size), // @[HellaCache.scala:278:43] .io_mem_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), // @[HellaCache.scala:278:43] .io_mem_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), // @[HellaCache.scala:278:43] .io_mem_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data (_dcache_io_cpu_resp_bits_data), // @[HellaCache.scala:278:43] .io_mem_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), // @[HellaCache.scala:278:43] .io_mem_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), // @[HellaCache.scala:278:43] .io_mem_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), // @[HellaCache.scala:278:43] .io_mem_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), // @[HellaCache.scala:278:43] .io_mem_replay_next (_dcache_io_cpu_replay_next), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), // @[HellaCache.scala:278:43] .io_mem_s2_gpa (_dcache_io_cpu_s2_gpa), // @[HellaCache.scala:278:43] .io_mem_ordered (_dcache_io_cpu_ordered), // @[HellaCache.scala:278:43] .io_mem_store_pending (_dcache_io_cpu_store_pending), // @[HellaCache.scala:278:43] .io_mem_perf_acquire (_dcache_io_cpu_perf_acquire), // @[HellaCache.scala:278:43] .io_mem_perf_release (_dcache_io_cpu_perf_release), // @[HellaCache.scala:278:43] .io_mem_perf_grant (_dcache_io_cpu_perf_grant), // @[HellaCache.scala:278:43] .io_mem_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), // @[HellaCache.scala:278:43] .io_mem_perf_blocked (_dcache_io_cpu_perf_blocked), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:278:43] .io_mem_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:278:43] .io_mem_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:278:43] .io_mem_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled) ); // @[HellaCache.scala:292:25] PTW_1 ptw ( // @[PTW.scala:802:19] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready), .io_requestor_0_req_valid (_dcache_io_ptw_req_valid), // @[HellaCache.scala:278:43] .io_requestor_0_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), // @[HellaCache.scala:278:43] .io_requestor_0_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), // @[HellaCache.scala:278:43] .io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), .io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), .io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), .io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), .io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), .io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), .io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), .io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), .io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), .io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), .io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), .io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), .io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), .io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), .io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), .io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), .io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), .io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), .io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), .io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), .io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), .io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), .io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), .io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), .io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), .io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug), .io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease), .io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi), .io_requestor_0_status_isa (_ptw_io_requestor_0_status_isa), .io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv), .io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv), .io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv), .io_requestor_0_status_v (_ptw_io_requestor_0_status_v), .io_requestor_0_status_sd (_ptw_io_requestor_0_status_sd), .io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv), .io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva), .io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr), .io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw), .io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm), .io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr), .io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum), .io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv), .io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs), .io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp), .io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp), .io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie), .io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie), .io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie), .io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie), .io_requestor_0_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), .io_requestor_0_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), .io_requestor_0_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), .io_requestor_0_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), .io_requestor_0_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), .io_requestor_0_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), .io_requestor_0_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), .io_requestor_0_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), .io_requestor_0_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), .io_requestor_0_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), .io_requestor_0_gstatus_v (_ptw_io_requestor_0_gstatus_v), .io_requestor_0_gstatus_sd (_ptw_io_requestor_0_gstatus_sd), .io_requestor_0_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), .io_requestor_0_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), .io_requestor_0_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), .io_requestor_0_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), .io_requestor_0_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), .io_requestor_0_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), .io_requestor_0_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), .io_requestor_0_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), .io_requestor_0_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), .io_requestor_0_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), .io_requestor_0_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), .io_requestor_0_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), .io_requestor_0_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), .io_requestor_0_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), .io_requestor_0_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), .io_requestor_0_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), .io_requestor_0_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), .io_requestor_0_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), .io_requestor_0_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), .io_requestor_0_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), .io_requestor_0_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), .io_requestor_0_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), .io_requestor_0_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), .io_requestor_0_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), .io_requestor_0_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), .io_requestor_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), .io_requestor_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), .io_requestor_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), .io_requestor_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), .io_requestor_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), .io_requestor_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), .io_requestor_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), .io_requestor_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), .io_requestor_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), .io_requestor_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), .io_requestor_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), .io_requestor_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), .io_requestor_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), .io_requestor_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), .io_requestor_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), .io_requestor_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), .io_requestor_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), .io_requestor_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), .io_requestor_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), .io_requestor_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), .io_requestor_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), .io_requestor_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), .io_requestor_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), .io_requestor_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), .io_requestor_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), .io_requestor_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), .io_requestor_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), .io_requestor_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), .io_requestor_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), .io_requestor_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), .io_requestor_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), .io_requestor_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), .io_requestor_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), .io_requestor_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), .io_requestor_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), .io_requestor_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), .io_requestor_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), .io_requestor_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), .io_requestor_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), .io_requestor_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), .io_requestor_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), .io_requestor_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), .io_requestor_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), .io_requestor_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), .io_requestor_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), .io_requestor_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), .io_requestor_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), .io_requestor_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), .io_requestor_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), .io_requestor_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), .io_requestor_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), .io_requestor_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), .io_requestor_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), .io_requestor_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), .io_requestor_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), .io_requestor_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), .io_requestor_0_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), .io_requestor_0_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), .io_requestor_0_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), .io_requestor_0_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), .io_requestor_0_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), .io_requestor_0_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), .io_requestor_0_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), .io_requestor_0_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), .io_requestor_0_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), .io_requestor_0_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), .io_requestor_0_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), .io_requestor_0_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), .io_requestor_0_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), .io_requestor_0_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), .io_requestor_0_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), .io_requestor_0_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value), .io_requestor_1_req_ready (_ptw_io_requestor_1_req_ready), .io_requestor_1_req_valid (_frontend_io_ptw_req_valid), // @[Frontend.scala:393:28] .io_requestor_1_req_bits_valid (_frontend_io_ptw_req_bits_valid), // @[Frontend.scala:393:28] .io_requestor_1_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), // @[Frontend.scala:393:28] .io_requestor_1_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), // @[Frontend.scala:393:28] .io_requestor_1_resp_valid (_ptw_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), .io_requestor_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), .io_requestor_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), .io_requestor_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), .io_requestor_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), .io_requestor_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), .io_requestor_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), .io_requestor_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), .io_requestor_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), .io_requestor_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), .io_requestor_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), .io_requestor_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), .io_requestor_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), .io_requestor_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), .io_requestor_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), .io_requestor_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), .io_requestor_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), .io_requestor_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), .io_requestor_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), .io_requestor_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), .io_requestor_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), .io_requestor_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), .io_requestor_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), .io_requestor_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), .io_requestor_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), .io_requestor_1_status_debug (_ptw_io_requestor_1_status_debug), .io_requestor_1_status_cease (_ptw_io_requestor_1_status_cease), .io_requestor_1_status_wfi (_ptw_io_requestor_1_status_wfi), .io_requestor_1_status_isa (_ptw_io_requestor_1_status_isa), .io_requestor_1_status_dprv (_ptw_io_requestor_1_status_dprv), .io_requestor_1_status_dv (_ptw_io_requestor_1_status_dv), .io_requestor_1_status_prv (_ptw_io_requestor_1_status_prv), .io_requestor_1_status_v (_ptw_io_requestor_1_status_v), .io_requestor_1_status_sd (_ptw_io_requestor_1_status_sd), .io_requestor_1_status_mpv (_ptw_io_requestor_1_status_mpv), .io_requestor_1_status_gva (_ptw_io_requestor_1_status_gva), .io_requestor_1_status_tsr (_ptw_io_requestor_1_status_tsr), .io_requestor_1_status_tw (_ptw_io_requestor_1_status_tw), .io_requestor_1_status_tvm (_ptw_io_requestor_1_status_tvm), .io_requestor_1_status_mxr (_ptw_io_requestor_1_status_mxr), .io_requestor_1_status_sum (_ptw_io_requestor_1_status_sum), .io_requestor_1_status_mprv (_ptw_io_requestor_1_status_mprv), .io_requestor_1_status_fs (_ptw_io_requestor_1_status_fs), .io_requestor_1_status_mpp (_ptw_io_requestor_1_status_mpp), .io_requestor_1_status_spp (_ptw_io_requestor_1_status_spp), .io_requestor_1_status_mpie (_ptw_io_requestor_1_status_mpie), .io_requestor_1_status_spie (_ptw_io_requestor_1_status_spie), .io_requestor_1_status_mie (_ptw_io_requestor_1_status_mie), .io_requestor_1_status_sie (_ptw_io_requestor_1_status_sie), .io_requestor_1_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), .io_requestor_1_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), .io_requestor_1_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), .io_requestor_1_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), .io_requestor_1_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), .io_requestor_1_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), .io_requestor_1_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), .io_requestor_1_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), .io_requestor_1_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), .io_requestor_1_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), .io_requestor_1_gstatus_v (_ptw_io_requestor_1_gstatus_v), .io_requestor_1_gstatus_sd (_ptw_io_requestor_1_gstatus_sd), .io_requestor_1_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), .io_requestor_1_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), .io_requestor_1_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), .io_requestor_1_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), .io_requestor_1_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), .io_requestor_1_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), .io_requestor_1_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), .io_requestor_1_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), .io_requestor_1_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), .io_requestor_1_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), .io_requestor_1_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), .io_requestor_1_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), .io_requestor_1_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), .io_requestor_1_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), .io_requestor_1_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), .io_requestor_1_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), .io_requestor_1_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), .io_requestor_1_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), .io_requestor_1_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), .io_requestor_1_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), .io_requestor_1_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), .io_requestor_1_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), .io_requestor_1_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), .io_requestor_1_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), .io_requestor_1_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), .io_requestor_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), .io_requestor_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), .io_requestor_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), .io_requestor_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), .io_requestor_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), .io_requestor_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), .io_requestor_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), .io_requestor_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), .io_requestor_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), .io_requestor_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), .io_requestor_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), .io_requestor_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), .io_requestor_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), .io_requestor_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), .io_requestor_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), .io_requestor_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), .io_requestor_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), .io_requestor_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), .io_requestor_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), .io_requestor_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), .io_requestor_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), .io_requestor_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), .io_requestor_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), .io_requestor_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), .io_requestor_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), .io_requestor_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), .io_requestor_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), .io_requestor_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), .io_requestor_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), .io_requestor_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), .io_requestor_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), .io_requestor_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), .io_requestor_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), .io_requestor_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), .io_requestor_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), .io_requestor_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), .io_requestor_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), .io_requestor_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), .io_requestor_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), .io_requestor_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), .io_requestor_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), .io_requestor_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), .io_requestor_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), .io_requestor_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), .io_requestor_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), .io_requestor_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), .io_requestor_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), .io_requestor_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), .io_requestor_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), .io_requestor_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), .io_requestor_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), .io_requestor_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), .io_requestor_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), .io_requestor_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), .io_requestor_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), .io_requestor_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), .io_requestor_1_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), .io_requestor_1_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), .io_requestor_1_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), .io_requestor_1_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), .io_requestor_1_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), .io_requestor_1_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), .io_requestor_1_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), .io_requestor_1_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), .io_requestor_1_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), .io_requestor_1_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), .io_requestor_1_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), .io_requestor_1_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), .io_requestor_1_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), .io_requestor_1_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), .io_requestor_1_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), .io_requestor_1_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value), .io_mem_req_ready (_dcacheArb_io_requestor_0_req_ready), // @[HellaCache.scala:292:25] .io_mem_req_valid (_ptw_io_mem_req_valid), .io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr), .io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv), .io_mem_s1_kill (_ptw_io_mem_s1_kill), .io_mem_s2_nack (_dcacheArb_io_requestor_0_s2_nack), // @[HellaCache.scala:292:25] .io_mem_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), // @[HellaCache.scala:292:25] .io_mem_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), // @[HellaCache.scala:292:25] .io_mem_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), // @[HellaCache.scala:292:25] .io_mem_resp_valid (_dcacheArb_io_requestor_0_resp_valid), // @[HellaCache.scala:292:25] .io_mem_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), // @[HellaCache.scala:292:25] .io_mem_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), // @[HellaCache.scala:292:25] .io_mem_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_mem_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), // @[HellaCache.scala:292:25] .io_mem_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), // @[HellaCache.scala:292:25] .io_mem_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_mem_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), // @[HellaCache.scala:292:25] .io_mem_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), // @[HellaCache.scala:292:25] .io_mem_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), // @[HellaCache.scala:292:25] .io_mem_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_mem_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_mem_replay_next (_dcacheArb_io_requestor_0_replay_next), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_mem_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), // @[HellaCache.scala:292:25] .io_mem_ordered (_dcacheArb_io_requestor_0_ordered), // @[HellaCache.scala:292:25] .io_mem_store_pending (_dcacheArb_io_requestor_0_store_pending), // @[HellaCache.scala:292:25] .io_mem_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), // @[HellaCache.scala:292:25] .io_mem_perf_release (_dcacheArb_io_requestor_0_perf_release), // @[HellaCache.scala:292:25] .io_mem_perf_grant (_dcacheArb_io_requestor_0_perf_grant), // @[HellaCache.scala:292:25] .io_mem_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_mem_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25] .io_mem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25] .io_mem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25] .io_dpath_ptbr_mode (_core_io_ptw_ptbr_mode), // @[RocketTile.scala:147:20] .io_dpath_ptbr_ppn (_core_io_ptw_ptbr_ppn), // @[RocketTile.scala:147:20] .io_dpath_sfence_valid (_core_io_ptw_sfence_valid), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), // @[RocketTile.scala:147:20] .io_dpath_status_debug (_core_io_ptw_status_debug), // @[RocketTile.scala:147:20] .io_dpath_status_cease (_core_io_ptw_status_cease), // @[RocketTile.scala:147:20] .io_dpath_status_wfi (_core_io_ptw_status_wfi), // @[RocketTile.scala:147:20] .io_dpath_status_isa (_core_io_ptw_status_isa), // @[RocketTile.scala:147:20] .io_dpath_status_dprv (_core_io_ptw_status_dprv), // @[RocketTile.scala:147:20] .io_dpath_status_dv (_core_io_ptw_status_dv), // @[RocketTile.scala:147:20] .io_dpath_status_prv (_core_io_ptw_status_prv), // @[RocketTile.scala:147:20] .io_dpath_status_v (_core_io_ptw_status_v), // @[RocketTile.scala:147:20] .io_dpath_status_sd (_core_io_ptw_status_sd), // @[RocketTile.scala:147:20] .io_dpath_status_mpv (_core_io_ptw_status_mpv), // @[RocketTile.scala:147:20] .io_dpath_status_gva (_core_io_ptw_status_gva), // @[RocketTile.scala:147:20] .io_dpath_status_tsr (_core_io_ptw_status_tsr), // @[RocketTile.scala:147:20] .io_dpath_status_tw (_core_io_ptw_status_tw), // @[RocketTile.scala:147:20] .io_dpath_status_tvm (_core_io_ptw_status_tvm), // @[RocketTile.scala:147:20] .io_dpath_status_mxr (_core_io_ptw_status_mxr), // @[RocketTile.scala:147:20] .io_dpath_status_sum (_core_io_ptw_status_sum), // @[RocketTile.scala:147:20] .io_dpath_status_mprv (_core_io_ptw_status_mprv), // @[RocketTile.scala:147:20] .io_dpath_status_fs (_core_io_ptw_status_fs), // @[RocketTile.scala:147:20] .io_dpath_status_mpp (_core_io_ptw_status_mpp), // @[RocketTile.scala:147:20] .io_dpath_status_spp (_core_io_ptw_status_spp), // @[RocketTile.scala:147:20] .io_dpath_status_mpie (_core_io_ptw_status_mpie), // @[RocketTile.scala:147:20] .io_dpath_status_spie (_core_io_ptw_status_spie), // @[RocketTile.scala:147:20] .io_dpath_status_mie (_core_io_ptw_status_mie), // @[RocketTile.scala:147:20] .io_dpath_status_sie (_core_io_ptw_status_sie), // @[RocketTile.scala:147:20] .io_dpath_hstatus_spvp (_core_io_ptw_hstatus_spvp), // @[RocketTile.scala:147:20] .io_dpath_hstatus_spv (_core_io_ptw_hstatus_spv), // @[RocketTile.scala:147:20] .io_dpath_hstatus_gva (_core_io_ptw_hstatus_gva), // @[RocketTile.scala:147:20] .io_dpath_gstatus_debug (_core_io_ptw_gstatus_debug), // @[RocketTile.scala:147:20] .io_dpath_gstatus_cease (_core_io_ptw_gstatus_cease), // @[RocketTile.scala:147:20] .io_dpath_gstatus_wfi (_core_io_ptw_gstatus_wfi), // @[RocketTile.scala:147:20] .io_dpath_gstatus_isa (_core_io_ptw_gstatus_isa), // @[RocketTile.scala:147:20] .io_dpath_gstatus_dprv (_core_io_ptw_gstatus_dprv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_dv (_core_io_ptw_gstatus_dv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_prv (_core_io_ptw_gstatus_prv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_v (_core_io_ptw_gstatus_v), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sd (_core_io_ptw_gstatus_sd), // @[RocketTile.scala:147:20] .io_dpath_gstatus_zero2 (_core_io_ptw_gstatus_zero2), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpv (_core_io_ptw_gstatus_mpv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_gva (_core_io_ptw_gstatus_gva), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mbe (_core_io_ptw_gstatus_mbe), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sbe (_core_io_ptw_gstatus_sbe), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sxl (_core_io_ptw_gstatus_sxl), // @[RocketTile.scala:147:20] .io_dpath_gstatus_zero1 (_core_io_ptw_gstatus_zero1), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tsr (_core_io_ptw_gstatus_tsr), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tw (_core_io_ptw_gstatus_tw), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tvm (_core_io_ptw_gstatus_tvm), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mxr (_core_io_ptw_gstatus_mxr), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sum (_core_io_ptw_gstatus_sum), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mprv (_core_io_ptw_gstatus_mprv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_fs (_core_io_ptw_gstatus_fs), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpp (_core_io_ptw_gstatus_mpp), // @[RocketTile.scala:147:20] .io_dpath_gstatus_vs (_core_io_ptw_gstatus_vs), // @[RocketTile.scala:147:20] .io_dpath_gstatus_spp (_core_io_ptw_gstatus_spp), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpie (_core_io_ptw_gstatus_mpie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_ube (_core_io_ptw_gstatus_ube), // @[RocketTile.scala:147:20] .io_dpath_gstatus_spie (_core_io_ptw_gstatus_spie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_upie (_core_io_ptw_gstatus_upie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mie (_core_io_ptw_gstatus_mie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_hie (_core_io_ptw_gstatus_hie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sie (_core_io_ptw_gstatus_sie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_uie (_core_io_ptw_gstatus_uie), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_addr (_core_io_ptw_pmp_0_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_mask (_core_io_ptw_pmp_0_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_addr (_core_io_ptw_pmp_1_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_mask (_core_io_ptw_pmp_1_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_addr (_core_io_ptw_pmp_2_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_mask (_core_io_ptw_pmp_2_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_addr (_core_io_ptw_pmp_3_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_mask (_core_io_ptw_pmp_3_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_addr (_core_io_ptw_pmp_4_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_mask (_core_io_ptw_pmp_4_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_addr (_core_io_ptw_pmp_5_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_mask (_core_io_ptw_pmp_5_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_addr (_core_io_ptw_pmp_6_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_mask (_core_io_ptw_pmp_6_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_addr (_core_io_ptw_pmp_7_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_mask (_core_io_ptw_pmp_7_mask), // @[RocketTile.scala:147:20] .io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), .io_dpath_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), .io_dpath_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), // @[RocketTile.scala:147:20] .io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled) ); // @[PTW.scala:802:19] Rocket_1 core ( // @[RocketTile.scala:147:20] .clock (clock), .reset (reset), .io_hartid (hartIdSinkNodeIn), // @[MixedNode.scala:551:17] .io_interrupts_debug (intSinkNodeIn_0), // @[MixedNode.scala:551:17] .io_interrupts_mtip (intSinkNodeIn_2), // @[MixedNode.scala:551:17] .io_interrupts_msip (intSinkNodeIn_1), // @[MixedNode.scala:551:17] .io_interrupts_meip (intSinkNodeIn_3), // @[MixedNode.scala:551:17] .io_interrupts_seip (intSinkNodeIn_4), // @[MixedNode.scala:551:17] .io_imem_might_request (_core_io_imem_might_request), .io_imem_req_valid (_core_io_imem_req_valid), .io_imem_req_bits_pc (_core_io_imem_req_bits_pc), .io_imem_req_bits_speculative (_core_io_imem_req_bits_speculative), .io_imem_sfence_valid (_core_io_imem_sfence_valid), .io_imem_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), .io_imem_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), .io_imem_sfence_bits_addr (_core_io_imem_sfence_bits_addr), .io_imem_sfence_bits_asid (_core_io_imem_sfence_bits_asid), .io_imem_sfence_bits_hv (_core_io_imem_sfence_bits_hv), .io_imem_sfence_bits_hg (_core_io_imem_sfence_bits_hg), .io_imem_resp_ready (_core_io_imem_resp_ready), .io_imem_resp_valid (_frontend_io_cpu_resp_valid), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), // @[Frontend.scala:393:28] .io_imem_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), // @[Frontend.scala:393:28] .io_imem_resp_bits_data (_frontend_io_cpu_resp_bits_data), // @[Frontend.scala:393:28] .io_imem_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), // @[Frontend.scala:393:28] .io_imem_gpa_valid (_frontend_io_cpu_gpa_valid), // @[Frontend.scala:393:28] .io_imem_gpa_bits (_frontend_io_cpu_gpa_bits), // @[Frontend.scala:393:28] .io_imem_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), // @[Frontend.scala:393:28] .io_imem_btb_update_valid (_core_io_imem_btb_update_valid), .io_imem_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), .io_imem_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), .io_imem_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), .io_imem_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), .io_imem_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), .io_imem_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), .io_imem_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), .io_imem_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), .io_imem_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), .io_imem_btb_update_bits_target (_core_io_imem_btb_update_bits_target), .io_imem_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), .io_imem_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), .io_imem_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), .io_imem_bht_update_valid (_core_io_imem_bht_update_valid), .io_imem_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), .io_imem_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), .io_imem_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), .io_imem_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), .io_imem_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), .io_imem_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), .io_imem_flush_icache (_core_io_imem_flush_icache), .io_imem_npc (_frontend_io_cpu_npc), // @[Frontend.scala:393:28] .io_imem_perf_acquire (_frontend_io_cpu_perf_acquire), // @[Frontend.scala:393:28] .io_imem_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), // @[Frontend.scala:393:28] .io_imem_progress (_core_io_imem_progress), .io_dmem_req_ready (_dcacheArb_io_requestor_1_req_ready), // @[HellaCache.scala:292:25] .io_dmem_req_valid (_core_io_dmem_req_valid), .io_dmem_req_bits_addr (_core_io_dmem_req_bits_addr), .io_dmem_req_bits_tag (_core_io_dmem_req_bits_tag), .io_dmem_req_bits_cmd (_core_io_dmem_req_bits_cmd), .io_dmem_req_bits_size (_core_io_dmem_req_bits_size), .io_dmem_req_bits_signed (_core_io_dmem_req_bits_signed), .io_dmem_req_bits_dprv (_core_io_dmem_req_bits_dprv), .io_dmem_req_bits_dv (_core_io_dmem_req_bits_dv), .io_dmem_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), .io_dmem_s1_kill (_core_io_dmem_s1_kill), .io_dmem_s1_data_data (_core_io_dmem_s1_data_data), .io_dmem_s2_nack (_dcacheArb_io_requestor_1_s2_nack), // @[HellaCache.scala:292:25] .io_dmem_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), // @[HellaCache.scala:292:25] .io_dmem_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), // @[HellaCache.scala:292:25] .io_dmem_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), // @[HellaCache.scala:292:25] .io_dmem_resp_valid (_dcacheArb_io_requestor_1_resp_valid), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_dmem_replay_next (_dcacheArb_io_requestor_1_replay_next), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_dmem_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), // @[HellaCache.scala:292:25] .io_dmem_ordered (_dcacheArb_io_requestor_1_ordered), // @[HellaCache.scala:292:25] .io_dmem_store_pending (_dcacheArb_io_requestor_1_store_pending), // @[HellaCache.scala:292:25] .io_dmem_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), // @[HellaCache.scala:292:25] .io_dmem_perf_release (_dcacheArb_io_requestor_1_perf_release), // @[HellaCache.scala:292:25] .io_dmem_perf_grant (_dcacheArb_io_requestor_1_perf_grant), // @[HellaCache.scala:292:25] .io_dmem_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_dmem_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25] .io_dmem_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), .io_ptw_ptbr_mode (_core_io_ptw_ptbr_mode), .io_ptw_ptbr_ppn (_core_io_ptw_ptbr_ppn), .io_ptw_sfence_valid (_core_io_ptw_sfence_valid), .io_ptw_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), .io_ptw_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), .io_ptw_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), .io_ptw_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), .io_ptw_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), .io_ptw_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), .io_ptw_status_debug (_core_io_ptw_status_debug), .io_ptw_status_cease (_core_io_ptw_status_cease), .io_ptw_status_wfi (_core_io_ptw_status_wfi), .io_ptw_status_isa (_core_io_ptw_status_isa), .io_ptw_status_dprv (_core_io_ptw_status_dprv), .io_ptw_status_dv (_core_io_ptw_status_dv), .io_ptw_status_prv (_core_io_ptw_status_prv), .io_ptw_status_v (_core_io_ptw_status_v), .io_ptw_status_sd (_core_io_ptw_status_sd), .io_ptw_status_mpv (_core_io_ptw_status_mpv), .io_ptw_status_gva (_core_io_ptw_status_gva), .io_ptw_status_tsr (_core_io_ptw_status_tsr), .io_ptw_status_tw (_core_io_ptw_status_tw), .io_ptw_status_tvm (_core_io_ptw_status_tvm), .io_ptw_status_mxr (_core_io_ptw_status_mxr), .io_ptw_status_sum (_core_io_ptw_status_sum), .io_ptw_status_mprv (_core_io_ptw_status_mprv), .io_ptw_status_fs (_core_io_ptw_status_fs), .io_ptw_status_mpp (_core_io_ptw_status_mpp), .io_ptw_status_spp (_core_io_ptw_status_spp), .io_ptw_status_mpie (_core_io_ptw_status_mpie), .io_ptw_status_spie (_core_io_ptw_status_spie), .io_ptw_status_mie (_core_io_ptw_status_mie), .io_ptw_status_sie (_core_io_ptw_status_sie), .io_ptw_hstatus_spvp (_core_io_ptw_hstatus_spvp), .io_ptw_hstatus_spv (_core_io_ptw_hstatus_spv), .io_ptw_hstatus_gva (_core_io_ptw_hstatus_gva), .io_ptw_gstatus_debug (_core_io_ptw_gstatus_debug), .io_ptw_gstatus_cease (_core_io_ptw_gstatus_cease), .io_ptw_gstatus_wfi (_core_io_ptw_gstatus_wfi), .io_ptw_gstatus_isa (_core_io_ptw_gstatus_isa), .io_ptw_gstatus_dprv (_core_io_ptw_gstatus_dprv), .io_ptw_gstatus_dv (_core_io_ptw_gstatus_dv), .io_ptw_gstatus_prv (_core_io_ptw_gstatus_prv), .io_ptw_gstatus_v (_core_io_ptw_gstatus_v), .io_ptw_gstatus_sd (_core_io_ptw_gstatus_sd), .io_ptw_gstatus_zero2 (_core_io_ptw_gstatus_zero2), .io_ptw_gstatus_mpv (_core_io_ptw_gstatus_mpv), .io_ptw_gstatus_gva (_core_io_ptw_gstatus_gva), .io_ptw_gstatus_mbe (_core_io_ptw_gstatus_mbe), .io_ptw_gstatus_sbe (_core_io_ptw_gstatus_sbe), .io_ptw_gstatus_sxl (_core_io_ptw_gstatus_sxl), .io_ptw_gstatus_zero1 (_core_io_ptw_gstatus_zero1), .io_ptw_gstatus_tsr (_core_io_ptw_gstatus_tsr), .io_ptw_gstatus_tw (_core_io_ptw_gstatus_tw), .io_ptw_gstatus_tvm (_core_io_ptw_gstatus_tvm), .io_ptw_gstatus_mxr (_core_io_ptw_gstatus_mxr), .io_ptw_gstatus_sum (_core_io_ptw_gstatus_sum), .io_ptw_gstatus_mprv (_core_io_ptw_gstatus_mprv), .io_ptw_gstatus_fs (_core_io_ptw_gstatus_fs), .io_ptw_gstatus_mpp (_core_io_ptw_gstatus_mpp), .io_ptw_gstatus_vs (_core_io_ptw_gstatus_vs), .io_ptw_gstatus_spp (_core_io_ptw_gstatus_spp), .io_ptw_gstatus_mpie (_core_io_ptw_gstatus_mpie), .io_ptw_gstatus_ube (_core_io_ptw_gstatus_ube), .io_ptw_gstatus_spie (_core_io_ptw_gstatus_spie), .io_ptw_gstatus_upie (_core_io_ptw_gstatus_upie), .io_ptw_gstatus_mie (_core_io_ptw_gstatus_mie), .io_ptw_gstatus_hie (_core_io_ptw_gstatus_hie), .io_ptw_gstatus_sie (_core_io_ptw_gstatus_sie), .io_ptw_gstatus_uie (_core_io_ptw_gstatus_uie), .io_ptw_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), .io_ptw_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), .io_ptw_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), .io_ptw_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), .io_ptw_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), .io_ptw_pmp_0_addr (_core_io_ptw_pmp_0_addr), .io_ptw_pmp_0_mask (_core_io_ptw_pmp_0_mask), .io_ptw_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), .io_ptw_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), .io_ptw_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), .io_ptw_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), .io_ptw_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), .io_ptw_pmp_1_addr (_core_io_ptw_pmp_1_addr), .io_ptw_pmp_1_mask (_core_io_ptw_pmp_1_mask), .io_ptw_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), .io_ptw_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), .io_ptw_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), .io_ptw_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), .io_ptw_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), .io_ptw_pmp_2_addr (_core_io_ptw_pmp_2_addr), .io_ptw_pmp_2_mask (_core_io_ptw_pmp_2_mask), .io_ptw_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), .io_ptw_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), .io_ptw_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), .io_ptw_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), .io_ptw_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), .io_ptw_pmp_3_addr (_core_io_ptw_pmp_3_addr), .io_ptw_pmp_3_mask (_core_io_ptw_pmp_3_mask), .io_ptw_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), .io_ptw_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), .io_ptw_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), .io_ptw_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), .io_ptw_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), .io_ptw_pmp_4_addr (_core_io_ptw_pmp_4_addr), .io_ptw_pmp_4_mask (_core_io_ptw_pmp_4_mask), .io_ptw_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), .io_ptw_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), .io_ptw_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), .io_ptw_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), .io_ptw_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), .io_ptw_pmp_5_addr (_core_io_ptw_pmp_5_addr), .io_ptw_pmp_5_mask (_core_io_ptw_pmp_5_mask), .io_ptw_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), .io_ptw_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), .io_ptw_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), .io_ptw_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), .io_ptw_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), .io_ptw_pmp_6_addr (_core_io_ptw_pmp_6_addr), .io_ptw_pmp_6_mask (_core_io_ptw_pmp_6_mask), .io_ptw_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), .io_ptw_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), .io_ptw_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), .io_ptw_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), .io_ptw_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), .io_ptw_pmp_7_addr (_core_io_ptw_pmp_7_addr), .io_ptw_pmp_7_mask (_core_io_ptw_pmp_7_mask), .io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[PTW.scala:802:19] .io_ptw_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), .io_ptw_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), .io_ptw_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), .io_ptw_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), .io_ptw_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), .io_ptw_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), .io_ptw_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), .io_ptw_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), .io_ptw_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), .io_ptw_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), .io_ptw_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), .io_ptw_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), .io_ptw_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), .io_ptw_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), .io_ptw_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), .io_ptw_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), .io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled), // @[PTW.scala:802:19] .io_fpu_hartid (_core_io_fpu_hartid), .io_fpu_time (_core_io_fpu_time), .io_fpu_inst (_core_io_fpu_inst), .io_fpu_fromint_data (_core_io_fpu_fromint_data), .io_fpu_fcsr_rm (_core_io_fpu_fcsr_rm), .io_fpu_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), // @[RocketTile.scala:242:62] .io_fpu_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), // @[RocketTile.scala:242:62] .io_fpu_store_data (_fpuOpt_io_store_data), // @[RocketTile.scala:242:62] .io_fpu_toint_data (_fpuOpt_io_toint_data), // @[RocketTile.scala:242:62] .io_fpu_ll_resp_val (_core_io_fpu_ll_resp_val), .io_fpu_ll_resp_type (_core_io_fpu_ll_resp_type), .io_fpu_ll_resp_tag (_core_io_fpu_ll_resp_tag), .io_fpu_ll_resp_data (_core_io_fpu_ll_resp_data), .io_fpu_valid (_core_io_fpu_valid), .io_fpu_fcsr_rdy (_fpuOpt_io_fcsr_rdy), // @[RocketTile.scala:242:62] .io_fpu_nack_mem (_fpuOpt_io_nack_mem), // @[RocketTile.scala:242:62] .io_fpu_illegal_rm (_fpuOpt_io_illegal_rm), // @[RocketTile.scala:242:62] .io_fpu_killx (_core_io_fpu_killx), .io_fpu_killm (_core_io_fpu_killm), .io_fpu_dec_ldst (_fpuOpt_io_dec_ldst), // @[RocketTile.scala:242:62] .io_fpu_dec_wen (_fpuOpt_io_dec_wen), // @[RocketTile.scala:242:62] .io_fpu_dec_ren1 (_fpuOpt_io_dec_ren1), // @[RocketTile.scala:242:62] .io_fpu_dec_ren2 (_fpuOpt_io_dec_ren2), // @[RocketTile.scala:242:62] .io_fpu_dec_ren3 (_fpuOpt_io_dec_ren3), // @[RocketTile.scala:242:62] .io_fpu_dec_swap12 (_fpuOpt_io_dec_swap12), // @[RocketTile.scala:242:62] .io_fpu_dec_swap23 (_fpuOpt_io_dec_swap23), // @[RocketTile.scala:242:62] .io_fpu_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), // @[RocketTile.scala:242:62] .io_fpu_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), // @[RocketTile.scala:242:62] .io_fpu_dec_fromint (_fpuOpt_io_dec_fromint), // @[RocketTile.scala:242:62] .io_fpu_dec_toint (_fpuOpt_io_dec_toint), // @[RocketTile.scala:242:62] .io_fpu_dec_fastpipe (_fpuOpt_io_dec_fastpipe), // @[RocketTile.scala:242:62] .io_fpu_dec_fma (_fpuOpt_io_dec_fma), // @[RocketTile.scala:242:62] .io_fpu_dec_div (_fpuOpt_io_dec_div), // @[RocketTile.scala:242:62] .io_fpu_dec_sqrt (_fpuOpt_io_dec_sqrt), // @[RocketTile.scala:242:62] .io_fpu_dec_wflags (_fpuOpt_io_dec_wflags), // @[RocketTile.scala:242:62] .io_fpu_dec_vec (_fpuOpt_io_dec_vec), // @[RocketTile.scala:242:62] .io_fpu_sboard_set (_fpuOpt_io_sboard_set), // @[RocketTile.scala:242:62] .io_fpu_sboard_clr (_fpuOpt_io_sboard_clr), // @[RocketTile.scala:242:62] .io_fpu_sboard_clra (_fpuOpt_io_sboard_clra), // @[RocketTile.scala:242:62] .io_fpu_keep_clock_enabled (_core_io_fpu_keep_clock_enabled), .io_trace_insns_0_valid (traceSourceNodeOut_insns_0_valid), .io_trace_insns_0_iaddr (traceSourceNodeOut_insns_0_iaddr), .io_trace_insns_0_insn (traceSourceNodeOut_insns_0_insn), .io_trace_insns_0_priv (traceSourceNodeOut_insns_0_priv), .io_trace_insns_0_exception (traceSourceNodeOut_insns_0_exception), .io_trace_insns_0_interrupt (traceSourceNodeOut_insns_0_interrupt), .io_trace_insns_0_cause (traceSourceNodeOut_insns_0_cause), .io_trace_insns_0_tval (traceSourceNodeOut_insns_0_tval), .io_trace_time (traceSourceNodeOut_time), .io_bpwatch_0_valid_0 (bpwatchSourceNodeOut_0_valid_0), .io_bpwatch_0_action (bpwatchSourceNodeOut_0_action), .io_wfi (_core_io_wfi) ); // @[RocketTile.scala:147:20] assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_b_ready = auto_buffer_out_b_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_valid = auto_buffer_out_c_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_opcode = auto_buffer_out_c_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_param = auto_buffer_out_c_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_size = auto_buffer_out_c_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_source = auto_buffer_out_c_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_address = auto_buffer_out_c_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_data = auto_buffer_out_c_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_e_valid = auto_buffer_out_e_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_e_bits_sink = auto_buffer_out_e_bits_sink_0; // @[RocketTile.scala:141:7] assign auto_wfi_out_0 = auto_wfi_out_0_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_valid = auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_iaddr = auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_insn = auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_priv = auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_exception = auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_interrupt = auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_cause = auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_tval = auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_time = auto_trace_source_out_time_0; // @[RocketTile.scala:141:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_233( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_13( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1502 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1502; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1502; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1575 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1575; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [4:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1428 = _T_1502 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1428 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1428 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1428 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1428 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1428 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1474 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1474 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1443 = _T_1575 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1443 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1443 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1443 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1546 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1546 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1528 = _T_1575 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1528 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1528 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1528 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_274( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_18 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File IngressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class IngressUnit( ingressNodeId: Int, cParam: IngressChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean, ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits))) } val io = IO(new IngressUnitIO) val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2, flow=combineRCVA)) assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR)) route_buffer.io.enq.bits.head := io.in.bits.head route_buffer.io.enq.bits.tail := io.in.bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { route_buffer.io.enq.bits.flow := DontCare } else { route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U route_buffer.io.enq.bits.flow.egress_node := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNode.U) ) route_buffer.io.enq.bits.flow.egress_node_id := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNodeId.U) ) } route_buffer.io.enq.bits.payload := io.in.bits.payload route_buffer.io.enq.bits.virt_channel_id := DontCare io.router_req.bits.src_virt_id := 0.U io.router_req.bits.flow := route_buffer.io.enq.bits.flow val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U route_buffer.io.enq.valid := io.in.valid && ( io.router_req.ready \|\| !io.in.bits.head \|\| at_dest) io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest io.in.ready := route_buffer.io.enq.ready && ( io.router_req.ready \|\| !io.in.bits.head \|\| at_dest) route_q.io.enq.valid := io.router_req.fire route_q.io.enq.bits := io.router_resp when (io.in.fire && io.in.bits.head && at_dest) { route_q.io.enq.valid := true.B route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (egressParams(o).egressId.U === io.in.bits.egress_id) { route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B } } } assert(!(route_q.io.enq.valid && !route_q.io.enq.ready)) val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams), 1, pipe=true)) vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow io.vcalloc_req.bits.in_vc := 0.U val head = route_buffer.io.deq.bits.head val tail = route_buffer.io.deq.bits.tail vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid && (route_q.io.deq.valid \|\| !head) && (io.vcalloc_req.ready \|\| !head) ) io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid && head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready) route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready && (route_q.io.deq.valid \|\| !head) && (io.vcalloc_req.ready \|\| !head) && (vcalloc_q.io.enq.ready \|\| !head)) route_q.io.deq.ready := (route_buffer.io.deq.fire && tail) vcalloc_q.io.enq.valid := io.vcalloc_req.fire vcalloc_q.io.enq.bits := io.vcalloc_resp assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready)) io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire val out_bundle = if (combineSAST) { Wire(Valid(new SwitchBundle(outParams, egressParams))) } else { Reg(Valid(new SwitchBundle(outParams, egressParams))) } io.out(0) := out_bundle out_bundle.valid := vcalloc_buffer.io.deq.fire out_bundle.bits.flit := vcalloc_buffer.io.deq.bits out_bundle.bits.flit.virt_channel_id := 0.U val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_\|\|_)).toSeq out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh, vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq) io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready // TODO: We should not generate input/ingress/output/egress units for untraversable channels if (!cParam.traversable) { io.in.ready := false.B io.router_req.valid := false.B io.router_req.bits := DontCare io.vcalloc_req.valid := false.B io.vcalloc_req.bits := DontCare io.salloc_req.foreach(_.valid := false.B) io.salloc_req.foreach(_.bits := DontCare) io.out.foreach(_.valid := false.B) io.out.foreach(_.bits := DontCare) } }	module IngressUnit_9( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_7_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_6_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_5_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_7_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_6_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_5_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_4_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_10, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_11, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_12, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_13, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_14, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_15, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_16, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_17, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_18, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_19, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_20, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_21, // @[IngressUnit.scala:24:14] input io_out_credit_available_7_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_6_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_5_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_4_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_8, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_10, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_11, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_12, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_13, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_14, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_15, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_16, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_17, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_18, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_19, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_20, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_21, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_7_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_6_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_5_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [5:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [5:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [5:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _GEN; // @[Decoupled.scala:51:35] wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_7_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_6_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_5_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_4_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_10; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_11; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_12; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_13; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_14; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_15; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_16; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_17; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_18; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_19; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_20; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_21; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [5:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [5:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [5:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [5:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 6'h27; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 6'h2A; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 6'h2D; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 6'h30; // @[IngressUnit.scala:30:72] wire [2:0] _GEN_0 = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_1, 1'h0} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 3'h6 : 3'h0); // @[Mux.scala:30:73] wire [2:0] _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = {1'h0, {2{_route_buffer_io_enq_bits_flow_egress_node_id_T}}} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h5 : 3'h0); // @[Mux.scala:30:73] wire [2:0] _GEN_1 = {_route_buffer_io_enq_bits_flow_egress_node_id_T_2, _GEN_0[2:1]}; // @[Mux.scala:30:73] assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _GEN_1 == 3'h1; // @[Decoupled.scala:51:35] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _GEN_1 != 3'h1; // @[Decoupled.scala:51:35] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLBuffer_a32d64s3k3z4c_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire nodeOut_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire [63:0] auto_out_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_source = 3'h0; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_source = 3'h0; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_40 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s3k3z4c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s3k3z4c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d64s3k3z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d64s3k3z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d64s3k3z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DivSqrtRecFN_small.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2017 SiFive, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of SiFive nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ /* s = sigWidth c_i = newBit Division: width of a is (s+2) Normal ------ (qi + ci * 2^(-i))b <= a q0 = 0 r0 = a q(i+1) = qi + ci2^(-i) ri = a - qib r(i+1) = a - q(i+1)b = a - qib - ci2^(-i)b r(i+1) = ri - ci2^(-i)b ci = ri >= 2^(-i)b summary_i = ri != 0 i = 0 to s+1 (s+1)th bit plus summary_(i+1) gives enough information for rounding If (a < b), then we need to calculate (s+2)th bit and summary_(i+1) because we need s bits ignoring the leading zero. (This is skipCycle2 part of Hauser's code.) Hauser ------ sig_i = qi rem_i = 2^(i-2)ri cycle_i = s+3-i sig_0 = 0 rem_0 = a/4 cycle_0 = s+3 bit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits) sig(i+1) = sig(i) + cibit_i rem(i+1) = 2rem_i - cib/2 ci = 2rem_i >= b/2 bit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits) cycle(i+1) = cycle_i-1 summary_1 = a <> b summary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0 Proof: 2^ir(i+1) = 2^iri - cib. Qed ci = 2^iri >= b. Qed summary(i+1) = if ci then rem(i+1) else summary_i, i <> 0 Now, note that all of ck's cannot be 0, since that means a is 0. So when you traverse through a chain of 0 ck's, from the end, eventually, you reach a non-zero cj. That is exactly the value of ri as the reminder remains the same. When all ck's are 0 except c0 (which must be 1) then summary_1 is set correctly according to r1 = a-b != 0. So summary(i+1) is always set correctly according to r(i+1) Square root: width of a is (s+1) Normal ------ (xi + ci2^(-i))^2 <= a xi^2 + ci2^(-i)(2xi+ci2^(-i)) <= a x0 = 0 x(i+1) = xi + ci2^(-i) ri = a - xi^2 r(i+1) = a - x(i+1)^2 = a - (xi^2 + ci2^(-i)(2xi+ci2^(-i))) = ri - ci2^(-i)(2xi+ci2^(-i)) = ri - ci2^(-i)(2xi+2^(-i)) // ci is always 0 or 1 ci = ri >= 2^(-i)(2xi + 2^(-i)) summary_i = ri != 0 i = 0 to s+1 For odd expression, do 2 steps initially. (s+1)th bit plus summary_(i+1) gives enough information for rounding. Hauser ------ sig_i = xi rem_i = ri2^(i-1) cycle_i = s+2-i bit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation) sig_0 = 0 rem_0 = a/2 cycle_0 = s+2 bit_0 = 1 (= 2^s in terms of bit representation) sig(i+1) = sig_i + ci * bit_i rem(i+1) = 2rem_i - ci(2sig_i + bit_i) ci = 2sig_i + bit_i <= 2rem_i bit_i = 2^(cycle_i-2) (in terms of bit representation) cycle(i+1) = cycle_i-1 summary_1 = a - (2^s) (in terms of bit representation) summary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0 Proof: ci = 2sig_i + bit_i <= 2rem_i ci = 2xi + 2^(-i) <= ri2^i. Qed sig(i+1) = sig_i + ci * bit_i x(i+1) = xi + ci2^(-i). Qed rem(i+1) = 2rem_i - ci(2sig_i + bit_i) r(i+1)2^i = ri2^i - ci(2xi + 2^(-i)) r(i+1) = ri - ci2^(-i)(2xi + 2^(-i)). Qed Same argument as before for summary. ------------------------------ Note that all registers are updated normally until cycle == 2. At cycle == 2, rem is not updated, but all other registers are updated normally. But, cycle == 1 does not read rem to calculate anything (note that final summary is calculated using the values at cycle = 2). / package hardfloat import chisel3._ import chisel3.util._ import consts._ /---------------------------------------------------------------------------- \| Computes a division or square root for floating-point in recoded form. \| Multiple clock cycles are needed for each division or square-root operation, \| except possibly in special cases. ----------------------------------------------------------------------------/ class DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int) extends Module { override def desiredName = s"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { /-------------------------------------------------------------------- --------------------------------------------------------------------/ val inReady = Output(Bool()) val inValid = Input(Bool()) val sqrtOp = Input(Bool()) val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val roundingMode = Input(UInt(3.W)) /-------------------------------------------------------------------- --------------------------------------------------------------------/ val rawOutValid_div = Output(Bool()) val rawOutValid_sqrt = Output(Bool()) val roundingModeOut = Output(UInt(3.W)) val invalidExc = Output(Bool()) val infiniteExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W)) val inReady = RegInit(true.B) // <-> (cycleNum <= 1) val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1) val sqrtOp_Z = Reg(Bool()) val majorExc_Z = Reg(Bool()) //*** REDUCE 3 BITS TO 2-BIT CODE: val isNaN_Z = Reg(Bool()) val isInf_Z = Reg(Bool()) val isZero_Z = Reg(Bool()) val sign_Z = Reg(Bool()) val sExp_Z = Reg(SInt((expWidth + 2).W)) val fractB_Z = Reg(UInt(sigWidth.W)) val roundingMode_Z = Reg(UInt(3.W)) /------------------------------------------------------------------------ \| (The most-significant and least-significant bits of 'rem_Z' are needed \| only for square roots.) ------------------------------------------------------------------------/ val rem_Z = Reg(UInt((sigWidth + 2).W)) val notZeroRem_Z = Reg(Bool()) val sigX_Z = Reg(UInt((sigWidth + 2).W)) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val rawA_S = io.a val rawB_S = io.b //* IMPROVE THESE: val notSigNaNIn_invalidExc_S_div = (rawA_S.isZero && rawB_S.isZero) \|\| (rawA_S.isInf && rawB_S.isInf) val notSigNaNIn_invalidExc_S_sqrt = ! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign val majorExc_S = Mux(io.sqrtOp, isSigNaNRawFloat(rawA_S) \|\| notSigNaNIn_invalidExc_S_sqrt, isSigNaNRawFloat(rawA_S) \|\| isSigNaNRawFloat(rawB_S) \|\| notSigNaNIn_invalidExc_S_div \|\| (! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero) ) val isNaN_S = Mux(io.sqrtOp, rawA_S.isNaN \|\| notSigNaNIn_invalidExc_S_sqrt, rawA_S.isNaN \|\| rawB_S.isNaN \|\| notSigNaNIn_invalidExc_S_div ) val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf \|\| rawB_S.isZero) val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero \|\| rawB_S.isInf) val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign) val specialCaseA_S = rawA_S.isNaN \|\| rawA_S.isInf \|\| rawA_S.isZero val specialCaseB_S = rawB_S.isNaN \|\| rawB_S.isInf \|\| rawB_S.isZero val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) val sExpQuot_S_div = rawA_S.sExp +& Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt //* IS THIS OPTIMAL?: val sSatExpQuot_S_div = Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div), 6.U, sExpQuot_S_div(expWidth + 1, expWidth - 2) ), sExpQuot_S_div(expWidth - 3, 0) ).asSInt val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0) val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val idle = cycleNum === 0.U val entering = inReady && io.inValid val entering_normalCase = entering && normalCase_S val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B when (! idle \|\| entering) { def computeCycleNum(f: UInt => UInt): UInt = { Mux(entering & ! normalCase_S, f(1.U), 0.U) \| Mux(entering_normalCase, Mux(io.sqrtOp, Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)), f((sigWidth + 2).U) ), 0.U ) \| Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) \| Mux(skipCycle2, f(1.U), 0.U) } inReady := computeCycleNum(_ <= 1.U).asBool rawOutValid := computeCycleNum(_ === 1.U).asBool cycleNum := computeCycleNum(x => x) } io.inReady := inReady /------------------------------------------------------------------------ ------------------------------------------------------------------------/ when (entering) { sqrtOp_Z := io.sqrtOp majorExc_Z := majorExc_S isNaN_Z := isNaN_S isInf_Z := isInf_S isZero_Z := isZero_S sign_Z := sign_S sExp_Z := Mux(io.sqrtOp, (rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S, sSatExpQuot_S_div ) roundingMode_Z := io.roundingMode } when (entering \|\| ! inReady && sqrtOp_Z) { fractB_Z := Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) \| Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) \| Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) \| Mux(! inReady /* sqrtOp_Z / && processTwoBits, fractB_Z>>2, 0.U) \| Mux(! inReady / sqrtOp_Z / && ! processTwoBits, fractB_Z>>1, 0.U) } /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val rem = Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) \| Mux(inReady && oddSqrt_S, Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U, rawA_S.sig(sigWidth - 3, 0)<<3 ), 0.U ) \| Mux(! inReady, rem_Z<<1, 0.U) val bitMask = (1.U<<cycleNum)>>2 val trialTerm = Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) \| Mux(inReady && evenSqrt_S, (BigInt(1)<<sigWidth).U, 0.U) \| Mux(inReady && oddSqrt_S, (BigInt(5)<<(sigWidth - 1)).U, 0.U) \| Mux(! inReady, fractB_Z, 0.U) \| Mux(! inReady && ! sqrtOp_Z, 1.U << sigWidth, 0.U) \| Mux(! inReady && sqrtOp_Z, sigX_Z<<1, 0.U) val trialRem = rem.zext -& trialTerm.zext val newBit = (0.S <= trialRem) val nextRem_Z = Mux(newBit, trialRem.asUInt, rem)(sigWidth + 1, 0) val rem2 = nextRem_Z<<1 val trialTerm2_newBit0 = Mux(sqrtOp_Z, fractB_Z>>1 \| sigX_Z<<1, fractB_Z \| (1.U << sigWidth)) val trialTerm2_newBit1 = trialTerm2_newBit0 \| Mux(sqrtOp_Z, fractB_Z<<1, 0.U) val trialRem2 = Mux(newBit, (trialRem<<1) - trialTerm2_newBit1.zext, (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) val newBit2 = (0.S <= trialRem2) val nextNotZeroRem_Z = Mux(inReady \|\| newBit, trialRem =/= 0.S, notZeroRem_Z) val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z) processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) \|\| processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) \|\| !(processTwoBits && newBit2) && nextNotZeroRem_Z val nextRem_Z_2 = Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) \| Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) \| Mux(!processTwoBits, nextRem_Z, 0.U) when (entering \|\| ! inReady) { notZeroRem_Z := nextNotZeroRem_Z_2 rem_Z := nextRem_Z_2 sigX_Z := Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) \| Mux(inReady && io.sqrtOp, (BigInt(1)<<sigWidth).U, 0.U) \| Mux(inReady && oddSqrt_S, newBit<<(sigWidth - 1), 0.U) \| Mux(! inReady, sigX_Z, 0.U) \| Mux(! inReady && newBit, bitMask, 0.U) \| Mux(processTwoBits && newBit2, bitMask>>1, 0.U) } /------------------------------------------------------------------------ ------------------------------------------------------------------------/ io.rawOutValid_div := rawOutValid && ! sqrtOp_Z io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z io.roundingModeOut := roundingMode_Z io.invalidExc := majorExc_Z && isNaN_Z io.infiniteExc := majorExc_Z && ! isNaN_Z io.rawOut.isNaN := isNaN_Z io.rawOut.isInf := isInf_Z io.rawOut.isZero := isZero_Z io.rawOut.sign := sign_Z io.rawOut.sExp := sExp_Z io.rawOut.sig := sigX_Z<<1 \| notZeroRem_Z } /---------------------------------------------------------------------------- ----------------------------------------------------------------------------/ class DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int) extends Module { override def desiredName = s"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { /-------------------------------------------------------------------- --------------------------------------------------------------------/ val inReady = Output(Bool()) val inValid = Input(Bool()) val sqrtOp = Input(Bool()) val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) /-------------------------------------------------------------------- --------------------------------------------------------------------/ val rawOutValid_div = Output(Bool()) val rawOutValid_sqrt = Output(Bool()) val roundingModeOut = Output(UInt(3.W)) val invalidExc = Output(Bool()) val infiniteExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val divSqrtRawFN = Module(new DivSqrtRawFN_small(expWidth, sigWidth, options)) io.inReady := divSqrtRawFN.io.inReady divSqrtRawFN.io.inValid := io.inValid divSqrtRawFN.io.sqrtOp := io.sqrtOp divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) divSqrtRawFN.io.roundingMode := io.roundingMode io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt io.roundingModeOut := divSqrtRawFN.io.roundingModeOut io.invalidExc := divSqrtRawFN.io.invalidExc io.infiniteExc := divSqrtRawFN.io.infiniteExc io.rawOut := divSqrtRawFN.io.rawOut } /---------------------------------------------------------------------------- ----------------------------------------------------------------------------/ class DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int) extends Module { override def desiredName = s"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { /-------------------------------------------------------------------- --------------------------------------------------------------------/ val inReady = Output(Bool()) val inValid = Input(Bool()) val sqrtOp = Input(Bool()) val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) /-------------------------------------------------------------------- --------------------------------------------------------------------*/ val outValid_div = Output(Bool()) val outValid_sqrt = Output(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val divSqrtRecFNToRaw = Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options)) io.inReady := divSqrtRecFNToRaw.io.inReady divSqrtRecFNToRaw.io.inValid := io.inValid divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp divSqrtRecFNToRaw.io.a := io.a divSqrtRecFNToRaw.io.b := io.b divSqrtRecFNToRaw.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module DivSqrtRawFN_small_e8_s24_5( // @[DivSqrtRecFN_small.scala:199:5] input clock, // @[DivSqrtRecFN_small.scala:199:5] input reset, // @[DivSqrtRecFN_small.scala:199:5] output io_inReady, // @[DivSqrtRecFN_small.scala:203:16] input io_inValid, // @[DivSqrtRecFN_small.scala:203:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:203:16] input io_a_isNaN, // @[DivSqrtRecFN_small.scala:203:16] input io_a_isInf, // @[DivSqrtRecFN_small.scala:203:16] input io_a_isZero, // @[DivSqrtRecFN_small.scala:203:16] input io_a_sign, // @[DivSqrtRecFN_small.scala:203:16] input [9:0] io_a_sExp, // @[DivSqrtRecFN_small.scala:203:16] input [24:0] io_a_sig, // @[DivSqrtRecFN_small.scala:203:16] input io_b_isNaN, // @[DivSqrtRecFN_small.scala:203:16] input io_b_isInf, // @[DivSqrtRecFN_small.scala:203:16] input io_b_isZero, // @[DivSqrtRecFN_small.scala:203:16] input io_b_sign, // @[DivSqrtRecFN_small.scala:203:16] input [9:0] io_b_sExp, // @[DivSqrtRecFN_small.scala:203:16] input [24:0] io_b_sig, // @[DivSqrtRecFN_small.scala:203:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:203:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:203:16] output io_invalidExc, // @[DivSqrtRecFN_small.scala:203:16] output io_infiniteExc, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:203:16] output [9:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:203:16] output [26:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:203:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:199:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_isNaN_0 = io_a_isNaN; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_isInf_0 = io_a_isInf; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_isZero_0 = io_a_isZero; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_sign_0 = io_a_sign; // @[DivSqrtRecFN_small.scala:199:5] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[DivSqrtRecFN_small.scala:199:5] wire [24:0] io_a_sig_0 = io_a_sig; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_isNaN_0 = io_b_isNaN; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_isInf_0 = io_b_isInf; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_isZero_0 = io_b_isZero; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_sign_0 = io_b_sign; // @[DivSqrtRecFN_small.scala:199:5] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[DivSqrtRecFN_small.scala:199:5] wire [24:0] io_b_sig_0 = io_b_sig; // @[DivSqrtRecFN_small.scala:199:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:199:5] wire [1:0] _inReady_T_15 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61] wire [1:0] _rawOutValid_T_15 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61] wire [1:0] _cycleNum_T_11 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61] wire [21:0] _fractB_Z_T_19 = 22'h0; // @[DivSqrtRecFN_small.scala:345:16] wire [24:0] _trialTerm_T_16 = 25'h1000000; // @[DivSqrtRecFN_small.scala:366:42] wire [24:0] _trialTerm2_newBit0_T_3 = 25'h1000000; // @[DivSqrtRecFN_small.scala:373:85] wire [25:0] _nextRem_Z_2_T_3 = 26'h0; // @[DivSqrtRecFN_small.scala:386:12] wire [25:0] _nextRem_Z_2_T_7 = 26'h0; // @[DivSqrtRecFN_small.scala:387:12] wire [25:0] _nextRem_Z_2_T_8 = 26'h0; // @[DivSqrtRecFN_small.scala:386:81] wire _inReady_T_2 = 1'h1; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:317:38] wire _rawOutValid_T_2 = 1'h1; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:318:42] wire _fractB_Z_T_22 = 1'h1; // @[DivSqrtRecFN_small.scala:346:45] wire _nextNotZeroRem_Z_2_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:384:9] wire _nextRem_Z_2_T_9 = 1'h1; // @[DivSqrtRecFN_small.scala:388:13] wire processTwoBits = 1'h0; // @[DivSqrtRecFN_small.scala:300:42] wire _inReady_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_6 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:308:24] wire _inReady_T_8 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:307:20] wire _inReady_T_10 = 1'h0; // @[DivSqrtRecFN_small.scala:306:16] wire _rawOutValid_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_6 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:308:24] wire _rawOutValid_T_8 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:307:20] wire _rawOutValid_T_10 = 1'h0; // @[DivSqrtRecFN_small.scala:306:16] wire _fractB_Z_T_17 = 1'h0; // @[DivSqrtRecFN_small.scala:345:42] wire _nextNotZeroRem_Z_2_T = 1'h0; // @[DivSqrtRecFN_small.scala:382:24] wire _nextNotZeroRem_Z_2_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:382:34] wire _nextNotZeroRem_Z_2_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:383:24] wire _nextNotZeroRem_Z_2_T_18 = 1'h0; // @[DivSqrtRecFN_small.scala:383:35] wire _nextNotZeroRem_Z_2_T_19 = 1'h0; // @[DivSqrtRecFN_small.scala:382:85] wire _nextNotZeroRem_Z_2_T_20 = 1'h0; // @[DivSqrtRecFN_small.scala:384:26] wire _nextRem_Z_2_T = 1'h0; // @[DivSqrtRecFN_small.scala:386:28] wire _nextRem_Z_2_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:387:28] wire _sigX_Z_T_18 = 1'h0; // @[DivSqrtRecFN_small.scala:399:32] wire [28:0] _sigX_Z_T_20 = 29'h0; // @[DivSqrtRecFN_small.scala:399:16] wire _io_rawOutValid_div_T_1; // @[DivSqrtRecFN_small.scala:404:40] wire _io_rawOutValid_sqrt_T; // @[DivSqrtRecFN_small.scala:405:40] wire _io_invalidExc_T; // @[DivSqrtRecFN_small.scala:407:36] wire _io_infiniteExc_T_1; // @[DivSqrtRecFN_small.scala:408:36] wire [26:0] _io_rawOut_sig_T_1; // @[DivSqrtRecFN_small.scala:414:35] wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:199:5] wire [9:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:199:5] wire [26:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:199:5] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:199:5] reg [4:0] cycleNum; // @[DivSqrtRecFN_small.scala:224:33] reg inReady; // @[DivSqrtRecFN_small.scala:225:33] assign io_inReady_0 = inReady; // @[DivSqrtRecFN_small.scala:199:5, :225:33] reg rawOutValid; // @[DivSqrtRecFN_small.scala:226:33] reg sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29] reg majorExc_Z; // @[DivSqrtRecFN_small.scala:229:29] reg isNaN_Z; // @[DivSqrtRecFN_small.scala:231:29] assign io_rawOut_isNaN_0 = isNaN_Z; // @[DivSqrtRecFN_small.scala:199:5, :231:29] reg isInf_Z; // @[DivSqrtRecFN_small.scala:232:29] assign io_rawOut_isInf_0 = isInf_Z; // @[DivSqrtRecFN_small.scala:199:5, :232:29] reg isZero_Z; // @[DivSqrtRecFN_small.scala:233:29] assign io_rawOut_isZero_0 = isZero_Z; // @[DivSqrtRecFN_small.scala:199:5, :233:29] reg sign_Z; // @[DivSqrtRecFN_small.scala:234:29] assign io_rawOut_sign_0 = sign_Z; // @[DivSqrtRecFN_small.scala:199:5, :234:29] reg [9:0] sExp_Z; // @[DivSqrtRecFN_small.scala:235:29] assign io_rawOut_sExp_0 = sExp_Z; // @[DivSqrtRecFN_small.scala:199:5, :235:29] reg [23:0] fractB_Z; // @[DivSqrtRecFN_small.scala:236:29] reg [2:0] roundingMode_Z; // @[DivSqrtRecFN_small.scala:237:29] assign io_roundingModeOut_0 = roundingMode_Z; // @[DivSqrtRecFN_small.scala:199:5, :237:29] reg [25:0] rem_Z; // @[DivSqrtRecFN_small.scala:243:29] reg notZeroRem_Z; // @[DivSqrtRecFN_small.scala:244:29] reg [25:0] sigX_Z; // @[DivSqrtRecFN_small.scala:245:29] wire _notSigNaNIn_invalidExc_S_div_T = io_a_isZero_0 & io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :254:24] wire _notSigNaNIn_invalidExc_S_div_T_1 = io_a_isInf_0 & io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :254:59] wire notSigNaNIn_invalidExc_S_div = _notSigNaNIn_invalidExc_S_div_T \| _notSigNaNIn_invalidExc_S_div_T_1; // @[DivSqrtRecFN_small.scala:254:{24,42,59}] wire _notSigNaNIn_invalidExc_S_sqrt_T = ~io_a_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :256:9] wire _notSigNaNIn_invalidExc_S_sqrt_T_1 = ~io_a_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :256:27] wire _notSigNaNIn_invalidExc_S_sqrt_T_2 = _notSigNaNIn_invalidExc_S_sqrt_T & _notSigNaNIn_invalidExc_S_sqrt_T_1; // @[DivSqrtRecFN_small.scala:256:{9,24,27}] wire notSigNaNIn_invalidExc_S_sqrt = _notSigNaNIn_invalidExc_S_sqrt_T_2 & io_a_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :256:{24,43}] wire _majorExc_S_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _majorExc_S_T_4 = io_a_sig_0[22]; // @[common.scala:82:56] wire _majorExc_S_T_1 = ~_majorExc_S_T; // @[common.scala:82:{49,56}] wire _majorExc_S_T_2 = io_a_isNaN_0 & _majorExc_S_T_1; // @[common.scala:82:{46,49}] wire _majorExc_S_T_3 = _majorExc_S_T_2 \| notSigNaNIn_invalidExc_S_sqrt; // @[common.scala:82:46] wire _majorExc_S_T_5 = ~_majorExc_S_T_4; // @[common.scala:82:{49,56}] wire _majorExc_S_T_6 = io_a_isNaN_0 & _majorExc_S_T_5; // @[common.scala:82:{46,49}] wire _majorExc_S_T_7 = io_b_sig_0[22]; // @[common.scala:82:56] wire _majorExc_S_T_8 = ~_majorExc_S_T_7; // @[common.scala:82:{49,56}] wire _majorExc_S_T_9 = io_b_isNaN_0 & _majorExc_S_T_8; // @[common.scala:82:{46,49}] wire _majorExc_S_T_10 = _majorExc_S_T_6 \| _majorExc_S_T_9; // @[common.scala:82:46] wire _majorExc_S_T_11 = _majorExc_S_T_10 \| notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecFN_small.scala:254:42, :260:{38,66}] wire _majorExc_S_T_12 = ~io_a_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :256:9, :262:18] wire _majorExc_S_T_13 = ~io_a_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :262:36] wire _majorExc_S_T_14 = _majorExc_S_T_12 & _majorExc_S_T_13; // @[DivSqrtRecFN_small.scala:262:{18,33,36}] wire _majorExc_S_T_15 = _majorExc_S_T_14 & io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :262:{33,51}] wire _majorExc_S_T_16 = _majorExc_S_T_11 \| _majorExc_S_T_15; // @[DivSqrtRecFN_small.scala:260:66, :261:46, :262:51] wire majorExc_S = io_sqrtOp_0 ? _majorExc_S_T_3 : _majorExc_S_T_16; // @[DivSqrtRecFN_small.scala:199:5, :258:12, :259:38, :261:46] wire _isNaN_S_T = io_a_isNaN_0 \| notSigNaNIn_invalidExc_S_sqrt; // @[DivSqrtRecFN_small.scala:199:5, :256:43, :266:26] wire _isNaN_S_T_1 = io_a_isNaN_0 \| io_b_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :267:26] wire _isNaN_S_T_2 = _isNaN_S_T_1 \| notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecFN_small.scala:254:42, :267:{26,42}] wire isNaN_S = io_sqrtOp_0 ? _isNaN_S_T : _isNaN_S_T_2; // @[DivSqrtRecFN_small.scala:199:5, :265:12, :266:26, :267:42] wire _isInf_S_T = io_a_isInf_0 \| io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :269:63] wire isInf_S = io_sqrtOp_0 ? io_a_isInf_0 : _isInf_S_T; // @[DivSqrtRecFN_small.scala:199:5, :269:{23,63}] wire _isZero_S_T = io_a_isZero_0 \| io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :270:64] wire isZero_S = io_sqrtOp_0 ? io_a_isZero_0 : _isZero_S_T; // @[DivSqrtRecFN_small.scala:199:5, :270:{23,64}] wire _sign_S_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33] wire _sign_S_T_1 = _sign_S_T & io_b_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :271:{33,45}] wire sign_S = io_a_sign_0 ^ _sign_S_T_1; // @[DivSqrtRecFN_small.scala:199:5, :271:{30,45}] wire _specialCaseA_S_T = io_a_isNaN_0 \| io_a_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :273:39] wire specialCaseA_S = _specialCaseA_S_T \| io_a_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :273:{39,55}] wire _specialCaseB_S_T = io_b_isNaN_0 \| io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :274:39] wire specialCaseB_S = _specialCaseB_S_T \| io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :274:{39,55}] wire _normalCase_S_div_T = ~specialCaseA_S; // @[DivSqrtRecFN_small.scala:273:55, :275:28] wire _normalCase_S_div_T_1 = ~specialCaseB_S; // @[DivSqrtRecFN_small.scala:274:55, :275:48] wire normalCase_S_div = _normalCase_S_div_T & _normalCase_S_div_T_1; // @[DivSqrtRecFN_small.scala:275:{28,45,48}] wire _normalCase_S_sqrt_T = ~specialCaseA_S; // @[DivSqrtRecFN_small.scala:273:55, :275:28, :276:29] wire _normalCase_S_sqrt_T_1 = ~io_a_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :276:49] wire normalCase_S_sqrt = _normalCase_S_sqrt_T & _normalCase_S_sqrt_T_1; // @[DivSqrtRecFN_small.scala:276:{29,46,49}] wire normalCase_S = io_sqrtOp_0 ? normalCase_S_sqrt : normalCase_S_div; // @[DivSqrtRecFN_small.scala:199:5, :275:45, :276:46, :277:27] wire _sExpQuot_S_div_T = io_b_sExp_0[8]; // @[DivSqrtRecFN_small.scala:199:5, :281:28] wire [7:0] _sExpQuot_S_div_T_1 = io_b_sExp_0[7:0]; // @[DivSqrtRecFN_small.scala:199:5, :281:52] wire [7:0] _sExpQuot_S_div_T_2 = ~_sExpQuot_S_div_T_1; // @[DivSqrtRecFN_small.scala:281:{40,52}] wire [8:0] _sExpQuot_S_div_T_3 = {_sExpQuot_S_div_T, _sExpQuot_S_div_T_2}; // @[DivSqrtRecFN_small.scala:281:{16,28,40}] wire [8:0] _sExpQuot_S_div_T_4 = _sExpQuot_S_div_T_3; // @[DivSqrtRecFN_small.scala:281:{16,71}] wire [10:0] sExpQuot_S_div = {io_a_sExp_0[9], io_a_sExp_0} + {{2{_sExpQuot_S_div_T_4[8]}}, _sExpQuot_S_div_T_4}; // @[DivSqrtRecFN_small.scala:199:5, :280:21, :281:71] wire _sSatExpQuot_S_div_T = $signed(sExpQuot_S_div) > 11'sh1BF; // @[DivSqrtRecFN_small.scala:280:21, :284:48] wire [3:0] _sSatExpQuot_S_div_T_1 = sExpQuot_S_div[9:6]; // @[DivSqrtRecFN_small.scala:280:21, :286:31] wire [3:0] _sSatExpQuot_S_div_T_2 = _sSatExpQuot_S_div_T ? 4'h6 : _sSatExpQuot_S_div_T_1; // @[DivSqrtRecFN_small.scala:284:{16,48}, :286:31] wire [5:0] _sSatExpQuot_S_div_T_3 = sExpQuot_S_div[5:0]; // @[DivSqrtRecFN_small.scala:280:21, :288:27] wire [9:0] _sSatExpQuot_S_div_T_4 = {_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3}; // @[DivSqrtRecFN_small.scala:284:{12,16}, :288:27] wire [9:0] sSatExpQuot_S_div = _sSatExpQuot_S_div_T_4; // @[DivSqrtRecFN_small.scala:284:12, :289:11] wire _evenSqrt_S_T = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48] wire _oddSqrt_S_T = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :292:48] wire _inReady_T_4 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36] wire _rawOutValid_T_4 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36] wire _cycleNum_T_3 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36] wire _fractB_Z_T_6 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :343:52] wire _fractB_Z_T_11 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :344:54] wire _evenSqrt_S_T_1 = ~_evenSqrt_S_T; // @[DivSqrtRecFN_small.scala:291:{35,48}] wire evenSqrt_S = io_sqrtOp_0 & _evenSqrt_S_T_1; // @[DivSqrtRecFN_small.scala:199:5, :291:{32,35}] wire oddSqrt_S = io_sqrtOp_0 & _oddSqrt_S_T; // @[DivSqrtRecFN_small.scala:199:5, :292:{32,48}] wire idle = cycleNum == 5'h0; // @[DivSqrtRecFN_small.scala:224:33, :296:25] wire entering = inReady & io_inValid_0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :297:28] wire entering_normalCase = entering & normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :297:28, :298:40] wire _processTwoBits_T = cycleNum > 5'h2; // @[DivSqrtRecFN_small.scala:224:33, :300:35] wire _skipCycle2_T = cycleNum == 5'h3; // @[DivSqrtRecFN_small.scala:224:33, :301:31] wire _skipCycle2_T_1 = sigX_Z[25]; // @[DivSqrtRecFN_small.scala:245:29, :301:48] wire _skipCycle2_T_2 = _skipCycle2_T & _skipCycle2_T_1; // @[DivSqrtRecFN_small.scala:301:{31,39,48}] wire skipCycle2 = _skipCycle2_T_2; // @[DivSqrtRecFN_small.scala:301:{39,63}] wire _inReady_T_22 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16] wire _rawOutValid_T_22 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16] wire _cycleNum_T_16 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16] wire _inReady_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28] wire _inReady_T_1 = entering & _inReady_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}] wire _inReady_T_3 = _inReady_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}] wire _inReady_T_11 = _inReady_T_3; // @[DivSqrtRecFN_small.scala:305:{16,57}] wire _inReady_T_12 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17] wire _inReady_T_13 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31] wire _inReady_T_14 = _inReady_T_12 & _inReady_T_13; // @[DivSqrtRecFN_small.scala:313:{17,28,31}] wire [5:0] _GEN = {1'h0, cycleNum} - 6'h1; // @[DivSqrtRecFN_small.scala:224:33, :313:56] wire [5:0] _inReady_T_16; // @[DivSqrtRecFN_small.scala:313:56] assign _inReady_T_16 = _GEN; // @[DivSqrtRecFN_small.scala:313:56] wire [5:0] _rawOutValid_T_16; // @[DivSqrtRecFN_small.scala:313:56] assign _rawOutValid_T_16 = _GEN; // @[DivSqrtRecFN_small.scala:313:56] wire [5:0] _cycleNum_T_12; // @[DivSqrtRecFN_small.scala:313:56] assign _cycleNum_T_12 = _GEN; // @[DivSqrtRecFN_small.scala:313:56] wire [4:0] _inReady_T_17 = _inReady_T_16[4:0]; // @[DivSqrtRecFN_small.scala:313:56] wire _inReady_T_18 = _inReady_T_17 < 5'h2; // @[DivSqrtRecFN_small.scala:313:56, :317:38] wire _inReady_T_19 = _inReady_T_14 & _inReady_T_18; // @[DivSqrtRecFN_small.scala:313:{16,28}, :317:38] wire _inReady_T_20 = _inReady_T_11 \| _inReady_T_19; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16] wire _inReady_T_23 = _inReady_T_20 \| _inReady_T_22; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16] wire _inReady_T_24 = _inReady_T_23; // @[DivSqrtRecFN_small.scala:313:95, :317:46] wire _rawOutValid_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28] wire _rawOutValid_T_1 = entering & _rawOutValid_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}] wire _rawOutValid_T_3 = _rawOutValid_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}] wire _rawOutValid_T_11 = _rawOutValid_T_3; // @[DivSqrtRecFN_small.scala:305:{16,57}] wire _rawOutValid_T_12 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17] wire _rawOutValid_T_13 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31] wire _rawOutValid_T_14 = _rawOutValid_T_12 & _rawOutValid_T_13; // @[DivSqrtRecFN_small.scala:313:{17,28,31}] wire [4:0] _rawOutValid_T_17 = _rawOutValid_T_16[4:0]; // @[DivSqrtRecFN_small.scala:313:56] wire _rawOutValid_T_18 = _rawOutValid_T_17 == 5'h1; // @[DivSqrtRecFN_small.scala:313:56, :318:42] wire _rawOutValid_T_19 = _rawOutValid_T_14 & _rawOutValid_T_18; // @[DivSqrtRecFN_small.scala:313:{16,28}, :318:42] wire _rawOutValid_T_20 = _rawOutValid_T_11 \| _rawOutValid_T_19; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16] wire _rawOutValid_T_23 = _rawOutValid_T_20 \| _rawOutValid_T_22; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16] wire _rawOutValid_T_24 = _rawOutValid_T_23; // @[DivSqrtRecFN_small.scala:313:95, :318:51] wire _cycleNum_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28] wire _cycleNum_T_1 = entering & _cycleNum_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}] wire _cycleNum_T_2 = _cycleNum_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}] wire [4:0] _cycleNum_T_4 = {4'hC, ~_cycleNum_T_3}; // @[DivSqrtRecFN_small.scala:308:{24,36}] wire [4:0] _cycleNum_T_5 = io_sqrtOp_0 ? _cycleNum_T_4 : 5'h1A; // @[DivSqrtRecFN_small.scala:199:5, :307:20, :308:24] wire [4:0] _cycleNum_T_6 = entering_normalCase ? _cycleNum_T_5 : 5'h0; // @[DivSqrtRecFN_small.scala:298:40, :306:16, :307:20] wire [4:0] _cycleNum_T_7 = {4'h0, _cycleNum_T_2} \| _cycleNum_T_6; // @[DivSqrtRecFN_small.scala:305:{16,57}, :306:16, :313:56] wire _cycleNum_T_8 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17] wire _cycleNum_T_9 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31] wire _cycleNum_T_10 = _cycleNum_T_8 & _cycleNum_T_9; // @[DivSqrtRecFN_small.scala:313:{17,28,31}] wire [4:0] _cycleNum_T_13 = _cycleNum_T_12[4:0]; // @[DivSqrtRecFN_small.scala:313:56] wire [4:0] _cycleNum_T_14 = _cycleNum_T_10 ? _cycleNum_T_13 : 5'h0; // @[DivSqrtRecFN_small.scala:313:{16,28,56}] wire [4:0] _cycleNum_T_15 = _cycleNum_T_7 \| _cycleNum_T_14; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16] wire [4:0] _cycleNum_T_17 = {_cycleNum_T_15[4:1], _cycleNum_T_15[0] \| _cycleNum_T_16}; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16] wire [8:0] _sExp_Z_T = io_a_sExp_0[9:1]; // @[DivSqrtRecFN_small.scala:199:5, :335:29] wire [9:0] _sExp_Z_T_1 = {_sExp_Z_T[8], _sExp_Z_T} + 10'h80; // @[DivSqrtRecFN_small.scala:335:{29,34}] wire [9:0] _sExp_Z_T_2 = io_sqrtOp_0 ? _sExp_Z_T_1 : sSatExpQuot_S_div; // @[DivSqrtRecFN_small.scala:199:5, :289:11, :334:16, :335:34] wire _fractB_Z_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :342:28] wire _fractB_Z_T_1 = inReady & _fractB_Z_T; // @[DivSqrtRecFN_small.scala:225:33, :342:{25,28}] wire [22:0] _fractB_Z_T_2 = io_b_sig_0[22:0]; // @[DivSqrtRecFN_small.scala:199:5, :342:73] wire [23:0] _fractB_Z_T_3 = {_fractB_Z_T_2, 1'h0}; // @[DivSqrtRecFN_small.scala:342:{73,90}] wire [23:0] _fractB_Z_T_4 = _fractB_Z_T_1 ? _fractB_Z_T_3 : 24'h0; // @[DivSqrtRecFN_small.scala:342:{16,25,90}] wire _GEN_0 = inReady & io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :343:25] wire _fractB_Z_T_5; // @[DivSqrtRecFN_small.scala:343:25] assign _fractB_Z_T_5 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25] wire _fractB_Z_T_10; // @[DivSqrtRecFN_small.scala:344:25] assign _fractB_Z_T_10 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25, :344:25] wire _sigX_Z_T_4; // @[DivSqrtRecFN_small.scala:395:25] assign _sigX_Z_T_4 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25, :395:25] wire _fractB_Z_T_7 = _fractB_Z_T_5 & _fractB_Z_T_6; // @[DivSqrtRecFN_small.scala:343:{25,38,52}] wire [22:0] _fractB_Z_T_8 = {_fractB_Z_T_7, 22'h0}; // @[DivSqrtRecFN_small.scala:343:{16,38}] wire [23:0] _fractB_Z_T_9 = {_fractB_Z_T_4[23], _fractB_Z_T_4[22:0] \| _fractB_Z_T_8}; // @[DivSqrtRecFN_small.scala:342:{16,100}, :343:16] wire _fractB_Z_T_12 = ~_fractB_Z_T_11; // @[DivSqrtRecFN_small.scala:344:{41,54}] wire _fractB_Z_T_13 = _fractB_Z_T_10 & _fractB_Z_T_12; // @[DivSqrtRecFN_small.scala:344:{25,38,41}] wire [23:0] _fractB_Z_T_14 = {_fractB_Z_T_13, 23'h0}; // @[DivSqrtRecFN_small.scala:344:{16,38}] wire [23:0] _fractB_Z_T_15 = _fractB_Z_T_9 \| _fractB_Z_T_14; // @[DivSqrtRecFN_small.scala:342:100, :343:100, :344:16] wire [23:0] _fractB_Z_T_20 = _fractB_Z_T_15; // @[DivSqrtRecFN_small.scala:343:100, :344:100] wire _fractB_Z_T_16 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :345:17] wire [21:0] _fractB_Z_T_18 = fractB_Z[23:2]; // @[DivSqrtRecFN_small.scala:236:29, :345:71] wire _fractB_Z_T_21 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :346:17] wire _fractB_Z_T_23 = _fractB_Z_T_21; // @[DivSqrtRecFN_small.scala:346:{17,42}] wire [22:0] _fractB_Z_T_24 = fractB_Z[23:1]; // @[DivSqrtRecFN_small.scala:236:29, :346:71] wire [22:0] _trialTerm2_newBit0_T = fractB_Z[23:1]; // @[DivSqrtRecFN_small.scala:236:29, :346:71, :373:52] wire [22:0] _fractB_Z_T_25 = _fractB_Z_T_23 ? _fractB_Z_T_24 : 23'h0; // @[DivSqrtRecFN_small.scala:346:{16,42,71}] wire [23:0] _fractB_Z_T_26 = {_fractB_Z_T_20[23], _fractB_Z_T_20[22:0] \| _fractB_Z_T_25}; // @[DivSqrtRecFN_small.scala:344:100, :345:100, :346:16] wire _rem_T = ~oddSqrt_S; // @[DivSqrtRecFN_small.scala:292:32, :352:24] wire _rem_T_1 = inReady & _rem_T; // @[DivSqrtRecFN_small.scala:225:33, :352:{21,24}] wire [25:0] _rem_T_2 = {io_a_sig_0, 1'h0}; // @[DivSqrtRecFN_small.scala:199:5, :352:47] wire [25:0] _rem_T_3 = _rem_T_1 ? _rem_T_2 : 26'h0; // @[DivSqrtRecFN_small.scala:352:{12,21,47}] wire _GEN_1 = inReady & oddSqrt_S; // @[DivSqrtRecFN_small.scala:225:33, :292:32, :353:21] wire _rem_T_4; // @[DivSqrtRecFN_small.scala:353:21] assign _rem_T_4 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21] wire _trialTerm_T_7; // @[DivSqrtRecFN_small.scala:364:21] assign _trialTerm_T_7 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21, :364:21] wire _sigX_Z_T_7; // @[DivSqrtRecFN_small.scala:396:25] assign _sigX_Z_T_7 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21, :396:25] wire [1:0] _rem_T_5 = io_a_sig_0[23:22]; // @[DivSqrtRecFN_small.scala:199:5, :354:27] wire [2:0] _rem_T_6 = {1'h0, _rem_T_5} - 3'h1; // @[DivSqrtRecFN_small.scala:354:{27,56}] wire [1:0] _rem_T_7 = _rem_T_6[1:0]; // @[DivSqrtRecFN_small.scala:354:56] wire [21:0] _rem_T_8 = io_a_sig_0[21:0]; // @[DivSqrtRecFN_small.scala:199:5, :355:27] wire [24:0] _rem_T_9 = {_rem_T_8, 3'h0}; // @[DivSqrtRecFN_small.scala:300:35, :355:{27,44}] wire [26:0] _rem_T_10 = {_rem_T_7, _rem_T_9}; // @[DivSqrtRecFN_small.scala:354:{16,56}, :355:44] wire [26:0] _rem_T_11 = _rem_T_4 ? _rem_T_10 : 27'h0; // @[DivSqrtRecFN_small.scala:353:{12,21}, :354:16] wire [26:0] _rem_T_12 = {1'h0, _rem_T_3} \| _rem_T_11; // @[DivSqrtRecFN_small.scala:352:{12,57}, :353:12] wire _rem_T_13 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :359:13] wire [26:0] _rem_T_14 = {rem_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:243:29, :359:29] wire [26:0] _rem_T_15 = _rem_T_13 ? _rem_T_14 : 27'h0; // @[DivSqrtRecFN_small.scala:359:{12,13,29}] wire [26:0] rem = _rem_T_12 \| _rem_T_15; // @[DivSqrtRecFN_small.scala:352:57, :358:11, :359:12] wire [31:0] _bitMask_T = 32'h1 << cycleNum; // @[DivSqrtRecFN_small.scala:224:33, :360:23] wire [29:0] bitMask = _bitMask_T[31:2]; // @[DivSqrtRecFN_small.scala:360:{23,34}] wire _trialTerm_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :362:24] wire _trialTerm_T_1 = inReady & _trialTerm_T; // @[DivSqrtRecFN_small.scala:225:33, :362:{21,24}] wire [25:0] _trialTerm_T_2 = {io_b_sig_0, 1'h0}; // @[DivSqrtRecFN_small.scala:199:5, :362:48] wire [25:0] _trialTerm_T_3 = _trialTerm_T_1 ? _trialTerm_T_2 : 26'h0; // @[DivSqrtRecFN_small.scala:362:{12,21,48}] wire _trialTerm_T_4 = inReady & evenSqrt_S; // @[DivSqrtRecFN_small.scala:225:33, :291:32, :363:21] wire [24:0] _trialTerm_T_5 = {_trialTerm_T_4, 24'h0}; // @[DivSqrtRecFN_small.scala:363:{12,21}] wire [25:0] _trialTerm_T_6 = {_trialTerm_T_3[25], _trialTerm_T_3[24:0] \| _trialTerm_T_5}; // @[DivSqrtRecFN_small.scala:362:{12,74}, :363:12] wire [25:0] _trialTerm_T_8 = _trialTerm_T_7 ? 26'h2800000 : 26'h0; // @[DivSqrtRecFN_small.scala:364:{12,21}] wire [25:0] _trialTerm_T_9 = _trialTerm_T_6 \| _trialTerm_T_8; // @[DivSqrtRecFN_small.scala:362:74, :363:74, :364:12] wire _trialTerm_T_10 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :365:13] wire [23:0] _trialTerm_T_11 = _trialTerm_T_10 ? fractB_Z : 24'h0; // @[DivSqrtRecFN_small.scala:236:29, :365:{12,13}] wire [25:0] _trialTerm_T_12 = {_trialTerm_T_9[25:24], _trialTerm_T_9[23:0] \| _trialTerm_T_11}; // @[DivSqrtRecFN_small.scala:363:74, :364:74, :365:12] wire _trialTerm_T_13 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :366:13] wire _trialTerm_T_14 = ~sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :366:26] wire _trialTerm_T_15 = _trialTerm_T_13 & _trialTerm_T_14; // @[DivSqrtRecFN_small.scala:366:{13,23,26}] wire [24:0] _trialTerm_T_17 = {_trialTerm_T_15, 24'h0}; // @[DivSqrtRecFN_small.scala:366:{12,23}] wire [25:0] _trialTerm_T_18 = {_trialTerm_T_12[25], _trialTerm_T_12[24:0] \| _trialTerm_T_17}; // @[DivSqrtRecFN_small.scala:364:74, :365:74, :366:12] wire _trialTerm_T_19 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :367:13] wire _trialTerm_T_20 = _trialTerm_T_19 & sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :367:{13,23}] wire [26:0] _GEN_2 = {sigX_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:245:29, :367:44] wire [26:0] _trialTerm_T_21; // @[DivSqrtRecFN_small.scala:367:44] assign _trialTerm_T_21 = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44] wire [26:0] _trialTerm2_newBit0_T_1; // @[DivSqrtRecFN_small.scala:373:64] assign _trialTerm2_newBit0_T_1 = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44, :373:64] wire [26:0] _io_rawOut_sig_T; // @[DivSqrtRecFN_small.scala:414:31] assign _io_rawOut_sig_T = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44, :414:31] wire [26:0] _trialTerm_T_22 = _trialTerm_T_20 ? _trialTerm_T_21 : 27'h0; // @[DivSqrtRecFN_small.scala:367:{12,23,44}] wire [26:0] trialTerm = {1'h0, _trialTerm_T_18} \| _trialTerm_T_22; // @[DivSqrtRecFN_small.scala:365:74, :366:74, :367:12] wire [27:0] _trialRem_T = {1'h0, rem}; // @[DivSqrtRecFN_small.scala:358:11, :368:24] wire [27:0] _trialRem_T_1 = {1'h0, trialTerm}; // @[DivSqrtRecFN_small.scala:366:74, :368:42] wire [28:0] trialRem = {_trialRem_T[27], _trialRem_T} - {_trialRem_T_1[27], _trialRem_T_1}; // @[DivSqrtRecFN_small.scala:368:{24,29,42}] wire [28:0] _nextRem_Z_T = trialRem; // @[DivSqrtRecFN_small.scala:368:29, :371:42] wire newBit = $signed(trialRem) > -29'sh1; // @[DivSqrtRecFN_small.scala:368:29, :369:23] wire [28:0] _nextRem_Z_T_1 = newBit ? _nextRem_Z_T : {2'h0, rem}; // @[DivSqrtRecFN_small.scala:354:56, :358:11, :369:23, :371:{24,42}] wire [25:0] nextRem_Z = _nextRem_Z_T_1[25:0]; // @[DivSqrtRecFN_small.scala:371:{24,54}] wire [25:0] _nextRem_Z_2_T_10 = nextRem_Z; // @[DivSqrtRecFN_small.scala:371:54, :388:12] wire [26:0] rem2 = {nextRem_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:371:54, :372:25] wire [26:0] _trialTerm2_newBit0_T_2 = {4'h0, _trialTerm2_newBit0_T} \| _trialTerm2_newBit0_T_1; // @[DivSqrtRecFN_small.scala:313:56, :373:{52,56,64}] wire [24:0] _trialTerm2_newBit0_T_4 = {1'h1, fractB_Z}; // @[DivSqrtRecFN_small.scala:236:29, :373:78] wire [26:0] trialTerm2_newBit0 = sqrtOp_Z ? _trialTerm2_newBit0_T_2 : {2'h0, _trialTerm2_newBit0_T_4}; // @[DivSqrtRecFN_small.scala:228:29, :354:56, :373:{33,56,78}] wire [24:0] _trialTerm2_newBit1_T = {fractB_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:236:29, :374:73] wire [24:0] _trialTerm2_newBit1_T_1 = sqrtOp_Z ? _trialTerm2_newBit1_T : 25'h0; // @[DivSqrtRecFN_small.scala:228:29, :374:{54,73}] wire [26:0] trialTerm2_newBit1 = {trialTerm2_newBit0[26:25], trialTerm2_newBit0[24:0] \| _trialTerm2_newBit1_T_1}; // @[DivSqrtRecFN_small.scala:373:33, :374:{49,54}] wire [29:0] _GEN_3 = {trialRem, 1'h0}; // @[DivSqrtRecFN_small.scala:368:29, :377:22] wire [29:0] _trialRem2_T; // @[DivSqrtRecFN_small.scala:377:22] assign _trialRem2_T = _GEN_3; // @[DivSqrtRecFN_small.scala:377:22] wire [29:0] _nextNotZeroRem_Z_2_T_1; // @[DivSqrtRecFN_small.scala:382:53] assign _nextNotZeroRem_Z_2_T_1 = _GEN_3; // @[DivSqrtRecFN_small.scala:377:22, :382:53] wire [27:0] _GEN_4 = {1'h0, trialTerm2_newBit1}; // @[DivSqrtRecFN_small.scala:374:49, :377:48] wire [27:0] _trialRem2_T_1; // @[DivSqrtRecFN_small.scala:377:48] assign _trialRem2_T_1 = _GEN_4; // @[DivSqrtRecFN_small.scala:377:48] wire [27:0] _nextNotZeroRem_Z_2_T_2; // @[DivSqrtRecFN_small.scala:382:79] assign _nextNotZeroRem_Z_2_T_2 = _GEN_4; // @[DivSqrtRecFN_small.scala:377:48, :382:79] wire [30:0] _trialRem2_T_2 = {_trialRem2_T[29], _trialRem2_T} - {{3{_trialRem2_T_1[27]}}, _trialRem2_T_1}; // @[DivSqrtRecFN_small.scala:377:{22,27,48}] wire [29:0] _trialRem2_T_3 = _trialRem2_T_2[29:0]; // @[DivSqrtRecFN_small.scala:377:27] wire [29:0] _trialRem2_T_4 = _trialRem2_T_3; // @[DivSqrtRecFN_small.scala:377:27] wire [27:0] _GEN_5 = {rem_Z, 2'h0}; // @[DivSqrtRecFN_small.scala:243:29, :354:56, :378:19] wire [27:0] _trialRem2_T_5; // @[DivSqrtRecFN_small.scala:378:19] assign _trialRem2_T_5 = _GEN_5; // @[DivSqrtRecFN_small.scala:378:19] wire [27:0] _nextNotZeroRem_Z_2_T_10; // @[DivSqrtRecFN_small.scala:383:51] assign _nextNotZeroRem_Z_2_T_10 = _GEN_5; // @[DivSqrtRecFN_small.scala:378:19, :383:51] wire [26:0] _trialRem2_T_6 = _trialRem2_T_5[26:0]; // @[DivSqrtRecFN_small.scala:378:{19,23}] wire [27:0] _trialRem2_T_7 = {1'h0, _trialRem2_T_6}; // @[DivSqrtRecFN_small.scala:378:{23,39}] wire [27:0] _GEN_6 = {1'h0, trialTerm2_newBit0}; // @[DivSqrtRecFN_small.scala:373:33, :378:65] wire [27:0] _trialRem2_T_8; // @[DivSqrtRecFN_small.scala:378:65] assign _trialRem2_T_8 = _GEN_6; // @[DivSqrtRecFN_small.scala:378:65] wire [27:0] _nextNotZeroRem_Z_2_T_13; // @[DivSqrtRecFN_small.scala:383:97] assign _nextNotZeroRem_Z_2_T_13 = _GEN_6; // @[DivSqrtRecFN_small.scala:378:65, :383:97] wire [28:0] _trialRem2_T_9 = {_trialRem2_T_7[27], _trialRem2_T_7} - {_trialRem2_T_8[27], _trialRem2_T_8}; // @[DivSqrtRecFN_small.scala:378:{39,44,65}] wire [27:0] _trialRem2_T_10 = _trialRem2_T_9[27:0]; // @[DivSqrtRecFN_small.scala:378:44] wire [27:0] _trialRem2_T_11 = _trialRem2_T_10; // @[DivSqrtRecFN_small.scala:378:44] wire [29:0] trialRem2 = newBit ? _trialRem2_T_4 : {{2{_trialRem2_T_11[27]}}, _trialRem2_T_11}; // @[DivSqrtRecFN_small.scala:369:23, :376:12, :377:27, :378:44] wire [29:0] _nextRem_Z_2_T_1 = trialRem2; // @[DivSqrtRecFN_small.scala:376:12, :386:51] wire newBit2 = $signed(trialRem2) > -30'sh1; // @[DivSqrtRecFN_small.scala:376:12, :379:24] wire _nextNotZeroRem_Z_T = inReady \| newBit; // @[DivSqrtRecFN_small.scala:225:33, :369:23, :380:40] wire _nextNotZeroRem_Z_T_1 = \|trialRem; // @[DivSqrtRecFN_small.scala:368:29, :380:60] wire nextNotZeroRem_Z = _nextNotZeroRem_Z_T ? _nextNotZeroRem_Z_T_1 : notZeroRem_Z; // @[DivSqrtRecFN_small.scala:244:29, :380:{31,40,60}] wire _nextNotZeroRem_Z_2_T_22 = nextNotZeroRem_Z; // @[DivSqrtRecFN_small.scala:380:31, :384:38] wire [30:0] _nextNotZeroRem_Z_2_T_3 = {_nextNotZeroRem_Z_2_T_1[29], _nextNotZeroRem_Z_2_T_1} - {{3{_nextNotZeroRem_Z_2_T_2[27]}}, _nextNotZeroRem_Z_2_T_2}; // @[DivSqrtRecFN_small.scala:382:{53,58,79}] wire [29:0] _nextNotZeroRem_Z_2_T_4 = _nextNotZeroRem_Z_2_T_3[29:0]; // @[DivSqrtRecFN_small.scala:382:58] wire [29:0] _nextNotZeroRem_Z_2_T_5 = _nextNotZeroRem_Z_2_T_4; // @[DivSqrtRecFN_small.scala:382:58] wire _nextNotZeroRem_Z_2_T_6 = $signed(_nextNotZeroRem_Z_2_T_5) > 30'sh0; // @[DivSqrtRecFN_small.scala:379:24, :382:{42,58}] wire _nextNotZeroRem_Z_2_T_8 = ~newBit; // @[DivSqrtRecFN_small.scala:369:23, :383:27] wire [26:0] _nextNotZeroRem_Z_2_T_11 = _nextNotZeroRem_Z_2_T_10[26:0]; // @[DivSqrtRecFN_small.scala:383:{51,55}] wire [27:0] _nextNotZeroRem_Z_2_T_12 = {1'h0, _nextNotZeroRem_Z_2_T_11}; // @[DivSqrtRecFN_small.scala:383:{55,71}] wire [28:0] _nextNotZeroRem_Z_2_T_14 = {_nextNotZeroRem_Z_2_T_12[27], _nextNotZeroRem_Z_2_T_12} - {_nextNotZeroRem_Z_2_T_13[27], _nextNotZeroRem_Z_2_T_13}; // @[DivSqrtRecFN_small.scala:383:{71,76,97}] wire [27:0] _nextNotZeroRem_Z_2_T_15 = _nextNotZeroRem_Z_2_T_14[27:0]; // @[DivSqrtRecFN_small.scala:383:76] wire [27:0] _nextNotZeroRem_Z_2_T_16 = _nextNotZeroRem_Z_2_T_15; // @[DivSqrtRecFN_small.scala:383:76] wire _nextNotZeroRem_Z_2_T_17 = $signed(_nextNotZeroRem_Z_2_T_16) > 28'sh0; // @[DivSqrtRecFN_small.scala:383:{43,76}] wire nextNotZeroRem_Z_2 = _nextNotZeroRem_Z_2_T_22; // @[DivSqrtRecFN_small.scala:383:103, :384:38] wire [25:0] _nextRem_Z_2_T_2 = _nextRem_Z_2_T_1[25:0]; // @[DivSqrtRecFN_small.scala:386:{51,57}] wire _nextRem_Z_2_T_4 = ~newBit2; // @[DivSqrtRecFN_small.scala:379:24, :387:31] wire [25:0] _nextRem_Z_2_T_6 = rem2[25:0]; // @[DivSqrtRecFN_small.scala:372:25, :387:45] wire [25:0] nextRem_Z_2 = _nextRem_Z_2_T_10; // @[DivSqrtRecFN_small.scala:387:83, :388:12] wire _sigX_Z_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :394:28] wire _sigX_Z_T_1 = inReady & _sigX_Z_T; // @[DivSqrtRecFN_small.scala:225:33, :394:{25,28}] wire [25:0] _sigX_Z_T_2 = {newBit, 25'h0}; // @[DivSqrtRecFN_small.scala:369:23, :394:50] wire [25:0] _sigX_Z_T_3 = _sigX_Z_T_1 ? _sigX_Z_T_2 : 26'h0; // @[DivSqrtRecFN_small.scala:394:{16,25,50}] wire [24:0] _sigX_Z_T_5 = {_sigX_Z_T_4, 24'h0}; // @[DivSqrtRecFN_small.scala:395:{16,25}] wire [25:0] _sigX_Z_T_6 = {_sigX_Z_T_3[25], _sigX_Z_T_3[24:0] \| _sigX_Z_T_5}; // @[DivSqrtRecFN_small.scala:394:{16,74}, :395:16] wire [23:0] _sigX_Z_T_8 = {newBit, 23'h0}; // @[DivSqrtRecFN_small.scala:369:23, :396:50] wire [23:0] _sigX_Z_T_9 = _sigX_Z_T_7 ? _sigX_Z_T_8 : 24'h0; // @[DivSqrtRecFN_small.scala:396:{16,25,50}] wire [25:0] _sigX_Z_T_10 = {_sigX_Z_T_6[25:24], _sigX_Z_T_6[23:0] \| _sigX_Z_T_9}; // @[DivSqrtRecFN_small.scala:394:74, :395:74, :396:16] wire _sigX_Z_T_11 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :397:17] wire [25:0] _sigX_Z_T_12 = _sigX_Z_T_11 ? sigX_Z : 26'h0; // @[DivSqrtRecFN_small.scala:245:29, :397:{16,17}] wire [25:0] _sigX_Z_T_13 = _sigX_Z_T_10 \| _sigX_Z_T_12; // @[DivSqrtRecFN_small.scala:395:74, :396:74, :397:16] wire _sigX_Z_T_14 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :398:17] wire _sigX_Z_T_15 = _sigX_Z_T_14 & newBit; // @[DivSqrtRecFN_small.scala:369:23, :398:{17,27}] wire [29:0] _sigX_Z_T_16 = _sigX_Z_T_15 ? bitMask : 30'h0; // @[DivSqrtRecFN_small.scala:360:34, :379:24, :398:{16,27}] wire [29:0] _sigX_Z_T_17 = {4'h0, _sigX_Z_T_13} \| _sigX_Z_T_16; // @[DivSqrtRecFN_small.scala:313:56, :396:74, :397:74, :398:16] wire [29:0] _sigX_Z_T_21 = _sigX_Z_T_17; // @[DivSqrtRecFN_small.scala:397:74, :398:74] wire [28:0] _sigX_Z_T_19 = bitMask[29:1]; // @[DivSqrtRecFN_small.scala:360:34, :399:51] wire _io_rawOutValid_div_T = ~sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :366:26, :404:43] assign _io_rawOutValid_div_T_1 = rawOutValid & _io_rawOutValid_div_T; // @[DivSqrtRecFN_small.scala:226:33, :404:{40,43}] assign io_rawOutValid_div_0 = _io_rawOutValid_div_T_1; // @[DivSqrtRecFN_small.scala:199:5, :404:40] assign _io_rawOutValid_sqrt_T = rawOutValid & sqrtOp_Z; // @[DivSqrtRecFN_small.scala:226:33, :228:29, :405:40] assign io_rawOutValid_sqrt_0 = _io_rawOutValid_sqrt_T; // @[DivSqrtRecFN_small.scala:199:5, :405:40] assign _io_invalidExc_T = majorExc_Z & isNaN_Z; // @[DivSqrtRecFN_small.scala:229:29, :231:29, :407:36] assign io_invalidExc_0 = _io_invalidExc_T; // @[DivSqrtRecFN_small.scala:199:5, :407:36] wire _io_infiniteExc_T = ~isNaN_Z; // @[DivSqrtRecFN_small.scala:231:29, :408:39] assign _io_infiniteExc_T_1 = majorExc_Z & _io_infiniteExc_T; // @[DivSqrtRecFN_small.scala:229:29, :408:{36,39}] assign io_infiniteExc_0 = _io_infiniteExc_T_1; // @[DivSqrtRecFN_small.scala:199:5, :408:36] assign _io_rawOut_sig_T_1 = {_io_rawOut_sig_T[26:1], _io_rawOut_sig_T[0] \| notZeroRem_Z}; // @[DivSqrtRecFN_small.scala:244:29, :414:{31,35}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_1; // @[DivSqrtRecFN_small.scala:199:5, :414:35] always @(posedge clock) begin // @[DivSqrtRecFN_small.scala:199:5] if (reset) begin // @[DivSqrtRecFN_small.scala:199:5] cycleNum <= 5'h0; // @[DivSqrtRecFN_small.scala:224:33] inReady <= 1'h1; // @[DivSqrtRecFN_small.scala:225:33] rawOutValid <= 1'h0; // @[DivSqrtRecFN_small.scala:226:33] end else if (~idle \| entering) begin // @[DivSqrtRecFN_small.scala:296:25, :297:28, :303:{11,18}] cycleNum <= _cycleNum_T_17; // @[DivSqrtRecFN_small.scala:224:33, :313:95] inReady <= _inReady_T_24; // @[DivSqrtRecFN_small.scala:225:33, :317:46] rawOutValid <= _rawOutValid_T_24; // @[DivSqrtRecFN_small.scala:226:33, :318:51] end if (entering) begin // @[DivSqrtRecFN_small.scala:297:28] sqrtOp_Z <= io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :228:29] majorExc_Z <= majorExc_S; // @[DivSqrtRecFN_small.scala:229:29, :258:12] isNaN_Z <= isNaN_S; // @[DivSqrtRecFN_small.scala:231:29, :265:12] isInf_Z <= isInf_S; // @[DivSqrtRecFN_small.scala:232:29, :269:23] isZero_Z <= isZero_S; // @[DivSqrtRecFN_small.scala:233:29, :270:23] sign_Z <= sign_S; // @[DivSqrtRecFN_small.scala:234:29, :271:30] sExp_Z <= _sExp_Z_T_2; // @[DivSqrtRecFN_small.scala:235:29, :334:16] roundingMode_Z <= io_roundingMode_0; // @[DivSqrtRecFN_small.scala:199:5, :237:29] end if (entering \| ~inReady & sqrtOp_Z) // @[DivSqrtRecFN_small.scala:225:33, :228:29, :297:28, :340:{20,23,33}] fractB_Z <= _fractB_Z_T_26; // @[DivSqrtRecFN_small.scala:236:29, :345:100] if (entering \| ~inReady) begin // @[DivSqrtRecFN_small.scala:225:33, :297:28, :340:23, :390:20] rem_Z <= nextRem_Z_2; // @[DivSqrtRecFN_small.scala:243:29, :387:83] notZeroRem_Z <= nextNotZeroRem_Z_2; // @[DivSqrtRecFN_small.scala:244:29, :383:103] sigX_Z <= _sigX_Z_T_21[25:0]; // @[DivSqrtRecFN_small.scala:245:29, :393:16, :398:74] end always @(posedge) assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:199:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_15( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [11:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [11:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [4:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [11:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25] reg [11:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [11:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 12'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_44( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_57 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid \|\| io.clear \|\| io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 \|\| rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_\|\|_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_\|\|_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready \|\| agen_ready \|\| dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }	module IssueSlot_39( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire [1:0] io_iss_uop_lrs2_rtype = 2'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0 = io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_agen; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_agen_0 = slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_agen = slot_uop_iw_issued_partial_agen; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_dgen_0 = slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_dgen = slot_uop_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_agen_0 = next_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_dgen_0 = next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //* POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //* UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //* REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero \|\| rawB.isZero \|\| (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign \|\| (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //* NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR \|\| reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN \|\| rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR \|\| CDom_reduced4SigExtra \|\| CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR \|\| notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd \|\| io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA \|\| io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny \|\| (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) \|\| (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) \|\| (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB \|\| io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros \|\| (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) \|\| (io.fromPreMul.isInfC && opSignC) \|\| (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) \|\| (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd \|\| opSignC)) \|\| (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulAddRecFNToRaw_postMul_e5_s11_6( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [6:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [3:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [12:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [22:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [6:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [13:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [6:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [3:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [12:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [22:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[MulAddRecFN.scala:169:7] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [6:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [13:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [6:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [13:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[MulAddRecFN.scala:169:7, :186:45] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[22]; // @[MulAddRecFN.scala:169:7, :192:32] wire [13:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 14'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [12:0] _sigSum_T_2 = _sigSum_T_1[12:0]; // @[MulAddRecFN.scala:193:47] wire [12:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [21:0] _sigSum_T_4 = io_mulAddResult_0[21:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [34:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [35:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [7:0] _GEN = {io_fromPreMul_sExpSum_0[6], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [7:0] _CDom_sExp_T_1 = _GEN - {{6{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [6:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[6:0]; // @[MulAddRecFN.scala:203:43] wire [6:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [23:0] _CDom_absSigSum_T = sigSum[35:12]; // @[MulAddRecFN.scala:192:12, :206:20] wire [23:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[12:11]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [20:0] _CDom_absSigSum_T_4 = sigSum[33:13]; // @[MulAddRecFN.scala:192:12, :210:23] wire [23:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [23:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [10:0] _CDom_absSigSumExtra_T = sigSum[11:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [10:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = \|_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [11:0] _CDom_absSigSumExtra_T_3 = sigSum[12:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = \|_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [38:0] _CDom_mainSig_T = {15'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [15:0] CDom_mainSig = _CDom_mainSig_T[23:8]; // @[MulAddRecFN.scala:219:{24,56}] wire [10:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[10:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [10:0] _CDom_reduced4SigExtra_T_1 = _CDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = \|_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = \|_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[10:8]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = \|_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[3:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [1:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [4:0] CDom_reduced4SigExtra_shift = $signed(5'sh10 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [1:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[2:1]; // @[primitives.scala:76:56, :78:22] wire _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[0]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_5[1]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_8 = {_CDom_reduced4SigExtra_T_6, _CDom_reduced4SigExtra_T_7}; // @[primitives.scala:77:20] wire [2:0] _CDom_reduced4SigExtra_T_9 = {1'h0, _CDom_reduced4SigExtra_T_2[1:0] & _CDom_reduced4SigExtra_T_8}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = \|_CDom_reduced4SigExtra_T_9; // @[MulAddRecFN.scala:222:72, :223:73] wire [12:0] _CDom_sig_T = CDom_mainSig[15:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = \|_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 \| CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 \| CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [13:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[25]; // @[MulAddRecFN.scala:192:12, :232:36] wire [24:0] _notCDom_absSigSum_T = sigSum[24:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [24:0] _notCDom_absSigSum_T_2 = sigSum[24:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [24:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [25:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {25'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [24:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[24:0]; // @[MulAddRecFN.scala:236:41] wire [24:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[24]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire [3:0] _notCDom_normDistReduced2_T_13 = _notCDom_normDistReduced2_T_1 ? 4'hB : 4'hC; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_14 = _notCDom_normDistReduced2_T_2 ? 4'hA : _notCDom_normDistReduced2_T_13; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_15 = _notCDom_normDistReduced2_T_3 ? 4'h9 : _notCDom_normDistReduced2_T_14; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_16 = _notCDom_normDistReduced2_T_4 ? 4'h8 : _notCDom_normDistReduced2_T_15; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_17 = _notCDom_normDistReduced2_T_5 ? 4'h7 : _notCDom_normDistReduced2_T_16; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_18 = _notCDom_normDistReduced2_T_6 ? 4'h6 : _notCDom_normDistReduced2_T_17; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_19 = _notCDom_normDistReduced2_T_7 ? 4'h5 : _notCDom_normDistReduced2_T_18; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_20 = _notCDom_normDistReduced2_T_8 ? 4'h4 : _notCDom_normDistReduced2_T_19; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_21 = _notCDom_normDistReduced2_T_9 ? 4'h3 : _notCDom_normDistReduced2_T_20; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_22 = _notCDom_normDistReduced2_T_10 ? 4'h2 : _notCDom_normDistReduced2_T_21; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_23 = _notCDom_normDistReduced2_T_11 ? 4'h1 : _notCDom_normDistReduced2_T_22; // @[Mux.scala:50:70] wire [3:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_12 ? 4'h0 : _notCDom_normDistReduced2_T_23; // @[Mux.scala:50:70] wire [4:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [5:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [7:0] _notCDom_sExp_T_1 = _GEN - {{2{_notCDom_sExp_T[5]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [6:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[6:0]; // @[MulAddRecFN.scala:241:46] wire [6:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [55:0] _notCDom_mainSig_T = {31'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [15:0] notCDom_mainSig = _notCDom_mainSig_T[25:10]; // @[MulAddRecFN.scala:243:{27,50}] wire [5:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[5:0]; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_1 = {_notCDom_reduced4SigExtra_T, 1'h0}; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[6]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = _notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_reducedVec_1, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_reducedVec_3, notCDom_reduced4SigExtra_reducedVec_2}; // @[primitives.scala:101:30, :107:20] wire [3:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [2:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[3:1]; // @[Mux.scala:50:70] wire [2:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] notCDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [2:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[3:1]; // @[primitives.scala:76:56, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[1:0]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_6[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_9 = {_notCDom_reduced4SigExtra_T_7, _notCDom_reduced4SigExtra_T_8}; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_10 = _notCDom_reduced4SigExtra_T_5[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _notCDom_reduced4SigExtra_T_11 = {_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_10}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_12 = {1'h0, _notCDom_reduced4SigExtra_T_2[2:0] & _notCDom_reduced4SigExtra_T_11}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = \|_notCDom_reduced4SigExtra_T_12; // @[MulAddRecFN.scala:247:78, :249:11] wire [12:0] _notCDom_sig_T = notCDom_mainSig[15:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = \|_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 \| notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [13:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[13:12]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = notCDom_completeCancellation ? roundingMode_min : _notCDom_sign_T; // @[MulAddRecFN.scala:186:45, :255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 \| io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd \| io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 \| io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 \| _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 \| _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 \| _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 \| io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros \| _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T \| _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_3 = ~roundingMode_min; // @[MulAddRecFN.scala:186:45, :287:29] wire _io_rawOut_sign_T_4 = notNaN_addZeros & _io_rawOut_sign_T_3; // @[MulAddRecFN.scala:267:58, :287:{26,29}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 \| _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_8 = notNaN_addZeros & roundingMode_min; // @[MulAddRecFN.scala:186:45, :267:58, :289:26] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 \| opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_10 = _io_rawOut_sign_T_8 & _io_rawOut_sign_T_9; // @[MulAddRecFN.scala:289:{26,46}, :290:37] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7 \| _io_rawOut_sign_T_10; // @[MulAddRecFN.scala:286:43, :288:48, :289:46] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 \| _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Error.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.resources.SimpleDevice import freechips.rocketchip.tilelink.{TLArbiter, TLMessages, TLPermissions} /** Adds a /dev/null slave that generates TL error response messages / class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends DevNullDevice(params, minLatency = if (buffer) 1 else 0, beatBytes, new SimpleDevice("error-device", Seq("sifive,error0"))) { lazy val module = new Impl class Impl extends LazyModuleImp(this) { import TLMessages._ import TLPermissions._ val (in, edge) = node.in(0) val a = if (buffer) {Queue(in.a, 1)} else in.a val da = Wire(chiselTypeOf(in.d)) val idle = RegInit(true.B) val a_last = edge.last(a) val (da_first, da_last, _) = edge.firstlast(da) assert (idle \|\| da_first) // we only send Grant, never GrantData => simplified flow control below a.ready := (da.ready && da_last && idle) \|\| !a_last da.valid := a.valid && a_last && idle da.bits.opcode := TLMessages.adResponse(a.bits.opcode) da.bits.param := 0.U // toT, but error grants must be handled transiently (ie: you don't keep permissions) da.bits.size := a.bits.size da.bits.source := a.bits.source da.bits.sink := 0.U da.bits.denied := true.B da.bits.data := 0.U da.bits.corrupt := edge.hasData(da.bits) if (params.acquire) { val c = if (buffer) {Queue(in.c, 1)} else in.c val dc = Wire(chiselTypeOf(in.d)) val c_last = edge.last(c) val dc_last = edge.last(dc) // Only allow one Grant in-flight at a time when (da.fire && da.bits.opcode === Grant) { idle := false.B } when (in.e.fire) { idle := true.B } c.ready := (dc.ready && dc_last) \|\| !c_last dc.valid := c.valid && c_last // ReleaseAck is not allowed to report failure dc.bits.opcode := ReleaseAck dc.bits.param := VecInit(toB, toN, toN)(c.bits.param(1,0)) dc.bits.size := c.bits.size dc.bits.source := c.bits.source dc.bits.sink := 0.U dc.bits.denied := false.B dc.bits.data := 0.U dc.bits.corrupt := false.B // Combine response channels TLArbiter.lowest(edge, in.d, dc, da) } else { in.d <> da } // We never probe or issue B requests in.b.valid := false.B // Sink GrantAcks in.e.ready := true.B } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLError( // @[Error.scala:21:9] input clock, // @[Error.scala:21:9] input reset, // @[Error.scala:21:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _a_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _a_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [3:0] _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire auto_in_a_valid_0 = auto_in_a_valid; // @[Error.scala:21:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Error.scala:21:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Error.scala:21:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Error.scala:21:9] wire [8:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Error.scala:21:9] wire [13:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Error.scala:21:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Error.scala:21:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Error.scala:21:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Error.scala:21:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Error.scala:21:9] wire [7:0][2:0] _GEN = '{3'h4, 3'h4, 3'h2, 3'h1, 3'h1, 3'h1, 3'h0, 3'h0}; wire auto_in_d_bits_denied = 1'h1; // @[Error.scala:21:9] wire nodeIn_d_bits_denied = 1'h1; // @[MixedNode.scala:551:17] wire da_bits_denied = 1'h1; // @[Error.scala:28:18] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Error.scala:21:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] da_bits_param = 2'h0; // @[Error.scala:28:18] wire auto_in_d_bits_sink = 1'h0; // @[Error.scala:21:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire da_bits_sink = 1'h0; // @[Error.scala:28:18] wire [63:0] auto_in_d_bits_data = 64'h0; // @[Error.scala:21:9] wire [63:0] nodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] da_bits_data = 64'h0; // @[Error.scala:28:18] wire [2:0] _da_bits_opcode_WIRE_6 = 3'h4; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_7 = 3'h4; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_5 = 3'h2; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_2 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_3 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_4 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_0 = 3'h0; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_1 = 3'h0; // @[Bundles.scala:47:27] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Error.scala:21:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Error.scala:21:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Error.scala:21:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Error.scala:21:9] wire [8:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Error.scala:21:9] wire [13:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Error.scala:21:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Error.scala:21:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Error.scala:21:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Error.scala:21:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Error.scala:21:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire auto_in_a_ready_0; // @[Error.scala:21:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Error.scala:21:9] wire [3:0] auto_in_d_bits_size_0; // @[Error.scala:21:9] wire [8:0] auto_in_d_bits_source_0; // @[Error.scala:21:9] wire auto_in_d_bits_corrupt_0; // @[Error.scala:21:9] wire auto_in_d_valid_0; // @[Error.scala:21:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Error.scala:21:9] wire da_ready = nodeIn_d_ready; // @[Error.scala:28:18] wire da_valid; // @[Error.scala:28:18] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Error.scala:21:9] wire [2:0] da_bits_opcode; // @[Error.scala:28:18] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Error.scala:21:9] wire [3:0] da_bits_size; // @[Error.scala:28:18] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Error.scala:21:9] wire [8:0] da_bits_source; // @[Error.scala:28:18] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Error.scala:21:9] wire da_bits_corrupt; // @[Error.scala:28:18] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Error.scala:21:9] wire _da_valid_T_1; // @[Error.scala:36:35] assign nodeIn_d_valid = da_valid; // @[Error.scala:28:18] assign nodeIn_d_bits_opcode = da_bits_opcode; // @[Error.scala:28:18] assign nodeIn_d_bits_size = da_bits_size; // @[Error.scala:28:18] assign nodeIn_d_bits_source = da_bits_source; // @[Error.scala:28:18] wire da_bits_corrupt_opdata; // @[Edges.scala:106:36] assign nodeIn_d_bits_corrupt = da_bits_corrupt; // @[Error.scala:28:18] wire _q_io_deq_ready_T_3; // @[Error.scala:35:46] wire _a_last_T = _q_io_deq_ready_T_3 & _a_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21] wire [26:0] _a_last_beats1_decode_T = 27'hFFF << _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [11:0] _a_last_beats1_decode_T_1 = _a_last_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_last_beats1_decode_T_2 = ~_a_last_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_last_beats1_decode = _a_last_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_last_beats1_opdata_T = _a_q_io_deq_bits_opcode[2]; // @[Decoupled.scala:362:21] wire a_last_beats1_opdata = ~_a_last_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_last_beats1 = a_last_beats1_opdata ? a_last_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_last_counter; // @[Edges.scala:229:27] wire [9:0] _a_last_counter1_T = {1'h0, a_last_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_last_counter1 = _a_last_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_last_first = a_last_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_last_last_T = a_last_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_last_last_T_1 = a_last_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_last = _a_last_last_T \| _a_last_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_last_done = a_last & _a_last_T; // @[Decoupled.scala:51:35] wire [8:0] _a_last_count_T = ~a_last_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_last_count = a_last_beats1 & _a_last_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_last_counter_T = a_last_first ? a_last_beats1 : a_last_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _T = da_ready & da_valid; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << da_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36] assign da_bits_corrupt_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire da_first = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire da_last = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire r_3 = da_last & _T; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = da_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _q_io_deq_ready_T = da_ready & da_last; // @[Edges.scala:232:33] wire _q_io_deq_ready_T_1 = _q_io_deq_ready_T; // @[Error.scala:35:{26,37}] wire _q_io_deq_ready_T_2 = ~a_last; // @[Edges.scala:232:33] assign _q_io_deq_ready_T_3 = _q_io_deq_ready_T_1 \| _q_io_deq_ready_T_2; // @[Error.scala:35:{37,46,49}] wire _da_valid_T = _a_q_io_deq_valid & a_last; // @[Decoupled.scala:362:21] assign _da_valid_T_1 = _da_valid_T; // @[Error.scala:36:{25,35}] assign da_valid = _da_valid_T_1; // @[Error.scala:28:18, :36:35] assign da_bits_opcode = _GEN[_a_q_io_deq_bits_opcode]; // @[Decoupled.scala:362:21] assign da_bits_corrupt = da_bits_corrupt_opdata; // @[Edges.scala:106:36] always @(posedge clock) begin // @[Error.scala:21:9] if (reset) begin // @[Error.scala:21:9] a_last_counter <= 9'h0; // @[Edges.scala:229:27] r_counter <= 9'h0; // @[Edges.scala:229:27] end else begin // @[Error.scala:21:9] if (_a_last_T) // @[Decoupled.scala:51:35] a_last_counter <= _a_last_counter_T; // @[Edges.scala:229:27, :236:21] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] end always @(posedge) TLMonitor_19 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a14d64s9k1z4u a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (_q_io_deq_ready_T_3), // @[Error.scala:35:46] .io_deq_valid (_a_q_io_deq_valid), .io_deq_bits_opcode (_a_q_io_deq_bits_opcode), .io_deq_bits_size (_a_q_io_deq_bits_size), .io_deq_bits_source (da_bits_source) ); // @[Decoupled.scala:362:21] assign da_bits_size = _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Error.scala:21:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Error.scala:21:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Error.scala:21:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Error.scala:21:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Error.scala:21:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Error.scala:21:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_16( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1502 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1502; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1502; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1575 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1575; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1428 = _T_1502 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1428 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1428 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1428 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1428 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1428 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1474 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1474 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1443 = _T_1575 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1443 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1443 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1443 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1546 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1546 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1528 = _T_1575 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1528 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1528 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1528 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File CustomCSRs.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import org.chipsalliance.cde.config.Parameters case class CustomCSR(id: Int, mask: BigInt, init: Option[BigInt]) object CustomCSR { def constant(id: Int, value: BigInt): CustomCSR = CustomCSR(id, BigInt(0), Some(value)) } class CustomCSRIO(implicit p: Parameters) extends CoreBundle { val ren = Output(Bool()) // set by CSRFile, indicates an instruction is reading the CSR val wen = Output(Bool()) // set by CSRFile, indicates an instruction is writing the CSR val wdata = Output(UInt(xLen.W)) // wdata provided by instruction writing CSR val value = Output(UInt(xLen.W)) // current value of CSR in CSRFile val stall = Input(Bool()) // reads and writes to this CSR should stall (must be bounded) val set = Input(Bool()) // set/sdata enables external agents to set the value of this CSR val sdata = Input(UInt(xLen.W)) } class CustomCSRs(implicit p: Parameters) extends CoreBundle { // Not all cores have these CSRs, but those that do should follow the same // numbering conventions. So we list them here but default them to None. protected def bpmCSRId = 0x7c0 protected def bpmCSR: Option[CustomCSR] = None protected def chickenCSRId = 0x7c1 protected def chickenCSR: Option[CustomCSR] = None // If you override this, you'll want to concatenate super.decls def decls: Seq[CustomCSR] = bpmCSR.toSeq ++ chickenCSR val csrs = Vec(decls.size, new CustomCSRIO) def flushBTB = getOrElse(bpmCSR, _.wen, false.B) def bpmStatic = getOrElse(bpmCSR, _.value(0), false.B) def disableDCacheClockGate = getOrElse(chickenCSR, _.value(0), false.B) def disableICacheClockGate = getOrElse(chickenCSR, _.value(1), false.B) def disableCoreClockGate = getOrElse(chickenCSR, _.value(2), false.B) def disableSpeculativeICacheRefill = getOrElse(chickenCSR, _.value(3), false.B) def suppressCorruptOnGrantData = getOrElse(chickenCSR, _.value(9), false.B) protected def getByIdOrElse[T](id: Int, f: CustomCSRIO => T, alt: T): T = { val idx = decls.indexWhere(_.id == id) if (idx < 0) alt else f(csrs(idx)) } protected def getOrElse[T](csr: Option[CustomCSR], f: CustomCSRIO => T, alt: T): T = csr.map(c => getByIdOrElse(c.id, f, alt)).getOrElse(alt) } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File Events.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.log2Ceil import freechips.rocketchip.util._ import freechips.rocketchip.util.property class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bool)]) { def size = events.size val hits = WireDefault(VecInit(Seq.fill(size)(false.B))) def check(mask: UInt) = { hits := events.map(_._2()) gate(mask, hits.asUInt) } def dump(): Unit = { for (((name, _), i) <- events.zipWithIndex) when (check(1.U << i)) { printf(s"Event $name\n") } } def withCovers: Unit = { events.zipWithIndex.foreach { case ((name, func), i) => property.cover(gate((1.U << i), (func() << i)), name) } } } class EventSets(val eventSets: Seq[EventSet]) { def maskEventSelector(eventSel: UInt): UInt = { // allow full associativity between counters and event sets (for now?) val setMask = (BigInt(1) << eventSetIdBits) - 1 val maskMask = ((BigInt(1) << eventSets.map(_.size).max) - 1) << maxEventSetIdBits eventSel & (setMask \| maskMask).U } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } def evaluate(eventSel: UInt): Bool = { val (set, mask) = decode(eventSel) val sets = for (e <- eventSets) yield { require(e.hits.getWidth <= mask.getWidth, s"too many events ${e.hits.getWidth} wider than mask ${mask.getWidth}") e check mask } sets(set) } def cover() = eventSets.foreach { _.withCovers } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSetIdBits <= maxEventSetIdBits) } class SuperscalarEventSets(val eventSets: Seq[(Seq[EventSet], (UInt, UInt) => UInt)]) { def evaluate(eventSel: UInt): UInt = { val (set, mask) = decode(eventSel) val sets = for ((sets, reducer) <- eventSets) yield { sets.map { set => require(set.hits.getWidth <= mask.getWidth, s"too many events ${set.hits.getWidth} wider than mask ${mask.getWidth}") set.check(mask) }.reduce(reducer) } val zeroPadded = sets.padTo(1 << eventSetIdBits, 0.U) zeroPadded(set) } def toScalarEventSets: EventSets = new EventSets(eventSets.map(_._1.head)) def cover(): Unit = { eventSets.foreach(_._1.foreach(_.withCovers)) } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSets.forall(s => s._1.forall(_.size == s._1.head.size))) require(eventSetIdBits <= maxEventSetIdBits) } File RocketCore.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.withClock import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ArrayBuffer case class RocketCoreParams( xLen: Int = 64, pgLevels: Int = 3, // sv39 default bootFreqHz: BigInt = 0, useVM: Boolean = true, useUser: Boolean = false, useSupervisor: Boolean = false, useHypervisor: Boolean = false, useDebug: Boolean = true, useAtomics: Boolean = true, useAtomicsOnlyForIO: Boolean = false, useCompressed: Boolean = true, useRVE: Boolean = false, useConditionalZero: Boolean = false, useZba: Boolean = false, useZbb: Boolean = false, useZbs: Boolean = false, nLocalInterrupts: Int = 0, useNMI: Boolean = false, nBreakpoints: Int = 1, useBPWatch: Boolean = false, mcontextWidth: Int = 0, scontextWidth: Int = 0, nPMPs: Int = 8, nPerfCounters: Int = 0, haveBasicCounters: Boolean = true, haveCFlush: Boolean = false, misaWritable: Boolean = true, nL2TLBEntries: Int = 0, nL2TLBWays: Int = 1, nPTECacheEntries: Int = 8, mtvecInit: Option[BigInt] = Some(BigInt(0)), mtvecWritable: Boolean = true, fastLoadWord: Boolean = true, fastLoadByte: Boolean = false, branchPredictionModeCSR: Boolean = false, clockGate: Boolean = false, mvendorid: Int = 0, // 0 means non-commercial implementation mimpid: Int = 0x20181004, // release date in BCD mulDiv: Option[MulDivParams] = Some(MulDivParams()), fpu: Option[FPUParams] = Some(FPUParams()), debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB haveCease: Boolean = true, // non-standard CEASE instruction haveSimTimeout: Boolean = true, // add plusarg for simulation timeout vector: Option[RocketCoreVectorParams] = None ) extends CoreParams { val lgPauseCycles = 5 val haveFSDirty = false val pmpGranularity: Int = if (useHypervisor) 4096 else 4 val fetchWidth: Int = if (useCompressed) 2 else 1 // fetchWidth doubled, but coreInstBytes halved, for RVC: val decodeWidth: Int = fetchWidth / (if (useCompressed) 2 else 1) val retireWidth: Int = 1 val instBits: Int = if (useCompressed) 16 else 32 val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace override val useVector = vector.isDefined override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false) override def vLen = vector.map(_.vLen).getOrElse(0) override def eLen = vector.map(_.eLen).getOrElse(0) override def vfLen = vector.map(_.vfLen).getOrElse(0) override def vfh = vector.map(_.vfh).getOrElse(false) override def vExts = vector.map(_.vExts).getOrElse(Nil) override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0) override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32) override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs } trait HasRocketCoreParameters extends HasCoreParameters { lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams] val fastLoadWord = rocketParams.fastLoadWord val fastLoadByte = rocketParams.fastLoadByte val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this require(!fastLoadByte \|\| fastLoadWord) require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty") } class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters { override def bpmCSR = { rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0)))) } private def haveDCache = tileParams.dcache.get.scratch.isEmpty override def chickenCSR = { val mask = BigInt( tileParams.dcache.get.clockGate.toInt << 0 \| rocketParams.clockGate.toInt << 1 \| rocketParams.clockGate.toInt << 2 \| 1 << 3 \| // disableSpeculativeICacheRefill haveDCache.toInt << 9 \| // suppressCorruptOnGrantData tileParams.icache.get.prefetch.toInt << 17 ) Some(CustomCSR(chickenCSRId, mask, Some(mask))) } def disableICachePrefetch = getOrElse(chickenCSR, _.value(17), true.B) def marchid = CustomCSR.constant(CSRs.marchid, BigInt(1)) def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid)) // mimpid encodes a release version in the form of a BCD-encoded datestamp. def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid)) override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid } class CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) { val buserror = Option.when(hasBeu)(Bool()) } trait HasRocketCoreIO extends HasRocketCoreParameters { implicit val p: Parameters def nTotalRoCCCSRs: Int val io = IO(new CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val reset_vector = Input(UInt(resetVectorLen.W)) val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParams].beuAddr.isDefined)) val imem = new FrontendIO val dmem = new HellaCacheIO val ptw = Flipped(new DatapathPTWIO()) val fpu = Flipped(new FPUCoreIO()) val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs)) val trace = Output(new TraceBundle) val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth))) val cease = Output(Bool()) val wfi = Output(Bool()) val traceStall = Input(Bool()) val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None }) } class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) with HasRocketCoreParameters with HasRocketCoreIO { def nTotalRoCCCSRs = tile.roccCSRs.flatten.size import ALU._ val clock_en_reg = RegInit(true.B) val long_latency_stall = Reg(Bool()) val id_reg_pause = Reg(Bool()) val imem_might_request_reg = Reg(Bool()) val clock_en = WireDefault(true.B) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "rocket_clock_gate") class RocketImpl { // entering gated-clock domain // performance counters def pipelineIDToWB[T <: Data](x: T): T = RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid) val perfEvents = new EventSets(Seq( new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq( ("exception", () => false.B), ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp), ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp), ("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) \|\| id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))), ("system", () => id_ctrl.csr =/= CSR.N), ("arith", () => id_ctrl.wxd && !(id_ctrl.jal \|\| id_ctrl.jalr \|\| id_ctrl.mem \|\| id_ctrl.fp \|\| id_ctrl.mul \|\| id_ctrl.div \|\| id_ctrl.csr =/= CSR.N)), ("branch", () => id_ctrl.branch), ("jal", () => id_ctrl.jal), ("jalr", () => id_ctrl.jalr)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV), ("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV))) ++ (if (!usingFPU) Seq() else Seq( ("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen), ("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen), ("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23), ("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3), ("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3), ("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div \|\| io.fpu.dec.sqrt)), ("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst \|\| io.fpu.dec.fma \|\| io.fpu.dec.div \|\| io.fpu.dec.sqrt))))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("load-use interlock", () => id_ex_hazard && ex_ctrl.mem \|\| id_mem_hazard && mem_ctrl.mem \|\| id_wb_hazard && wb_ctrl.mem), ("long-latency interlock", () => id_sboard_hazard), ("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N \|\| id_mem_hazard && mem_ctrl.csr =/= CSR.N \|\| id_wb_hazard && wb_ctrl.csr =/= CSR.N), ("I$ blocked", () => icache_blocked), ("D$ blocked", () => id_ctrl.mem && dcache_blocked), ("branch misprediction", () => take_pc_mem && mem_direction_misprediction), ("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked), ("flush", () => wb_reg_flush_pipe), ("replay", () => replay_wb)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul \|\| ex_ctrl.div) \|\| id_mem_hazard && (mem_ctrl.mul \|\| mem_ctrl.div) \|\| id_wb_hazard && wb_ctrl.div))) ++ (if (!usingFPU) Seq() else Seq( ("fp interlock", () => id_ex_hazard && ex_ctrl.fp \|\| id_mem_hazard && mem_ctrl.fp \|\| id_wb_hazard && wb_ctrl.fp \|\| id_ctrl.fp && id_stall_fpu)))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("I$ miss", () => io.imem.perf.acquire), ("D$ miss", () => io.dmem.perf.acquire), ("D$ release", () => io.dmem.perf.release), ("ITLB miss", () => io.imem.perf.tlbMiss), ("DTLB miss", () => io.dmem.perf.tlbMiss), ("L2 TLB miss", () => io.ptw.perf.l2miss))))) val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen val decode_table = { (if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++: (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: (if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++: (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++: (if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++: (usingRoCC.option(new RoCCDecode)) ++: (if (xLen == 32) new I32Decode else new I64Decode) +: (usingVM.option(new SVMDecode)) ++: (usingSupervisor.option(new SDecode)) ++: (usingHypervisor.option(new HypervisorDecode)) ++: ((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++: (usingDebug.option(new DebugDecode)) ++: (usingNMI.option(new NMIDecode)) ++: (usingConditionalZero.option(new ConditionalZeroDecode)) ++: Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++: coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++: rocketParams.haveCease.option(new CeaseDecode) ++: usingVector.option(new VCFGDecode) ++: (if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++: (if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++: coreParams.useZbs.option(new ZbsDecode) ++: Seq(new IDecode) } flatMap(_.table) val ex_ctrl = Reg(new IntCtrlSigs) val mem_ctrl = Reg(new IntCtrlSigs) val wb_ctrl = Reg(new IntCtrlSigs) val ex_reg_xcpt_interrupt = Reg(Bool()) val ex_reg_valid = Reg(Bool()) val ex_reg_rvc = Reg(Bool()) val ex_reg_btb_resp = Reg(new BTBResp) val ex_reg_xcpt = Reg(Bool()) val ex_reg_flush_pipe = Reg(Bool()) val ex_reg_load_use = Reg(Bool()) val ex_reg_cause = Reg(UInt()) val ex_reg_replay = Reg(Bool()) val ex_reg_pc = Reg(UInt()) val ex_reg_mem_size = Reg(UInt()) val ex_reg_hls = Reg(Bool()) val ex_reg_inst = Reg(Bits()) val ex_reg_raw_inst = Reg(UInt()) val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val ex_reg_set_vconfig = Reg(Bool()) val mem_reg_xcpt_interrupt = Reg(Bool()) val mem_reg_valid = Reg(Bool()) val mem_reg_rvc = Reg(Bool()) val mem_reg_btb_resp = Reg(new BTBResp) val mem_reg_xcpt = Reg(Bool()) val mem_reg_replay = Reg(Bool()) val mem_reg_flush_pipe = Reg(Bool()) val mem_reg_cause = Reg(UInt()) val mem_reg_slow_bypass = Reg(Bool()) val mem_reg_load = Reg(Bool()) val mem_reg_store = Reg(Bool()) val mem_reg_set_vconfig = Reg(Bool()) val mem_reg_sfence = Reg(Bool()) val mem_reg_pc = Reg(UInt()) val mem_reg_inst = Reg(Bits()) val mem_reg_mem_size = Reg(UInt()) val mem_reg_hls_or_dv = Reg(Bool()) val mem_reg_raw_inst = Reg(UInt()) val mem_reg_wdata = Reg(Bits()) val mem_reg_rs2 = Reg(Bits()) val mem_br_taken = Reg(Bool()) val take_pc_mem = Wire(Bool()) val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val wb_reg_valid = Reg(Bool()) val wb_reg_xcpt = Reg(Bool()) val wb_reg_replay = Reg(Bool()) val wb_reg_flush_pipe = Reg(Bool()) val wb_reg_cause = Reg(UInt()) val wb_reg_set_vconfig = Reg(Bool()) val wb_reg_sfence = Reg(Bool()) val wb_reg_pc = Reg(UInt()) val wb_reg_mem_size = Reg(UInt()) val wb_reg_hls_or_dv = Reg(Bool()) val wb_reg_hfence_v = Reg(Bool()) val wb_reg_hfence_g = Reg(Bool()) val wb_reg_inst = Reg(Bits()) val wb_reg_raw_inst = Reg(UInt()) val wb_reg_wdata = Reg(Bits()) val wb_reg_rs2 = Reg(Bits()) val take_pc_wb = Wire(Bool()) val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val take_pc_mem_wb = take_pc_wb \|\| take_pc_mem val take_pc = take_pc_mem_wb // decode stage val ibuf = Module(new IBuf) val id_expanded_inst = ibuf.io.inst.map(_.bits.inst) val id_raw_inst = ibuf.io.inst.map(_.bits.raw) val id_inst = id_expanded_inst.map(_.bits) ibuf.io.imem <> io.imem.resp ibuf.io.kill := take_pc require(decodeWidth == 1 / TODO / && retireWidth == decodeWidth) require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point") require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor") val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table) val lgNXRegs = if (coreParams.useRVE) 4 else 5 val regAddrMask = (1 << lgNXRegs) - 1 def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0)) val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3) val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2) val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1) val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd) val id_load_use = Wire(Bool()) val id_reg_fence = RegInit(false.B) val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2) val id_raddr = IndexedSeq(id_raddr1, id_raddr2) val rf = new RegFile(regAddrMask, xLen) val id_rs = id_raddr.map(rf.read _) val ctrl_killd = Wire(Bool()) val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined)) val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W) val id_system_insn = id_ctrl.csr === CSR.I val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr)) val id_csr_flush = id_system_insn \|\| (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush) val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B id_ctrl.vec := false.B if (usingVector) { val v_decode = rocketParams.vector.get.decoder(p) v_decode.io.inst := id_inst(0) v_decode.io.vconfig := csr.io.vector.get.vconfig when (v_decode.io.legal) { id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill id_ctrl.fp := v_decode.io.fp id_ctrl.rocc := false.B id_ctrl.branch := false.B id_ctrl.jal := false.B id_ctrl.jalr := false.B id_ctrl.rxs2 := v_decode.io.read_rs2 id_ctrl.rxs1 := v_decode.io.read_rs1 id_ctrl.mem := false.B id_ctrl.rfs1 := v_decode.io.read_frs1 id_ctrl.rfs2 := false.B id_ctrl.rfs3 := false.B id_ctrl.wfd := v_decode.io.write_frd id_ctrl.mul := false.B id_ctrl.div := false.B id_ctrl.wxd := v_decode.io.write_rd id_ctrl.csr := CSR.N id_ctrl.fence_i := false.B id_ctrl.fence := false.B id_ctrl.amo := false.B id_ctrl.dp := false.B id_ctrl.vec := true.B } } val id_illegal_insn = !id_ctrl.legal \|\| (id_ctrl.mul \|\| id_ctrl.div) && !csr.io.status.isa('m'-'a') \|\| id_ctrl.amo && !csr.io.status.isa('a'-'a') \|\| id_ctrl.fp && (csr.io.decode(0).fp_illegal \|\| (io.fpu.illegal_rm && !id_ctrl.vec)) \|\| (id_ctrl.vec) && (csr.io.decode(0).vector_illegal \|\| csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) \|\| id_ctrl.dp && !csr.io.status.isa('d'-'a') \|\| ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') \|\| id_raddr2_illegal && id_ctrl.rxs2 \|\| id_raddr1_illegal && id_ctrl.rxs1 \|\| id_waddr_illegal && id_ctrl.wxd \|\| id_ctrl.rocc && csr.io.decode(0).rocc_illegal \|\| id_csr_en && (csr.io.decode(0).read_illegal \|\| !id_csr_ren && csr.io.decode(0).write_illegal) \|\| !ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal) val id_virtual_insn = id_ctrl.legal && ((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) \|\| (!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal)) // stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE) val id_amo_aq = id_inst(0)(26) val id_amo_rl = id_inst(0)(25) val id_fence_pred = id_inst(0)(27,24) val id_fence_succ = id_inst(0)(23,20) val id_fence_next = id_ctrl.fence \|\| id_ctrl.amo && id_amo_aq val id_mem_busy = !io.dmem.ordered \|\| io.dmem.req.valid when (!id_mem_busy) { id_reg_fence := false.B } val id_rocc_busy = usingRoCC.B && (io.rocc.busy \|\| ex_reg_valid && ex_ctrl.rocc \|\| mem_reg_valid && mem_ctrl.rocc \|\| wb_reg_valid && wb_ctrl.rocc) val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren val id_vec_busy = io.vector.map(v => v.backend_busy \|\| v.trap_check_busy).getOrElse(false.B) val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence \|\| id_csr_rocc_write) \|\| id_vec_busy && id_ctrl.fence \|\| id_mem_busy && (id_ctrl.amo && id_amo_rl \|\| id_ctrl.fence_i \|\| id_reg_fence && (id_ctrl.mem \|\| id_ctrl.rocc))) val bpu = Module(new BreakpointUnit(nBreakpoints)) bpu.io.status := csr.io.status bpu.io.bp := csr.io.bp bpu.io.pc := ibuf.io.pc bpu.io.ea := mem_reg_wdata bpu.io.mcontext := csr.io.mcontext bpu.io.scontext := csr.io.scontext val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0 val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1 val (id_xcpt, id_cause) = checkExceptions(List( (csr.io.interrupt, csr.io.interrupt_cause), (bpu.io.debug_if, CSR.debugTriggerCause.U), (bpu.io.xcpt_if, Causes.breakpoint.U), (id_xcpt0.pf.inst, Causes.fetch_page_fault.U), (id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt0.ae.inst, Causes.fetch_access.U), (id_xcpt1.pf.inst, Causes.fetch_page_fault.U), (id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt1.ae.inst, Causes.fetch_access.U), (id_virtual_insn, Causes.virtual_instruction.U), (id_illegal_insn, Causes.illegal_instruction.U))) val idCoverCauses = List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.fetch_access, "FETCH_ACCESS"), (Causes.illegal_instruction, "ILLEGAL_INSTRUCTION") ) ++ (if (usingVM) List( (Causes.fetch_page_fault, "FETCH_PAGE_FAULT") ) else Nil) coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses) val dcache_bypass_data = if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0) else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0) else wb_reg_wdata // detect bypass opportunities val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U val bypass_sources = IndexedSeq( (true.B, 0.U, 0.U), // treat reading x0 as a bypass (ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata), (mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata), (mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data)) val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr)) // execute stage val bypass_mux = bypass_sources.map(_._3) val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool())) val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W))) val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt())) val ex_rs = for (i <- 0 until id_raddr.size) yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i))) val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst) val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13) val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq( A1_RS1 -> ex_rs(0).asSInt, A1_PC -> ex_reg_pc.asSInt, A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S) )) val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq( A2_RS2 -> ex_rs(1).asSInt, A2_IMM -> ex_imm, A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S), ) ++ (if (coreParams.useZbs) Seq( A2_RS2OH -> ex_op2_oh, A2_IMMOH -> ex_op2_oh, ) else Nil)) val (ex_new_vl, ex_new_vconfig) = if (usingVector) { val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq( ex_reg_inst(31,30).andR -> ex_reg_inst(29,20), !ex_reg_inst(31) -> ex_reg_inst(30,20)))) val ex_avl = Mux(ex_ctrl.rxs1, Mux(ex_reg_inst(19,15) === 0.U, Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax), ex_rs(0) ), ex_reg_inst(19,15)) val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B) val ex_new_vconfig = Wire(new VConfig) ex_new_vconfig.vtype := ex_new_vtype ex_new_vconfig.vl := ex_new_vl (Some(ex_new_vl), Some(ex_new_vconfig)) } else { (None, None) } val alu = Module(new ALU) alu.io.dw := ex_ctrl.alu_dw alu.io.fn := ex_ctrl.alu_fn alu.io.in2 := ex_op2.asUInt alu.io.in1 := ex_op1.asUInt // multiplier and divider val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen)) div.io.req.valid := ex_reg_valid && ex_ctrl.div div.io.req.bits.dw := ex_ctrl.alu_dw div.io.req.bits.fn := ex_ctrl.alu_fn div.io.req.bits.in1 := ex_rs(0) div.io.req.bits.in2 := ex_rs(1) div.io.req.bits.tag := ex_waddr val mul = pipelinedMul.option { val m = Module(new PipelinedMultiplier(xLen, 2)) m.io.req.valid := ex_reg_valid && ex_ctrl.mul m.io.req.bits := div.io.req.bits m } ex_reg_valid := !ctrl_killd ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay ex_reg_xcpt := !ctrl_killd && id_xcpt ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt when (!ctrl_killd) { ex_ctrl := id_ctrl ex_reg_rvc := ibuf.io.inst(0).bits.rvc ex_ctrl.csr := id_csr when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B } when (id_fence_next) { id_reg_fence := true.B } when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr ex_ctrl.alu_fn := FN_ADD ex_ctrl.alu_dw := DW_XPR ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction ex_ctrl.sel_alu2 := A2_ZERO when (id_xcpt1.asUInt.orR) { // badaddr := PC+2 ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_SIZE ex_reg_rvc := true.B } when (bpu.io.xcpt_if \|\| id_xcpt0.asUInt.orR) { // badaddr := PC ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_ZERO } } ex_reg_flush_pipe := id_ctrl.fence_i \|\| id_csr_flush ex_reg_load_use := id_load_use ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX) ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12)) when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) { ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U) } when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) { ex_ctrl.mem_cmd := M_HFENCEV } if (tile.dcache.flushOnFenceI) { when (id_ctrl.fence_i) { ex_reg_mem_size := 0.U } } for (i <- 0 until id_raddr.size) { val do_bypass = id_bypass_src(i).reduce(_\|\|_) val bypass_src = PriorityEncoder(id_bypass_src(i)) ex_reg_rs_bypass(i) := do_bypass ex_reg_rs_lsb(i) := bypass_src when (id_ren(i) && !do_bypass) { ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size) } } when (id_illegal_insn \|\| id_virtual_insn) { val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0)) ex_reg_rs_bypass(0) := false.B ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size) } } when (!ctrl_killd \|\| csr.io.interrupt \|\| ibuf.io.inst(0).bits.replay) { ex_reg_cause := id_cause ex_reg_inst := id_inst(0) ex_reg_raw_inst := id_raw_inst(0) ex_reg_pc := ibuf.io.pc ex_reg_btb_resp := ibuf.io.btb_resp ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) } ex_reg_set_vconfig := id_set_vconfig && !id_xcpt } // replay inst in ex stage? val ex_pc_valid = ex_reg_valid \|\| ex_reg_replay \|\| ex_reg_xcpt_interrupt val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready \|\| ex_ctrl.div && !div.io.req.ready \|\| ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B) val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use val replay_ex = ex_reg_replay \|\| (ex_reg_valid && (replay_ex_structural \|\| replay_ex_load_use)) val ctrl_killx = take_pc_mem_wb \|\| replay_ex \|\| !ex_reg_valid // detect 2-cycle load-use delay for LB/LH/SC val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC \|\| ex_reg_mem_size < 2.U val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE \|\| ex_ctrl.mem_cmd === M_HFENCEV \|\| ex_ctrl.mem_cmd === M_HFENCEG) val (ex_xcpt, ex_cause) = checkExceptions(List( (ex_reg_xcpt_interrupt \|\| ex_reg_xcpt, ex_reg_cause))) val exCoverCauses = idCoverCauses coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses) // memory stage val mem_pc_valid = mem_reg_valid \|\| mem_reg_replay \|\| mem_reg_xcpt_interrupt val mem_br_target = mem_reg_pc.asSInt + Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst), Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), Mux(mem_reg_rvc, 2.S, 4.S))) val mem_npc = (Mux(mem_ctrl.jalr \|\| mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt val mem_wrong_npc = Mux(ex_pc_valid, mem_npc =/= ex_reg_pc, Mux(ibuf.io.inst(0).valid \|\| ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B)) val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt val mem_cfi = mem_ctrl.branch \|\| mem_ctrl.jalr \|\| mem_ctrl.jal val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) \|\| mem_ctrl.jalr \|\| mem_ctrl.jal val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken) val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction \|\| mem_reg_sfence) mem_reg_valid := !ctrl_killx mem_reg_replay := !take_pc_mem_wb && replay_ex mem_reg_xcpt := !ctrl_killx && ex_xcpt mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt // on pipeline flushes, cause mem_npc to hold the sequential npc, which // will drive the W-stage npc mux when (mem_reg_valid && mem_reg_flush_pipe) { mem_reg_sfence := false.B }.elsewhen (ex_pc_valid) { mem_ctrl := ex_ctrl mem_reg_rvc := ex_reg_rvc mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd) mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd) mem_reg_sfence := ex_sfence mem_reg_btb_resp := ex_reg_btb_resp mem_reg_flush_pipe := ex_reg_flush_pipe mem_reg_slow_bypass := ex_slow_bypass mem_reg_wphit := ex_reg_wphit mem_reg_set_vconfig := ex_reg_set_vconfig mem_reg_cause := ex_cause mem_reg_inst := ex_reg_inst mem_reg_raw_inst := ex_reg_raw_inst mem_reg_mem_size := ex_reg_mem_size mem_reg_hls_or_dv := io.dmem.req.bits.dv mem_reg_pc := ex_reg_pc // IDecode ensured they are 1H mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out) mem_br_taken := alu.io.cmp_out when (ex_ctrl.rxs2 && (ex_ctrl.mem \|\| ex_ctrl.rocc \|\| ex_sfence)) { val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size) mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data } if (usingVector) { when (ex_reg_set_vconfig) { mem_reg_rs2 := ex_new_vconfig.get.asUInt } } when (ex_ctrl.jalr && csr.io.status.debug) { // flush I$ on D-mode JALR to effect uncached fetch without D$ flush mem_ctrl.fence_i := true.B mem_reg_flush_pipe := true.B } } val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) \|\| (mem_reg_store && bpu.io.xcpt_st) val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) \|\| (mem_reg_store && bpu.io.debug_st) val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List( (mem_debug_breakpoint, CSR.debugTriggerCause.U), (mem_breakpoint, Causes.breakpoint.U))) val (mem_xcpt, mem_cause) = checkExceptions(List( (mem_reg_xcpt_interrupt \|\| mem_reg_xcpt, mem_reg_cause), (mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U), (mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause))) val memCoverCauses = (exCoverCauses ++ List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.misaligned_fetch, "MISALIGNED_FETCH") )).distinct coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses) val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B) val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B) val replay_mem = dcache_kill_mem \|\| mem_reg_replay \|\| fpu_kill_mem \|\| vec_kill_mem \|\| vec_kill_all val killm_common = dcache_kill_mem \|\| take_pc_wb \|\| mem_reg_xcpt \|\| !mem_reg_valid div.io.kill := killm_common && RegNext(div.io.req.fire) val ctrl_killm = killm_common \|\| mem_xcpt \|\| fpu_kill_mem \|\| vec_kill_mem // writeback stage wb_reg_valid := !ctrl_killm wb_reg_replay := replay_mem && !take_pc_wb wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B) wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe when (mem_pc_valid) { wb_ctrl := mem_ctrl wb_reg_sfence := mem_reg_sfence wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata) when (mem_ctrl.rocc \|\| mem_reg_sfence \|\| mem_reg_set_vconfig) { wb_reg_rs2 := mem_reg_rs2 } wb_reg_cause := mem_cause wb_reg_inst := mem_reg_inst wb_reg_raw_inst := mem_reg_raw_inst wb_reg_mem_size := mem_reg_mem_size wb_reg_hls_or_dv := mem_reg_hls_or_dv wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG wb_reg_pc := mem_reg_pc wb_reg_wphit := mem_reg_wphit \| bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) \|\| (bpw.wvalid(0) && mem_reg_store) } wb_reg_set_vconfig := mem_reg_set_vconfig } val (wb_xcpt, wb_cause) = checkExceptions(List( (wb_reg_xcpt, wb_reg_cause), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U) )) val wbCoverCauses = List( (Causes.misaligned_store, "MISALIGNED_STORE"), (Causes.misaligned_load, "MISALIGNED_LOAD"), (Causes.store_access, "STORE_ACCESS"), (Causes.load_access, "LOAD_ACCESS") ) ++ (if(usingVM) List( (Causes.store_page_fault, "STORE_PAGE_FAULT"), (Causes.load_page_fault, "LOAD_PAGE_FAULT") ) else Nil) ++ (if (usingHypervisor) List( (Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"), (Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT"), ) else Nil) coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses) val wb_pc_valid = wb_reg_valid \|\| wb_reg_replay \|\| wb_reg_xcpt val wb_wxd = wb_reg_valid && wb_ctrl.wxd val wb_set_sboard = wb_ctrl.div \|\| wb_dcache_miss \|\| wb_ctrl.rocc \|\| wb_ctrl.vec val replay_wb_common = io.dmem.s2_nack \|\| wb_reg_replay val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B) val replay_wb = replay_wb_common \|\| replay_wb_rocc \|\| replay_wb_csr \|\| replay_wb_vec take_pc_wb := replay_wb \|\| wb_xcpt \|\| csr.io.eret \|\| wb_reg_flush_pipe // writeback arbitration val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1) val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay class LLWB extends Bundle { val data = UInt(xLen.W) val tag = UInt(5.W) } val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec ll_arb.io.in.foreach(_.valid := false.B) ll_arb.io.in.foreach(_.bits := DontCare) val ll_wdata = WireInit(ll_arb.io.out.bits.data) val ll_waddr = WireInit(ll_arb.io.out.bits.tag) val ll_wen = WireInit(ll_arb.io.out.fire) ll_arb.io.out.ready := !wb_wxd div.io.resp.ready := ll_arb.io.in(0).ready ll_arb.io.in(0).valid := div.io.resp.valid ll_arb.io.in(0).bits.data := div.io.resp.bits.data ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag if (usingRoCC) { io.rocc.resp.ready := ll_arb.io.in(1).ready ll_arb.io.in(1).valid := io.rocc.resp.valid ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd } else { // tie off RoCC io.rocc.resp.ready := false.B io.rocc.mem.req.ready := false.B } io.vector.map { v => v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready) ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp ll_arb.io.in(2).bits.data := v.resp.bits.data ll_arb.io.in(2).bits.tag := v.resp.bits.rd } // Dont care mem since not all RoCC need accessing memory io.rocc.mem := DontCare when (dmem_resp_replay && dmem_resp_xpu) { ll_arb.io.out.ready := false.B ll_waddr := dmem_resp_waddr ll_wen := true.B } val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt val wb_wen = wb_valid && wb_ctrl.wxd val rf_wen = wb_wen \|\| ll_wen val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr) val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0), Mux(ll_wen, ll_wdata, Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata, Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata), wb_reg_wdata)))) when (rf_wen) { rf.write(rf_waddr, rf_wdata) } // hook up control/status regfile csr.io.ungated_clock := clock csr.io.decode(0).inst := id_inst(0) csr.io.exception := wb_xcpt csr.io.cause := wb_cause csr.io.retire := wb_valid csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst) csr.io.interrupts := io.interrupts csr.io.hartid := io.hartid io.fpu.fcsr_rm := csr.io.fcsr_rm val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W)) val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B) csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid \| vector_fcsr_flags_valid csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) \| (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid)) io.fpu.time := csr.io.time(31,0) io.fpu.hartid := io.hartid csr.io.rocc_interrupt := io.rocc.interrupt csr.io.pc := wb_reg_pc val tval_dmem_addr = !wb_reg_xcpt val tval_any_addr = tval_dmem_addr \|\| wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U) val tval_inst = wb_reg_cause === Causes.illegal_instruction.U val tval_valid = wb_xcpt && (tval_any_addr \|\| tval_inst) csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v \|\| tval_dmem_addr && wb_reg_hls_or_dv) csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U) val (htval, mhtinst_read_pseudo) = { val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U) assert(!htval_valid_imem \|\| io.imem.gpa.valid) val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U) val htval = (htval_dmem \| htval_imem) >> hypervisorExtraAddrBits // read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) \|\| (io.dmem.s2_gpa_is_pte && htval_valid_dmem) (htval, mhtinst_read_pseudo) } csr.io.vector.foreach { v => v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig) v.set_vs_dirty := wb_valid && wb_ctrl.vec v.set_vstart.valid := wb_valid && wb_reg_set_vconfig v.set_vstart.bits := 0.U } io.vector.foreach { v => when (v.wb.retire \|\| v.wb.xcpt \|\| wb_ctrl.vec) { csr.io.pc := v.wb.pc csr.io.retire := v.wb.retire csr.io.inst(0) := v.wb.inst when (v.wb.xcpt && !wb_reg_xcpt) { wb_xcpt := true.B wb_cause := v.wb.cause csr.io.tval := v.wb.tval } } v.wb.store_pending := io.dmem.store_pending v.wb.vxrm := csr.io.vector.get.vxrm v.wb.frm := csr.io.fcsr_rm csr.io.vector.get.set_vxsat := v.set_vxsat when (v.set_vconfig.valid) { csr.io.vector.get.set_vconfig.valid := true.B csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits } when (v.set_vstart.valid) { csr.io.vector.get.set_vstart.valid := true.B csr.io.vector.get.set_vstart.bits := v.set_vstart.bits } } csr.io.htval := htval csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo io.ptw.ptbr := csr.io.ptbr io.ptw.hgatp := csr.io.hgatp io.ptw.vsatp := csr.io.vsatp (io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs } io.ptw.status := csr.io.status io.ptw.hstatus := csr.io.hstatus io.ptw.gstatus := csr.io.gstatus io.ptw.pmp := csr.io.pmp csr.io.rw.addr := wb_reg_inst(31,20) csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr) csr.io.rw.wdata := wb_reg_wdata io.rocc.csrs <> csr.io.roccCSRs io.trace.time := csr.io.time io.trace.insns := csr.io.trace if (rocketParams.debugROB.isDefined) { val sz = rocketParams.debugROB.get.size if (sz < 1) { // use unsynthesizable ROB val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val should_wb = WireInit((wb_ctrl.wfd \|\| (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception) val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard) val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)) io.vector.foreach { v => when (v.wb.retire) { should_wb := v.wb.rob_should_wb has_wb := false.B wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7)) }} DebugROB.pushTrace(clock, reset, io.hartid, csr_trace_with_wdata, should_wb, has_wb, wb_addr) io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid) DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata) } else { // synthesizable ROB (no FPRs) require(!usingVector, "Synthesizable ROB does not support vector implementations") val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val debug_rob = Module(new HardDebugROB(sz, 32)) debug_rob.io.i_insn := csr_trace_with_wdata debug_rob.io.should_wb := (wb_ctrl.wfd \|\| (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U) debug_rob.io.wb_val := ll_wen debug_rob.io.wb_tag := rf_waddr debug_rob.io.wb_data := rf_wdata io.trace.insns(0) := debug_rob.io.o_insn } } else { io.trace.insns := csr.io.trace } for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) { iobpw.valid(0) := wphit iobpw.action := bp.control.action // tie off bpwatch valids iobpw.rvalid.foreach(_ := false.B) iobpw.wvalid.foreach(_ := false.B) iobpw.ivalid.foreach(_ := false.B) } val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1), (id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2), (id_ctrl.wxd && id_waddr =/= 0.U, id_waddr)) val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1), (io.fpu.dec.ren2, id_raddr2), (io.fpu.dec.ren3, id_raddr3), (io.fpu.dec.wen, id_waddr)) val sboard = new Scoreboard(32, true) sboard.clear(ll_wen, ll_waddr) def id_sboard_clear_bypass(r: UInt) = { // ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r else div.io.resp.fire && div.io.resp.bits.tag === r \|\| dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r } val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd)) sboard.set(wb_set_sboard && wb_wen, wb_waddr) // stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage. val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N \|\| ex_ctrl.jalr \|\| ex_ctrl.mem \|\| ex_ctrl.mul \|\| ex_ctrl.div \|\| ex_ctrl.fp \|\| ex_ctrl.rocc \|\| ex_ctrl.vec val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr) val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr) val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass \|\| fp_data_hazard_ex) // stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage. val mem_mem_cmd_bh = if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass else true.B val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N \|\| mem_ctrl.mem && mem_mem_cmd_bh \|\| mem_ctrl.mul \|\| mem_ctrl.div \|\| mem_ctrl.fp \|\| mem_ctrl.rocc \|\| mem_ctrl.vec val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr) val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr) val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass \|\| fp_data_hazard_mem) id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem val id_vconfig_hazard = id_ctrl.vec && ( (ex_reg_valid && ex_reg_set_vconfig) \|\| (mem_reg_valid && mem_reg_set_vconfig) \|\| (wb_reg_valid && wb_reg_set_vconfig)) // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback. val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr) val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr) val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard \|\| fp_data_hazard_wb) val id_stall_fpu = if (usingFPU) { val fp_sboard = new Scoreboard(32) fp_sboard.set(((wb_dcache_miss \|\| wb_ctrl.vec) && wb_ctrl.wfd \|\| io.fpu.sboard_set) && wb_valid, wb_waddr) val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B) fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) \|\| v_ll, io.fpu.ll_resp_tag) fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) checkHazards(fp_hazard_targets, fp_sboard.read _) } else false.B val dcache_blocked = { // speculate that a blocked D$ will unblock the cycle after a Grant val blocked = Reg(Bool()) blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked \|\| io.dmem.req.valid \|\| io.dmem.s2_nack) blocked && !io.dmem.perf.grant } val rocc_blocked = Reg(Bool()) rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid \|\| rocc_blocked) val ctrl_stalld = id_ex_hazard \|\| id_mem_hazard \|\| id_wb_hazard \|\| id_sboard_hazard \|\| id_vconfig_hazard \|\| csr.io.singleStep && (ex_reg_valid \|\| mem_reg_valid \|\| wb_reg_valid) \|\| id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy \|\| id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy \|\| id_ctrl.fp && id_stall_fpu \|\| id_ctrl.mem && dcache_blocked \|\| // reduce activity during D$ misses id_ctrl.rocc && rocc_blocked \|\| // reduce activity while RoCC is busy id_ctrl.div && (!(div.io.req.ready \|\| (div.io.resp.valid && !wb_wxd)) \|\| div.io.req.valid) \|\| // reduce odds of replay !clock_en \|\| id_do_fence \|\| csr.io.csr_stall \|\| id_reg_pause \|\| io.traceStall ctrl_killd := !ibuf.io.inst(0).valid \|\| ibuf.io.inst(0).bits.replay \|\| take_pc_mem_wb \|\| ctrl_stalld \|\| csr.io.interrupt io.imem.req.valid := take_pc io.imem.req.bits.speculative := !take_pc_wb io.imem.req.bits.pc := Mux(wb_xcpt \|\| csr.io.eret, csr.io.evec, // exception or [m\|s]ret Mux(replay_wb, wb_reg_pc, // replay mem_npc)) // flush or branch misprediction io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack io.imem.might_request := { imem_might_request_reg := ex_pc_valid \|\| mem_pc_valid \|\| io.ptw.customCSRs.disableICacheClockGate \|\| io.vector.map(_.trap_check_busy).getOrElse(false.B) imem_might_request_reg } io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common) io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence io.imem.sfence.bits.rs1 := wb_reg_mem_size(0) io.imem.sfence.bits.rs2 := wb_reg_mem_size(1) io.imem.sfence.bits.addr := wb_reg_wdata io.imem.sfence.bits.asid := wb_reg_rs2 io.imem.sfence.bits.hv := wb_reg_hfence_v io.imem.sfence.bits.hg := wb_reg_hfence_g io.ptw.sfence := io.imem.sfence ibuf.io.inst(0).ready := !ctrl_stalld io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi \|\| mem_cfi_taken) io.imem.btb_update.bits.isValid := mem_cfi io.imem.btb_update.bits.cfiType := Mux((mem_ctrl.jal \|\| mem_ctrl.jalr) && mem_waddr(0), CFIType.call, Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat("b00?01"), CFIType.ret, Mux(mem_ctrl.jal \|\| mem_ctrl.jalr, CFIType.jump, CFIType.branch))) io.imem.btb_update.bits.target := io.imem.req.bits.pc io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc) io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc \| (coreInstBytesfetchWidth-1).U) io.imem.btb_update.bits.prediction := mem_reg_btb_resp io.imem.btb_update.bits.taken := DontCare io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc io.imem.bht_update.bits.taken := mem_br_taken io.imem.bht_update.bits.mispredict := mem_wrong_npc io.imem.bht_update.bits.branch := mem_ctrl.branch io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht // Connect RAS in Frontend io.imem.ras_update := DontCare io.fpu.valid := !ctrl_killd && id_ctrl.fp io.fpu.killx := ctrl_killx io.fpu.killm := killm_common io.fpu.inst := id_inst(0) io.fpu.fromint_data := ex_rs(0) io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data) io.fpu.ll_resp_type := io.dmem.resp.bits.size io.fpu.ll_resp_tag := dmem_resp_waddr io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U) io.vector.map { v => when (!(dmem_resp_valid && dmem_resp_fpu)) { io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp io.fpu.ll_resp_data := v.resp.bits.data io.fpu.ll_resp_type := v.resp.bits.size io.fpu.ll_resp_tag := v.resp.bits.rd } } io.vector.foreach { v => v.ex.valid := ex_reg_valid && (ex_ctrl.vec \|\| rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx v.ex.inst := ex_reg_inst v.ex.vconfig := csr.io.vector.get.vconfig v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec \|\| wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart) v.ex.rs1 := ex_rs(0) v.ex.rs2 := ex_rs(1) v.ex.pc := ex_reg_pc v.mem.frs1 := io.fpu.store_data v.killm := killm_common v.status := csr.io.status } io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp) require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth) io.dmem.req.bits.tag := ex_dcache_tag io.dmem.req.bits.cmd := ex_ctrl.mem_cmd io.dmem.req.bits.size := ex_reg_mem_size io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14)) io.dmem.req.bits.phys := false.B io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out) io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr) io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv) io.dmem.req.bits.dv := ex_reg_hls \|\| csr.io.status.dv io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) \|\| (!ex_ctrl.fp && ex_waddr === 0.U) io.dmem.req.bits.no_alloc := DontCare io.dmem.req.bits.no_xcpt := DontCare io.dmem.req.bits.data := DontCare io.dmem.req.bits.mask := DontCare io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2)) io.dmem.s1_data.mask := DontCare io.dmem.s1_kill := killm_common \|\| mem_ldst_xcpt \|\| fpu_kill_mem \|\| vec_kill_mem io.dmem.s2_kill := false.B // don't let D$ go to sleep if we're probably going to use it soon io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common io.rocc.exception := wb_xcpt && csr.io.status.xs.orR io.rocc.cmd.bits.status := csr.io.status io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction()) io.rocc.cmd.bits.rs1 := wb_reg_wdata io.rocc.cmd.bits.rs2 := wb_reg_rs2 // gate the clock val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U \|\| csr.io.inhibit_cycle \|\| io.dmem.perf.release \|\| take_pc when (unpause) { id_reg_pause := false.B } io.cease := csr.io.status.cease && !clock_en_reg io.wfi := csr.io.status.wfi if (rocketParams.clockGate) { long_latency_stall := csr.io.csr_stall \|\| io.dmem.perf.blocked \|\| id_reg_pause && !unpause clock_en := clock_en_reg \|\| ex_pc_valid \|\| (!long_latency_stall && io.imem.resp.valid) clock_en_reg := ex_pc_valid \|\| mem_pc_valid \|\| wb_pc_valid \|\| // instruction in flight io.ptw.customCSRs.disableCoreClockGate \|\| // chicken bit !div.io.req.ready \|\| // mul/div in flight usingFPU.B && !io.fpu.fcsr_rdy \|\| // long-latency FPU in flight io.dmem.replay_next \|\| // long-latency load replaying (!long_latency_stall && (ibuf.io.inst(0).valid \|\| io.imem.resp.valid)) // instruction pending assert(!(ex_pc_valid \|\| mem_pc_valid \|\| wb_pc_valid) \|\| clock_en) } // evaluate performance counters val icache_blocked = !(io.imem.resp.valid \|\| RegNext(io.imem.resp.valid)) csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) } val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen)) coreMonitorBundle.clock := clock coreMonitorBundle.reset := reset coreMonitorBundle.hartid := io.hartid coreMonitorBundle.timer := csr.io.time(31,0) coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen) coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard coreMonitorBundle.wrenf := false.B coreMonitorBundle.wrdst := wb_waddr coreMonitorBundle.wrdata := rf_wdata coreMonitorBundle.rd0src := wb_reg_inst(19,15) coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0))) coreMonitorBundle.rd1src := wb_reg_inst(24,20) coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1))) coreMonitorBundle.inst := csr.io.trace(0).insn coreMonitorBundle.excpt := csr.io.trace(0).exception coreMonitorBundle.priv_mode := csr.io.trace(0).priv if (enableCommitLog) { val t = csr.io.trace(0) val rd = wb_waddr val wfd = wb_ctrl.wfd val wxd = wb_ctrl.wxd val has_data = wb_wen && !wb_set_sboard when (t.valid && !t.exception) { when (wfd) { printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+32.U) } .elsewhen (wxd && rd =/= 0.U && has_data) { printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata) } .elsewhen (wxd && rd =/= 0.U && !has_data) { printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd) } .otherwise { printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn) } } when (ll_wen && rf_waddr =/= 0.U) { printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata) } } else { when (csr.io.trace(0).valid) { printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid, coreMonitorBundle.pc, Mux(wb_ctrl.wxd \|\| wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U), Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U), coreMonitorBundle.wrenx, Mux(wb_ctrl.rxs1 \|\| wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U), Mux(wb_ctrl.rxs1 \|\| wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U), Mux(wb_ctrl.rxs2 \|\| wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U), Mux(wb_ctrl.rxs2 \|\| wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U), coreMonitorBundle.inst, coreMonitorBundle.inst) } } // CoreMonitorBundle for late latency writes val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen)) xrfWriteBundle.clock := clock xrfWriteBundle.reset := reset xrfWriteBundle.hartid := io.hartid xrfWriteBundle.timer := csr.io.time(31,0) xrfWriteBundle.valid := false.B xrfWriteBundle.pc := 0.U xrfWriteBundle.wrdst := rf_waddr xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr)) xrfWriteBundle.wrenf := false.B xrfWriteBundle.wrdata := rf_wdata xrfWriteBundle.rd0src := 0.U xrfWriteBundle.rd0val := 0.U xrfWriteBundle.rd1src := 0.U xrfWriteBundle.rd1val := 0.U xrfWriteBundle.inst := 0.U xrfWriteBundle.excpt := false.B xrfWriteBundle.priv_mode := csr.io.trace(0).priv if (rocketParams.haveSimTimeout) PlusArg.timeout( name = "max_core_cycles", docstring = "Kill the emulation after INT rdtime cycles. Off if 0." )(csr.io.time) } // leaving gated-clock domain val rocketImpl = withClock (gated_clock) { new RocketImpl } def checkExceptions(x: Seq[(Bool, UInt)]) = (WireInit(x.map(_._1).reduce(_\|\|_)), WireInit(PriorityMux(x))) def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = { for ((coverCause, label) <- coverCausesLabels) { property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_${label}") } } def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) = targets.map(h => h._1 && cond(h._2)).reduce(_\|\|_) def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else { // efficient means to compress 64-bit VA into vaddrBits+1 bits // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) val b = vaddrBitsExtended-1 val a = (a0 >> b).asSInt val msb = Mux(a === 0.S \|\| a === -1.S, ea(b), !ea(b-1)) Cat(msb, ea(b-1, 0)) } class Scoreboard(n: Int, zero: Boolean = false) { def set(en: Bool, addr: UInt): Unit = update(en, _next \| mask(en, addr)) def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr)) def read(addr: UInt): Bool = r(addr) def readBypassed(addr: UInt): Bool = _next(addr) private val _r = RegInit(0.U(n.W)) private val r = if (zero) (_r >> 1 << 1) else _r private var _next = r private var ens = false.B private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U) private def update(en: Bool, update: UInt) = { _next = update ens = ens \|\| en when (ens) { _r := _next } } } } class RegFile(n: Int, w: Int, zero: Boolean = false) { val rf = Mem(n, UInt(w.W)) private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0)) private val reads = ArrayBuffer[(UInt,UInt)]() private var canRead = true def read(addr: UInt) = { require(canRead) reads += addr -> Wire(UInt()) reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr)) reads.last._2 } def write(addr: UInt, data: UInt) = { canRead = false when (addr =/= 0.U) { access(addr) := data for ((raddr, rdata) <- reads) when (addr === raddr) { rdata := data } } } } object ImmGen { def apply(sel: UInt, inst: UInt) = { val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt) val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign) val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt) val b11 = Mux(sel === IMM_U \|\| sel === IMM_Z, 0.S, Mux(sel === IMM_UJ, inst(20).asSInt, Mux(sel === IMM_SB, inst(7).asSInt, sign))) val b10_5 = Mux(sel === IMM_U \|\| sel === IMM_Z, 0.U, inst(30,25)) val b4_1 = Mux(sel === IMM_U, 0.U, Mux(sel === IMM_S \|\| sel === IMM_SB, inst(11,8), Mux(sel === IMM_Z, inst(19,16), inst(24,21)))) val b0 = Mux(sel === IMM_S, inst(7), Mux(sel === IMM_I, inst(20), Mux(sel === IMM_Z, inst(15), 0.U))) Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out } File CSR.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.LinkedHashMap import Instructions._ import CustomInstructions._ class MStatus extends Bundle { // not truly part of mstatus, but convenient val debug = Bool() val cease = Bool() val wfi = Bool() val isa = UInt(32.W) val dprv = UInt(PRV.SZ.W) // effective prv for data accesses val dv = Bool() // effective v for data accesses val prv = UInt(PRV.SZ.W) val v = Bool() val sd = Bool() val zero2 = UInt(23.W) val mpv = Bool() val gva = Bool() val mbe = Bool() val sbe = Bool() val sxl = UInt(2.W) val uxl = UInt(2.W) val sd_rv32 = Bool() val zero1 = UInt(8.W) val tsr = Bool() val tw = Bool() val tvm = Bool() val mxr = Bool() val sum = Bool() val mprv = Bool() val xs = UInt(2.W) val fs = UInt(2.W) val mpp = UInt(2.W) val vs = UInt(2.W) val spp = UInt(1.W) val mpie = Bool() val ube = Bool() val spie = Bool() val upie = Bool() val mie = Bool() val hie = Bool() val sie = Bool() val uie = Bool() } class MNStatus extends Bundle { val mpp = UInt(2.W) val zero3 = UInt(3.W) val mpv = Bool() val zero2 = UInt(3.W) val mie = Bool() val zero1 = UInt(3.W) } class HStatus extends Bundle { val zero6 = UInt(30.W) val vsxl = UInt(2.W) val zero5 = UInt(9.W) val vtsr = Bool() val vtw = Bool() val vtvm = Bool() val zero3 = UInt(2.W) val vgein = UInt(6.W) val zero2 = UInt(2.W) val hu = Bool() val spvp = Bool() val spv = Bool() val gva = Bool() val vsbe = Bool() val zero1 = UInt(5.W) } class DCSR extends Bundle { val xdebugver = UInt(2.W) val zero4 = UInt(2.W) val zero3 = UInt(12.W) val ebreakm = Bool() val ebreakh = Bool() val ebreaks = Bool() val ebreaku = Bool() val zero2 = Bool() val stopcycle = Bool() val stoptime = Bool() val cause = UInt(3.W) val v = Bool() val zero1 = UInt(2.W) val step = Bool() val prv = UInt(PRV.SZ.W) } class MIP(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val lip = Vec(coreParams.nLocalInterrupts, Bool()) val zero1 = Bool() val debug = Bool() // keep in sync with CSR.debugIntCause val rocc = Bool() val sgeip = Bool() val meip = Bool() val vseip = Bool() val seip = Bool() val ueip = Bool() val mtip = Bool() val vstip = Bool() val stip = Bool() val utip = Bool() val msip = Bool() val vssip = Bool() val ssip = Bool() val usip = Bool() } class Envcfg extends Bundle { val stce = Bool() // only for menvcfg/henvcfg val pbmte = Bool() // only for menvcfg/henvcfg val zero54 = UInt(54.W) val cbze = Bool() val cbcfe = Bool() val cbie = UInt(2.W) val zero3 = UInt(3.W) val fiom = Bool() def write(wdata: UInt) { val new_envcfg = wdata.asTypeOf(new Envcfg) fiom := new_envcfg.fiom // only FIOM is writable currently } } class PTBR(implicit p: Parameters) extends CoreBundle()(p) { def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0) def pgLevelsToMode(i: Int) = (xLen, i) match { case (32, 2) => 1 case (64, x) if x >= 3 && x <= 6 => x + 5 } val (modeBits, maxASIdBits) = xLen match { case 32 => (1, 9) case 64 => (4, 16) } require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen) val mode = UInt(modeBits.W) val asid = UInt(maxASIdBits.W) val ppn = UInt((maxPAddrBits - pgIdxBits).W) } object PRV { val SZ = 2 val U = 0 val S = 1 val H = 2 val M = 3 } object CSR { // commands val SZ = 3 def X = BitPat.dontCare(SZ) def N = 0.U(SZ.W) def R = 2.U(SZ.W) def I = 4.U(SZ.W) def W = 5.U(SZ.W) def S = 6.U(SZ.W) def C = 7.U(SZ.W) // mask a CSR cmd with a valid bit def maskCmd(valid: Bool, cmd: UInt): UInt = { // all commands less than CSR.I are treated by CSRFile as NOPs cmd & ~Mux(valid, 0.U, CSR.I) } val ADDRSZ = 12 def modeLSB: Int = 8 def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ) def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB) def busErrorIntCause = 128 def debugIntCause = 14 // keep in sync with MIP.debug def debugTriggerCause = { val res = debugIntCause require(!(Causes.all contains res)) res } def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause def rnmiBEUCause = 12 val firstCtr = CSRs.cycle val firstCtrH = CSRs.cycleh val firstHPC = CSRs.hpmcounter3 val firstHPCH = CSRs.hpmcounter3h val firstHPE = CSRs.mhpmevent3 val firstMHPC = CSRs.mhpmcounter3 val firstMHPCH = CSRs.mhpmcounter3h val firstHPM = 3 val nCtr = 32 val nHPM = nCtr - firstHPM val hpmWidth = 40 val maxPMPs = 16 } class PerfCounterIO(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val eventSel = Output(UInt(xLen.W)) val inc = Input(UInt(log2Ceil(1+retireWidth).W)) } class TracedInstruction(implicit p: Parameters) extends CoreBundle { val valid = Bool() val iaddr = UInt(coreMaxAddrBits.W) val insn = UInt(iLen.W) val priv = UInt(3.W) val exception = Bool() val interrupt = Bool() val cause = UInt(xLen.W) val tval = UInt((coreMaxAddrBits max iLen).W) val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W)) } class TraceAux extends Bundle { val enable = Bool() val stall = Bool() } class CSRDecodeIO(implicit p: Parameters) extends CoreBundle { val inst = Input(UInt(iLen.W)) def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0) val fp_illegal = Output(Bool()) val vector_illegal = Output(Bool()) val fp_csr = Output(Bool()) val vector_csr = Output(Bool()) val rocc_illegal = Output(Bool()) val read_illegal = Output(Bool()) val write_illegal = Output(Bool()) val write_flush = Output(Bool()) val system_illegal = Output(Bool()) val virtual_access_illegal = Output(Bool()) val virtual_system_illegal = Output(Bool()) } class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val ungated_clock = Input(Clock()) val interrupts = Input(new CoreInterrupts(hasBeu)) val hartid = Input(UInt(hartIdLen.W)) val rw = new Bundle { val addr = Input(UInt(CSR.ADDRSZ.W)) val cmd = Input(Bits(CSR.SZ.W)) val rdata = Output(Bits(xLen.W)) val wdata = Input(Bits(xLen.W)) } val decode = Vec(decodeWidth, new CSRDecodeIO) val csr_stall = Output(Bool()) // stall retire for wfi val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall val eret = Output(Bool()) val singleStep = Output(Bool()) val status = Output(new MStatus()) val hstatus = Output(new HStatus()) val gstatus = Output(new MStatus()) val ptbr = Output(new PTBR()) val hgatp = Output(new PTBR()) val vsatp = Output(new PTBR()) val evec = Output(UInt(vaddrBitsExtended.W)) val exception = Input(Bool()) val retire = Input(UInt(log2Up(1+retireWidth).W)) val cause = Input(UInt(xLen.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val tval = Input(UInt(vaddrBitsExtended.W)) val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W)) val mhtinst_read_pseudo = Input(Bool()) val gva = Input(Bool()) val time = Output(UInt(xLen.W)) val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W))) val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool())) val rocc_interrupt = Input(Bool()) val interrupt = Output(Bool()) val interrupt_cause = Output(UInt(xLen.W)) val bp = Output(Vec(nBreakpoints, new BP)) val pmp = Output(Vec(nPMPs, new PMP)) val counters = Vec(nPerfCounters, new PerfCounterIO) val csrw_counter = Output(UInt(CSR.nCtr.W)) val inhibit_cycle = Output(Bool()) val inst = Input(Vec(retireWidth, UInt(iLen.W))) val trace = Output(Vec(retireWidth, new TracedInstruction)) val mcontext = Output(UInt(coreParams.mcontextWidth.W)) val scontext = Output(UInt(coreParams.scontextWidth.W)) val fiom = Output(Bool()) val vector = usingVector.option(new Bundle { val vconfig = Output(new VConfig()) val vstart = Output(UInt(maxVLMax.log2.W)) val vxrm = Output(UInt(2.W)) val set_vs_dirty = Input(Bool()) val set_vconfig = Flipped(Valid(new VConfig)) val set_vstart = Flipped(Valid(vstart)) val set_vxsat = Input(Bool()) }) } class VConfig(implicit p: Parameters) extends CoreBundle { val vl = UInt((maxVLMax.log2 + 1).W) val vtype = new VType } object VType { def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = { val res = 0.U.asTypeOf(new VType) val in = that.asTypeOf(res) val vill = (in.max_vsew.U < in.vsew) \|\| !in.lmul_ok \|\| in.reserved =/= 0.U \|\| in.vill when (!vill \|\| ignore_vill.B) { res := in res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0) } res.reserved := 0.U res.vill := vill res } def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt = VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero) } class VType(implicit p: Parameters) extends CoreBundle { val vill = Bool() val reserved = UInt((xLen - 9).W) val vma = Bool() val vta = Bool() val vsew = UInt(3.W) val vlmul_sign = Bool() val vlmul_mag = UInt(2.W) def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt @deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9") def vlmul: UInt = vlmul_mag def max_vsew = log2Ceil(eLen/8) def max_vlmul = (1 << vlmul_mag.getWidth) - 1 def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B) def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1 def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U) def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = { val atLeastMaxVLMax = useMax \|\| Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U) val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0) val atLeastVLMax = atLeastMaxVLMax \|\| (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR val isZero = vill \|\| useZero Mux(!isZero && atLeastVLMax, vlMax, 0.U) \| Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U) } } class CSRFile( perfEventSets: EventSets = new EventSets(Seq()), customCSRs: Seq[CustomCSR] = Nil, roccCSRs: Seq[CustomCSR] = Nil, hasBeu: Boolean = false)(implicit p: Parameters) extends CoreModule()(p) with HasCoreParameters { val io = IO(new CSRFileIO(hasBeu) { val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO) val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO) }) io.rw_stall := false.B val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := PRV.M.U reset_mstatus.prv := PRV.M.U reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U) val reg_mstatus = RegInit(reset_mstatus) val new_prv = WireDefault(reg_mstatus.prv) reg_mstatus.prv := legalizePrivilege(new_prv) val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR())) reset_dcsr.xdebugver := 1.U reset_dcsr.prv := PRV.M.U val reg_dcsr = RegInit(reset_dcsr) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) sup.usip := false.B sup.ssip := usingSupervisor.B sup.vssip := usingHypervisor.B sup.msip := true.B sup.utip := false.B sup.stip := usingSupervisor.B sup.vstip := usingHypervisor.B sup.mtip := true.B sup.ueip := false.B sup.seip := usingSupervisor.B sup.vseip := usingHypervisor.B sup.meip := true.B sup.sgeip := false.B sup.rocc := usingRoCC.B sup.debug := false.B sup.zero1 := false.B sup.lip foreach { _ := true.B } val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U val del = WireDefault(sup) del.msip := false.B del.mtip := false.B del.meip := false.B (sup.asUInt \| supported_high_interrupts, del.asUInt) } val delegable_base_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_page_fault, Causes.breakpoint, Causes.load_page_fault, Causes.store_page_fault, Causes.misaligned_load, Causes.misaligned_store, Causes.illegal_instruction, Causes.user_ecall, ) val delegable_hypervisor_exceptions = Seq( Causes.virtual_supervisor_ecall, Causes.fetch_guest_page_fault, Causes.load_guest_page_fault, Causes.virtual_instruction, Causes.store_guest_page_fault, ) val delegable_exceptions = ( delegable_base_exceptions ++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq()) ).map(1 << _).sum.U val hs_delegable_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_access, Causes.illegal_instruction, Causes.breakpoint, Causes.misaligned_load, Causes.load_access, Causes.misaligned_store, Causes.store_access, Causes.user_ecall, Causes.fetch_page_fault, Causes.load_page_fault, Causes.store_page_fault).map(1 << _).sum.U val (hs_delegable_interrupts, mideleg_always_hs) = { val always = WireDefault(0.U.asTypeOf(new MIP())) always.vssip := usingHypervisor.B always.vstip := usingHypervisor.B always.vseip := usingHypervisor.B val deleg = WireDefault(always) deleg.lip.foreach { _ := usingHypervisor.B } (deleg.asUInt, always.asUInt) } val reg_debug = RegInit(false.B) val reg_dpc = Reg(UInt(vaddrBitsExtended.W)) val reg_dscratch0 = Reg(UInt(xLen.W)) val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W))) val reg_singleStepped = Reg(Bool()) val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W))) val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W))) val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W)) val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP)) val reg_pmp = Reg(Vec(nPMPs, new PMPReg)) val reg_mie = Reg(UInt(xLen.W)) val (reg_mideleg, read_mideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_interrupts \| mideleg_always_hs, 0.U)) } val (reg_medeleg, read_medeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U)) } val reg_mip = Reg(new MIP) val reg_mepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mcause = RegInit(0.U(xLen.W)) val reg_mtval = Reg(UInt(vaddrBitsExtended.W)) val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W)) val reg_mscratch = Reg(Bits(xLen.W)) val mtvecWidth = paddrBits min xLen val reg_mtvec = mtvecInit match { case Some(addr) => RegInit(addr.U(mtvecWidth.W)) case None => Reg(UInt(mtvecWidth.W)) } val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus())) reset_mnstatus.mpp := PRV.M.U val reg_mnscratch = Reg(Bits(xLen.W)) val reg_mnepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mncause = RegInit(0.U(xLen.W)) val reg_mnstatus = RegInit(reset_mnstatus) val reg_rnmie = RegInit(true.B) val nmie = reg_rnmie val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U val (reg_mcounteren, read_mcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingUser.B, reg & delegable_counters, 0.U)) } val (reg_scounteren, read_scounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U)) } val (reg_hideleg, read_hideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U)) } val (reg_hedeleg, read_hedeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U)) } val hs_delegable_counters = delegable_counters val (reg_hcounteren, read_hcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U)) } val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus)) val reg_hgatp = Reg(new PTBR) val reg_htval = Reg(reg_mtval2.cloneType) val read_hvip = reg_mip.asUInt & hs_delegable_interrupts val read_hie = reg_mie & hs_delegable_interrupts val (reg_vstvec, read_vstvec) = { val reg = Reg(UInt(vaddrBitsExtended.W)) (reg, formTVec(reg).sextTo(xLen)) } val reg_vsstatus = Reg(new MStatus) val reg_vsscratch = Reg(Bits(xLen.W)) val reg_vsepc = Reg(UInt(vaddrBitsExtended.W)) val reg_vscause = Reg(Bits(xLen.W)) val reg_vstval = Reg(UInt(vaddrBitsExtended.W)) val reg_vsatp = Reg(new PTBR) val reg_sepc = Reg(UInt(vaddrBitsExtended.W)) val reg_scause = Reg(Bits(xLen.W)) val reg_stval = Reg(UInt(vaddrBitsExtended.W)) val reg_sscratch = Reg(Bits(xLen.W)) val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W)) val reg_satp = Reg(new PTBR) val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) } val reg_fflags = Reg(UInt(5.W)) val reg_frm = Reg(UInt(3.W)) val reg_vconfig = usingVector.option(Reg(new VConfig)) val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W))) val reg_vxsat = usingVector.option(Reg(Bool())) val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W))) val reg_mtinst_read_pseudo = Reg(Bool()) val reg_htinst_read_pseudo = Reg(Bool()) // XLEN=32: 0x00002000 // XLEN=64: 0x00003000 val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W))) val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W)) io.inhibit_cycle := reg_mcountinhibit(0) val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2)) val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0)) else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) } val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W))) (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e } val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) => WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) } val mip = WireDefault(reg_mip) mip.lip := (io.interrupts.lip: Seq[Bool]) mip.mtip := io.interrupts.mtip mip.msip := io.interrupts.msip mip.meip := io.interrupts.meip // seip is the OR of reg_mip.seip and the actual line from the PLIC io.interrupts.seip.foreach { mip.seip := reg_mip.seip \|\| _ } // Simimlar sort of thing would apply if the PLIC had a VSEIP line: //io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip \|\| _ } mip.rocc := io.rocc_interrupt val read_mip = mip.asUInt & supported_interrupts val read_hip = read_mip & hs_delegable_interrupts val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U)) val pending_interrupts = high_interrupts \| (read_mip & reg_mie) val d_interrupts = io.interrupts.debug << CSR.debugIntCause val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi => (((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) \| io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U), !io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B) val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U \|\| reg_mstatus.mie), ~(~pending_interrupts \| read_mideleg), 0.U) val s_interrupts = Mux(nmie && (reg_mstatus.v \|\| reg_mstatus.prv < PRV.S.U \|\| (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U) val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U \|\| reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U) val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts)) val interruptMSB = BigInt(1) << (xLen-1) val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt io.interrupt := (anyInterrupt && !io.singleStep \|\| reg_singleStepped) && !(reg_debug \|\| io.status.cease) io.interrupt_cause := interruptCause io.bp := reg_bp take nBreakpoints io.mcontext := reg_mcontext.getOrElse(0.U) io.scontext := reg_scontext.getOrElse(0.U) io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) \|\| (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) \|\| (reg_mstatus.v && reg_henvcfg.fiom) io.pmp := reg_pmp.map(PMP(_)) val isaMaskString = (if (usingMulDiv) "M" else "") + (if (usingAtomics) "A" else "") + (if (fLen >= 32) "F" else "") + (if (fLen >= 64) "D" else "") + (if (coreParams.hasV) "V" else "") + (if (usingCompressed) "C" else "") val isaString = (if (coreParams.useRVE) "E" else "I") + isaMaskString + (if (customIsaExt.isDefined \|\| usingRoCC) "X" else "") + (if (usingSupervisor) "S" else "") + (if (usingHypervisor) "H" else "") + (if (usingUser) "U" else "") val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) \| isaStringToMask(isaString) val reg_misa = RegInit(isaMax.U) val read_mstatus = io.status.asUInt.extract(xLen-1,0) val read_mtvec = formTVec(reg_mtvec).padTo(xLen) val read_stvec = formTVec(reg_stvec).sextTo(xLen) val read_mapping = LinkedHashMap[Int,Bits]( CSRs.tselect -> reg_tselect, CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt, CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen), CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt, CSRs.misa -> reg_misa, CSRs.mstatus -> read_mstatus, CSRs.mtvec -> read_mtvec, CSRs.mip -> read_mip, CSRs.mie -> reg_mie, CSRs.mscratch -> reg_mscratch, CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen), CSRs.mtval -> reg_mtval.sextTo(xLen), CSRs.mcause -> reg_mcause, CSRs.mhartid -> io.hartid) val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.dcsr -> reg_dcsr.asUInt, CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen), CSRs.dscratch0 -> reg_dscratch0.asUInt) ++ reg_dscratch1.map(r => CSRs.dscratch1 -> r) val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus())) read_mnstatus.mpp := reg_mnstatus.mpp read_mnstatus.mpv := reg_mnstatus.mpv read_mnstatus.mie := reg_rnmie val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits]( CustomCSRs.mnscratch -> reg_mnscratch, CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen), CustomCSRs.mncause -> reg_mncause, CustomCSRs.mnstatus -> read_mnstatus.asUInt) val context_csrs = LinkedHashMap[Int,Bits]() ++ reg_mcontext.map(r => CSRs.mcontext -> r) ++ reg_scontext.map(r => CSRs.scontext -> r) val read_fcsr = Cat(reg_frm, reg_fflags) val fp_csrs = LinkedHashMap[Int,Bits]() ++ usingFPU.option(CSRs.fflags -> reg_fflags) ++ usingFPU.option(CSRs.frm -> reg_frm) ++ (usingFPU \|\| usingVector).option(CSRs.fcsr -> read_fcsr) val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U)) val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.vxsat -> reg_vxsat.get, CSRs.vxrm -> reg_vxrm.get, CSRs.vcsr -> read_vcsr, CSRs.vstart -> reg_vstart.get, CSRs.vtype -> reg_vconfig.get.vtype.asUInt, CSRs.vl -> reg_vconfig.get.vl, CSRs.vlenb -> (vLen / 8).U) read_mapping ++= debug_csrs read_mapping ++= nmi_csrs read_mapping ++= context_csrs read_mapping ++= fp_csrs read_mapping ++= vector_csrs if (coreParams.haveBasicCounters) { read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit read_mapping += CSRs.mcycle -> reg_cycle read_mapping += CSRs.minstret -> reg_instret for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U) zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) { read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN if (xLen == 32) { read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh } } if (usingUser) { read_mapping += CSRs.mcounteren -> read_mcounteren } read_mapping += CSRs.cycle -> reg_cycle read_mapping += CSRs.instret -> reg_instret if (xLen == 32) { read_mapping += CSRs.mcycleh -> (reg_cycle >> 32) read_mapping += CSRs.minstreth -> (reg_instret >> 32) read_mapping += CSRs.cycleh -> (reg_cycle >> 32) read_mapping += CSRs.instreth -> (reg_instret >> 32) } } if (usingUser) { read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt if (xLen == 32) read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32) } val sie_mask = { val sgeip_mask = WireInit(0.U.asTypeOf(new MIP)) sgeip_mask.sgeip := true.B read_mideleg & ~(hs_delegable_interrupts \| sgeip_mask.asUInt) } if (usingSupervisor) { val read_sie = reg_mie & sie_mask val read_sip = read_mip & sie_mask val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus)) read_sstatus.sd := io.status.sd read_sstatus.uxl := io.status.uxl read_sstatus.sd_rv32 := io.status.sd_rv32 read_sstatus.mxr := io.status.mxr read_sstatus.sum := io.status.sum read_sstatus.xs := io.status.xs read_sstatus.fs := io.status.fs read_sstatus.vs := io.status.vs read_sstatus.spp := io.status.spp read_sstatus.spie := io.status.spie read_sstatus.sie := io.status.sie read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0) read_mapping += CSRs.sip -> read_sip.asUInt read_mapping += CSRs.sie -> read_sie.asUInt read_mapping += CSRs.sscratch -> reg_sscratch read_mapping += CSRs.scause -> reg_scause read_mapping += CSRs.stval -> reg_stval.sextTo(xLen) read_mapping += CSRs.satp -> reg_satp.asUInt read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen) read_mapping += CSRs.stvec -> read_stvec read_mapping += CSRs.scounteren -> read_scounteren read_mapping += CSRs.mideleg -> read_mideleg read_mapping += CSRs.medeleg -> read_medeleg read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt } val pmpCfgPerCSR = xLen / new PMPConfig().getWidth def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR) if (reg_pmp.nonEmpty) { require(reg_pmp.size <= CSR.maxPMPs) val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP)) for (i <- 0 until read_pmp.size by pmpCfgPerCSR) read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt for ((pmp, i) <- read_pmp.zipWithIndex) read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr } // implementation-defined CSRs def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = { require(csr.mask >= 0 && csr.mask.bitLength <= xLen) require(!read_mapping.contains(csr.id)) val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W))) val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U csr_io.ren := read when (read && csr_io.stall) { io.rw_stall := true.B } read_mapping += csr.id -> reg reg } val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2)) val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2)) if (usingHypervisor) { read_mapping += CSRs.mtinst -> read_mtinst read_mapping += CSRs.mtval2 -> reg_mtval2 val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.hstatus -> read_hstatus read_mapping += CSRs.hedeleg -> read_hedeleg read_mapping += CSRs.hideleg -> read_hideleg read_mapping += CSRs.hcounteren-> read_hcounteren read_mapping += CSRs.hgatp -> reg_hgatp.asUInt read_mapping += CSRs.hip -> read_hip read_mapping += CSRs.hie -> read_hie read_mapping += CSRs.hvip -> read_hvip read_mapping += CSRs.hgeie -> 0.U read_mapping += CSRs.hgeip -> 0.U read_mapping += CSRs.htval -> reg_htval read_mapping += CSRs.htinst -> read_htinst read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt if (xLen == 32) read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32) val read_vsie = (read_hie & read_hideleg) >> 1 val read_vsip = (read_hip & read_hideleg) >> 1 val read_vsepc = readEPC(reg_vsepc).sextTo(xLen) val read_vstval = reg_vstval.sextTo(xLen) val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.vsstatus -> read_vsstatus read_mapping += CSRs.vsip -> read_vsip read_mapping += CSRs.vsie -> read_vsie read_mapping += CSRs.vsscratch -> reg_vsscratch read_mapping += CSRs.vscause -> reg_vscause read_mapping += CSRs.vstval -> read_vstval read_mapping += CSRs.vsatp -> reg_vsatp.asUInt read_mapping += CSRs.vsepc -> read_vsepc read_mapping += CSRs.vstvec -> read_vstvec } // mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U)) val decoded_addr = { val addr = Cat(io.status.v, io.rw.addr) val pats = for (((k, _), i) <- read_mapping.zipWithIndex) yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B))) val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats) val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap for ((k, v) <- unvirtualized_mapping) yield k -> { val alt: Option[Bool] = CSR.mode(k) match { // hcontext was assigned an unfortunate address; it lives where a // hypothetical vscontext will live. Exclude them from the S/VS remapping. // (on separate lines so scala-lint doesnt do something stupid) case _ if k == CSRs.scontext => None case _ if k == CSRs.hcontext => None // When V=1, if a corresponding VS CSR exists, access it instead... case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB)) // ...and don't access the original S-mode version. case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B) case _ => None } alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v) } } val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata) val system_insn = io.rw.cmd === CSR.I val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU) val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N), EBREAK-> List(N,Y,N,N,N,N,N,N,N), MRET-> List(N,N,Y,N,N,N,N,N,N), CEASE-> List(N,N,N,Y,N,N,N,N,N), WFI-> List(N,N,N,N,Y,N,N,N,N)) ++ usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++ coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++ usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++ usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++ usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++ (if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq()) val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = { val insn = ECALL.value.U \| (io.rw.addr << 20) DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool) } for (io_dec <- io.decode) { val addr = io_dec.inst(31, 20) def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_\|\|_) def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U)) val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil = DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool) val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) \|\| addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U)) val allow_wfi = (!usingSupervisor).B \|\| reg_mstatus.prv > PRV.S.U \|\| !reg_mstatus.tw && (!reg_mstatus.v \|\| !reg_hstatus.vtw) val allow_sfence_vma = (!usingVM).B \|\| reg_mstatus.prv > PRV.S.U \|\| !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) val allow_hfence_vvma = (!usingHypervisor).B \|\| !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U) val allow_hlsv = (!usingHypervisor).B \|\| !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U \|\| reg_hstatus.hu) val allow_sret = (!usingSupervisor).B \|\| reg_mstatus.prv > PRV.S.U \|\| !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0) val allow_counter = (reg_mstatus.prv > PRV.S.U \|\| read_mcounteren(counter_addr)) && (!usingSupervisor.B \|\| reg_mstatus.prv >= PRV.S.U \|\| read_scounteren(counter_addr)) && (!usingHypervisor.B \|\| !reg_mstatus.v \|\| read_hcounteren(counter_addr)) io_dec.fp_illegal := io.status.fs === 0.U \|\| reg_mstatus.v && reg_vsstatus.fs === 0.U \|\| !reg_misa('f'-'a') io_dec.vector_illegal := io.status.vs === 0.U \|\| reg_mstatus.v && reg_vsstatus.vs === 0.U \|\| !reg_misa('v'-'a') io_dec.fp_csr := decodeFast(fp_csrs.keys.toList) io_dec.vector_csr := decodeFast(vector_csrs.keys.toList) io_dec.rocc_illegal := io.status.xs === 0.U \|\| reg_mstatus.v && reg_vsstatus.xs === 0.U \|\| !reg_misa('x'-'a') val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) \|\| usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U val csr_exists = decodeAny(read_mapping) io_dec.read_illegal := !csr_addr_legal \|\| !csr_exists \|\| ((addr === CSRs.satp.U \|\| addr === CSRs.hgatp.U) && !allow_sfence_vma) \|\| is_counter && !allow_counter \|\| decodeFast(debug_csrs.keys.toList) && !reg_debug \|\| decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal \|\| io_dec.fp_csr && io_dec.fp_illegal io_dec.write_illegal := addr(11,10).andR io_dec.write_flush := { val addr_m = addr \| (PRV.M.U << CSR.modeLSB) !(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U) } io_dec.system_illegal := !csr_addr_legal && !is_hlsv \|\| is_wfi && !allow_wfi \|\| is_ret && !allow_sret \|\| is_ret && addr(10) && addr(7) && !reg_debug \|\| (is_sfence \|\| is_hfence_gvma) && !allow_sfence_vma \|\| is_hfence_vvma && !allow_hfence_vvma \|\| is_hlsv && !allow_hlsv io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && ( CSR.mode(addr) === PRV.H.U \|\| is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) \|\| !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) \|\| CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) \|\| addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm) io_dec.virtual_system_illegal := reg_mstatus.v && ( is_hfence_vvma \|\| is_hfence_gvma \|\| is_hlsv \|\| is_wfi && (!reg_mstatus.prv(0) \|\| !reg_mstatus.tw && reg_hstatus.vtw) \|\| is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) \|\| reg_hstatus.vtsr) \|\| is_sfence && (!reg_mstatus.prv(0) \|\| reg_hstatus.vtvm)) } val cause = Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv), Mux[UInt](insn_break, Causes.breakpoint.U, io.cause)) val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0) val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0) val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv) val trapToDebug = usingDebug.B && (reg_singleStepped \|\| causeIsDebugInt \|\| causeIsDebugTrigger \|\| causeIsDebugBreak \|\| reg_debug) val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800)) val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808)) val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U) val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs)) val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs)) def mtvecBaseAlign = 2 def mtvecInterruptAlign = { require(reg_mip.getWidth <= xLen) log2Ceil(xLen) } val notDebugTVec = { val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec) val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset) val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign) } val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U \|\| cause_lsbs === CSR.rnmiBEUCause.U) val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U val causeIsNmi = causeIsRnmiInt val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U) val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U) val trapToNmiInt = usingNMI.B && causeIsNmi val trapToNmiXcpt = usingNMI.B && !nmie val trapToNmi = trapToNmiInt \|\| trapToNmiXcpt val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1 val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec)) io.evec := tvec io.ptbr := reg_satp io.hgatp := reg_hgatp io.vsatp := reg_vsatp io.eret := insn_call \|\| insn_break \|\| insn_ret io.singleStep := reg_dcsr.step && !reg_debug io.status := reg_mstatus io.status.sd := io.status.fs.andR \|\| io.status.xs.andR \|\| io.status.vs.andR io.status.debug := reg_debug io.status.isa := reg_misa io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv) io.status.dv := reg_mstatus.v \|\| Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B) io.status.sd_rv32 := (xLen == 32).B && io.status.sd io.status.mpv := reg_mstatus.mpv io.status.gva := reg_mstatus.gva io.hstatus := reg_hstatus io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.gstatus := reg_vsstatus io.gstatus.sd := io.gstatus.fs.andR \|\| io.gstatus.xs.andR \|\| io.gstatus.vs.andR io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd val exception = insn_call \|\| insn_break \|\| io.exception assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive") when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B } when (pending_interrupts.orR \|\| io.interrupts.debug \|\| exception) { reg_wfi := false.B } io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } ) when (io.retire(0) \|\| exception) { reg_singleStepped := true.B } when (!io.singleStep) { reg_singleStepped := false.B } assert(!io.singleStep \|\| io.retire <= 1.U) assert(!reg_singleStepped \|\| io.retire === 0.U) val epc = formEPC(io.pc) val tval = Mux(insn_break, epc, io.tval) when (exception) { when (trapToDebug) { when (!reg_debug) { reg_mstatus.v := false.B reg_debug := true.B reg_dpc := epc reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U))) reg_dcsr.prv := trimPrivilege(reg_mstatus.prv) reg_dcsr.v := reg_mstatus.v new_prv := PRV.M.U } }.elsewhen (trapToNmiInt) { when (reg_rnmie) { reg_mstatus.v := false.B reg_mnstatus.mpv := reg_mstatus.v reg_rnmie := false.B reg_mnepc := epc reg_mncause := (BigInt(1) << (xLen-1)).U \| Mux(causeIsRnmiBEU, 3.U, 2.U) reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv) new_prv := PRV.M.U } }.elsewhen (delegateVS && nmie) { reg_mstatus.v := true.B reg_vsstatus.spp := reg_mstatus.prv reg_vsepc := epc reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause) reg_vstval := tval reg_vsstatus.spie := reg_vsstatus.sie reg_vsstatus.sie := false.B new_prv := PRV.S.U }.elsewhen (delegate && nmie) { reg_mstatus.v := false.B reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp) reg_hstatus.gva := io.gva reg_hstatus.spv := reg_mstatus.v reg_sepc := epc reg_scause := cause reg_stval := tval reg_htval := io.htval reg_htinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.spie := reg_mstatus.sie reg_mstatus.spp := reg_mstatus.prv reg_mstatus.sie := false.B new_prv := PRV.S.U }.otherwise { reg_mstatus.v := false.B reg_mstatus.mpv := reg_mstatus.v reg_mstatus.gva := io.gva reg_mepc := epc reg_mcause := cause reg_mtval := tval reg_mtval2 := io.htval reg_mtinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.mpie := reg_mstatus.mie reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv) reg_mstatus.mie := false.B new_prv := PRV.M.U } } for (i <- 0 until supported_interrupts.getWidth) { val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"INTERRUPT_M_$i") property.cover(en && delegable && delegate, s"INTERRUPT_S_$i") } for (i <- 0 until xLen) { val supported_exceptions: BigInt = 0x8fe \| (if (usingCompressed && !coreParams.misaWritable) 0 else 1) \| (if (usingUser) 0x100 else 0) \| (if (usingSupervisor) 0x200 else 0) \| (if (usingVM) 0xb000 else 0) if (((supported_exceptions >> i) & 1) != 0) { val en = exception && cause === i.U val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"EXCEPTION_M_$i") property.cover(en && delegable && delegate, s"EXCEPTION_S_$i") } } when (insn_ret) { val ret_prv = WireInit(UInt(), DontCare) when (usingSupervisor.B && !io.rw.addr(9)) { when (!reg_mstatus.v) { reg_mstatus.sie := reg_mstatus.spie reg_mstatus.spie := true.B reg_mstatus.spp := PRV.U.U ret_prv := reg_mstatus.spp reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv io.evec := readEPC(reg_sepc) reg_hstatus.spv := false.B }.otherwise { reg_vsstatus.sie := reg_vsstatus.spie reg_vsstatus.spie := true.B reg_vsstatus.spp := PRV.U.U ret_prv := reg_vsstatus.spp reg_mstatus.v := usingHypervisor.B io.evec := readEPC(reg_vsepc) } }.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) { ret_prv := reg_dcsr.prv reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U reg_debug := false.B io.evec := readEPC(reg_dpc) }.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) { ret_prv := reg_mnstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U reg_rnmie := true.B io.evec := readEPC(reg_mnepc) }.otherwise { reg_mstatus.mie := reg_mstatus.mpie reg_mstatus.mpie := true.B reg_mstatus.mpp := legalizePrivilege(PRV.U.U) reg_mstatus.mpv := false.B ret_prv := reg_mstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U io.evec := readEPC(reg_mepc) } new_prv := ret_prv when (usingUser.B && ret_prv <= PRV.S.U) { reg_mstatus.mprv := false.B } } io.time := reg_cycle io.csr_stall := reg_wfi \|\| io.status.cease io.status.cease := RegEnable(true.B, false.B, insn_cease) io.status.wfi := reg_wfi for ((io, reg) <- io.customCSRs zip reg_custom) { io.wen := false.B io.wdata := wdata io.value := reg } for ((io, reg) <- io.roccCSRs zip reg_rocc) { io.wen := false.B io.wdata := wdata io.value := reg } io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) // cover access to register val coverable_counters = read_mapping.filterNot { case (k, _) => k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM } coverable_counters.foreach( {case (k, v) => { when (!k.U(11,10).andR) { // Cover points for RW CSR registers property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } .otherwise { // Cover points for RO CSR registers property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } }}) val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B)) io.vector.foreach { vio => when (set_vs_dirty) { assert(reg_mstatus.vs > 0.U) when (reg_mstatus.v) { reg_vsstatus.vs := 3.U } reg_mstatus.vs := 3.U } } val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B)) if (coreParams.haveFSDirty) { when (set_fs_dirty) { assert(reg_mstatus.fs > 0.U) when (reg_mstatus.v) { reg_vsstatus.fs := 3.U } reg_mstatus.fs := 3.U } } io.fcsr_rm := reg_frm when (io.fcsr_flags.valid) { reg_fflags := reg_fflags \| io.fcsr_flags.bits set_fs_dirty := true.B } io.vector.foreach { vio => when (vio.set_vxsat) { reg_vxsat.get := true.B set_vs_dirty := true.B } } val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) \|\| io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U) when (csr_wen) { val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB / val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_)) when (decoded_addr(CSRs.mstatus)) { val new_mstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.mie := new_mstatus.mie reg_mstatus.mpie := new_mstatus.mpie if (usingUser) { reg_mstatus.mprv := new_mstatus.mprv reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp) if (usingSupervisor) { reg_mstatus.spp := new_mstatus.spp reg_mstatus.spie := new_mstatus.spie reg_mstatus.sie := new_mstatus.sie reg_mstatus.tw := new_mstatus.tw reg_mstatus.tsr := new_mstatus.tsr } if (usingVM) { reg_mstatus.mxr := new_mstatus.mxr reg_mstatus.sum := new_mstatus.sum reg_mstatus.tvm := new_mstatus.tvm } if (usingHypervisor) { reg_mstatus.mpv := new_mstatus.mpv reg_mstatus.gva := new_mstatus.gva } } if (usingSupervisor \|\| usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs) reg_mstatus.vs := formVS(new_mstatus.vs) } when (decoded_addr(CSRs.misa)) { val mask = isaStringToMask(isaMaskString).U(xLen.W) val f = wdata('f' - 'a') // suppress write if it would cause the next fetch to be misaligned when (!usingCompressed.B \|\| !io.pc(1) \|\| wdata('c' - 'a')) { if (coreParams.misaWritable) reg_misa := ~(~wdata \| (!f << ('d' - 'a'))) & mask \| reg_misa & ~mask } } when (decoded_addr(CSRs.mip)) { // MIP should be modified based on the value in reg_mip, not the value // in read_mip, since read_mip.seip is the OR of reg_mip.seip and // io.interrupts.seip. We don't want the value on the PLIC line to // inadvertently be OR'd into read_mip.seip. val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP) if (usingSupervisor) { reg_mip.ssip := new_mip.ssip reg_mip.stip := new_mip.stip reg_mip.seip := new_mip.seip } if (usingHypervisor) { reg_mip.vssip := new_mip.vssip } } when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts } when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) } when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata } if (mtvecWritable) when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata } when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U } when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata } if (usingNMI) { val new_mnstatus = wdata.asTypeOf(new MNStatus()) when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata } when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) } when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U } when (decoded_addr(CustomCSRs.mnstatus)) { reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp) reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv reg_rnmie := reg_rnmie \| new_mnstatus.mie // mnie bit settable but not clearable from software } } for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) { writeCounter(i + CSR.firstMHPC, c, wdata) when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) } } if (coreParams.haveBasicCounters) { when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero writeCounter(CSRs.mcycle, reg_cycle, wdata) writeCounter(CSRs.minstret, reg_instret, wdata) } if (usingFPU) { when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata } when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata } when (decoded_addr(CSRs.fcsr)) { set_fs_dirty := true.B reg_fflags := wdata reg_frm := wdata >> reg_fflags.getWidth } } if (usingDebug) { when (decoded_addr(CSRs.dcsr)) { val new_dcsr = wdata.asTypeOf(new DCSR()) reg_dcsr.step := new_dcsr.step reg_dcsr.ebreakm := new_dcsr.ebreakm if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv) if (usingHypervisor) reg_dcsr.v := new_dcsr.v } when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) } when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata } reg_dscratch1.foreach { r => when (decoded_addr(CSRs.dscratch1)) { r := wdata } } } if (usingSupervisor) { when (decoded_addr(CSRs.sstatus)) { val new_sstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.sie := new_sstatus.sie reg_mstatus.spie := new_sstatus.spie reg_mstatus.spp := new_sstatus.spp reg_mstatus.fs := formFS(new_sstatus.fs) reg_mstatus.vs := formVS(new_sstatus.vs) if (usingVM) { reg_mstatus.mxr := new_sstatus.mxr reg_mstatus.sum := new_sstatus.sum } } when (decoded_addr(CSRs.sip)) { val new_sip = ((read_mip & ~read_mideleg) \| (wdata & read_mideleg)).asTypeOf(new MIP()) reg_mip.ssip := new_sip.ssip } when (decoded_addr(CSRs.satp)) { if (usingVM) { val new_satp = wdata.asTypeOf(new PTBR()) when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) { reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_\|_).U reg_satp.ppn := new_satp.ppn(ppnBits-1,0) if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0) } } } when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) \| (wdata & sie_mask) } when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata } when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) } when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata } when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask } when (decoded_addr(CSRs.stval)) { reg_stval := wdata } when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata } when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata } when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata } when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) } } if (usingHypervisor) { when (decoded_addr(CSRs.hstatus)) { val new_hstatus = wdata.asTypeOf(new HStatus()) reg_hstatus.gva := new_hstatus.gva reg_hstatus.spv := new_hstatus.spv reg_hstatus.spvp := new_hstatus.spvp reg_hstatus.hu := new_hstatus.hu reg_hstatus.vtvm := new_hstatus.vtvm reg_hstatus.vtw := new_hstatus.vtw reg_hstatus.vtsr := new_hstatus.vtsr reg_hstatus.vsxl := new_hstatus.vsxl } when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata } when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata } when (decoded_addr(CSRs.hgatp)) { val new_hgatp = wdata.asTypeOf(new PTBR()) val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_)) when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) { reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_\|_).U } reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W)) if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0) } when (decoded_addr(CSRs.hip)) { val new_hip = ((read_mip & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_hip.vssip } when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts) } when (decoded_addr(CSRs.hvip)) { val new_sip = ((read_mip & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_sip.vssip reg_mip.vstip := new_sip.vstip reg_mip.vseip := new_sip.vseip } when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata } when (decoded_addr(CSRs.htval)) { reg_htval := wdata } when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata } val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12)) when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo } when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo } when (decoded_addr(CSRs.vsstatus)) { val new_vsstatus = wdata.asTypeOf(new MStatus()) reg_vsstatus.sie := new_vsstatus.sie reg_vsstatus.spie := new_vsstatus.spie reg_vsstatus.spp := new_vsstatus.spp reg_vsstatus.mxr := new_vsstatus.mxr reg_vsstatus.sum := new_vsstatus.sum reg_vsstatus.fs := formFS(new_vsstatus.fs) reg_vsstatus.vs := formVS(new_vsstatus.vs) } when (decoded_addr(CSRs.vsip)) { val new_vsip = ((read_hip & ~read_hideleg) \| ((wdata << 1) & read_hideleg)).asTypeOf(new MIP()) reg_mip.vssip := new_vsip.vssip } when (decoded_addr(CSRs.vsatp)) { val new_vsatp = wdata.asTypeOf(new PTBR()) val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U)) when (mode_ok) { reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_\|_).U } when (mode_ok \|\| !reg_mstatus.v) { reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0) if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0) } } when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) \| ((wdata << 1) & read_hideleg) } when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata } when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) } when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata } when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask } when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata } when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) } } if (usingUser) { when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata } when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) } } if (nBreakpoints > 0) { when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata } for ((bp, i) <- reg_bp.zipWithIndex) { when (i.U === reg_tselect && (!bp.control.dmode \|\| reg_debug)) { when (decoded_addr(CSRs.tdata2)) { bp.address := wdata } when (decoded_addr(CSRs.tdata3)) { if (coreParams.mcontextWidth > 0) { bp.textra.mselect := wdata(bp.textra.mselectPos) bp.textra.mvalue := wdata >> bp.textra.mvaluePos } if (coreParams.scontextWidth > 0) { bp.textra.sselect := wdata(bp.textra.sselectPos) bp.textra.svalue := wdata >> bp.textra.svaluePos } } when (decoded_addr(CSRs.tdata1)) { bp.control := wdata.asTypeOf(bp.control) val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control) val dMode = newBPC.dmode && reg_debug && (prevDMode \|\| !prevChain) bp.control.dmode := dMode when (dMode \|\| (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U } bp.control.chain := newBPC.chain && !(prevChain \|\| nextChain) && (dMode \|\| !nextDMode) } } } } reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }} reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }} if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) { require(xLen % pmp.cfg.getWidth == 0) when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) { val newCfg = (wdata >> ((i pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig()) pmp.cfg := newCfg // disallow unreadable but writable PMPs pmp.cfg.w := newCfg.w && newCfg.r // can't select a=NA4 with coarse-grained PMPs if (pmpGranularity.log2 > PMP.lgAlign) pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR) } when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) { pmp.addr := wdata } } def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (decoded_addr(csr.id)) { reg := (wdata & mask) \| (reg & ~mask) io.wen := true.B } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { writeCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { writeCustomCSR(io, csr, reg) } if (usingVector) { when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata } when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata } when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata } when (decoded_addr(CSRs.vcsr)) { set_vs_dirty := true.B reg_vxsat.get := wdata reg_vxrm.get := wdata >> 1 } } } def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (io.set) { reg := (io.sdata & mask) \| (reg & ~mask) } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { setCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { setCustomCSR(io, csr, reg) } io.vector.map { vio => when (vio.set_vconfig.valid) { // user of CSRFile is responsible for set_vs_dirty in this case assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax) reg_vconfig.get := vio.set_vconfig.bits } when (vio.set_vstart.valid) { set_vs_dirty := true.B reg_vstart.get := vio.set_vstart.bits } vio.vstart := reg_vstart.get vio.vconfig := reg_vconfig.get vio.vxrm := reg_vxrm.get when (reset.asBool) { reg_vconfig.get.vl := 0.U reg_vconfig.get.vtype := 0.U.asTypeOf(new VType) reg_vconfig.get.vtype.vill := true.B } } when(reset.asBool) { reg_satp.mode := 0.U reg_vsatp.mode := 0.U reg_hgatp.mode := 0.U } if (!usingVM) { reg_satp.mode := 0.U reg_satp.ppn := 0.U reg_satp.asid := 0.U } if (!usingHypervisor) { reg_vsatp.mode := 0.U reg_vsatp.ppn := 0.U reg_vsatp.asid := 0.U reg_hgatp.mode := 0.U reg_hgatp.ppn := 0.U reg_hgatp.asid := 0.U } if (!(asIdBits > 0)) { reg_satp.asid := 0.U reg_vsatp.asid := 0.U } if (!(vmIdBits > 0)) { reg_hgatp.asid := 0.U } reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U) if (nBreakpoints <= 1) reg_tselect := 0.U for (bpc <- reg_bp map {_.control}) { bpc.ttype := bpc.tType.U bpc.maskmax := bpc.maskMax.U bpc.reserved := 0.U bpc.zero := 0.U bpc.h := false.B if (!usingSupervisor) bpc.s := false.B if (!usingUser) bpc.u := false.B if (!usingSupervisor && !usingUser) bpc.m := true.B when (reset.asBool) { bpc.action := 0.U bpc.dmode := false.B bpc.chain := false.B bpc.r := false.B bpc.w := false.B bpc.x := false.B } } for (bpx <- reg_bp map {_.textra}) { if (coreParams.mcontextWidth == 0) bpx.mselect := false.B if (coreParams.scontextWidth == 0) bpx.sselect := false.B } for (bp <- reg_bp drop nBreakpoints) bp := 0.U.asTypeOf(new BP()) for (pmp <- reg_pmp) { pmp.cfg.res := 0.U when (reset.asBool) { pmp.reset() } } for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) { t.exception := io.retire >= i.U && exception t.valid := io.retire > i.U \|\| t.exception t.insn := insn t.iaddr := io.pc t.priv := Cat(reg_debug, reg_mstatus.prv) t.cause := cause t.interrupt := cause(xLen-1) t.tval := io.tval t.wdata.foreach(_ := DontCare) } def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = { val nonstandard = supported_interrupts.getWidth-1 to 12 by -1 // MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4) val priority = nonstandard ++ standard val masks = masksIn.reverse val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_\|\|_) val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U)))) (any, which) } def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = { (Mux(cmd(1), rdata, 0.U) \| wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U) } def legalizePrivilege(priv: UInt): UInt = if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv) else if (usingUser) Fill(2, priv(0)) else PRV.M.U def trimPrivilege(priv: UInt): UInt = if (usingSupervisor) priv else legalizePrivilege(priv) def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { if (xLen == 32) { val hi = lo + CSRs.mcycleh - CSRs.mcycle when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } } else { when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) } } } def formEPC(x: UInt) = ~(~x \| (if (usingCompressed) 1.U else 3.U)) def readEPC(x: UInt) = ~(~x \| Mux(reg_misa('c' - 'a'), 1.U, 3.U)) def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) \| 2).U, 2.U) def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_\|_) def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR) def formVS(vs: UInt) = if (usingVector) vs else 0.U }	module Rocket_1( // @[RocketCore.scala:153:7] input clock, // @[RocketCore.scala:153:7] input reset, // @[RocketCore.scala:153:7] input io_hartid, // @[RocketCore.scala:134:14] input io_interrupts_debug, // @[RocketCore.scala:134:14] input io_interrupts_mtip, // @[RocketCore.scala:134:14] input io_interrupts_msip, // @[RocketCore.scala:134:14] input io_interrupts_meip, // @[RocketCore.scala:134:14] input io_interrupts_seip, // @[RocketCore.scala:134:14] output io_imem_might_request, // @[RocketCore.scala:134:14] output io_imem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_imem_req_bits_pc, // @[RocketCore.scala:134:14] output io_imem_req_bits_speculative, // @[RocketCore.scala:134:14] output io_imem_sfence_valid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_imem_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_asid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_hv, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_hg, // @[RocketCore.scala:134:14] output io_imem_resp_ready, // @[RocketCore.scala:134:14] input io_imem_resp_valid, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_btb_cfiType, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_taken, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_btb_mask, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bridx, // @[RocketCore.scala:134:14] input [38:0] io_imem_resp_bits_btb_target, // @[RocketCore.scala:134:14] input [4:0] io_imem_resp_bits_btb_entry, // @[RocketCore.scala:134:14] input [7:0] io_imem_resp_bits_btb_bht_history, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bht_value, // @[RocketCore.scala:134:14] input [39:0] io_imem_resp_bits_pc, // @[RocketCore.scala:134:14] input [31:0] io_imem_resp_bits_data, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_mask, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_pf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_gf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_ae_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_imem_gpa_valid, // @[RocketCore.scala:134:14] input [39:0] io_imem_gpa_bits, // @[RocketCore.scala:134:14] input io_imem_gpa_is_pte, // @[RocketCore.scala:134:14] output io_imem_btb_update_valid, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_prediction_cfiType, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_taken, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_prediction_mask, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_bridx, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_prediction_target, // @[RocketCore.scala:134:14] output [4:0] io_imem_btb_update_bits_prediction_entry, // @[RocketCore.scala:134:14] output [7:0] io_imem_btb_update_bits_prediction_bht_history, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_bht_value, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_pc, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_target, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_isValid, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_br_pc, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_cfiType, // @[RocketCore.scala:134:14] output io_imem_bht_update_valid, // @[RocketCore.scala:134:14] output [7:0] io_imem_bht_update_bits_prediction_history, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_prediction_value, // @[RocketCore.scala:134:14] output [38:0] io_imem_bht_update_bits_pc, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_branch, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_taken, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_mispredict, // @[RocketCore.scala:134:14] output io_imem_flush_icache, // @[RocketCore.scala:134:14] input [39:0] io_imem_npc, // @[RocketCore.scala:134:14] input io_imem_perf_acquire, // @[RocketCore.scala:134:14] input io_imem_perf_tlbMiss, // @[RocketCore.scala:134:14] output io_imem_progress, // @[RocketCore.scala:134:14] input io_dmem_req_ready, // @[RocketCore.scala:134:14] output io_dmem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_dmem_req_bits_addr, // @[RocketCore.scala:134:14] output [6:0] io_dmem_req_bits_tag, // @[RocketCore.scala:134:14] output [4:0] io_dmem_req_bits_cmd, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_size, // @[RocketCore.scala:134:14] output io_dmem_req_bits_signed, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_dprv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_dv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_no_resp, // @[RocketCore.scala:134:14] output io_dmem_s1_kill, // @[RocketCore.scala:134:14] output [63:0] io_dmem_s1_data_data, // @[RocketCore.scala:134:14] input io_dmem_s2_nack, // @[RocketCore.scala:134:14] input io_dmem_s2_nack_cause_raw, // @[RocketCore.scala:134:14] input io_dmem_s2_uncached, // @[RocketCore.scala:134:14] input [31:0] io_dmem_s2_paddr, // @[RocketCore.scala:134:14] input io_dmem_resp_valid, // @[RocketCore.scala:134:14] input [39:0] io_dmem_resp_bits_addr, // @[RocketCore.scala:134:14] input [6:0] io_dmem_resp_bits_tag, // @[RocketCore.scala:134:14] input [4:0] io_dmem_resp_bits_cmd, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_size, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_signed, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_dprv, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_dv, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data, // @[RocketCore.scala:134:14] input [7:0] io_dmem_resp_bits_mask, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_has_data, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_word_bypass, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_raw, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_store_data, // @[RocketCore.scala:134:14] input io_dmem_replay_next, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_st, // @[RocketCore.scala:134:14] input [39:0] io_dmem_s2_gpa, // @[RocketCore.scala:134:14] input io_dmem_ordered, // @[RocketCore.scala:134:14] input io_dmem_store_pending, // @[RocketCore.scala:134:14] input io_dmem_perf_acquire, // @[RocketCore.scala:134:14] input io_dmem_perf_release, // @[RocketCore.scala:134:14] input io_dmem_perf_grant, // @[RocketCore.scala:134:14] input io_dmem_perf_tlbMiss, // @[RocketCore.scala:134:14] input io_dmem_perf_blocked, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptStoreThenLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptStoreThenRMW, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptLoadThenLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_storeBufferEmptyAfterLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_storeBufferEmptyAfterStore, // @[RocketCore.scala:134:14] output io_dmem_keep_clock_enabled, // @[RocketCore.scala:134:14] output [3:0] io_ptw_ptbr_mode, // @[RocketCore.scala:134:14] output [43:0] io_ptw_ptbr_ppn, // @[RocketCore.scala:134:14] output io_ptw_sfence_valid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_ptw_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_asid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_hv, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_hg, // @[RocketCore.scala:134:14] output io_ptw_status_debug, // @[RocketCore.scala:134:14] output io_ptw_status_cease, // @[RocketCore.scala:134:14] output io_ptw_status_wfi, // @[RocketCore.scala:134:14] output [31:0] io_ptw_status_isa, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_dprv, // @[RocketCore.scala:134:14] output io_ptw_status_dv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_prv, // @[RocketCore.scala:134:14] output io_ptw_status_v, // @[RocketCore.scala:134:14] output io_ptw_status_sd, // @[RocketCore.scala:134:14] output io_ptw_status_mpv, // @[RocketCore.scala:134:14] output io_ptw_status_gva, // @[RocketCore.scala:134:14] output io_ptw_status_tsr, // @[RocketCore.scala:134:14] output io_ptw_status_tw, // @[RocketCore.scala:134:14] output io_ptw_status_tvm, // @[RocketCore.scala:134:14] output io_ptw_status_mxr, // @[RocketCore.scala:134:14] output io_ptw_status_sum, // @[RocketCore.scala:134:14] output io_ptw_status_mprv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_fs, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_mpp, // @[RocketCore.scala:134:14] output io_ptw_status_spp, // @[RocketCore.scala:134:14] output io_ptw_status_mpie, // @[RocketCore.scala:134:14] output io_ptw_status_spie, // @[RocketCore.scala:134:14] output io_ptw_status_mie, // @[RocketCore.scala:134:14] output io_ptw_status_sie, // @[RocketCore.scala:134:14] output io_ptw_hstatus_spvp, // @[RocketCore.scala:134:14] output io_ptw_hstatus_spv, // @[RocketCore.scala:134:14] output io_ptw_hstatus_gva, // @[RocketCore.scala:134:14] output io_ptw_gstatus_debug, // @[RocketCore.scala:134:14] output io_ptw_gstatus_cease, // @[RocketCore.scala:134:14] output io_ptw_gstatus_wfi, // @[RocketCore.scala:134:14] output [31:0] io_ptw_gstatus_isa, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_dprv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_dv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_prv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_v, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sd, // @[RocketCore.scala:134:14] output [22:0] io_ptw_gstatus_zero2, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mpv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_gva, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mbe, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sbe, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_sxl, // @[RocketCore.scala:134:14] output [7:0] io_ptw_gstatus_zero1, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tsr, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tw, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tvm, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mxr, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sum, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mprv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_fs, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_mpp, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_vs, // @[RocketCore.scala:134:14] output io_ptw_gstatus_spp, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mpie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_ube, // @[RocketCore.scala:134:14] output io_ptw_gstatus_spie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_upie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_hie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_uie, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_0_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_0_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_0_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_1_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_1_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_1_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_2_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_2_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_2_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_3_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_3_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_3_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_4_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_4_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_4_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_5_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_5_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_5_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_6_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_6_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_6_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_7_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_7_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_7_mask, // @[RocketCore.scala:134:14] input io_ptw_perf_pte_miss, // @[RocketCore.scala:134:14] input io_ptw_perf_pte_hit, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_0_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_0_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_1_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_1_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_1_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_2_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_2_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_2_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_3_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_3_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_3_value, // @[RocketCore.scala:134:14] input io_ptw_clock_enabled, // @[RocketCore.scala:134:14] output io_fpu_hartid, // @[RocketCore.scala:134:14] output [63:0] io_fpu_time, // @[RocketCore.scala:134:14] output [31:0] io_fpu_inst, // @[RocketCore.scala:134:14] output [63:0] io_fpu_fromint_data, // @[RocketCore.scala:134:14] output [2:0] io_fpu_fcsr_rm, // @[RocketCore.scala:134:14] input io_fpu_fcsr_flags_valid, // @[RocketCore.scala:134:14] input [4:0] io_fpu_fcsr_flags_bits, // @[RocketCore.scala:134:14] input [63:0] io_fpu_store_data, // @[RocketCore.scala:134:14] input [63:0] io_fpu_toint_data, // @[RocketCore.scala:134:14] output io_fpu_ll_resp_val, // @[RocketCore.scala:134:14] output [2:0] io_fpu_ll_resp_type, // @[RocketCore.scala:134:14] output [4:0] io_fpu_ll_resp_tag, // @[RocketCore.scala:134:14] output [63:0] io_fpu_ll_resp_data, // @[RocketCore.scala:134:14] output io_fpu_valid, // @[RocketCore.scala:134:14] input io_fpu_fcsr_rdy, // @[RocketCore.scala:134:14] input io_fpu_nack_mem, // @[RocketCore.scala:134:14] input io_fpu_illegal_rm, // @[RocketCore.scala:134:14] output io_fpu_killx, // @[RocketCore.scala:134:14] output io_fpu_killm, // @[RocketCore.scala:134:14] input io_fpu_dec_ldst, // @[RocketCore.scala:134:14] input io_fpu_dec_wen, // @[RocketCore.scala:134:14] input io_fpu_dec_ren1, // @[RocketCore.scala:134:14] input io_fpu_dec_ren2, // @[RocketCore.scala:134:14] input io_fpu_dec_ren3, // @[RocketCore.scala:134:14] input io_fpu_dec_swap12, // @[RocketCore.scala:134:14] input io_fpu_dec_swap23, // @[RocketCore.scala:134:14] input [1:0] io_fpu_dec_typeTagIn, // @[RocketCore.scala:134:14] input [1:0] io_fpu_dec_typeTagOut, // @[RocketCore.scala:134:14] input io_fpu_dec_fromint, // @[RocketCore.scala:134:14] input io_fpu_dec_toint, // @[RocketCore.scala:134:14] input io_fpu_dec_fastpipe, // @[RocketCore.scala:134:14] input io_fpu_dec_fma, // @[RocketCore.scala:134:14] input io_fpu_dec_div, // @[RocketCore.scala:134:14] input io_fpu_dec_sqrt, // @[RocketCore.scala:134:14] input io_fpu_dec_wflags, // @[RocketCore.scala:134:14] input io_fpu_dec_vec, // @[RocketCore.scala:134:14] input io_fpu_sboard_set, // @[RocketCore.scala:134:14] input io_fpu_sboard_clr, // @[RocketCore.scala:134:14] input [4:0] io_fpu_sboard_clra, // @[RocketCore.scala:134:14] output io_fpu_keep_clock_enabled, // @[RocketCore.scala:134:14] output io_trace_insns_0_valid, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_iaddr, // @[RocketCore.scala:134:14] output [31:0] io_trace_insns_0_insn, // @[RocketCore.scala:134:14] output [2:0] io_trace_insns_0_priv, // @[RocketCore.scala:134:14] output io_trace_insns_0_exception, // @[RocketCore.scala:134:14] output io_trace_insns_0_interrupt, // @[RocketCore.scala:134:14] output [63:0] io_trace_insns_0_cause, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_tval, // @[RocketCore.scala:134:14] output [63:0] io_trace_time, // @[RocketCore.scala:134:14] output io_bpwatch_0_valid_0, // @[RocketCore.scala:134:14] output [2:0] io_bpwatch_0_action, // @[RocketCore.scala:134:14] output io_wfi // @[RocketCore.scala:134:14] ); wire ll_arb_io_out_ready; // @[RocketCore.scala:782:23, :809:44, :810:25] wire id_ctrl_fence; // @[RocketCore.scala:321:21] wire id_ctrl_rocc; // @[RocketCore.scala:321:21] wire io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_valid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7] wire _ll_arb_io_in_0_ready; // @[RocketCore.scala:776:22] wire _ll_arb_io_out_valid; // @[RocketCore.scala:776:22] wire [4:0] _ll_arb_io_out_bits_tag; // @[RocketCore.scala:776:22] wire _div_io_req_ready; // @[RocketCore.scala:511:19] wire _div_io_resp_valid; // @[RocketCore.scala:511:19] wire [63:0] _div_io_resp_bits_data; // @[RocketCore.scala:511:19] wire [4:0] _div_io_resp_bits_tag; // @[RocketCore.scala:511:19] wire [63:0] _alu_io_adder_out; // @[RocketCore.scala:504:19] wire _alu_io_cmp_out; // @[RocketCore.scala:504:19] wire _bpu_io_xcpt_if; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_ld; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_st; // @[RocketCore.scala:414:19] wire _bpu_io_debug_if; // @[RocketCore.scala:414:19] wire _bpu_io_debug_ld; // @[RocketCore.scala:414:19] wire _bpu_io_debug_st; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_rvalid_0; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_wvalid_0; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_ivalid_0; // @[RocketCore.scala:414:19] wire [63:0] _csr_io_rw_rdata; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_csr; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_read_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_csr_stall; // @[RocketCore.scala:341:19] wire _csr_io_eret; // @[RocketCore.scala:341:19] wire _csr_io_singleStep; // @[RocketCore.scala:341:19] wire _csr_io_status_debug; // @[RocketCore.scala:341:19] wire _csr_io_status_cease; // @[RocketCore.scala:341:19] wire _csr_io_status_wfi; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_status_isa; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_dprv; // @[RocketCore.scala:341:19] wire _csr_io_status_dv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_prv; // @[RocketCore.scala:341:19] wire _csr_io_status_v; // @[RocketCore.scala:341:19] wire _csr_io_status_sd; // @[RocketCore.scala:341:19] wire _csr_io_status_mpv; // @[RocketCore.scala:341:19] wire _csr_io_status_gva; // @[RocketCore.scala:341:19] wire _csr_io_status_tsr; // @[RocketCore.scala:341:19] wire _csr_io_status_tw; // @[RocketCore.scala:341:19] wire _csr_io_status_tvm; // @[RocketCore.scala:341:19] wire _csr_io_status_mxr; // @[RocketCore.scala:341:19] wire _csr_io_status_sum; // @[RocketCore.scala:341:19] wire _csr_io_status_mprv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_fs; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_mpp; // @[RocketCore.scala:341:19] wire _csr_io_status_spp; // @[RocketCore.scala:341:19] wire _csr_io_status_mpie; // @[RocketCore.scala:341:19] wire _csr_io_status_spie; // @[RocketCore.scala:341:19] wire _csr_io_status_mie; // @[RocketCore.scala:341:19] wire _csr_io_status_sie; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_evec; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_time; // @[RocketCore.scala:341:19] wire _csr_io_interrupt; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_interrupt_cause; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_dmode; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_action; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_bp_0_control_tmatch; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_m; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_s; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_u; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_x; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_w; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_r; // @[RocketCore.scala:341:19] wire [38:0] _csr_io_bp_0_address; // @[RocketCore.scala:341:19] wire [47:0] _csr_io_bp_0_textra_pad2; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_textra_pad1; // @[RocketCore.scala:341:19] wire _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_valid; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_trace_0_iaddr; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_trace_0_insn; // @[RocketCore.scala:341:19] wire [2:0] _csr_io_trace_0_priv; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_exception; // @[RocketCore.scala:341:19] wire [39:0] _ibuf_io_pc; // @[RocketCore.scala:311:20] wire [1:0] _ibuf_io_btb_resp_cfiType; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_taken; // @[RocketCore.scala:311:20] wire [1:0] _ibuf_io_btb_resp_mask; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_bridx; // @[RocketCore.scala:311:20] wire [38:0] _ibuf_io_btb_resp_target; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_btb_resp_entry; // @[RocketCore.scala:311:20] wire [7:0] _ibuf_io_btb_resp_bht_history; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_bht_value; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20] wire io_hartid_0 = io_hartid; // @[RocketCore.scala:153:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[RocketCore.scala:153:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[RocketCore.scala:153:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[RocketCore.scala:153:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[RocketCore.scala:153:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[RocketCore.scala:153:7] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_btb_cfiType_0 = io_imem_resp_bits_btb_cfiType; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_taken_0 = io_imem_resp_bits_btb_taken; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_btb_mask_0 = io_imem_resp_bits_btb_mask; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_bridx_0 = io_imem_resp_bits_btb_bridx; // @[RocketCore.scala:153:7] wire [38:0] io_imem_resp_bits_btb_target_0 = io_imem_resp_bits_btb_target; // @[RocketCore.scala:153:7] wire [4:0] io_imem_resp_bits_btb_entry_0 = io_imem_resp_bits_btb_entry; // @[RocketCore.scala:153:7] wire [7:0] io_imem_resp_bits_btb_bht_history_0 = io_imem_resp_bits_btb_bht_history; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_bht_value_0 = io_imem_resp_bits_btb_bht_value; // @[RocketCore.scala:153:7] wire [39:0] io_imem_resp_bits_pc_0 = io_imem_resp_bits_pc; // @[RocketCore.scala:153:7] wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_mask_0 = io_imem_resp_bits_mask; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_pf_inst_0 = io_imem_resp_bits_xcpt_pf_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_gf_inst_0 = io_imem_resp_bits_xcpt_gf_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_ae_inst_0 = io_imem_resp_bits_xcpt_ae_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_replay_0 = io_imem_resp_bits_replay; // @[RocketCore.scala:153:7] wire io_imem_gpa_valid_0 = io_imem_gpa_valid; // @[RocketCore.scala:153:7] wire [39:0] io_imem_gpa_bits_0 = io_imem_gpa_bits; // @[RocketCore.scala:153:7] wire io_imem_gpa_is_pte_0 = io_imem_gpa_is_pte; // @[RocketCore.scala:153:7] wire [39:0] io_imem_npc_0 = io_imem_npc; // @[RocketCore.scala:153:7] wire io_imem_perf_acquire_0 = io_imem_perf_acquire; // @[RocketCore.scala:153:7] wire io_imem_perf_tlbMiss_0 = io_imem_perf_tlbMiss; // @[RocketCore.scala:153:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[RocketCore.scala:153:7] wire io_dmem_s2_nack_0 = io_dmem_s2_nack; // @[RocketCore.scala:153:7] wire io_dmem_s2_nack_cause_raw_0 = io_dmem_s2_nack_cause_raw; // @[RocketCore.scala:153:7] wire io_dmem_s2_uncached_0 = io_dmem_s2_uncached; // @[RocketCore.scala:153:7] wire [31:0] io_dmem_s2_paddr_0 = io_dmem_s2_paddr; // @[RocketCore.scala:153:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_resp_bits_addr_0 = io_dmem_resp_bits_addr; // @[RocketCore.scala:153:7] wire [6:0] io_dmem_resp_bits_tag_0 = io_dmem_resp_bits_tag; // @[RocketCore.scala:153:7] wire [4:0] io_dmem_resp_bits_cmd_0 = io_dmem_resp_bits_cmd; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_resp_bits_size_0 = io_dmem_resp_bits_size; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_signed_0 = io_dmem_resp_bits_signed; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_resp_bits_dprv_0 = io_dmem_resp_bits_dprv; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_dv_0 = io_dmem_resp_bits_dv; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_resp_bits_mask_0 = io_dmem_resp_bits_mask; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_replay_0 = io_dmem_resp_bits_replay; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_has_data_0 = io_dmem_resp_bits_has_data; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_word_bypass_0 = io_dmem_resp_bits_data_word_bypass; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_raw_0 = io_dmem_resp_bits_data_raw; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_store_data_0 = io_dmem_resp_bits_store_data; // @[RocketCore.scala:153:7] wire io_dmem_replay_next_0 = io_dmem_replay_next; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ma_ld_0 = io_dmem_s2_xcpt_ma_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ma_st_0 = io_dmem_s2_xcpt_ma_st; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_pf_ld_0 = io_dmem_s2_xcpt_pf_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_pf_st_0 = io_dmem_s2_xcpt_pf_st; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ae_ld_0 = io_dmem_s2_xcpt_ae_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ae_st_0 = io_dmem_s2_xcpt_ae_st; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_s2_gpa_0 = io_dmem_s2_gpa; // @[RocketCore.scala:153:7] wire io_dmem_ordered_0 = io_dmem_ordered; // @[RocketCore.scala:153:7] wire io_dmem_store_pending_0 = io_dmem_store_pending; // @[RocketCore.scala:153:7] wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[RocketCore.scala:153:7] wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[RocketCore.scala:153:7] wire io_dmem_perf_grant_0 = io_dmem_perf_grant; // @[RocketCore.scala:153:7] wire io_dmem_perf_tlbMiss_0 = io_dmem_perf_tlbMiss; // @[RocketCore.scala:153:7] wire io_dmem_perf_blocked_0 = io_dmem_perf_blocked; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptStoreThenLoad_0 = io_dmem_perf_canAcceptStoreThenLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptStoreThenRMW_0 = io_dmem_perf_canAcceptStoreThenRMW; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptLoadThenLoad_0 = io_dmem_perf_canAcceptLoadThenLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_storeBufferEmptyAfterLoad_0 = io_dmem_perf_storeBufferEmptyAfterLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_storeBufferEmptyAfterStore_0 = io_dmem_perf_storeBufferEmptyAfterStore; // @[RocketCore.scala:153:7] wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[RocketCore.scala:153:7] wire io_ptw_perf_pte_hit_0 = io_ptw_perf_pte_hit; // @[RocketCore.scala:153:7] wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[RocketCore.scala:153:7] wire io_fpu_fcsr_flags_valid_0 = io_fpu_fcsr_flags_valid; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_fcsr_flags_bits_0 = io_fpu_fcsr_flags_bits; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_store_data_0 = io_fpu_store_data; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_toint_data_0 = io_fpu_toint_data; // @[RocketCore.scala:153:7] wire io_fpu_fcsr_rdy_0 = io_fpu_fcsr_rdy; // @[RocketCore.scala:153:7] wire io_fpu_nack_mem_0 = io_fpu_nack_mem; // @[RocketCore.scala:153:7] wire io_fpu_illegal_rm_0 = io_fpu_illegal_rm; // @[RocketCore.scala:153:7] wire io_fpu_dec_ldst_0 = io_fpu_dec_ldst; // @[RocketCore.scala:153:7] wire io_fpu_dec_wen_0 = io_fpu_dec_wen; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren1_0 = io_fpu_dec_ren1; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren2_0 = io_fpu_dec_ren2; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren3_0 = io_fpu_dec_ren3; // @[RocketCore.scala:153:7] wire io_fpu_dec_swap12_0 = io_fpu_dec_swap12; // @[RocketCore.scala:153:7] wire io_fpu_dec_swap23_0 = io_fpu_dec_swap23; // @[RocketCore.scala:153:7] wire [1:0] io_fpu_dec_typeTagIn_0 = io_fpu_dec_typeTagIn; // @[RocketCore.scala:153:7] wire [1:0] io_fpu_dec_typeTagOut_0 = io_fpu_dec_typeTagOut; // @[RocketCore.scala:153:7] wire io_fpu_dec_fromint_0 = io_fpu_dec_fromint; // @[RocketCore.scala:153:7] wire io_fpu_dec_toint_0 = io_fpu_dec_toint; // @[RocketCore.scala:153:7] wire io_fpu_dec_fastpipe_0 = io_fpu_dec_fastpipe; // @[RocketCore.scala:153:7] wire io_fpu_dec_fma_0 = io_fpu_dec_fma; // @[RocketCore.scala:153:7] wire io_fpu_dec_div_0 = io_fpu_dec_div; // @[RocketCore.scala:153:7] wire io_fpu_dec_sqrt_0 = io_fpu_dec_sqrt; // @[RocketCore.scala:153:7] wire io_fpu_dec_wflags_0 = io_fpu_dec_wflags; // @[RocketCore.scala:153:7] wire io_fpu_dec_vec_0 = io_fpu_dec_vec; // @[RocketCore.scala:153:7] wire io_fpu_sboard_set_0 = io_fpu_sboard_set; // @[RocketCore.scala:153:7] wire io_fpu_sboard_clr_0 = io_fpu_sboard_clr; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_sboard_clra_0 = io_fpu_sboard_clra; // @[RocketCore.scala:153:7] wire coreMonitorBundle_clock = clock; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_reset = reset; // @[RocketCore.scala:1186:31] wire xrfWriteBundle_clock = clock; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_reset = reset; // @[RocketCore.scala:1249:28] wire io_imem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7] wire io_dmem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7] wire clock_en = 1'h1; // @[RocketCore.scala:153:7, :163:29] wire _id_npc_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _id_npc_b11_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1345:23] wire _id_illegal_insn_T_10 = 1'h1; // @[RocketCore.scala:153:7, :384:73] wire _id_illegal_insn_T_15 = 1'h1; // @[RocketCore.scala:153:7, :385:55] wire _mem_br_target_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _mem_br_target_b19_12_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1343:43] wire _mem_br_target_b19_12_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1343:36] wire _mem_br_target_b11_T_6 = 1'h1; // @[RocketCore.scala:153:7, :1346:23] wire _mem_br_target_b4_1_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1349:41] wire _mem_br_target_b4_1_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1349:34] wire _mem_br_target_b19_12_T_5 = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _mem_br_target_b11_T_14 = 1'h1; // @[RocketCore.scala:153:7, :1345:23] wire _wb_reg_xcpt_T_2 = 1'h1; // @[RocketCore.scala:153:7, :707:45] wire _replay_wb_rocc_T_1 = 1'h1; // @[RocketCore.scala:153:7, :758:56] wire _rocc_blocked_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1029:31] wire io_imem_btb_update_bits_taken = 1'h0; // @[RocketCore.scala:153:7] wire io_imem_ras_update_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtw = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_hu = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_perf_l2miss = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_perf_l2hit = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_resp_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_resp_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_signed = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_dv = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_resp = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s1_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_nack = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_nack_cause_raw = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_uncached = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_signed = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_dv = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_replay = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_has_data = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_replay_next = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ma_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_pf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ae_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_ordered = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_store_pending = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_acquire = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_release = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_grant = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_tlbMiss = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_blocked = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_keep_clock_enabled = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_clock_enabled = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_busy = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_interrupt = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_exception = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_rvalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_wvalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_ivalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_cease = 1'h0; // @[RocketCore.scala:153:7] wire io_traceStall = 1'h0; // @[RocketCore.scala:153:7] wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_5 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_6 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_7 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_8 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_9 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_10 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_11 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_12 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_13 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_14 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_15 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_16 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_17 = 1'h0; // @[Events.scala:13:33] wire hits_0 = 1'h0; // @[Events.scala:13:25] wire hits_1 = 1'h0; // @[Events.scala:13:25] wire hits_2 = 1'h0; // @[Events.scala:13:25] wire hits_3 = 1'h0; // @[Events.scala:13:25] wire hits_4 = 1'h0; // @[Events.scala:13:25] wire hits_5 = 1'h0; // @[Events.scala:13:25] wire hits_6 = 1'h0; // @[Events.scala:13:25] wire hits_7 = 1'h0; // @[Events.scala:13:25] wire hits_8 = 1'h0; // @[Events.scala:13:25] wire hits_9 = 1'h0; // @[Events.scala:13:25] wire hits_10 = 1'h0; // @[Events.scala:13:25] wire hits_11 = 1'h0; // @[Events.scala:13:25] wire hits_12 = 1'h0; // @[Events.scala:13:25] wire hits_13 = 1'h0; // @[Events.scala:13:25] wire hits_14 = 1'h0; // @[Events.scala:13:25] wire hits_15 = 1'h0; // @[Events.scala:13:25] wire hits_16 = 1'h0; // @[Events.scala:13:25] wire hits_17 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_1_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_5 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_6 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_7 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_8 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_9 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_10 = 1'h0; // @[Events.scala:13:33] wire hits_1_0 = 1'h0; // @[Events.scala:13:25] wire hits_1_1 = 1'h0; // @[Events.scala:13:25] wire hits_1_2 = 1'h0; // @[Events.scala:13:25] wire hits_1_3 = 1'h0; // @[Events.scala:13:25] wire hits_1_4 = 1'h0; // @[Events.scala:13:25] wire hits_1_5 = 1'h0; // @[Events.scala:13:25] wire hits_1_6 = 1'h0; // @[Events.scala:13:25] wire hits_1_7 = 1'h0; // @[Events.scala:13:25] wire hits_1_8 = 1'h0; // @[Events.scala:13:25] wire hits_1_9 = 1'h0; // @[Events.scala:13:25] wire hits_1_10 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_2_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_5 = 1'h0; // @[Events.scala:13:33] wire hits_2_0 = 1'h0; // @[Events.scala:13:25] wire hits_2_1 = 1'h0; // @[Events.scala:13:25] wire hits_2_2 = 1'h0; // @[Events.scala:13:25] wire hits_2_3 = 1'h0; // @[Events.scala:13:25] wire hits_2_4 = 1'h0; // @[Events.scala:13:25] wire hits_2_5 = 1'h0; // @[Events.scala:13:25] wire id_ctrl_vec = 1'h0; // @[RocketCore.scala:321:21] wire _id_rs_T_1 = 1'h0; // @[RocketCore.scala:1326:33] wire _id_rs_T_6 = 1'h0; // @[RocketCore.scala:1326:33] wire _id_npc_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _id_npc_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _id_npc_b19_12_T_1 = 1'h0; // @[RocketCore.scala:1343:43] wire _id_npc_b19_12_T_2 = 1'h0; // @[RocketCore.scala:1343:36] wire _id_npc_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _id_npc_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _id_npc_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _id_npc_b11_T_6 = 1'h0; // @[RocketCore.scala:1346:23] wire _id_npc_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _id_npc_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _id_npc_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _id_npc_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _id_npc_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _id_npc_b4_1_T_2 = 1'h0; // @[RocketCore.scala:1349:41] wire _id_npc_b4_1_T_3 = 1'h0; // @[RocketCore.scala:1349:34] wire _id_npc_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _id_npc_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _id_npc_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _id_npc_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _id_npc_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _id_npc_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire id_npc_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire id_set_vconfig = 1'h0; // @[RocketCore.scala:347:120] wire _id_illegal_insn_T_16 = 1'h0; // @[RocketCore.scala:385:19] wire _id_illegal_insn_T_26 = 1'h0; // @[RocketCore.scala:388:23] wire _id_illegal_insn_T_28 = 1'h0; // @[RocketCore.scala:389:23] wire _id_illegal_insn_T_30 = 1'h0; // @[RocketCore.scala:390:22] wire id_rocc_busy = 1'h0; // @[RocketCore.scala:405:34] wire _id_csr_rocc_write_T = 1'h0; // @[RocketCore.scala:408:87] wire id_csr_rocc_write = 1'h0; // @[RocketCore.scala:408:100] wire _id_do_fence_T_1 = 1'h0; // @[RocketCore.scala:410:46] wire _id_do_fence_T_2 = 1'h0; // @[RocketCore.scala:411:17] wire _id_do_fence_T_3 = 1'h0; // @[RocketCore.scala:410:86] wire _ex_reg_hls_T = 1'h0; // @[RocketCore.scala:553:37] wire _ex_reg_hls_T_6 = 1'h0; // @[RocketCore.scala:553:55] wire _ex_reg_mem_size_T = 1'h0; // @[RocketCore.scala:554:46] wire _ex_reg_set_vconfig_T_1 = 1'h0; // @[RocketCore.scala:591:42] wire _replay_ex_structural_T_5 = 1'h0; // @[RocketCore.scala:599:45] wire _replay_ex_structural_T_6 = 1'h0; // @[RocketCore.scala:599:42] wire _mem_br_target_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_br_target_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_br_target_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_br_target_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_br_target_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_br_target_b11_T_3 = 1'h0; // @[RocketCore.scala:1345:23] wire _mem_br_target_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_br_target_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_br_target_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_br_target_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_br_target_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_br_target_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_br_target_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_br_target_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_br_target_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_br_target_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_br_target_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_br_target_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _mem_br_target_sign_T_3 = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_br_target_b30_20_T_3 = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_br_target_b19_12_T_6 = 1'h0; // @[RocketCore.scala:1343:43] wire _mem_br_target_b19_12_T_7 = 1'h0; // @[RocketCore.scala:1343:36] wire _mem_br_target_b11_T_11 = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_br_target_b11_T_12 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_br_target_b11_T_13 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_br_target_b11_T_17 = 1'h0; // @[RocketCore.scala:1346:23] wire _mem_br_target_b10_5_T_4 = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_br_target_b10_5_T_5 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_br_target_b10_5_T_6 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_br_target_b4_1_T_10 = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_br_target_b4_1_T_11 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_br_target_b4_1_T_12 = 1'h0; // @[RocketCore.scala:1349:41] wire _mem_br_target_b4_1_T_13 = 1'h0; // @[RocketCore.scala:1349:34] wire _mem_br_target_b4_1_T_15 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_br_target_b0_T_8 = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_br_target_b0_T_10 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_br_target_b0_T_12 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_br_target_b0_T_14 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_br_target_b0_T_15 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_br_target_b0_1 = 1'h0; // @[RocketCore.scala:1351:17] wire vec_kill_mem = 1'h0; // @[RocketCore.scala:697:52] wire vec_kill_all = 1'h0; // @[RocketCore.scala:698:36] wire replay_wb_csr = 1'h0; // @[RocketCore.scala:759:42] wire replay_wb_vec = 1'h0; // @[RocketCore.scala:760:36] wire _htval_valid_dmem_T_2 = 1'h0; // @[RocketCore.scala:857:83] wire _htval_valid_dmem_T_3 = 1'h0; // @[RocketCore.scala:857:54] wire htval_valid_dmem = 1'h0; // @[RocketCore.scala:857:87] wire _mhtinst_read_pseudo_T_1 = 1'h0; // @[RocketCore.scala:862:98] wire _id_vconfig_hazard_T = 1'h0; // @[RocketCore.scala:1003:19] wire id_vconfig_hazard = 1'h0; // @[RocketCore.scala:1002:39] wire _ctrl_stalld_T_12 = 1'h0; // @[RocketCore.scala:1036:15] wire _ctrl_stalld_T_13 = 1'h0; // @[RocketCore.scala:1036:46] wire _ctrl_stalld_T_28 = 1'h0; // @[RocketCore.scala:1041:5] wire _io_rocc_exception_T = 1'h0; // @[RocketCore.scala:1157:52] wire _io_rocc_exception_T_1 = 1'h0; // @[RocketCore.scala:1157:32] wire _io_cease_T = 1'h0; // @[RocketCore.scala:1166:38] wire _io_cease_T_1 = 1'h0; // @[RocketCore.scala:1166:35] wire coreMonitorBundle_wrenf = 1'h0; // @[RocketCore.scala:1186:31] wire xrfWriteBundle_excpt = 1'h0; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_valid = 1'h0; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_wrenf = 1'h0; // @[RocketCore.scala:1249:28] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[RocketCore.scala:153:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[RocketCore.scala:153:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[RocketCore.scala:153:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_ras_update_bits_cfiType = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_vs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_req_bits_size = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_resp_bits_size = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] _htval_valid_dmem_T_1 = 2'h0; // @[RocketCore.scala:857:76] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[RocketCore.scala:153:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[RocketCore.scala:153:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[RocketCore.scala:153:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_resp_bits_rd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] _csr_io_fcsr_flags_bits_T_2 = 5'h0; // @[RocketCore.scala:839:116] wire [4:0] _csr_io_fcsr_flags_bits_T_3 = 5'h0; // @[RocketCore.scala:839:110] wire [4:0] xrfWriteBundle_rd0src = 5'h0; // @[RocketCore.scala:1249:28] wire [4:0] xrfWriteBundle_rd1src = 5'h0; // @[RocketCore.scala:1249:28] wire [39:0] io_rocc_mem_req_bits_addr = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_s2_gpa = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] htval_dmem = 40'h0; // @[RocketCore.scala:858:25] wire [31:0] io_reset_vector = 32'h0; // @[RocketCore.scala:153:7] wire [31:0] io_rocc_mem_s2_paddr = 32'h0; // @[RocketCore.scala:153:7] wire [31:0] xrfWriteBundle_inst = 32'h0; // @[RocketCore.scala:1249:28] wire [38:0] io_imem_ras_update_bits_returnAddr = 39'h0; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_s1_data_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] xrfWriteBundle_pc = 64'h0; // @[RocketCore.scala:1249:28] wire [63:0] xrfWriteBundle_rd0val = 64'h0; // @[RocketCore.scala:1249:28] wire [63:0] xrfWriteBundle_rd1val = 64'h0; // @[RocketCore.scala:1249:28] wire [1:0] io_ptw_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_v_sew = 3'h0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_mem_req_bits_tag = 7'h0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0; // @[RocketCore.scala:153:7] wire io_fpu_hartid_0 = io_hartid_0; // @[RocketCore.scala:153:7] wire take_pc_mem_wb; // @[RocketCore.scala:307:35] wire [39:0] _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:1051:8] wire _io_imem_req_bits_speculative_T; // @[RocketCore.scala:1049:35] wire _io_imem_sfence_valid_T; // @[RocketCore.scala:1060:40] wire io_ptw_sfence_valid_0 = io_imem_sfence_valid_0; // @[RocketCore.scala:153:7] wire _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:1061:45] wire io_ptw_sfence_bits_rs1_0 = io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7] wire _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:1062:45] wire io_ptw_sfence_bits_rs2_0 = io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7] wire [38:0] io_ptw_sfence_bits_addr_0 = io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_asid_0 = io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_hv_0 = io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_hg_0 = io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7] wire _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:1071:77] wire [38:0] _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:1080:33] wire [38:0] io_imem_bht_update_bits_pc_0 = io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7] wire mem_cfi; // @[RocketCore.scala:625:50] wire [1:0] _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:1074:8] wire _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:1084:45] wire mem_wrong_npc; // @[RocketCore.scala:621:8] wire _io_imem_flush_icache_T_2; // @[RocketCore.scala:1054:59] wire _io_dmem_req_valid_T; // @[RocketCore.scala:1130:41] wire [39:0] _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:1295:8] wire _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:1136:30] wire [1:0] _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:1140:31] wire _io_dmem_req_bits_dv_T; // @[RocketCore.scala:1141:37] wire _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:1142:56] wire _io_dmem_s1_kill_T_2; // @[RocketCore.scala:1151:68] wire [63:0] _io_dmem_s1_data_data_T; // @[RocketCore.scala:1148:63] wire [63:0] io_fpu_ll_resp_data_0 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7] wire [63:0] _rf_wdata_T_1 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7, :819:78] wire [63:0] dcache_bypass_data = io_dmem_resp_bits_data_word_bypass_0; // @[RocketCore.scala:153:7, :449:62] wire _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:1154:70] wire [63:0] ex_rs_0; // @[RocketCore.scala:469:14] wire _csr_io_fcsr_flags_valid_T = io_fpu_fcsr_flags_valid_0; // @[RocketCore.scala:153:7, :838:54] wire _io_fpu_ll_resp_val_T; // @[RocketCore.scala:1099:41] wire [4:0] dmem_resp_waddr; // @[RocketCore.scala:767:46] wire _io_fpu_valid_T_1; // @[RocketCore.scala:1094:31] wire _id_illegal_insn_T_11 = io_fpu_illegal_rm_0; // @[RocketCore.scala:153:7, :384:70] wire ctrl_killx; // @[RocketCore.scala:602:48] wire killm_common; // @[RocketCore.scala:700:68] wire _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59] wire _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:1156:53] wire [6:0] _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:1159:48] wire [6:0] _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:1159:48] wire [39:0] io_imem_req_bits_pc_0; // @[RocketCore.scala:153:7] wire io_imem_req_bits_speculative_0; // @[RocketCore.scala:153:7] wire io_imem_req_valid_0; // @[RocketCore.scala:153:7] wire io_imem_resp_ready_0; // @[RocketCore.scala:153:7] wire [7:0] io_imem_btb_update_bits_prediction_bht_history_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_bht_value_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_prediction_cfiType_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_taken_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_prediction_mask_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_bridx_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_prediction_target_0; // @[RocketCore.scala:153:7] wire [4:0] io_imem_btb_update_bits_prediction_entry_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_target_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_isValid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_cfiType_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_valid_0; // @[RocketCore.scala:153:7] wire [7:0] io_imem_bht_update_bits_prediction_history_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_prediction_value_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_branch_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_taken_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_mispredict_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_valid_0; // @[RocketCore.scala:153:7] wire io_imem_might_request_0; // @[RocketCore.scala:153:7] wire io_imem_flush_icache_0; // @[RocketCore.scala:153:7] wire io_imem_progress_0; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_req_bits_addr_0; // @[RocketCore.scala:153:7] wire [6:0] io_dmem_req_bits_tag_0; // @[RocketCore.scala:153:7] wire [4:0] io_dmem_req_bits_cmd_0; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_req_bits_size_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_signed_0; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_req_bits_dprv_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_dv_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_resp_0; // @[RocketCore.scala:153:7] wire io_dmem_req_valid_0; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_s1_data_data_0; // @[RocketCore.scala:153:7] wire io_dmem_s1_kill_0; // @[RocketCore.scala:153:7] wire io_dmem_keep_clock_enabled_0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_ptbr_mode_0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_ptbr_ppn_0; // @[RocketCore.scala:153:7] wire io_ptw_status_debug_0; // @[RocketCore.scala:153:7] wire io_ptw_status_cease_0; // @[RocketCore.scala:153:7] wire io_ptw_status_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_status_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_dprv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_prv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_v_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sd_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mpv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tsr_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tw_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tvm_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mxr_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sum_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_mpp_0; // @[RocketCore.scala:153:7] wire io_ptw_status_spp_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mpie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_spie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sie_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_spvp_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_spv_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_debug_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_cease_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_gstatus_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_dprv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_prv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_v_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sd_0; // @[RocketCore.scala:153:7] wire [22:0] io_ptw_gstatus_zero2_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mpv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mbe_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sbe_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_sxl_0; // @[RocketCore.scala:153:7] wire [7:0] io_ptw_gstatus_zero1_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tsr_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tw_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tvm_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mxr_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sum_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_mpp_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_vs_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_spp_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mpie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_ube_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_spie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_upie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_hie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_uie_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_0_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_0_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_0_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_1_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_1_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_1_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_2_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_2_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_2_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_3_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_3_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_3_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_4_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_4_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_4_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_5_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_5_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_5_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_6_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_6_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_6_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_7_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_7_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_7_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_time_0; // @[RocketCore.scala:153:7] wire [31:0] io_fpu_inst_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_fromint_data_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_fcsr_rm_0; // @[RocketCore.scala:153:7] wire io_fpu_ll_resp_val_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_ll_resp_type_0; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7] wire io_fpu_valid_0; // @[RocketCore.scala:153:7] wire io_fpu_killx_0; // @[RocketCore.scala:153:7] wire io_fpu_killm_0; // @[RocketCore.scala:153:7] wire io_fpu_keep_clock_enabled_0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_cmd_bits_inst_funct; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rs2; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rs1; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xd; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xs1; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xs2; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rd; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_cmd_bits_inst_opcode; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_debug; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_cease; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_wfi; // @[RocketCore.scala:153:7] wire [31:0] io_rocc_cmd_bits_status_isa; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_dprv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_dv; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_prv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_v; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sd; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mpv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_gva; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tsr; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tw; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tvm; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mxr; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sum; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mprv; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_fs; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_mpp; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_spp; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mpie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_spie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sie; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_cmd_bits_rs1; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_cmd_bits_rs2; // @[RocketCore.scala:153:7] wire io_rocc_cmd_valid; // @[RocketCore.scala:153:7] wire io_trace_insns_0_valid_0; // @[RocketCore.scala:153:7] wire [39:0] io_trace_insns_0_iaddr_0; // @[RocketCore.scala:153:7] wire [31:0] io_trace_insns_0_insn_0; // @[RocketCore.scala:153:7] wire [2:0] io_trace_insns_0_priv_0; // @[RocketCore.scala:153:7] wire io_trace_insns_0_exception_0; // @[RocketCore.scala:153:7] wire io_trace_insns_0_interrupt_0; // @[RocketCore.scala:153:7] wire [63:0] io_trace_insns_0_cause_0; // @[RocketCore.scala:153:7] wire [39:0] io_trace_insns_0_tval_0; // @[RocketCore.scala:153:7] wire [63:0] io_trace_time_0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_valid_0_0; // @[RocketCore.scala:153:7] wire [2:0] io_bpwatch_0_action_0; // @[RocketCore.scala:153:7] wire io_wfi_0; // @[RocketCore.scala:153:7] reg id_reg_pause; // @[RocketCore.scala:161:25] reg imem_might_request_reg; // @[RocketCore.scala:162:35] assign io_imem_might_request_0 = imem_might_request_reg; // @[RocketCore.scala:153:7, :162:35] reg ex_ctrl_legal; // @[RocketCore.scala:243:20] reg ex_ctrl_fp; // @[RocketCore.scala:243:20] reg ex_ctrl_rocc; // @[RocketCore.scala:243:20] reg ex_ctrl_branch; // @[RocketCore.scala:243:20] reg ex_ctrl_jal; // @[RocketCore.scala:243:20] reg ex_ctrl_jalr; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_alu2; // @[RocketCore.scala:243:20] reg [1:0] ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_imm; // @[RocketCore.scala:243:20] reg ex_ctrl_alu_dw; // @[RocketCore.scala:243:20] reg [4:0] ex_ctrl_alu_fn; // @[RocketCore.scala:243:20] reg ex_ctrl_mem; // @[RocketCore.scala:243:20] wire _ex_sfence_T = ex_ctrl_mem; // @[RocketCore.scala:243:20, :605:29] reg [4:0] ex_ctrl_mem_cmd; // @[RocketCore.scala:243:20] assign io_dmem_req_bits_cmd_0 = ex_ctrl_mem_cmd; // @[RocketCore.scala:153:7, :243:20] reg ex_ctrl_rfs1; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs3; // @[RocketCore.scala:243:20] reg ex_ctrl_wfd; // @[RocketCore.scala:243:20] reg ex_ctrl_mul; // @[RocketCore.scala:243:20] reg ex_ctrl_div; // @[RocketCore.scala:243:20] reg ex_ctrl_wxd; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_csr; // @[RocketCore.scala:243:20] reg ex_ctrl_fence_i; // @[RocketCore.scala:243:20] reg ex_ctrl_fence; // @[RocketCore.scala:243:20] reg ex_ctrl_amo; // @[RocketCore.scala:243:20] reg ex_ctrl_dp; // @[RocketCore.scala:243:20] reg mem_ctrl_legal; // @[RocketCore.scala:244:21] reg mem_ctrl_fp; // @[RocketCore.scala:244:21] reg mem_ctrl_rocc; // @[RocketCore.scala:244:21] reg mem_ctrl_branch; // @[RocketCore.scala:244:21] assign io_imem_bht_update_bits_branch_0 = mem_ctrl_branch; // @[RocketCore.scala:153:7, :244:21] reg mem_ctrl_jal; // @[RocketCore.scala:244:21] reg mem_ctrl_jalr; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs1; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_sel_alu2; // @[RocketCore.scala:244:21] reg [1:0] mem_ctrl_sel_alu1; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_sel_imm; // @[RocketCore.scala:244:21] reg mem_ctrl_alu_dw; // @[RocketCore.scala:244:21] reg [4:0] mem_ctrl_alu_fn; // @[RocketCore.scala:244:21] reg mem_ctrl_mem; // @[RocketCore.scala:244:21] reg [4:0] mem_ctrl_mem_cmd; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs1; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs3; // @[RocketCore.scala:244:21] reg mem_ctrl_wfd; // @[RocketCore.scala:244:21] reg mem_ctrl_mul; // @[RocketCore.scala:244:21] reg mem_ctrl_div; // @[RocketCore.scala:244:21] reg mem_ctrl_wxd; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_csr; // @[RocketCore.scala:244:21] reg mem_ctrl_fence_i; // @[RocketCore.scala:244:21] reg mem_ctrl_fence; // @[RocketCore.scala:244:21] reg mem_ctrl_amo; // @[RocketCore.scala:244:21] reg mem_ctrl_dp; // @[RocketCore.scala:244:21] reg mem_ctrl_vec; // @[RocketCore.scala:244:21] reg wb_ctrl_legal; // @[RocketCore.scala:245:20] reg wb_ctrl_fp; // @[RocketCore.scala:245:20] reg wb_ctrl_rocc; // @[RocketCore.scala:245:20] reg wb_ctrl_branch; // @[RocketCore.scala:245:20] reg wb_ctrl_jal; // @[RocketCore.scala:245:20] reg wb_ctrl_jalr; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs1; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_sel_alu2; // @[RocketCore.scala:245:20] reg [1:0] wb_ctrl_sel_alu1; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_sel_imm; // @[RocketCore.scala:245:20] reg wb_ctrl_alu_dw; // @[RocketCore.scala:245:20] reg [4:0] wb_ctrl_alu_fn; // @[RocketCore.scala:245:20] reg wb_ctrl_mem; // @[RocketCore.scala:245:20] reg [4:0] wb_ctrl_mem_cmd; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs1; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs3; // @[RocketCore.scala:245:20] reg wb_ctrl_wfd; // @[RocketCore.scala:245:20] reg wb_ctrl_mul; // @[RocketCore.scala:245:20] reg wb_ctrl_div; // @[RocketCore.scala:245:20] reg wb_ctrl_wxd; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_csr; // @[RocketCore.scala:245:20] reg wb_ctrl_fence_i; // @[RocketCore.scala:245:20] reg wb_ctrl_fence; // @[RocketCore.scala:245:20] reg wb_ctrl_amo; // @[RocketCore.scala:245:20] reg wb_ctrl_dp; // @[RocketCore.scala:245:20] reg wb_ctrl_vec; // @[RocketCore.scala:245:20] reg ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35] reg ex_reg_valid; // @[RocketCore.scala:248:35] reg ex_reg_rvc; // @[RocketCore.scala:249:35] reg [1:0] ex_reg_btb_resp_cfiType; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_taken; // @[RocketCore.scala:250:35] reg [1:0] ex_reg_btb_resp_mask; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_bridx; // @[RocketCore.scala:250:35] reg [38:0] ex_reg_btb_resp_target; // @[RocketCore.scala:250:35] reg [4:0] ex_reg_btb_resp_entry; // @[RocketCore.scala:250:35] reg [7:0] ex_reg_btb_resp_bht_history; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_bht_value; // @[RocketCore.scala:250:35] reg ex_reg_xcpt; // @[RocketCore.scala:251:35] reg ex_reg_flush_pipe; // @[RocketCore.scala:252:35] reg ex_reg_load_use; // @[RocketCore.scala:253:35] reg [63:0] ex_reg_cause; // @[RocketCore.scala:254:35] wire [63:0] ex_cause = ex_reg_cause; // @[RocketCore.scala:254:35, :1278:50] reg ex_reg_replay; // @[RocketCore.scala:255:26] reg [39:0] ex_reg_pc; // @[RocketCore.scala:256:22] wire [39:0] _ex_op1_T_1 = ex_reg_pc; // @[RocketCore.scala:256:22, :474:24] reg [1:0] ex_reg_mem_size; // @[RocketCore.scala:257:28] assign io_dmem_req_bits_size_0 = ex_reg_mem_size; // @[RocketCore.scala:153:7, :257:28] reg [31:0] ex_reg_inst; // @[RocketCore.scala:259:24] reg [31:0] ex_reg_raw_inst; // @[RocketCore.scala:260:28] reg ex_reg_wphit_0; // @[RocketCore.scala:261:36] reg mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36] reg mem_reg_valid; // @[RocketCore.scala:265:36] reg mem_reg_rvc; // @[RocketCore.scala:266:36] reg [1:0] mem_reg_btb_resp_cfiType; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_cfiType_0 = mem_reg_btb_resp_cfiType; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_taken_0 = mem_reg_btb_resp_taken; // @[RocketCore.scala:153:7, :267:36] wire _mem_direction_misprediction_T = mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36, :627:85] reg [1:0] mem_reg_btb_resp_mask; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_mask_0 = mem_reg_btb_resp_mask; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_bridx; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bridx_0 = mem_reg_btb_resp_bridx; // @[RocketCore.scala:153:7, :267:36] reg [38:0] mem_reg_btb_resp_target; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_target_0 = mem_reg_btb_resp_target; // @[RocketCore.scala:153:7, :267:36] reg [4:0] mem_reg_btb_resp_entry; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_entry_0 = mem_reg_btb_resp_entry; // @[RocketCore.scala:153:7, :267:36] reg [7:0] mem_reg_btb_resp_bht_history; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bht_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36] assign io_imem_bht_update_bits_prediction_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_bht_value; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bht_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36] assign io_imem_bht_update_bits_prediction_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_xcpt; // @[RocketCore.scala:268:36] reg mem_reg_replay; // @[RocketCore.scala:269:36] reg mem_reg_flush_pipe; // @[RocketCore.scala:270:36] reg [63:0] mem_reg_cause; // @[RocketCore.scala:271:36] reg mem_reg_slow_bypass; // @[RocketCore.scala:272:36] wire mem_mem_cmd_bh = mem_reg_slow_bypass; // @[RocketCore.scala:272:36, :995:41] reg mem_reg_load; // @[RocketCore.scala:273:36] reg mem_reg_store; // @[RocketCore.scala:274:36] reg mem_reg_set_vconfig; // @[RocketCore.scala:275:36] reg mem_reg_sfence; // @[RocketCore.scala:276:27] reg [39:0] mem_reg_pc; // @[RocketCore.scala:277:23] wire [39:0] _mem_br_target_T = mem_reg_pc; // @[RocketCore.scala:277:23, :615:34] reg [31:0] mem_reg_inst; // @[RocketCore.scala:278:25] reg [1:0] mem_reg_mem_size; // @[RocketCore.scala:279:29] reg mem_reg_hls_or_dv; // @[RocketCore.scala:280:30] reg [31:0] mem_reg_raw_inst; // @[RocketCore.scala:281:29] reg [63:0] mem_reg_wdata; // @[RocketCore.scala:282:26] wire [63:0] _mem_int_wdata_T_3 = mem_reg_wdata; // @[RocketCore.scala:282:26, :624:111] reg [63:0] mem_reg_rs2; // @[RocketCore.scala:283:24] reg mem_br_taken; // @[RocketCore.scala:284:25] assign io_imem_bht_update_bits_taken_0 = mem_br_taken; // @[RocketCore.scala:153:7, :284:25] wire _take_pc_mem_T_3; // @[RocketCore.scala:629:49] wire take_pc_mem; // @[RocketCore.scala:285:25] reg mem_reg_wphit_0; // @[RocketCore.scala:286:35] reg wb_reg_valid; // @[RocketCore.scala:288:35] reg wb_reg_xcpt; // @[RocketCore.scala:289:35] reg wb_reg_replay; // @[RocketCore.scala:290:35] reg wb_reg_flush_pipe; // @[RocketCore.scala:291:35] reg [63:0] wb_reg_cause; // @[RocketCore.scala:292:35] reg wb_reg_set_vconfig; // @[RocketCore.scala:293:35] reg wb_reg_sfence; // @[RocketCore.scala:294:26] reg [39:0] wb_reg_pc; // @[RocketCore.scala:295:22] reg [1:0] wb_reg_mem_size; // @[RocketCore.scala:296:28] reg wb_reg_hls_or_dv; // @[RocketCore.scala:297:29] reg wb_reg_hfence_v; // @[RocketCore.scala:298:28] assign io_imem_sfence_bits_hv_0 = wb_reg_hfence_v; // @[RocketCore.scala:153:7, :298:28] reg wb_reg_hfence_g; // @[RocketCore.scala:299:28] assign io_imem_sfence_bits_hg_0 = wb_reg_hfence_g; // @[RocketCore.scala:153:7, :299:28] reg [31:0] wb_reg_inst; // @[RocketCore.scala:300:24] wire [31:0] _io_rocc_cmd_bits_inst_WIRE_1 = wb_reg_inst; // @[RocketCore.scala:300:24, :1159:48] reg [31:0] wb_reg_raw_inst; // @[RocketCore.scala:301:28] reg [63:0] wb_reg_wdata; // @[RocketCore.scala:302:25] assign io_rocc_cmd_bits_rs1 = wb_reg_wdata; // @[RocketCore.scala:153:7, :302:25] wire [63:0] _rf_wdata_T_3 = wb_reg_wdata; // @[RocketCore.scala:302:25, :822:21] reg [63:0] wb_reg_rs2; // @[RocketCore.scala:303:23] assign io_rocc_cmd_bits_rs2 = wb_reg_rs2; // @[RocketCore.scala:153:7, :303:23] wire _take_pc_wb_T_2; // @[RocketCore.scala:762:53] wire take_pc_wb; // @[RocketCore.scala:304:24] reg wb_reg_wphit_0; // @[RocketCore.scala:305:35] assign io_bpwatch_0_valid_0_0 = wb_reg_wphit_0; // @[RocketCore.scala:153:7, :305:35] assign take_pc_mem_wb = take_pc_wb \| take_pc_mem; // @[RocketCore.scala:285:25, :304:24, :307:35] assign io_imem_req_valid_0 = take_pc_mem_wb; // @[RocketCore.scala:153:7, :307:35] wire id_ctrl_decoder_0; // @[Decode.scala:50:77] wire id_ctrl_decoder_1; // @[Decode.scala:50:77] wire id_ctrl_decoder_2; // @[Decode.scala:50:77] wire id_ctrl_decoder_3; // @[Decode.scala:50:77] wire _id_illegal_insn_T_32 = id_ctrl_rocc; // @[RocketCore.scala:321:21, :391:18] wire id_ctrl_decoder_4; // @[Decode.scala:50:77] wire id_ctrl_decoder_5; // @[Decode.scala:50:77] wire id_ctrl_decoder_6; // @[Decode.scala:50:77] wire id_ctrl_decoder_7; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_8; // @[Decode.scala:50:77] wire [1:0] id_ctrl_decoder_9; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_10; // @[Decode.scala:50:77] wire id_ctrl_decoder_11; // @[Decode.scala:50:77] wire [4:0] id_ctrl_decoder_12; // @[Decode.scala:50:77] wire id_ctrl_decoder_13; // @[Decode.scala:50:77] wire [4:0] id_ctrl_decoder_14; // @[Decode.scala:50:77] wire id_ctrl_decoder_15; // @[Decode.scala:50:77] wire id_ctrl_decoder_16; // @[Decode.scala:50:77] wire id_ctrl_decoder_17; // @[Decode.scala:50:77] wire id_ctrl_decoder_18; // @[Decode.scala:50:77] wire id_ctrl_decoder_19; // @[Decode.scala:50:77] wire id_ctrl_decoder_20; // @[Decode.scala:50:77] wire id_ctrl_decoder_21; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_22; // @[Decode.scala:50:77] wire id_ctrl_decoder_23; // @[Decode.scala:50:77] wire id_ctrl_decoder_24; // @[Decode.scala:50:77] wire id_ctrl_decoder_25; // @[Decode.scala:50:77] wire _id_do_fence_T = id_ctrl_fence; // @[RocketCore.scala:321:21, :410:64] wire id_ctrl_decoder_26; // @[Decode.scala:50:77] wire id_ctrl_legal; // @[RocketCore.scala:321:21] wire id_ctrl_fp; // @[RocketCore.scala:321:21] wire id_ctrl_branch; // @[RocketCore.scala:321:21] wire id_ctrl_jal; // @[RocketCore.scala:321:21] wire id_ctrl_jalr; // @[RocketCore.scala:321:21] wire id_ctrl_rxs2; // @[RocketCore.scala:321:21] wire id_ctrl_rxs1; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_sel_alu2; // @[RocketCore.scala:321:21] wire [1:0] id_ctrl_sel_alu1; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_sel_imm; // @[RocketCore.scala:321:21] wire id_ctrl_alu_dw; // @[RocketCore.scala:321:21] wire [4:0] id_ctrl_alu_fn; // @[RocketCore.scala:321:21] wire id_ctrl_mem; // @[RocketCore.scala:321:21] wire [4:0] id_ctrl_mem_cmd; // @[RocketCore.scala:321:21] wire id_ctrl_rfs1; // @[RocketCore.scala:321:21] wire id_ctrl_rfs2; // @[RocketCore.scala:321:21] wire id_ctrl_rfs3; // @[RocketCore.scala:321:21] wire id_ctrl_wfd; // @[RocketCore.scala:321:21] wire id_ctrl_mul; // @[RocketCore.scala:321:21] wire id_ctrl_div; // @[RocketCore.scala:321:21] wire id_ctrl_wxd; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_csr; // @[RocketCore.scala:321:21] wire id_ctrl_fence_i; // @[RocketCore.scala:321:21] wire id_ctrl_amo; // @[RocketCore.scala:321:21] wire id_ctrl_dp; // @[RocketCore.scala:321:21] wire [31:0] id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22] wire [31:0] id_ctrl_decoder_decoded_invInputs = ~id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [41:0] id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [41:0] id_ctrl_decoder_decoded; // @[pla.scala:81:23] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T = {id_ctrl_decoder_decoded_andMatrixOutputs_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_99_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_102_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_9_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_29_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_139_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_117_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_4 = id_ctrl_decoder_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_96_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_35_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_182_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_128_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_67_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_78_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_190_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_7_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_98_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_32_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_71_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [4:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_181_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_16 = id_ctrl_decoder_decoded_andMatrixOutputs_181_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_145_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_143_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_20_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_22_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_97_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_39_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_131_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_191_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_63 = id_ctrl_decoder_decoded_andMatrixOutputs_191_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_164_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_64 = id_ctrl_decoder_decoded_andMatrixOutputs_164_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_55_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_90_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_30_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_26_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_175_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_77_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_21_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_5 = id_ctrl_decoder_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_121_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_61_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_105_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_24_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_165_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_160_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_95_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_56_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_16_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_185_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_6 = id_ctrl_decoder_decoded_andMatrixOutputs_185_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_140_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_53_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_193_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_92_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_17_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_129_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_177_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_123_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_14_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_27 = id_ctrl_decoder_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_132_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_49_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_155_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_7 = id_ctrl_decoder_decoded_andMatrixOutputs_155_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_184_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_148_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_115_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_162_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_44_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_126_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_150_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_161_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_133_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_179_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_5_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_88_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_94_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_66_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_125_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_91_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_112_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_170_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_146_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_168_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_2_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_15_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_176_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_172_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_76_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_87_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_144_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_36_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_41_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_8_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_104_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_73_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_189_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_28_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_0_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_60_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_48_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_167_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_163_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_137_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_74_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_59_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_152_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_47_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_103_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_83_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_28 = id_ctrl_decoder_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_31_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_13_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_111_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_65_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_124_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_50_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_6_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_134_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_153_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_109_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_187_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_45_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_79_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_159_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_34_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_86_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_10_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_93_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_180_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_43_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_135_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_3_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_188_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_4_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_25_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_58_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_147_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_27_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_52_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_138_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_178_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_173_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_120_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_19_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_64_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_142_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_11_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_46_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_141_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_114_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_70_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_72_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_174_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_81_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_130_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_157_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_68_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_42_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_54_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_63_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_69_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_183_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_51_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_136_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_127_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_151_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_1_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_100_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_106_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_186_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_18_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_108_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_89_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_62_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_149_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_171_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_37_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = id_ctrl_decoder_decoded_plaInput[23]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_169}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_122_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_169; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_170}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_82_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_170; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167}; // @[pla.scala:98:53] wire [31:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_171}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_119_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_171; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_172}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_169_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_172; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_173}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_57_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_173; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_174}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_80_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_174; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_175}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_166_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_175; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_176}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_154_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_176; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_177}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_192_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_177; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_178}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_38_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_178; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_179}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_158_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_179; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_180}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_110_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_180; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_181}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_23_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_181; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_182}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_101_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_182; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_183}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_118_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_183; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_184}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_116_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_184; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_185}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_156_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_185; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_186}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_113_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_186; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_187}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_107_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_187; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_188}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_84_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_188; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_189}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_33_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_189; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_190}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_85_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_190; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_191}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_40_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_191; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_192}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_12_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_192; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_lo_193}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_75_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_193; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_118_2, id_ctrl_decoder_decoded_andMatrixOutputs_85_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_114_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_86_2, id_ctrl_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_148_2, id_ctrl_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [11:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T = {id_ctrl_decoder_decoded_orMatrixOutputs_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_1 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _GEN = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_1 = _GEN; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6 = _GEN; // @[pla.scala:114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_3 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_47_2, id_ctrl_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_55_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_9 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_0 = {id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_154_2, id_ctrl_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_57_2, id_ctrl_decoder_decoded_andMatrixOutputs_80_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_1; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = _GEN_1; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = _GEN_1; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_24; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_24 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3 = _GEN_2; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = _GEN_3; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = _GEN_3; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4 = _GEN_3; // @[pla.scala:114:19] wire [1:0] _GEN_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = _GEN_4; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = _GEN_4; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3 = _GEN_4; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = _GEN_5; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3 = _GEN_5; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_98_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = _GEN_6; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = _GEN_6; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = _GEN_6; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = _GEN_7; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [45:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_11 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_176_2, id_ctrl_decoder_decoded_andMatrixOutputs_172_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_13 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_116_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_72_2, id_ctrl_decoder_decoded_andMatrixOutputs_81_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_157_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_45_2, id_ctrl_decoder_decoded_andMatrixOutputs_114_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_153_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3 = _GEN_11; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_187_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_77_2, id_ctrl_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_181_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = _GEN_12; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_15 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = _GEN_13; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = _GEN_13; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = _GEN_13; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_123_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_22_2, id_ctrl_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [12:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_18 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_70_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = _GEN_14; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = _GEN_14; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_124_2, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_20 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_65_2, id_ctrl_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_177_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_22 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_24 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_23; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_169_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_10; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_10 = _GEN_15; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = _GEN_15; // @[pla.scala:114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_26 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_25; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_74_2, id_ctrl_decoder_decoded_andMatrixOutputs_111_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_102_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [8:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_30 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_167_2, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_104_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_94_2, id_ctrl_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_56_2, id_ctrl_decoder_decoded_andMatrixOutputs_179_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = _GEN_16; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19] wire [14:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_32 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_64_2, id_ctrl_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_138_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = _GEN_17; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = _GEN_17; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_43_2, id_ctrl_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_73_2, id_ctrl_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_168_2, id_ctrl_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_112_2, id_ctrl_decoder_decoded_andMatrixOutputs_170_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_39_2, id_ctrl_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19] wire [17:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_34 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_5_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_150_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19] wire [10:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_36 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_54_2, id_ctrl_decoder_decoded_andMatrixOutputs_183_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_147_2, id_ctrl_decoder_decoded_andMatrixOutputs_178_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_48_2, id_ctrl_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_129_2, id_ctrl_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19] wire [9:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_38 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_37; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_171_2, id_ctrl_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_108_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = _GEN_18; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = _GEN_18; // @[pla.scala:114:19] wire [1:0] _GEN_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_106_2, id_ctrl_decoder_decoded_andMatrixOutputs_186_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = _GEN_19; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3 = _GEN_19; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_11_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19] wire [13:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_40 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_62_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_151_2, id_ctrl_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_135_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_34_2, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_189_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_164_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_78_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19] wire [35:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_42 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_66_2, id_ctrl_decoder_decoded_andMatrixOutputs_146_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_44 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}] wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_46 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] _GEN_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = _GEN_22; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN_22; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = _GEN_22; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = _GEN_23; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = _GEN_23; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_91_2, id_ctrl_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_24_2, id_ctrl_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19] wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_48 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_116_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = _GEN_24; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = _GEN_24; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = _GEN_25; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_31_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = _GEN_26; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = _GEN_26; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] _GEN_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = _GEN_27; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = _GEN_27; // @[pla.scala:114:19] wire [1:0] _GEN_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = _GEN_28; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = _GEN_28; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = _GEN_28; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = _GEN_29; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4 = _GEN_29; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] _GEN_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = _GEN_30; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = _GEN_30; // @[pla.scala:114:19] wire [1:0] _GEN_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = _GEN_31; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = _GEN_31; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = _GEN_31; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = _GEN_32; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = _GEN_32; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19] wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_50 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_49; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_182_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_189_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_52 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_120_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19] wire [1:0] _GEN_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_140_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = _GEN_33; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = _GEN_33; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = _GEN_33; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_91_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_29_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:114:19] wire [12:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19] wire [24:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_54 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_89_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] _GEN_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_159_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = _GEN_34; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = _GEN_34; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = _GEN_34; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_146_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_190_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19] wire [34:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_56 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_68_2, id_ctrl_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_24, id_ctrl_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_58 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19] wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_25, id_ctrl_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_60 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_59; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19] wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_26, id_ctrl_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_62 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_61; // @[pla.scala:114:{19,36}] wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_66 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_65; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_158_2, id_ctrl_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = _GEN_35; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = _GEN_35; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_136_2, id_ctrl_decoder_decoded_andMatrixOutputs_192_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_141_2, id_ctrl_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_50_2, id_ctrl_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_175_2, id_ctrl_decoder_decoded_andMatrixOutputs_193_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19] wire [20:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_27, id_ctrl_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_68 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_67; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_113_2, id_ctrl_decoder_decoded_andMatrixOutputs_107_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_173_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_111_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:114:19] wire [33:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_152_2, id_ctrl_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_90_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_131_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_143_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_117_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:114:19] wire [34:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19] wire [68:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_28, id_ctrl_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_70 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_69; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_3, _id_ctrl_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_9, _id_ctrl_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5 = {1'h0, _id_ctrl_decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5, _id_ctrl_decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_16, _id_ctrl_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_22, _id_ctrl_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_27, _id_ctrl_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_32, _id_ctrl_decoder_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:102:36] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:102:36] wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_36, _id_ctrl_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_42, _id_ctrl_decoder_decoded_orMatrixOutputs_T_40}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_38}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_46, _id_ctrl_decoder_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_52, _id_ctrl_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_56, _id_ctrl_decoder_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_62, _id_ctrl_decoder_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_66, _id_ctrl_decoder_decoded_orMatrixOutputs_T_64}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_70, _id_ctrl_decoder_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6, 1'h0}; // @[pla.scala:102:36] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:102:36] wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:102:36] wire [41:0] id_ctrl_decoder_decoded_orMatrixOutputs = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_29, id_ctrl_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:102:36] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T = id_ctrl_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_1 = id_ctrl_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_2 = id_ctrl_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_3 = id_ctrl_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_4 = id_ctrl_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_5 = id_ctrl_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_6 = id_ctrl_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_7 = id_ctrl_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_8 = id_ctrl_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_9 = id_ctrl_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_10 = id_ctrl_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_11 = id_ctrl_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_12 = id_ctrl_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_13 = id_ctrl_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_14 = id_ctrl_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_15 = id_ctrl_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_16 = id_ctrl_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_17 = id_ctrl_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_18 = id_ctrl_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_19 = id_ctrl_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_20 = id_ctrl_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_21 = id_ctrl_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_22 = id_ctrl_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_23 = id_ctrl_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_24 = id_ctrl_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_25 = id_ctrl_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_26 = id_ctrl_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_27 = id_ctrl_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_28 = id_ctrl_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_29 = id_ctrl_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_30 = id_ctrl_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_31 = id_ctrl_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_32 = id_ctrl_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_33 = id_ctrl_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_34 = id_ctrl_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_35 = id_ctrl_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_36 = id_ctrl_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_37 = id_ctrl_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_38 = id_ctrl_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_39 = id_ctrl_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_40 = id_ctrl_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_41 = id_ctrl_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_1, _id_ctrl_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_4, _id_ctrl_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_6, _id_ctrl_decoder_decoded_invMatrixOutputs_T_5}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_9, _id_ctrl_decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_11, _id_ctrl_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_14, _id_ctrl_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_17, _id_ctrl_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_20, _id_ctrl_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_22, _id_ctrl_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_25, _id_ctrl_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_27, _id_ctrl_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_30, _id_ctrl_decoder_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_32, _id_ctrl_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_35, _id_ctrl_decoder_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_38, _id_ctrl_decoder_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_41, _id_ctrl_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign id_ctrl_decoder_decoded_invMatrixOutputs = {id_ctrl_decoder_decoded_invMatrixOutputs_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign id_ctrl_decoder_decoded = id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign id_ctrl_decoder_0 = id_ctrl_decoder_decoded[41]; // @[pla.scala:81:23] assign id_ctrl_legal = id_ctrl_decoder_0; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_1 = id_ctrl_decoder_decoded[40]; // @[pla.scala:81:23] assign id_ctrl_fp = id_ctrl_decoder_1; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_2 = id_ctrl_decoder_decoded[39]; // @[pla.scala:81:23] assign id_ctrl_rocc = id_ctrl_decoder_2; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_3 = id_ctrl_decoder_decoded[38]; // @[pla.scala:81:23] assign id_ctrl_branch = id_ctrl_decoder_3; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_4 = id_ctrl_decoder_decoded[37]; // @[pla.scala:81:23] assign id_ctrl_jal = id_ctrl_decoder_4; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_5 = id_ctrl_decoder_decoded[36]; // @[pla.scala:81:23] assign id_ctrl_jalr = id_ctrl_decoder_5; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_6 = id_ctrl_decoder_decoded[35]; // @[pla.scala:81:23] assign id_ctrl_rxs2 = id_ctrl_decoder_6; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_7 = id_ctrl_decoder_decoded[34]; // @[pla.scala:81:23] assign id_ctrl_rxs1 = id_ctrl_decoder_7; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_8 = id_ctrl_decoder_decoded[33:31]; // @[pla.scala:81:23] assign id_ctrl_sel_alu2 = id_ctrl_decoder_8; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_9 = id_ctrl_decoder_decoded[30:29]; // @[pla.scala:81:23] assign id_ctrl_sel_alu1 = id_ctrl_decoder_9; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_10 = id_ctrl_decoder_decoded[28:26]; // @[pla.scala:81:23] assign id_ctrl_sel_imm = id_ctrl_decoder_10; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_11 = id_ctrl_decoder_decoded[25]; // @[pla.scala:81:23] assign id_ctrl_alu_dw = id_ctrl_decoder_11; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_12 = id_ctrl_decoder_decoded[24:20]; // @[pla.scala:81:23] assign id_ctrl_alu_fn = id_ctrl_decoder_12; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_13 = id_ctrl_decoder_decoded[19]; // @[pla.scala:81:23] assign id_ctrl_mem = id_ctrl_decoder_13; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_14 = id_ctrl_decoder_decoded[18:14]; // @[pla.scala:81:23] assign id_ctrl_mem_cmd = id_ctrl_decoder_14; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_15 = id_ctrl_decoder_decoded[13]; // @[pla.scala:81:23] assign id_ctrl_rfs1 = id_ctrl_decoder_15; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_16 = id_ctrl_decoder_decoded[12]; // @[pla.scala:81:23] assign id_ctrl_rfs2 = id_ctrl_decoder_16; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_17 = id_ctrl_decoder_decoded[11]; // @[pla.scala:81:23] assign id_ctrl_rfs3 = id_ctrl_decoder_17; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_18 = id_ctrl_decoder_decoded[10]; // @[pla.scala:81:23] assign id_ctrl_wfd = id_ctrl_decoder_18; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_19 = id_ctrl_decoder_decoded[9]; // @[pla.scala:81:23] assign id_ctrl_mul = id_ctrl_decoder_19; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_20 = id_ctrl_decoder_decoded[8]; // @[pla.scala:81:23] assign id_ctrl_div = id_ctrl_decoder_20; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_21 = id_ctrl_decoder_decoded[7]; // @[pla.scala:81:23] assign id_ctrl_wxd = id_ctrl_decoder_21; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_22 = id_ctrl_decoder_decoded[6:4]; // @[pla.scala:81:23] assign id_ctrl_csr = id_ctrl_decoder_22; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_23 = id_ctrl_decoder_decoded[3]; // @[pla.scala:81:23] assign id_ctrl_fence_i = id_ctrl_decoder_23; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_24 = id_ctrl_decoder_decoded[2]; // @[pla.scala:81:23] assign id_ctrl_fence = id_ctrl_decoder_24; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_25 = id_ctrl_decoder_decoded[1]; // @[pla.scala:81:23] assign id_ctrl_amo = id_ctrl_decoder_25; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_26 = id_ctrl_decoder_decoded[0]; // @[pla.scala:81:23] assign id_ctrl_dp = id_ctrl_decoder_26; // @[RocketCore.scala:321:21] wire [4:0] id_raddr3; // @[RocketCore.scala:326:72] wire [4:0] id_raddr2; // @[RocketCore.scala:326:72] wire [4:0] _id_rs_T_7 = id_raddr2; // @[RocketCore.scala:326:72, :1320:44] wire [4:0] id_raddr1; // @[RocketCore.scala:326:72] wire [4:0] _id_rs_T_2 = id_raddr1; // @[RocketCore.scala:326:72, :1320:44] wire [4:0] id_waddr; // @[RocketCore.scala:326:72] wire _id_load_use_T_1; // @[RocketCore.scala:1001:51] wire id_load_use; // @[RocketCore.scala:332:25] reg id_reg_fence; // @[RocketCore.scala:333:29] wire [63:0] id_rs_0; // @[RocketCore.scala:1325:26] wire _id_rs_T = ~(\|id_raddr1); // @[RocketCore.scala:326:72, :1326:41] wire [4:0] _id_rs_T_3 = ~_id_rs_T_2; // @[RocketCore.scala:1320:{39,44}] wire [63:0] id_rs_1; // @[RocketCore.scala:1325:26] wire _id_rs_T_5 = ~(\|id_raddr2); // @[RocketCore.scala:326:72, :1326:41] wire [4:0] _id_rs_T_8 = ~_id_rs_T_7; // @[RocketCore.scala:1320:{39,44}] wire _ctrl_killd_T_4; // @[RocketCore.scala:1046:104] wire ctrl_killd; // @[RocketCore.scala:338:24] wire _id_npc_sign_T_1 = _ibuf_io_inst_0_bits_inst_bits[31]; // @[RocketCore.scala:311:20, :1341:44] wire _id_npc_sign_T_2 = _id_npc_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire id_npc_sign = _id_npc_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire _id_npc_b11_T_9 = id_npc_sign; // @[RocketCore.scala:1341:19, :1346:18] wire id_npc_hi_hi_hi = id_npc_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _id_npc_b30_20_T_1 = _ibuf_io_inst_0_bits_inst_bits[30:20]; // @[RocketCore.scala:311:20, :1342:41] wire [10:0] _id_npc_b30_20_T_2 = _id_npc_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] id_npc_b30_20 = {11{id_npc_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] id_npc_hi_hi_lo = id_npc_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _id_npc_b19_12_T_3 = _ibuf_io_inst_0_bits_inst_bits[19:12]; // @[RocketCore.scala:311:20, :1343:65] wire [7:0] _id_npc_b19_12_T_4 = _id_npc_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] id_npc_b19_12 = _id_npc_b19_12_T_4; // @[RocketCore.scala:1343:{21,73}] wire [7:0] id_npc_hi_lo_hi = id_npc_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _id_npc_b11_T_4 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39] wire _id_npc_b0_T_3 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39, :1352:37] wire _id_npc_b11_T_5 = _id_npc_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _id_npc_b11_T_10 = _id_npc_b11_T_5; // @[RocketCore.scala:1345:{18,44}] wire _id_npc_b11_T_7 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39] wire _id_npc_b0_T_1 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39, :1351:37] wire _id_npc_b11_T_8 = _id_npc_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire id_npc_b11 = _id_npc_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire id_npc_hi_lo_lo = id_npc_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _id_npc_b10_5_T_3 = _ibuf_io_inst_0_bits_inst_bits[30:25]; // @[RocketCore.scala:311:20, :1347:62] wire [5:0] id_npc_b10_5 = _id_npc_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _id_npc_b4_1_T_4 = _ibuf_io_inst_0_bits_inst_bits[11:8]; // @[RocketCore.scala:311:20, :1349:57] wire [3:0] _id_npc_b4_1_T_6 = _ibuf_io_inst_0_bits_inst_bits[19:16]; // @[RocketCore.scala:311:20, :1350:39] wire [3:0] _id_npc_b4_1_T_7 = _ibuf_io_inst_0_bits_inst_bits[24:21]; // @[RocketCore.scala:311:20, :1350:52] wire [3:0] _id_npc_b4_1_T_8 = _id_npc_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _id_npc_b4_1_T_9 = _id_npc_b4_1_T_8; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] id_npc_b4_1 = _id_npc_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _id_npc_b0_T_5 = _ibuf_io_inst_0_bits_inst_bits[15]; // @[RocketCore.scala:311:20, :1353:37] wire [9:0] id_npc_lo_hi = {id_npc_b10_5, id_npc_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] id_npc_lo = {id_npc_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] id_npc_hi_lo = {id_npc_hi_lo_hi, id_npc_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] id_npc_hi_hi = {id_npc_hi_hi_hi, id_npc_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] id_npc_hi = {id_npc_hi_hi, id_npc_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _id_npc_T_1 = {id_npc_hi, id_npc_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _id_npc_T_2 = _id_npc_T_1; // @[RocketCore.scala:1355:{8,53}] wire [39:0] _id_npc_T; // @[RocketCore.scala:339:28] wire [40:0] _id_npc_T_3 = {_id_npc_T[39], _id_npc_T} + {{9{_id_npc_T_2[31]}}, _id_npc_T_2}; // @[RocketCore.scala:339:{28,35}, :1355:53] wire [39:0] _id_npc_T_4 = _id_npc_T_3[39:0]; // @[RocketCore.scala:339:35] wire [39:0] _id_npc_T_5 = _id_npc_T_4; // @[RocketCore.scala:339:35] wire [39:0] id_npc = _id_npc_T_5; // @[RocketCore.scala:339:{35,65}] wire _GEN_36 = id_ctrl_csr == 3'h6; // @[package.scala:16:47] wire _id_csr_en_T; // @[package.scala:16:47] assign _id_csr_en_T = _GEN_36; // @[package.scala:16:47] wire _id_csr_ren_T; // @[package.scala:16:47] assign _id_csr_ren_T = _GEN_36; // @[package.scala:16:47] wire _id_csr_en_T_1 = &id_ctrl_csr; // @[package.scala:16:47] wire _id_csr_en_T_2 = id_ctrl_csr == 3'h5; // @[package.scala:16:47] wire _id_csr_en_T_3 = _id_csr_en_T \| _id_csr_en_T_1; // @[package.scala:16:47, :81:59] wire id_csr_en = _id_csr_en_T_3 \| _id_csr_en_T_2; // @[package.scala:16:47, :81:59] wire id_system_insn = id_ctrl_csr == 3'h4; // @[RocketCore.scala:321:21, :343:36] wire _id_csr_ren_T_1 = &id_ctrl_csr; // @[package.scala:16:47] wire _id_csr_ren_T_2 = _id_csr_ren_T \| _id_csr_ren_T_1; // @[package.scala:16:47, :81:59] wire _id_csr_ren_T_3 = _ibuf_io_inst_0_bits_inst_rs1 == 5'h0; // @[RocketCore.scala:311:20, :344:81] wire id_csr_ren = _id_csr_ren_T_2 & _id_csr_ren_T_3; // @[package.scala:81:59] wire _id_csr_T = id_system_insn & id_ctrl_mem; // @[RocketCore.scala:321:21, :343:36, :345:35] wire [2:0] _id_csr_T_1 = id_csr_ren ? 3'h2 : id_ctrl_csr; // @[RocketCore.scala:321:21, :344:54, :345:61] wire [2:0] id_csr = _id_csr_T ? 3'h0 : _id_csr_T_1; // @[RocketCore.scala:345:{19,35,61}] wire _id_csr_flush_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54] wire _id_csr_flush_T_1 = id_csr_en & _id_csr_flush_T; // @[package.scala:81:59] wire _id_csr_flush_T_2 = _id_csr_flush_T_1 & _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19, :346:{51,66}] wire id_csr_flush = id_system_insn \| _id_csr_flush_T_2; // @[RocketCore.scala:343:36, :346:{37,66}] wire [31:0] _id_set_vconfig_T = _ibuf_io_inst_0_bits_inst_bits & 32'h8000707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_1 = _id_set_vconfig_T == 32'h7057; // @[RocketCore.scala:347:100] wire [31:0] _id_set_vconfig_T_2 = _ibuf_io_inst_0_bits_inst_bits & 32'hC000707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_3 = _id_set_vconfig_T_2 == 32'hC0007057; // @[RocketCore.scala:347:100] wire [31:0] _id_set_vconfig_T_4 = _ibuf_io_inst_0_bits_inst_bits & 32'hFE00707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_5 = _id_set_vconfig_T_4 == 32'h80007057; // @[RocketCore.scala:347:100] wire _id_set_vconfig_T_6 = _id_set_vconfig_T_1 \| _id_set_vconfig_T_3; // @[package.scala:81:59] wire _id_set_vconfig_T_7 = _id_set_vconfig_T_6 \| _id_set_vconfig_T_5; // @[package.scala:81:59] wire _id_illegal_insn_T = ~id_ctrl_legal; // @[RocketCore.scala:321:21, :381:25] wire _id_illegal_insn_T_1 = id_ctrl_mul \| id_ctrl_div; // @[RocketCore.scala:321:21, :382:18] wire _id_illegal_insn_T_2 = _csr_io_status_isa[12]; // @[RocketCore.scala:341:19, :382:55] wire _id_illegal_insn_T_3 = ~_id_illegal_insn_T_2; // @[RocketCore.scala:382:{37,55}] wire _id_illegal_insn_T_4 = _id_illegal_insn_T_1 & _id_illegal_insn_T_3; // @[RocketCore.scala:382:{18,34,37}] wire _id_illegal_insn_T_5 = _id_illegal_insn_T \| _id_illegal_insn_T_4; // @[RocketCore.scala:381:{25,40}, :382:34] wire _id_illegal_insn_T_6 = _csr_io_status_isa[0]; // @[RocketCore.scala:341:19, :383:38] wire _id_illegal_insn_T_7 = ~_id_illegal_insn_T_6; // @[RocketCore.scala:383:{20,38}] wire _id_illegal_insn_T_8 = id_ctrl_amo & _id_illegal_insn_T_7; // @[RocketCore.scala:321:21, :383:{17,20}] wire _id_illegal_insn_T_9 = _id_illegal_insn_T_5 \| _id_illegal_insn_T_8; // @[RocketCore.scala:381:40, :382:65, :383:17] wire _id_illegal_insn_T_12 = _csr_io_decode_0_fp_illegal \| _id_illegal_insn_T_11; // @[RocketCore.scala:341:19, :384:{48,70}] wire _id_illegal_insn_T_13 = id_ctrl_fp & _id_illegal_insn_T_12; // @[RocketCore.scala:321:21, :384:{16,48}] wire _id_illegal_insn_T_14 = _id_illegal_insn_T_9 \| _id_illegal_insn_T_13; // @[RocketCore.scala:382:65, :383:48, :384:16] wire _id_illegal_insn_T_17 = _id_illegal_insn_T_14; // @[RocketCore.scala:383:48, :384:88] wire _id_illegal_insn_T_18 = _csr_io_status_isa[3]; // @[RocketCore.scala:341:19, :386:37] wire _id_illegal_insn_T_19 = ~_id_illegal_insn_T_18; // @[RocketCore.scala:386:{19,37}] wire _id_illegal_insn_T_20 = id_ctrl_dp & _id_illegal_insn_T_19; // @[RocketCore.scala:321:21, :386:{16,19}] wire _id_illegal_insn_T_21 = _id_illegal_insn_T_17 \| _id_illegal_insn_T_20; // @[RocketCore.scala:384:88, :385:118, :386:16] wire _id_illegal_insn_T_22 = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51] wire _mem_npc_misaligned_T = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51, :623:46] wire _id_illegal_insn_T_23 = ~_id_illegal_insn_T_22; // @[RocketCore.scala:387:{33,51}] wire _id_illegal_insn_T_24 = _ibuf_io_inst_0_bits_rvc & _id_illegal_insn_T_23; // @[RocketCore.scala:311:20, :387:{30,33}] wire _id_illegal_insn_T_25 = _id_illegal_insn_T_21 \| _id_illegal_insn_T_24; // @[RocketCore.scala:385:118, :386:47, :387:30] wire _id_illegal_insn_T_27 = _id_illegal_insn_T_25; // @[RocketCore.scala:386:47, :387:61] wire _id_illegal_insn_T_29 = _id_illegal_insn_T_27; // @[RocketCore.scala:387:61, :388:39] wire _id_illegal_insn_T_31 = _id_illegal_insn_T_29; // @[RocketCore.scala:388:39, :389:39] wire _id_illegal_insn_T_33 = _id_illegal_insn_T_31 \| _id_illegal_insn_T_32; // @[RocketCore.scala:389:39, :390:37, :391:18] wire _id_illegal_insn_T_34 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :392:52] wire _id_illegal_insn_T_35 = _id_illegal_insn_T_34 & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :392:{52,64}] wire _id_illegal_insn_T_36 = _csr_io_decode_0_read_illegal \| _id_illegal_insn_T_35; // @[RocketCore.scala:341:19, :392:{49,64}] wire _id_illegal_insn_T_37 = id_csr_en & _id_illegal_insn_T_36; // @[package.scala:81:59] wire _id_illegal_insn_T_38 = _id_illegal_insn_T_33 \| _id_illegal_insn_T_37; // @[RocketCore.scala:390:37, :391:51, :392:15] wire _id_illegal_insn_T_39 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5] wire _id_illegal_insn_T_40 = id_system_insn & _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19, :343:36, :393:50] wire _id_illegal_insn_T_41 = _id_illegal_insn_T_39 & _id_illegal_insn_T_40; // @[RocketCore.scala:393:{5,31,50}] wire id_illegal_insn = _id_illegal_insn_T_38 \| _id_illegal_insn_T_41; // @[RocketCore.scala:391:51, :392:99, :393:31] wire _id_virtual_insn_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :395:22] wire _id_virtual_insn_T_1 = _id_virtual_insn_T & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :395:{22,34}] wire _id_virtual_insn_T_2 = ~_id_virtual_insn_T_1; // @[RocketCore.scala:395:{20,34}] wire _id_virtual_insn_T_3 = id_csr_en & _id_virtual_insn_T_2; // @[package.scala:81:59] wire _id_virtual_insn_T_4 = _id_virtual_insn_T_3 & _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19, :395:{17,69}] wire _id_virtual_insn_T_5 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5, :396:7] wire _id_virtual_insn_T_6 = _id_virtual_insn_T_5 & id_system_insn; // @[RocketCore.scala:343:36, :396:{7,33}] wire _id_virtual_insn_T_7 = _id_virtual_insn_T_6 & _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19, :396:{33,51}] wire _id_virtual_insn_T_8 = _id_virtual_insn_T_4 \| _id_virtual_insn_T_7; // @[RocketCore.scala:395:{69,113}, :396:51] wire id_virtual_insn = id_ctrl_legal & _id_virtual_insn_T_8; // @[RocketCore.scala:321:21, :394:39, :395:113] wire id_amo_aq = _ibuf_io_inst_0_bits_inst_bits[26]; // @[RocketCore.scala:311:20, :398:29] wire id_amo_rl = _ibuf_io_inst_0_bits_inst_bits[25]; // @[RocketCore.scala:311:20, :399:29] wire [3:0] id_fence_pred = _ibuf_io_inst_0_bits_inst_bits[27:24]; // @[RocketCore.scala:311:20, :400:33] wire [3:0] id_fence_succ = _ibuf_io_inst_0_bits_inst_bits[23:20]; // @[RocketCore.scala:311:20, :401:33] wire _id_fence_next_T = id_ctrl_amo & id_amo_aq; // @[RocketCore.scala:321:21, :398:29, :402:52] wire id_fence_next = id_ctrl_fence \| _id_fence_next_T; // @[RocketCore.scala:321:21, :402:{37,52}] wire _id_mem_busy_T = ~io_dmem_ordered_0; // @[RocketCore.scala:153:7, :403:21] wire id_mem_busy = _id_mem_busy_T \| io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :403:{21,38}] wire _id_rocc_busy_T = ex_reg_valid & ex_ctrl_rocc; // @[RocketCore.scala:243:20, :248:35, :406:35] wire _id_rocc_busy_T_1 = _id_rocc_busy_T; // @[RocketCore.scala:406:{19,35}] wire _id_rocc_busy_T_2 = mem_reg_valid & mem_ctrl_rocc; // @[RocketCore.scala:244:21, :265:36, :407:20] wire _id_rocc_busy_T_3 = _id_rocc_busy_T_1 \| _id_rocc_busy_T_2; // @[RocketCore.scala:406:{19,51}, :407:20] wire _GEN_37 = wb_reg_valid & wb_ctrl_rocc; // @[RocketCore.scala:245:20, :288:35, :407:53] wire _id_rocc_busy_T_4; // @[RocketCore.scala:407:53] assign _id_rocc_busy_T_4 = _GEN_37; // @[RocketCore.scala:407:53] wire _replay_wb_rocc_T; // @[RocketCore.scala:758:37] assign _replay_wb_rocc_T = _GEN_37; // @[RocketCore.scala:407:53, :758:37] wire _io_rocc_cmd_valid_T; // @[RocketCore.scala:1156:37] assign _io_rocc_cmd_valid_T = _GEN_37; // @[RocketCore.scala:407:53, :1156:37] wire _id_rocc_busy_T_5 = _id_rocc_busy_T_3 \| _id_rocc_busy_T_4; // @[RocketCore.scala:406:51, :407:{37,53}] wire _id_csr_rocc_write_T_1 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :408:103] wire _id_do_fence_T_4 = id_ctrl_amo & id_amo_rl; // @[RocketCore.scala:321:21, :399:29, :412:33] wire _id_do_fence_T_5 = _id_do_fence_T_4 \| id_ctrl_fence_i; // @[RocketCore.scala:321:21, :412:{33,46}] wire _id_do_fence_T_6 = id_ctrl_mem \| id_ctrl_rocc; // @[RocketCore.scala:321:21, :412:97] wire _id_do_fence_T_7 = id_reg_fence & _id_do_fence_T_6; // @[RocketCore.scala:333:29, :412:{81,97}] wire _id_do_fence_T_8 = _id_do_fence_T_5 \| _id_do_fence_T_7; // @[RocketCore.scala:412:{46,65,81}] wire _id_do_fence_T_9 = id_mem_busy & _id_do_fence_T_8; // @[RocketCore.scala:403:38, :412:{17,65}] wire _id_do_fence_T_10 = _id_do_fence_T_9; // @[RocketCore.scala:411:34, :412:17] wire id_do_fence = _id_do_fence_T_10; // @[RocketCore.scala:410:32, :411:34] wire [38:0] _mem_npc_T_1 = mem_reg_wdata[38:0]; // @[RocketCore.scala:282:26, :418:13, :1295:16] wire id_xcpt = _csr_io_interrupt \| _bpu_io_debug_if \| _bpu_io_xcpt_if \| _ibuf_io_inst_0_bits_xcpt0_pf_inst \| _ibuf_io_inst_0_bits_xcpt0_gf_inst \| _ibuf_io_inst_0_bits_xcpt0_ae_inst \| _ibuf_io_inst_0_bits_xcpt1_pf_inst \| _ibuf_io_inst_0_bits_xcpt1_gf_inst \| _ibuf_io_inst_0_bits_xcpt1_ae_inst \| id_virtual_insn \| id_illegal_insn; // @[RocketCore.scala:311:20, :341:19, :392:99, :394:39, :414:19, :1278:{14,35}] wire [63:0] id_cause = _csr_io_interrupt ? _csr_io_interrupt_cause : {59'h0, _bpu_io_debug_if ? 5'hE : _bpu_io_xcpt_if ? 5'h3 : _ibuf_io_inst_0_bits_xcpt0_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt0_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt0_ae_inst ? 5'h1 : _ibuf_io_inst_0_bits_xcpt1_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt1_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt1_ae_inst ? 5'h1 : id_virtual_insn ? 5'h16 : 5'h2}; // @[Mux.scala:50:70] wire [4:0] _ex_waddr_T = ex_reg_inst[11:7]; // @[RocketCore.scala:259:24, :453:29] wire [4:0] ex_waddr = _ex_waddr_T; // @[RocketCore.scala:453:{29,36}] wire [4:0] _mem_waddr_T = mem_reg_inst[11:7]; // @[RocketCore.scala:278:25, :454:31] wire [4:0] mem_waddr = _mem_waddr_T; // @[RocketCore.scala:454:{31,38}] wire [4:0] _wb_waddr_T = wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :455:29] wire [4:0] wb_waddr = _wb_waddr_T; // @[RocketCore.scala:455:{29,36}] wire [4:0] coreMonitorBundle_wrdst = wb_waddr; // @[RocketCore.scala:455:36, :1186:31] wire bypass_sources_1_1 = ex_reg_valid & ex_ctrl_wxd; // @[RocketCore.scala:243:20, :248:35, :458:19] wire _GEN_38 = mem_reg_valid & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :265:36, :459:20] wire _bypass_sources_T; // @[RocketCore.scala:459:20] assign _bypass_sources_T = _GEN_38; // @[RocketCore.scala:459:20] wire bypass_sources_3_1; // @[RocketCore.scala:460:20] assign bypass_sources_3_1 = _GEN_38; // @[RocketCore.scala:459:20, :460:20] wire _dcache_kill_mem_T; // @[RocketCore.scala:695:39] assign _dcache_kill_mem_T = _GEN_38; // @[RocketCore.scala:459:20, :695:39] wire _bypass_sources_T_1 = ~mem_ctrl_mem; // @[RocketCore.scala:244:21, :459:39] wire bypass_sources_2_1 = _bypass_sources_T & _bypass_sources_T_1; // @[RocketCore.scala:459:{20,36,39}] wire _id_bypass_src_T = ~(\|id_raddr1); // @[RocketCore.scala:326:72, :461:82, :1326:41] wire id_bypass_src_0_0 = _id_bypass_src_T; // @[RocketCore.scala:461:{74,82}] wire _GEN_39 = ex_waddr == id_raddr1; // @[RocketCore.scala:326:72, :453:36, :461:82] wire _id_bypass_src_T_1; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_1 = _GEN_39; // @[RocketCore.scala:461:82] wire _data_hazard_ex_T; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T = _GEN_39; // @[RocketCore.scala:461:82, :989:70] wire _fp_data_hazard_ex_T_1; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_1 = _GEN_39; // @[RocketCore.scala:461:82, :990:90] wire id_bypass_src_0_1 = bypass_sources_1_1 & _id_bypass_src_T_1; // @[RocketCore.scala:458:19, :461:{74,82}] wire _GEN_40 = mem_waddr == id_raddr1; // @[RocketCore.scala:326:72, :454:38, :461:82] wire _id_bypass_src_T_2; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_2 = _GEN_40; // @[RocketCore.scala:461:82] wire _id_bypass_src_T_3; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_3 = _GEN_40; // @[RocketCore.scala:461:82] wire _data_hazard_mem_T; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T = _GEN_40; // @[RocketCore.scala:461:82, :998:72] wire _fp_data_hazard_mem_T_1; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_1 = _GEN_40; // @[RocketCore.scala:461:82, :999:92] wire id_bypass_src_0_2 = bypass_sources_2_1 & _id_bypass_src_T_2; // @[RocketCore.scala:459:36, :461:{74,82}] wire id_bypass_src_0_3 = bypass_sources_3_1 & _id_bypass_src_T_3; // @[RocketCore.scala:460:20, :461:{74,82}] wire _id_bypass_src_T_4 = ~(\|id_raddr2); // @[RocketCore.scala:326:72, :461:82, :1326:41] wire id_bypass_src_1_0 = _id_bypass_src_T_4; // @[RocketCore.scala:461:{74,82}] wire _GEN_41 = ex_waddr == id_raddr2; // @[RocketCore.scala:326:72, :453:36, :461:82] wire _id_bypass_src_T_5; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_5 = _GEN_41; // @[RocketCore.scala:461:82] wire _data_hazard_ex_T_2; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T_2 = _GEN_41; // @[RocketCore.scala:461:82, :989:70] wire _fp_data_hazard_ex_T_3; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_3 = _GEN_41; // @[RocketCore.scala:461:82, :990:90] wire id_bypass_src_1_1 = bypass_sources_1_1 & _id_bypass_src_T_5; // @[RocketCore.scala:458:19, :461:{74,82}] wire _GEN_42 = mem_waddr == id_raddr2; // @[RocketCore.scala:326:72, :454:38, :461:82] wire _id_bypass_src_T_6; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_6 = _GEN_42; // @[RocketCore.scala:461:82] wire _id_bypass_src_T_7; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_7 = _GEN_42; // @[RocketCore.scala:461:82] wire _data_hazard_mem_T_2; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T_2 = _GEN_42; // @[RocketCore.scala:461:82, :998:72] wire _fp_data_hazard_mem_T_3; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_3 = _GEN_42; // @[RocketCore.scala:461:82, :999:92] wire id_bypass_src_1_2 = bypass_sources_2_1 & _id_bypass_src_T_6; // @[RocketCore.scala:459:36, :461:{74,82}] wire id_bypass_src_1_3 = bypass_sources_3_1 & _id_bypass_src_T_7; // @[RocketCore.scala:460:20, :461:{74,82}] reg ex_reg_rs_bypass_0; // @[RocketCore.scala:465:29] reg ex_reg_rs_bypass_1; // @[RocketCore.scala:465:29] reg [1:0] ex_reg_rs_lsb_0; // @[RocketCore.scala:466:26] reg [1:0] ex_reg_rs_lsb_1; // @[RocketCore.scala:466:26] reg [61:0] ex_reg_rs_msb_0; // @[RocketCore.scala:467:26] reg [61:0] ex_reg_rs_msb_1; // @[RocketCore.scala:467:26] wire _ex_rs_T = ex_reg_rs_lsb_0 == 2'h1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_1 = _ex_rs_T ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}] wire _ex_rs_T_2 = ex_reg_rs_lsb_0 == 2'h2; // @[package.scala:39:86] wire [63:0] _ex_rs_T_3 = _ex_rs_T_2 ? wb_reg_wdata : _ex_rs_T_1; // @[package.scala:39:{76,86}] wire _ex_rs_T_4 = &ex_reg_rs_lsb_0; // @[package.scala:39:86] wire [63:0] _ex_rs_T_5 = _ex_rs_T_4 ? dcache_bypass_data : _ex_rs_T_3; // @[package.scala:39:{76,86}] wire [63:0] _ex_rs_T_6 = {ex_reg_rs_msb_0, ex_reg_rs_lsb_0}; // @[RocketCore.scala:466:26, :467:26, :469:69] assign ex_rs_0 = ex_reg_rs_bypass_0 ? _ex_rs_T_5 : _ex_rs_T_6; // @[package.scala:39:76] assign io_fpu_fromint_data_0 = ex_rs_0; // @[RocketCore.scala:153:7, :469:14] wire [63:0] _ex_op1_T = ex_rs_0; // @[RocketCore.scala:469:14, :473:24] wire _ex_rs_T_7 = ex_reg_rs_lsb_1 == 2'h1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_8 = _ex_rs_T_7 ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}] wire _ex_rs_T_9 = ex_reg_rs_lsb_1 == 2'h2; // @[package.scala:39:86] wire [63:0] _ex_rs_T_10 = _ex_rs_T_9 ? wb_reg_wdata : _ex_rs_T_8; // @[package.scala:39:{76,86}] wire _ex_rs_T_11 = &ex_reg_rs_lsb_1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_12 = _ex_rs_T_11 ? dcache_bypass_data : _ex_rs_T_10; // @[package.scala:39:{76,86}] wire [63:0] _ex_rs_T_13 = {ex_reg_rs_msb_1, ex_reg_rs_lsb_1}; // @[RocketCore.scala:466:26, :467:26, :469:69] wire [63:0] ex_rs_1 = ex_reg_rs_bypass_1 ? _ex_rs_T_12 : _ex_rs_T_13; // @[package.scala:39:76] wire [63:0] _ex_op2_T = ex_rs_1; // @[RocketCore.scala:469:14, :479:24] wire [63:0] mem_reg_rs2_dat_padded = ex_rs_1; // @[RocketCore.scala:469:14] wire _GEN_43 = ex_ctrl_sel_imm == 3'h5; // @[RocketCore.scala:243:20, :1341:24] wire _ex_imm_sign_T; // @[RocketCore.scala:1341:24] assign _ex_imm_sign_T = _GEN_43; // @[RocketCore.scala:1341:24] wire _ex_imm_b11_T_1; // @[RocketCore.scala:1344:40] assign _ex_imm_b11_T_1 = _GEN_43; // @[RocketCore.scala:1341:24, :1344:40] wire _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:42] assign _ex_imm_b10_5_T_1 = _GEN_43; // @[RocketCore.scala:1341:24, :1347:42] wire _ex_imm_b4_1_T_5; // @[RocketCore.scala:1350:24] assign _ex_imm_b4_1_T_5 = _GEN_43; // @[RocketCore.scala:1341:24, :1350:24] wire _ex_imm_b0_T_4; // @[RocketCore.scala:1353:22] assign _ex_imm_b0_T_4 = _GEN_43; // @[RocketCore.scala:1341:24, :1353:22] wire _ex_imm_sign_T_1 = ex_reg_inst[31]; // @[RocketCore.scala:259:24, :1341:44] wire _ex_imm_sign_T_2 = _ex_imm_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire ex_imm_sign = ~_ex_imm_sign_T & _ex_imm_sign_T_2; // @[RocketCore.scala:1341:{19,24,49}] wire ex_imm_hi_hi_hi = ex_imm_sign; // @[RocketCore.scala:1341:19, :1355:8] wire _GEN_44 = ex_ctrl_sel_imm == 3'h2; // @[RocketCore.scala:243:20, :1342:26] wire _ex_imm_b30_20_T; // @[RocketCore.scala:1342:26] assign _ex_imm_b30_20_T = _GEN_44; // @[RocketCore.scala:1342:26] wire _ex_imm_b11_T; // @[RocketCore.scala:1344:23] assign _ex_imm_b11_T = _GEN_44; // @[RocketCore.scala:1342:26, :1344:23] wire _ex_imm_b10_5_T; // @[RocketCore.scala:1347:25] assign _ex_imm_b10_5_T = _GEN_44; // @[RocketCore.scala:1342:26, :1347:25] wire _ex_imm_b4_1_T; // @[RocketCore.scala:1348:24] assign _ex_imm_b4_1_T = _GEN_44; // @[RocketCore.scala:1342:26, :1348:24] wire [10:0] _ex_imm_b30_20_T_1 = ex_reg_inst[30:20]; // @[RocketCore.scala:259:24, :1342:41] wire [10:0] _ex_imm_b30_20_T_2 = _ex_imm_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] ex_imm_b30_20 = _ex_imm_b30_20_T ? _ex_imm_b30_20_T_2 : {11{ex_imm_sign}}; // @[RocketCore.scala:1341:19, :1342:{21,26,49}] wire [10:0] ex_imm_hi_hi_lo = ex_imm_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire _ex_imm_b19_12_T = ex_ctrl_sel_imm != 3'h2; // @[RocketCore.scala:243:20, :1343:26] wire _ex_imm_b19_12_T_1 = ex_ctrl_sel_imm != 3'h3; // @[RocketCore.scala:243:20, :1343:43] wire _ex_imm_b19_12_T_2 = _ex_imm_b19_12_T & _ex_imm_b19_12_T_1; // @[RocketCore.scala:1343:{26,36,43}] wire [7:0] _ex_imm_b19_12_T_3 = ex_reg_inst[19:12]; // @[RocketCore.scala:259:24, :1343:65] wire [7:0] _ex_imm_b19_12_T_4 = _ex_imm_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] ex_imm_b19_12 = _ex_imm_b19_12_T_2 ? {8{ex_imm_sign}} : _ex_imm_b19_12_T_4; // @[RocketCore.scala:1341:19, :1343:{21,36,73}] wire [7:0] ex_imm_hi_lo_hi = ex_imm_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _ex_imm_b11_T_2 = _ex_imm_b11_T \| _ex_imm_b11_T_1; // @[RocketCore.scala:1344:{23,33,40}] wire _ex_imm_b11_T_3 = ex_ctrl_sel_imm == 3'h3; // @[RocketCore.scala:243:20, :1345:23] wire _ex_imm_b11_T_4 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39] wire _ex_imm_b0_T_3 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39, :1352:37] wire _io_dmem_req_bits_signed_T = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1136:58, :1345:39] wire _ex_imm_b11_T_5 = _ex_imm_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _GEN_45 = ex_ctrl_sel_imm == 3'h1; // @[RocketCore.scala:243:20, :1346:23] wire _ex_imm_b11_T_6; // @[RocketCore.scala:1346:23] assign _ex_imm_b11_T_6 = _GEN_45; // @[RocketCore.scala:1346:23] wire _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:41] assign _ex_imm_b4_1_T_2 = _GEN_45; // @[RocketCore.scala:1346:23, :1349:41] wire _ex_imm_b11_T_7 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39] wire _ex_imm_b0_T_1 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39, :1351:37] wire _ex_imm_b11_T_8 = _ex_imm_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _ex_imm_b11_T_9 = _ex_imm_b11_T_6 ? _ex_imm_b11_T_8 : ex_imm_sign; // @[RocketCore.scala:1341:19, :1346:{18,23,43}] wire _ex_imm_b11_T_10 = _ex_imm_b11_T_3 ? _ex_imm_b11_T_5 : _ex_imm_b11_T_9; // @[RocketCore.scala:1345:{18,23,44}, :1346:18] wire ex_imm_b11 = ~_ex_imm_b11_T_2 & _ex_imm_b11_T_10; // @[RocketCore.scala:1344:{18,33}, :1345:18] wire ex_imm_hi_lo_lo = ex_imm_b11; // @[RocketCore.scala:1344:18, :1355:8] wire _ex_imm_b10_5_T_2 = _ex_imm_b10_5_T \| _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:{25,35,42}] wire [5:0] _ex_imm_b10_5_T_3 = ex_reg_inst[30:25]; // @[RocketCore.scala:259:24, :1347:62] wire [5:0] ex_imm_b10_5 = _ex_imm_b10_5_T_2 ? 6'h0 : _ex_imm_b10_5_T_3; // @[RocketCore.scala:1347:{20,35,62}] wire _GEN_46 = ex_ctrl_sel_imm == 3'h0; // @[RocketCore.scala:243:20, :1349:24] wire _ex_imm_b4_1_T_1; // @[RocketCore.scala:1349:24] assign _ex_imm_b4_1_T_1 = _GEN_46; // @[RocketCore.scala:1349:24] wire _ex_imm_b0_T; // @[RocketCore.scala:1351:22] assign _ex_imm_b0_T = _GEN_46; // @[RocketCore.scala:1349:24, :1351:22] wire _ex_imm_b4_1_T_3 = _ex_imm_b4_1_T_1 \| _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:{24,34,41}] wire [3:0] _ex_imm_b4_1_T_4 = ex_reg_inst[11:8]; // @[RocketCore.scala:259:24, :1349:57] wire [3:0] _ex_imm_b4_1_T_6 = ex_reg_inst[19:16]; // @[RocketCore.scala:259:24, :1350:39] wire [3:0] _ex_imm_b4_1_T_7 = ex_reg_inst[24:21]; // @[RocketCore.scala:259:24, :1350:52] wire [3:0] _ex_imm_b4_1_T_8 = _ex_imm_b4_1_T_5 ? _ex_imm_b4_1_T_6 : _ex_imm_b4_1_T_7; // @[RocketCore.scala:1350:{19,24,39,52}] wire [3:0] _ex_imm_b4_1_T_9 = _ex_imm_b4_1_T_3 ? _ex_imm_b4_1_T_4 : _ex_imm_b4_1_T_8; // @[RocketCore.scala:1349:{19,34,57}, :1350:19] wire [3:0] ex_imm_b4_1 = _ex_imm_b4_1_T ? 4'h0 : _ex_imm_b4_1_T_9; // @[RocketCore.scala:1348:{19,24}, :1349:19] wire _ex_imm_b0_T_2 = ex_ctrl_sel_imm == 3'h4; // @[RocketCore.scala:243:20, :1352:22] wire _ex_imm_b0_T_5 = ex_reg_inst[15]; // @[RocketCore.scala:259:24, :1353:37] wire _ex_imm_b0_T_6 = _ex_imm_b0_T_4 & _ex_imm_b0_T_5; // @[RocketCore.scala:1353:{17,22,37}] wire _ex_imm_b0_T_7 = _ex_imm_b0_T_2 ? _ex_imm_b0_T_3 : _ex_imm_b0_T_6; // @[RocketCore.scala:1352:{17,22,37}, :1353:17] wire ex_imm_b0 = _ex_imm_b0_T ? _ex_imm_b0_T_1 : _ex_imm_b0_T_7; // @[RocketCore.scala:1351:{17,22,37}, :1352:17] wire [9:0] ex_imm_lo_hi = {ex_imm_b10_5, ex_imm_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] ex_imm_lo = {ex_imm_lo_hi, ex_imm_b0}; // @[RocketCore.scala:1351:17, :1355:8] wire [8:0] ex_imm_hi_lo = {ex_imm_hi_lo_hi, ex_imm_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] ex_imm_hi_hi = {ex_imm_hi_hi_hi, ex_imm_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] ex_imm_hi = {ex_imm_hi_hi, ex_imm_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _ex_imm_T = {ex_imm_hi, ex_imm_lo}; // @[RocketCore.scala:1355:8] wire [31:0] ex_imm = _ex_imm_T; // @[RocketCore.scala:1355:{8,53}] wire _ex_rs1shl_T = ex_reg_inst[3]; // @[RocketCore.scala:259:24, :471:34] wire [31:0] _ex_rs1shl_T_1 = ex_rs_0[31:0]; // @[RocketCore.scala:469:14, :471:47] wire [63:0] _ex_rs1shl_T_2 = _ex_rs1shl_T ? {32'h0, _ex_rs1shl_T_1} : ex_rs_0; // @[RocketCore.scala:469:14, :471:{22,34,47}] wire [1:0] _ex_rs1shl_T_3 = ex_reg_inst[14:13]; // @[RocketCore.scala:259:24, :471:79] wire [66:0] ex_rs1shl = {3'h0, _ex_rs1shl_T_2} << _ex_rs1shl_T_3; // @[RocketCore.scala:471:{22,65,79}] wire [66:0] _ex_op1_T_2 = ex_rs1shl; // @[RocketCore.scala:471:65, :475:54] wire _ex_op1_T_3 = ex_ctrl_sel_alu1 == 2'h1; // @[RocketCore.scala:243:20, :472:48] wire [63:0] _ex_op1_T_4 = _ex_op1_T_3 ? _ex_op1_T : 64'h0; // @[RocketCore.scala:472:48, :473:24] wire _ex_op1_T_5 = ex_ctrl_sel_alu1 == 2'h2; // @[RocketCore.scala:243:20, :472:48] wire [63:0] _ex_op1_T_6 = _ex_op1_T_5 ? {{24{_ex_op1_T_1[39]}}, _ex_op1_T_1} : _ex_op1_T_4; // @[RocketCore.scala:472:48, :474:24] wire _ex_op1_T_7 = &ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20, :472:48] wire [66:0] ex_op1 = _ex_op1_T_7 ? _ex_op1_T_2 : {{3{_ex_op1_T_6[63]}}, _ex_op1_T_6}; // @[RocketCore.scala:472:48, :475:54] wire [66:0] _alu_io_in1_T = ex_op1; // @[RocketCore.scala:472:48, :508:24] wire _ex_op2_oh_T = ex_ctrl_sel_alu2[0]; // @[RocketCore.scala:243:20, :477:48] wire [11:0] _ex_op2_oh_T_1 = ex_reg_inst[31:20]; // @[RocketCore.scala:259:24, :477:66] wire [63:0] _ex_op2_oh_T_2 = _ex_op2_oh_T ? {52'h0, _ex_op2_oh_T_1} : ex_rs_1; // @[RocketCore.scala:469:14, :477:{31,48,66}] wire [5:0] _ex_op2_oh_T_3 = _ex_op2_oh_T_2[5:0]; // @[RocketCore.scala:477:{31,90}] wire [63:0] _ex_op2_oh_T_4 = 64'h1 << _ex_op2_oh_T_3; // @[OneHot.scala:58:35] wire [63:0] ex_op2_oh = _ex_op2_oh_T_4; // @[OneHot.scala:58:35] wire [3:0] _ex_op2_T_1 = ex_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:249:35, :481:19] wire _ex_op2_T_2 = ex_ctrl_sel_alu2 == 3'h2; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_3 = _ex_op2_T_2 ? _ex_op2_T : 64'h0; // @[RocketCore.scala:478:48, :479:24] wire _ex_op2_T_4 = ex_ctrl_sel_alu2 == 3'h3; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_5 = _ex_op2_T_4 ? {{32{ex_imm[31]}}, ex_imm} : _ex_op2_T_3; // @[RocketCore.scala:478:48, :1355:53] wire _ex_op2_T_6 = ex_ctrl_sel_alu2 == 3'h1; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_7 = _ex_op2_T_6 ? {{60{_ex_op2_T_1[3]}}, _ex_op2_T_1} : _ex_op2_T_5; // @[RocketCore.scala:478:48, :481:19] wire _ex_op2_T_8 = ex_ctrl_sel_alu2 == 3'h4; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_9 = _ex_op2_T_8 ? ex_op2_oh : _ex_op2_T_7; // @[RocketCore.scala:477:112, :478:48] wire _ex_op2_T_10 = ex_ctrl_sel_alu2 == 3'h5; // @[RocketCore.scala:243:20, :478:48] wire [63:0] ex_op2 = _ex_op2_T_10 ? ex_op2_oh : _ex_op2_T_9; // @[RocketCore.scala:477:112, :478:48] wire [63:0] _alu_io_in2_T = ex_op2; // @[RocketCore.scala:478:48, :507:24] wire _div_io_req_valid_T = ex_reg_valid & ex_ctrl_div; // @[RocketCore.scala:243:20, :248:35, :512:36] wire _ex_reg_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19] wire _ex_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20] wire _ex_reg_replay_T_1 = _ex_reg_replay_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :526:{20,29}] wire _ex_reg_replay_T_2 = _ex_reg_replay_T_1 & _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :526:{29,54}] wire _ex_reg_xcpt_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :527:18] wire _ex_reg_xcpt_T_1 = _ex_reg_xcpt_T & id_xcpt; // @[RocketCore.scala:527:{18,30}, :1278:14] wire _ex_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :528:28] wire _ex_reg_xcpt_interrupt_T_1 = _ex_reg_xcpt_interrupt_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :528:{28,37}] wire _ex_reg_xcpt_interrupt_T_2 = _ex_reg_xcpt_interrupt_T_1 & _csr_io_interrupt; // @[RocketCore.scala:341:19, :528:{37,62}] wire [1:0] hi = {_ibuf_io_inst_0_bits_xcpt1_pf_inst, _ibuf_io_inst_0_bits_xcpt1_gf_inst}; // @[RocketCore.scala:311:20, :541:22] wire [1:0] hi_1 = {_ibuf_io_inst_0_bits_xcpt0_pf_inst, _ibuf_io_inst_0_bits_xcpt0_gf_inst}; // @[RocketCore.scala:311:20, :546:40] wire _ex_reg_flush_pipe_T = id_ctrl_fence_i \| id_csr_flush; // @[RocketCore.scala:321:21, :346:37, :551:42] wire _ex_reg_hls_T_1 = id_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47] wire _ex_reg_hls_T_2 = id_ctrl_mem_cmd == 5'h1; // @[package.scala:16:47] wire _ex_reg_hls_T_3 = id_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47] wire _ex_reg_hls_T_4 = _ex_reg_hls_T_1 \| _ex_reg_hls_T_2; // @[package.scala:16:47, :81:59] wire _ex_reg_hls_T_5 = _ex_reg_hls_T_4 \| _ex_reg_hls_T_3; // @[package.scala:16:47, :81:59] wire [1:0] _ex_reg_mem_size_T_1 = _ibuf_io_inst_0_bits_inst_bits[27:26]; // @[RocketCore.scala:311:20, :554:75] wire [1:0] _ex_reg_mem_size_T_2 = _ibuf_io_inst_0_bits_inst_bits[13:12]; // @[RocketCore.scala:311:20, :554:95] wire [1:0] _ex_reg_mem_size_T_3 = _ex_reg_mem_size_T_2; // @[RocketCore.scala:554:{27,95}] wire _ex_reg_mem_size_T_4 = \|id_raddr2; // @[RocketCore.scala:326:72, :556:40, :1326:41] wire _ex_reg_mem_size_T_5 = \|id_raddr1; // @[RocketCore.scala:326:72, :556:59, :1326:41] wire [1:0] _ex_reg_mem_size_T_6 = {_ex_reg_mem_size_T_4, _ex_reg_mem_size_T_5}; // @[RocketCore.scala:556:{29,40,59}] wire _do_bypass_T = id_bypass_src_0_0 \| id_bypass_src_0_1; // @[RocketCore.scala:461:74, :568:48] wire _do_bypass_T_1 = _do_bypass_T \| id_bypass_src_0_2; // @[RocketCore.scala:461:74, :568:48] wire do_bypass = _do_bypass_T_1 \| id_bypass_src_0_3; // @[RocketCore.scala:461:74, :568:48] wire [1:0] _bypass_src_T = {1'h1, ~id_bypass_src_0_2}; // @[Mux.scala:50:70] wire [1:0] _bypass_src_T_1 = id_bypass_src_0_1 ? 2'h1 : _bypass_src_T; // @[Mux.scala:50:70] wire [1:0] bypass_src = id_bypass_src_0_0 ? 2'h0 : _bypass_src_T_1; // @[Mux.scala:50:70] wire [1:0] _ex_reg_rs_lsb_0_T = id_rs_0[1:0]; // @[RocketCore.scala:573:37, :1325:26] wire [61:0] _ex_reg_rs_msb_0_T = id_rs_0[63:2]; // @[RocketCore.scala:574:38, :1325:26] wire _do_bypass_T_2 = id_bypass_src_1_0 \| id_bypass_src_1_1; // @[RocketCore.scala:461:74, :568:48] wire _do_bypass_T_3 = _do_bypass_T_2 \| id_bypass_src_1_2; // @[RocketCore.scala:461:74, :568:48] wire do_bypass_1 = _do_bypass_T_3 \| id_bypass_src_1_3; // @[RocketCore.scala:461:74, :568:48] wire [1:0] _bypass_src_T_2 = {1'h1, ~id_bypass_src_1_2}; // @[Mux.scala:50:70] wire [1:0] _bypass_src_T_3 = id_bypass_src_1_1 ? 2'h1 : _bypass_src_T_2; // @[Mux.scala:50:70] wire [1:0] bypass_src_1 = id_bypass_src_1_0 ? 2'h0 : _bypass_src_T_3; // @[Mux.scala:50:70] wire [1:0] _ex_reg_rs_lsb_1_T = id_rs_1[1:0]; // @[RocketCore.scala:573:37, :1325:26] wire [61:0] _ex_reg_rs_msb_1_T = id_rs_1[63:2]; // @[RocketCore.scala:574:38, :1325:26] wire [15:0] _inst_T = _ibuf_io_inst_0_bits_raw[15:0]; // @[RocketCore.scala:311:20, :578:62] wire [31:0] inst = _ibuf_io_inst_0_bits_rvc ? {16'h0, _inst_T} : _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20, :578:{21,62}] wire [1:0] _ex_reg_rs_lsb_0_T_1 = inst[1:0]; // @[RocketCore.scala:578:21, :580:31] wire [29:0] _ex_reg_rs_msb_0_T_1 = inst[31:2]; // @[RocketCore.scala:578:21, :581:32] wire _ex_reg_set_vconfig_T = ~id_xcpt; // @[RocketCore.scala:591:45, :1278:14] wire _ex_pc_valid_T = ex_reg_valid \| ex_reg_replay; // @[RocketCore.scala:248:35, :255:26, :595:34] wire ex_pc_valid = _ex_pc_valid_T \| ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :595:{34,51}] wire _wb_dcache_miss_T = ~io_dmem_resp_valid_0; // @[RocketCore.scala:153:7, :596:39] wire wb_dcache_miss = wb_ctrl_mem & _wb_dcache_miss_T; // @[RocketCore.scala:245:20, :596:{36,39}] wire _replay_ex_structural_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45] wire _replay_ex_structural_T_1 = ex_ctrl_mem & _replay_ex_structural_T; // @[RocketCore.scala:243:20, :597:{42,45}] wire _replay_ex_structural_T_2 = ~_div_io_req_ready; // @[RocketCore.scala:511:19, :598:45] wire _replay_ex_structural_T_3 = ex_ctrl_div & _replay_ex_structural_T_2; // @[RocketCore.scala:243:20, :598:{42,45}] wire _replay_ex_structural_T_4 = _replay_ex_structural_T_1 \| _replay_ex_structural_T_3; // @[RocketCore.scala:597:{42,64}, :598:42] wire replay_ex_structural = _replay_ex_structural_T_4; // @[RocketCore.scala:597:64, :598:63] wire replay_ex_load_use = wb_dcache_miss & ex_reg_load_use; // @[RocketCore.scala:253:35, :596:36, :600:43] wire _replay_ex_T = replay_ex_structural \| replay_ex_load_use; // @[RocketCore.scala:598:63, :600:43, :601:75] wire _replay_ex_T_1 = ex_reg_valid & _replay_ex_T; // @[RocketCore.scala:248:35, :601:{50,75}] wire replay_ex = ex_reg_replay \| _replay_ex_T_1; // @[RocketCore.scala:255:26, :601:{33,50}] wire _ctrl_killx_T = take_pc_mem_wb \| replay_ex; // @[RocketCore.scala:307:35, :601:33, :602:35] wire _ctrl_killx_T_1 = ~ex_reg_valid; // @[RocketCore.scala:248:35, :602:51] assign ctrl_killx = _ctrl_killx_T \| _ctrl_killx_T_1; // @[RocketCore.scala:602:{35,48,51}] assign io_fpu_killx_0 = ctrl_killx; // @[RocketCore.scala:153:7, :602:48] wire _GEN_47 = ex_ctrl_mem_cmd == 5'h7; // @[RocketCore.scala:243:20, :604:40] wire _ex_slow_bypass_T; // @[RocketCore.scala:604:40] assign _ex_slow_bypass_T = _GEN_47; // @[RocketCore.scala:604:40] wire _mem_reg_load_T_3; // @[package.scala:16:47] assign _mem_reg_load_T_3 = _GEN_47; // @[package.scala:16:47] wire _mem_reg_store_T_3; // @[Consts.scala:90:66] assign _mem_reg_store_T_3 = _GEN_47; // @[RocketCore.scala:604:40] wire _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_3 = _GEN_47; // @[package.scala:16:47] wire _ex_slow_bypass_T_1 = ~(ex_reg_mem_size[1]); // @[RocketCore.scala:257:28, :604:69] wire ex_slow_bypass = _ex_slow_bypass_T \| _ex_slow_bypass_T_1; // @[RocketCore.scala:604:{40,50,69}] wire _ex_sfence_T_1 = ex_ctrl_mem_cmd == 5'h14; // @[RocketCore.scala:243:20, :605:64] wire _ex_sfence_T_2 = ex_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:243:20, :605:96] wire _ex_sfence_T_3 = _ex_sfence_T_1 \| _ex_sfence_T_2; // @[RocketCore.scala:605:{64,77,96}] wire _ex_sfence_T_4 = ex_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:243:20, :605:129] wire _ex_sfence_T_5 = _ex_sfence_T_3 \| _ex_sfence_T_4; // @[RocketCore.scala:605:{77,110,129}] wire ex_sfence = _ex_sfence_T & _ex_sfence_T_5; // @[RocketCore.scala:605:{29,44,110}] wire ex_xcpt = ex_reg_xcpt_interrupt \| ex_reg_xcpt; // @[RocketCore.scala:247:35, :251:35, :608:28, :1278:14] wire _mem_pc_valid_T = mem_reg_valid \| mem_reg_replay; // @[RocketCore.scala:265:36, :269:36, :614:36] wire mem_pc_valid = _mem_pc_valid_T \| mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36, :614:{36,54}] wire _GEN_48 = mem_ctrl_branch & mem_br_taken; // @[RocketCore.scala:244:21, :284:25, :616:25] wire _mem_br_target_T_1; // @[RocketCore.scala:616:25] assign _mem_br_target_T_1 = _GEN_48; // @[RocketCore.scala:616:25] wire _mem_cfi_taken_T; // @[RocketCore.scala:626:40] assign _mem_cfi_taken_T = _GEN_48; // @[RocketCore.scala:616:25, :626:40] wire _mem_br_target_sign_T_1 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44] wire _mem_br_target_sign_T_4 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44] wire _mem_br_target_sign_T_2 = _mem_br_target_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire mem_br_target_sign = _mem_br_target_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire mem_br_target_hi_hi_hi = mem_br_target_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_br_target_b30_20_T_1 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41] wire [10:0] _mem_br_target_b30_20_T_4 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41] wire [10:0] _mem_br_target_b30_20_T_2 = _mem_br_target_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_br_target_b30_20 = {11{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_br_target_hi_hi_lo = mem_br_target_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_br_target_b19_12_T_3 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65] wire [7:0] _mem_br_target_b19_12_T_8 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65] wire [7:0] _mem_br_target_b19_12_T_4 = _mem_br_target_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_br_target_b19_12 = {8{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] mem_br_target_hi_lo_hi = mem_br_target_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_br_target_b11_T_4 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39] wire _mem_br_target_b0_T_3 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37] wire _mem_br_target_b11_T_15 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39] wire _mem_br_target_b0_T_11 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37] wire _mem_br_target_b11_T_5 = _mem_br_target_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _mem_br_target_b11_T_7 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39] wire _mem_br_target_b0_T_1 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37] wire _mem_br_target_b11_T_18 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39] wire _mem_br_target_b0_T_9 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37] wire _mem_br_target_b11_T_8 = _mem_br_target_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _mem_br_target_b11_T_9 = _mem_br_target_b11_T_8; // @[RocketCore.scala:1346:{18,43}] wire _mem_br_target_b11_T_10 = _mem_br_target_b11_T_9; // @[RocketCore.scala:1345:18, :1346:18] wire mem_br_target_b11 = _mem_br_target_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire mem_br_target_hi_lo_lo = mem_br_target_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _mem_br_target_b10_5_T_3 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62] wire [5:0] _mem_br_target_b10_5_T_7 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62] wire [5:0] mem_br_target_b10_5 = _mem_br_target_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_br_target_b4_1_T_4 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57] wire [3:0] _mem_br_target_b4_1_T_14 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57] wire [3:0] _mem_br_target_b4_1_T_9 = _mem_br_target_b4_1_T_4; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _mem_br_target_b4_1_T_6 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39] wire [3:0] _mem_br_target_b4_1_T_16 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39] wire [3:0] _mem_br_target_b4_1_T_7 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52] wire [3:0] _mem_br_target_b4_1_T_17 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52] wire [3:0] _mem_br_target_b4_1_T_8 = _mem_br_target_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] mem_br_target_b4_1 = _mem_br_target_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _mem_br_target_b0_T_5 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37] wire _mem_br_target_b0_T_13 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37] wire [9:0] mem_br_target_lo_hi = {mem_br_target_b10_5, mem_br_target_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_br_target_lo = {mem_br_target_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_br_target_hi_lo = {mem_br_target_hi_lo_hi, mem_br_target_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] mem_br_target_hi_hi = {mem_br_target_hi_hi_hi, mem_br_target_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] mem_br_target_hi = {mem_br_target_hi_hi, mem_br_target_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_2 = {mem_br_target_hi, mem_br_target_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_3 = _mem_br_target_T_2; // @[RocketCore.scala:1355:{8,53}] wire _mem_br_target_sign_T_5 = _mem_br_target_sign_T_4; // @[RocketCore.scala:1341:{44,49}] wire mem_br_target_sign_1 = _mem_br_target_sign_T_5; // @[RocketCore.scala:1341:{19,49}] wire _mem_br_target_b11_T_20 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1346:18] wire mem_br_target_hi_hi_hi_1 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_br_target_b30_20_T_5 = _mem_br_target_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_br_target_b30_20_1 = {11{mem_br_target_sign_1}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_br_target_hi_hi_lo_1 = mem_br_target_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_br_target_b19_12_T_9 = _mem_br_target_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_br_target_b19_12_1 = _mem_br_target_b19_12_T_9; // @[RocketCore.scala:1343:{21,73}] wire [7:0] mem_br_target_hi_lo_hi_1 = mem_br_target_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_br_target_b11_T_16 = _mem_br_target_b11_T_15; // @[RocketCore.scala:1345:{39,44}] wire _mem_br_target_b11_T_21 = _mem_br_target_b11_T_16; // @[RocketCore.scala:1345:{18,44}] wire _mem_br_target_b11_T_19 = _mem_br_target_b11_T_18; // @[RocketCore.scala:1346:{39,43}] wire mem_br_target_b11_1 = _mem_br_target_b11_T_21; // @[RocketCore.scala:1344:18, :1345:18] wire mem_br_target_hi_lo_lo_1 = mem_br_target_b11_1; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] mem_br_target_b10_5_1 = _mem_br_target_b10_5_T_7; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_br_target_b4_1_T_18 = _mem_br_target_b4_1_T_17; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _mem_br_target_b4_1_T_19 = _mem_br_target_b4_1_T_18; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] mem_br_target_b4_1_1 = _mem_br_target_b4_1_T_19; // @[RocketCore.scala:1348:19, :1349:19] wire [9:0] mem_br_target_lo_hi_1 = {mem_br_target_b10_5_1, mem_br_target_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_br_target_lo_1 = {mem_br_target_lo_hi_1, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_br_target_hi_lo_1 = {mem_br_target_hi_lo_hi_1, mem_br_target_hi_lo_lo_1}; // @[RocketCore.scala:1355:8] wire [11:0] mem_br_target_hi_hi_1 = {mem_br_target_hi_hi_hi_1, mem_br_target_hi_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [20:0] mem_br_target_hi_1 = {mem_br_target_hi_hi_1, mem_br_target_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_4 = {mem_br_target_hi_1, mem_br_target_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_5 = _mem_br_target_T_4; // @[RocketCore.scala:1355:{8,53}] wire [3:0] _mem_br_target_T_6 = mem_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:266:36, :618:8] wire [31:0] _mem_br_target_T_7 = mem_ctrl_jal ? _mem_br_target_T_5 : {{28{_mem_br_target_T_6[3]}}, _mem_br_target_T_6}; // @[RocketCore.scala:244:21, :617:8, :618:8, :1355:53] wire [31:0] _mem_br_target_T_8 = _mem_br_target_T_1 ? _mem_br_target_T_3 : _mem_br_target_T_7; // @[RocketCore.scala:616:{8,25}, :617:8, :1355:53] wire [40:0] _mem_br_target_T_9 = {_mem_br_target_T[39], _mem_br_target_T} + {{9{_mem_br_target_T_8[31]}}, _mem_br_target_T_8}; // @[RocketCore.scala:615:{34,41}, :616:8] wire [39:0] _mem_br_target_T_10 = _mem_br_target_T_9[39:0]; // @[RocketCore.scala:615:41] wire [39:0] mem_br_target = _mem_br_target_T_10; // @[RocketCore.scala:615:41] wire _mem_npc_T = mem_ctrl_jalr \| mem_reg_sfence; // @[RocketCore.scala:244:21, :276:27, :619:36] wire [24:0] _mem_npc_a_T = mem_reg_wdata[63:39]; // @[RocketCore.scala:282:26, :1293:17] wire [24:0] mem_npc_a = _mem_npc_a_T; // @[RocketCore.scala:1293:{17,23}] wire _mem_npc_msb_T = mem_npc_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _mem_npc_msb_T_1 = &mem_npc_a; // @[RocketCore.scala:1293:23, :1294:34] wire _mem_npc_msb_T_2 = _mem_npc_msb_T \| _mem_npc_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _mem_npc_msb_T_3 = mem_reg_wdata[39]; // @[RocketCore.scala:282:26, :1294:46] wire _mem_npc_msb_T_4 = mem_reg_wdata[38]; // @[RocketCore.scala:282:26, :1294:54] wire _mem_npc_msb_T_5 = ~_mem_npc_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire mem_npc_msb = _mem_npc_msb_T_2 ? _mem_npc_msb_T_3 : _mem_npc_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] wire [39:0] _mem_npc_T_2 = {mem_npc_msb, _mem_npc_T_1}; // @[RocketCore.scala:1294:18, :1295:{8,16}] wire [39:0] _mem_npc_T_3 = _mem_npc_T_2; // @[RocketCore.scala:619:106, :1295:8] wire [39:0] _mem_npc_T_4 = _mem_npc_T ? _mem_npc_T_3 : mem_br_target; // @[RocketCore.scala:615:41, :619:{21,36,106}] wire [39:0] _mem_npc_T_5 = _mem_npc_T_4 & 40'hFFFFFFFFFE; // @[RocketCore.scala:619:{21,129}] wire [39:0] _mem_npc_T_6 = _mem_npc_T_5; // @[RocketCore.scala:619:129] wire [39:0] mem_npc = _mem_npc_T_6; // @[RocketCore.scala:619:{129,139}] wire _mem_wrong_npc_T = mem_npc != ex_reg_pc; // @[RocketCore.scala:256:22, :619:139, :621:30] wire _mem_wrong_npc_T_1 = _ibuf_io_inst_0_valid \| io_imem_resp_valid_0; // @[RocketCore.scala:153:7, :311:20, :622:31] wire _mem_wrong_npc_T_2 = mem_npc != _ibuf_io_pc; // @[RocketCore.scala:311:20, :619:139, :622:62] wire _mem_wrong_npc_T_3 = ~_mem_wrong_npc_T_1 \| _mem_wrong_npc_T_2; // @[RocketCore.scala:622:{8,31,62}] assign mem_wrong_npc = ex_pc_valid ? _mem_wrong_npc_T : _mem_wrong_npc_T_3; // @[RocketCore.scala:595:51, :621:{8,30}, :622:8] assign io_imem_bht_update_bits_mispredict_0 = mem_wrong_npc; // @[RocketCore.scala:153:7, :621:8] wire _mem_npc_misaligned_T_1 = ~_mem_npc_misaligned_T; // @[RocketCore.scala:623:{28,46}] wire _mem_npc_misaligned_T_2 = mem_npc[1]; // @[RocketCore.scala:619:139, :623:66] wire _mem_npc_misaligned_T_3 = _mem_npc_misaligned_T_1 & _mem_npc_misaligned_T_2; // @[RocketCore.scala:623:{28,56,66}] wire _mem_npc_misaligned_T_4 = ~mem_reg_sfence; // @[RocketCore.scala:276:27, :623:73] wire mem_npc_misaligned = _mem_npc_misaligned_T_3 & _mem_npc_misaligned_T_4; // @[RocketCore.scala:623:{56,70,73}] wire _mem_int_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27] wire _mem_int_wdata_T_1 = mem_ctrl_jalr ^ mem_npc_misaligned; // @[RocketCore.scala:244:21, :623:70, :624:59] wire _mem_int_wdata_T_2 = _mem_int_wdata_T & _mem_int_wdata_T_1; // @[RocketCore.scala:624:{27,41,59}] wire [63:0] _mem_int_wdata_T_4 = _mem_int_wdata_T_2 ? {{24{mem_br_target[39]}}, mem_br_target} : _mem_int_wdata_T_3; // @[RocketCore.scala:615:41, :624:{26,41,111}] wire [63:0] mem_int_wdata = _mem_int_wdata_T_4; // @[RocketCore.scala:624:{26,119}] wire _mem_cfi_T = mem_ctrl_branch \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :625:33] assign mem_cfi = _mem_cfi_T \| mem_ctrl_jal; // @[RocketCore.scala:244:21, :625:{33,50}] assign io_imem_btb_update_bits_isValid_0 = mem_cfi; // @[RocketCore.scala:153:7, :625:50] wire _mem_cfi_taken_T_1 = _mem_cfi_taken_T \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :626:{40,57}] wire mem_cfi_taken = _mem_cfi_taken_T_1 \| mem_ctrl_jal; // @[RocketCore.scala:244:21, :626:{57,74}] wire _mem_direction_misprediction_T_1 = mem_br_taken != _mem_direction_misprediction_T; // @[RocketCore.scala:284:25, :627:{69,85}] wire mem_direction_misprediction = mem_ctrl_branch & _mem_direction_misprediction_T_1; // @[RocketCore.scala:244:21, :627:{53,69}] wire _take_pc_mem_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :629:35] wire _take_pc_mem_T_1 = mem_reg_valid & _take_pc_mem_T; // @[RocketCore.scala:265:36, :629:{32,35}] wire _take_pc_mem_T_2 = mem_wrong_npc \| mem_reg_sfence; // @[RocketCore.scala:276:27, :621:8, :629:71] assign _take_pc_mem_T_3 = _take_pc_mem_T_1 & _take_pc_mem_T_2; // @[RocketCore.scala:629:{32,49,71}] assign take_pc_mem = _take_pc_mem_T_3; // @[RocketCore.scala:285:25, :629:49] wire _mem_reg_valid_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20] wire _mem_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :632:21] wire _mem_reg_replay_T_1 = _mem_reg_replay_T & replay_ex; // @[RocketCore.scala:601:33, :632:{21,37}] wire _mem_reg_xcpt_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20, :633:19] wire _mem_reg_xcpt_T_1 = _mem_reg_xcpt_T & ex_xcpt; // @[RocketCore.scala:633:{19,31}, :1278:14] wire _mem_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :634:29] wire _mem_reg_xcpt_interrupt_T_1 = _mem_reg_xcpt_interrupt_T & ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :634:{29,45}] wire _GEN_49 = ex_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47] wire _mem_reg_load_T; // @[package.scala:16:47] assign _mem_reg_load_T = _GEN_49; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = ex_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47] wire _mem_reg_load_T_1; // @[package.scala:16:47] assign _mem_reg_load_T_1 = _GEN_50; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_1 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = ex_ctrl_mem_cmd == 5'h6; // @[package.scala:16:47] wire _mem_reg_load_T_2; // @[package.scala:16:47] assign _mem_reg_load_T_2 = _GEN_51; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_2 = _GEN_51; // @[package.scala:16:47] wire _mem_reg_load_T_4 = _mem_reg_load_T \| _mem_reg_load_T_1; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_5 = _mem_reg_load_T_4 \| _mem_reg_load_T_2; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_6 = _mem_reg_load_T_5 \| _mem_reg_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_52 = ex_ctrl_mem_cmd == 5'h4; // @[package.scala:16:47] wire _mem_reg_load_T_7; // @[package.scala:16:47] assign _mem_reg_load_T_7 = _GEN_52; // @[package.scala:16:47] wire _mem_reg_store_T_5; // @[package.scala:16:47] assign _mem_reg_store_T_5 = _GEN_52; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_7; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_7 = _GEN_52; // @[package.scala:16:47] wire _GEN_53 = ex_ctrl_mem_cmd == 5'h9; // @[package.scala:16:47] wire _mem_reg_load_T_8; // @[package.scala:16:47] assign _mem_reg_load_T_8 = _GEN_53; // @[package.scala:16:47] wire _mem_reg_store_T_6; // @[package.scala:16:47] assign _mem_reg_store_T_6 = _GEN_53; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_8 = _GEN_53; // @[package.scala:16:47] wire _GEN_54 = ex_ctrl_mem_cmd == 5'hA; // @[package.scala:16:47] wire _mem_reg_load_T_9; // @[package.scala:16:47] assign _mem_reg_load_T_9 = _GEN_54; // @[package.scala:16:47] wire _mem_reg_store_T_7; // @[package.scala:16:47] assign _mem_reg_store_T_7 = _GEN_54; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_9 = _GEN_54; // @[package.scala:16:47] wire _GEN_55 = ex_ctrl_mem_cmd == 5'hB; // @[package.scala:16:47] wire _mem_reg_load_T_10; // @[package.scala:16:47] assign _mem_reg_load_T_10 = _GEN_55; // @[package.scala:16:47] wire _mem_reg_store_T_8; // @[package.scala:16:47] assign _mem_reg_store_T_8 = _GEN_55; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_10 = _GEN_55; // @[package.scala:16:47] wire _mem_reg_load_T_11 = _mem_reg_load_T_7 \| _mem_reg_load_T_8; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_12 = _mem_reg_load_T_11 \| _mem_reg_load_T_9; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_13 = _mem_reg_load_T_12 \| _mem_reg_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_56 = ex_ctrl_mem_cmd == 5'h8; // @[package.scala:16:47] wire _mem_reg_load_T_14; // @[package.scala:16:47] assign _mem_reg_load_T_14 = _GEN_56; // @[package.scala:16:47] wire _mem_reg_store_T_12; // @[package.scala:16:47] assign _mem_reg_store_T_12 = _GEN_56; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_14; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_14 = _GEN_56; // @[package.scala:16:47] wire _GEN_57 = ex_ctrl_mem_cmd == 5'hC; // @[package.scala:16:47] wire _mem_reg_load_T_15; // @[package.scala:16:47] assign _mem_reg_load_T_15 = _GEN_57; // @[package.scala:16:47] wire _mem_reg_store_T_13; // @[package.scala:16:47] assign _mem_reg_store_T_13 = _GEN_57; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_15 = _GEN_57; // @[package.scala:16:47] wire _GEN_58 = ex_ctrl_mem_cmd == 5'hD; // @[package.scala:16:47] wire _mem_reg_load_T_16; // @[package.scala:16:47] assign _mem_reg_load_T_16 = _GEN_58; // @[package.scala:16:47] wire _mem_reg_store_T_14; // @[package.scala:16:47] assign _mem_reg_store_T_14 = _GEN_58; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_16 = _GEN_58; // @[package.scala:16:47] wire _GEN_59 = ex_ctrl_mem_cmd == 5'hE; // @[package.scala:16:47] wire _mem_reg_load_T_17; // @[package.scala:16:47] assign _mem_reg_load_T_17 = _GEN_59; // @[package.scala:16:47] wire _mem_reg_store_T_15; // @[package.scala:16:47] assign _mem_reg_store_T_15 = _GEN_59; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_17 = _GEN_59; // @[package.scala:16:47] wire _GEN_60 = ex_ctrl_mem_cmd == 5'hF; // @[package.scala:16:47] wire _mem_reg_load_T_18; // @[package.scala:16:47] assign _mem_reg_load_T_18 = _GEN_60; // @[package.scala:16:47] wire _mem_reg_store_T_16; // @[package.scala:16:47] assign _mem_reg_store_T_16 = _GEN_60; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_18 = _GEN_60; // @[package.scala:16:47] wire _mem_reg_load_T_19 = _mem_reg_load_T_14 \| _mem_reg_load_T_15; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_20 = _mem_reg_load_T_19 \| _mem_reg_load_T_16; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_21 = _mem_reg_load_T_20 \| _mem_reg_load_T_17; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_22 = _mem_reg_load_T_21 \| _mem_reg_load_T_18; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_23 = _mem_reg_load_T_13 \| _mem_reg_load_T_22; // @[package.scala:81:59] wire _mem_reg_load_T_24 = _mem_reg_load_T_6 \| _mem_reg_load_T_23; // @[package.scala:81:59] wire _mem_reg_load_T_25 = ex_ctrl_mem & _mem_reg_load_T_24; // @[RocketCore.scala:243:20, :643:33] wire _mem_reg_store_T = ex_ctrl_mem_cmd == 5'h1; // @[RocketCore.scala:243:20] wire _mem_reg_store_T_1 = ex_ctrl_mem_cmd == 5'h11; // @[RocketCore.scala:243:20] wire _mem_reg_store_T_2 = _mem_reg_store_T \| _mem_reg_store_T_1; // @[Consts.scala:90:{32,42,49}] wire _mem_reg_store_T_4 = _mem_reg_store_T_2 \| _mem_reg_store_T_3; // @[Consts.scala:90:{42,59,66}] wire _mem_reg_store_T_9 = _mem_reg_store_T_5 \| _mem_reg_store_T_6; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_10 = _mem_reg_store_T_9 \| _mem_reg_store_T_7; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_11 = _mem_reg_store_T_10 \| _mem_reg_store_T_8; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_17 = _mem_reg_store_T_12 \| _mem_reg_store_T_13; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_18 = _mem_reg_store_T_17 \| _mem_reg_store_T_14; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_19 = _mem_reg_store_T_18 \| _mem_reg_store_T_15; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_20 = _mem_reg_store_T_19 \| _mem_reg_store_T_16; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_21 = _mem_reg_store_T_11 \| _mem_reg_store_T_20; // @[package.scala:81:59] wire _mem_reg_store_T_22 = _mem_reg_store_T_4 \| _mem_reg_store_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _mem_reg_store_T_23 = ex_ctrl_mem & _mem_reg_store_T_22; // @[RocketCore.scala:243:20, :644:34] wire [1:0] size = ex_ctrl_rocc ? 2'h3 : ex_reg_mem_size; // @[RocketCore.scala:243:20, :257:28, :664:21] wire [1:0] mem_reg_rs2_size = size; // @[RocketCore.scala:664:21] wire _mem_reg_rs2_T = mem_reg_rs2_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _mem_reg_rs2_T_1 = mem_reg_rs2_dat_padded[7:0]; // @[AMOALU.scala:13:27, :29:69] wire [15:0] _mem_reg_rs2_T_2 = {2{_mem_reg_rs2_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _mem_reg_rs2_T_3 = {2{_mem_reg_rs2_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _mem_reg_rs2_T_4 = {2{_mem_reg_rs2_T_3}}; // @[AMOALU.scala:29:32] wire _mem_reg_rs2_T_5 = mem_reg_rs2_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _mem_reg_rs2_T_6 = mem_reg_rs2_dat_padded[15:0]; // @[AMOALU.scala:13:27, :29:69] wire [31:0] _mem_reg_rs2_T_7 = {2{_mem_reg_rs2_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_reg_rs2_T_8 = {2{_mem_reg_rs2_T_7}}; // @[AMOALU.scala:29:32] wire _mem_reg_rs2_T_9 = mem_reg_rs2_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _mem_reg_rs2_T_10 = mem_reg_rs2_dat_padded[31:0]; // @[AMOALU.scala:13:27, :29:69] wire [63:0] _mem_reg_rs2_T_11 = {2{_mem_reg_rs2_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_reg_rs2_T_12 = _mem_reg_rs2_T_9 ? _mem_reg_rs2_T_11 : mem_reg_rs2_dat_padded; // @[AMOALU.scala:13:27, :29:{13,19,32}] wire [63:0] _mem_reg_rs2_T_13 = _mem_reg_rs2_T_5 ? _mem_reg_rs2_T_8 : _mem_reg_rs2_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _mem_reg_rs2_T_14 = _mem_reg_rs2_T ? _mem_reg_rs2_T_4 : _mem_reg_rs2_T_13; // @[AMOALU.scala:29:{13,19,32}] wire _mem_breakpoint_T = mem_reg_load & _bpu_io_xcpt_ld; // @[RocketCore.scala:273:36, :414:19, :677:38] wire _mem_breakpoint_T_1 = mem_reg_store & _bpu_io_xcpt_st; // @[RocketCore.scala:274:36, :414:19, :677:75] wire mem_breakpoint = _mem_breakpoint_T \| _mem_breakpoint_T_1; // @[RocketCore.scala:677:{38,57,75}] wire _mem_debug_breakpoint_T = mem_reg_load & _bpu_io_debug_ld; // @[RocketCore.scala:273:36, :414:19, :678:44] wire _mem_debug_breakpoint_T_1 = mem_reg_store & _bpu_io_debug_st; // @[RocketCore.scala:274:36, :414:19, :678:82] wire mem_debug_breakpoint = _mem_debug_breakpoint_T \| _mem_debug_breakpoint_T_1; // @[RocketCore.scala:678:{44,64,82}] wire mem_ldst_xcpt = mem_debug_breakpoint \| mem_breakpoint; // @[RocketCore.scala:677:57, :678:64, :1278:{14,35}] wire [3:0] mem_ldst_cause = mem_debug_breakpoint ? 4'hE : 4'h3; // @[Mux.scala:50:70] wire _T_74 = mem_reg_xcpt_interrupt \| mem_reg_xcpt; // @[RocketCore.scala:264:36, :268:36, :684:29] wire _T_75 = mem_reg_valid & mem_npc_misaligned; // @[RocketCore.scala:265:36, :623:70, :685:20] wire mem_xcpt = _T_74 \| _T_75 \| mem_reg_valid & mem_ldst_xcpt; // @[RocketCore.scala:265:36, :684:29, :685:20, :686:20, :1278:{14,35}] wire [63:0] mem_cause = _T_74 ? mem_reg_cause : {60'h0, _T_75 ? 4'h0 : mem_ldst_cause}; // @[Mux.scala:50:70] wire dcache_kill_mem = _dcache_kill_mem_T & io_dmem_replay_next_0; // @[RocketCore.scala:153:7, :695:{39,55}] wire _fpu_kill_mem_T = mem_reg_valid & mem_ctrl_fp; // @[RocketCore.scala:244:21, :265:36, :696:36] wire fpu_kill_mem = _fpu_kill_mem_T & io_fpu_nack_mem_0; // @[RocketCore.scala:153:7, :696:{36,51}] wire _vec_kill_mem_T = mem_reg_valid & mem_ctrl_mem; // @[RocketCore.scala:244:21, :265:36, :697:36] wire _replay_mem_T = dcache_kill_mem \| mem_reg_replay; // @[RocketCore.scala:269:36, :695:55, :699:37] wire _replay_mem_T_1 = _replay_mem_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :699:{37,55}] wire _replay_mem_T_2 = _replay_mem_T_1; // @[RocketCore.scala:699:{55,71}] wire replay_mem = _replay_mem_T_2; // @[RocketCore.scala:699:{71,87}] wire _killm_common_T = dcache_kill_mem \| take_pc_wb; // @[RocketCore.scala:304:24, :695:55, :700:38] wire _killm_common_T_1 = _killm_common_T \| mem_reg_xcpt; // @[RocketCore.scala:268:36, :700:{38,52}] wire _killm_common_T_2 = ~mem_reg_valid; // @[RocketCore.scala:265:36, :700:71] assign killm_common = _killm_common_T_1 \| _killm_common_T_2; // @[RocketCore.scala:700:{52,68,71}] assign io_fpu_killm_0 = killm_common; // @[RocketCore.scala:153:7, :700:68] wire _div_io_kill_T = _div_io_req_ready & _div_io_req_valid_T; // @[Decoupled.scala:51:35] reg div_io_kill_REG; // @[RocketCore.scala:701:41] wire _div_io_kill_T_1 = killm_common & div_io_kill_REG; // @[RocketCore.scala:700:68, :701:{31,41}] wire _ctrl_killm_T = killm_common \| mem_xcpt; // @[RocketCore.scala:700:68, :702:33, :1278:14] wire _ctrl_killm_T_1 = _ctrl_killm_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :702:{33,45}] wire ctrl_killm = _ctrl_killm_T_1; // @[RocketCore.scala:702:{45,61}] wire _wb_reg_valid_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19] wire _wb_reg_replay_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34] wire _wb_reg_replay_T_1 = replay_mem & _wb_reg_replay_T; // @[RocketCore.scala:699:87, :706:{31,34}] wire _wb_reg_xcpt_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :707:30] wire _wb_reg_xcpt_T_1 = mem_xcpt & _wb_reg_xcpt_T; // @[RocketCore.scala:707:{27,30}, :1278:14] wire _wb_reg_xcpt_T_3 = _wb_reg_xcpt_T_1; // @[RocketCore.scala:707:{27,42}] wire _wb_reg_flush_pipe_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19, :708:24] wire _wb_reg_flush_pipe_T_1 = _wb_reg_flush_pipe_T & mem_reg_flush_pipe; // @[RocketCore.scala:270:36, :708:{24,36}] wire _wb_reg_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :712:25] wire _wb_reg_wdata_T_1 = _wb_reg_wdata_T & mem_ctrl_fp; // @[RocketCore.scala:244:21, :712:{25,39}] wire _wb_reg_wdata_T_2 = _wb_reg_wdata_T_1 & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :712:{39,54}] wire [63:0] _wb_reg_wdata_T_3 = _wb_reg_wdata_T_2 ? io_fpu_toint_data_0 : mem_int_wdata; // @[RocketCore.scala:153:7, :624:119, :712:{24,54}] wire _wb_reg_hfence_v_T = mem_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:244:21, :721:41] wire _wb_reg_hfence_g_T = mem_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:244:21, :722:41] wire _T_113 = wb_reg_valid & wb_ctrl_mem; // @[RocketCore.scala:245:20, :288:35, :730:19] wire _T_100 = _T_113 & io_dmem_s2_xcpt_pf_st_0; // @[RocketCore.scala:153:7, :730:{19,34}] wire _T_102 = _T_113 & io_dmem_s2_xcpt_pf_ld_0; // @[RocketCore.scala:153:7, :730:19, :731:34] wire _T_108 = _T_113 & io_dmem_s2_xcpt_ae_st_0; // @[RocketCore.scala:153:7, :730:19, :734:34] wire _T_110 = _T_113 & io_dmem_s2_xcpt_ae_ld_0; // @[RocketCore.scala:153:7, :730:19, :735:34] wire _T_112 = _T_113 & io_dmem_s2_xcpt_ma_st_0; // @[RocketCore.scala:153:7, :730:19, :736:34] wire wb_xcpt = wb_reg_xcpt \| _T_100 \| _T_102 \| _T_108 \| _T_110 \| _T_112 \| _T_113 & io_dmem_s2_xcpt_ma_ld_0; // @[RocketCore.scala:153:7, :289:35, :730:{19,34}, :731:34, :734:34, :735:34, :736:34, :737:34, :1278:{14,35}] wire [63:0] wb_cause = wb_reg_xcpt ? wb_reg_cause : {59'h0, _T_100 ? 5'hF : _T_102 ? 5'hD : {2'h0, _T_108 ? 3'h7 : _T_110 ? 3'h5 : {1'h1, _T_112, 1'h0}}}; // @[Mux.scala:50:70] wire _wb_pc_valid_T = wb_reg_valid \| wb_reg_replay; // @[RocketCore.scala:288:35, :290:35, :754:34] wire wb_pc_valid = _wb_pc_valid_T \| wb_reg_xcpt; // @[RocketCore.scala:289:35, :754:{34,51}] wire wb_wxd = wb_reg_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :288:35, :755:29] wire _wb_set_sboard_T = wb_ctrl_div \| wb_dcache_miss; // @[RocketCore.scala:245:20, :596:36, :756:35] wire _wb_set_sboard_T_1 = _wb_set_sboard_T \| wb_ctrl_rocc; // @[RocketCore.scala:245:20, :756:{35,53}] wire wb_set_sboard = _wb_set_sboard_T_1 \| wb_ctrl_vec; // @[RocketCore.scala:245:20, :756:{53,69}] wire replay_wb_common = io_dmem_s2_nack_0 \| wb_reg_replay; // @[RocketCore.scala:153:7, :290:35, :757:42] wire replay_wb_rocc = _replay_wb_rocc_T; // @[RocketCore.scala:758:{37,53}] wire _replay_wb_T = replay_wb_common \| replay_wb_rocc; // @[RocketCore.scala:757:42, :758:53, :761:36] wire _replay_wb_T_1 = _replay_wb_T; // @[RocketCore.scala:761:{36,54}] wire replay_wb = _replay_wb_T_1; // @[RocketCore.scala:761:{54,71}] wire _take_pc_wb_T = replay_wb \| wb_xcpt; // @[RocketCore.scala:761:71, :762:27, :1278:14] wire _take_pc_wb_T_1 = _take_pc_wb_T \| _csr_io_eret; // @[RocketCore.scala:341:19, :762:{27,38}] assign _take_pc_wb_T_2 = _take_pc_wb_T_1 \| wb_reg_flush_pipe; // @[RocketCore.scala:291:35, :762:{38,53}] assign take_pc_wb = _take_pc_wb_T_2; // @[RocketCore.scala:304:24, :762:53] wire _dmem_resp_xpu_T = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45] wire dmem_resp_fpu = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45, :766:45] wire dmem_resp_xpu = ~_dmem_resp_xpu_T; // @[RocketCore.scala:765:{23,45}] assign dmem_resp_waddr = io_dmem_resp_bits_tag_0[5:1]; // @[RocketCore.scala:153:7, :767:46] assign io_fpu_ll_resp_tag_0 = dmem_resp_waddr; // @[RocketCore.scala:153:7, :767:46] wire dmem_resp_valid = io_dmem_resp_valid_0 & io_dmem_resp_bits_has_data_0; // @[RocketCore.scala:153:7, :768:44] wire dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay_0; // @[RocketCore.scala:153:7, :768:44, :769:42] wire [63:0] ll_wdata; // @[RocketCore.scala:779:26] wire [4:0] ll_waddr; // @[RocketCore.scala:780:26] wire _ll_wen_T = ll_arb_io_out_ready & _ll_arb_io_out_valid; // @[Decoupled.scala:51:35] wire ll_wen; // @[RocketCore.scala:781:24] wire _ll_arb_io_out_ready_T = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26] wire _T_143 = dmem_resp_replay & dmem_resp_xpu; // @[RocketCore.scala:765:23, :769:42, :809:26] assign ll_arb_io_out_ready = ~_T_143 & _ll_arb_io_out_ready_T; // @[RocketCore.scala:782:{23,26}, :809:{26,44}, :810:25] assign ll_waddr = _T_143 ? dmem_resp_waddr : _ll_arb_io_out_bits_tag; // @[RocketCore.scala:767:46, :776:22, :780:26, :809:{26,44}, :811:14] assign ll_wen = _T_143 \| _ll_wen_T; // @[Decoupled.scala:51:35] wire _wb_valid_T = ~replay_wb; // @[RocketCore.scala:761:71, :815:34] wire _wb_valid_T_1 = wb_reg_valid & _wb_valid_T; // @[RocketCore.scala:288:35, :815:{31,34}] wire _wb_valid_T_2 = ~wb_xcpt; // @[RocketCore.scala:815:48, :1278:14] wire wb_valid = _wb_valid_T_1 & _wb_valid_T_2; // @[RocketCore.scala:815:{31,45,48}] wire wb_wen = wb_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :815:45, :816:25] wire rf_wen = wb_wen \| ll_wen; // @[RocketCore.scala:781:24, :816:25, :817:23] wire [4:0] rf_waddr = ll_wen ? ll_waddr : wb_waddr; // @[RocketCore.scala:455:36, :780:26, :781:24, :818:21] wire [4:0] xrfWriteBundle_wrdst = rf_waddr; // @[RocketCore.scala:818:21, :1249:28] wire _rf_wdata_T = dmem_resp_valid & dmem_resp_xpu; // @[RocketCore.scala:765:23, :768:44, :819:38] wire _rf_wdata_T_2 = \|wb_ctrl_csr; // @[RocketCore.scala:245:20, :821:34] wire [63:0] _rf_wdata_T_4 = _rf_wdata_T_2 ? _csr_io_rw_rdata : _rf_wdata_T_3; // @[RocketCore.scala:341:19, :821:{21,34}, :822:21] wire [63:0] _rf_wdata_T_5 = ll_wen ? ll_wdata : _rf_wdata_T_4; // @[RocketCore.scala:779:26, :781:24, :820:21, :821:21] wire [63:0] rf_wdata = _rf_wdata_T ? _rf_wdata_T_1 : _rf_wdata_T_5; // @[RocketCore.scala:819:{21,38,78}, :820:21] wire [63:0] coreMonitorBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1186:31] wire [63:0] xrfWriteBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1249:28] wire [63:0] _id_rs_T_4; // @[RocketCore.scala:1326:25] assign id_rs_0 = rf_wen & (\|rf_waddr) & rf_waddr == id_raddr1 ? rf_wdata : _id_rs_T_4; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}] wire [63:0] _id_rs_T_9; // @[RocketCore.scala:1326:25] assign id_rs_1 = rf_wen & (\|rf_waddr) & rf_waddr == id_raddr2 ? rf_wdata : _id_rs_T_9; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}] wire [1:0] _csr_io_inst_0_T = wb_reg_raw_inst[1:0]; // @[RocketCore.scala:301:28, :832:66] wire _csr_io_inst_0_T_1 = &_csr_io_inst_0_T; // @[RocketCore.scala:832:{66,73}] wire [15:0] _csr_io_inst_0_T_2 = wb_reg_inst[31:16]; // @[RocketCore.scala:300:24, :832:91] wire [15:0] _csr_io_inst_0_T_3 = _csr_io_inst_0_T_1 ? _csr_io_inst_0_T_2 : 16'h0; // @[RocketCore.scala:832:{50,73,91}] wire [15:0] _csr_io_inst_0_T_4 = wb_reg_raw_inst[15:0]; // @[RocketCore.scala:301:28, :832:119] wire [31:0] _csr_io_inst_0_T_5 = {_csr_io_inst_0_T_3, _csr_io_inst_0_T_4}; // @[RocketCore.scala:832:{46,50,119}] wire [4:0] _csr_io_fcsr_flags_bits_T = {5{io_fpu_fcsr_flags_valid_0}}; // @[RocketCore.scala:153:7, :839:59] wire [4:0] _csr_io_fcsr_flags_bits_T_1 = io_fpu_fcsr_flags_bits_0 & _csr_io_fcsr_flags_bits_T; // @[RocketCore.scala:153:7, :839:{53,59}] wire [4:0] _csr_io_fcsr_flags_bits_T_4 = _csr_io_fcsr_flags_bits_T_1; // @[RocketCore.scala:839:{53,89}] wire [31:0] _io_fpu_time_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29] wire [31:0] _coreMonitorBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1191:41] wire [31:0] _xrfWriteBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1254:38] assign io_fpu_time_0 = {32'h0, _io_fpu_time_T}; // @[RocketCore.scala:153:7, :840:{15,29}] wire tval_dmem_addr = ~wb_reg_xcpt; // @[RocketCore.scala:289:35, :845:24] wire _tval_any_addr_T = wb_reg_cause == 64'h3; // @[package.scala:16:47] wire _tval_any_addr_T_1 = wb_reg_cause == 64'h1; // @[package.scala:16:47] wire _tval_any_addr_T_2 = wb_reg_cause == 64'hC; // @[package.scala:16:47] wire _GEN_61 = wb_reg_cause == 64'h14; // @[package.scala:16:47] wire _tval_any_addr_T_3; // @[package.scala:16:47] assign _tval_any_addr_T_3 = _GEN_61; // @[package.scala:16:47] wire _htval_valid_imem_T; // @[RocketCore.scala:853:56] assign _htval_valid_imem_T = _GEN_61; // @[package.scala:16:47] wire _tval_any_addr_T_4 = _tval_any_addr_T \| _tval_any_addr_T_1; // @[package.scala:16:47, :81:59] wire _tval_any_addr_T_5 = _tval_any_addr_T_4 \| _tval_any_addr_T_2; // @[package.scala:16:47, :81:59] wire _tval_any_addr_T_6 = _tval_any_addr_T_5 \| _tval_any_addr_T_3; // @[package.scala:16:47, :81:59] wire tval_any_addr = tval_dmem_addr \| _tval_any_addr_T_6; // @[package.scala:81:59] wire tval_inst = wb_reg_cause == 64'h2; // @[RocketCore.scala:292:35, :848:32] wire _tval_valid_T = tval_any_addr \| tval_inst; // @[RocketCore.scala:846:38, :848:32, :849:46] wire tval_valid = wb_xcpt & _tval_valid_T; // @[RocketCore.scala:849:{28,46}, :1278:14] wire _csr_io_gva_T = tval_any_addr & _csr_io_status_v; // @[RocketCore.scala:341:19, :846:38, :850:43] wire _csr_io_gva_T_1 = tval_dmem_addr & wb_reg_hls_or_dv; // @[RocketCore.scala:297:29, :845:24, :850:80] wire _csr_io_gva_T_2 = _csr_io_gva_T \| _csr_io_gva_T_1; // @[RocketCore.scala:850:{43,62,80}] wire _csr_io_gva_T_3 = wb_xcpt & _csr_io_gva_T_2; // @[RocketCore.scala:850:{25,62}, :1278:14] wire [24:0] _csr_io_tval_a_T = wb_reg_wdata[63:39]; // @[RocketCore.scala:302:25, :1293:17] wire [24:0] csr_io_tval_a = _csr_io_tval_a_T; // @[RocketCore.scala:1293:{17,23}] wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _csr_io_tval_msb_T_1 = &csr_io_tval_a; // @[RocketCore.scala:1293:23, :1294:34] wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T \| _csr_io_tval_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _csr_io_tval_msb_T_3 = wb_reg_wdata[39]; // @[RocketCore.scala:302:25, :1294:46] wire _csr_io_tval_msb_T_4 = wb_reg_wdata[38]; // @[RocketCore.scala:302:25, :1294:54] wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] assign io_imem_sfence_bits_addr_0 = wb_reg_wdata[38:0]; // @[RocketCore.scala:153:7, :302:25, :1295:16] wire [38:0] _csr_io_tval_T = wb_reg_wdata[38:0]; // @[RocketCore.scala:302:25, :1295:16] wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}] wire [39:0] _csr_io_tval_T_2 = tval_valid ? _csr_io_tval_T_1 : 40'h0; // @[RocketCore.scala:849:28, :851:21, :1295:8] wire htval_valid_imem = wb_reg_xcpt & _htval_valid_imem_T; // @[RocketCore.scala:289:35, :853:{40,56}] wire [39:0] htval_imem = htval_valid_imem ? io_imem_gpa_bits_0 : 40'h0; // @[RocketCore.scala:153:7, :853:40, :854:25] wire [39:0] _htval_T = htval_imem; // @[RocketCore.scala:854:25, :860:29] wire _htval_valid_dmem_T = wb_xcpt & tval_dmem_addr; // @[RocketCore.scala:845:24, :857:36, :1278:14] wire [1:0] _htval_valid_dmem_T_4 = {io_dmem_s2_xcpt_pf_ld_0, io_dmem_s2_xcpt_pf_st_0}; // @[RocketCore.scala:153:7, :857:110] wire _htval_valid_dmem_T_5 = \|_htval_valid_dmem_T_4; // @[RocketCore.scala:857:{110,117}] wire _htval_valid_dmem_T_6 = ~_htval_valid_dmem_T_5; // @[RocketCore.scala:857:{90,117}] wire [39:0] htval = _htval_T; // @[RocketCore.scala:860:{29,43}] wire _mhtinst_read_pseudo_T = io_imem_gpa_is_pte_0 & htval_valid_imem; // @[RocketCore.scala:153:7, :853:40, :862:51] wire mhtinst_read_pseudo = _mhtinst_read_pseudo_T; // @[RocketCore.scala:862:{51,72}] wire [11:0] _csr_io_rw_addr_T = wb_reg_inst[31:20]; // @[RocketCore.scala:300:24, :909:32] wire [2:0] _csr_io_rw_cmd_T = {~wb_reg_valid, 2'h0}; // @[RocketCore.scala:288:35] wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala:183:{11,15}] wire [2:0] _csr_io_rw_cmd_T_2 = wb_ctrl_csr & _csr_io_rw_cmd_T_1; // @[RocketCore.scala:245:20] assign io_bpwatch_0_action_0 = {2'h0, _csr_io_bp_0_control_action}; // @[RocketCore.scala:153:7, :341:19, :962:18] wire _hazard_targets_T = \|id_raddr1; // @[RocketCore.scala:326:72, :969:55, :1326:41] wire hazard_targets_0_1 = id_ctrl_rxs1 & _hazard_targets_T; // @[RocketCore.scala:321:21, :969:{42,55}] wire _hazard_targets_T_1 = \|id_raddr2; // @[RocketCore.scala:326:72, :970:55, :1326:41] wire hazard_targets_1_1 = id_ctrl_rxs2 & _hazard_targets_T_1; // @[RocketCore.scala:321:21, :970:{42,55}] wire _hazard_targets_T_2 = \|id_waddr; // @[RocketCore.scala:326:72, :971:55] wire hazard_targets_2_1 = id_ctrl_wxd & _hazard_targets_T_2; // @[RocketCore.scala:321:21, :971:{42,55}] reg [31:0] _r; // @[RocketCore.scala:1305:29] wire [30:0] _r_T = _r[31:1]; // @[RocketCore.scala:1305:29, :1306:35] wire [31:0] r = {_r_T, 1'h0}; // @[RocketCore.scala:1306:{35,40}] wire [31:0] _GEN_62 = {27'h0, id_raddr1}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T = r >> _GEN_62; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_1 = _id_sboard_hazard_T[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_2 = ll_waddr == id_raddr1; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_3 = ll_wen & _id_sboard_hazard_T_2; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_4 = ~_id_sboard_hazard_T_3; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_5 = _id_sboard_hazard_T_1 & _id_sboard_hazard_T_4; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_6 = hazard_targets_0_1 & _id_sboard_hazard_T_5; // @[RocketCore.scala:969:42, :984:77, :1287:27] wire [31:0] _GEN_63 = {27'h0, id_raddr2}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_7 = r >> _GEN_63; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_8 = _id_sboard_hazard_T_7[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_9 = ll_waddr == id_raddr2; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_10 = ll_wen & _id_sboard_hazard_T_9; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_11 = ~_id_sboard_hazard_T_10; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_12 = _id_sboard_hazard_T_8 & _id_sboard_hazard_T_11; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_13 = hazard_targets_1_1 & _id_sboard_hazard_T_12; // @[RocketCore.scala:970:42, :984:77, :1287:27] wire [31:0] _GEN_64 = {27'h0, id_waddr}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_14 = r >> _GEN_64; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_15 = _id_sboard_hazard_T_14[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_16 = ll_waddr == id_waddr; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_17 = ll_wen & _id_sboard_hazard_T_16; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_18 = ~_id_sboard_hazard_T_17; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_19 = _id_sboard_hazard_T_15 & _id_sboard_hazard_T_18; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_20 = hazard_targets_2_1 & _id_sboard_hazard_T_19; // @[RocketCore.scala:971:42, :984:77, :1287:27] wire _id_sboard_hazard_T_21 = _id_sboard_hazard_T_6 \| _id_sboard_hazard_T_13; // @[RocketCore.scala:1287:{27,50}] wire id_sboard_hazard = _id_sboard_hazard_T_21 \| _id_sboard_hazard_T_20; // @[RocketCore.scala:1287:{27,50}] wire [31:0] _id_stall_fpu_T_4 = 32'h1 << wb_waddr; // @[RocketCore.scala:455:36, :1309:58] wire _ex_cannot_bypass_T = \|ex_ctrl_csr; // @[RocketCore.scala:243:20, :988:38] wire _ex_cannot_bypass_T_1 = _ex_cannot_bypass_T \| ex_ctrl_jalr; // @[RocketCore.scala:243:20, :988:{38,48}] wire _ex_cannot_bypass_T_2 = _ex_cannot_bypass_T_1 \| ex_ctrl_mem; // @[RocketCore.scala:243:20, :988:{48,64}] wire _ex_cannot_bypass_T_3 = _ex_cannot_bypass_T_2 \| ex_ctrl_mul; // @[RocketCore.scala:243:20, :988:{64,79}] wire _ex_cannot_bypass_T_4 = _ex_cannot_bypass_T_3 \| ex_ctrl_div; // @[RocketCore.scala:243:20, :988:{79,94}] wire _ex_cannot_bypass_T_5 = _ex_cannot_bypass_T_4 \| ex_ctrl_fp; // @[RocketCore.scala:243:20, :988:{94,109}] wire _ex_cannot_bypass_T_6 = _ex_cannot_bypass_T_5 \| ex_ctrl_rocc; // @[RocketCore.scala:243:20, :988:{109,123}] wire ex_cannot_bypass = _ex_cannot_bypass_T_6; // @[RocketCore.scala:988:{123,139}] wire _data_hazard_ex_T_1 = hazard_targets_0_1 & _data_hazard_ex_T; // @[RocketCore.scala:969:42, :989:70, :1287:27] wire _data_hazard_ex_T_3 = hazard_targets_1_1 & _data_hazard_ex_T_2; // @[RocketCore.scala:970:42, :989:70, :1287:27] wire _GEN_65 = id_waddr == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :989:70] wire _data_hazard_ex_T_4; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T_4 = _GEN_65; // @[RocketCore.scala:989:70] wire _fp_data_hazard_ex_T_7; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_7 = _GEN_65; // @[RocketCore.scala:989:70, :990:90] wire _data_hazard_ex_T_5 = hazard_targets_2_1 & _data_hazard_ex_T_4; // @[RocketCore.scala:971:42, :989:70, :1287:27] wire _data_hazard_ex_T_6 = _data_hazard_ex_T_1 \| _data_hazard_ex_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_ex_T_7 = _data_hazard_ex_T_6 \| _data_hazard_ex_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_ex = ex_ctrl_wxd & _data_hazard_ex_T_7; // @[RocketCore.scala:243:20, :989:36, :1287:50] wire _fp_data_hazard_ex_T = id_ctrl_fp & ex_ctrl_wfd; // @[RocketCore.scala:243:20, :321:21, :990:38] wire _fp_data_hazard_ex_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_ex_T_1; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_ex_T_3; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_5 = id_raddr3 == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :990:90] wire _fp_data_hazard_ex_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_ex_T_5; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_ex_T_7; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_9 = _fp_data_hazard_ex_T_2 \| _fp_data_hazard_ex_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_ex_T_10 = _fp_data_hazard_ex_T_9 \| _fp_data_hazard_ex_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_ex_T_11 = _fp_data_hazard_ex_T_10 \| _fp_data_hazard_ex_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_ex = _fp_data_hazard_ex_T & _fp_data_hazard_ex_T_11; // @[RocketCore.scala:990:{38,53}, :1287:50] wire _id_ex_hazard_T = data_hazard_ex & ex_cannot_bypass; // @[RocketCore.scala:988:139, :989:36, :991:54] wire _id_ex_hazard_T_1 = _id_ex_hazard_T \| fp_data_hazard_ex; // @[RocketCore.scala:990:53, :991:{54,74}] wire id_ex_hazard = ex_reg_valid & _id_ex_hazard_T_1; // @[RocketCore.scala:248:35, :991:{35,74}] wire _mem_cannot_bypass_T = \|mem_ctrl_csr; // @[RocketCore.scala:244:21, :997:40] wire _mem_cannot_bypass_T_1 = mem_ctrl_mem & mem_mem_cmd_bh; // @[RocketCore.scala:244:21, :995:41, :997:66] wire _mem_cannot_bypass_T_2 = _mem_cannot_bypass_T \| _mem_cannot_bypass_T_1; // @[RocketCore.scala:997:{40,50,66}] wire _mem_cannot_bypass_T_3 = _mem_cannot_bypass_T_2 \| mem_ctrl_mul; // @[RocketCore.scala:244:21, :997:{50,84}] wire _mem_cannot_bypass_T_4 = _mem_cannot_bypass_T_3 \| mem_ctrl_div; // @[RocketCore.scala:244:21, :997:{84,100}] wire _mem_cannot_bypass_T_5 = _mem_cannot_bypass_T_4 \| mem_ctrl_fp; // @[RocketCore.scala:244:21, :997:{100,116}] wire _mem_cannot_bypass_T_6 = _mem_cannot_bypass_T_5 \| mem_ctrl_rocc; // @[RocketCore.scala:244:21, :997:{116,131}] wire mem_cannot_bypass = _mem_cannot_bypass_T_6 \| mem_ctrl_vec; // @[RocketCore.scala:244:21, :997:{131,148}] wire _data_hazard_mem_T_1 = hazard_targets_0_1 & _data_hazard_mem_T; // @[RocketCore.scala:969:42, :998:72, :1287:27] wire _data_hazard_mem_T_3 = hazard_targets_1_1 & _data_hazard_mem_T_2; // @[RocketCore.scala:970:42, :998:72, :1287:27] wire _GEN_66 = id_waddr == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :998:72] wire _data_hazard_mem_T_4; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T_4 = _GEN_66; // @[RocketCore.scala:998:72] wire _fp_data_hazard_mem_T_7; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_7 = _GEN_66; // @[RocketCore.scala:998:72, :999:92] wire _data_hazard_mem_T_5 = hazard_targets_2_1 & _data_hazard_mem_T_4; // @[RocketCore.scala:971:42, :998:72, :1287:27] wire _data_hazard_mem_T_6 = _data_hazard_mem_T_1 \| _data_hazard_mem_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_mem_T_7 = _data_hazard_mem_T_6 \| _data_hazard_mem_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_mem = mem_ctrl_wxd & _data_hazard_mem_T_7; // @[RocketCore.scala:244:21, :998:38, :1287:50] wire _fp_data_hazard_mem_T = id_ctrl_fp & mem_ctrl_wfd; // @[RocketCore.scala:244:21, :321:21, :999:39] wire _fp_data_hazard_mem_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_mem_T_1; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_mem_T_3; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_5 = id_raddr3 == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :999:92] wire _fp_data_hazard_mem_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_mem_T_5; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_mem_T_7; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_9 = _fp_data_hazard_mem_T_2 \| _fp_data_hazard_mem_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_mem_T_10 = _fp_data_hazard_mem_T_9 \| _fp_data_hazard_mem_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_mem_T_11 = _fp_data_hazard_mem_T_10 \| _fp_data_hazard_mem_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_mem = _fp_data_hazard_mem_T & _fp_data_hazard_mem_T_11; // @[RocketCore.scala:999:{39,55}, :1287:50] wire _id_mem_hazard_T = data_hazard_mem & mem_cannot_bypass; // @[RocketCore.scala:997:148, :998:38, :1000:57] wire _id_mem_hazard_T_1 = _id_mem_hazard_T \| fp_data_hazard_mem; // @[RocketCore.scala:999:55, :1000:{57,78}] wire id_mem_hazard = mem_reg_valid & _id_mem_hazard_T_1; // @[RocketCore.scala:265:36, :1000:{37,78}] wire _id_load_use_T = mem_reg_valid & data_hazard_mem; // @[RocketCore.scala:265:36, :998:38, :1001:32] assign _id_load_use_T_1 = _id_load_use_T & mem_ctrl_mem; // @[RocketCore.scala:244:21, :1001:{32,51}] assign id_load_use = _id_load_use_T_1; // @[RocketCore.scala:332:25, :1001:51] wire _id_vconfig_hazard_T_1 = mem_reg_valid & mem_reg_set_vconfig; // @[RocketCore.scala:265:36, :275:36, :1004:20] wire _id_vconfig_hazard_T_2 = _id_vconfig_hazard_T_1; // @[RocketCore.scala:1003:42, :1004:20] wire _id_vconfig_hazard_T_3 = wb_reg_valid & wb_reg_set_vconfig; // @[RocketCore.scala:288:35, :293:35, :1005:19] wire _id_vconfig_hazard_T_4 = _id_vconfig_hazard_T_2 \| _id_vconfig_hazard_T_3; // @[RocketCore.scala:1003:42, :1004:44, :1005:19] wire _GEN_67 = id_raddr1 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T = _GEN_67; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_1; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_1 = _GEN_67; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_1 = hazard_targets_0_1 & _data_hazard_wb_T; // @[RocketCore.scala:969:42, :1008:70, :1287:27] wire _GEN_68 = id_raddr2 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T_2; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T_2 = _GEN_68; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_3; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_3 = _GEN_68; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_3 = hazard_targets_1_1 & _data_hazard_wb_T_2; // @[RocketCore.scala:970:42, :1008:70, :1287:27] wire _GEN_69 = id_waddr == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T_4; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T_4 = _GEN_69; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_7; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_7 = _GEN_69; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_5 = hazard_targets_2_1 & _data_hazard_wb_T_4; // @[RocketCore.scala:971:42, :1008:70, :1287:27] wire _data_hazard_wb_T_6 = _data_hazard_wb_T_1 \| _data_hazard_wb_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_wb_T_7 = _data_hazard_wb_T_6 \| _data_hazard_wb_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_wb = wb_ctrl_wxd & _data_hazard_wb_T_7; // @[RocketCore.scala:245:20, :1008:36, :1287:50] wire _fp_data_hazard_wb_T = id_ctrl_fp & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :321:21, :1009:38] wire _fp_data_hazard_wb_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_wb_T_1; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_wb_T_3; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_5 = id_raddr3 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1009:90] wire _fp_data_hazard_wb_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_wb_T_5; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_wb_T_7; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_9 = _fp_data_hazard_wb_T_2 \| _fp_data_hazard_wb_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_wb_T_10 = _fp_data_hazard_wb_T_9 \| _fp_data_hazard_wb_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_wb_T_11 = _fp_data_hazard_wb_T_10 \| _fp_data_hazard_wb_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_wb = _fp_data_hazard_wb_T & _fp_data_hazard_wb_T_11; // @[RocketCore.scala:1009:{38,53}, :1287:50] wire _id_wb_hazard_T = data_hazard_wb & wb_set_sboard; // @[RocketCore.scala:756:69, :1008:36, :1010:54] wire _id_wb_hazard_T_1 = _id_wb_hazard_T \| fp_data_hazard_wb; // @[RocketCore.scala:1009:53, :1010:{54,71}] wire id_wb_hazard = wb_reg_valid & _id_wb_hazard_T_1; // @[RocketCore.scala:288:35, :1010:{35,71}] reg [31:0] _id_stall_fpu_r; // @[RocketCore.scala:1305:29] wire _id_stall_fpu_T = wb_dcache_miss \| wb_ctrl_vec; // @[RocketCore.scala:245:20, :596:36, :1014:36] wire _id_stall_fpu_T_1 = _id_stall_fpu_T & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :1014:{36,52}] wire _id_stall_fpu_T_2 = _id_stall_fpu_T_1 \| io_fpu_sboard_set_0; // @[RocketCore.scala:153:7, :1014:{52,67}] wire _id_stall_fpu_T_3 = _id_stall_fpu_T_2 & wb_valid; // @[RocketCore.scala:815:45, :1014:{67,89}] wire _id_stall_fpu_T_7 = _id_stall_fpu_T_3; // @[RocketCore.scala:1014:89, :1312:17] wire [31:0] _id_stall_fpu_T_5 = _id_stall_fpu_T_3 ? _id_stall_fpu_T_4 : 32'h0; // @[RocketCore.scala:1014:89, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_6 = _id_stall_fpu_r \| _id_stall_fpu_T_5; // @[RocketCore.scala:1300:60, :1305:29, :1309:49] wire _id_stall_fpu_T_8 = dmem_resp_replay & dmem_resp_fpu; // @[RocketCore.scala:766:45, :769:42, :1016:39] wire _id_stall_fpu_T_9 = _id_stall_fpu_T_8; // @[RocketCore.scala:1016:{39,57}] wire [31:0] _id_stall_fpu_T_10 = 32'h1 << io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7, :1309:58] wire [31:0] _id_stall_fpu_T_11 = _id_stall_fpu_T_9 ? _id_stall_fpu_T_10 : 32'h0; // @[RocketCore.scala:1016:57, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_12 = ~_id_stall_fpu_T_11; // @[RocketCore.scala:1301:64, :1309:49] wire [31:0] _id_stall_fpu_T_13 = _id_stall_fpu_T_6 & _id_stall_fpu_T_12; // @[RocketCore.scala:1300:60, :1301:{62,64}] wire _id_stall_fpu_T_14 = _id_stall_fpu_T_7 \| _id_stall_fpu_T_9; // @[RocketCore.scala:1016:57, :1312:17] wire [31:0] _id_stall_fpu_T_15 = 32'h1 << io_fpu_sboard_clra_0; // @[RocketCore.scala:153:7, :1309:58] wire [31:0] _id_stall_fpu_T_16 = io_fpu_sboard_clr_0 ? _id_stall_fpu_T_15 : 32'h0; // @[RocketCore.scala:153:7, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_17 = ~_id_stall_fpu_T_16; // @[RocketCore.scala:1301:64, :1309:49] wire [31:0] _id_stall_fpu_T_18 = _id_stall_fpu_T_13 & _id_stall_fpu_T_17; // @[RocketCore.scala:1301:{62,64}] wire _id_stall_fpu_T_19 = _id_stall_fpu_T_14 \| io_fpu_sboard_clr_0; // @[RocketCore.scala:153:7, :1312:17] wire [31:0] _id_stall_fpu_T_20 = _id_stall_fpu_r >> _GEN_62; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_21 = _id_stall_fpu_T_20[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_22 = io_fpu_dec_ren1_0 & _id_stall_fpu_T_21; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_23 = _id_stall_fpu_r >> _GEN_63; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_24 = _id_stall_fpu_T_23[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_25 = io_fpu_dec_ren2_0 & _id_stall_fpu_T_24; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_26 = _id_stall_fpu_r >> id_raddr3; // @[RocketCore.scala:326:72, :1302:35, :1305:29] wire _id_stall_fpu_T_27 = _id_stall_fpu_T_26[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_28 = io_fpu_dec_ren3_0 & _id_stall_fpu_T_27; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_29 = _id_stall_fpu_r >> _GEN_64; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_30 = _id_stall_fpu_T_29[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_31 = io_fpu_dec_wen_0 & _id_stall_fpu_T_30; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire _id_stall_fpu_T_32 = _id_stall_fpu_T_22 \| _id_stall_fpu_T_25; // @[RocketCore.scala:1287:{27,50}] wire _id_stall_fpu_T_33 = _id_stall_fpu_T_32 \| _id_stall_fpu_T_28; // @[RocketCore.scala:1287:{27,50}] wire id_stall_fpu = _id_stall_fpu_T_33 \| _id_stall_fpu_T_31; // @[RocketCore.scala:1287:{27,50}] reg dcache_blocked_blocked; // @[RocketCore.scala:1024:22] wire _dcache_blocked_blocked_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45, :1025:16] wire _dcache_blocked_blocked_T_1 = _dcache_blocked_blocked_T; // @[RocketCore.scala:1025:{16,35}] wire _dcache_blocked_blocked_T_2 = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63] wire _dcache_blocked_blocked_T_3 = _dcache_blocked_blocked_T_1 & _dcache_blocked_blocked_T_2; // @[RocketCore.scala:1025:{35,60,63}] wire _dcache_blocked_blocked_T_4 = dcache_blocked_blocked \| io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :1024:22, :1025:95] wire _dcache_blocked_blocked_T_5 = _dcache_blocked_blocked_T_4 \| io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1025:{95,116}] wire _dcache_blocked_blocked_T_6 = _dcache_blocked_blocked_T_3 & _dcache_blocked_blocked_T_5; // @[RocketCore.scala:1025:{60,83,116}] wire _dcache_blocked_T = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63, :1026:16] wire dcache_blocked = dcache_blocked_blocked & _dcache_blocked_T; // @[RocketCore.scala:1024:22, :1026:{13,16}] reg rocc_blocked; // @[RocketCore.scala:1028:25] wire _rocc_blocked_T = ~wb_xcpt; // @[RocketCore.scala:815:48, :1029:19, :1278:14] wire _rocc_blocked_T_2 = _rocc_blocked_T; // @[RocketCore.scala:1029:{19,28}] wire _rocc_blocked_T_3 = io_rocc_cmd_valid \| rocc_blocked; // @[RocketCore.scala:153:7, :1028:25, :1029:72] wire _rocc_blocked_T_4 = _rocc_blocked_T_2 & _rocc_blocked_T_3; // @[RocketCore.scala:1029:{28,50,72}] wire _ctrl_stalld_T = id_ex_hazard \| id_mem_hazard; // @[RocketCore.scala:991:35, :1000:37, :1032:18] wire _ctrl_stalld_T_1 = _ctrl_stalld_T \| id_wb_hazard; // @[RocketCore.scala:1010:35, :1032:{18,35}] wire _ctrl_stalld_T_2 = _ctrl_stalld_T_1 \| id_sboard_hazard; // @[RocketCore.scala:1032:{35,51}, :1287:50] wire _ctrl_stalld_T_3 = _ctrl_stalld_T_2; // @[RocketCore.scala:1032:{51,71}] wire _ctrl_stalld_T_4 = ex_reg_valid \| mem_reg_valid; // @[RocketCore.scala:248:35, :265:36, :1034:40] wire _ctrl_stalld_T_5 = _ctrl_stalld_T_4 \| wb_reg_valid; // @[RocketCore.scala:288:35, :1034:{40,57}] wire _ctrl_stalld_T_6 = _csr_io_singleStep & _ctrl_stalld_T_5; // @[RocketCore.scala:341:19, :1034:{23,57}] wire _ctrl_stalld_T_7 = _ctrl_stalld_T_3 \| _ctrl_stalld_T_6; // @[RocketCore.scala:1032:71, :1033:23, :1034:23] wire _ctrl_stalld_T_8 = id_csr_en & _csr_io_decode_0_fp_csr; // @[package.scala:81:59] wire _ctrl_stalld_T_9 = ~io_fpu_fcsr_rdy_0; // @[RocketCore.scala:153:7, :1035:45] wire _ctrl_stalld_T_10 = _ctrl_stalld_T_8 & _ctrl_stalld_T_9; // @[RocketCore.scala:1035:{15,42,45}] wire _ctrl_stalld_T_11 = _ctrl_stalld_T_7 \| _ctrl_stalld_T_10; // @[RocketCore.scala:1033:23, :1034:74, :1035:42] wire _ctrl_stalld_T_14 = _ctrl_stalld_T_11; // @[RocketCore.scala:1034:74, :1035:62] wire _ctrl_stalld_T_15 = id_ctrl_fp & id_stall_fpu; // @[RocketCore.scala:321:21, :1037:16, :1287:50] wire _ctrl_stalld_T_16 = _ctrl_stalld_T_14 \| _ctrl_stalld_T_15; // @[RocketCore.scala:1035:62, :1036:61, :1037:16] wire _ctrl_stalld_T_17 = id_ctrl_mem & dcache_blocked; // @[RocketCore.scala:321:21, :1026:13, :1038:17] wire _ctrl_stalld_T_18 = _ctrl_stalld_T_16 \| _ctrl_stalld_T_17; // @[RocketCore.scala:1036:61, :1037:32, :1038:17] wire _ctrl_stalld_T_19 = id_ctrl_rocc & rocc_blocked; // @[RocketCore.scala:321:21, :1028:25, :1039:18] wire _ctrl_stalld_T_20 = _ctrl_stalld_T_18 \| _ctrl_stalld_T_19; // @[RocketCore.scala:1037:32, :1038:35, :1039:18] wire _ctrl_stalld_T_21 = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26, :1040:65] wire _ctrl_stalld_T_22 = _div_io_resp_valid & _ctrl_stalld_T_21; // @[RocketCore.scala:511:19, :1040:{62,65}] wire _ctrl_stalld_T_23 = _div_io_req_ready \| _ctrl_stalld_T_22; // @[RocketCore.scala:511:19, :1040:{40,62}] wire _ctrl_stalld_T_24 = ~_ctrl_stalld_T_23; // @[RocketCore.scala:1040:{21,40}] wire _ctrl_stalld_T_25 = _ctrl_stalld_T_24 \| _div_io_req_valid_T; // @[RocketCore.scala:512:36, :1040:{21,75}] wire _ctrl_stalld_T_26 = id_ctrl_div & _ctrl_stalld_T_25; // @[RocketCore.scala:321:21, :1040:{17,75}] wire _ctrl_stalld_T_27 = _ctrl_stalld_T_20 \| _ctrl_stalld_T_26; // @[RocketCore.scala:1038:35, :1039:34, :1040:17] wire _ctrl_stalld_T_29 = _ctrl_stalld_T_27; // @[RocketCore.scala:1039:34, :1040:96] wire _ctrl_stalld_T_30 = _ctrl_stalld_T_29 \| id_do_fence; // @[RocketCore.scala:410:32, :1040:96, :1041:15] wire _ctrl_stalld_T_31 = _ctrl_stalld_T_30 \| _csr_io_csr_stall; // @[RocketCore.scala:341:19, :1041:15, :1042:17] wire _ctrl_stalld_T_32 = _ctrl_stalld_T_31 \| id_reg_pause; // @[RocketCore.scala:161:25, :1042:17, :1043:22] wire ctrl_stalld = _ctrl_stalld_T_32; // @[RocketCore.scala:1043:22, :1044:18] wire _ctrl_killd_T = ~_ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :1046:17] wire _ctrl_killd_T_1 = _ctrl_killd_T \| _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :1046:{17,40}] wire _ctrl_killd_T_2 = _ctrl_killd_T_1 \| take_pc_mem_wb; // @[RocketCore.scala:307:35, :1046:{40,71}] wire _ctrl_killd_T_3 = _ctrl_killd_T_2 \| ctrl_stalld; // @[RocketCore.scala:1044:18, :1046:{71,89}] assign _ctrl_killd_T_4 = _ctrl_killd_T_3 \| _csr_io_interrupt; // @[RocketCore.scala:341:19, :1046:{89,104}] assign ctrl_killd = _ctrl_killd_T_4; // @[RocketCore.scala:338:24, :1046:104] assign _io_imem_req_bits_speculative_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1049:35] assign io_imem_req_bits_speculative_0 = _io_imem_req_bits_speculative_T; // @[RocketCore.scala:153:7, :1049:35] wire _io_imem_req_bits_pc_T = wb_xcpt \| _csr_io_eret; // @[RocketCore.scala:341:19, :1051:17, :1278:14] wire [39:0] _io_imem_req_bits_pc_T_1 = replay_wb ? wb_reg_pc : mem_npc; // @[RocketCore.scala:295:22, :619:139, :761:71, :1052:8] assign _io_imem_req_bits_pc_T_2 = _io_imem_req_bits_pc_T ? _csr_io_evec : _io_imem_req_bits_pc_T_1; // @[RocketCore.scala:341:19, :1051:{8,17}, :1052:8] assign io_imem_req_bits_pc_0 = _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:153:7, :1051:8] wire _io_imem_flush_icache_T = wb_reg_valid & wb_ctrl_fence_i; // @[RocketCore.scala:245:20, :288:35, :1054:40] wire _io_imem_flush_icache_T_1 = ~io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1054:62] assign _io_imem_flush_icache_T_2 = _io_imem_flush_icache_T & _io_imem_flush_icache_T_1; // @[RocketCore.scala:1054:{40,59,62}] assign io_imem_flush_icache_0 = _io_imem_flush_icache_T_2; // @[RocketCore.scala:153:7, :1054:59] wire _io_imem_might_request_imem_might_request_reg_T = ex_pc_valid \| mem_pc_valid; // @[RocketCore.scala:595:51, :614:54, :1056:43] wire _io_imem_might_request_imem_might_request_reg_T_1 = io_ptw_customCSRs_csrs_0_value_0[1]; // @[CustomCSRs.scala:44:61] wire _io_imem_might_request_imem_might_request_reg_T_2 = _io_imem_might_request_imem_might_request_reg_T \| _io_imem_might_request_imem_might_request_reg_T_1; // @[CustomCSRs.scala:44:61] wire _io_imem_might_request_imem_might_request_reg_T_3 = _io_imem_might_request_imem_might_request_reg_T_2; // @[RocketCore.scala:1056:{59,103}] wire _io_imem_progress_T = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47] wire _io_imem_progress_T_1 = wb_reg_valid & _io_imem_progress_T; // @[RocketCore.scala:288:35, :1059:{44,47}] reg io_imem_progress_REG; // @[RocketCore.scala:1059:30] assign io_imem_progress_0 = io_imem_progress_REG; // @[RocketCore.scala:153:7, :1059:30] assign _io_imem_sfence_valid_T = wb_reg_valid & wb_reg_sfence; // @[RocketCore.scala:288:35, :294:26, :1060:40] assign io_imem_sfence_valid_0 = _io_imem_sfence_valid_T; // @[RocketCore.scala:153:7, :1060:40] assign _io_imem_sfence_bits_rs1_T = wb_reg_mem_size[0]; // @[RocketCore.scala:296:28, :1061:45] assign io_imem_sfence_bits_rs1_0 = _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:153:7, :1061:45] assign _io_imem_sfence_bits_rs2_T = wb_reg_mem_size[1]; // @[RocketCore.scala:296:28, :1062:45] assign io_imem_sfence_bits_rs2_0 = _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:153:7, :1062:45] assign io_imem_sfence_bits_asid_0 = wb_reg_rs2[0]; // @[RocketCore.scala:153:7, :303:23, :1064:28] wire _ibuf_io_inst_0_ready_T = ~ctrl_stalld; // @[RocketCore.scala:1044:18, :1069:28] wire _io_imem_btb_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1071:48] wire _io_imem_btb_update_valid_T_1 = mem_reg_valid & _io_imem_btb_update_valid_T; // @[RocketCore.scala:265:36, :1071:{45,48}] wire _io_imem_btb_update_valid_T_2 = _io_imem_btb_update_valid_T_1 & mem_wrong_npc; // @[RocketCore.scala:621:8, :1071:{45,60}] wire _io_imem_btb_update_valid_T_3 = ~mem_cfi; // @[RocketCore.scala:625:50, :1071:81] wire _io_imem_btb_update_valid_T_4 = _io_imem_btb_update_valid_T_3 \| mem_cfi_taken; // @[RocketCore.scala:626:74, :1071:{81,90}] assign _io_imem_btb_update_valid_T_5 = _io_imem_btb_update_valid_T_2 & _io_imem_btb_update_valid_T_4; // @[RocketCore.scala:1071:{60,77,90}] assign io_imem_btb_update_valid_0 = _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:153:7, :1071:77] wire _GEN_70 = mem_ctrl_jal \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :1074:23] wire _io_imem_btb_update_bits_cfiType_T; // @[RocketCore.scala:1074:23] assign _io_imem_btb_update_bits_cfiType_T = _GEN_70; // @[RocketCore.scala:1074:23] wire _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:22] assign _io_imem_btb_update_bits_cfiType_T_8 = _GEN_70; // @[RocketCore.scala:1074:23, :1076:22] wire _io_imem_btb_update_bits_cfiType_T_1 = mem_waddr[0]; // @[RocketCore.scala:454:38, :1074:53] wire _io_imem_btb_update_bits_cfiType_T_2 = _io_imem_btb_update_bits_cfiType_T & _io_imem_btb_update_bits_cfiType_T_1; // @[RocketCore.scala:1074:{23,41,53}] wire [4:0] _io_imem_btb_update_bits_cfiType_T_3 = mem_reg_inst[19:15]; // @[RocketCore.scala:278:25, :1075:39] wire [4:0] _io_imem_btb_update_bits_cfiType_T_4 = _io_imem_btb_update_bits_cfiType_T_3; // @[RocketCore.scala:1075:{39,47}] wire [4:0] _io_imem_btb_update_bits_cfiType_T_5 = _io_imem_btb_update_bits_cfiType_T_4 & 5'h1B; // @[RocketCore.scala:1075:{47,64}] wire _io_imem_btb_update_bits_cfiType_T_6 = _io_imem_btb_update_bits_cfiType_T_5 == 5'h1; // @[RocketCore.scala:1075:64] wire _io_imem_btb_update_bits_cfiType_T_7 = mem_ctrl_jalr & _io_imem_btb_update_bits_cfiType_T_6; // @[RocketCore.scala:244:21, :1075:{23,64}] wire _io_imem_btb_update_bits_cfiType_T_9 = _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:{8,22}] wire [1:0] _io_imem_btb_update_bits_cfiType_T_10 = _io_imem_btb_update_bits_cfiType_T_7 ? 2'h3 : {1'h0, _io_imem_btb_update_bits_cfiType_T_9}; // @[RocketCore.scala:1075:{8,23}, :1076:8] assign _io_imem_btb_update_bits_cfiType_T_11 = _io_imem_btb_update_bits_cfiType_T_2 ? 2'h2 : _io_imem_btb_update_bits_cfiType_T_10; // @[RocketCore.scala:1074:{8,41}, :1075:8] assign io_imem_btb_update_bits_cfiType_0 = _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:153:7, :1074:8] assign io_imem_btb_update_bits_target_0 = io_imem_req_bits_pc_0[38:0]; // @[RocketCore.scala:153:7, :1078:34] wire [1:0] _io_imem_btb_update_bits_br_pc_T = {~mem_reg_rvc, 1'h0}; // @[RocketCore.scala:266:36, :1079:74] wire [40:0] _io_imem_btb_update_bits_br_pc_T_1 = {1'h0, mem_reg_pc} + {39'h0, _io_imem_btb_update_bits_br_pc_T}; // @[RocketCore.scala:277:23, :1079:{69,74}] wire [39:0] _io_imem_btb_update_bits_br_pc_T_2 = _io_imem_btb_update_bits_br_pc_T_1[39:0]; // @[RocketCore.scala:1079:69] assign io_imem_btb_update_bits_br_pc_0 = _io_imem_btb_update_bits_br_pc_T_2[38:0]; // @[RocketCore.scala:153:7, :1079:{33,69}] wire [38:0] _io_imem_btb_update_bits_pc_T = ~io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7, :1080:35] wire [38:0] _io_imem_btb_update_bits_pc_T_1 = {_io_imem_btb_update_bits_pc_T[38:2], 2'h3}; // @[RocketCore.scala:1080:{35,66}] assign _io_imem_btb_update_bits_pc_T_2 = ~_io_imem_btb_update_bits_pc_T_1; // @[RocketCore.scala:1080:{33,66}] assign io_imem_btb_update_bits_pc_0 = _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:153:7, :1080:33] wire _io_imem_bht_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1084:48] assign _io_imem_bht_update_valid_T_1 = mem_reg_valid & _io_imem_bht_update_valid_T; // @[RocketCore.scala:265:36, :1084:{45,48}] assign io_imem_bht_update_valid_0 = _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:153:7, :1084:45] wire _io_fpu_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :1094:19] assign _io_fpu_valid_T_1 = _io_fpu_valid_T & id_ctrl_fp; // @[RocketCore.scala:321:21, :1094:{19,31}] assign io_fpu_valid_0 = _io_fpu_valid_T_1; // @[RocketCore.scala:153:7, :1094:31] assign _io_fpu_ll_resp_val_T = dmem_resp_valid & dmem_resp_fpu; // @[RocketCore.scala:766:45, :768:44, :1099:41] assign io_fpu_ll_resp_val_0 = _io_fpu_ll_resp_val_T; // @[RocketCore.scala:153:7, :1099:41] assign io_fpu_ll_resp_type_0 = {1'h0, io_dmem_resp_bits_size_0}; // @[RocketCore.scala:153:7, :1101:23] assign _io_fpu_keep_clock_enabled_T = io_ptw_customCSRs_csrs_0_value_0[2]; // @[CustomCSRs.scala:45:59] assign io_fpu_keep_clock_enabled_0 = _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59] assign _io_dmem_req_valid_T = ex_reg_valid & ex_ctrl_mem; // @[RocketCore.scala:243:20, :248:35, :1130:41] assign io_dmem_req_valid_0 = _io_dmem_req_valid_T; // @[RocketCore.scala:153:7, :1130:41] wire [5:0] ex_dcache_tag = {ex_waddr, ex_ctrl_fp}; // @[RocketCore.scala:243:20, :453:36, :1131:26] assign io_dmem_req_bits_tag_0 = {1'h0, ex_dcache_tag}; // @[RocketCore.scala:153:7, :1131:26, :1133:25] wire _io_dmem_req_bits_signed_T_1 = ex_reg_inst[14]; // @[RocketCore.scala:259:24, :1136:75] wire _io_dmem_req_bits_signed_T_2 = _io_dmem_req_bits_signed_T_1; // @[RocketCore.scala:1136:{34,75}] assign _io_dmem_req_bits_signed_T_3 = ~_io_dmem_req_bits_signed_T_2; // @[RocketCore.scala:1136:{30,34}] assign io_dmem_req_bits_signed_0 = _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:153:7, :1136:30] wire [24:0] _io_dmem_req_bits_addr_a_T = ex_rs_0[63:39]; // @[RocketCore.scala:469:14, :1293:17] wire [24:0] io_dmem_req_bits_addr_a = _io_dmem_req_bits_addr_a_T; // @[RocketCore.scala:1293:{17,23}] wire _io_dmem_req_bits_addr_msb_T = io_dmem_req_bits_addr_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _io_dmem_req_bits_addr_msb_T_1 = &io_dmem_req_bits_addr_a; // @[RocketCore.scala:1293:23, :1294:34] wire _io_dmem_req_bits_addr_msb_T_2 = _io_dmem_req_bits_addr_msb_T \| _io_dmem_req_bits_addr_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _io_dmem_req_bits_addr_msb_T_3 = _alu_io_adder_out[39]; // @[RocketCore.scala:504:19, :1294:46] wire _io_dmem_req_bits_addr_msb_T_4 = _alu_io_adder_out[38]; // @[RocketCore.scala:504:19, :1294:54] wire _io_dmem_req_bits_addr_msb_T_5 = ~_io_dmem_req_bits_addr_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire io_dmem_req_bits_addr_msb = _io_dmem_req_bits_addr_msb_T_2 ? _io_dmem_req_bits_addr_msb_T_3 : _io_dmem_req_bits_addr_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] wire [38:0] _io_dmem_req_bits_addr_T = _alu_io_adder_out[38:0]; // @[RocketCore.scala:504:19, :1295:16] assign _io_dmem_req_bits_addr_T_1 = {io_dmem_req_bits_addr_msb, _io_dmem_req_bits_addr_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}] assign io_dmem_req_bits_addr_0 = _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:153:7, :1295:8] assign io_dmem_req_bits_dprv_0 = _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:153:7, :1140:31] assign io_dmem_req_bits_dv_0 = _io_dmem_req_bits_dv_T; // @[RocketCore.scala:153:7, :1141:37] wire _io_dmem_req_bits_no_resp_T_4 = _io_dmem_req_bits_no_resp_T \| _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_5 = _io_dmem_req_bits_no_resp_T_4 \| _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_6 = _io_dmem_req_bits_no_resp_T_5 \| _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_11 = _io_dmem_req_bits_no_resp_T_7 \| _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_12 = _io_dmem_req_bits_no_resp_T_11 \| _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_13 = _io_dmem_req_bits_no_resp_T_12 \| _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_19 = _io_dmem_req_bits_no_resp_T_14 \| _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_20 = _io_dmem_req_bits_no_resp_T_19 \| _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_21 = _io_dmem_req_bits_no_resp_T_20 \| _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_22 = _io_dmem_req_bits_no_resp_T_21 \| _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_23 = _io_dmem_req_bits_no_resp_T_13 \| _io_dmem_req_bits_no_resp_T_22; // @[package.scala:81:59] wire _io_dmem_req_bits_no_resp_T_24 = _io_dmem_req_bits_no_resp_T_6 \| _io_dmem_req_bits_no_resp_T_23; // @[package.scala:81:59] wire _io_dmem_req_bits_no_resp_T_25 = ~_io_dmem_req_bits_no_resp_T_24; // @[RocketCore.scala:1142:31] wire _io_dmem_req_bits_no_resp_T_26 = ~ex_ctrl_fp; // @[RocketCore.scala:243:20, :1142:60] wire _io_dmem_req_bits_no_resp_T_27 = ex_waddr == 5'h0; // @[RocketCore.scala:453:36, :1142:84] wire _io_dmem_req_bits_no_resp_T_28 = _io_dmem_req_bits_no_resp_T_26 & _io_dmem_req_bits_no_resp_T_27; // @[RocketCore.scala:1142:{60,72,84}] assign _io_dmem_req_bits_no_resp_T_29 = _io_dmem_req_bits_no_resp_T_25 \| _io_dmem_req_bits_no_resp_T_28; // @[RocketCore.scala:1142:{31,56,72}] assign io_dmem_req_bits_no_resp_0 = _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:153:7, :1142:56] assign _io_dmem_s1_data_data_T = mem_ctrl_fp ? io_fpu_store_data_0 : mem_reg_rs2; // @[RocketCore.scala:153:7, :244:21, :283:24, :1148:63] assign io_dmem_s1_data_data_0 = _io_dmem_s1_data_data_T; // @[RocketCore.scala:153:7, :1148:63] wire _io_dmem_s1_kill_T = killm_common \| mem_ldst_xcpt; // @[RocketCore.scala:700:68, :1151:35, :1278:14] wire _io_dmem_s1_kill_T_1 = _io_dmem_s1_kill_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :1151:{35,52}] assign _io_dmem_s1_kill_T_2 = _io_dmem_s1_kill_T_1; // @[RocketCore.scala:1151:{52,68}] assign io_dmem_s1_kill_0 = _io_dmem_s1_kill_T_2; // @[RocketCore.scala:153:7, :1151:68] wire _io_dmem_keep_clock_enabled_T = _ibuf_io_inst_0_valid & id_ctrl_mem; // @[RocketCore.scala:311:20, :321:21, :1154:55] wire _io_dmem_keep_clock_enabled_T_1 = ~_csr_io_csr_stall; // @[RocketCore.scala:341:19, :1154:73] assign _io_dmem_keep_clock_enabled_T_2 = _io_dmem_keep_clock_enabled_T & _io_dmem_keep_clock_enabled_T_1; // @[RocketCore.scala:1154:{55,70,73}] assign io_dmem_keep_clock_enabled_0 = _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:153:7, :1154:70] wire _io_rocc_cmd_valid_T_1 = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47, :1156:56] assign _io_rocc_cmd_valid_T_2 = _io_rocc_cmd_valid_T & _io_rocc_cmd_valid_T_1; // @[RocketCore.scala:1156:{37,53,56}] assign io_rocc_cmd_valid = _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:153:7, :1156:53] wire [6:0] _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_funct = _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rs2 = _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rs1 = _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xd = _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xs1 = _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xs2 = _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rd = _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:153:7, :1159:48] wire [6:0] _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_opcode = _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:153:7, :1159:48] assign _io_rocc_cmd_bits_inst_T = _io_rocc_cmd_bits_inst_WIRE_1[6:0]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_opcode = _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_1 = _io_rocc_cmd_bits_inst_WIRE_1[11:7]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rd = _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_2 = _io_rocc_cmd_bits_inst_WIRE_1[12]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xs2 = _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_3 = _io_rocc_cmd_bits_inst_WIRE_1[13]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xs1 = _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_4 = _io_rocc_cmd_bits_inst_WIRE_1[14]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xd = _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_5 = _io_rocc_cmd_bits_inst_WIRE_1[19:15]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rs1 = _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_6 = _io_rocc_cmd_bits_inst_WIRE_1[24:20]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rs2 = _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_7 = _io_rocc_cmd_bits_inst_WIRE_1[31:25]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_funct = _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48] wire [4:0] _unpause_T = _csr_io_time[4:0]; // @[RocketCore.scala:341:19, :1164:28] wire _unpause_T_1 = _unpause_T == 5'h0; // @[RocketCore.scala:1164:{28,62}] wire _unpause_T_2 = _unpause_T_1 \| _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19, :1164:{62,70}] wire _unpause_T_3 = _unpause_T_2 \| io_dmem_perf_release_0; // @[RocketCore.scala:153:7, :1164:{70,94}] wire unpause = _unpause_T_3 \| take_pc_mem_wb; // @[RocketCore.scala:307:35, :1164:{94,118}] reg icache_blocked_REG; // @[RocketCore.scala:1183:55] wire _icache_blocked_T = io_imem_resp_valid_0 \| icache_blocked_REG; // @[RocketCore.scala:153:7, :1183:{45,55}] wire icache_blocked = ~_icache_blocked_T; // @[RocketCore.scala:1183:{24,45}] wire _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1192:52] wire [63:0] _coreMonitorBundle_pc_T_3; // @[package.scala:132:15] wire _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1194:37] wire [4:0] _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1198:42] wire [4:0] _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1200:42] wire coreMonitorBundle_excpt; // @[RocketCore.scala:1186:31] wire [2:0] coreMonitorBundle_priv_mode; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_hartid; // @[RocketCore.scala:1186:31] wire [31:0] coreMonitorBundle_timer; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_valid; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_pc; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_wrenx; // @[RocketCore.scala:1186:31] wire [4:0] coreMonitorBundle_rd0src; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_rd0val; // @[RocketCore.scala:1186:31] wire [4:0] coreMonitorBundle_rd1src; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_rd1val; // @[RocketCore.scala:1186:31] wire [31:0] coreMonitorBundle_inst; // @[RocketCore.scala:1186:31] wire [63:0] _GEN_71 = {63'h0, io_hartid_0}; // @[RocketCore.scala:153:7, :1190:28] assign coreMonitorBundle_hartid = _GEN_71; // @[RocketCore.scala:1186:31, :1190:28] wire [63:0] xrfWriteBundle_hartid; // @[RocketCore.scala:1249:28] assign xrfWriteBundle_hartid = _GEN_71; // @[RocketCore.scala:1190:28, :1249:28] assign coreMonitorBundle_timer = _coreMonitorBundle_timer_T; // @[RocketCore.scala:1186:31, :1191:41] wire _coreMonitorBundle_valid_T = ~_csr_io_trace_0_exception; // @[RocketCore.scala:341:19, :1192:55] assign _coreMonitorBundle_valid_T_1 = _csr_io_trace_0_valid & _coreMonitorBundle_valid_T; // @[RocketCore.scala:341:19, :1192:{52,55}] assign coreMonitorBundle_valid = _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1186:31, :1192:52] wire [39:0] _coreMonitorBundle_pc_T; // @[RocketCore.scala:1193:48] wire _coreMonitorBundle_pc_T_1 = _coreMonitorBundle_pc_T[39]; // @[package.scala:132:38] wire [23:0] _coreMonitorBundle_pc_T_2 = {24{_coreMonitorBundle_pc_T_1}}; // @[package.scala:132:{20,38}] assign _coreMonitorBundle_pc_T_3 = {_coreMonitorBundle_pc_T_2, _coreMonitorBundle_pc_T}; // @[package.scala:132:{15,20}] assign coreMonitorBundle_pc = _coreMonitorBundle_pc_T_3; // @[package.scala:132:15] wire _coreMonitorBundle_wrenx_T = ~wb_set_sboard; // @[RocketCore.scala:756:69, :1194:40] assign _coreMonitorBundle_wrenx_T_1 = wb_wen & _coreMonitorBundle_wrenx_T; // @[RocketCore.scala:816:25, :1194:{37,40}] assign coreMonitorBundle_wrenx = _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1186:31, :1194:37] assign _coreMonitorBundle_rd0src_T = wb_reg_inst[19:15]; // @[RocketCore.scala:300:24, :1198:42] assign coreMonitorBundle_rd0src = _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1186:31, :1198:42] reg [63:0] coreMonitorBundle_rd0val_REG; // @[RocketCore.scala:1199:46] reg [63:0] coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1199:38] assign coreMonitorBundle_rd0val = coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1186:31, :1199:38] assign _coreMonitorBundle_rd1src_T = wb_reg_inst[24:20]; // @[RocketCore.scala:300:24, :1200:42] assign coreMonitorBundle_rd1src = _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1186:31, :1200:42] reg [63:0] coreMonitorBundle_rd1val_REG; // @[RocketCore.scala:1201:46] reg [63:0] coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1201:38] assign coreMonitorBundle_rd1val = coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1186:31, :1201:38]
Generate the Verilog code corresponding to the following Chisel files. File RouteComputer.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.experimental.decode.{TruthTable, decoder} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import freechips.rocketchip.rocket.DecodeLogic import constellation.channel._ import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo} import constellation.noc.{HasNoCParams} class RouteComputerReq(implicit val p: Parameters) extends Bundle with HasNoCParams { val src_virt_id = UInt(virtualChannelBits.W) val flow = new FlowRoutingBundle } class RouteComputerResp( val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } class RouteComputer( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams with HasNoCParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new RouteComputerReq)) }) val resp = MixedVec(allInParams.map { u => Output(new RouteComputerResp(outParams, egressParams)) }) }) (io.req zip io.resp).zipWithIndex.map { case ((req, resp), i) => req.ready := true.B if (outParams.size == 0) { assert(!req.valid) resp.vc_sel := DontCare } else { def toUInt(t: (Int, FlowRoutingInfo)): UInt = { val l2 = (BigInt(t._1) << req.bits.flow.vnet_id .getWidth) \| t._2.vNetId val l3 = ( l2 << req.bits.flow.ingress_node .getWidth) \| t._2.ingressNode val l4 = ( l3 << req.bits.flow.ingress_node_id.getWidth) \| t._2.ingressNodeId val l5 = ( l4 << req.bits.flow.egress_node .getWidth) \| t._2.egressNode val l6 = ( l5 << req.bits.flow.egress_node_id .getWidth) \| t._2.egressNodeId l6.U(req.bits.getWidth.W) } val flow = req.bits.flow val table = allInParams(i).possibleFlows.toSeq.distinct.map { pI => allInParams(i).channelRoutingInfos.map { cI => var row: String = "b" (0 until nOutputs).foreach { o => (0 until outParams(o).nVirtualChannels).foreach { outVId => row = row + (if (routingRelation(cI, outParams(o).channelRoutingInfos(outVId), pI)) "1" else "0") } } ((cI.vc, pI), row) } }.flatten val addr = req.bits.asUInt val width = outParams.map(_.nVirtualChannels).reduce(_+_) val decoded = if (table.size > 0) { val truthTable = TruthTable( table.map { e => (BitPat(toUInt(e._1)), BitPat(e._2)) }, BitPat("b" + "?" * width) ) Reverse(decoder(addr, truthTable)) } else { 0.U(width.W) } var idx = 0 (0 until nAllOutputs).foreach { o => if (o < nOutputs) { (0 until outParams(o).nVirtualChannels).foreach { outVId => resp.vc_sel(o)(outVId) := decoded(idx) idx += 1 } } else { resp.vc_sel(o)(0) := false.B } } } } }	module RouteComputer_19( // @[RouteComputer.scala:29:7] input [2:0] io_req_4_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_4_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_4_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_4_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_4_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_4_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_3_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_3_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_3_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_3_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_3, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_4, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_5, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_6, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_7, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_3, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_4, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_5, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_6, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_7, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_3, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_4, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_7, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_3, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_4, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_5, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_6, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_7, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_3, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_4, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_5, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_6, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_7, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_3, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_4, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_7, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_3, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_7, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_3, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_7, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_7, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_4_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_4_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_4_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_4_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_4_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_4_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_4_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_7 // @[RouteComputer.scala:40:14] ); wire [16:0] decoded_invInputs = ~{io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [16:0] _decoded_andMatrixOutputs_T = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_1 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_2 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_4 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_5 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_7 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_8 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_9 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_11 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_12 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_14 = {decoded_invInputs[0], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_16 = {decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_17 = {decoded_invInputs[0], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_18 = {decoded_invInputs[0], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_19 = {decoded_invInputs[0], decoded_invInputs[3], decoded_invInputs[4], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_21 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_22 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_23 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_25 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_26 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_28 = {decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_30 = {decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_31 = {decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_32 = {decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_33 = {decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[3], decoded_invInputs[4], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] decoded_invInputs_1 = ~{io_req_1_bits_flow_vnet_id, io_req_1_bits_flow_ingress_node, io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [14:0] _decoded_andMatrixOutputs_T_36 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[0], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_38 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[0], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_40 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_41 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_42 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_43 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_47 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_48 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_49 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_50 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_51 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_52 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_53 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_55 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_59 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_61 = {io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_62 = {io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_63 = {io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_64 = {io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_65 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_66 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_67 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_68 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_69 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_70 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_71 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_73 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_74 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_75 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_77 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_78 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_79 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_81 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[0], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_82 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[0], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_85 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_86 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_87 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_88 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_89 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[1], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_90 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[1], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_91 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[1], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_92 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[1], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] decoded_orMatrixOutputs_hi_hi_38 = {&_decoded_andMatrixOutputs_T_36, &_decoded_andMatrixOutputs_T_38}; // @[pla.scala:98:{53,70}, :114:19] wire [16:0] decoded_invInputs_2 = ~{io_req_2_bits_flow_vnet_id, io_req_2_bits_flow_ingress_node, io_req_2_bits_flow_ingress_node_id, io_req_2_bits_flow_egress_node, io_req_2_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [14:0] _decoded_andMatrixOutputs_T_94 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[0], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _decoded_andMatrixOutputs_T_96 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[0], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_97 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_98 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_99 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_100 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_101 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_102 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_103 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_104 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_105 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_109 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_111 = {io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_112 = {io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_113 = {io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_114 = {io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_115 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_116 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_117 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_118 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_119 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_120 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_121 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_123 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_124 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_125 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_127 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[0], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_128 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[0], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_132 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_133 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_134 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_135 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_136 = {decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_137 = {decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_138 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_139 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_140 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_141 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_142 = {decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_143 = {decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] decoded_orMatrixOutputs_hi_hi_58 = {&_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_96}; // @[pla.scala:98:{53,70}, :114:19] wire [16:0] decoded_invInputs_3 = ~{io_req_3_bits_flow_vnet_id, io_req_3_bits_flow_ingress_node, io_req_3_bits_flow_ingress_node_id, io_req_3_bits_flow_egress_node, io_req_3_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [14:0] _decoded_andMatrixOutputs_T_144 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_146 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_148 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_149 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_150 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_159 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_160 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_161 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_162 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_163 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_165 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_166 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_168 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_170 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_171 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_173 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_175 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_177 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_178 = {io_req_3_bits_flow_egress_node_id[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_179 = {io_req_3_bits_flow_egress_node_id[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_186 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_187 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_188 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_189 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_190 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_192 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_193 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_195 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_197 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_198 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_200 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_201 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_202 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_203 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_204 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_205 = {decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_206 = {decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_207 = {decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_208 = {decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_210 = {decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_211 = {decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_212 = {decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_214 = {decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_216 = {decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_217 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_218 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_219 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[1], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_220 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[1], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] decoded_invInputs_4 = ~{io_req_4_bits_flow_vnet_id, io_req_4_bits_flow_ingress_node, io_req_4_bits_flow_ingress_node_id, io_req_4_bits_flow_egress_node, io_req_4_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [2:0] _decoded_andMatrixOutputs_T_221 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], io_req_4_bits_flow_egress_node[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_223 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_224 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_230 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_231 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_232 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[2], decoded_invInputs_4[3], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_233 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_235 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_236 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_237 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_239 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_241 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_242 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_244 = {io_req_4_bits_flow_egress_node_id[0], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_245 = {io_req_4_bits_flow_egress_node_id[0], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_251 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_252 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_253 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[2], decoded_invInputs_4[3], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_254 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_256 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_257 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_258 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_260 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_261 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_262 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_263 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_264 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_265 = {decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_267 = {decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_268 = {decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_269 = {decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_270 = {decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_272 = {decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_273 = {decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_275 = {decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_276 = {decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_277 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_278 = {decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_279 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_280 = {decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[1], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_281 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[1], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_282 = {decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[1], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_283 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[1], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] assign io_resp_4_vc_sel_3_0 = &{decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], decoded_invInputs_4[2], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_4_vc_sel_3_1 = \|{&_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_224, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_231, &_decoded_andMatrixOutputs_T_235, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_252, &_decoded_andMatrixOutputs_T_256}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_3_2 = \|{&_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_224, &_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_231, &_decoded_andMatrixOutputs_T_235, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_252, &_decoded_andMatrixOutputs_T_256, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_264}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_3_3 = \|{&_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_224, &_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_231, &_decoded_andMatrixOutputs_T_235, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_245, &{decoded_invInputs_4[0], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_252, &_decoded_andMatrixOutputs_T_256, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_267}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_3_4 = \|{&_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_224, &_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_231, &_decoded_andMatrixOutputs_T_235, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_245, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_252, &_decoded_andMatrixOutputs_T_256, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_267, &{decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}, &{decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_3_5 = \|{&_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_224, &_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_231, &_decoded_andMatrixOutputs_T_235, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_245, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_252, &_decoded_andMatrixOutputs_T_256, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_267, &_decoded_andMatrixOutputs_T_277, &_decoded_andMatrixOutputs_T_279, &_decoded_andMatrixOutputs_T_281, &_decoded_andMatrixOutputs_T_283}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_3_6 = \|{&_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_224, &_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_231, &_decoded_andMatrixOutputs_T_235, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_245, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_252, &_decoded_andMatrixOutputs_T_256, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_267, &_decoded_andMatrixOutputs_T_277, &_decoded_andMatrixOutputs_T_279, &_decoded_andMatrixOutputs_T_281, &_decoded_andMatrixOutputs_T_283}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_3_7 = \|{&_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_224, &_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_231, &_decoded_andMatrixOutputs_T_235, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_245, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_252, &_decoded_andMatrixOutputs_T_256, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_267, &_decoded_andMatrixOutputs_T_277, &_decoded_andMatrixOutputs_T_279, &_decoded_andMatrixOutputs_T_281, &_decoded_andMatrixOutputs_T_283}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_2_1 = \|{&{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[2], decoded_invInputs_4[3], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_236, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_257}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_2_2 = \|{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_236, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_257}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_2_3 = \|{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_236, &{decoded_invInputs_4[0], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}, &{decoded_invInputs_4[0], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_257, &_decoded_andMatrixOutputs_T_268, &_decoded_andMatrixOutputs_T_270}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_2_4 = \|{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_236, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_257, &_decoded_andMatrixOutputs_T_268, &_decoded_andMatrixOutputs_T_270}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_2_5 = \|{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_236, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_257, &_decoded_andMatrixOutputs_T_268, &_decoded_andMatrixOutputs_T_270}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_2_6 = \|{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_236, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_257, &_decoded_andMatrixOutputs_T_268, &_decoded_andMatrixOutputs_T_270}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_2_7 = \|{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_236, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_257, &_decoded_andMatrixOutputs_T_268, &_decoded_andMatrixOutputs_T_270}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_1 = \|{&{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[0], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[0], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[0], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[0], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[0], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[0], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_2 = \|{&_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_237, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_258}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_3 = \|{&_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_237, &{decoded_invInputs_4[0], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}, &{decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_258, &{decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}, &_decoded_andMatrixOutputs_T_269}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_4 = \|{&_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_237, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_258, &_decoded_andMatrixOutputs_T_265, &_decoded_andMatrixOutputs_T_269}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_5 = \|{&_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_237, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_258, &_decoded_andMatrixOutputs_T_265, &_decoded_andMatrixOutputs_T_269, &_decoded_andMatrixOutputs_T_276, &_decoded_andMatrixOutputs_T_278, &_decoded_andMatrixOutputs_T_280, &_decoded_andMatrixOutputs_T_282}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_6 = \|{&_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_237, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_258, &_decoded_andMatrixOutputs_T_265, &_decoded_andMatrixOutputs_T_269, &_decoded_andMatrixOutputs_T_276, &_decoded_andMatrixOutputs_T_278, &_decoded_andMatrixOutputs_T_280, &_decoded_andMatrixOutputs_T_282}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_7 = \|{&_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_237, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_258, &_decoded_andMatrixOutputs_T_265, &_decoded_andMatrixOutputs_T_269, &_decoded_andMatrixOutputs_T_276, &_decoded_andMatrixOutputs_T_278, &_decoded_andMatrixOutputs_T_280, &_decoded_andMatrixOutputs_T_282}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_0_0 = &_decoded_andMatrixOutputs_T_221; // @[pla.scala:98:{53,70}] assign io_resp_4_vc_sel_0_1 = &_decoded_andMatrixOutputs_T_221; // @[pla.scala:98:{53,70}] assign io_resp_4_vc_sel_0_2 = \|{&_decoded_andMatrixOutputs_T_221, &_decoded_andMatrixOutputs_T_239, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_260, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_263}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_0_3 = \|{&_decoded_andMatrixOutputs_T_221, &_decoded_andMatrixOutputs_T_239, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_260, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_263}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_0_4 = \|{&_decoded_andMatrixOutputs_T_221, &_decoded_andMatrixOutputs_T_239, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_260, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_263, &_decoded_andMatrixOutputs_T_272, &_decoded_andMatrixOutputs_T_273, &_decoded_andMatrixOutputs_T_275}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_0_5 = \|{&_decoded_andMatrixOutputs_T_221, &_decoded_andMatrixOutputs_T_239, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_260, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_263, &_decoded_andMatrixOutputs_T_272, &_decoded_andMatrixOutputs_T_273, &_decoded_andMatrixOutputs_T_275}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_0_6 = \|{&_decoded_andMatrixOutputs_T_221, &_decoded_andMatrixOutputs_T_239, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_260, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_263, &_decoded_andMatrixOutputs_T_272, &_decoded_andMatrixOutputs_T_273, &_decoded_andMatrixOutputs_T_275}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_0_7 = \|{&_decoded_andMatrixOutputs_T_221, &_decoded_andMatrixOutputs_T_239, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_260, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_263, &_decoded_andMatrixOutputs_T_272, &_decoded_andMatrixOutputs_T_273, &_decoded_andMatrixOutputs_T_275}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_0 = \|{&{decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16]}, &{decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_1 = \|{&_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_150, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_159, &_decoded_andMatrixOutputs_T_160, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_187, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_2 = \|{&_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_159, &_decoded_andMatrixOutputs_T_160, &_decoded_andMatrixOutputs_T_162, &_decoded_andMatrixOutputs_T_168, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_195, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_203}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_3 = \|{&_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_159, &_decoded_andMatrixOutputs_T_160, &_decoded_andMatrixOutputs_T_162, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_179, &{decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_195, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_203, &{decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_4 = \|{&_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_159, &_decoded_andMatrixOutputs_T_160, &_decoded_andMatrixOutputs_T_162, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_179, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_195, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_203, &_decoded_andMatrixOutputs_T_207, &{decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}, &{decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_5 = \|{&_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_159, &_decoded_andMatrixOutputs_T_160, &_decoded_andMatrixOutputs_T_162, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_179, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_195, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_203, &_decoded_andMatrixOutputs_T_207, &_decoded_andMatrixOutputs_T_217, &_decoded_andMatrixOutputs_T_218, &_decoded_andMatrixOutputs_T_219, &_decoded_andMatrixOutputs_T_220}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_6 = \|{&_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_159, &_decoded_andMatrixOutputs_T_160, &_decoded_andMatrixOutputs_T_162, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_179, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_195, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_203, &_decoded_andMatrixOutputs_T_207, &_decoded_andMatrixOutputs_T_217, &_decoded_andMatrixOutputs_T_218, &_decoded_andMatrixOutputs_T_219, &_decoded_andMatrixOutputs_T_220}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_7 = \|{&_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_159, &_decoded_andMatrixOutputs_T_160, &_decoded_andMatrixOutputs_T_162, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_179, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_195, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_203, &_decoded_andMatrixOutputs_T_207, &_decoded_andMatrixOutputs_T_217, &_decoded_andMatrixOutputs_T_218, &_decoded_andMatrixOutputs_T_219, &_decoded_andMatrixOutputs_T_220}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_2_1 = \|{&{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_161, &_decoded_andMatrixOutputs_T_163, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_170, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_192, &_decoded_andMatrixOutputs_T_197}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_2_2 = \|{&_decoded_andMatrixOutputs_T_161, &_decoded_andMatrixOutputs_T_163, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_170, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_192, &_decoded_andMatrixOutputs_T_197}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_2_3 = \|{&_decoded_andMatrixOutputs_T_161, &_decoded_andMatrixOutputs_T_163, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_170, &{decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}, &{decoded_invInputs_3[0], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}, &{decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_192, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_208, &_decoded_andMatrixOutputs_T_211}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_2_4 = \|{&_decoded_andMatrixOutputs_T_161, &_decoded_andMatrixOutputs_T_163, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_170, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_192, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_208, &_decoded_andMatrixOutputs_T_211}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_2_5 = \|{&_decoded_andMatrixOutputs_T_161, &_decoded_andMatrixOutputs_T_163, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_170, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_192, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_208, &_decoded_andMatrixOutputs_T_211}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_2_6 = \|{&_decoded_andMatrixOutputs_T_161, &_decoded_andMatrixOutputs_T_163, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_170, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_192, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_208, &_decoded_andMatrixOutputs_T_211}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_2_7 = \|{&_decoded_andMatrixOutputs_T_161, &_decoded_andMatrixOutputs_T_163, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_170, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_192, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_208, &_decoded_andMatrixOutputs_T_211}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_1_1 = \|{&{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[3], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[3], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[3], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[3], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[3], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[3], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_1_2 = \|{&_decoded_andMatrixOutputs_T_166, &_decoded_andMatrixOutputs_T_171, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_198}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_1_3 = \|{&_decoded_andMatrixOutputs_T_166, &_decoded_andMatrixOutputs_T_171, &{decoded_invInputs_3[0], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}, &{decoded_invInputs_3[0], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_198, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_210}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_1_4 = \|{&_decoded_andMatrixOutputs_T_166, &_decoded_andMatrixOutputs_T_171, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_198, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_210}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_1_5 = \|{&_decoded_andMatrixOutputs_T_166, &_decoded_andMatrixOutputs_T_171, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_198, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_210}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_1_6 = \|{&_decoded_andMatrixOutputs_T_166, &_decoded_andMatrixOutputs_T_171, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_198, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_210}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_1_7 = \|{&_decoded_andMatrixOutputs_T_166, &_decoded_andMatrixOutputs_T_171, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_198, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_210}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_0 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_1 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_2 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_175, &_decoded_andMatrixOutputs_T_177, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_3 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_175, &_decoded_andMatrixOutputs_T_177, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_4 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_175, &_decoded_andMatrixOutputs_T_177, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204, &_decoded_andMatrixOutputs_T_212, &_decoded_andMatrixOutputs_T_214, &_decoded_andMatrixOutputs_T_216}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_5 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_175, &_decoded_andMatrixOutputs_T_177, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204, &_decoded_andMatrixOutputs_T_212, &_decoded_andMatrixOutputs_T_214, &_decoded_andMatrixOutputs_T_216}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_6 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_175, &_decoded_andMatrixOutputs_T_177, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204, &_decoded_andMatrixOutputs_T_212, &_decoded_andMatrixOutputs_T_214, &_decoded_andMatrixOutputs_T_216}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_7 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_175, &_decoded_andMatrixOutputs_T_177, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204, &_decoded_andMatrixOutputs_T_212, &_decoded_andMatrixOutputs_T_214, &_decoded_andMatrixOutputs_T_216}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_4_0 = &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[0], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_2_vc_sel_4_1 = \|{&_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_116}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_4_2 = \|{&_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_102, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[3], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_116, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[3], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_4_3 = \|{&_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_112, &_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_121}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_4_4 = \|{&_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_112, &_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_121, &{decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[0], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_4_5 = \|{&_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_112, &_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_121, &_decoded_andMatrixOutputs_T_134, &_decoded_andMatrixOutputs_T_140}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_4_6 = \|{&_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_112, &_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_121, &_decoded_andMatrixOutputs_T_134, &_decoded_andMatrixOutputs_T_140}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_4_7 = \|{&_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_112, &_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_121, &_decoded_andMatrixOutputs_T_134, &_decoded_andMatrixOutputs_T_140}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_0 = &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], decoded_invInputs_2[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_2_vc_sel_3_1 = \|{&_decoded_andMatrixOutputs_T_97, &_decoded_andMatrixOutputs_T_99, &_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_101, &_decoded_andMatrixOutputs_T_103, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_118}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_2 = \|{&_decoded_andMatrixOutputs_T_97, &_decoded_andMatrixOutputs_T_99, &_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_101, &_decoded_andMatrixOutputs_T_103, &_decoded_andMatrixOutputs_T_104, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_123, &_decoded_andMatrixOutputs_T_125}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_3 = \|{&_decoded_andMatrixOutputs_T_97, &_decoded_andMatrixOutputs_T_99, &_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_101, &_decoded_andMatrixOutputs_T_103, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_111, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_123, &_decoded_andMatrixOutputs_T_125}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_4 = \|{&_decoded_andMatrixOutputs_T_97, &_decoded_andMatrixOutputs_T_99, &_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_101, &_decoded_andMatrixOutputs_T_103, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_111, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_123, &_decoded_andMatrixOutputs_T_125, &{decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[2], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}, &{decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}, &{decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_5 = \|{&_decoded_andMatrixOutputs_T_97, &_decoded_andMatrixOutputs_T_99, &_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_101, &_decoded_andMatrixOutputs_T_103, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_111, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_123, &_decoded_andMatrixOutputs_T_125, &_decoded_andMatrixOutputs_T_132, &_decoded_andMatrixOutputs_T_133, &_decoded_andMatrixOutputs_T_135, &_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_138, &_decoded_andMatrixOutputs_T_139, &_decoded_andMatrixOutputs_T_141, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_143}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_6 = \|{&_decoded_andMatrixOutputs_T_97, &_decoded_andMatrixOutputs_T_99, &_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_101, &_decoded_andMatrixOutputs_T_103, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_111, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_123, &_decoded_andMatrixOutputs_T_125, &_decoded_andMatrixOutputs_T_132, &_decoded_andMatrixOutputs_T_133, &_decoded_andMatrixOutputs_T_135, &_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_138, &_decoded_andMatrixOutputs_T_139, &_decoded_andMatrixOutputs_T_141, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_143}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_7 = \|{&_decoded_andMatrixOutputs_T_97, &_decoded_andMatrixOutputs_T_99, &_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_101, &_decoded_andMatrixOutputs_T_103, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_111, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_123, &_decoded_andMatrixOutputs_T_125, &_decoded_andMatrixOutputs_T_132, &_decoded_andMatrixOutputs_T_133, &_decoded_andMatrixOutputs_T_135, &_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_138, &_decoded_andMatrixOutputs_T_139, &_decoded_andMatrixOutputs_T_141, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_143}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_5 = \|{&_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_143}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_6 = \|{&_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_143}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_7 = \|{&_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_143}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_0 = \|decoded_orMatrixOutputs_hi_hi_58; // @[pla.scala:114:{19,36}] assign io_resp_2_vc_sel_0_1 = \|decoded_orMatrixOutputs_hi_hi_58; // @[pla.scala:114:{19,36}] assign io_resp_2_vc_sel_0_2 = \|{&_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_96, &_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_109, &_decoded_andMatrixOutputs_T_119, &_decoded_andMatrixOutputs_T_124}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_3 = \|{&_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_96, &_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_109, &_decoded_andMatrixOutputs_T_119, &_decoded_andMatrixOutputs_T_124}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_4 = \|{&_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_96, &_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_109, &_decoded_andMatrixOutputs_T_119, &_decoded_andMatrixOutputs_T_124, &_decoded_andMatrixOutputs_T_127, &_decoded_andMatrixOutputs_T_128}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_5 = \|{&_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_96, &_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_109, &_decoded_andMatrixOutputs_T_119, &_decoded_andMatrixOutputs_T_124, &_decoded_andMatrixOutputs_T_127, &_decoded_andMatrixOutputs_T_128}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_6 = \|{&_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_96, &_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_109, &_decoded_andMatrixOutputs_T_119, &_decoded_andMatrixOutputs_T_124, &_decoded_andMatrixOutputs_T_127, &_decoded_andMatrixOutputs_T_128}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_7 = \|{&_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_96, &_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_109, &_decoded_andMatrixOutputs_T_119, &_decoded_andMatrixOutputs_T_124, &_decoded_andMatrixOutputs_T_127, &_decoded_andMatrixOutputs_T_128}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_0 = \|{&{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16]}, &{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_1 = \|{&_decoded_andMatrixOutputs_T_41, &_decoded_andMatrixOutputs_T_43, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_48, &_decoded_andMatrixOutputs_T_50, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_66, &_decoded_andMatrixOutputs_T_68, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_2 = \|{&_decoded_andMatrixOutputs_T_41, &_decoded_andMatrixOutputs_T_43, &_decoded_andMatrixOutputs_T_48, &_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_66, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}, &_decoded_andMatrixOutputs_T_79}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_3 = \|{&_decoded_andMatrixOutputs_T_41, &_decoded_andMatrixOutputs_T_43, &_decoded_andMatrixOutputs_T_48, &_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_64, &_decoded_andMatrixOutputs_T_66, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_79}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_4 = \|{&_decoded_andMatrixOutputs_T_41, &_decoded_andMatrixOutputs_T_43, &_decoded_andMatrixOutputs_T_48, &_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_64, &_decoded_andMatrixOutputs_T_66, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_79, &{decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}, &{decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_5 = \|{&_decoded_andMatrixOutputs_T_41, &_decoded_andMatrixOutputs_T_43, &_decoded_andMatrixOutputs_T_48, &_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_64, &_decoded_andMatrixOutputs_T_66, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_79, &_decoded_andMatrixOutputs_T_86, &_decoded_andMatrixOutputs_T_87, &_decoded_andMatrixOutputs_T_90, &_decoded_andMatrixOutputs_T_91}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_6 = \|{&_decoded_andMatrixOutputs_T_41, &_decoded_andMatrixOutputs_T_43, &_decoded_andMatrixOutputs_T_48, &_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_64, &_decoded_andMatrixOutputs_T_66, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_79, &_decoded_andMatrixOutputs_T_86, &_decoded_andMatrixOutputs_T_87, &_decoded_andMatrixOutputs_T_90, &_decoded_andMatrixOutputs_T_91}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_7 = \|{&_decoded_andMatrixOutputs_T_41, &_decoded_andMatrixOutputs_T_43, &_decoded_andMatrixOutputs_T_48, &_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_64, &_decoded_andMatrixOutputs_T_66, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_79, &_decoded_andMatrixOutputs_T_86, &_decoded_andMatrixOutputs_T_87, &_decoded_andMatrixOutputs_T_90, &_decoded_andMatrixOutputs_T_91}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_0 = &{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], decoded_invInputs_1[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_1_vc_sel_3_1 = \|{&_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_67}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_2 = \|{&_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_49, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_67, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_3 = \|{&_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_61, &_decoded_andMatrixOutputs_T_63, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_67, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_4 = \|{&_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_61, &_decoded_andMatrixOutputs_T_63, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_67, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77, &{decoded_invInputs_1[0], decoded_invInputs_1[1], decoded_invInputs_1[2], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_5 = \|{&_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_61, &_decoded_andMatrixOutputs_T_63, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_67, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77, &_decoded_andMatrixOutputs_T_85, &_decoded_andMatrixOutputs_T_88, &_decoded_andMatrixOutputs_T_89, &_decoded_andMatrixOutputs_T_92}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_6 = \|{&_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_61, &_decoded_andMatrixOutputs_T_63, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_67, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77, &_decoded_andMatrixOutputs_T_85, &_decoded_andMatrixOutputs_T_88, &_decoded_andMatrixOutputs_T_89, &_decoded_andMatrixOutputs_T_92}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_7 = \|{&_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_61, &_decoded_andMatrixOutputs_T_63, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_67, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77, &_decoded_andMatrixOutputs_T_85, &_decoded_andMatrixOutputs_T_88, &_decoded_andMatrixOutputs_T_89, &_decoded_andMatrixOutputs_T_92}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_1 = \|{&{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_53, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_2 = \|{&_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_53, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_3 = \|{&_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_53, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_4 = \|{&_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_53, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_5 = \|{&_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_53, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_6 = \|{&_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_53, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_7 = \|{&_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_53, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_0 = \|decoded_orMatrixOutputs_hi_hi_38; // @[pla.scala:114:{19,36}] assign io_resp_1_vc_sel_0_1 = \|decoded_orMatrixOutputs_hi_hi_38; // @[pla.scala:114:{19,36}] assign io_resp_1_vc_sel_0_2 = \|{&_decoded_andMatrixOutputs_T_36, &_decoded_andMatrixOutputs_T_38, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_78}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_3 = \|{&_decoded_andMatrixOutputs_T_36, &_decoded_andMatrixOutputs_T_38, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_78}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_4 = \|{&_decoded_andMatrixOutputs_T_36, &_decoded_andMatrixOutputs_T_38, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_78, &_decoded_andMatrixOutputs_T_81, &_decoded_andMatrixOutputs_T_82}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_5 = \|{&_decoded_andMatrixOutputs_T_36, &_decoded_andMatrixOutputs_T_38, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_78, &_decoded_andMatrixOutputs_T_81, &_decoded_andMatrixOutputs_T_82}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_6 = \|{&_decoded_andMatrixOutputs_T_36, &_decoded_andMatrixOutputs_T_38, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_78, &_decoded_andMatrixOutputs_T_81, &_decoded_andMatrixOutputs_T_82}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_7 = \|{&_decoded_andMatrixOutputs_T_36, &_decoded_andMatrixOutputs_T_38, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_78, &_decoded_andMatrixOutputs_T_81, &_decoded_andMatrixOutputs_T_82}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_4_1 = \|{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_4_2 = \|{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_26}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_4_3 = \|{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_12, &{decoded_invInputs[0], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_26, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_4_4 = \|{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_26, &_decoded_andMatrixOutputs_T_32}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_4_5 = \|{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_26, &_decoded_andMatrixOutputs_T_32}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_4_6 = \|{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_26, &_decoded_andMatrixOutputs_T_32}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_4_7 = \|{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_26, &_decoded_andMatrixOutputs_T_32}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_1 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_25}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_2 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_25}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_3 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_25, &_decoded_andMatrixOutputs_T_30}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_4 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_25, &_decoded_andMatrixOutputs_T_30}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_5 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_25, &_decoded_andMatrixOutputs_T_30}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_6 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_25, &_decoded_andMatrixOutputs_T_30}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_7 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_25, &_decoded_andMatrixOutputs_T_30}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_1 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_22}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_2 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_22}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_3 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_22, &_decoded_andMatrixOutputs_T_31, &_decoded_andMatrixOutputs_T_33}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_4 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_22, &_decoded_andMatrixOutputs_T_31, &_decoded_andMatrixOutputs_T_33}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_5 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_22, &_decoded_andMatrixOutputs_T_31, &_decoded_andMatrixOutputs_T_33}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_6 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_22, &_decoded_andMatrixOutputs_T_31, &_decoded_andMatrixOutputs_T_33}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_7 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_22, &_decoded_andMatrixOutputs_T_31, &_decoded_andMatrixOutputs_T_33}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_1 = \|{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_2 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_23}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_3 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_9, &{decoded_invInputs[0], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_23, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_4 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_23, &_decoded_andMatrixOutputs_T_28}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_5 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_23, &_decoded_andMatrixOutputs_T_28}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_6 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_23, &_decoded_andMatrixOutputs_T_28}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_7 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_23, &_decoded_andMatrixOutputs_T_28}; // @[pla.scala:98:{53,70}, :114:{19,36}] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module InputBuffer_1( // @[InputUnit.scala:49:7] input clock, // @[InputUnit.scala:49:7] input reset, // @[InputUnit.scala:49:7] input io_enq_0_valid, // @[InputUnit.scala:51:14] input io_enq_0_bits_head, // @[InputUnit.scala:51:14] input io_enq_0_bits_tail, // @[InputUnit.scala:51:14] input [72:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14] input [4:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14] output io_deq_0_bits_head, // @[InputUnit.scala:51:14] output io_deq_0_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14] output io_deq_1_bits_head, // @[InputUnit.scala:51:14] output io_deq_1_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14] input io_deq_2_ready, // @[InputUnit.scala:51:14] output io_deq_2_valid, // @[InputUnit.scala:51:14] output io_deq_2_bits_head, // @[InputUnit.scala:51:14] output io_deq_2_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14] input io_deq_3_ready, // @[InputUnit.scala:51:14] output io_deq_3_valid, // @[InputUnit.scala:51:14] output io_deq_3_bits_head, // @[InputUnit.scala:51:14] output io_deq_3_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_3_bits_payload, // @[InputUnit.scala:51:14] output io_deq_4_bits_head, // @[InputUnit.scala:51:14] output io_deq_4_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_4_bits_payload, // @[InputUnit.scala:51:14] output io_deq_5_bits_head, // @[InputUnit.scala:51:14] output io_deq_5_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_5_bits_payload, // @[InputUnit.scala:51:14] output io_deq_6_bits_head, // @[InputUnit.scala:51:14] output io_deq_6_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_6_bits_payload, // @[InputUnit.scala:51:14] output io_deq_7_bits_head, // @[InputUnit.scala:51:14] output io_deq_7_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_7_bits_payload, // @[InputUnit.scala:51:14] output io_deq_8_bits_head, // @[InputUnit.scala:51:14] output io_deq_8_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_8_bits_payload, // @[InputUnit.scala:51:14] output io_deq_9_bits_head, // @[InputUnit.scala:51:14] output io_deq_9_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_9_bits_payload, // @[InputUnit.scala:51:14] input io_deq_10_ready, // @[InputUnit.scala:51:14] output io_deq_10_valid, // @[InputUnit.scala:51:14] output io_deq_10_bits_head, // @[InputUnit.scala:51:14] output io_deq_10_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_10_bits_payload, // @[InputUnit.scala:51:14] input io_deq_11_ready, // @[InputUnit.scala:51:14] output io_deq_11_valid, // @[InputUnit.scala:51:14] output io_deq_11_bits_head, // @[InputUnit.scala:51:14] output io_deq_11_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_11_bits_payload, // @[InputUnit.scala:51:14] input io_deq_12_ready, // @[InputUnit.scala:51:14] output io_deq_12_valid, // @[InputUnit.scala:51:14] output io_deq_12_bits_head, // @[InputUnit.scala:51:14] output io_deq_12_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_12_bits_payload, // @[InputUnit.scala:51:14] input io_deq_13_ready, // @[InputUnit.scala:51:14] output io_deq_13_valid, // @[InputUnit.scala:51:14] output io_deq_13_bits_head, // @[InputUnit.scala:51:14] output io_deq_13_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_13_bits_payload, // @[InputUnit.scala:51:14] input io_deq_14_ready, // @[InputUnit.scala:51:14] output io_deq_14_valid, // @[InputUnit.scala:51:14] output io_deq_14_bits_head, // @[InputUnit.scala:51:14] output io_deq_14_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_14_bits_payload, // @[InputUnit.scala:51:14] input io_deq_15_ready, // @[InputUnit.scala:51:14] output io_deq_15_valid, // @[InputUnit.scala:51:14] output io_deq_15_bits_head, // @[InputUnit.scala:51:14] output io_deq_15_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_15_bits_payload, // @[InputUnit.scala:51:14] input io_deq_16_ready, // @[InputUnit.scala:51:14] output io_deq_16_valid, // @[InputUnit.scala:51:14] output io_deq_16_bits_head, // @[InputUnit.scala:51:14] output io_deq_16_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_16_bits_payload, // @[InputUnit.scala:51:14] input io_deq_17_ready, // @[InputUnit.scala:51:14] output io_deq_17_valid, // @[InputUnit.scala:51:14] output io_deq_17_bits_head, // @[InputUnit.scala:51:14] output io_deq_17_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_17_bits_payload, // @[InputUnit.scala:51:14] input io_deq_18_ready, // @[InputUnit.scala:51:14] output io_deq_18_valid, // @[InputUnit.scala:51:14] output io_deq_18_bits_head, // @[InputUnit.scala:51:14] output io_deq_18_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_18_bits_payload, // @[InputUnit.scala:51:14] input io_deq_19_ready, // @[InputUnit.scala:51:14] output io_deq_19_valid, // @[InputUnit.scala:51:14] output io_deq_19_bits_head, // @[InputUnit.scala:51:14] output io_deq_19_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_19_bits_payload, // @[InputUnit.scala:51:14] input io_deq_20_ready, // @[InputUnit.scala:51:14] output io_deq_20_valid, // @[InputUnit.scala:51:14] output io_deq_20_bits_head, // @[InputUnit.scala:51:14] output io_deq_20_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_20_bits_payload, // @[InputUnit.scala:51:14] input io_deq_21_ready, // @[InputUnit.scala:51:14] output io_deq_21_valid, // @[InputUnit.scala:51:14] output io_deq_21_bits_head, // @[InputUnit.scala:51:14] output io_deq_21_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_21_bits_payload // @[InputUnit.scala:51:14] ); wire _qs_21_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_20_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_19_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_18_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_17_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_16_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_15_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_14_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_13_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_12_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_11_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_10_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_9_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_8_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_7_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_6_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_5_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_4_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49] wire [74:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R4_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R5_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R6_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R7_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R8_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R9_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R10_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R11_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R12_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R13_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R14_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R15_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R16_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R17_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R18_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R19_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R20_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R21_data; // @[InputUnit.scala:85:18] reg [5:0] heads_0; // @[InputUnit.scala:86:24] reg [5:0] heads_1; // @[InputUnit.scala:86:24] reg [5:0] heads_2; // @[InputUnit.scala:86:24] reg [5:0] heads_3; // @[InputUnit.scala:86:24] reg [5:0] heads_4; // @[InputUnit.scala:86:24] reg [5:0] heads_5; // @[InputUnit.scala:86:24] reg [5:0] heads_6; // @[InputUnit.scala:86:24] reg [5:0] heads_7; // @[InputUnit.scala:86:24] reg [5:0] heads_8; // @[InputUnit.scala:86:24] reg [5:0] heads_9; // @[InputUnit.scala:86:24] reg [5:0] heads_10; // @[InputUnit.scala:86:24] reg [5:0] heads_11; // @[InputUnit.scala:86:24] reg [5:0] heads_12; // @[InputUnit.scala:86:24] reg [5:0] heads_13; // @[InputUnit.scala:86:24] reg [5:0] heads_14; // @[InputUnit.scala:86:24] reg [5:0] heads_15; // @[InputUnit.scala:86:24] reg [5:0] heads_16; // @[InputUnit.scala:86:24] reg [5:0] heads_17; // @[InputUnit.scala:86:24] reg [5:0] heads_18; // @[InputUnit.scala:86:24] reg [5:0] heads_19; // @[InputUnit.scala:86:24] reg [5:0] heads_20; // @[InputUnit.scala:86:24] reg [5:0] heads_21; // @[InputUnit.scala:86:24] reg [5:0] tails_0; // @[InputUnit.scala:87:24] reg [5:0] tails_1; // @[InputUnit.scala:87:24] reg [5:0] tails_2; // @[InputUnit.scala:87:24] reg [5:0] tails_3; // @[InputUnit.scala:87:24] reg [5:0] tails_4; // @[InputUnit.scala:87:24] reg [5:0] tails_5; // @[InputUnit.scala:87:24] reg [5:0] tails_6; // @[InputUnit.scala:87:24] reg [5:0] tails_7; // @[InputUnit.scala:87:24] reg [5:0] tails_8; // @[InputUnit.scala:87:24] reg [5:0] tails_9; // @[InputUnit.scala:87:24] reg [5:0] tails_10; // @[InputUnit.scala:87:24] reg [5:0] tails_11; // @[InputUnit.scala:87:24] reg [5:0] tails_12; // @[InputUnit.scala:87:24] reg [5:0] tails_13; // @[InputUnit.scala:87:24] reg [5:0] tails_14; // @[InputUnit.scala:87:24] reg [5:0] tails_15; // @[InputUnit.scala:87:24] reg [5:0] tails_16; // @[InputUnit.scala:87:24] reg [5:0] tails_17; // @[InputUnit.scala:87:24] reg [5:0] tails_18; // @[InputUnit.scala:87:24] reg [5:0] tails_19; // @[InputUnit.scala:87:24] reg [5:0] tails_20; // @[InputUnit.scala:87:24] reg [5:0] tails_21; // @[InputUnit.scala:87:24] wire _tails_T_66 = io_enq_0_bits_virt_channel_id == 5'h0; // @[Mux.scala:32:36] wire _tails_T_67 = io_enq_0_bits_virt_channel_id == 5'h1; // @[Mux.scala:32:36] wire _tails_T_68 = io_enq_0_bits_virt_channel_id == 5'h2; // @[Mux.scala:32:36] wire _tails_T_69 = io_enq_0_bits_virt_channel_id == 5'h3; // @[Mux.scala:32:36] wire _tails_T_70 = io_enq_0_bits_virt_channel_id == 5'h4; // @[Mux.scala:32:36] wire _tails_T_71 = io_enq_0_bits_virt_channel_id == 5'h5; // @[Mux.scala:32:36] wire _tails_T_72 = io_enq_0_bits_virt_channel_id == 5'h6; // @[Mux.scala:32:36] wire _tails_T_73 = io_enq_0_bits_virt_channel_id == 5'h7; // @[Mux.scala:32:36] wire _tails_T_74 = io_enq_0_bits_virt_channel_id == 5'h8; // @[Mux.scala:32:36] wire _tails_T_75 = io_enq_0_bits_virt_channel_id == 5'h9; // @[Mux.scala:32:36] wire _tails_T_76 = io_enq_0_bits_virt_channel_id == 5'hA; // @[Mux.scala:32:36] wire _tails_T_77 = io_enq_0_bits_virt_channel_id == 5'hB; // @[Mux.scala:32:36] wire _tails_T_78 = io_enq_0_bits_virt_channel_id == 5'hC; // @[Mux.scala:32:36] wire _tails_T_79 = io_enq_0_bits_virt_channel_id == 5'hD; // @[Mux.scala:32:36] wire _tails_T_80 = io_enq_0_bits_virt_channel_id == 5'hE; // @[Mux.scala:32:36] wire _tails_T_81 = io_enq_0_bits_virt_channel_id == 5'hF; // @[Mux.scala:32:36] wire _tails_T_82 = io_enq_0_bits_virt_channel_id == 5'h10; // @[Mux.scala:32:36] wire _tails_T_83 = io_enq_0_bits_virt_channel_id == 5'h11; // @[Mux.scala:32:36] wire _tails_T_84 = io_enq_0_bits_virt_channel_id == 5'h12; // @[Mux.scala:32:36] wire _tails_T_85 = io_enq_0_bits_virt_channel_id == 5'h13; // @[Mux.scala:32:36] wire _tails_T_86 = io_enq_0_bits_virt_channel_id == 5'h14; // @[Mux.scala:32:36] wire _tails_T_87 = io_enq_0_bits_virt_channel_id == 5'h15; // @[Mux.scala:32:36] wire direct_to_q = (_tails_T_66 & _qs_0_io_enq_ready \| _tails_T_67 & _qs_1_io_enq_ready \| _tails_T_68 & _qs_2_io_enq_ready \| _tails_T_69 & _qs_3_io_enq_ready \| _tails_T_70 & _qs_4_io_enq_ready \| _tails_T_71 & _qs_5_io_enq_ready \| _tails_T_72 & _qs_6_io_enq_ready \| _tails_T_73 & _qs_7_io_enq_ready \| _tails_T_74 & _qs_8_io_enq_ready \| _tails_T_75 & _qs_9_io_enq_ready \| _tails_T_76 & _qs_10_io_enq_ready \| _tails_T_77 & _qs_11_io_enq_ready \| _tails_T_78 & _qs_12_io_enq_ready \| _tails_T_79 & _qs_13_io_enq_ready \| _tails_T_80 & _qs_14_io_enq_ready \| _tails_T_81 & _qs_15_io_enq_ready \| _tails_T_82 & _qs_16_io_enq_ready \| _tails_T_83 & _qs_17_io_enq_ready \| _tails_T_84 & _qs_18_io_enq_ready \| _tails_T_85 & _qs_19_io_enq_ready \| _tails_T_86 & _qs_20_io_enq_ready \| _tails_T_87 & _qs_21_io_enq_ready) & (_tails_T_66 & heads_0 == tails_0 \| _tails_T_67 & heads_1 == tails_1 \| _tails_T_68 & heads_2 == tails_2 \| _tails_T_69 & heads_3 == tails_3 \| _tails_T_70 & heads_4 == tails_4 \| _tails_T_71 & heads_5 == tails_5 \| _tails_T_72 & heads_6 == tails_6 \| _tails_T_73 & heads_7 == tails_7 \| _tails_T_74 & heads_8 == tails_8 \| _tails_T_75 & heads_9 == tails_9 \| _tails_T_76 & heads_10 == tails_10 \| _tails_T_77 & heads_11 == tails_11 \| _tails_T_78 & heads_12 == tails_12 \| _tails_T_79 & heads_13 == tails_13 \| _tails_T_80 & heads_14 == tails_14 \| _tails_T_81 & heads_15 == tails_15 \| _tails_T_82 & heads_16 == tails_16 \| _tails_T_83 & heads_17 == tails_17 \| _tails_T_84 & heads_18 == tails_18 \| _tails_T_85 & heads_19 == tails_19 \| _tails_T_86 & heads_20 == tails_20 \| _tails_T_87 & heads_21 == tails_21); // @[Mux.scala:30:73, :32:36] wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}] wire [31:0][5:0] _GEN = {{tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_21}, {tails_20}, {tails_19}, {tails_18}, {tails_17}, {tails_16}, {tails_15}, {tails_14}, {tails_13}, {tails_12}, {tails_11}, {tails_10}, {tails_9}, {tails_8}, {tails_7}, {tails_6}, {tails_5}, {tails_4}, {tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16] wire _GEN_0 = io_enq_0_bits_virt_channel_id == 5'h0; // @[InputUnit.scala:103:45] wire _GEN_1 = io_enq_0_bits_virt_channel_id == 5'h1; // @[InputUnit.scala:103:45] wire _GEN_2 = io_enq_0_bits_virt_channel_id == 5'h2; // @[InputUnit.scala:103:45] wire _GEN_3 = io_enq_0_bits_virt_channel_id == 5'h3; // @[InputUnit.scala:103:45] wire _GEN_4 = io_enq_0_bits_virt_channel_id == 5'h4; // @[InputUnit.scala:103:45] wire _GEN_5 = io_enq_0_bits_virt_channel_id == 5'h5; // @[InputUnit.scala:103:45] wire _GEN_6 = io_enq_0_bits_virt_channel_id == 5'h6; // @[InputUnit.scala:103:45] wire _GEN_7 = io_enq_0_bits_virt_channel_id == 5'h7; // @[InputUnit.scala:103:45] wire _GEN_8 = io_enq_0_bits_virt_channel_id == 5'h8; // @[InputUnit.scala:103:45] wire _GEN_9 = io_enq_0_bits_virt_channel_id == 5'h9; // @[InputUnit.scala:103:45] wire _GEN_10 = io_enq_0_bits_virt_channel_id == 5'hA; // @[InputUnit.scala:103:45] wire _GEN_11 = io_enq_0_bits_virt_channel_id == 5'hB; // @[InputUnit.scala:103:45] wire _GEN_12 = io_enq_0_bits_virt_channel_id == 5'hC; // @[InputUnit.scala:103:45] wire _GEN_13 = io_enq_0_bits_virt_channel_id == 5'hD; // @[InputUnit.scala:103:45] wire _GEN_14 = io_enq_0_bits_virt_channel_id == 5'hE; // @[InputUnit.scala:103:45] wire _GEN_15 = io_enq_0_bits_virt_channel_id == 5'hF; // @[InputUnit.scala:103:45] wire _GEN_16 = io_enq_0_bits_virt_channel_id == 5'h10; // @[InputUnit.scala:103:45] wire _GEN_17 = io_enq_0_bits_virt_channel_id == 5'h11; // @[InputUnit.scala:103:45] wire _GEN_18 = io_enq_0_bits_virt_channel_id == 5'h12; // @[InputUnit.scala:103:45] wire _GEN_19 = io_enq_0_bits_virt_channel_id == 5'h13; // @[InputUnit.scala:103:45] wire _GEN_20 = io_enq_0_bits_virt_channel_id == 5'h14; // @[InputUnit.scala:103:45] wire _GEN_21 = io_enq_0_bits_virt_channel_id == 5'h15; // @[InputUnit.scala:103:45] wire _GEN_22 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34] wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_4 = heads_4 != tails_4 & _qs_4_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_5 = heads_5 != tails_5 & _qs_5_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_6 = heads_6 != tails_6 & _qs_6_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_7 = heads_7 != tails_7 & _qs_7_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_8 = heads_8 != tails_8 & _qs_8_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_9 = heads_9 != tails_9 & _qs_9_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_10 = heads_10 != tails_10 & _qs_10_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_11 = heads_11 != tails_11 & _qs_11_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_12 = heads_12 != tails_12 & _qs_12_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_13 = heads_13 != tails_13 & _qs_13_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_14 = heads_14 != tails_14 & _qs_14_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_15 = heads_15 != tails_15 & _qs_15_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_16 = heads_16 != tails_16 & _qs_16_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_17 = heads_17 != tails_17 & _qs_17_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_18 = heads_18 != tails_18 & _qs_18_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_19 = heads_19 != tails_19 & _qs_19_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_20 = heads_20 != tails_20 & _qs_20_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_21 = heads_21 != tails_21 & _qs_21_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire [21:0] to_q_oh_enc = can_to_q_0 ? 22'h1 : can_to_q_1 ? 22'h2 : can_to_q_2 ? 22'h4 : can_to_q_3 ? 22'h8 : can_to_q_4 ? 22'h10 : can_to_q_5 ? 22'h20 : can_to_q_6 ? 22'h40 : can_to_q_7 ? 22'h80 : can_to_q_8 ? 22'h100 : can_to_q_9 ? 22'h200 : can_to_q_10 ? 22'h400 : can_to_q_11 ? 22'h800 : can_to_q_12 ? 22'h1000 : can_to_q_13 ? 22'h2000 : can_to_q_14 ? 22'h4000 : can_to_q_15 ? 22'h8000 : can_to_q_16 ? 22'h10000 : can_to_q_17 ? 22'h20000 : can_to_q_18 ? 22'h40000 : can_to_q_19 ? 22'h80000 : can_to_q_20 ? 22'h100000 : {can_to_q_21, 21'h0}; // @[Mux.scala:50:70] wire _GEN_23 = can_to_q_0 \| can_to_q_1 \| can_to_q_2 \| can_to_q_3 \| can_to_q_4 \| can_to_q_5 \| can_to_q_6 \| can_to_q_7 \| can_to_q_8 \| can_to_q_9 \| can_to_q_10 \| can_to_q_11 \| can_to_q_12 \| can_to_q_13 \| can_to_q_14 \| can_to_q_15 \| can_to_q_16 \| can_to_q_17 \| can_to_q_18 \| can_to_q_19 \| can_to_q_20 \| can_to_q_21; // @[package.scala:81:59] wire [5:0] head = (to_q_oh_enc[0] ? heads_0 : 6'h0) \| (to_q_oh_enc[1] ? heads_1 : 6'h0) \| (to_q_oh_enc[2] ? heads_2 : 6'h0) \| (to_q_oh_enc[3] ? heads_3 : 6'h0) \| (to_q_oh_enc[4] ? heads_4 : 6'h0) \| (to_q_oh_enc[5] ? heads_5 : 6'h0) \| (to_q_oh_enc[6] ? heads_6 : 6'h0) \| (to_q_oh_enc[7] ? heads_7 : 6'h0) \| (to_q_oh_enc[8] ? heads_8 : 6'h0) \| (to_q_oh_enc[9] ? heads_9 : 6'h0) \| (to_q_oh_enc[10] ? heads_10 : 6'h0) \| (to_q_oh_enc[11] ? heads_11 : 6'h0) \| (to_q_oh_enc[12] ? heads_12 : 6'h0) \| (to_q_oh_enc[13] ? heads_13 : 6'h0) \| (to_q_oh_enc[14] ? heads_14 : 6'h0) \| (to_q_oh_enc[15] ? heads_15 : 6'h0) \| (to_q_oh_enc[16] ? heads_16 : 6'h0) \| (to_q_oh_enc[17] ? heads_17 : 6'h0) \| (to_q_oh_enc[18] ? heads_18 : 6'h0) \| (to_q_oh_enc[19] ? heads_19 : 6'h0) \| (to_q_oh_enc[20] ? heads_20 : 6'h0) \| (to_q_oh_enc[21] ? heads_21 : 6'h0); // @[OneHot.scala:83:30] wire _GEN_24 = _GEN_23 & to_q_oh_enc[0]; // @[OneHot.scala:83:30] wire _GEN_25 = _GEN_23 & to_q_oh_enc[1]; // @[OneHot.scala:83:30] wire _GEN_26 = _GEN_23 & to_q_oh_enc[2]; // @[OneHot.scala:83:30] wire _GEN_27 = _GEN_23 & to_q_oh_enc[3]; // @[OneHot.scala:83:30] wire _GEN_28 = _GEN_23 & to_q_oh_enc[4]; // @[OneHot.scala:83:30] wire _GEN_29 = _GEN_23 & to_q_oh_enc[5]; // @[OneHot.scala:83:30] wire _GEN_30 = _GEN_23 & to_q_oh_enc[6]; // @[OneHot.scala:83:30] wire _GEN_31 = _GEN_23 & to_q_oh_enc[7]; // @[OneHot.scala:83:30] wire _GEN_32 = _GEN_23 & to_q_oh_enc[8]; // @[OneHot.scala:83:30] wire _GEN_33 = _GEN_23 & to_q_oh_enc[9]; // @[OneHot.scala:83:30] wire _GEN_34 = _GEN_23 & to_q_oh_enc[10]; // @[OneHot.scala:83:30] wire _GEN_35 = _GEN_23 & to_q_oh_enc[11]; // @[OneHot.scala:83:30] wire _GEN_36 = _GEN_23 & to_q_oh_enc[12]; // @[OneHot.scala:83:30] wire _GEN_37 = _GEN_23 & to_q_oh_enc[13]; // @[OneHot.scala:83:30] wire _GEN_38 = _GEN_23 & to_q_oh_enc[14]; // @[OneHot.scala:83:30] wire _GEN_39 = _GEN_23 & to_q_oh_enc[15]; // @[OneHot.scala:83:30] wire _GEN_40 = _GEN_23 & to_q_oh_enc[16]; // @[OneHot.scala:83:30] wire _GEN_41 = _GEN_23 & to_q_oh_enc[17]; // @[OneHot.scala:83:30] wire _GEN_42 = _GEN_23 & to_q_oh_enc[18]; // @[OneHot.scala:83:30] wire _GEN_43 = _GEN_23 & to_q_oh_enc[19]; // @[OneHot.scala:83:30] wire _GEN_44 = _GEN_23 & to_q_oh_enc[20]; // @[OneHot.scala:83:30] wire _GEN_45 = _GEN_23 & to_q_oh_enc[21]; // @[OneHot.scala:83:30] wire [5:0] _tails_T_133 = _GEN[io_enq_0_bits_virt_channel_id] == ({1'h0, {1'h0, {1'h0, {1'h0, {2{_tails_T_68}}} \| {3{_tails_T_69}}} \| (_tails_T_76 ? 4'hB : 4'h0) \| {4{_tails_T_77}}} \| (_tails_T_78 ? 5'h13 : 5'h0) \| (_tails_T_79 ? 5'h17 : 5'h0) \| (_tails_T_80 ? 5'h1B : 5'h0) \| {5{_tails_T_81}}} \| (_tails_T_82 ? 6'h23 : 6'h0) \| (_tails_T_83 ? 6'h27 : 6'h0) \| (_tails_T_84 ? 6'h2B : 6'h0) \| (_tails_T_85 ? 6'h2F : 6'h0) \| (_tails_T_86 ? 6'h33 : 6'h0) \| (_tails_T_87 ? 6'h37 : 6'h0)) ? {_tails_T_82, {_tails_T_78, {_tails_T_76, _tails_T_69, 2'h0} \| (_tails_T_77 ? 4'hC : 4'h0)} \| (_tails_T_79 ? 5'h14 : 5'h0) \| (_tails_T_80 ? 5'h18 : 5'h0) \| (_tails_T_81 ? 5'h1C : 5'h0)} \| (_tails_T_83 ? 6'h24 : 6'h0) \| (_tails_T_84 ? 6'h28 : 6'h0) \| (_tails_T_85 ? 6'h2C : 6'h0) \| (_tails_T_86 ? 6'h30 : 6'h0) \| (_tails_T_87 ? 6'h34 : 6'h0) : _GEN[io_enq_0_bits_virt_channel_id] + 6'h1; // @[Mux.scala:30:73, :32:36] wire [14:0] _to_q_T_2 = {10'h0, to_q_oh_enc[21:17]} \| to_q_oh_enc[15:1]; // @[OneHot.scala:31:18, :32:28] wire [6:0] _to_q_T_4 = _to_q_T_2[14:8] \| _to_q_T_2[6:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] _to_q_T_6 = _to_q_T_4[6:4] \| _to_q_T_4[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire _to_q_T_8 = _to_q_T_6[2] \| _to_q_T_6[0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [4:0] to_q = {\|(to_q_oh_enc[21:16]), \|(_to_q_T_2[14:7]), \|(_to_q_T_4[6:3]), \|(_to_q_T_6[2:1]), _to_q_T_8}; // @[OneHot.scala:30:18, :32:{10,14,28}] wire [5:0] _heads_T_89 = head == ({1'h0, {1'h0, {1'h0, {1'h0, {2{to_q_oh_enc[2]}}} \| {3{to_q_oh_enc[3]}}} \| (to_q_oh_enc[10] ? 4'hB : 4'h0) \| {4{to_q_oh_enc[11]}}} \| (to_q_oh_enc[12] ? 5'h13 : 5'h0) \| (to_q_oh_enc[13] ? 5'h17 : 5'h0) \| (to_q_oh_enc[14] ? 5'h1B : 5'h0) \| {5{to_q_oh_enc[15]}}} \| (to_q_oh_enc[16] ? 6'h23 : 6'h0) \| (to_q_oh_enc[17] ? 6'h27 : 6'h0) \| (to_q_oh_enc[18] ? 6'h2B : 6'h0) \| (to_q_oh_enc[19] ? 6'h2F : 6'h0) \| (to_q_oh_enc[20] ? 6'h33 : 6'h0) \| (to_q_oh_enc[21] ? 6'h37 : 6'h0)) ? {to_q_oh_enc[16], {to_q_oh_enc[12], {to_q_oh_enc[10], to_q_oh_enc[3], 2'h0} \| (to_q_oh_enc[11] ? 4'hC : 4'h0)} \| (to_q_oh_enc[13] ? 5'h14 : 5'h0) \| (to_q_oh_enc[14] ? 5'h18 : 5'h0) \| (to_q_oh_enc[15] ? 5'h1C : 5'h0)} \| (to_q_oh_enc[17] ? 6'h24 : 6'h0) \| (to_q_oh_enc[18] ? 6'h28 : 6'h0) \| (to_q_oh_enc[19] ? 6'h2C : 6'h0) \| (to_q_oh_enc[20] ? 6'h30 : 6'h0) \| (to_q_oh_enc[21] ? 6'h34 : 6'h0) : head + 6'h1; // @[OneHot.scala:83:30] always @(posedge clock) begin // @[InputUnit.scala:49:7] if (reset) begin // @[InputUnit.scala:49:7] heads_0 <= 6'h0; // @[InputUnit.scala:86:24] heads_1 <= 6'h0; // @[InputUnit.scala:86:24] heads_2 <= 6'h0; // @[InputUnit.scala:86:24] heads_3 <= 6'h4; // @[InputUnit.scala:86:24] heads_4 <= 6'h0; // @[InputUnit.scala:86:24] heads_5 <= 6'h0; // @[InputUnit.scala:86:24] heads_6 <= 6'h0; // @[InputUnit.scala:86:24] heads_7 <= 6'h0; // @[InputUnit.scala:86:24] heads_8 <= 6'h0; // @[InputUnit.scala:86:24] heads_9 <= 6'h0; // @[InputUnit.scala:86:24] heads_10 <= 6'h8; // @[InputUnit.scala:86:24] heads_11 <= 6'hC; // @[InputUnit.scala:86:24] heads_12 <= 6'h10; // @[InputUnit.scala:86:24] heads_13 <= 6'h14; // @[InputUnit.scala:86:24] heads_14 <= 6'h18; // @[InputUnit.scala:86:24] heads_15 <= 6'h1C; // @[InputUnit.scala:86:24] heads_16 <= 6'h20; // @[InputUnit.scala:86:24] heads_17 <= 6'h24; // @[InputUnit.scala:86:24] heads_18 <= 6'h28; // @[InputUnit.scala:86:24] heads_19 <= 6'h2C; // @[InputUnit.scala:86:24] heads_20 <= 6'h30; // @[InputUnit.scala:86:24] heads_21 <= 6'h34; // @[InputUnit.scala:86:24] tails_0 <= 6'h0; // @[InputUnit.scala:87:24] tails_1 <= 6'h0; // @[InputUnit.scala:87:24] tails_2 <= 6'h0; // @[InputUnit.scala:87:24] tails_3 <= 6'h4; // @[InputUnit.scala:87:24] tails_4 <= 6'h0; // @[InputUnit.scala:87:24] tails_5 <= 6'h0; // @[InputUnit.scala:87:24] tails_6 <= 6'h0; // @[InputUnit.scala:87:24] tails_7 <= 6'h0; // @[InputUnit.scala:87:24] tails_8 <= 6'h0; // @[InputUnit.scala:87:24] tails_9 <= 6'h0; // @[InputUnit.scala:87:24] tails_10 <= 6'h8; // @[InputUnit.scala:87:24] tails_11 <= 6'hC; // @[InputUnit.scala:87:24] tails_12 <= 6'h10; // @[InputUnit.scala:87:24] tails_13 <= 6'h14; // @[InputUnit.scala:87:24] tails_14 <= 6'h18; // @[InputUnit.scala:87:24] tails_15 <= 6'h1C; // @[InputUnit.scala:87:24] tails_16 <= 6'h20; // @[InputUnit.scala:87:24] tails_17 <= 6'h24; // @[InputUnit.scala:87:24] tails_18 <= 6'h28; // @[InputUnit.scala:87:24] tails_19 <= 6'h2C; // @[InputUnit.scala:87:24] tails_20 <= 6'h30; // @[InputUnit.scala:87:24] tails_21 <= 6'h34; // @[InputUnit.scala:87:24] end else begin // @[InputUnit.scala:49:7] if (_GEN_23 & {to_q_oh_enc[21:16], \|(_to_q_T_2[14:7]), \|(_to_q_T_4[6:3]), \|(_to_q_T_6[2:1]), _to_q_T_8} == 10'h0) // @[OneHot.scala:30:18, :32:{10,14,28}] heads_0 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h1) // @[OneHot.scala:32:10] heads_1 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h2) // @[OneHot.scala:32:10] heads_2 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h3) // @[OneHot.scala:32:10] heads_3 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h4) // @[OneHot.scala:32:10] heads_4 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h5) // @[OneHot.scala:32:10] heads_5 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h6) // @[OneHot.scala:32:10] heads_6 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h7) // @[OneHot.scala:32:10] heads_7 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h8) // @[OneHot.scala:32:10] heads_8 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h9) // @[OneHot.scala:32:10] heads_9 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hA) // @[OneHot.scala:32:10] heads_10 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hB) // @[OneHot.scala:32:10] heads_11 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hC) // @[OneHot.scala:32:10] heads_12 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hD) // @[OneHot.scala:32:10] heads_13 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hE) // @[OneHot.scala:32:10] heads_14 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hF) // @[OneHot.scala:32:10] heads_15 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h10) // @[OneHot.scala:32:10] heads_16 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h11) // @[OneHot.scala:32:10] heads_17 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h12) // @[OneHot.scala:32:10] heads_18 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h13) // @[OneHot.scala:32:10] heads_19 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h14) // @[OneHot.scala:32:10] heads_20 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h15) // @[OneHot.scala:32:10] heads_21 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_0 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_1 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_2 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_3) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_3 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_4) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_4 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_5) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_5 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_6) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_6 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_7) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_7 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_8) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_8 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_9) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_9 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_10) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_10 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_11) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_11 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_12) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_12 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_13) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_13 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_14) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_14 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_15) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_15 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_16) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_16 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_17) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_17 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_18) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_18 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_19) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_19 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_20) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_20 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_21) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_21 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_20( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [4099:0] _c_sizes_set_T_1 = 4100'h0; // @[Monitor.scala:768:52] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79] wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77] wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35] wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35] wire [2055:0] c_sizes_set = 2056'h0; // @[Monitor.scala:741:34] wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34] wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34] wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 9'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 9'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 9'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_22 = _uncommonBits_T_22[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_23 = _uncommonBits_T_23[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_34 = _uncommonBits_T_34[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_35 = _uncommonBits_T_35[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_46 = _uncommonBits_T_46[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_47 = _uncommonBits_T_47[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_51 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_57 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_63 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_69 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 7'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 7'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 7'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 7'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 9'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 9'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 9'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1727 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1727; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1727; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [8:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1800 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1800; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1800; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1800; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [8:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [256:0] inflight; // @[Monitor.scala:614:27] reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [2055:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [256:0] a_set; // @[Monitor.scala:626:34] wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [2055:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [11:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [2055:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [2055:0] _a_size_lookup_T_6 = {2048'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [2055:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[2055:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [511:0] _GEN_3 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [511:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1653 = _T_1727 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1653 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1653 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1653 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [11:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1653 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [11:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [4099:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1653 ? _a_sizes_set_T_1[2055:0] : 2056'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [256:0] d_clr; // @[Monitor.scala:664:34] wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [2055:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1699 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1699 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1668 = _T_1800 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1668 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1668 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [4110:0] _d_sizes_clr_T_5 = 4111'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1668 ? _d_sizes_clr_T_5[2055:0] : 2056'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [256:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [1027:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [2055:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [2055:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [2055:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [256:0] inflight_1; // @[Monitor.scala:726:35] wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [2055:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [2055:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [2055:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [2055:0] _c_size_lookup_T_6 = {2048'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [2055:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[2055:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [256:0] d_clr_1; // @[Monitor.scala:774:34] wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [2055:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1771 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1771 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1753 = _T_1800 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1753 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1753 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [4110:0] _d_sizes_clr_T_11 = 4111'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1753 ? _d_sizes_clr_T_11[2055:0] : 2056'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113] wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [2055:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [2055:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File IOHandler.scala: package shuttle.dmem import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ class IOHandler(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Decoupled(new ShuttleDMemReq)) val resp = Decoupled(new ShuttleDMemResp) val mem_access = Decoupled(new TLBundleA(edge.bundle)) val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle))) val replay_next = Output(Bool()) val store_pending = Output(Bool()) }) def beatOffset(addr: UInt) = addr.extract(beatOffBits - 1, wordOffBits) def wordFromBeat(addr: UInt, dat: UInt) = { val shift = Cat(beatOffset(addr), 0.U((wordOffBits + log2Up(wordBytes)).W)) (dat >> shift)(wordBits - 1, 0) } val req = Reg(new ShuttleDMemReq) val grant_word = Reg(UInt(wordBits.W)) val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4) val state = RegInit(s_idle) io.req.ready := (state === s_idle) val loadgen = new LoadGen(req.size, req.signed, req.addr, grant_word, false.B, wordBytes) val a_source = id.U val a_address = req.addr val a_size = req.size val a_data = Fill(beatWords, req.data) val get = edge.Get(a_source, a_address, a_size)._2 val put = edge.Put(a_source, a_address, a_size, a_data)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(req.cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array( M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert(state === s_idle \|\| !isAMO(req.cmd)) (0.U).asTypeOf(new TLBundleA(edge.bundle)) } assert(state === s_idle \|\| req.cmd =/= M_XSC) io.mem_access.valid := (state === s_mem_access) io.mem_access.bits := Mux(isAMO(req.cmd), atomics, Mux(isRead(req.cmd), get, put)) io.replay_next := (state === s_mem_ack) \|\| io.resp.valid && !io.resp.ready io.resp.valid := (state === s_resp) io.resp.bits.tag := req.tag io.resp.bits.has_data := isRead(req.cmd) io.resp.bits.data := loadgen.data io.resp.bits.size := req.size io.store_pending := state =/= s_idle && isWrite(req.cmd) when (io.req.fire) { req := io.req.bits state := s_mem_access } when (io.mem_access.fire) { state := s_mem_ack } when (state === s_mem_ack && io.mem_ack.valid) { state := s_resp when (isRead(req.cmd)) { grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data) } } when (io.resp.fire) { state := s_idle } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out }	module IOHandler( // @[IOHandler.scala:13:7] input clock, // @[IOHandler.scala:13:7] input reset, // @[IOHandler.scala:13:7] output io_req_ready, // @[IOHandler.scala:14:14] input io_req_valid, // @[IOHandler.scala:14:14] input [39:0] io_req_bits_addr, // @[IOHandler.scala:14:14] input [6:0] io_req_bits_tag, // @[IOHandler.scala:14:14] input [4:0] io_req_bits_cmd, // @[IOHandler.scala:14:14] input [1:0] io_req_bits_size, // @[IOHandler.scala:14:14] input io_req_bits_signed, // @[IOHandler.scala:14:14] input [63:0] io_req_bits_data, // @[IOHandler.scala:14:14] input [7:0] io_req_bits_mask, // @[IOHandler.scala:14:14] input io_resp_ready, // @[IOHandler.scala:14:14] output io_resp_valid, // @[IOHandler.scala:14:14] output io_resp_bits_has_data, // @[IOHandler.scala:14:14] output [6:0] io_resp_bits_tag, // @[IOHandler.scala:14:14] output [63:0] io_resp_bits_data, // @[IOHandler.scala:14:14] output [1:0] io_resp_bits_size, // @[IOHandler.scala:14:14] input io_mem_access_ready, // @[IOHandler.scala:14:14] output io_mem_access_valid, // @[IOHandler.scala:14:14] output [2:0] io_mem_access_bits_opcode, // @[IOHandler.scala:14:14] output [2:0] io_mem_access_bits_param, // @[IOHandler.scala:14:14] output [3:0] io_mem_access_bits_size, // @[IOHandler.scala:14:14] output [2:0] io_mem_access_bits_source, // @[IOHandler.scala:14:14] output [31:0] io_mem_access_bits_address, // @[IOHandler.scala:14:14] output [7:0] io_mem_access_bits_mask, // @[IOHandler.scala:14:14] output [63:0] io_mem_access_bits_data, // @[IOHandler.scala:14:14] input io_mem_ack_valid, // @[IOHandler.scala:14:14] input [2:0] io_mem_ack_bits_opcode, // @[IOHandler.scala:14:14] input [1:0] io_mem_ack_bits_param, // @[IOHandler.scala:14:14] input [3:0] io_mem_ack_bits_size, // @[IOHandler.scala:14:14] input [2:0] io_mem_ack_bits_source, // @[IOHandler.scala:14:14] input [2:0] io_mem_ack_bits_sink, // @[IOHandler.scala:14:14] input io_mem_ack_bits_denied, // @[IOHandler.scala:14:14] input [63:0] io_mem_ack_bits_data, // @[IOHandler.scala:14:14] input io_mem_ack_bits_corrupt, // @[IOHandler.scala:14:14] output io_replay_next, // @[IOHandler.scala:14:14] output io_store_pending // @[IOHandler.scala:14:14] ); wire io_req_valid_0 = io_req_valid; // @[IOHandler.scala:13:7] wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[IOHandler.scala:13:7] wire [6:0] io_req_bits_tag_0 = io_req_bits_tag; // @[IOHandler.scala:13:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[IOHandler.scala:13:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[IOHandler.scala:13:7] wire io_req_bits_signed_0 = io_req_bits_signed; // @[IOHandler.scala:13:7] wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[IOHandler.scala:13:7] wire [7:0] io_req_bits_mask_0 = io_req_bits_mask; // @[IOHandler.scala:13:7] wire io_resp_ready_0 = io_resp_ready; // @[IOHandler.scala:13:7] wire io_mem_access_ready_0 = io_mem_access_ready; // @[IOHandler.scala:13:7] wire io_mem_ack_valid_0 = io_mem_ack_valid; // @[IOHandler.scala:13:7] wire [2:0] io_mem_ack_bits_opcode_0 = io_mem_ack_bits_opcode; // @[IOHandler.scala:13:7] wire [1:0] io_mem_ack_bits_param_0 = io_mem_ack_bits_param; // @[IOHandler.scala:13:7] wire [3:0] io_mem_ack_bits_size_0 = io_mem_ack_bits_size; // @[IOHandler.scala:13:7] wire [2:0] io_mem_ack_bits_source_0 = io_mem_ack_bits_source; // @[IOHandler.scala:13:7] wire [2:0] io_mem_ack_bits_sink_0 = io_mem_ack_bits_sink; // @[IOHandler.scala:13:7] wire io_mem_ack_bits_denied_0 = io_mem_ack_bits_denied; // @[IOHandler.scala:13:7] wire [63:0] io_mem_ack_bits_data_0 = io_mem_ack_bits_data; // @[IOHandler.scala:13:7] wire io_mem_ack_bits_corrupt_0 = io_mem_ack_bits_corrupt; // @[IOHandler.scala:13:7] wire io_mem_access_bits_corrupt = 1'h0; // @[IOHandler.scala:13:7] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire _put_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _put_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire _atomics_WIRE_corrupt = 1'h0; // @[IOHandler.scala:47:38] wire _atomics_legal_T_46 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_52 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_100 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_106 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_154 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_160 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_208 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_214 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_262 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_268 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_316 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_322 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_370 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_376 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_424 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_430 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_478 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_484 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_T_1_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _atomics_T_3_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _atomics_T_5_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _atomics_T_7_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _atomics_T_9_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _atomics_T_11_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _atomics_T_13_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _atomics_T_15_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire atomics_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_42_corrupt = 1'h0; // @[IOHandler.scala:65:57] wire _io_mem_access_bits_T_43_corrupt = 1'h0; // @[IOHandler.scala:65:28] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire [6:0] grant_word_shift = 7'h0; // @[IOHandler.scala:26:20] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] get_source = 3'h4; // @[Edges.scala:460:17] wire [2:0] put_source = 3'h4; // @[Edges.scala:480:17] wire [2:0] atomics_a_source = 3'h4; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_source = 3'h4; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_source = 3'h4; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_source = 3'h4; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [2:0] atomics_a_4_source = 3'h4; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_source = 3'h4; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_source = 3'h4; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_source = 3'h4; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_source = 3'h4; // @[Edges.scala:517:17] wire [2:0] _io_mem_access_bits_T_42_source = 3'h4; // @[IOHandler.scala:65:57] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[IOHandler.scala:47:38] wire [2:0] _atomics_WIRE_param = 3'h0; // @[IOHandler.scala:47:38] wire [2:0] _atomics_WIRE_source = 3'h0; // @[IOHandler.scala:47:38] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] _io_mem_access_bits_T_42_param = 3'h0; // @[IOHandler.scala:65:57] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_54 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_55 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_56 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_57 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_108 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_109 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_110 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_111 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_162 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_163 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_164 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_165 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_216 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_217 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_270 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_271 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_272 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_273 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_324 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_325 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_326 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_327 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_378 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_379 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_380 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_381 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_432 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_433 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_434 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_435 = 1'h1; // @[Parameters.scala:684:29] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [63:0] get_data = 64'h0; // @[Edges.scala:460:17] wire [63:0] _atomics_WIRE_data = 64'h0; // @[IOHandler.scala:47:38] wire [7:0] _atomics_WIRE_mask = 8'h0; // @[IOHandler.scala:47:38] wire [31:0] _atomics_WIRE_address = 32'h0; // @[IOHandler.scala:47:38] wire [3:0] _atomics_WIRE_size = 4'h0; // @[IOHandler.scala:47:38] wire _io_req_ready_T; // @[IOHandler.scala:35:26] wire _io_resp_valid_T; // @[IOHandler.scala:68:27] wire _io_resp_bits_has_data_T_24; // @[Consts.scala:89:68] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_mem_access_valid_T; // @[IOHandler.scala:64:33] wire [2:0] _io_mem_access_bits_T_43_opcode; // @[IOHandler.scala:65:28] wire [2:0] _io_mem_access_bits_T_43_param; // @[IOHandler.scala:65:28] wire [3:0] _io_mem_access_bits_T_43_size; // @[IOHandler.scala:65:28] wire [2:0] _io_mem_access_bits_T_43_source; // @[IOHandler.scala:65:28] wire [31:0] _io_mem_access_bits_T_43_address; // @[IOHandler.scala:65:28] wire [7:0] _io_mem_access_bits_T_43_mask; // @[IOHandler.scala:65:28] wire [63:0] _io_mem_access_bits_T_43_data; // @[IOHandler.scala:65:28] wire [63:0] _grant_word_T = io_mem_ack_bits_data_0; // @[IOHandler.scala:13:7, :27:10] wire _io_replay_next_T_3; // @[IOHandler.scala:67:43] wire _io_store_pending_T_24; // @[IOHandler.scala:73:40] wire io_req_ready_0; // @[IOHandler.scala:13:7] wire io_resp_bits_has_data_0; // @[IOHandler.scala:13:7] wire [6:0] io_resp_bits_tag_0; // @[IOHandler.scala:13:7] wire [63:0] io_resp_bits_data_0; // @[IOHandler.scala:13:7] wire [1:0] io_resp_bits_size_0; // @[IOHandler.scala:13:7] wire io_resp_valid_0; // @[IOHandler.scala:13:7] wire [2:0] io_mem_access_bits_opcode_0; // @[IOHandler.scala:13:7] wire [2:0] io_mem_access_bits_param_0; // @[IOHandler.scala:13:7] wire [3:0] io_mem_access_bits_size_0; // @[IOHandler.scala:13:7] wire [2:0] io_mem_access_bits_source_0; // @[IOHandler.scala:13:7] wire [31:0] io_mem_access_bits_address_0; // @[IOHandler.scala:13:7] wire [7:0] io_mem_access_bits_mask_0; // @[IOHandler.scala:13:7] wire [63:0] io_mem_access_bits_data_0; // @[IOHandler.scala:13:7] wire io_mem_access_valid_0; // @[IOHandler.scala:13:7] wire io_replay_next_0; // @[IOHandler.scala:13:7] wire io_store_pending_0; // @[IOHandler.scala:13:7] reg [39:0] req_addr; // @[IOHandler.scala:30:16] wire [39:0] _get_legal_T_14 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _put_legal_T_14 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_4 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_58 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_112 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_166 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_220 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_274 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_328 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_382 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_436 = req_addr; // @[IOHandler.scala:30:16] reg [6:0] req_tag; // @[IOHandler.scala:30:16] assign io_resp_bits_tag_0 = req_tag; // @[IOHandler.scala:13:7, :30:16] reg [4:0] req_cmd; // @[IOHandler.scala:30:16] reg [1:0] req_size; // @[IOHandler.scala:30:16] assign io_resp_bits_size_0 = req_size; // @[IOHandler.scala:13:7, :30:16] wire [1:0] size = req_size; // @[IOHandler.scala:30:16] reg req_signed; // @[IOHandler.scala:30:16] reg [63:0] req_data; // @[IOHandler.scala:30:16] wire [63:0] put_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_1_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_2_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_3_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_4_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_5_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_6_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_7_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_8_data = req_data; // @[IOHandler.scala:30:16] reg [7:0] req_mask; // @[IOHandler.scala:30:16] reg [63:0] grant_word; // @[IOHandler.scala:31:23] reg [1:0] state; // @[IOHandler.scala:34:22] assign _io_req_ready_T = ~(\|state); // @[IOHandler.scala:34:22, :35:26] assign io_req_ready_0 = _io_req_ready_T; // @[IOHandler.scala:13:7, :35:26] wire [39:0] _GEN = {req_addr[39:14], req_addr[13:0] ^ 14'h3000}; // @[IOHandler.scala:30:16] wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31] assign _get_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31] assign _put_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_62 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'h9A012000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_0 = {req_addr[39:17], req_addr[16:0] ^ 17'h10000}; // @[IOHandler.scala:30:16] wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_63; // @[Parameters.scala:137:31] assign _put_legal_T_63 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_47; // @[Parameters.scala:137:31] assign _atomics_legal_T_47 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_101; // @[Parameters.scala:137:31] assign _atomics_legal_T_101 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_155; // @[Parameters.scala:137:31] assign _atomics_legal_T_155 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_209; // @[Parameters.scala:137:31] assign _atomics_legal_T_209 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_263; // @[Parameters.scala:137:31] assign _atomics_legal_T_263 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_317; // @[Parameters.scala:137:31] assign _atomics_legal_T_317 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_371; // @[Parameters.scala:137:31] assign _atomics_legal_T_371 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_425; // @[Parameters.scala:137:31] assign _atomics_legal_T_425 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_479; // @[Parameters.scala:137:31] assign _atomics_legal_T_479 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'h98013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {req_addr[39:26], req_addr[25:0] ^ 26'h2000000}; // @[IOHandler.scala:30:16] wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31] assign _get_legal_T_29 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46] wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {req_addr[39:28], req_addr[27:0] ^ 28'h8000000}; // @[IOHandler.scala:30:16] wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31] assign _get_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31] assign _get_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31] assign _put_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31] assign _put_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31] assign _atomics_legal_T_19 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31] assign _atomics_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_73; // @[Parameters.scala:137:31] assign _atomics_legal_T_73 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_78; // @[Parameters.scala:137:31] assign _atomics_legal_T_78 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_127; // @[Parameters.scala:137:31] assign _atomics_legal_T_127 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_132; // @[Parameters.scala:137:31] assign _atomics_legal_T_132 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_181; // @[Parameters.scala:137:31] assign _atomics_legal_T_181 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_186; // @[Parameters.scala:137:31] assign _atomics_legal_T_186 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_235; // @[Parameters.scala:137:31] assign _atomics_legal_T_235 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_240; // @[Parameters.scala:137:31] assign _atomics_legal_T_240 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_289; // @[Parameters.scala:137:31] assign _atomics_legal_T_289 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_294; // @[Parameters.scala:137:31] assign _atomics_legal_T_294 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_343; // @[Parameters.scala:137:31] assign _atomics_legal_T_343 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_348; // @[Parameters.scala:137:31] assign _atomics_legal_T_348 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_397; // @[Parameters.scala:137:31] assign _atomics_legal_T_397 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_402; // @[Parameters.scala:137:31] assign _atomics_legal_T_402 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_451; // @[Parameters.scala:137:31] assign _atomics_legal_T_451 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_456; // @[Parameters.scala:137:31] assign _atomics_legal_T_456 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46] wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46] wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {req_addr[39:29], req_addr[28:0] ^ 29'h10000000}; // @[IOHandler.scala:30:16] wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31] assign _get_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31] assign _put_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_29; // @[Parameters.scala:137:31] assign _atomics_legal_T_29 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_83; // @[Parameters.scala:137:31] assign _atomics_legal_T_83 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_137; // @[Parameters.scala:137:31] assign _atomics_legal_T_137 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_191; // @[Parameters.scala:137:31] assign _atomics_legal_T_191 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_245; // @[Parameters.scala:137:31] assign _atomics_legal_T_245 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_299; // @[Parameters.scala:137:31] assign _atomics_legal_T_299 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_353; // @[Parameters.scala:137:31] assign _atomics_legal_T_353 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_407; // @[Parameters.scala:137:31] assign _atomics_legal_T_407 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_461; // @[Parameters.scala:137:31] assign _atomics_legal_T_461 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46] wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] get_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] put_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_1_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_2_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_3_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_4_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_5_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_6_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_7_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_8_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [39:0] _GEN_4 = {req_addr[39:32], req_addr[31:0] ^ 32'h80000000}; // @[IOHandler.scala:30:16] wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31] assign _get_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31] assign _put_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_34; // @[Parameters.scala:137:31] assign _atomics_legal_T_34 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_88; // @[Parameters.scala:137:31] assign _atomics_legal_T_88 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_142; // @[Parameters.scala:137:31] assign _atomics_legal_T_142 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_196; // @[Parameters.scala:137:31] assign _atomics_legal_T_196 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_250; // @[Parameters.scala:137:31] assign _atomics_legal_T_250 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_304; // @[Parameters.scala:137:31] assign _atomics_legal_T_304 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_358; // @[Parameters.scala:137:31] assign _atomics_legal_T_358 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_412; // @[Parameters.scala:137:31] assign _atomics_legal_T_412 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_466; // @[Parameters.scala:137:31] assign _atomics_legal_T_466 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46] wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_54 = _get_legal_T_18 \| _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_55 = _get_legal_T_54 \| _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_56 = _get_legal_T_55 \| _get_legal_T_33; // @[Parameters.scala:685:42] wire _get_legal_T_57 = _get_legal_T_56 \| _get_legal_T_38; // @[Parameters.scala:685:42] wire _get_legal_T_58 = _get_legal_T_57 \| _get_legal_T_43; // @[Parameters.scala:685:42] wire _get_legal_T_59 = _get_legal_T_58 \| _get_legal_T_48; // @[Parameters.scala:685:42] wire _get_legal_T_60 = _get_legal_T_59 \| _get_legal_T_53; // @[Parameters.scala:685:42] wire _get_legal_T_61 = _get_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_62 \| _get_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [7:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_5 = {2'h0, req_size}; // @[IOHandler.scala:30:16] assign get_size = _GEN_5; // @[Edges.scala:460:17, :463:15] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_5; // @[Edges.scala:463:15, :480:17] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [2:0] _GEN_6 = {1'h0, req_size}; // @[IOHandler.scala:30:16] wire [2:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_6; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_0_1 = &req_size; // @[IOHandler.scala:30:16] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = req_addr[2]; // @[IOHandler.scala:30:16] wire put_a_mask_sub_sub_bit = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_1 = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_2 = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_3 = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_4 = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_5 = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_6 = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_7 = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_8 = req_addr[2]; // @[IOHandler.scala:30:16] wire _io_resp_bits_data_shifted_T = req_addr[2]; // @[IOHandler.scala:30:16] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = req_addr[1]; // @[IOHandler.scala:30:16] wire put_a_mask_sub_bit = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_1 = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_2 = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_3 = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_4 = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_5 = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_6 = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_7 = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_8 = req_addr[1]; // @[IOHandler.scala:30:16] wire _io_resp_bits_data_shifted_T_3 = req_addr[1]; // @[IOHandler.scala:30:16] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = req_addr[0]; // @[IOHandler.scala:30:16] wire put_a_mask_bit = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_1 = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_2 = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_3 = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_4 = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_5 = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_6 = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_7 = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_8 = req_addr[0]; // @[IOHandler.scala:30:16] wire _io_resp_bits_data_shifted_T_6 = req_addr[0]; // @[IOHandler.scala:30:16] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 \| _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 \| _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_69 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_7 = {req_addr[39:21], req_addr[20:0] ^ 21'h100000}; // @[IOHandler.scala:30:16] wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31] assign _atomics_legal_T_9 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_63; // @[Parameters.scala:137:31] assign _atomics_legal_T_63 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_117; // @[Parameters.scala:137:31] assign _atomics_legal_T_117 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_171; // @[Parameters.scala:137:31] assign _atomics_legal_T_171 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_225; // @[Parameters.scala:137:31] assign _atomics_legal_T_225 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_279; // @[Parameters.scala:137:31] assign _atomics_legal_T_279 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_333; // @[Parameters.scala:137:31] assign _atomics_legal_T_333 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_387; // @[Parameters.scala:137:31] assign _atomics_legal_T_387 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_441; // @[Parameters.scala:137:31] assign _atomics_legal_T_441 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_8 = {req_addr[39:26], req_addr[25:0] ^ 26'h2010000}; // @[IOHandler.scala:30:16] wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31] assign _put_legal_T_29 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31] assign _atomics_legal_T_14 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_68; // @[Parameters.scala:137:31] assign _atomics_legal_T_68 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_122; // @[Parameters.scala:137:31] assign _atomics_legal_T_122 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_176; // @[Parameters.scala:137:31] assign _atomics_legal_T_176 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_230; // @[Parameters.scala:137:31] assign _atomics_legal_T_230 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_284; // @[Parameters.scala:137:31] assign _atomics_legal_T_284 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_338; // @[Parameters.scala:137:31] assign _atomics_legal_T_338 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_392; // @[Parameters.scala:137:31] assign _atomics_legal_T_392 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_446; // @[Parameters.scala:137:31] assign _atomics_legal_T_446 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46] wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46] wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46] wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46] wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46] wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_54 = _put_legal_T_18 \| _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_55 = _put_legal_T_54 \| _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_56 = _put_legal_T_55 \| _put_legal_T_33; // @[Parameters.scala:685:42] wire _put_legal_T_57 = _put_legal_T_56 \| _put_legal_T_38; // @[Parameters.scala:685:42] wire _put_legal_T_58 = _put_legal_T_57 \| _put_legal_T_43; // @[Parameters.scala:685:42] wire _put_legal_T_59 = _put_legal_T_58 \| _put_legal_T_48; // @[Parameters.scala:685:42] wire _put_legal_T_60 = _put_legal_T_59 \| _put_legal_T_53; // @[Parameters.scala:685:42] wire _put_legal_T_61 = _put_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [40:0] _put_legal_T_64 = {1'h0, _put_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_65 = _put_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_66 = _put_legal_T_65; // @[Parameters.scala:137:46] wire _put_legal_T_67 = _put_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_70 = _put_legal_T_69 \| _put_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire put_legal = _put_legal_T_70; // @[Parameters.scala:686:26] wire [7:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [7:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_0_1 = &req_size; // @[IOHandler.scala:30:16] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 \| _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 \| _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46] wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46] wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46] wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46] wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46] wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_30 = {1'h0, _atomics_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_31 = _atomics_legal_T_30 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_32 = _atomics_legal_T_31; // @[Parameters.scala:137:46] wire _atomics_legal_T_33 = _atomics_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_35 = {1'h0, _atomics_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_36 = _atomics_legal_T_35 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36; // @[Parameters.scala:137:46] wire _atomics_legal_T_38 = _atomics_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_39 = _atomics_legal_T_8 \| _atomics_legal_T_13; // @[Parameters.scala:685:42] wire _atomics_legal_T_40 = _atomics_legal_T_39 \| _atomics_legal_T_18; // @[Parameters.scala:685:42] wire _atomics_legal_T_41 = _atomics_legal_T_40 \| _atomics_legal_T_23; // @[Parameters.scala:685:42] wire _atomics_legal_T_42 = _atomics_legal_T_41 \| _atomics_legal_T_28; // @[Parameters.scala:685:42] wire _atomics_legal_T_43 = _atomics_legal_T_42 \| _atomics_legal_T_33; // @[Parameters.scala:685:42] wire _atomics_legal_T_44 = _atomics_legal_T_43 \| _atomics_legal_T_38; // @[Parameters.scala:685:42] wire _atomics_legal_T_45 = _atomics_legal_T_44; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_53 = _atomics_legal_T_45; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_48 = {1'h0, _atomics_legal_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_49 = _atomics_legal_T_48 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_50 = _atomics_legal_T_49; // @[Parameters.scala:137:46] wire _atomics_legal_T_51 = _atomics_legal_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal = _atomics_legal_T_53; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_59 = {1'h0, _atomics_legal_T_58}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_60 = _atomics_legal_T_59 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_61 = _atomics_legal_T_60; // @[Parameters.scala:137:46] wire _atomics_legal_T_62 = _atomics_legal_T_61 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_64 = {1'h0, _atomics_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_65 = _atomics_legal_T_64 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65; // @[Parameters.scala:137:46] wire _atomics_legal_T_67 = _atomics_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_69 = {1'h0, _atomics_legal_T_68}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_70 = _atomics_legal_T_69 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70; // @[Parameters.scala:137:46] wire _atomics_legal_T_72 = _atomics_legal_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_74 = {1'h0, _atomics_legal_T_73}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_75 = _atomics_legal_T_74 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75; // @[Parameters.scala:137:46] wire _atomics_legal_T_77 = _atomics_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_79 = {1'h0, _atomics_legal_T_78}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_80 = _atomics_legal_T_79 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:137:46] wire _atomics_legal_T_82 = _atomics_legal_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46] wire _atomics_legal_T_87 = _atomics_legal_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_89 = {1'h0, _atomics_legal_T_88}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_90 = _atomics_legal_T_89 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_91 = _atomics_legal_T_90; // @[Parameters.scala:137:46] wire _atomics_legal_T_92 = _atomics_legal_T_91 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_93 = _atomics_legal_T_62 \| _atomics_legal_T_67; // @[Parameters.scala:685:42] wire _atomics_legal_T_94 = _atomics_legal_T_93 \| _atomics_legal_T_72; // @[Parameters.scala:685:42] wire _atomics_legal_T_95 = _atomics_legal_T_94 \| _atomics_legal_T_77; // @[Parameters.scala:685:42] wire _atomics_legal_T_96 = _atomics_legal_T_95 \| _atomics_legal_T_82; // @[Parameters.scala:685:42] wire _atomics_legal_T_97 = _atomics_legal_T_96 \| _atomics_legal_T_87; // @[Parameters.scala:685:42] wire _atomics_legal_T_98 = _atomics_legal_T_97 \| _atomics_legal_T_92; // @[Parameters.scala:685:42] wire _atomics_legal_T_99 = _atomics_legal_T_98; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_107 = _atomics_legal_T_99; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_102 = {1'h0, _atomics_legal_T_101}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_103 = _atomics_legal_T_102 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_104 = _atomics_legal_T_103; // @[Parameters.scala:137:46] wire _atomics_legal_T_105 = _atomics_legal_T_104 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_1 = _atomics_legal_T_107; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [7:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_1 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size_1 & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size_1 & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size_1 & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size_1 & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size_1 & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size_1 & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size_1 & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size_1 & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_113 = {1'h0, _atomics_legal_T_112}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_114 = _atomics_legal_T_113 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:137:46] wire _atomics_legal_T_116 = _atomics_legal_T_115 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_118 = {1'h0, _atomics_legal_T_117}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_119 = _atomics_legal_T_118 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_120 = _atomics_legal_T_119; // @[Parameters.scala:137:46] wire _atomics_legal_T_121 = _atomics_legal_T_120 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46] wire _atomics_legal_T_126 = _atomics_legal_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_128 = {1'h0, _atomics_legal_T_127}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_129 = _atomics_legal_T_128 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_130 = _atomics_legal_T_129; // @[Parameters.scala:137:46] wire _atomics_legal_T_131 = _atomics_legal_T_130 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_133 = {1'h0, _atomics_legal_T_132}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_134 = _atomics_legal_T_133 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_135 = _atomics_legal_T_134; // @[Parameters.scala:137:46] wire _atomics_legal_T_136 = _atomics_legal_T_135 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_138 = {1'h0, _atomics_legal_T_137}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_139 = _atomics_legal_T_138 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_140 = _atomics_legal_T_139; // @[Parameters.scala:137:46] wire _atomics_legal_T_141 = _atomics_legal_T_140 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_143 = {1'h0, _atomics_legal_T_142}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_144 = _atomics_legal_T_143 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_145 = _atomics_legal_T_144; // @[Parameters.scala:137:46] wire _atomics_legal_T_146 = _atomics_legal_T_145 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_147 = _atomics_legal_T_116 \| _atomics_legal_T_121; // @[Parameters.scala:685:42] wire _atomics_legal_T_148 = _atomics_legal_T_147 \| _atomics_legal_T_126; // @[Parameters.scala:685:42] wire _atomics_legal_T_149 = _atomics_legal_T_148 \| _atomics_legal_T_131; // @[Parameters.scala:685:42] wire _atomics_legal_T_150 = _atomics_legal_T_149 \| _atomics_legal_T_136; // @[Parameters.scala:685:42] wire _atomics_legal_T_151 = _atomics_legal_T_150 \| _atomics_legal_T_141; // @[Parameters.scala:685:42] wire _atomics_legal_T_152 = _atomics_legal_T_151 \| _atomics_legal_T_146; // @[Parameters.scala:685:42] wire _atomics_legal_T_153 = _atomics_legal_T_152; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_161 = _atomics_legal_T_153; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_156 = {1'h0, _atomics_legal_T_155}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_157 = _atomics_legal_T_156 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_158 = _atomics_legal_T_157; // @[Parameters.scala:137:46] wire _atomics_legal_T_159 = _atomics_legal_T_158 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_2 = _atomics_legal_T_161; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [7:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_2 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_2 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_2 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_2 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_2 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_2 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_2 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_2 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_2 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_167 = {1'h0, _atomics_legal_T_166}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_168 = _atomics_legal_T_167 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_169 = _atomics_legal_T_168; // @[Parameters.scala:137:46] wire _atomics_legal_T_170 = _atomics_legal_T_169 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_172 = {1'h0, _atomics_legal_T_171}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_173 = _atomics_legal_T_172 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_174 = _atomics_legal_T_173; // @[Parameters.scala:137:46] wire _atomics_legal_T_175 = _atomics_legal_T_174 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_177 = {1'h0, _atomics_legal_T_176}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_178 = _atomics_legal_T_177 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_179 = _atomics_legal_T_178; // @[Parameters.scala:137:46] wire _atomics_legal_T_180 = _atomics_legal_T_179 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_182 = {1'h0, _atomics_legal_T_181}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_183 = _atomics_legal_T_182 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_184 = _atomics_legal_T_183; // @[Parameters.scala:137:46] wire _atomics_legal_T_185 = _atomics_legal_T_184 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_187 = {1'h0, _atomics_legal_T_186}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_188 = _atomics_legal_T_187 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_189 = _atomics_legal_T_188; // @[Parameters.scala:137:46] wire _atomics_legal_T_190 = _atomics_legal_T_189 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_192 = {1'h0, _atomics_legal_T_191}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_193 = _atomics_legal_T_192 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_194 = _atomics_legal_T_193; // @[Parameters.scala:137:46] wire _atomics_legal_T_195 = _atomics_legal_T_194 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_197 = {1'h0, _atomics_legal_T_196}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_198 = _atomics_legal_T_197 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_199 = _atomics_legal_T_198; // @[Parameters.scala:137:46] wire _atomics_legal_T_200 = _atomics_legal_T_199 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_201 = _atomics_legal_T_170 \| _atomics_legal_T_175; // @[Parameters.scala:685:42] wire _atomics_legal_T_202 = _atomics_legal_T_201 \| _atomics_legal_T_180; // @[Parameters.scala:685:42] wire _atomics_legal_T_203 = _atomics_legal_T_202 \| _atomics_legal_T_185; // @[Parameters.scala:685:42] wire _atomics_legal_T_204 = _atomics_legal_T_203 \| _atomics_legal_T_190; // @[Parameters.scala:685:42] wire _atomics_legal_T_205 = _atomics_legal_T_204 \| _atomics_legal_T_195; // @[Parameters.scala:685:42] wire _atomics_legal_T_206 = _atomics_legal_T_205 \| _atomics_legal_T_200; // @[Parameters.scala:685:42] wire _atomics_legal_T_207 = _atomics_legal_T_206; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_215 = _atomics_legal_T_207; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_210 = {1'h0, _atomics_legal_T_209}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_211 = _atomics_legal_T_210 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_212 = _atomics_legal_T_211; // @[Parameters.scala:137:46] wire _atomics_legal_T_213 = _atomics_legal_T_212 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_3 = _atomics_legal_T_215; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [7:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_3 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_3 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_3 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_3 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_3 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_3 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_3 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_3 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_3 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_221 = {1'h0, _atomics_legal_T_220}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_222 = _atomics_legal_T_221 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_223 = _atomics_legal_T_222; // @[Parameters.scala:137:46] wire _atomics_legal_T_224 = _atomics_legal_T_223 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_226 = {1'h0, _atomics_legal_T_225}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_227 = _atomics_legal_T_226 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_228 = _atomics_legal_T_227; // @[Parameters.scala:137:46] wire _atomics_legal_T_229 = _atomics_legal_T_228 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_231 = {1'h0, _atomics_legal_T_230}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_232 = _atomics_legal_T_231 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:137:46] wire _atomics_legal_T_234 = _atomics_legal_T_233 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_236 = {1'h0, _atomics_legal_T_235}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_237 = _atomics_legal_T_236 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_238 = _atomics_legal_T_237; // @[Parameters.scala:137:46] wire _atomics_legal_T_239 = _atomics_legal_T_238 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_241 = {1'h0, _atomics_legal_T_240}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_242 = _atomics_legal_T_241 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_243 = _atomics_legal_T_242; // @[Parameters.scala:137:46] wire _atomics_legal_T_244 = _atomics_legal_T_243 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_246 = {1'h0, _atomics_legal_T_245}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_248 = _atomics_legal_T_247; // @[Parameters.scala:137:46] wire _atomics_legal_T_249 = _atomics_legal_T_248 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_251 = {1'h0, _atomics_legal_T_250}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_253 = _atomics_legal_T_252; // @[Parameters.scala:137:46] wire _atomics_legal_T_254 = _atomics_legal_T_253 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_255 = _atomics_legal_T_224 \| _atomics_legal_T_229; // @[Parameters.scala:685:42] wire _atomics_legal_T_256 = _atomics_legal_T_255 \| _atomics_legal_T_234; // @[Parameters.scala:685:42] wire _atomics_legal_T_257 = _atomics_legal_T_256 \| _atomics_legal_T_239; // @[Parameters.scala:685:42] wire _atomics_legal_T_258 = _atomics_legal_T_257 \| _atomics_legal_T_244; // @[Parameters.scala:685:42] wire _atomics_legal_T_259 = _atomics_legal_T_258 \| _atomics_legal_T_249; // @[Parameters.scala:685:42] wire _atomics_legal_T_260 = _atomics_legal_T_259 \| _atomics_legal_T_254; // @[Parameters.scala:685:42] wire _atomics_legal_T_261 = _atomics_legal_T_260; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_269 = _atomics_legal_T_261; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_264 = {1'h0, _atomics_legal_T_263}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_265 = _atomics_legal_T_264 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_266 = _atomics_legal_T_265; // @[Parameters.scala:137:46] wire _atomics_legal_T_267 = _atomics_legal_T_266 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_4 = _atomics_legal_T_269; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [7:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_4 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_4 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_4 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_4 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_4 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_4 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_4 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_4 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_4 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_275 = {1'h0, _atomics_legal_T_274}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_276 = _atomics_legal_T_275 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_277 = _atomics_legal_T_276; // @[Parameters.scala:137:46] wire _atomics_legal_T_278 = _atomics_legal_T_277 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_280 = {1'h0, _atomics_legal_T_279}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_281 = _atomics_legal_T_280 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_282 = _atomics_legal_T_281; // @[Parameters.scala:137:46] wire _atomics_legal_T_283 = _atomics_legal_T_282 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_285 = {1'h0, _atomics_legal_T_284}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_286 = _atomics_legal_T_285 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_287 = _atomics_legal_T_286; // @[Parameters.scala:137:46] wire _atomics_legal_T_288 = _atomics_legal_T_287 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_290 = {1'h0, _atomics_legal_T_289}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_291 = _atomics_legal_T_290 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_292 = _atomics_legal_T_291; // @[Parameters.scala:137:46] wire _atomics_legal_T_293 = _atomics_legal_T_292 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_295 = {1'h0, _atomics_legal_T_294}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_296 = _atomics_legal_T_295 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_297 = _atomics_legal_T_296; // @[Parameters.scala:137:46] wire _atomics_legal_T_298 = _atomics_legal_T_297 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_300 = {1'h0, _atomics_legal_T_299}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_301 = _atomics_legal_T_300 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_302 = _atomics_legal_T_301; // @[Parameters.scala:137:46] wire _atomics_legal_T_303 = _atomics_legal_T_302 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46] wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_309 = _atomics_legal_T_278 \| _atomics_legal_T_283; // @[Parameters.scala:685:42] wire _atomics_legal_T_310 = _atomics_legal_T_309 \| _atomics_legal_T_288; // @[Parameters.scala:685:42] wire _atomics_legal_T_311 = _atomics_legal_T_310 \| _atomics_legal_T_293; // @[Parameters.scala:685:42] wire _atomics_legal_T_312 = _atomics_legal_T_311 \| _atomics_legal_T_298; // @[Parameters.scala:685:42] wire _atomics_legal_T_313 = _atomics_legal_T_312 \| _atomics_legal_T_303; // @[Parameters.scala:685:42] wire _atomics_legal_T_314 = _atomics_legal_T_313 \| _atomics_legal_T_308; // @[Parameters.scala:685:42] wire _atomics_legal_T_315 = _atomics_legal_T_314; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_323 = _atomics_legal_T_315; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_318 = {1'h0, _atomics_legal_T_317}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_319 = _atomics_legal_T_318 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_320 = _atomics_legal_T_319; // @[Parameters.scala:137:46] wire _atomics_legal_T_321 = _atomics_legal_T_320 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_5 = _atomics_legal_T_323; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [7:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_5 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_5 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_5 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_5 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_5 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_5 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_5 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_5 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_5 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_329 = {1'h0, _atomics_legal_T_328}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_330 = _atomics_legal_T_329 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_331 = _atomics_legal_T_330; // @[Parameters.scala:137:46] wire _atomics_legal_T_332 = _atomics_legal_T_331 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_334 = {1'h0, _atomics_legal_T_333}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_335 = _atomics_legal_T_334 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_336 = _atomics_legal_T_335; // @[Parameters.scala:137:46] wire _atomics_legal_T_337 = _atomics_legal_T_336 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_339 = {1'h0, _atomics_legal_T_338}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_340 = _atomics_legal_T_339 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_341 = _atomics_legal_T_340; // @[Parameters.scala:137:46] wire _atomics_legal_T_342 = _atomics_legal_T_341 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_344 = {1'h0, _atomics_legal_T_343}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_345 = _atomics_legal_T_344 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_346 = _atomics_legal_T_345; // @[Parameters.scala:137:46] wire _atomics_legal_T_347 = _atomics_legal_T_346 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_349 = {1'h0, _atomics_legal_T_348}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_350 = _atomics_legal_T_349 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:137:46] wire _atomics_legal_T_352 = _atomics_legal_T_351 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_354 = {1'h0, _atomics_legal_T_353}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_355 = _atomics_legal_T_354 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_356 = _atomics_legal_T_355; // @[Parameters.scala:137:46] wire _atomics_legal_T_357 = _atomics_legal_T_356 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_359 = {1'h0, _atomics_legal_T_358}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_360 = _atomics_legal_T_359 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_361 = _atomics_legal_T_360; // @[Parameters.scala:137:46] wire _atomics_legal_T_362 = _atomics_legal_T_361 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_363 = _atomics_legal_T_332 \| _atomics_legal_T_337; // @[Parameters.scala:685:42] wire _atomics_legal_T_364 = _atomics_legal_T_363 \| _atomics_legal_T_342; // @[Parameters.scala:685:42] wire _atomics_legal_T_365 = _atomics_legal_T_364 \| _atomics_legal_T_347; // @[Parameters.scala:685:42] wire _atomics_legal_T_366 = _atomics_legal_T_365 \| _atomics_legal_T_352; // @[Parameters.scala:685:42] wire _atomics_legal_T_367 = _atomics_legal_T_366 \| _atomics_legal_T_357; // @[Parameters.scala:685:42] wire _atomics_legal_T_368 = _atomics_legal_T_367 \| _atomics_legal_T_362; // @[Parameters.scala:685:42] wire _atomics_legal_T_369 = _atomics_legal_T_368; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_377 = _atomics_legal_T_369; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_372 = {1'h0, _atomics_legal_T_371}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_373 = _atomics_legal_T_372 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_374 = _atomics_legal_T_373; // @[Parameters.scala:137:46] wire _atomics_legal_T_375 = _atomics_legal_T_374 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_6 = _atomics_legal_T_377; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [7:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_6 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_6 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_6 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_6 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_6 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_6 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_6 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_6 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_6 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_383 = {1'h0, _atomics_legal_T_382}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_384 = _atomics_legal_T_383 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_385 = _atomics_legal_T_384; // @[Parameters.scala:137:46] wire _atomics_legal_T_386 = _atomics_legal_T_385 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_388 = {1'h0, _atomics_legal_T_387}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_389 = _atomics_legal_T_388 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_390 = _atomics_legal_T_389; // @[Parameters.scala:137:46] wire _atomics_legal_T_391 = _atomics_legal_T_390 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_393 = {1'h0, _atomics_legal_T_392}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_394 = _atomics_legal_T_393 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_395 = _atomics_legal_T_394; // @[Parameters.scala:137:46] wire _atomics_legal_T_396 = _atomics_legal_T_395 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_398 = {1'h0, _atomics_legal_T_397}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_399 = _atomics_legal_T_398 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_400 = _atomics_legal_T_399; // @[Parameters.scala:137:46] wire _atomics_legal_T_401 = _atomics_legal_T_400 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_403 = {1'h0, _atomics_legal_T_402}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_404 = _atomics_legal_T_403 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_405 = _atomics_legal_T_404; // @[Parameters.scala:137:46] wire _atomics_legal_T_406 = _atomics_legal_T_405 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_408 = {1'h0, _atomics_legal_T_407}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_409 = _atomics_legal_T_408 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_410 = _atomics_legal_T_409; // @[Parameters.scala:137:46] wire _atomics_legal_T_411 = _atomics_legal_T_410 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_413 = {1'h0, _atomics_legal_T_412}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_414 = _atomics_legal_T_413 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_415 = _atomics_legal_T_414; // @[Parameters.scala:137:46] wire _atomics_legal_T_416 = _atomics_legal_T_415 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_417 = _atomics_legal_T_386 \| _atomics_legal_T_391; // @[Parameters.scala:685:42] wire _atomics_legal_T_418 = _atomics_legal_T_417 \| _atomics_legal_T_396; // @[Parameters.scala:685:42] wire _atomics_legal_T_419 = _atomics_legal_T_418 \| _atomics_legal_T_401; // @[Parameters.scala:685:42] wire _atomics_legal_T_420 = _atomics_legal_T_419 \| _atomics_legal_T_406; // @[Parameters.scala:685:42] wire _atomics_legal_T_421 = _atomics_legal_T_420 \| _atomics_legal_T_411; // @[Parameters.scala:685:42] wire _atomics_legal_T_422 = _atomics_legal_T_421 \| _atomics_legal_T_416; // @[Parameters.scala:685:42] wire _atomics_legal_T_423 = _atomics_legal_T_422; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_431 = _atomics_legal_T_423; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_426 = {1'h0, _atomics_legal_T_425}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_427 = _atomics_legal_T_426 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_428 = _atomics_legal_T_427; // @[Parameters.scala:137:46] wire _atomics_legal_T_429 = _atomics_legal_T_428 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_7 = _atomics_legal_T_431; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [7:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_7 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_7 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_7 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_7 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_7 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_7 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_7 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_7 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_7 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_437 = {1'h0, _atomics_legal_T_436}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_438 = _atomics_legal_T_437 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_439 = _atomics_legal_T_438; // @[Parameters.scala:137:46] wire _atomics_legal_T_440 = _atomics_legal_T_439 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_442 = {1'h0, _atomics_legal_T_441}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_443 = _atomics_legal_T_442 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_444 = _atomics_legal_T_443; // @[Parameters.scala:137:46] wire _atomics_legal_T_445 = _atomics_legal_T_444 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_447 = {1'h0, _atomics_legal_T_446}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_448 = _atomics_legal_T_447 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_449 = _atomics_legal_T_448; // @[Parameters.scala:137:46] wire _atomics_legal_T_450 = _atomics_legal_T_449 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_452 = {1'h0, _atomics_legal_T_451}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_453 = _atomics_legal_T_452 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_454 = _atomics_legal_T_453; // @[Parameters.scala:137:46] wire _atomics_legal_T_455 = _atomics_legal_T_454 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_457 = {1'h0, _atomics_legal_T_456}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_458 = _atomics_legal_T_457 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_459 = _atomics_legal_T_458; // @[Parameters.scala:137:46] wire _atomics_legal_T_460 = _atomics_legal_T_459 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_462 = {1'h0, _atomics_legal_T_461}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_463 = _atomics_legal_T_462 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_464 = _atomics_legal_T_463; // @[Parameters.scala:137:46] wire _atomics_legal_T_465 = _atomics_legal_T_464 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_467 = {1'h0, _atomics_legal_T_466}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_468 = _atomics_legal_T_467 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_469 = _atomics_legal_T_468; // @[Parameters.scala:137:46] wire _atomics_legal_T_470 = _atomics_legal_T_469 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_471 = _atomics_legal_T_440 \| _atomics_legal_T_445; // @[Parameters.scala:685:42] wire _atomics_legal_T_472 = _atomics_legal_T_471 \| _atomics_legal_T_450; // @[Parameters.scala:685:42] wire _atomics_legal_T_473 = _atomics_legal_T_472 \| _atomics_legal_T_455; // @[Parameters.scala:685:42] wire _atomics_legal_T_474 = _atomics_legal_T_473 \| _atomics_legal_T_460; // @[Parameters.scala:685:42] wire _atomics_legal_T_475 = _atomics_legal_T_474 \| _atomics_legal_T_465; // @[Parameters.scala:685:42] wire _atomics_legal_T_476 = _atomics_legal_T_475 \| _atomics_legal_T_470; // @[Parameters.scala:685:42] wire _atomics_legal_T_477 = _atomics_legal_T_476; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_485 = _atomics_legal_T_477; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_480 = {1'h0, _atomics_legal_T_479}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_481 = _atomics_legal_T_480 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_482 = _atomics_legal_T_481; // @[Parameters.scala:137:46] wire _atomics_legal_T_483 = _atomics_legal_T_482 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_8 = _atomics_legal_T_485; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [7:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_8 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_8 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_8 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_8 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_8 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_8 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_8 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_8 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_8 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire _T_17 = req_cmd == 5'h4; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T; // @[IOHandler.scala:47:67] assign _atomics_T = _T_17; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T; // @[package.scala:16:47] assign _io_mem_access_bits_T = _T_17; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_24; // @[package.scala:16:47] assign _io_mem_access_bits_T_24 = _T_17; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_7; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_7 = _T_17; // @[IOHandler.scala:47:67] wire _io_store_pending_T_6; // @[package.scala:16:47] assign _io_store_pending_T_6 = _T_17; // @[IOHandler.scala:47:67] wire [2:0] _GEN_9 = _atomics_T ? 3'h3 : 3'h0; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_1_opcode; // @[IOHandler.scala:47:67] assign _atomics_T_1_opcode = _GEN_9; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_1_param; // @[IOHandler.scala:47:67] assign _atomics_T_1_param = _GEN_9; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_1_source = {_atomics_T, 2'h0}; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 8'h0; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 64'h0; // @[IOHandler.scala:47:67] wire _T_18 = req_cmd == 5'h9; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_2; // @[IOHandler.scala:47:67] assign _atomics_T_2 = _T_18; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_1; // @[package.scala:16:47] assign _io_mem_access_bits_T_1 = _T_18; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_25; // @[package.scala:16:47] assign _io_mem_access_bits_T_25 = _T_18; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_8; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_8 = _T_18; // @[IOHandler.scala:47:67] wire _io_store_pending_T_7; // @[package.scala:16:47] assign _io_store_pending_T_7 = _T_18; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_3_source = _atomics_T_2 ? 3'h4 : _atomics_T_1_source; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[IOHandler.scala:47:67] wire _T_19 = req_cmd == 5'hA; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_4; // @[IOHandler.scala:47:67] assign _atomics_T_4 = _T_19; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_2; // @[package.scala:16:47] assign _io_mem_access_bits_T_2 = _T_19; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_26; // @[package.scala:16:47] assign _io_mem_access_bits_T_26 = _T_19; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_9; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_9 = _T_19; // @[IOHandler.scala:47:67] wire _io_store_pending_T_8; // @[package.scala:16:47] assign _io_store_pending_T_8 = _T_19; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_5_source = _atomics_T_4 ? 3'h4 : _atomics_T_3_source; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[IOHandler.scala:47:67] wire _T_20 = req_cmd == 5'hB; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_6; // @[IOHandler.scala:47:67] assign _atomics_T_6 = _T_20; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_3; // @[package.scala:16:47] assign _io_mem_access_bits_T_3 = _T_20; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_27; // @[package.scala:16:47] assign _io_mem_access_bits_T_27 = _T_20; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_10; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_10 = _T_20; // @[IOHandler.scala:47:67] wire _io_store_pending_T_9; // @[package.scala:16:47] assign _io_store_pending_T_9 = _T_20; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_7_source = _atomics_T_6 ? 3'h4 : _atomics_T_5_source; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[IOHandler.scala:47:67] wire _T_24 = req_cmd == 5'h8; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_8; // @[IOHandler.scala:47:67] assign _atomics_T_8 = _T_24; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_7; // @[package.scala:16:47] assign _io_mem_access_bits_T_7 = _T_24; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_31; // @[package.scala:16:47] assign _io_mem_access_bits_T_31 = _T_24; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_14; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_14 = _T_24; // @[IOHandler.scala:47:67] wire _io_store_pending_T_13; // @[package.scala:16:47] assign _io_store_pending_T_13 = _T_24; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_9_source = _atomics_T_8 ? 3'h4 : _atomics_T_7_source; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[IOHandler.scala:47:67] wire _T_25 = req_cmd == 5'hC; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_10; // @[IOHandler.scala:47:67] assign _atomics_T_10 = _T_25; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_8; // @[package.scala:16:47] assign _io_mem_access_bits_T_8 = _T_25; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_32; // @[package.scala:16:47] assign _io_mem_access_bits_T_32 = _T_25; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_15; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_15 = _T_25; // @[IOHandler.scala:47:67] wire _io_store_pending_T_14; // @[package.scala:16:47] assign _io_store_pending_T_14 = _T_25; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_11_source = _atomics_T_10 ? 3'h4 : _atomics_T_9_source; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[IOHandler.scala:47:67] wire _T_26 = req_cmd == 5'hD; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_12; // @[IOHandler.scala:47:67] assign _atomics_T_12 = _T_26; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_9; // @[package.scala:16:47] assign _io_mem_access_bits_T_9 = _T_26; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_33; // @[package.scala:16:47] assign _io_mem_access_bits_T_33 = _T_26; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_16; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_16 = _T_26; // @[IOHandler.scala:47:67] wire _io_store_pending_T_15; // @[package.scala:16:47] assign _io_store_pending_T_15 = _T_26; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_13_source = _atomics_T_12 ? 3'h4 : _atomics_T_11_source; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[IOHandler.scala:47:67] wire _T_27 = req_cmd == 5'hE; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_14; // @[IOHandler.scala:47:67] assign _atomics_T_14 = _T_27; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_10; // @[package.scala:16:47] assign _io_mem_access_bits_T_10 = _T_27; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_34; // @[package.scala:16:47] assign _io_mem_access_bits_T_34 = _T_27; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_17; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_17 = _T_27; // @[IOHandler.scala:47:67] wire _io_store_pending_T_16; // @[package.scala:16:47] assign _io_store_pending_T_16 = _T_27; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_15_source = _atomics_T_14 ? 3'h4 : _atomics_T_13_source; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[IOHandler.scala:47:67] wire _T_28 = req_cmd == 5'hF; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_16; // @[IOHandler.scala:47:67] assign _atomics_T_16 = _T_28; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_11; // @[package.scala:16:47] assign _io_mem_access_bits_T_11 = _T_28; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_35; // @[package.scala:16:47] assign _io_mem_access_bits_T_35 = _T_28; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_18; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_18 = _T_28; // @[IOHandler.scala:47:67] wire _io_store_pending_T_17; // @[package.scala:16:47] assign _io_store_pending_T_17 = _T_28; // @[IOHandler.scala:47:67] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[IOHandler.scala:47:67] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[IOHandler.scala:47:67] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[IOHandler.scala:47:67] wire [2:0] atomics_source = _atomics_T_16 ? 3'h4 : _atomics_T_15_source; // @[IOHandler.scala:47:67] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[IOHandler.scala:47:67] wire [7:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[IOHandler.scala:47:67] wire [63:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[IOHandler.scala:47:67]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_115( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_203 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_337( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_81 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire \|\| io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) \|\| !io.outCol.fire) assert(!(state === 1.U) \|\| !io.inRow.fire) }	module PE_204( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File alu.scala: // This is borrowed from rocket, and modified to be hardcoded to 32b. // I will leave it as an excercise to the reader to make a parameterizable ALU // that doesn't generate extra hardware for 32b. I also didn't carefully // consider the function encodings. - Chris package sodor.stage3 import chisel3._ import chisel3.util._ import sodor.common._ import sodor.stage3.Constants._ object ALU { // TODO is this the optimal encoding? val SZ_ALU_FN = 4 val ALU_X = 0.U // TODO use a more optimal decode table, which uses "???" format val ALU_ADD = 0.U val ALU_SLL = 1.U val ALU_XOR = 4.U val ALU_OR = 6.U val ALU_AND = 7.U val ALU_SRL = 5.U val ALU_SUB = 10.U val ALU_SRA = 11.U val ALU_SLT = 12.U val ALU_SLTU = 14.U val ALU_COPY1= 8.U def isSub(cmd: UInt) = cmd(3) def isSLTU(cmd: UInt) = cmd(1) } import ALU._ class ALUIO(implicit val conf: SodorCoreParams) extends Bundle { val fn = Input(UInt(SZ_ALU_FN.W)) val in2 = Input(UInt(conf.xprlen.W)) val in1 = Input(UInt(conf.xprlen.W)) val out = Output(UInt(conf.xprlen.W)) val adder_out = Output(UInt(conf.xprlen.W)) } class ALU(implicit val conf: SodorCoreParams) extends Module { val io = IO(new ALUIO) val msb = conf.xprlen-1 // ADD, SUB val sum = io.in1 + Mux(isSub(io.fn), -io.in2, io.in2) // SLT, SLTU val less = Mux(io.in1(msb) === io.in2(msb), sum(msb), Mux(isSLTU(io.fn), io.in2(msb), io.in1(msb))) require(conf.xprlen == 32) // SLL, SRL, SRA val shamt = io.in2(4,0).asUInt val shin_r = io.in1(31,0) val shin = Mux(io.fn === ALU_SRL \|\| io.fn === ALU_SRA, shin_r, Reverse(shin_r)) val shout_r = (Cat(isSub(io.fn) & shin(msb), shin).asSInt >> shamt)(msb,0) val shout_l = Reverse(shout_r) val bitwise_logic = Mux(io.fn === ALU_AND, io.in1 & io.in2, Mux(io.fn === ALU_OR, io.in1 \| io.in2, Mux(io.fn === ALU_XOR, io.in1 ^ io.in2, io.in1))) // ALU_COPY1 val out_xpr_length = Mux(io.fn === ALU_ADD \|\| io.fn === ALU_SUB, sum, Mux(io.fn === ALU_SLT \|\| io.fn === ALU_SLTU, less, Mux(io.fn === ALU_SRL \|\| io.fn === ALU_SRA, shout_r, Mux(io.fn === ALU_SLL, shout_l, bitwise_logic)))) io.out := out_xpr_length(31,0).asUInt io.adder_out := sum }	module ALU( // @[alu.scala:43:7] input clock, // @[alu.scala:43:7] input reset, // @[alu.scala:43:7] input [3:0] io_fn, // @[alu.scala:45:14] input [31:0] io_in2, // @[alu.scala:45:14] input [31:0] io_in1, // @[alu.scala:45:14] output [31:0] io_out, // @[alu.scala:45:14] output [31:0] io_adder_out // @[alu.scala:45:14] ); wire [3:0] io_fn_0 = io_fn; // @[alu.scala:43:7] wire [31:0] io_in2_0 = io_in2; // @[alu.scala:43:7] wire [31:0] io_in1_0 = io_in1; // @[alu.scala:43:7] wire [31:0] _shin_T_4 = 32'hFFFF; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_1 = 32'hFFFF; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_3 = 32'hFFFF0000; // @[alu.scala:60:74] wire [31:0] _shin_T_9 = 32'hFFFF0000; // @[alu.scala:60:74] wire [31:0] _shout_l_T = 32'hFFFF0000; // @[alu.scala:62:24] wire [31:0] _shout_l_T_6 = 32'hFFFF0000; // @[alu.scala:62:24] wire [23:0] _shin_T_12 = 24'hFFFF; // @[alu.scala:60:74, :62:24] wire [23:0] _shout_l_T_9 = 24'hFFFF; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_13 = 32'hFFFF00; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_10 = 32'hFFFF00; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_14 = 32'hFF00FF; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_11 = 32'hFF00FF; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_19 = 32'hFF00FF00; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_16 = 32'hFF00FF00; // @[alu.scala:60:74, :62:24] wire [27:0] _shin_T_22 = 28'hFF00FF; // @[alu.scala:60:74, :62:24] wire [27:0] _shout_l_T_19 = 28'hFF00FF; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_23 = 32'hFF00FF0; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_20 = 32'hFF00FF0; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_24 = 32'hF0F0F0F; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_21 = 32'hF0F0F0F; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_29 = 32'hF0F0F0F0; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_26 = 32'hF0F0F0F0; // @[alu.scala:60:74, :62:24] wire [29:0] _shin_T_32 = 30'hF0F0F0F; // @[alu.scala:60:74, :62:24] wire [29:0] _shout_l_T_29 = 30'hF0F0F0F; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_33 = 32'h3C3C3C3C; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_30 = 32'h3C3C3C3C; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_34 = 32'h33333333; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_31 = 32'h33333333; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_39 = 32'hCCCCCCCC; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_36 = 32'hCCCCCCCC; // @[alu.scala:60:74, :62:24] wire [30:0] _shin_T_42 = 31'h33333333; // @[alu.scala:60:74, :62:24] wire [30:0] _shout_l_T_39 = 31'h33333333; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_43 = 32'h66666666; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_40 = 32'h66666666; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_44 = 32'h55555555; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_41 = 32'h55555555; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_49 = 32'hAAAAAAAA; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_46 = 32'hAAAAAAAA; // @[alu.scala:60:74, :62:24] wire [31:0] shin_r = io_in1_0; // @[alu.scala:43:7, :59:22] wire [31:0] _io_out_T; // @[alu.scala:77:27] wire [31:0] sum; // @[alu.scala:50:20] wire [31:0] io_out_0; // @[alu.scala:43:7] wire [31:0] io_adder_out_0; // @[alu.scala:43:7] wire _sum_T = io_fn_0[3]; // @[alu.scala:30:29, :43:7] wire _shout_r_T = io_fn_0[3]; // @[alu.scala:30:29, :43:7] wire [32:0] _sum_T_1 = 33'h0 - {1'h0, io_in2_0}; // @[alu.scala:43:7, :50:40] wire [31:0] _sum_T_2 = _sum_T_1[31:0]; // @[alu.scala:50:40] wire [31:0] _sum_T_3 = _sum_T ? _sum_T_2 : io_in2_0; // @[alu.scala:30:29, :43:7, :50:{25,40}] wire [32:0] _sum_T_4 = {1'h0, io_in1_0} + {1'h0, _sum_T_3}; // @[alu.scala:43:7, :50:{20,25,40}] assign sum = _sum_T_4[31:0]; // @[alu.scala:50:20] assign io_adder_out_0 = sum; // @[alu.scala:43:7, :50:20] wire _less_T = io_in1_0[31]; // @[alu.scala:43:7, :53:26] wire _less_T_6 = io_in1_0[31]; // @[alu.scala:43:7, :53:26, :54:53] wire _less_T_1 = io_in2_0[31]; // @[alu.scala:43:7, :53:42] wire _less_T_5 = io_in2_0[31]; // @[alu.scala:43:7, :53:42, :54:40] wire _less_T_2 = _less_T == _less_T_1; // @[alu.scala:53:{26,32,42}] wire _less_T_3 = sum[31]; // @[alu.scala:50:20, :53:52] wire _less_T_4 = io_fn_0[1]; // @[alu.scala:31:30, :43:7] wire _less_T_7 = _less_T_4 ? _less_T_5 : _less_T_6; // @[alu.scala:31:30, :54:{18,40,53}] wire less = _less_T_2 ? _less_T_3 : _less_T_7; // @[alu.scala:53:{19,32,52}, :54:18] wire [4:0] shamt = io_in2_0[4:0]; // @[alu.scala:43:7, :58:21] wire _GEN = io_fn_0 == 4'h5; // @[alu.scala:43:7, :60:24] wire _shin_T; // @[alu.scala:60:24] assign _shin_T = _GEN; // @[alu.scala:60:24] wire _out_xpr_length_T_6; // @[alu.scala:73:15] assign _out_xpr_length_T_6 = _GEN; // @[alu.scala:60:24, :73:15] wire _GEN_0 = io_fn_0 == 4'hB; // @[alu.scala:43:7, :60:46] wire _shin_T_1; // @[alu.scala:60:46] assign _shin_T_1 = _GEN_0; // @[alu.scala:60:46] wire _out_xpr_length_T_7; // @[alu.scala:73:36] assign _out_xpr_length_T_7 = _GEN_0; // @[alu.scala:60:46, :73:36] wire _shin_T_2 = _shin_T \| _shin_T_1; // @[alu.scala:60:{24,37,46}] wire [15:0] _shin_T_5 = shin_r[31:16]; // @[alu.scala:59:22, :60:74] wire [31:0] _shin_T_6 = {16'h0, _shin_T_5}; // @[alu.scala:60:74] wire [15:0] _shin_T_7 = shin_r[15:0]; // @[alu.scala:59:22, :60:74] wire [31:0] _shin_T_8 = {_shin_T_7, 16'h0}; // @[alu.scala:60:74] wire [31:0] _shin_T_10 = _shin_T_8 & 32'hFFFF0000; // @[alu.scala:60:74] wire [31:0] _shin_T_11 = _shin_T_6 \| _shin_T_10; // @[alu.scala:60:74] wire [23:0] _shin_T_15 = _shin_T_11[31:8]; // @[alu.scala:60:74] wire [31:0] _shin_T_16 = {8'h0, _shin_T_15 & 24'hFF00FF}; // @[alu.scala:60:74, :62:24] wire [23:0] _shin_T_17 = _shin_T_11[23:0]; // @[alu.scala:60:74] wire [31:0] _shin_T_18 = {_shin_T_17, 8'h0}; // @[alu.scala:60:74] wire [31:0] _shin_T_20 = _shin_T_18 & 32'hFF00FF00; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_21 = _shin_T_16 \| _shin_T_20; // @[alu.scala:60:74] wire [27:0] _shin_T_25 = _shin_T_21[31:4]; // @[alu.scala:60:74] wire [31:0] _shin_T_26 = {4'h0, _shin_T_25 & 28'hF0F0F0F}; // @[alu.scala:60:74, :62:24] wire [27:0] _shin_T_27 = _shin_T_21[27:0]; // @[alu.scala:60:74] wire [31:0] _shin_T_28 = {_shin_T_27, 4'h0}; // @[alu.scala:60:74] wire [31:0] _shin_T_30 = _shin_T_28 & 32'hF0F0F0F0; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_31 = _shin_T_26 \| _shin_T_30; // @[alu.scala:60:74] wire [29:0] _shin_T_35 = _shin_T_31[31:2]; // @[alu.scala:60:74] wire [31:0] _shin_T_36 = {2'h0, _shin_T_35 & 30'h33333333}; // @[alu.scala:60:74, :62:24] wire [29:0] _shin_T_37 = _shin_T_31[29:0]; // @[alu.scala:60:74] wire [31:0] _shin_T_38 = {_shin_T_37, 2'h0}; // @[alu.scala:60:74] wire [31:0] _shin_T_40 = _shin_T_38 & 32'hCCCCCCCC; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_41 = _shin_T_36 \| _shin_T_40; // @[alu.scala:60:74] wire [30:0] _shin_T_45 = _shin_T_41[31:1]; // @[alu.scala:60:74] wire [31:0] _shin_T_46 = {1'h0, _shin_T_45 & 31'h55555555}; // @[alu.scala:50:40, :60:74, :62:24] wire [30:0] _shin_T_47 = _shin_T_41[30:0]; // @[alu.scala:60:74] wire [31:0] _shin_T_48 = {_shin_T_47, 1'h0}; // @[alu.scala:50:40, :60:74] wire [31:0] _shin_T_50 = _shin_T_48 & 32'hAAAAAAAA; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_51 = _shin_T_46 \| _shin_T_50; // @[alu.scala:60:74] wire [31:0] shin = _shin_T_2 ? shin_r : _shin_T_51; // @[alu.scala:59:22, :60:{17,37,74}] wire _shout_r_T_1 = shin[31]; // @[alu.scala:60:17, :61:41] wire _shout_r_T_2 = _shout_r_T & _shout_r_T_1; // @[alu.scala:30:29, :61:{35,41}] wire [32:0] _shout_r_T_3 = {_shout_r_T_2, shin}; // @[alu.scala:60:17, :61:{21,35}] wire [32:0] _shout_r_T_4 = _shout_r_T_3; // @[alu.scala:61:{21,54}] wire [32:0] _shout_r_T_5 = $signed($signed(_shout_r_T_4) >>> shamt); // @[alu.scala:58:21, :61:{54,61}] wire [31:0] shout_r = _shout_r_T_5[31:0]; // @[alu.scala:61:{61,70}] wire [15:0] _shout_l_T_2 = shout_r[31:16]; // @[alu.scala:61:70, :62:24] wire [31:0] _shout_l_T_3 = {16'h0, _shout_l_T_2}; // @[alu.scala:60:74, :62:24] wire [15:0] _shout_l_T_4 = shout_r[15:0]; // @[alu.scala:61:70, :62:24] wire [31:0] _shout_l_T_5 = {_shout_l_T_4, 16'h0}; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_7 = _shout_l_T_5 & 32'hFFFF0000; // @[alu.scala:62:24] wire [31:0] _shout_l_T_8 = _shout_l_T_3 \| _shout_l_T_7; // @[alu.scala:62:24] wire [23:0] _shout_l_T_12 = _shout_l_T_8[31:8]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_13 = {8'h0, _shout_l_T_12 & 24'hFF00FF}; // @[alu.scala:60:74, :62:24] wire [23:0] _shout_l_T_14 = _shout_l_T_8[23:0]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_15 = {_shout_l_T_14, 8'h0}; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_17 = _shout_l_T_15 & 32'hFF00FF00; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_18 = _shout_l_T_13 \| _shout_l_T_17; // @[alu.scala:62:24] wire [27:0] _shout_l_T_22 = _shout_l_T_18[31:4]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_23 = {4'h0, _shout_l_T_22 & 28'hF0F0F0F}; // @[alu.scala:60:74, :62:24] wire [27:0] _shout_l_T_24 = _shout_l_T_18[27:0]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_25 = {_shout_l_T_24, 4'h0}; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_27 = _shout_l_T_25 & 32'hF0F0F0F0; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_28 = _shout_l_T_23 \| _shout_l_T_27; // @[alu.scala:62:24] wire [29:0] _shout_l_T_32 = _shout_l_T_28[31:2]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_33 = {2'h0, _shout_l_T_32 & 30'h33333333}; // @[alu.scala:60:74, :62:24] wire [29:0] _shout_l_T_34 = _shout_l_T_28[29:0]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_35 = {_shout_l_T_34, 2'h0}; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_37 = _shout_l_T_35 & 32'hCCCCCCCC; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_38 = _shout_l_T_33 \| _shout_l_T_37; // @[alu.scala:62:24] wire [30:0] _shout_l_T_42 = _shout_l_T_38[31:1]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_43 = {1'h0, _shout_l_T_42 & 31'h55555555}; // @[alu.scala:50:40, :60:74, :62:24] wire [30:0] _shout_l_T_44 = _shout_l_T_38[30:0]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_45 = {_shout_l_T_44, 1'h0}; // @[alu.scala:50:40, :62:24] wire [31:0] _shout_l_T_47 = _shout_l_T_45 & 32'hAAAAAAAA; // @[alu.scala:60:74, :62:24] wire [31:0] shout_l = _shout_l_T_43 \| _shout_l_T_47; // @[alu.scala:62:24] wire _bitwise_logic_T = io_fn_0 == 4'h7; // @[alu.scala:43:7, :65:15] wire [31:0] _bitwise_logic_T_1 = io_in1_0 & io_in2_0; // @[alu.scala:43:7, :65:35] wire _bitwise_logic_T_2 = io_fn_0 == 4'h6; // @[alu.scala:43:7, :66:15] wire [31:0] _bitwise_logic_T_3 = io_in1_0 \| io_in2_0; // @[alu.scala:43:7, :66:35] wire _bitwise_logic_T_4 = io_fn_0 == 4'h4; // @[alu.scala:43:7, :67:15] wire [31:0] _bitwise_logic_T_5 = io_in1_0 ^ io_in2_0; // @[alu.scala:43:7, :67:35] wire [31:0] _bitwise_logic_T_6 = _bitwise_logic_T_4 ? _bitwise_logic_T_5 : io_in1_0; // @[alu.scala:43:7, :67:{8,15,35}] wire [31:0] _bitwise_logic_T_7 = _bitwise_logic_T_2 ? _bitwise_logic_T_3 : _bitwise_logic_T_6; // @[alu.scala:66:{8,15,35}, :67:8] wire [31:0] bitwise_logic = _bitwise_logic_T ? _bitwise_logic_T_1 : _bitwise_logic_T_7; // @[alu.scala:65:{8,15,35}, :66:8] wire _out_xpr_length_T = io_fn_0 == 4'h0; // @[alu.scala:43:7, :60:74, :71:15] wire _out_xpr_length_T_1 = io_fn_0 == 4'hA; // @[alu.scala:43:7, :71:36] wire _out_xpr_length_T_2 = _out_xpr_length_T \| _out_xpr_length_T_1; // @[alu.scala:71:{15,27,36}] wire _out_xpr_length_T_3 = io_fn_0 == 4'hC; // @[alu.scala:43:7, :72:15] wire _out_xpr_length_T_4 = io_fn_0 == 4'hE; // @[alu.scala:43:7, :72:36] wire _out_xpr_length_T_5 = _out_xpr_length_T_3 \| _out_xpr_length_T_4; // @[alu.scala:72:{15,27,36}] wire _out_xpr_length_T_8 = _out_xpr_length_T_6 \| _out_xpr_length_T_7; // @[alu.scala:73:{15,27,36}] wire _out_xpr_length_T_9 = io_fn_0 == 4'h1; // @[alu.scala:43:7, :74:15] wire [31:0] _out_xpr_length_T_10 = _out_xpr_length_T_9 ? shout_l : bitwise_logic; // @[alu.scala:62:24, :65:8, :74:{8,15}] wire [31:0] _out_xpr_length_T_11 = _out_xpr_length_T_8 ? shout_r : _out_xpr_length_T_10; // @[alu.scala:61:70, :73:{8,27}, :74:8] wire [31:0] _out_xpr_length_T_12 = _out_xpr_length_T_5 ? {31'h0, less} : _out_xpr_length_T_11; // @[alu.scala:53:19, :72:{8,27}, :73:8] wire [31:0] out_xpr_length = _out_xpr_length_T_2 ? sum : _out_xpr_length_T_12; // @[alu.scala:50:20, :71:{8,27}, :72:8] assign _io_out_T = out_xpr_length; // @[alu.scala:71:8, :77:27] assign io_out_0 = _io_out_T; // @[alu.scala:43:7, :77:27] assign io_out = io_out_0; // @[alu.scala:43:7] assign io_adder_out = io_adder_out_0; // @[alu.scala:43:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File FunctionalUnit.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ import saturn.insns.{VectorInstruction} abstract class FunctionalUnitIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val iss = new Bundle { val valid = Input(Bool()) val op = Input(new ExecuteMicroOp) val ready = Output(Bool()) } val scalar_write = Decoupled(new ScalarWrite) val set_vxsat = Output(Bool()) val set_fflags = Output(Valid(UInt(5.W))) } class PipelinedFunctionalUnitIO(depth: Int)(implicit p: Parameters) extends FunctionalUnitIO { val write = Valid(new VectorWrite(dLen)) val pipe = Input(Vec(depth, Valid(new ExecuteMicroOp))) val pipe0_stall = Output(Bool()) } class IterativeFunctionalUnitIO(implicit p: Parameters) extends FunctionalUnitIO { val write = Decoupled(new VectorWrite(dLen)) val hazard = Output(Valid(new PipeHazard(10))) val acc = Output(Bool()) val tail = Output(Bool()) val busy = Output(Bool()) } trait FunctionalUnitFactory { def insns: Seq[VectorInstruction] def generate(implicit p: Parameters): FunctionalUnit } abstract class FunctionalUnit(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io: FunctionalUnitIO } abstract class PipelinedFunctionalUnit(val depth: Int)(implicit p: Parameters) extends FunctionalUnit()(p) { val io = IO(new PipelinedFunctionalUnitIO(depth)) require (depth > 0) def narrow2_expand(bits: Seq[UInt], eew: UInt, upper: Bool, sext: Bool): Vec[UInt] = { val narrow_eew = (0 until 3).map { eew => Wire(Vec(dLenB >> (eew + 1), UInt((16 << eew).W))) } for (eew <- 0 until 3) { val in_vec = bits.grouped(1 << eew).map(g => VecInit(g).asUInt).toSeq for (i <- 0 until dLenB >> (eew + 1)) { val lo = Mux(upper, in_vec(i + (dLenB >> (eew + 1))), in_vec(i)) val hi = Fill(16 << eew, lo((8 << eew)-1) && sext) narrow_eew(eew)(i) := Cat(hi, lo) } } VecInit(narrow_eew.map(_.asUInt))(eew).asTypeOf(Vec(dLenB, UInt(8.W))) } } abstract class IterativeFunctionalUnit(implicit p: Parameters) extends FunctionalUnit()(p) { val io = IO(new IterativeFunctionalUnitIO) val valid = RegInit(false.B) val op = Reg(new ExecuteMicroOp) val last = Wire(Bool()) io.busy := valid io.hazard.bits.latency := DontCare when (io.iss.valid && io.iss.ready) { valid := true.B op := io.iss.op } .elsewhen (last) { valid := false.B } } File Bundles.scala: package saturn.common import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ class VectorMemMacroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val debug_id = UInt(debugIdSz.W) val base_offset = UInt(pgIdxBits.W) val page = UInt((paddrBits - pgIdxBits).W) val stride = UInt(pgIdxBits.W) val segstart = UInt(3.W) val segend = UInt(3.W) val vstart = UInt(log2Ceil(maxVLMax).W) val vl = UInt((1+log2Ceil(maxVLMax)).W) val mop = UInt(2.W) val vm = Bool() val nf = UInt(3.W) val idx_size = UInt(2.W) val elem_size = UInt(2.W) val whole_reg = Bool() val store = Bool() val fast_sg = Bool() def indexed = !mop.isOneOf(mopUnit, mopStrided) def seg_nf = Mux(whole_reg, 0.U, nf) def wr_nf = Mux(whole_reg, nf, 0.U) } class VectorIssueInst(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val pc = UInt(vaddrBitsExtended.W) val bits = UInt(32.W) val vconfig = new VConfig val vstart = UInt(log2Ceil(maxVLMax).W) val segstart = UInt(3.W) val segend = UInt(3.W) val rs1_data = UInt(xLen.W) val rs2_data = UInt(xLen.W) val page = UInt((paddrBits - pgIdxBits).W) val vat = UInt(vParams.vatSz.W) val rm = UInt(3.W) val emul = UInt(2.W) val fast_sg = Bool() val debug_id = UInt(debugIdSz.W) val mop = UInt(2.W) // stored separately from bits since dispatch may need to set this def opcode = bits(6,0) def store = opcode(5) def mem_idx_size = bits(13,12) def mem_elem_size = Mux(mop(0), vconfig.vtype.vsew, bits(13,12)) def vm = bits(25) def orig_mop = bits(27,26) def umop = bits(24,20) def nf = bits(31,29) def wr = orig_mop === mopUnit && umop === lumopWhole def seg_nf = Mux(wr, 0.U, nf) def wr_nf = Mux(wr, nf, 0.U) def vmu = opcode.isOneOf(opcLoad, opcStore) def rs1 = bits(19,15) def rs2 = bits(24,20) def rd = bits(11,7) def may_write_v0 = rd === 0.U && opcode =/= opcStore def funct3 = bits(14,12) def imm5 = bits(19,15) def imm5_sext = Cat(Fill(59, imm5(4)), imm5) def funct6 = bits(31,26) def writes_xrf = !vmu && ((funct3 === OPMVV && opmf6 === OPMFunct6.wrxunary0) \|\| (funct3 === OPFVV && opff6 === OPFFunct6.wrfunary0)) def writes_frf = !vmu && (funct3 === OPFVV) def isOpi = funct3.isOneOf(OPIVV, OPIVI, OPIVX) def isOpm = funct3.isOneOf(OPMVV, OPMVX) def isOpf = funct3.isOneOf(OPFVV, OPFVF) def opmf6 = Mux(isOpm, OPMFunct6(funct6), OPMFunct6.illegal) def opif6 = Mux(isOpi, OPIFunct6(funct6), OPIFunct6.illegal) def opff6 = Mux(isOpf, OPFFunct6(funct6), OPFFunct6.illegal) } class BackendIssueInst(implicit p: Parameters) extends VectorIssueInst()(p) { val reduction = Bool() // accumulates into vd[0] val scalar_to_vd0 = Bool() // mv scalar to vd[0] val wide_vd = Bool() // vd reads/writes at 2xSEW val wide_vs2 = Bool() // vs2 reads at 2xSEW val writes_mask = Bool() // writes dest as a mask val reads_vs1_mask = Bool() // vs1 read as mask val reads_vs2_mask = Bool() // vs2 read as mask val rs1_is_rs2 = Bool() val nf_log2 = UInt(2.W) val renv1 = Bool() val renv2 = Bool() val renvd = Bool() val renvm = Bool() val wvd = Bool() } class IssueQueueInst(nSeqs: Int)(implicit p: Parameters) extends BackendIssueInst()(p) { val seq = UInt(nSeqs.W) } class VectorWrite(writeBits: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val eg = UInt(log2Ceil(32 * vLen / writeBits).W) def bankId = if (vrfBankBits == 0) 0.U else eg(vrfBankBits-1,0) val data = UInt(writeBits.W) val mask = UInt(writeBits.W) } class ScalarWrite extends Bundle { val data = UInt(64.W) val fp = Bool() val size = UInt(2.W) val rd = UInt(5.W) } class VectorReadReq(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val eg = UInt(log2Ceil(egsTotal).W) val oldest = Bool() } class VectorReadIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val req = Decoupled(new VectorReadReq) val resp = Input(UInt(dLen.W)) } class VectorIndexAccessIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val ready = Output(Bool()) val valid = Input(Bool()) val vrs = Input(UInt(5.W)) val eidx = Input(UInt((1+log2Ceil(maxVLMax)).W)) val eew = Input(UInt(2.W)) val idx = Output(UInt(64.W)) } class VectorMaskAccessIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val ready = Output(Bool()) val valid = Input(Bool()) val eidx = Input(UInt((1+log2Ceil(maxVLMax)).W)) val mask = Output(Bool()) } class MaskedByte(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val debug_id = UInt(debugIdSz.W) val data = UInt(8.W) val mask = Bool() } class ExecuteMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val eidx = UInt(log2Ceil(maxVLMax).W) val vl = UInt((1+log2Ceil(maxVLMax)).W) val rvs1_data = UInt(dLen.W) val rvs2_data = UInt(dLen.W) val rvd_data = UInt(dLen.W) val rvm_data = UInt(dLen.W) val rvs1_elem = UInt(64.W) val rvs2_elem = UInt(64.W) val rvd_elem = UInt(64.W) val rvs1_eew = UInt(2.W) val rvs2_eew = UInt(2.W) val rvd_eew = UInt(2.W) val vd_eew = UInt(2.W) val rmask = UInt(dLenB.W) val wmask = UInt(dLenB.W) val full_tail_mask = UInt(dLen.W) val wvd_eg = UInt(log2Ceil(egsTotal).W) val funct3 = UInt(3.W) def isOpi = funct3.isOneOf(OPIVV, OPIVI, OPIVX) def isOpm = funct3.isOneOf(OPMVV, OPMVX) def isOpf = funct3.isOneOf(OPFVV, OPFVF) def opmf6 = Mux(isOpm, OPMFunct6(funct6), OPMFunct6.illegal) def opif6 = Mux(isOpi, OPIFunct6(funct6), OPIFunct6.illegal) def opff6 = Mux(isOpf, OPFFunct6(funct6), OPFFunct6.illegal) def vd_eew8 = vd_eew === 0.U def vd_eew16 = vd_eew === 1.U def vd_eew32 = vd_eew === 2.U def vd_eew64 = vd_eew === 3.U val funct6 = UInt(6.W) val rs1 = UInt(5.W) val rs2 = UInt(5.W) val rd = UInt(5.W) val vm = Bool() val head = Bool() val tail = Bool() val vat = UInt(vParams.vatSz.W) val acc = Bool() val rm = UInt(3.W) def vxrm = rm(1,0) def frm = rm } class StoreDataMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val stdata = UInt(dLen.W) val stmask = UInt(dLenB.W) val debug_id = UInt(debugIdSz.W) val tail = Bool() val vat = UInt(vParams.vatSz.W) def asMaskedBytes = { val bytes = Wire(Vec(dLenB, new MaskedByte)) for (i <- 0 until dLenB) { bytes(i).data := stdata(((i+1)8)-1,i8) bytes(i).mask := stmask(i) bytes(i).debug_id := debug_id } bytes } } class LoadRespMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val wvd_eg = UInt(log2Ceil(egsTotal).W) val wmask = UInt(dLenB.W) val tail = Bool() val debug_id = UInt(debugIdSz.W) val vat = UInt(vParams.vatSz.W) } class PermuteMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val renv2 = Bool() val renvm = Bool() val rvs2_data = UInt(dLen.W) val eidx = UInt(log2Ceil(maxVLMax).W) val rvs2_eew = UInt(2.W) val rvm_data = UInt(dLen.W) val vmu = Bool() val vl = UInt((1+log2Ceil(maxVLMax)).W) val tail = Bool() } class PipeHazard(pipe_depth: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val latency = UInt(log2Ceil(pipe_depth).W) val eg = UInt(log2Ceil(egsTotal).W) def eg_oh = UIntToOH(eg) } class SequencerHazard(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val vat = UInt(vParams.vatSz.W) val rintent = UInt(egsTotal.W) val wintent = UInt(egsTotal.W) } class InstructionHazard(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val vat = UInt(vParams.vatSz.W) val rintent = UInt(32.W) val wintent = UInt(32.W) } File SegmentedMultiplyPipe.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ import saturn.insns._ case class IntegerMultiplyFactory(depth: Int, segmented: Boolean) extends FunctionalUnitFactory { def base_insns = Seq( MUL.VV, MUL.VX, MULH.VV, MULH.VX, MULHU.VV, MULHU.VX, MULHSU.VV, MULHSU.VX, WMUL.VV, WMUL.VX, WMULU.VV, WMULU.VX, WMULSU.VV, WMULSU.VX, MACC.VV, MACC.VX, NMSAC.VV, NMSAC.VX, MADD.VV, MADD.VX, NMSUB.VV, NMSUB.VX, WMACC.VV, WMACC.VX, WMACCU.VV, WMACCU.VX, WMACCSU.VV , WMACCSU.VX, WMACCUS.VV, WMACCUS.VX, SMUL.VV, SMUL.VX) def insns = if (segmented) base_insns else base_insns.map(_.elementWise) def generate(implicit p: Parameters) = if (segmented) { new SegmentedMultiplyPipe(depth)(p) } else { new ElementwiseMultiplyPipe(depth)(p) } } class SegmentedMultiplyPipe(depth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit(depth)(p) { val supported_insns = IntegerMultiplyFactory(depth, true).insns io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched io.set_vxsat := false.B io.set_fflags.valid := false.B io.set_fflags.bits := DontCare val ctrl = new VectorDecoder(io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, 0.U, 0.U, supported_insns, Seq( MULHi, MULSign1, MULSign2, MULSwapVdV2, MULAccumulate, MULSub)) val in_eew = io.pipe(0).bits.rvs1_eew val out_eew = io.pipe(0).bits.vd_eew val in_vs1 = io.pipe(0).bits.rvs1_data val in_vs2 = io.pipe(0).bits.rvs2_data val in_vd = io.pipe(0).bits.rvd_data val mul_in1 = in_vs1 val mul_in2 = Mux(ctrl.bool(MULSwapVdV2), in_vd, in_vs2) val multipliers = Seq.fill(dLenB >> 3)(Module(new MultiplyBlock)) for (i <- 0 until (dLenB >> 3)) { multipliers(i).io.in1_signed := ctrl.bool(MULSign1) multipliers(i).io.in2_signed := ctrl.bool(MULSign2) multipliers(i).io.eew := io.pipe(0).bits.rvs1_eew multipliers(i).io.in1 := mul_in1.asTypeOf(Vec(dLenB >> 3, UInt(64.W)))(i) multipliers(i).io.in2 := mul_in2.asTypeOf(Vec(dLenB >> 3, UInt(64.W)))(i) } val mul_out_comb = VecInit(multipliers.map(_.io.out_data)).asUInt //////////////////////////////////////////////////////////////////////////////////////////// // Pipeline Stages Before Adder Array //////////////////////////////////////////////////////////////////////////////////////////// val mul_out = Pipe(io.pipe(0).valid, mul_out_comb, depth-2).bits val in_eew_pipe = io.pipe(depth-2).bits.rvs1_eew val out_eew_pipe = io.pipe(depth-2).bits.vd_eew val ctrl_wmul = out_eew_pipe > in_eew_pipe val ctrl_smul = io.pipe(depth-2).bits.isOpi val ctrl_MULSub = Pipe(io.pipe(0).valid, ctrl.bool(MULSub), depth-2).bits val ctrl_MULSwapVdV2 = Pipe(io.pipe(0).valid, ctrl.bool(MULSwapVdV2), depth-2).bits val ctrl_MULAccumulate = Pipe(io.pipe(0).valid, ctrl.bool(MULAccumulate), depth-2).bits val ctrl_MULHi = Pipe(io.pipe(0).valid, ctrl.bool(MULHi), depth-2).bits val in_vs2_pipe = io.pipe(depth-2).bits.rvs2_data val in_vd_pipe = io.pipe(depth-2).bits.rvd_data //////////////////////////////////////////////////////////////////////////////////////////// val hi = VecInit.tabulate(4)({sew => VecInit(mul_out.asTypeOf(Vec((2dLenB) >> sew, UInt((8 << sew).W))).grouped(2).map(_.last).toSeq).asUInt })(in_eew_pipe) val lo = VecInit.tabulate(4)({sew => VecInit(mul_out.asTypeOf(Vec((2dLenB) >> sew, UInt((8 << sew).W))).grouped(2).map(_.head).toSeq).asUInt })(in_eew_pipe) val half_sel = (io.pipe(depth-2).bits.eidx >> (dLenOffBits.U - out_eew_pipe))(0) val wide = Mux(half_sel, mul_out >> dLen, mul_out)(dLen-1,0) val (smul_clipped, smul_sat) = { val smul_arr = Module(new VectorSMul) smul_arr.io.mul_in := mul_out smul_arr.io.eew := out_eew_pipe smul_arr.io.vxrm := io.pipe(depth-2).bits.vxrm (smul_arr.io.clipped, smul_arr.io.sat) } val adder_arr = Module(new AdderArray(dLenB)) adder_arr.io.in1 := Mux(ctrl_wmul, wide, lo).asTypeOf(Vec(dLenB, UInt(8.W))) adder_arr.io.in2 := Mux(ctrl_MULAccumulate, Mux(ctrl_MULSwapVdV2, in_vs2_pipe, in_vd_pipe), 0.U(dLen.W)).asTypeOf(Vec(dLenB, UInt(8.W))) adder_arr.io.incr := VecInit.fill(dLenB)(false.B) adder_arr.io.mask_carry := 0.U adder_arr.io.signed := DontCare adder_arr.io.eew := out_eew_pipe adder_arr.io.avg := false.B adder_arr.io.rm := DontCare adder_arr.io.sub := ctrl_MULSub adder_arr.io.cmask := false.B val add_out = adder_arr.io.out val out = Mux(ctrl_smul, smul_clipped, 0.U) \| Mux(ctrl_MULHi, hi, 0.U) \| Mux(!ctrl_smul && !ctrl_MULHi, add_out.asUInt, 0.U) val pipe_out = Pipe(io.pipe(depth-2).valid, out, 1).bits val vxsat = Mux(ctrl_smul, smul_sat, 0.U) & io.pipe(depth-2).bits.wmask val pipe_vxsat = Pipe(io.pipe(depth-2).valid, vxsat, 1).bits io.pipe0_stall := false.B io.write.valid := io.pipe(depth-1).valid io.write.bits.eg := io.pipe(depth-1).bits.wvd_eg io.write.bits.data := pipe_out io.write.bits.mask := FillInterleaved(8, io.pipe(depth-1).bits.wmask) io.set_vxsat := io.pipe(depth-1).valid && (pipe_vxsat =/= 0.U) io.scalar_write.valid := false.B io.scalar_write.bits := DontCare } class MultiplyBlock extends Module { val xLen = 64 val io = IO(new Bundle { val in1_signed = Input(Bool()) val in2_signed = Input(Bool()) val eew = Input(UInt(2.W)) val in1 = Input(UInt(xLen.W)) val in2 = Input(UInt(xLen.W)) val out_data = Output(UInt((2xLen).W)) }) val mul64 = Module(new Multiplier(64)) mul64.io.in1_signed := io.in1_signed mul64.io.in2_signed := io.in2_signed mul64.io.in1 := io.in1 mul64.io.in2 := io.in2 val mul32 = Module(new Multiplier(32)) mul32.io.in1_signed := io.in1_signed mul32.io.in2_signed := io.in2_signed mul32.io.in1 := io.in1(63,32) mul32.io.in2 := io.in2(63,32) val mul16 = Seq.tabulate(2) { i => val indh = 32(i+1) - 1 val indl = 32i + 16 val in1 = io.in1(indh, indl) val in2 = io.in2(indh, indl) val mul = Module(new Multiplier(16)) mul.io.in1_signed := io.in1_signed mul.io.in2_signed := io.in2_signed mul.io.in1 := in1 mul.io.in2 := in2 mul } val mul8 = Seq.tabulate(4) { i => val indh = 16(i+1) - 1 val indl = 16i + 8 val in1 = io.in1(indh, indl) val in2 = io.in2(indh, indl) val mul = Module(new Multiplier(8)) mul.io.in1_signed := io.in1_signed mul.io.in2_signed := io.in2_signed mul.io.in1 := in1 mul.io.in2 := in2 mul } when (io.eew === 0.U) { mul16(1).io.in1 := Cat(Fill(8, io.in1_signed && io.in1(55)), io.in1(55, 48)) mul16(1).io.in2 := Cat(Fill(8, io.in2_signed && io.in2(55)), io.in2(55, 48)) mul32.io.in1 := Cat(Fill(8, io.in1_signed && io.in1(39)), io.in1(39, 32)) mul32.io.in2 := Cat(Fill(8, io.in2_signed && io.in2(39)), io.in2(39, 32)) mul16(0).io.in1 := Cat(Fill(8, io.in1_signed && io.in1(23)), io.in1(23, 16)) mul16(0).io.in2 := Cat(Fill(8, io.in2_signed && io.in2(23)), io.in2(23, 16)) mul64.io.in1 := Cat(Fill(8, io.in1_signed && io.in1(7)), io.in1(7,0)) mul64.io.in2 := Cat(Fill(8, io.in2_signed && io.in2(7)), io.in2(7,0)) io.out_data := Cat(mul8(3).io.out_data, mul16(1).io.out_data(15,0), mul8(2).io.out_data, mul32.io.out_data(15,0), mul8(1).io.out_data, mul16(0).io.out_data(15,0), mul8(0).io.out_data, mul64.io.out_data(15,0)) } .elsewhen (io.eew === 1.U) { mul32.io.in1 := Cat(Fill(16, io.in1_signed && io.in1(47)), io.in1(47, 32)) mul32.io.in2 := Cat(Fill(16, io.in2_signed && io.in2(47)), io.in2(47, 32)) mul64.io.in1 := Cat(Fill(16, io.in1_signed && io.in1(15)), io.in1(15,0)) mul64.io.in2 := Cat(Fill(16, io.in2_signed && io.in2(15)), io.in2(15,0)) io.out_data := Cat(mul16(1).io.out_data, mul32.io.out_data(31,0), mul16(0).io.out_data, mul64.io.out_data(31,0)) } .elsewhen (io.eew === 2.U) { mul64.io.in1 := Cat(Fill(32, io.in1_signed && io.in1(31)), io.in1(31,0)) mul64.io.in2 := Cat(Fill(32, io.in2_signed && io.in2(31)), io.in2(31,0)) io.out_data := Cat(mul32.io.out_data, mul64.io.out_data(63,0)) } .otherwise { io.out_data := mul64.io.out_data } } class Multiplier(width: Int) extends Module { val io = IO(new Bundle { val in1_signed = Input(Bool()) val in2_signed = Input(Bool()) val in1 = Input(UInt(width.W)) val in2 = Input(UInt(width.W)) val out_data = Output(UInt((2width).W)) }) val lhs = Cat(io.in1_signed && io.in1(width-1), io.in1).asSInt val rhs = Cat(io.in2_signed && io.in2(width-1), io.in2).asSInt val prod = lhs * rhs io.out_data := prod(2width-1,0) } class VectorSMul(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val eew = Input(UInt(2.W)) val vxrm = Input(UInt(2.W)) val mul_in = Input(UInt((2dLen).W)) val clipped = Output(UInt((dLen).W)) val sat = Output(UInt(dLenB.W)) }) val sat_sew = Wire(Vec(4, UInt(dLenB.W))) val clipped_sew = Wire(Vec(4, UInt(dLen.W))) for (sew <- 0 until 4) { val wideProds = io.mul_in.asTypeOf(Vec(dLenB >> sew, SInt((16 << sew).W))) val smul = wideProds.map { wideElem => val rounding_incr = RoundingIncrement(io.vxrm, wideElem((8 << sew)-1, 0)) (wideElem >> ((8 << sew) - 1)) + Cat(0.U(1.W), rounding_incr).asSInt } val clip_neg = (-1 << ((8 << sew)-1)).S val clip_pos = ((1 << ((8 << sew)-1)) - 1).S val clip_hi = smul.map{ _ > clip_pos } val clip_lo = smul.map{ _ < clip_neg } clipped_sew(sew) := smul.zipWithIndex.map { case (sm, i) => val long = Mux(clip_hi(i), clip_pos, 0.S) \| Mux(clip_lo(i), clip_neg, 0.S) \| Mux(!clip_hi(i) && !clip_lo(i), sm, 0.S) long((8 << sew)-1, 0) }.asUInt val sat_vec_sew = smul.zipWithIndex.map { case (sm, i) => clip_hi(i) \|\| clip_lo(i) } sat_sew(sew) := FillInterleaved((1 << sew), sat_vec_sew) } io.clipped := clipped_sew(io.eew) io.sat := sat_sew(io.eew) }	module SegmentedMultiplyPipe( // @[SegmentedMultiplyPipe.scala:31:7] input clock, // @[SegmentedMultiplyPipe.scala:31:7] input [2:0] io_iss_op_funct3, // @[FunctionalUnit.scala:49:14] input [5:0] io_iss_op_funct6, // @[FunctionalUnit.scala:49:14] output io_iss_ready, // @[FunctionalUnit.scala:49:14] output io_set_vxsat, // @[FunctionalUnit.scala:49:14] output io_write_valid, // @[FunctionalUnit.scala:49:14] output [6:0] io_write_bits_eg, // @[FunctionalUnit.scala:49:14] output [63:0] io_write_bits_data, // @[FunctionalUnit.scala:49:14] output [63:0] io_write_bits_mask, // @[FunctionalUnit.scala:49:14] input io_pipe_0_valid, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_rvs1_data, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_rvs2_data, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_rvd_data, // @[FunctionalUnit.scala:49:14] input [1:0] io_pipe_0_bits_rvs1_eew, // @[FunctionalUnit.scala:49:14] input [2:0] io_pipe_0_bits_funct3, // @[FunctionalUnit.scala:49:14] input [5:0] io_pipe_0_bits_funct6, // @[FunctionalUnit.scala:49:14] input io_pipe_1_valid, // @[FunctionalUnit.scala:49:14] input [7:0] io_pipe_1_bits_eidx, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_1_bits_rvs2_data, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_1_bits_rvd_data, // @[FunctionalUnit.scala:49:14] input [1:0] io_pipe_1_bits_rvs1_eew, // @[FunctionalUnit.scala:49:14] input [1:0] io_pipe_1_bits_vd_eew, // @[FunctionalUnit.scala:49:14] input [7:0] io_pipe_1_bits_wmask, // @[FunctionalUnit.scala:49:14] input [2:0] io_pipe_1_bits_funct3, // @[FunctionalUnit.scala:49:14] input [2:0] io_pipe_1_bits_rm, // @[FunctionalUnit.scala:49:14] input io_pipe_2_valid, // @[FunctionalUnit.scala:49:14] input [7:0] io_pipe_2_bits_wmask, // @[FunctionalUnit.scala:49:14] input [6:0] io_pipe_2_bits_wvd_eg // @[FunctionalUnit.scala:49:14] ); wire [7:0] _adder_arr_io_out_0; // @[SegmentedMultiplyPipe.scala:96:25] wire [7:0] _adder_arr_io_out_1; // @[SegmentedMultiplyPipe.scala:96:25] wire [7:0] _adder_arr_io_out_2; // @[SegmentedMultiplyPipe.scala:96:25] wire [7:0] _adder_arr_io_out_3; // @[SegmentedMultiplyPipe.scala:96:25] wire [7:0] _adder_arr_io_out_4; // @[SegmentedMultiplyPipe.scala:96:25] wire [7:0] _adder_arr_io_out_5; // @[SegmentedMultiplyPipe.scala:96:25] wire [7:0] _adder_arr_io_out_6; // @[SegmentedMultiplyPipe.scala:96:25] wire [7:0] _adder_arr_io_out_7; // @[SegmentedMultiplyPipe.scala:96:25] wire [63:0] _smul_arr_io_clipped; // @[SegmentedMultiplyPipe.scala:89:26] wire [7:0] _smul_arr_io_sat; // @[SegmentedMultiplyPipe.scala:89:26] wire [127:0] _multipliers_0_io_out_data; // @[SegmentedMultiplyPipe.scala:52:48] wire [4:0] _GEN = ~(io_iss_op_funct6[4:0]); // @[pla.scala:78:21] wire [4:0] _GEN_0 = ~(io_pipe_0_bits_funct6[4:0]); // @[pla.scala:78:21] wire [1:0] _decode_andMatrixOutputs_T_1 = {_GEN_0[2], _GEN_0[4]}; // @[pla.scala:78:21, :91:29, :98:53] reg [127:0] mul_out_pipe_b; // @[Valid.scala:142:26] reg ctrl_MULSub_pipe_b; // @[Valid.scala:142:26] reg ctrl_MULSwapVdV2_pipe_b; // @[Valid.scala:142:26] reg ctrl_MULAccumulate_pipe_b; // @[Valid.scala:142:26] reg ctrl_MULHi_pipe_b; // @[Valid.scala:142:26] wire [7:0] _half_sel_T_2 = io_pipe_1_bits_eidx >> 2'h3 - io_pipe_1_bits_vd_eew; // @[SegmentedMultiplyPipe.scala:85:{46,64}] wire [3:0][63:0] _GEN_1 = {{mul_out_pipe_b[63:0]}, {{mul_out_pipe_b[95:64], mul_out_pipe_b[31:0]}}, {{mul_out_pipe_b[111:96], mul_out_pipe_b[79:64], mul_out_pipe_b[47:32], mul_out_pipe_b[15:0]}}, {{mul_out_pipe_b[119:112], mul_out_pipe_b[103:96], mul_out_pipe_b[87:80], mul_out_pipe_b[71:64], mul_out_pipe_b[55:48], mul_out_pipe_b[39:32], mul_out_pipe_b[23:16], mul_out_pipe_b[7:0]}}}; // @[Valid.scala:142:26] wire [63:0] _GEN_2 = io_pipe_1_bits_vd_eew > io_pipe_1_bits_rvs1_eew ? (_half_sel_T_2[0] ? mul_out_pipe_b[127:64] : mul_out_pipe_b[63:0]) : _GEN_1[io_pipe_1_bits_rvs1_eew]; // @[Valid.scala:142:26] wire [63:0] _GEN_3 = ctrl_MULAccumulate_pipe_b ? (ctrl_MULSwapVdV2_pipe_b ? io_pipe_1_bits_rvs2_data : io_pipe_1_bits_rvd_data) : 64'h0; // @[Valid.scala:142:26] reg [63:0] pipe_out_pipe_b; // @[Valid.scala:142:26] reg [7:0] pipe_vxsat_pipe_b; // @[Valid.scala:142:26] wire ctrl_smul = io_pipe_1_bits_funct3 == 3'h0 \| io_pipe_1_bits_funct3 == 3'h3 \| io_pipe_1_bits_funct3 == 3'h4; // @[SegmentedMultiplyPipe.scala:31:7] wire [3:0][63:0] _GEN_4 = {{mul_out_pipe_b[127:64]}, {{mul_out_pipe_b[127:96], mul_out_pipe_b[63:32]}}, {{mul_out_pipe_b[127:112], mul_out_pipe_b[95:80], mul_out_pipe_b[63:48], mul_out_pipe_b[31:16]}}, {{mul_out_pipe_b[127:120], mul_out_pipe_b[111:104], mul_out_pipe_b[95:88], mul_out_pipe_b[79:72], mul_out_pipe_b[63:56], mul_out_pipe_b[47:40], mul_out_pipe_b[31:24], mul_out_pipe_b[15:8]}}}; // @[Valid.scala:142:26] always @(posedge clock) begin // @[SegmentedMultiplyPipe.scala:31:7] if (io_pipe_0_valid) begin // @[FunctionalUnit.scala:49:14] mul_out_pipe_b <= _multipliers_0_io_out_data; // @[Valid.scala:142:26] ctrl_MULSub_pipe_b <= &{io_pipe_0_bits_funct6[1], io_pipe_0_bits_funct6[3], _GEN_0[4]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] ctrl_MULSwapVdV2_pipe_b <= &_decode_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] ctrl_MULAccumulate_pipe_b <= \|{&_decode_andMatrixOutputs_T_1, &{io_pipe_0_bits_funct6[2], io_pipe_0_bits_funct6[3]}}; // @[pla.scala:90:45, :98:{53,70}, :114:{19,36}] ctrl_MULHi_pipe_b <= \|{&{_GEN_0[0], _GEN_0[3]}, &{io_pipe_0_bits_funct6[1], _GEN_0[3], io_pipe_0_bits_funct3[1]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] end if (io_pipe_1_valid) begin // @[FunctionalUnit.scala:49:14] pipe_out_pipe_b <= (ctrl_smul ? _smul_arr_io_clipped : 64'h0) \| (ctrl_MULHi_pipe_b ? _GEN_4[io_pipe_1_bits_rvs1_eew] : 64'h0) \| (ctrl_smul \| ctrl_MULHi_pipe_b ? 64'h0 : {_adder_arr_io_out_7, _adder_arr_io_out_6, _adder_arr_io_out_5, _adder_arr_io_out_4, _adder_arr_io_out_3, _adder_arr_io_out_2, _adder_arr_io_out_1, _adder_arr_io_out_0}); // @[Valid.scala:142:26] pipe_vxsat_pipe_b <= (ctrl_smul ? _smul_arr_io_sat : 8'h0) & io_pipe_1_bits_wmask; // @[Valid.scala:142:26] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File FSECompressorDicBuilder.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants import ZstdConsts._ class FSECompTransformationTable extends Bundle { val nbbit = UInt(32.W) val findstate = UInt(32.W) val from_last_symbol = Bool() } class FSECompressorDicBuilderIO(val interleave_cnt: Int)(implicit p: Parameters) extends Bundle { val nb_seq = Flipped(Decoupled(UInt(64.W))) val ll_stream = Flipped(new MemLoaderConsumerBundle) val ll_table_log = Decoupled(UInt(4.W)) val symbol_info = Vec(interleave_cnt, Flipped(Decoupled(new FSESymbolInfo))) val symbolTT_info = Vec(interleave_cnt, Decoupled(new FSECompTransformationTable)) val state_table_idx = Vec(interleave_cnt, Input(UInt(16.W))) val new_state = Vec(interleave_cnt, Valid(UInt(16.W))) val header_writes = Decoupled(new WriterBundle) val predefined_mode = Decoupled(Bool()) val lookup_done = Flipped(Decoupled(Bool())) } // NOTE : about 4 * 2^tableLog Bytes of on-chip regs class FSECompressorDicBuilder( val printInfo: String, val interleave_cnt: Int, val as_zstd_submodule: Boolean, val max_symbol_value: Int, val max_table_log: Int, val predefined_table_log: Int, val mark_end_of_header: Boolean = false) (implicit p: Parameters) extends Module { val io = IO(new FSECompressorDicBuilderIO(interleave_cnt)) def BIT_highbit32(x: UInt): UInt = { // add assertion about x width? val highBit = 31.U - PriorityEncoder(Reverse(x)) highBit } val rtbTable_initialized = RegInit(false.B) val rtbTable = RegInit(VecInit(Seq.fill(8)(0.U(32.W)))) when (!rtbTable_initialized) { rtbTable(0) := 0.U rtbTable(1) := 473195.U rtbTable(2) := 504333.U rtbTable(3) := 520860.U rtbTable(4) := 550000.U rtbTable(5) := 700000.U rtbTable(6) := 750000.U rtbTable(7) := 830000.U rtbTable_initialized := true.B } val LL_symbolTTDeltaNbBitsDefaultValues = List( 327552, 327584, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393152, 393152, 393152, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 327584, 393088, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152 ) val LL_symbolTTDeltaFindStateDefaultValues = List( -4, 1, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 28, 29, 30, 30, 32, 34, 36, 38, 40, 42, 44, 46, 47, 51, 54, 55, 56, 57, 58, 59, 60, 61, 62 ) val LL_DefaultTableU16 = List( 64, 65, 86, 107, 66, 87, 108, 88, 109, 67, 110, 68, 89, 90, 111, 69, 112, 70, 91, 92, 113, 71, 114, 72, 93, 94, 115, 73, 116, 95, 74, 117, 75, 96, 97, 118, 76, 119, 77, 98, 99, 120, 78, 121, 79, 100, 101, 122, 80, 123, 81, 102, 103, 82, 104, 83, 105, 84, 106, 85, 127, 126, 125, 124 ) val OF_symbolTTDeltaNbBitsDefaultValues = List( 327648, 327648, 327648, 327648, 327648, 327648, 327616, 327616, 327616, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648 ) val OF_symbolTTDeltaFindStateDefaultValues = List( -1, 0, 1, 2, 3, 4, 4, 6, 8, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 ) val OF_DefaultTableU16 = List( 32, 55, 46, 37, 51, 42, 33, 56, 38, 47, 43, 52, 34, 57, 48, 39, 53, 44, 35, 58, 49, 40, 54, 45, 36, 50, 41, 63, 62, 61, 60, 59 ) val ML_symbolTTDeltaNbBitsDefaultValues = List( 393152, 327552, 327584, 393088, 393088, 393088, 393088, 393088, 393088, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152 ) val ML_symbolTTDeltaFindStateDefaultValues = List( -1, -3, 2, 6, 8, 10, 12, 14, 16, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62 ) val ML_DefaultTableU16 = List( 64, 65, 86, 107, 108, 66, 87, 109, 67, 88, 89, 110, 68, 111, 69, 90, 91, 112, 70, 113, 92, 71, 114, 93, 72, 115, 94, 73, 116, 95, 74, 117, 96, 75, 118, 97, 76, 119, 98, 77, 120, 99, 78, 100, 79, 101, 80, 102, 81, 103, 82, 104, 83, 105, 84, 106, 85, 127, 126, 125, 124, 123, 122, 121 ) // Tie up wires io.ll_stream.output_ready := false.B io.ll_stream.user_consumed_bytes := 0.U io.nb_seq.ready := false.B val predefined_mode_q = Module(new Queue(Bool(), 4)) predefined_mode_q.io.enq.valid := false.B predefined_mode_q.io.enq.bits := false.B io.predefined_mode <> predefined_mode_q.io.deq val sIdle = 0.U val sCount = 1.U val sNormalizeCount = 2.U val sBuildCTableSymbolStartPositions = 3.U val sBuildCTableSpreadSymbols = 4.U val sBuildCTableBuildTable = 5.U val sBuildCTableSymbolTT = 6.U val sWriteCTable = 7.U val sLookup = 8.U val dicBuilderState = RegInit(0.U(4.W)) val COLLECT_STAT_PROCESS_BYTES = p(FSECompressDicBuilderProcessedStatBytesPerCycle) val COLLECT_STAT_PROCESS_BYTES_LOG2 = log2Ceil(COLLECT_STAT_PROCESS_BYTES + 1) val tableLogLL = max_table_log // Always use maximum possible tableLog since dictionary lookups are basically free??????? val maxSymbolLL = max_symbol_value val maxSymbolLLPlus1 = max_symbol_value + 1 /////////////////////////////////////////////////////////////////////////// // sCount /////////////////////////////////////////////////////////////////////////// val ll_count = RegInit(VecInit(Seq.fill(maxSymbolLLPlus1)(0.U(32.W)))) val ll_max_symbol_value = RegInit(0.U(32.W)) val ll_nbseq_1 = RegInit(0.U(64.W)) val input_ll_symbols = WireInit(VecInit(Seq.fill(COLLECT_STAT_PROCESS_BYTES)(0.U(8.W)))) for (i <- 0 until COLLECT_STAT_PROCESS_BYTES) { input_ll_symbols(i) := io.ll_stream.output_data >> (i8).U } dontTouch(input_ll_symbols) val avail_bytes = io.ll_stream.available_output_bytes val table = Seq.fill(maxSymbolLLPlus1)(WireInit(VecInit(Seq.fill(COLLECT_STAT_PROCESS_BYTES)(0.U(1.W))))) for (i <- 0 until maxSymbolLLPlus1) { for (j <- 0 until COLLECT_STAT_PROCESS_BYTES) { table(i)(j) := Mux(j.U < avail_bytes && (input_ll_symbols(j) === i.U), 1.U, 0.U) } } val stat_sum = WireInit(VecInit(Seq.fill(maxSymbolLLPlus1)(0.U(COLLECT_STAT_PROCESS_BYTES_LOG2.W)))) for (i <- 0 until maxSymbolLLPlus1) { stat_sum(i) := table(i).reduce(_ +& _) } val has_value = WireInit(VecInit(Seq.fill(maxSymbolLLPlus1)(0.U(1.W)))) for (i <- 0 until maxSymbolLLPlus1) { has_value(i) := Mux(stat_sum(i) > 0.U, 1.U, 0.U) } val has_value_cat = Cat(has_value) val cur_max_value = (maxSymbolLLPlus1 - 1).U - PriorityEncoder(has_value_cat) when (dicBuilderState === sCount) { when (io.ll_stream.output_valid) { for (i <- 0 until maxSymbolLLPlus1) { ll_count(i) := ll_count(i) + stat_sum(i) } ll_max_symbol_value := Mux(ll_max_symbol_value > cur_max_value, ll_max_symbol_value, cur_max_value) } } /////////////////////////////////////////////////////////////////////////// // sNormalizeCount (FSE_normalizeCount) /////////////////////////////////////////////////////////////////////////// / * { static U32 const rtbTable[] = { 0, 473195, 504333, 520860, 550000, 700000, 750000, 830000 }; * short const lowProbCount = useLowProbCount ? -1 : 1; * U64 const scale = 62 - tableLog; * U64 const step = ZSTD_div64((U64)1<<62, (U32)total); * U64 const vStep = 1ULL<<(scale-20); * int stillToDistribute = 1<<tableLog; * unsigned s; * unsigned largest=0; * short largestP=0; * U32 lowThreshold = (U32)(total >> tableLog); * for (s=0; s<=maxSymbolValue; s++) { * if (count[s] == total) return 0; // rle special case * if (count[s] == 0) { normalizedCounter[s]=0; continue; } * if (count[s] <= lowThreshold) { * normalizedCounter[s] = lowProbCount; * stillToDistribute--; * } else { * short proba = (short)((count[s]step) >> scale); if (proba<8) { * U64 restToBeat = vStep * rtbTable[proba]; * proba += (count[s]step) - ((U64)proba<<scale) > restToBeat; } * if (proba > largestP) { largestP=proba; largest=s; } * normalizedCounter[s] = proba; * stillToDistribute -= proba; * } } * if (-stillToDistribute >= (normalizedCounter[largest] >> 1)) { * // corner case, need another normalization method * size_t const errorCode = FSE_normalizeM2(normalizedCounter, tableLog, count, total, maxSymbolValue, lowProbCount); * if (FSE_isError(errorCode)) return errorCode; * } * else normalizedCounter[largest] += (short)stillToDistribute; / val neg_one_uint16 = (1 << 16) - 1 // val ll_useLowProbCount = ll_nbseq_1 >= 2048.U // don't use lowProb stuff for now, (small comp ratio gains for thousands of cycle tradeoff) val ll_useLowProbCount = ll_nbseq_1 >= BigInt("FFFFFFFF", 16).U val ll_lowProbCount = Wire(UInt(16.W)) ll_lowProbCount := Mux(ll_useLowProbCount, neg_one_uint16.U, 1.U) val ll_scale = Wire(UInt(7.W)) ll_scale := 62.U - tableLogLL.U val ll_step = Wire(UInt(64.W)) ll_step := BigInt("4000000000000000", 16).U / ll_nbseq_1 val ll_scale_20 = Wire(UInt(7.W)) ll_scale_20 := ll_scale - 20.U val ll_vStep = Wire(UInt(64.W)) ll_vStep := 1.U << ll_scale_20 val ll_still_to_distribute = (1 << tableLogLL).U val ll_lowThreshold = Wire(UInt(32.W)) ll_lowThreshold := ll_nbseq_1 >> tableLogLL.U val ll_proba_base = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) val ll_proba = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) val ll_count_times_step = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(64.W)))) for (i <- 0 until maxSymbolLL + 1) { ll_count_times_step(i) := ll_count(i) ll_step ll_proba_base(i) := ll_count_times_step(i) >> ll_scale val restToBeat = ll_vStep * rtbTable(ll_proba_base(i)) val ll_add_to_proba_base = Mux(ll_count(i) * ll_step - (ll_proba_base(i) << ll_scale) > restToBeat, 1.U, 0.U) ll_proba(i) := Mux(ll_proba_base(i) < 8.U, ll_proba_base(i) + ll_add_to_proba_base, ll_proba_base(i)) } val ll_normalizedCounter = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) val ll_normalizedCounterMaxAdjusted = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) val ll_count_has_nbseq_1_as_value = ll_count.map{ case count => count === ll_nbseq_1 }.reduce(_ \|\| _) val ll_rle = ll_count_has_nbseq_1_as_value for (i <- 0 until maxSymbolLL + 1) { ll_normalizedCounter(i) := Mux(ll_count(i) === 0.U, 0.U, Mux(ll_count(i) <= ll_lowThreshold, ll_lowProbCount, ll_proba(i))) } val ll_smallOrEqToLowThresholdCount = ll_count.map{ case count => ((count <= ll_lowThreshold) && (count > 0.U)).asUInt }.reduce(_ +& _) val ll_largerThanLowThresholdProbaSum = ll_count.zipWithIndex.map{ case (count, idx) => Mux((count === ll_nbseq_1) \|\| (count === 0.U) \|\| (count <= ll_lowThreshold), 0.U, ll_proba(idx)) }.reduce(_ +& _) val ll_normalizedCounterMax = ll_normalizedCounter.reduceTree((a, b) => Mux(a > b, a, b)) val ll_normalizedCounterIdx = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) for (i <- 0 until maxSymbolLL + 1) { ll_normalizedCounterIdx(i) := i.U } val ll_normalizedCounterMaxIdx = ll_normalizedCounter.zip(ll_normalizedCounterIdx).reduce{ (x, y) => (Mux(x._1 < y._1, y._1, x._1), Mux(x._1 < y._1, y._2, x._2)) }._2 val ll_nxtStillToDistribute = (ll_still_to_distribute - ll_largerThanLowThresholdProbaSum - ll_smallOrEqToLowThresholdCount).asSInt val ll_negNxtStillToDistribute = (-1).S * ll_nxtStillToDistribute val fse_normalize_corner_case = ll_negNxtStillToDistribute >= (ll_normalizedCounterMax >> 1.U).asSInt val fse_normalize_corner_case_reg = RegInit(false.B) when (dicBuilderState === sNormalizeCount && predefined_mode_q.io.enq.ready) { predefined_mode_q.io.enq.valid := true.B for (i <- 0 until maxSymbolLL + 1) { val ll_ncountSumStill2Dist = (ll_normalizedCounter(i).asSInt + ll_nxtStillToDistribute).asUInt ll_normalizedCounterMaxAdjusted(i) := Mux(i.U === ll_normalizedCounterMaxIdx, ll_ncountSumStill2Dist, ll_normalizedCounter(i)) } // Force predefined mode when we encounter normalization corner case fse_normalize_corner_case_reg := fse_normalize_corner_case predefined_mode_q.io.enq.bits := fse_normalize_corner_case when (fse_normalize_corner_case) { CompressAccelLogger.logInfo(printInfo + " DICBUILDER ForcePredefinedMode\n") } } // insert registers to avoid critical path issues val ll_normalizedCounterReg = RegInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) when (dicBuilderState === sNormalizeCount) { for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_count(%d): %d\n", i.U, ll_count(i)) } CompressAccelLogger.logInfo(printInfo + " ll_lowProbCount: %d\n", ll_lowProbCount) CompressAccelLogger.logInfo(printInfo + " ll_scale: %d\n", ll_scale) CompressAccelLogger.logInfo(printInfo + " ll_scale_20: %d\n", ll_scale_20) CompressAccelLogger.logInfo(printInfo + " ll_step: %d\n", ll_step) CompressAccelLogger.logInfo(printInfo + " ll_vStep: %d\n", ll_vStep) CompressAccelLogger.logInfo(printInfo + " ll_still_to_distribute: %d\n", ll_still_to_distribute) CompressAccelLogger.logInfo(printInfo + " ll_lowThreshold: %d\n", ll_lowThreshold) for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_count_times_step(%d): %d\n", i.U, ll_count_times_step(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_proba_base(%d): %d\n", i.U, ll_proba_base(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_proba(%d): %d\n", i.U, ll_proba(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounter(%d): %d\n", i.U, ll_normalizedCounter(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounterMaxAdjusted(%d): %d\n", i.U, ll_normalizedCounterMaxAdjusted(i)) } CompressAccelLogger.logInfo(printInfo + " ll_smallOrEqToLowThresholdCount: %d\n", ll_smallOrEqToLowThresholdCount) CompressAccelLogger.logInfo(printInfo + " ll_largerThanLowThresholdProbaSum: %d\n", ll_largerThanLowThresholdProbaSum) CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounterMax: %d\n", ll_normalizedCounterMax) CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounterMaxIdx: %d\n", ll_normalizedCounterMaxIdx) CompressAccelLogger.logInfo(printInfo + " ll_nxtStillToDistribute: %d\n", ll_nxtStillToDistribute) CompressAccelLogger.logInfo(printInfo + " ll_negNxtStillToDistribute: %d\n", ll_negNxtStillToDistribute) CompressAccelLogger.logInfo(printInfo + " (ll_normalizedCounterMax >> 1.U).asSInt: %d\n", (ll_normalizedCounterMax >> 1.U).asSInt) } /////////////////////////////////////////////////////////////////////////// // sBuildCTableSymbolStartPositions /////////////////////////////////////////////////////////////////////////// val LL_TABLESIZE = 1 << tableLogLL val ll_maxSV1 = ll_max_symbol_value + 1.U val ll_tableSize = LL_TABLESIZE.U val ll_tableMask = ll_tableSize - 1.U val ll_cumul = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) val ll_tableSymbol = RegInit(VecInit(Seq.fill(LL_TABLESIZE)(0.U(8.W)))) val ll_highThresholdBeforeCumul = WireInit(0.U(32.W)) ll_highThresholdBeforeCumul := ll_tableSize - 1.U val ll_normCountEqsNegOne = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(8.W)))) val ll_normCountEqsNegOneCumul = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(8.W)))) val ll_normCountEqsNegOneSum = ll_normCountEqsNegOne.reduce(_ +& _) val ll_highThresholdAfterCumul = RegInit(0.U(32.W)) val ll_cumulReg = RegInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) /////////////////////////////////////////////////////////////////////////// // sBuildCTableSpreadSymbols /////////////////////////////////////////////////////////////////////////// val LL_SPREAD_TABLE_SIZE = LL_TABLESIZE + 8 val ll_spread = RegInit(VecInit(Seq.fill(LL_SPREAD_TABLE_SIZE)(0.U(8.W)))) val add = BigInt("0101010101010101", 16) val ll_pos = RegInit(0.U(64.W)) val ll_s = RegInit(0.U(64.W)) val ll_sv = RegInit(0.U(64.W)) val ll_fse_tablestep = (ll_tableSize >> 1.U) + (ll_tableSize >> 3.U) + 3.U /////////////////////////////////////////////////////////////////////////// // sBuildCTableBuildTable / sBuildCTableSymbolTT /////////////////////////////////////////////////////////////////////////// val ll_tableU16 = RegInit(VecInit(Seq.fill(LL_TABLESIZE)(0.U(16.W)))) val ll_symbolTTDeltaNbBits = RegInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(32.W)))) val ll_symbolTTDeltaFindState = RegInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.S(32.W)))) val ll_total = RegInit(0.U(32.W)) val normCount = Wire(UInt(32.W)) normCount := ll_normalizedCounterReg(ll_s) /////////////////////////////////////////////////////////////////////////// // sLookup /////////////////////////////////////////////////////////////////////////// val symbolTT_lookup_fire_and_last_vec = WireInit(VecInit(Seq.fill(interleave_cnt)(false.B))) for (i <- 0 until interleave_cnt) { val cur_symbol = io.symbol_info(i).bits.symbol val last_symbol = io.symbol_info(i).bits.last_symbol val symbolTT_lookup_fire = DecoupledHelper( io.symbol_info(i).valid, io.symbolTT_info(i).ready, dicBuilderState === sLookup) io.symbol_info(i).ready := symbolTT_lookup_fire.fire(io.symbol_info(i).valid) io.symbolTT_info(i).valid := symbolTT_lookup_fire.fire(io.symbolTT_info(i).ready) io.symbolTT_info(i).bits.nbbit := ll_symbolTTDeltaNbBits(cur_symbol) io.symbolTT_info(i).bits.findstate := ll_symbolTTDeltaFindState(cur_symbol).asUInt io.symbolTT_info(i).bits.from_last_symbol := last_symbol io.new_state(i).valid := (dicBuilderState === sLookup) io.new_state(i).bits := ll_tableU16(io.state_table_idx(i)) symbolTT_lookup_fire_and_last_vec(i) := symbolTT_lookup_fire.fire && last_symbol } val dictionary_lookup_done = symbolTT_lookup_fire_and_last_vec.reduce(_ \|\| _) // this is okay since we know for sure that in huffman, the fse compressor will // not be kicked-off unless there are enough symobls to compress val use_predefined_mode = (io.nb_seq.bits <= ZSTD_SEQUENCE_PREDEFINED_MODE_LIMIT.U) \|\| fse_normalize_corner_case_reg val ll_table_log_fired = RegInit(false.B) io.ll_table_log.bits := Mux(use_predefined_mode, predefined_table_log.U, tableLogLL.U) io.ll_table_log.valid := !ll_table_log_fired && (dicBuilderState === sLookup) when (io.ll_table_log.fire) { ll_table_log_fired := true.B } val print_table = RegInit(true.B) val write_header_started = RegInit(false.B) val nbBits = RegInit(0.U(32.W)) val remaining = RegInit(0.U(32.W)) val threshold = RegInit(0.U(32.W)) val symbol = RegInit(0.U(32.W)) val alphabetSize = ll_max_symbol_value + 1.U val previousIs0 = RegInit(false.B) val bitStream = RegInit(0.U(64.W)) val bitCount = RegInit(0.U(7.W)) val writeBitStream = RegInit(false.B) // TODO : optimize to write & update bitStream at the same time val start = RegInit(0.U(32.W)) val start_initialized = RegInit(false.B) val skip_zeros_done = RegInit(false.B) val skip_24_done = RegInit(false.B) val skip_3_done = RegInit(false.B) val writeBitStreamPrev0 = RegInit(false.B) val FSE_MIN_TABLELOG = 5 io.header_writes.valid := false.B io.header_writes.bits.data := 0.U io.header_writes.bits.validbytes := 0.U io.header_writes.bits.end_of_message := false.B val shifted_thresholds = WireInit(VecInit(Seq.fill(tableLogLL+1)(0.U(32.W)))) shifted_thresholds(0) := threshold for (i <- 1 until tableLogLL + 1) { shifted_thresholds(i) := shifted_thresholds(i-1) >> 1.U } val shifted_threshold_small_or_eq_remaining = WireInit(VecInit(Seq.fill(tableLogLL+1)(0.U(32.W)))) val nxt_shifted_threshold_idx = shifted_threshold_small_or_eq_remaining.reduce(_ + _) io.lookup_done.ready := true.B when (io.lookup_done.valid) { for (i <- 0 until maxSymbolLL+1) { ll_count(i) := 0.U } ll_max_symbol_value := 0.U ll_nbseq_1 := 0.U for (i <- 0 until maxSymbolLL + 1) { ll_normalizedCounterReg(i) := 0.U } for (i <- 0 until LL_TABLESIZE) { ll_tableSymbol(i) := 0.U } ll_highThresholdAfterCumul := 0.U for (i <- 0 until maxSymbolLL + 1) { ll_cumulReg(i) := 0.U } for (i <- 0 until LL_SPREAD_TABLE_SIZE) { ll_spread(i) := 0.U } ll_pos := 0.U ll_s := 0.U ll_sv := 0.U for (i <- 0 until LL_TABLESIZE) { ll_tableU16(i) := 0.U } for (i <- 0 until maxSymbolLL+ 1) { ll_symbolTTDeltaNbBits(i) := 0.U ll_symbolTTDeltaFindState(i) := 0.S } ll_total := 0.U ll_table_log_fired := false.B fse_normalize_corner_case_reg := false.B print_table := true.B write_header_started := false.B nbBits := 0.U remaining := 0.U threshold := 0.U symbol := 0.U previousIs0 := false.B bitStream := 0.U bitCount := 0.U writeBitStream := false.B start := 0.U start_initialized := false.B skip_zeros_done := false.B skip_24_done := false.B skip_3_done := false.B writeBitStreamPrev0 := false.B } switch (dicBuilderState) { is (sIdle) { when (io.ll_stream.output_valid && io.nb_seq.valid) { dicBuilderState := sCount } } is (sCount) { io.ll_stream.output_ready := predefined_mode_q.io.enq.ready io.ll_stream.user_consumed_bytes := Mux(io.ll_stream.available_output_bytes < COLLECT_STAT_PROCESS_BYTES.U, io.ll_stream.available_output_bytes, COLLECT_STAT_PROCESS_BYTES.U) when (io.ll_stream.output_valid) { for (i <- 0 until maxSymbolLL + 1) { ll_count(i) := ll_count(i) + stat_sum(i) } ll_max_symbol_value := Mux(ll_max_symbol_value > cur_max_value, ll_max_symbol_value, cur_max_value) } when (predefined_mode_q.io.enq.ready && io.ll_stream.output_valid && io.ll_stream.output_last_chunk && (io.ll_stream.user_consumed_bytes === io.ll_stream.available_output_bytes)) { // zstd_compress_sequences.c 271 // if (count[codeTable[nbSeq-1]] > 1) { // count[codeTable[nbSeq-1]]--; // nbSeq_1--; // } if (as_zstd_submodule) { val ll_last_codetable = input_ll_symbols(io.ll_stream.user_consumed_bytes - 1.U) val ll_count_last_codetable = ll_count(ll_last_codetable) val ll_last_statcount = stat_sum(ll_last_codetable) val ll_last_count = ll_count_last_codetable + ll_last_statcount val do_subtract = ll_last_count > 1.U ll_nbseq_1 := Mux(do_subtract, io.nb_seq.bits - 1.U, io.nb_seq.bits) ll_count(ll_last_codetable) := Mux(do_subtract, ll_last_count - 1.U, ll_last_count) } else { ll_nbseq_1 := io.nb_seq.bits } when (!use_predefined_mode) { dicBuilderState := sNormalizeCount } .otherwise { // TODO : set io.ll_stream.output_ready to true & move on to sLookup without going through sCount dicBuilderState := sLookup predefined_mode_q.io.enq.valid := true.B predefined_mode_q.io.enq.bits := true.B if (printInfo == "LL") { for (i <- 0 until 36) { ll_symbolTTDeltaNbBits(i) := LL_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := LL_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 64) { ll_tableU16(i) := LL_DefaultTableU16(i).U } } else if (printInfo == "ML") { for (i <- 0 until 53) { ll_symbolTTDeltaNbBits(i) := ML_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := ML_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 64) { ll_tableU16(i) := ML_DefaultTableU16(i).U } } else if (printInfo == "OF") { for (i <- 0 until 29) { ll_symbolTTDeltaNbBits(i) := OF_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := OF_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 32) { ll_tableU16(i) := OF_DefaultTableU16(i).U } } } } } is (sNormalizeCount) { CompressAccelLogger.logInfo(printInfo + "ll_nbseq_1: %d\n", ll_nbseq_1) for (i <- 0 until maxSymbolLL + 1) { ll_normalizedCounterReg(i) := ll_normalizedCounterMaxAdjusted(i) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_proba_base(%d): %d\n", i.U, ll_proba_base(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_proba(%d): %d\n", i.U, ll_proba(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_proba(%d): %d\n", i.U, ll_proba(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounter(%d): %d\n", i.U, ll_normalizedCounter(i)) } CompressAccelLogger.logInfo(printInfo + " ll_lowThreshold: %d\n", ll_lowThreshold) CompressAccelLogger.logInfo(printInfo + " ll_lowProbCount: %d\n", ll_lowProbCount) // Takes only one cycle when (predefined_mode_q.io.enq.ready) { when (fse_normalize_corner_case) { dicBuilderState := sLookup if (printInfo == "LL") { for (i <- 0 until 36) { ll_symbolTTDeltaNbBits(i) := LL_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := LL_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 64) { ll_tableU16(i) := LL_DefaultTableU16(i).U } } else if (printInfo == "ML") { for (i <- 0 until 53) { ll_symbolTTDeltaNbBits(i) := ML_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := ML_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 64) { ll_tableU16(i) := ML_DefaultTableU16(i).U } } else if (printInfo == "OF") { for (i <- 0 until 29) { ll_symbolTTDeltaNbBits(i) := OF_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := OF_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 32) { ll_tableU16(i) := OF_DefaultTableU16(i).U } } } .otherwise { dicBuilderState := sBuildCTableSymbolStartPositions } } } is (sBuildCTableSymbolStartPositions) { ll_normCountEqsNegOneCumul(0) := ll_normCountEqsNegOne(0) for (i <- 1 until maxSymbolLL + 1) { when (ll_normalizedCounterReg(i-1) === neg_one_uint16.U) { ll_normCountEqsNegOne(i-1) := 1.U ll_cumul(i) := ll_cumul(i-1) + 1.U ll_tableSymbol(ll_highThresholdBeforeCumul - ll_normCountEqsNegOneCumul(i-1) + 1.U) := (i-1).U } .otherwise { ll_cumul(i) := ll_cumul(i-1) + ll_normalizedCounterReg(i-1) } ll_normCountEqsNegOneCumul(i) := ll_normCountEqsNegOneCumul(i-1) + ll_normCountEqsNegOne(i) } ll_cumul(ll_maxSV1) := ll_tableSize + 1.U ll_highThresholdAfterCumul := ll_highThresholdBeforeCumul - ll_normCountEqsNegOneSum for (i <- 0 until maxSymbolLL + 1) { ll_cumulReg(i) := ll_cumul(i) } // Takes only one cycle dicBuilderState := sBuildCTableSpreadSymbols } is (sBuildCTableSpreadSymbols) { when (ll_highThresholdAfterCumul === ll_tableSize - 1.U) { ll_s := ll_s + 1.U ll_sv := ll_sv + add.U val n = ll_normalizedCounterReg(ll_s) val write_spread_cnt = n >> 3.U val write_extra = (n & 7.U) =/= 0.U val write_spread_cnt_wrapped = write_spread_cnt +& write_extra.asUInt val write_spread_bytes = write_spread_cnt_wrapped << 3.U ll_pos := ll_pos + n // pos + n for (i <- 0 until LL_SPREAD_TABLE_SIZE) { when ((i.U >= ll_pos) && (i.U < ll_pos + write_spread_bytes)) { val shift_bytes = (i.U - ll_pos)(2, 0) val shift_bits = shift_bytes << 3.U ll_spread(i) := ll_sv >> shift_bits } } when (ll_s === ll_maxSV1) { for (i <- 0 until LL_TABLESIZE) { val uPosition = (i.U * ll_fse_tablestep) & ll_tableMask when ((i.U >= ll_pos) && (i.U < ll_pos + write_spread_bytes)) { val shift_bytes = (i.U - ll_pos)(2, 0) val shift_bits = shift_bytes << 3.U ll_tableSymbol(uPosition) := ll_sv >> shift_bits } .otherwise { ll_tableSymbol(uPosition) := ll_spread(i) } } dicBuilderState := sBuildCTableBuildTable ll_s := 0.U } } .otherwise { CompressAccelLogger.logInfo(printInfo + " Doesn't support low probability cases") assert(false.B, "Doesn't support low probability cases") } } is (sBuildCTableBuildTable) { // 2^tableLogLL cycles ll_s := ll_s + 1.U val s = ll_tableSymbol(ll_s) ll_cumulReg(s) := ll_cumulReg(s) + 1.U ll_tableU16(ll_cumulReg(s)) := ll_tableSize + ll_s when (ll_s === ll_tableSize - 1.U) { ll_s := 0.U dicBuilderState := sBuildCTableSymbolTT } } is (sBuildCTableSymbolTT) { ll_s := ll_s + 1.U when (normCount === 0.U) { ll_symbolTTDeltaNbBits(ll_s) := (((tableLogLL + 1) << 16) - (1 << tableLogLL)).U ll_symbolTTDeltaFindState(ll_s) := 0.S } .elsewhen (normCount === 1.U) { // ignore low-prob (normCount === -1.S) for now ll_symbolTTDeltaNbBits(ll_s) := (((tableLogLL) << 16) - (1 << tableLogLL)).U ll_symbolTTDeltaFindState(ll_s) := (ll_total - 1.U).asSInt ll_total := ll_total + 1.U } .otherwise { val maxBitsOut = tableLogLL.U - BIT_highbit32(normCount - 1.U) val minStatePlus = normCount << maxBitsOut(3, 0) ll_symbolTTDeltaNbBits(ll_s) := (maxBitsOut << 16.U) - minStatePlus ll_symbolTTDeltaFindState(ll_s) := (ll_total - normCount).asSInt ll_total := ll_total + normCount } when (ll_s === ll_max_symbol_value) { ll_s := 0.U dicBuilderState := sWriteCTable } } is (sWriteCTable) { when (!write_header_started) { write_header_started := true.B remaining := ll_tableSize + 1.U threshold := ll_tableSize nbBits := (tableLogLL + 1).U bitStream := (tableLogLL - FSE_MIN_TABLELOG).U bitCount := 4.U } .otherwise { when ((symbol < alphabetSize) && (remaining > 1.U)) { when(writeBitStream) { when (io.header_writes.ready) { writeBitStream := false.B bitStream := bitStream >> 16.U bitCount := bitCount - 16.U CompressAccelLogger.logInfo(printInfo + " bitStream(7, 0): %d\n", bitStream(7, 0)) CompressAccelLogger.logInfo(printInfo + " bitStream(15, 8): %d\n", bitStream(15, 8)) } io.header_writes.valid := true.B io.header_writes.bits.data := bitStream io.header_writes.bits.validbytes := 2.U } .elsewhen (writeBitStreamPrev0) { when (io.header_writes.ready) { writeBitStreamPrev0 := false.B bitStream := bitStream >> 16.U CompressAccelLogger.logInfo(printInfo + "writeBitStreamPrev0") } io.header_writes.valid := true.B io.header_writes.bits.data := bitStream io.header_writes.bits.validbytes := 2.U } .elsewhen (previousIs0) { when (!start_initialized) { start := symbol start_initialized := true.B CompressAccelLogger.logInfo(printInfo + " start: %d\n", symbol) } .elsewhen (!skip_zeros_done) { val cur_norm_count = ll_normalizedCounterReg(symbol) when (cur_norm_count =/= 0.U) { skip_zeros_done := true.B CompressAccelLogger.logInfo(printInfo + " symbol: %d\n", symbol) } .otherwise { symbol := symbol + 1.U when ((symbol + 1.U) === alphabetSize) { assert(false.B, printInfo + " Wrong distribution for FSE compression\n"); } } } .elsewhen (!skip_24_done) { when (symbol >= start + 24.U) { start := start + 24.U bitStream := bitStream + (BigInt("FFFF", 16).U << bitCount) writeBitStreamPrev0 := true.B } .otherwise { skip_24_done := true.B CompressAccelLogger.logInfo(printInfo + " skip_24_done\n") } CompressAccelLogger.logInfo(printInfo + " skip_24\n") } .elsewhen (!skip_3_done) { when (symbol >= start + 3.U) { start := start + 3.U bitStream := bitStream + (3.U << bitCount) bitCount := bitCount + 2.U } .otherwise { skip_3_done := true.B CompressAccelLogger.logInfo(printInfo + " skip_3_done\n") } CompressAccelLogger.logInfo(printInfo + " skip_3\n") } .otherwise { bitStream := bitStream + ((symbol - start) << bitCount) bitCount := bitCount + 2.U previousIs0 := false.B start := 0.U start_initialized := false.B skip_zeros_done := false.B skip_24_done := false.B skip_3_done := false.B when (bitCount > 16.U) { writeBitStream := true.B } CompressAccelLogger.logInfo(printInfo + " previousIs0_done\n") } } .otherwise { val count = ll_normalizedCounterReg(symbol) symbol := symbol + 1.U val max = ((threshold << 1.U) - 1.U) - remaining // fse_compress.c 327 ????? // remaining := remaining - Mux(count < 0.S, (-1.S)count, count) val nxt_remaining = remaining - count remaining := nxt_remaining val count1 = count + 1.U val count1_max = Mux(count1 >= threshold, count1 + max, count1) val nxt_bitCount = bitCount + nbBits - Mux(count1_max < max, 1.U, 0.U) bitStream := bitStream + (count1_max << bitCount) bitCount := nxt_bitCount writeBitStream := nxt_bitCount > 16.U previousIs0 := (count1_max === 1.U) assert(remaining >= 1.U, "Not enough remaining for FSE header writes\n") CompressAccelLogger.logInfo(printInfo + " previousIs0: %d\n", (count1_max === 1.U)) CompressAccelLogger.logInfo(printInfo + " alphabetSize: %d\n", alphabetSize) CompressAccelLogger.logInfo(printInfo + " symbol: %d\n", symbol) CompressAccelLogger.logInfo(printInfo + " threshold: %d\n", threshold) CompressAccelLogger.logInfo(printInfo + " max: %d\n", max) CompressAccelLogger.logInfo(printInfo + " remaining: %d\n", remaining) CompressAccelLogger.logInfo(printInfo + " nxt_remaining: %d\n", nxt_remaining) CompressAccelLogger.logInfo(printInfo + " count: %d\n", count) CompressAccelLogger.logInfo(printInfo + " count1_max: %d\n", count1_max) CompressAccelLogger.logInfo(printInfo + " nxt_bitCount: %d\n", nxt_bitCount) CompressAccelLogger.logInfo(printInfo + " writeBitStream: %d\n", writeBitStream) CompressAccelLogger.logInfo(printInfo + " BitStream: 0x%x\n", (bitStream + (count1_max << bitCount))) for (i <- 0 until tableLogLL + 1) { shifted_threshold_small_or_eq_remaining(i) := Mux(nxt_remaining < shifted_thresholds(i), 1.U, 0.U) } threshold := shifted_thresholds(nxt_shifted_threshold_idx) nbBits := nbBits - nxt_shifted_threshold_idx } } .otherwise { io.header_writes.valid := true.B io.header_writes.bits.data := bitStream io.header_writes.bits.validbytes := ((bitCount + 7.U) >> 3.U) if (mark_end_of_header) { io.header_writes.bits.end_of_message := true.B } when (io.header_writes.ready) { dicBuilderState := sLookup bitStream := 0.U bitCount := 0.U } } } } is (sLookup) { when (print_table) { print_table := false.B // for (i <- 0 until maxSymbolLL + 1) { // CompressAccelLogger.logInfo(printInfo + " ll_count(%d): %d\n", i.U, ll_count(i)) // } CompressAccelLogger.logInfo(printInfo + " ll_max_symbol_value: %d\n", ll_max_symbol_value) for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounterReg(%d): %d\n", i.U, ll_normalizedCounterReg(i)) } for (i <- 0 until LL_TABLESIZE) { CompressAccelLogger.logInfo(printInfo + " ll_tableSymbol(%d): %d\n", i.U, ll_tableSymbol(i)) } CompressAccelLogger.logInfo(printInfo + " ll_highThresholdAfterCumul: %d\n", ll_highThresholdAfterCumul) for (i <- 0 until LL_SPREAD_TABLE_SIZE) { CompressAccelLogger.logInfo(printInfo + " ll_spread(%d): %d\n", i.U, ll_spread(i)) } CompressAccelLogger.logInfo(printInfo + " ll_fse_tablestep: %d\n", ll_fse_tablestep) for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " symbolTTDeltaNbBits(%d): %d, ll_symbolTTDeltaFindState(%d): %d\n", i.U, ll_symbolTTDeltaNbBits(i), i.U, ll_symbolTTDeltaFindState(i).asSInt) } for (i <- 0 until (1 << tableLogLL)) { CompressAccelLogger.logInfo(printInfo + " ll_tableU16(%d): %d\n", i.U, ll_tableU16(i)) } } when (io.lookup_done.valid) { io.nb_seq.ready := true.B dicBuilderState := sIdle } } } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /* Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File Util.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants object CompressAccelLogger { def logInfo(format: String, args: Bits)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_)) } def logCritical(format: String, args: Bits)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U if (p(CompressAccelPrintfEnable)) { printf(midas.targetutils.SynthesizePrintf("cy: %d, ", loginfo_cycles)) printf(midas.targetutils.SynthesizePrintf(format, args:_)) } else { printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_)) } } def logWaveStyle(format: String, args: Bits)(implicit p: Parameters) { } } object CompressAccelParams { }	module FSECompressorDicBuilder_2( // @[FSECompressorDicBuilder.scala:39:7] input clock, // @[FSECompressorDicBuilder.scala:39:7] input reset, // @[FSECompressorDicBuilder.scala:39:7] output io_nb_seq_ready, // @[FSECompressorDicBuilder.scala:48:14] input io_nb_seq_valid, // @[FSECompressorDicBuilder.scala:48:14] input [63:0] io_nb_seq_bits, // @[FSECompressorDicBuilder.scala:48:14] output [5:0] io_ll_stream_user_consumed_bytes, // @[FSECompressorDicBuilder.scala:48:14] input [5:0] io_ll_stream_available_output_bytes, // @[FSECompressorDicBuilder.scala:48:14] input io_ll_stream_output_valid, // @[FSECompressorDicBuilder.scala:48:14] output io_ll_stream_output_ready, // @[FSECompressorDicBuilder.scala:48:14] input [255:0] io_ll_stream_output_data, // @[FSECompressorDicBuilder.scala:48:14] input io_ll_stream_output_last_chunk, // @[FSECompressorDicBuilder.scala:48:14] input io_ll_table_log_ready, // @[FSECompressorDicBuilder.scala:48:14] output io_ll_table_log_valid, // @[FSECompressorDicBuilder.scala:48:14] output [3:0] io_ll_table_log_bits, // @[FSECompressorDicBuilder.scala:48:14] output io_symbol_info_0_ready, // @[FSECompressorDicBuilder.scala:48:14] input io_symbol_info_0_valid, // @[FSECompressorDicBuilder.scala:48:14] input [7:0] io_symbol_info_0_bits_symbol, // @[FSECompressorDicBuilder.scala:48:14] input io_symbol_info_0_bits_last_symbol, // @[FSECompressorDicBuilder.scala:48:14] input io_symbolTT_info_0_ready, // @[FSECompressorDicBuilder.scala:48:14] output io_symbolTT_info_0_valid, // @[FSECompressorDicBuilder.scala:48:14] output [31:0] io_symbolTT_info_0_bits_nbbit, // @[FSECompressorDicBuilder.scala:48:14] output [31:0] io_symbolTT_info_0_bits_findstate, // @[FSECompressorDicBuilder.scala:48:14] output io_symbolTT_info_0_bits_from_last_symbol, // @[FSECompressorDicBuilder.scala:48:14] input [15:0] io_state_table_idx_0, // @[FSECompressorDicBuilder.scala:48:14] output io_new_state_0_valid, // @[FSECompressorDicBuilder.scala:48:14] output [15:0] io_new_state_0_bits, // @[FSECompressorDicBuilder.scala:48:14] input io_header_writes_ready, // @[FSECompressorDicBuilder.scala:48:14] output io_header_writes_valid, // @[FSECompressorDicBuilder.scala:48:14] output [255:0] io_header_writes_bits_data, // @[FSECompressorDicBuilder.scala:48:14] output [5:0] io_header_writes_bits_validbytes, // @[FSECompressorDicBuilder.scala:48:14] output io_header_writes_bits_end_of_message, // @[FSECompressorDicBuilder.scala:48:14] input io_predefined_mode_ready, // @[FSECompressorDicBuilder.scala:48:14] output io_predefined_mode_valid, // @[FSECompressorDicBuilder.scala:48:14] output io_predefined_mode_bits, // @[FSECompressorDicBuilder.scala:48:14] input io_lookup_done_valid // @[FSECompressorDicBuilder.scala:48:14] ); wire [15:0] ll_normalizedCounter_30; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_29; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_28; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_27; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_26; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_25; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_24; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_23; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_22; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_21; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_20; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_19; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_18; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_17; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_16; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_15; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_14; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_13; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_12; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_11; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_10; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_9; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_8; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_7; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_6; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_5; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_4; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_3; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_2; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_1; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_0; // @[FSECompressorDicBuilder.scala:277:38] wire _predefined_mode_q_io_enq_ready; // @[FSECompressorDicBuilder.scala:141:33] wire io_nb_seq_valid_0 = io_nb_seq_valid; // @[FSECompressorDicBuilder.scala:39:7] wire [63:0] io_nb_seq_bits_0 = io_nb_seq_bits; // @[FSECompressorDicBuilder.scala:39:7] wire [5:0] io_ll_stream_available_output_bytes_0 = io_ll_stream_available_output_bytes; // @[FSECompressorDicBuilder.scala:39:7] wire io_ll_stream_output_valid_0 = io_ll_stream_output_valid; // @[FSECompressorDicBuilder.scala:39:7] wire [255:0] io_ll_stream_output_data_0 = io_ll_stream_output_data; // @[FSECompressorDicBuilder.scala:39:7] wire io_ll_stream_output_last_chunk_0 = io_ll_stream_output_last_chunk; // @[FSECompressorDicBuilder.scala:39:7] wire io_ll_table_log_ready_0 = io_ll_table_log_ready; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbol_info_0_valid_0 = io_symbol_info_0_valid; // @[FSECompressorDicBuilder.scala:39:7] wire [7:0] io_symbol_info_0_bits_symbol_0 = io_symbol_info_0_bits_symbol; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbol_info_0_bits_last_symbol_0 = io_symbol_info_0_bits_last_symbol; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbolTT_info_0_ready_0 = io_symbolTT_info_0_ready; // @[FSECompressorDicBuilder.scala:39:7] wire [15:0] io_state_table_idx_0_0 = io_state_table_idx_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_header_writes_ready_0 = io_header_writes_ready; // @[FSECompressorDicBuilder.scala:39:7] wire io_predefined_mode_ready_0 = io_predefined_mode_ready; // @[FSECompressorDicBuilder.scala:39:7] wire io_lookup_done_valid_0 = io_lookup_done_valid; // @[FSECompressorDicBuilder.scala:39:7] wire [31:0] _rtbTable_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_7 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _ll_count_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_7 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_8 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_9 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_10 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_11 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_12 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_13 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_14 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_15 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_16 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_17 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_18 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_19 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_20 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_21 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_22 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_23 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_24 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_25 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_26 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_27 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_28 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_29 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_30 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_31 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_7 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_8 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_9 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_10 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_11 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_12 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_13 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_14 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_15 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_16 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_17 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_18 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_19 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_20 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_21 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_22 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_23 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_24 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_25 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_26 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_27 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_28 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_29 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_30 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_31 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_7 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_8 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_9 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_10 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_11 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_12 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_13 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_14 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_15 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_16 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_17 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_18 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_19 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_20 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_21 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_22 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_23 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_24 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_25 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_26 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_27 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_28 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_29 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_30 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_31 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _shifted_thresholds_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire io_lookup_done_ready = 1'h1; // @[FSECompressorDicBuilder.scala:39:7] wire io_lookup_done_bits = 1'h1; // @[FSECompressorDicBuilder.scala:39:7] wire [6:0] _ll_cumul_T_1 = 7'h41; // @[FSECompressorDicBuilder.scala:703:43] wire [6:0] _remaining_T_1 = 7'h41; // @[FSECompressorDicBuilder.scala:793:35] wire [31:0] _maxBitsOut_highBit_T_46 = 32'hAAAAAAAA; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_41 = 32'h55555555; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_40 = 32'h66666666; // @[FSECompressorDicBuilder.scala:52:49] wire [30:0] _maxBitsOut_highBit_T_39 = 31'h33333333; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_36 = 32'hCCCCCCCC; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_31 = 32'h33333333; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_30 = 32'h3C3C3C3C; // @[FSECompressorDicBuilder.scala:52:49] wire [29:0] _maxBitsOut_highBit_T_29 = 30'hF0F0F0F; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_26 = 32'hF0F0F0F0; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_21 = 32'hF0F0F0F; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_20 = 32'hFF00FF0; // @[FSECompressorDicBuilder.scala:52:49] wire [27:0] _maxBitsOut_highBit_T_19 = 28'hFF00FF; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_16 = 32'hFF00FF00; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_11 = 32'hFF00FF; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_10 = 32'hFFFF00; // @[FSECompressorDicBuilder.scala:52:49] wire [23:0] _maxBitsOut_highBit_T_9 = 24'hFFFF; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T = 32'hFFFF0000; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_6 = 32'hFFFF0000; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_1 = 32'hFFFF; // @[FSECompressorDicBuilder.scala:52:49] wire _table_WIRE_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_1_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_1_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_1_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_1_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_2_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_2_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_2_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_2_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_3_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_3_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_3_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_3_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_4_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_4_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_4_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_4_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_5_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_5_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_5_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_5_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_6_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_6_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_6_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_6_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_7_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_7_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_7_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_7_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_8_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_8_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_8_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_8_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_9_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_9_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_9_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_9_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_10_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_10_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_10_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_10_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_11_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_11_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_11_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_11_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_12_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_12_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_12_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_12_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_13_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_13_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_13_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_13_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_14_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_14_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_14_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_14_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_15_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_15_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_15_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_15_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_16_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_16_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_16_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_16_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_17_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_17_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_17_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_17_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_18_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_18_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_18_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_18_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_19_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_19_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_19_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_19_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_20_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_20_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_20_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_20_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_21_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_21_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_21_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_21_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_22_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_22_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_22_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_22_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_23_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_23_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_23_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_23_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_24_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_24_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_24_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_24_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_25_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_25_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_25_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_25_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_26_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_26_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_26_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_26_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_27_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_27_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_27_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_27_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_28_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_28_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_28_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_28_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_29_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_29_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_29_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_29_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_30_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_30_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_30_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_30_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_31_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_31_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_31_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_31_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _has_value_WIRE_0 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_1 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_2 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_3 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_4 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_5 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_6 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_7 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_8 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_9 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_10 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_11 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_12 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_13 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_14 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_15 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_16 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_17 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_18 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_19 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_20 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_21 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_22 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_23 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_24 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_25 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_26 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_27 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_28 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_29 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_30 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_31 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _symbolTT_lookup_fire_and_last_vec_WIRE_0 = 1'h0; // @[FSECompressorDicBuilder.scala:422:59] wire [12:0] uPosition_63 = 13'h15; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_63 = 13'hA95; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_62 = 13'h2A; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_62 = 13'hA6A; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_61 = 13'h3F; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_61 = 13'hA3F; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_60 = 13'h14; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_60 = 13'hA14; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_59 = 13'h29; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_59 = 13'h9E9; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_58 = 13'h3E; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_58 = 13'h9BE; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_57 = 13'h13; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_57 = 13'h993; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_56 = 13'h28; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_56 = 13'h968; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_55 = 13'h3D; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_55 = 13'h93D; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_54 = 13'h12; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_54 = 13'h912; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_53 = 13'h27; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_53 = 13'h8E7; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_52 = 13'h3C; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_52 = 13'h8BC; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_51 = 13'h11; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_51 = 13'h891; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_50 = 13'h26; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_50 = 13'h866; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_49 = 13'h3B; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_49 = 13'h83B; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_48 = 13'h10; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_48 = 13'h810; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_47 = 13'h25; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_47 = 13'h7E5; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_46 = 13'h3A; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_46 = 13'h7BA; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_45 = 13'hF; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_45 = 13'h78F; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_44 = 13'h24; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_44 = 13'h764; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_43 = 13'h39; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_43 = 13'h739; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_42 = 13'hE; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_42 = 13'h70E; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_41 = 13'h23; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_41 = 13'h6E3; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_40 = 13'h38; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_40 = 13'h6B8; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_39 = 13'hD; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_39 = 13'h68D; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_38 = 13'h22; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_38 = 13'h662; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_37 = 13'h37; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_37 = 13'h637; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_36 = 13'hC; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_36 = 13'h60C; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_35 = 13'h21; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_35 = 13'h5E1; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_34 = 13'h36; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_34 = 13'h5B6; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_33 = 13'hB; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_33 = 13'h58B; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_32 = 13'h20; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_32 = 13'h560; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_31 = 12'h35; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_31 = 12'h535; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_30 = 12'hA; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_30 = 12'h50A; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_29 = 12'h1F; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_29 = 12'h4DF; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_28 = 12'h34; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_28 = 12'h4B4; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_27 = 12'h9; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_27 = 12'h489; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_26 = 12'h1E; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_26 = 12'h45E; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_25 = 12'h33; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_25 = 12'h433; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_24 = 12'h8; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_24 = 12'h408; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_23 = 12'h1D; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_23 = 12'h3DD; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_22 = 12'h32; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_22 = 12'h3B2; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_21 = 12'h7; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_21 = 12'h387; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_20 = 12'h1C; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_20 = 12'h35C; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_19 = 12'h31; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_19 = 12'h331; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_18 = 12'h6; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_18 = 12'h306; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_17 = 12'h1B; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_17 = 12'h2DB; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_16 = 12'h30; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_16 = 12'h2B0; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_15 = 11'h5; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_15 = 11'h285; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_14 = 11'h1A; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_14 = 11'h25A; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_13 = 11'h2F; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_13 = 11'h22F; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_12 = 11'h4; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_12 = 11'h204; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_11 = 11'h19; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_11 = 11'h1D9; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_10 = 11'h2E; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_10 = 11'h1AE; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_9 = 11'h3; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_9 = 11'h183; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_8 = 11'h18; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_8 = 11'h158; // @[FSECompressorDicBuilder.scala:736:34] wire [9:0] uPosition_7 = 10'h2D; // @[FSECompressorDicBuilder.scala:736:54] wire [9:0] _uPosition_T_7 = 10'h12D; // @[FSECompressorDicBuilder.scala:736:34] wire [9:0] uPosition_6 = 10'h2; // @[FSECompressorDicBuilder.scala:736:54] wire [9:0] _uPosition_T_6 = 10'h102; // @[FSECompressorDicBuilder.scala:736:34] wire [9:0] uPosition_5 = 10'h17; // @[FSECompressorDicBuilder.scala:736:54] wire [9:0] _uPosition_T_5 = 10'hD7; // @[FSECompressorDicBuilder.scala:736:34] wire [9:0] uPosition_4 = 10'h2C; // @[FSECompressorDicBuilder.scala:736:54] wire [9:0] _uPosition_T_4 = 10'hAC; // @[FSECompressorDicBuilder.scala:736:34] wire [8:0] uPosition_3 = 9'h1; // @[FSECompressorDicBuilder.scala:736:54] wire [8:0] _uPosition_T_3 = 9'h81; // @[FSECompressorDicBuilder.scala:736:34] wire [8:0] uPosition_2 = 9'h16; // @[FSECompressorDicBuilder.scala:736:54] wire [8:0] _uPosition_T_2 = 9'h56; // @[FSECompressorDicBuilder.scala:736:34] wire [7:0] _ll_fse_tablestep_T_4 = 8'h2B; // @[FSECompressorDicBuilder.scala:405:72] wire [7:0] _uPosition_T_1 = 8'h2B; // @[FSECompressorDicBuilder.scala:736:34] wire [7:0] uPosition_1 = 8'h2B; // @[FSECompressorDicBuilder.scala:736:54] wire [7:0] _input_ll_symbols_WIRE_0 = 8'h0; // @[FSECompressorDicBuilder.scala:172:42] wire [7:0] _input_ll_symbols_WIRE_1 = 8'h0; // @[FSECompressorDicBuilder.scala:172:42] wire [7:0] _input_ll_symbols_WIRE_2 = 8'h0; // @[FSECompressorDicBuilder.scala:172:42] wire [7:0] _input_ll_symbols_WIRE_3 = 8'h0; // @[FSECompressorDicBuilder.scala:172:42] wire [7:0] _ll_tableSymbol_WIRE_0 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_1 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_2 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_3 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_4 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_5 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_6 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_7 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_8 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_9 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_10 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_11 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_12 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_13 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_14 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_15 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_16 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_17 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_18 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_19 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_20 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_21 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_22 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_23 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_24 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_25 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_26 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_27 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_28 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_29 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_30 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_31 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_32 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_33 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_34 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_35 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_36 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_37 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_38 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_39 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_40 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_41 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_42 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_43 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_44 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_45 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_46 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_47 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_48 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_49 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_50 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_51 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_52 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_53 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_54 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_55 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_56 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_57 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_58 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_59 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_60 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_61 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_62 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_63 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_normCountEqsNegOne_WIRE_0 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_1 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_2 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_3 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_4 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_5 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_6 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_7 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_8 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_9 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_10 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_11 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_12 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_13 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_14 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_15 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_16 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_17 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_18 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_19 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_20 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_21 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_22 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_23 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_24 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_25 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_26 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_27 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_28 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_29 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_30 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_31 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] ll_normCountEqsNegOne_31 = 8'h0; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_0 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_1 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_2 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_3 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_4 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_5 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_6 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_7 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_8 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_9 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_10 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_11 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_12 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_13 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_14 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_15 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_16 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_17 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_18 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_19 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_20 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_21 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_22 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_23 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_24 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_25 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_26 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_27 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_28 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_29 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_30 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_31 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_spread_WIRE_0 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_1 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_2 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_3 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_4 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_5 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_6 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_7 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_8 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_9 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_10 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_11 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_12 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_13 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_14 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_15 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_16 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_17 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_18 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_19 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_20 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_21 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_22 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_23 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_24 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_25 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_26 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_27 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_28 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_29 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_30 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_31 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_32 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_33 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_34 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_35 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_36 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_37 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_38 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_39 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_40 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_41 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_42 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_43 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_44 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_45 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_46 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_47 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_48 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_49 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_50 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_51 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_52 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_53 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_54 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_55 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_56 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_57 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_58 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_59 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_60 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_61 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_62 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_63 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_64 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_65 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_66 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_67 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_68 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_69 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_70 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_71 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _uPosition_T = 8'h0; // @[FSECompressorDicBuilder.scala:736:34] wire [7:0] uPosition = 8'h0; // @[FSECompressorDicBuilder.scala:736:54] wire [15:0] _ll_proba_base_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_normalizedCounter_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterIdx_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] ll_normalizedCounterIdx_0 = 16'h0; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] _ll_normalizedCounterReg_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_cumul_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumulReg_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_tableU16_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_32 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_33 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_34 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_35 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_36 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_37 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_38 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_39 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_40 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_41 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_42 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_43 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_44 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_45 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_46 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_47 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_48 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_49 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_50 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_51 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_52 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_53 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_54 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_55 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_56 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_57 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_58 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_59 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_60 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_61 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_62 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_63 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [6:0] ll_fse_tablestep = 7'h2B; // @[FSECompressorDicBuilder.scala:405:72] wire [6:0] _ll_fse_tablestep_T_3 = 7'h28; // @[FSECompressorDicBuilder.scala:405:48] wire [7:0] _ll_fse_tablestep_T_2 = 8'h28; // @[FSECompressorDicBuilder.scala:405:48] wire [31:0] ll_highThresholdBeforeCumul = 32'h3F; // @[FSECompressorDicBuilder.scala:385:45] wire [6:0] ll_tableMask = 7'h3F; // @[FSECompressorDicBuilder.scala:381:35] wire [6:0] _ll_highThresholdBeforeCumul_T_1 = 7'h3F; // @[FSECompressorDicBuilder.scala:386:47] wire [15:0] ll_normalizedCounterIdx_31 = 16'h1F; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_30 = 16'h1E; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_29 = 16'h1D; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_28 = 16'h1C; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_27 = 16'h1B; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_26 = 16'h1A; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_25 = 16'h19; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_24 = 16'h18; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_23 = 16'h17; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_22 = 16'h16; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_21 = 16'h15; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_20 = 16'h14; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_19 = 16'h13; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_18 = 16'h12; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_17 = 16'h11; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_16 = 16'h10; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_15 = 16'hF; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_14 = 16'hE; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_13 = 16'hD; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_12 = 16'hC; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_11 = 16'hB; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_10 = 16'hA; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_9 = 16'h9; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_8 = 16'h8; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_7 = 16'h7; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_6 = 16'h6; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_5 = 16'h5; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_4 = 16'h4; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_3 = 16'h3; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_2 = 16'h2; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_1 = 16'h1; // @[FSECompressorDicBuilder.scala:301:41] wire [63:0] ll_vStep = 64'h1000000000; // @[FSECompressorDicBuilder.scala:257:22] wire [127:0] _ll_vStep_T = 128'h1000000000; // @[FSECompressorDicBuilder.scala:258:19] wire [6:0] ll_scale_20 = 7'h24; // @[FSECompressorDicBuilder.scala:255:25] wire [6:0] _ll_scale_20_T_1 = 7'h24; // @[FSECompressorDicBuilder.scala:256:27] wire [7:0] _ll_scale_20_T = 8'h24; // @[FSECompressorDicBuilder.scala:256:27] wire [6:0] ll_scale = 7'h38; // @[FSECompressorDicBuilder.scala:251:22] wire [6:0] _ll_scale_T = 7'h38; // @[FSECompressorDicBuilder.scala:252:20] wire [5:0] _ll_scale_T_1 = 6'h38; // @[FSECompressorDicBuilder.scala:252:20] wire [7:0] _ll_cumul_T = 8'h41; // @[FSECompressorDicBuilder.scala:703:43] wire [7:0] _remaining_T = 8'h41; // @[FSECompressorDicBuilder.scala:793:35] wire [6:0] _ll_fse_tablestep_T_1 = 7'h8; // @[FSECompressorDicBuilder.scala:405:64] wire [6:0] _ll_fse_tablestep_T = 7'h20; // @[FSECompressorDicBuilder.scala:405:40] wire [7:0] _ll_tableMask_T = 8'h3F; // @[FSECompressorDicBuilder.scala:381:35] wire [7:0] _ll_highThresholdBeforeCumul_T = 8'h3F; // @[FSECompressorDicBuilder.scala:386:47] wire [2:0] _stat_sum_WIRE_0 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_1 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_2 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_3 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_4 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_5 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_6 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_7 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_8 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_9 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_10 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_11 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_12 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_13 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_14 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_15 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_16 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_17 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_18 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_19 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_20 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_21 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_22 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_23 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_24 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_25 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_26 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_27 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_28 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_29 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_30 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_31 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [63:0] _ll_count_times_step_WIRE_0 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_1 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_2 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_3 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_4 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_5 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_6 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_7 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_8 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_9 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_10 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_11 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_12 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_13 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_14 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_15 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_16 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_17 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_18 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_19 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_20 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_21 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_22 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_23 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_24 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_25 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_26 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_27 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_28 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_29 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_30 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_31 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [255:0] _input_ll_symbols_0_T = io_ll_stream_output_data_0; // @[FSECompressorDicBuilder.scala:39:7, :174:53] wire _io_ll_table_log_valid_T_2; // @[FSECompressorDicBuilder.scala:453:48] wire _io_symbol_info_0_ready_T; // @[Misc.scala:26:53] wire io_symbolTT_info_0_bits_from_last_symbol_0 = io_symbol_info_0_bits_last_symbol_0; // @[FSECompressorDicBuilder.scala:39:7] wire _io_symbolTT_info_0_valid_T; // @[Misc.scala:26:53] wire [31:0] _io_symbolTT_info_0_bits_findstate_T_1; // @[FSECompressorDicBuilder.scala:435:81] wire _io_new_state_0_valid_T; // @[FSECompressorDicBuilder.scala:438:47] wire io_nb_seq_ready_0; // @[FSECompressorDicBuilder.scala:39:7] wire [5:0] io_ll_stream_user_consumed_bytes_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_ll_stream_output_ready_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_ll_table_log_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire [3:0] io_ll_table_log_bits_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbol_info_0_ready_0; // @[FSECompressorDicBuilder.scala:39:7] wire [31:0] io_symbolTT_info_0_bits_nbbit_0; // @[FSECompressorDicBuilder.scala:39:7] wire [31:0] io_symbolTT_info_0_bits_findstate_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbolTT_info_0_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_new_state_0_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire [15:0] io_new_state_0_bits_0; // @[FSECompressorDicBuilder.scala:39:7] wire [255:0] io_header_writes_bits_data_0; // @[FSECompressorDicBuilder.scala:39:7] wire [5:0] io_header_writes_bits_validbytes_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_header_writes_bits_end_of_message_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_header_writes_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_predefined_mode_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_predefined_mode_bits_0; // @[FSECompressorDicBuilder.scala:39:7] reg rtbTable_initialized; // @[FSECompressorDicBuilder.scala:56:37] reg [31:0] rtbTable_1; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_2; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_3; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_4; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_5; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_6; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_7; // @[FSECompressorDicBuilder.scala:57:25] reg [3:0] dicBuilderState; // @[FSECompressorDicBuilder.scala:156:32] reg [31:0] ll_count_0; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_1; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_2; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_3; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_4; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_5; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_6; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_7; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_8; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_9; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_10; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_11; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_12; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_13; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_14; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_15; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_16; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_17; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_18; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_19; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_20; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_21; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_22; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_23; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_24; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_25; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_26; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_27; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_28; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_29; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_30; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_31; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_max_symbol_value; // @[FSECompressorDicBuilder.scala:170:36] reg [63:0] ll_nbseq_1; // @[FSECompressorDicBuilder.scala:171:27] wire [7:0] input_ll_symbols_0; // @[FSECompressorDicBuilder.scala:172:34] wire [7:0] input_ll_symbols_1; // @[FSECompressorDicBuilder.scala:172:34] wire [7:0] input_ll_symbols_2; // @[FSECompressorDicBuilder.scala:172:34] wire [7:0] input_ll_symbols_3; // @[FSECompressorDicBuilder.scala:172:34] assign input_ll_symbols_0 = _input_ll_symbols_0_T[7:0]; // @[FSECompressorDicBuilder.scala:172:34, :174:{25,53}] wire [255:0] _input_ll_symbols_1_T = {8'h0, io_ll_stream_output_data_0[255:8]}; // @[FSECompressorDicBuilder.scala:39:7, :174:53] assign input_ll_symbols_1 = _input_ll_symbols_1_T[7:0]; // @[FSECompressorDicBuilder.scala:172:34, :174:{25,53}] wire [255:0] _input_ll_symbols_2_T = {16'h0, io_ll_stream_output_data_0[255:16]}; // @[FSECompressorDicBuilder.scala:39:7, :174:53] assign input_ll_symbols_2 = _input_ll_symbols_2_T[7:0]; // @[FSECompressorDicBuilder.scala:172:34, :174:{25,53}] wire [255:0] _input_ll_symbols_3_T = {24'h0, io_ll_stream_output_data_0[255:24]}; // @[FSECompressorDicBuilder.scala:39:7, :174:53] assign input_ll_symbols_3 = _input_ll_symbols_3_T[7:0]; // @[FSECompressorDicBuilder.scala:172:34, :174:{25,53}] wire _table_0_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_0_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_0_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_0_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_0_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_0_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_0_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_0_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_1_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_1_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_1_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_1_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_1_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_1_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_1_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_1_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_2_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_2_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_2_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_2_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_2_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_2_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_2_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_2_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_3_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_3_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_3_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_3_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_3_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_3_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_3_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_3_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_4_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_4_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_4_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_4_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_4_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_4_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_4_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_4_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_5_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_5_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_5_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_5_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_5_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_5_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_5_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_5_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_6_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_6_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_6_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_6_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_6_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_6_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_6_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_6_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_7_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_7_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_7_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_7_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_7_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_7_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_7_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_7_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_8_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_8_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_8_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_8_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_8_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_8_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_8_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_8_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_9_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_9_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_9_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_9_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_9_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_9_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_9_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_9_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_10_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_10_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_10_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_10_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_10_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_10_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_10_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_10_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_11_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_11_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_11_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_11_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_11_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_11_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_11_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_11_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_12_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_12_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_12_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_12_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_12_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_12_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_12_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_12_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_13_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_13_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_13_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_13_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_13_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_13_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_13_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_13_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_14_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_14_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_14_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_14_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_14_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_14_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_14_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_14_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_15_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_15_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_15_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_15_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_15_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_15_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_15_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_15_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_16_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_16_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_16_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_16_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_16_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_16_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_16_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_16_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_17_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_17_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_17_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_17_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_17_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_17_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_17_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_17_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_18_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_18_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_18_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_18_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_18_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_18_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_18_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_18_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_19_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_19_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_19_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_19_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_19_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_19_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_19_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_19_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_20_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_20_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_20_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_20_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_20_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_20_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_20_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_20_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_21_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_21_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_21_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_21_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_21_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_21_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_21_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_21_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_22_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_22_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_22_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_22_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_22_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_22_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_22_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_22_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_23_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_23_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_23_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_23_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_23_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_23_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_23_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_23_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_24_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_24_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_24_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_24_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_24_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_24_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_24_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_24_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_25_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_25_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_25_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_25_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_25_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_25_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_25_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_25_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_26_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_26_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_26_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_26_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_26_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_26_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_26_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_26_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_27_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_27_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_27_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_27_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_27_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_27_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_27_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_27_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_28_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_28_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_28_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_28_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_28_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_28_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_28_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_28_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_29_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_29_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_29_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_29_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_29_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_29_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_29_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_29_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_30_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_30_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_30_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_30_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_30_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_30_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_30_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_30_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_31_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_31_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_31_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_31_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_31_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_31_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_31_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_31_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_0_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_0_0_T_1 = input_ll_symbols_0 == 8'h0; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_0_0_T_2 = _table_0_0_T & _table_0_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_0_0_T_3 = _table_0_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_0_0 = _table_0_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_0_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_0_1_T_1 = input_ll_symbols_1 == 8'h0; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_0_1_T_2 = _table_0_1_T & _table_0_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_0_1_T_3 = _table_0_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_0_1 = _table_0_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _GEN = io_ll_stream_available_output_bytes_0 > 6'h2; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_0_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_0_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_1_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_1_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_2_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_2_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_3_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_3_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_4_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_4_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_5_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_5_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_6_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_6_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_7_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_7_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_8_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_8_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_9_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_9_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_10_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_10_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_11_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_11_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_12_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_12_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_13_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_13_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_14_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_14_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_15_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_15_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_16_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_16_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_17_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_17_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_18_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_18_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_19_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_19_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_20_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_20_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_21_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_21_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_22_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_22_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_23_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_23_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_24_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_24_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_25_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_25_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_26_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_26_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_27_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_27_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_28_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_28_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_29_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_29_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_30_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_30_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_31_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_31_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_0_2_T_1 = input_ll_symbols_2 == 8'h0; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_0_2_T_2 = _table_0_2_T & _table_0_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_0_2_T_3 = _table_0_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_0_2 = _table_0_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_0_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_0_3_T_1 = input_ll_symbols_3 == 8'h0; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_0_3_T_2 = _table_0_3_T & _table_0_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_0_3_T_3 = _table_0_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_0_3 = _table_0_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_1_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_1_0_T_1 = input_ll_symbols_0 == 8'h1; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_1_0_T_2 = _table_1_0_T & _table_1_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_1_0_T_3 = _table_1_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_1_0 = _table_1_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_1_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_1_1_T_1 = input_ll_symbols_1 == 8'h1; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_1_1_T_2 = _table_1_1_T & _table_1_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_1_1_T_3 = _table_1_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_1_1 = _table_1_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_1_2_T_1 = input_ll_symbols_2 == 8'h1; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_1_2_T_2 = _table_1_2_T & _table_1_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_1_2_T_3 = _table_1_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_1_2 = _table_1_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_1_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_1_3_T_1 = input_ll_symbols_3 == 8'h1; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_1_3_T_2 = _table_1_3_T & _table_1_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_1_3_T_3 = _table_1_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_1_3 = _table_1_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_2_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_2_0_T_1 = input_ll_symbols_0 == 8'h2; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_2_0_T_2 = _table_2_0_T & _table_2_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_2_0_T_3 = _table_2_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_2_0 = _table_2_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_2_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_2_1_T_1 = input_ll_symbols_1 == 8'h2; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_2_1_T_2 = _table_2_1_T & _table_2_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_2_1_T_3 = _table_2_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_2_1 = _table_2_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_2_2_T_1 = input_ll_symbols_2 == 8'h2; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_2_2_T_2 = _table_2_2_T & _table_2_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_2_2_T_3 = _table_2_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_2_2 = _table_2_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_2_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_2_3_T_1 = input_ll_symbols_3 == 8'h2; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_2_3_T_2 = _table_2_3_T & _table_2_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_2_3_T_3 = _table_2_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_2_3 = _table_2_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_3_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_3_0_T_1 = input_ll_symbols_0 == 8'h3; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_3_0_T_2 = _table_3_0_T & _table_3_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_3_0_T_3 = _table_3_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_3_0 = _table_3_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_3_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_3_1_T_1 = input_ll_symbols_1 == 8'h3; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_3_1_T_2 = _table_3_1_T & _table_3_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_3_1_T_3 = _table_3_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_3_1 = _table_3_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_3_2_T_1 = input_ll_symbols_2 == 8'h3; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_3_2_T_2 = _table_3_2_T & _table_3_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_3_2_T_3 = _table_3_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_3_2 = _table_3_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_3_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_3_3_T_1 = input_ll_symbols_3 == 8'h3; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_3_3_T_2 = _table_3_3_T & _table_3_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_3_3_T_3 = _table_3_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_3_3 = _table_3_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_4_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_4_0_T_1 = input_ll_symbols_0 == 8'h4; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_4_0_T_2 = _table_4_0_T & _table_4_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_4_0_T_3 = _table_4_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_4_0 = _table_4_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_4_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_4_1_T_1 = input_ll_symbols_1 == 8'h4; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_4_1_T_2 = _table_4_1_T & _table_4_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_4_1_T_3 = _table_4_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_4_1 = _table_4_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_4_2_T_1 = input_ll_symbols_2 == 8'h4; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_4_2_T_2 = _table_4_2_T & _table_4_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_4_2_T_3 = _table_4_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_4_2 = _table_4_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_4_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_4_3_T_1 = input_ll_symbols_3 == 8'h4; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_4_3_T_2 = _table_4_3_T & _table_4_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_4_3_T_3 = _table_4_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_4_3 = _table_4_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_5_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_5_0_T_1 = input_ll_symbols_0 == 8'h5; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_5_0_T_2 = _table_5_0_T & _table_5_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_5_0_T_3 = _table_5_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_5_0 = _table_5_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_5_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_5_1_T_1 = input_ll_symbols_1 == 8'h5; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_5_1_T_2 = _table_5_1_T & _table_5_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_5_1_T_3 = _table_5_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_5_1 = _table_5_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_5_2_T_1 = input_ll_symbols_2 == 8'h5; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_5_2_T_2 = _table_5_2_T & _table_5_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_5_2_T_3 = _table_5_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_5_2 = _table_5_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_5_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_5_3_T_1 = input_ll_symbols_3 == 8'h5; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_5_3_T_2 = _table_5_3_T & _table_5_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_5_3_T_3 = _table_5_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_5_3 = _table_5_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_6_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_6_0_T_1 = input_ll_symbols_0 == 8'h6; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_6_0_T_2 = _table_6_0_T & _table_6_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_6_0_T_3 = _table_6_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_6_0 = _table_6_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_6_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_6_1_T_1 = input_ll_symbols_1 == 8'h6; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_6_1_T_2 = _table_6_1_T & _table_6_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_6_1_T_3 = _table_6_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_6_1 = _table_6_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_6_2_T_1 = input_ll_symbols_2 == 8'h6; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_6_2_T_2 = _table_6_2_T & _table_6_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_6_2_T_3 = _table_6_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_6_2 = _table_6_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_6_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_6_3_T_1 = input_ll_symbols_3 == 8'h6; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_6_3_T_2 = _table_6_3_T & _table_6_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_6_3_T_3 = _table_6_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_6_3 = _table_6_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_7_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_7_0_T_1 = input_ll_symbols_0 == 8'h7; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_7_0_T_2 = _table_7_0_T & _table_7_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_7_0_T_3 = _table_7_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_7_0 = _table_7_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_7_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_7_1_T_1 = input_ll_symbols_1 == 8'h7; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_7_1_T_2 = _table_7_1_T & _table_7_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_7_1_T_3 = _table_7_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_7_1 = _table_7_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_7_2_T_1 = input_ll_symbols_2 == 8'h7; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_7_2_T_2 = _table_7_2_T & _table_7_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_7_2_T_3 = _table_7_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_7_2 = _table_7_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_7_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_7_3_T_1 = input_ll_symbols_3 == 8'h7; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_7_3_T_2 = _table_7_3_T & _table_7_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_7_3_T_3 = _table_7_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_7_3 = _table_7_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_8_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_8_0_T_1 = input_ll_symbols_0 == 8'h8; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_8_0_T_2 = _table_8_0_T & _table_8_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_8_0_T_3 = _table_8_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_8_0 = _table_8_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_8_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_8_1_T_1 = input_ll_symbols_1 == 8'h8; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_8_1_T_2 = _table_8_1_T & _table_8_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_8_1_T_3 = _table_8_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_8_1 = _table_8_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_8_2_T_1 = input_ll_symbols_2 == 8'h8; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_8_2_T_2 = _table_8_2_T & _table_8_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_8_2_T_3 = _table_8_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_8_2 = _table_8_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_8_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_8_3_T_1 = input_ll_symbols_3 == 8'h8; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_8_3_T_2 = _table_8_3_T & _table_8_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_8_3_T_3 = _table_8_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_8_3 = _table_8_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_9_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_9_0_T_1 = input_ll_symbols_0 == 8'h9; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_9_0_T_2 = _table_9_0_T & _table_9_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_9_0_T_3 = _table_9_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_9_0 = _table_9_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_9_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_9_1_T_1 = input_ll_symbols_1 == 8'h9; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_9_1_T_2 = _table_9_1_T & _table_9_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_9_1_T_3 = _table_9_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_9_1 = _table_9_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_9_2_T_1 = input_ll_symbols_2 == 8'h9; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_9_2_T_2 = _table_9_2_T & _table_9_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_9_2_T_3 = _table_9_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_9_2 = _table_9_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_9_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_9_3_T_1 = input_ll_symbols_3 == 8'h9; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_9_3_T_2 = _table_9_3_T & _table_9_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_9_3_T_3 = _table_9_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_9_3 = _table_9_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_10_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_10_0_T_1 = input_ll_symbols_0 == 8'hA; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_10_0_T_2 = _table_10_0_T & _table_10_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_10_0_T_3 = _table_10_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_10_0 = _table_10_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_10_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_10_1_T_1 = input_ll_symbols_1 == 8'hA; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_10_1_T_2 = _table_10_1_T & _table_10_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_10_1_T_3 = _table_10_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_10_1 = _table_10_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_10_2_T_1 = input_ll_symbols_2 == 8'hA; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_10_2_T_2 = _table_10_2_T & _table_10_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_10_2_T_3 = _table_10_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_10_2 = _table_10_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_10_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_10_3_T_1 = input_ll_symbols_3 == 8'hA; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_10_3_T_2 = _table_10_3_T & _table_10_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_10_3_T_3 = _table_10_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_10_3 = _table_10_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_11_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_11_0_T_1 = input_ll_symbols_0 == 8'hB; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_11_0_T_2 = _table_11_0_T & _table_11_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_11_0_T_3 = _table_11_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_11_0 = _table_11_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_11_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_11_1_T_1 = input_ll_symbols_1 == 8'hB; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_11_1_T_2 = _table_11_1_T & _table_11_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_11_1_T_3 = _table_11_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_11_1 = _table_11_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_11_2_T_1 = input_ll_symbols_2 == 8'hB; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_11_2_T_2 = _table_11_2_T & _table_11_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_11_2_T_3 = _table_11_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_11_2 = _table_11_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_11_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_11_3_T_1 = input_ll_symbols_3 == 8'hB; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_11_3_T_2 = _table_11_3_T & _table_11_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_11_3_T_3 = _table_11_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_11_3 = _table_11_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_12_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_12_0_T_1 = input_ll_symbols_0 == 8'hC; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_12_0_T_2 = _table_12_0_T & _table_12_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_12_0_T_3 = _table_12_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_12_0 = _table_12_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_12_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_12_1_T_1 = input_ll_symbols_1 == 8'hC; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_12_1_T_2 = _table_12_1_T & _table_12_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_12_1_T_3 = _table_12_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_12_1 = _table_12_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_12_2_T_1 = input_ll_symbols_2 == 8'hC; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_12_2_T_2 = _table_12_2_T & _table_12_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_12_2_T_3 = _table_12_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_12_2 = _table_12_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_12_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_12_3_T_1 = input_ll_symbols_3 == 8'hC; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_12_3_T_2 = _table_12_3_T & _table_12_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_12_3_T_3 = _table_12_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_12_3 = _table_12_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_13_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_13_0_T_1 = input_ll_symbols_0 == 8'hD; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_13_0_T_2 = _table_13_0_T & _table_13_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_13_0_T_3 = _table_13_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_13_0 = _table_13_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_13_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_13_1_T_1 = input_ll_symbols_1 == 8'hD; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_13_1_T_2 = _table_13_1_T & _table_13_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_13_1_T_3 = _table_13_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_13_1 = _table_13_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_13_2_T_1 = input_ll_symbols_2 == 8'hD; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_13_2_T_2 = _table_13_2_T & _table_13_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_13_2_T_3 = _table_13_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_13_2 = _table_13_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_13_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_13_3_T_1 = input_ll_symbols_3 == 8'hD; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_13_3_T_2 = _table_13_3_T & _table_13_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_13_3_T_3 = _table_13_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_13_3 = _table_13_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_14_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_14_0_T_1 = input_ll_symbols_0 == 8'hE; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_14_0_T_2 = _table_14_0_T & _table_14_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_14_0_T_3 = _table_14_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_14_0 = _table_14_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_14_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_14_1_T_1 = input_ll_symbols_1 == 8'hE; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_14_1_T_2 = _table_14_1_T & _table_14_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_14_1_T_3 = _table_14_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_14_1 = _table_14_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_14_2_T_1 = input_ll_symbols_2 == 8'hE; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_14_2_T_2 = _table_14_2_T & _table_14_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_14_2_T_3 = _table_14_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_14_2 = _table_14_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_14_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_14_3_T_1 = input_ll_symbols_3 == 8'hE; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_14_3_T_2 = _table_14_3_T & _table_14_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_14_3_T_3 = _table_14_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_14_3 = _table_14_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_15_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_15_0_T_1 = input_ll_symbols_0 == 8'hF; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_15_0_T_2 = _table_15_0_T & _table_15_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_15_0_T_3 = _table_15_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_15_0 = _table_15_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_15_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_15_1_T_1 = input_ll_symbols_1 == 8'hF; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_15_1_T_2 = _table_15_1_T & _table_15_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_15_1_T_3 = _table_15_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_15_1 = _table_15_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_15_2_T_1 = input_ll_symbols_2 == 8'hF; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_15_2_T_2 = _table_15_2_T & _table_15_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_15_2_T_3 = _table_15_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_15_2 = _table_15_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_15_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_15_3_T_1 = input_ll_symbols_3 == 8'hF; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_15_3_T_2 = _table_15_3_T & _table_15_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_15_3_T_3 = _table_15_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_15_3 = _table_15_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_16_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_16_0_T_1 = input_ll_symbols_0 == 8'h10; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_16_0_T_2 = _table_16_0_T & _table_16_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_16_0_T_3 = _table_16_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_16_0 = _table_16_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_16_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_16_1_T_1 = input_ll_symbols_1 == 8'h10; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_16_1_T_2 = _table_16_1_T & _table_16_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_16_1_T_3 = _table_16_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_16_1 = _table_16_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_16_2_T_1 = input_ll_symbols_2 == 8'h10; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_16_2_T_2 = _table_16_2_T & _table_16_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_16_2_T_3 = _table_16_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_16_2 = _table_16_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_16_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_16_3_T_1 = input_ll_symbols_3 == 8'h10; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_16_3_T_2 = _table_16_3_T & _table_16_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_16_3_T_3 = _table_16_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_16_3 = _table_16_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_17_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_17_0_T_1 = input_ll_symbols_0 == 8'h11; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_17_0_T_2 = _table_17_0_T & _table_17_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_17_0_T_3 = _table_17_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_17_0 = _table_17_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_17_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_17_1_T_1 = input_ll_symbols_1 == 8'h11; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_17_1_T_2 = _table_17_1_T & _table_17_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_17_1_T_3 = _table_17_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_17_1 = _table_17_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_17_2_T_1 = input_ll_symbols_2 == 8'h11; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_17_2_T_2 = _table_17_2_T & _table_17_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_17_2_T_3 = _table_17_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_17_2 = _table_17_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_17_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_17_3_T_1 = input_ll_symbols_3 == 8'h11; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_17_3_T_2 = _table_17_3_T & _table_17_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_17_3_T_3 = _table_17_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_17_3 = _table_17_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_18_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_18_0_T_1 = input_ll_symbols_0 == 8'h12; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_18_0_T_2 = _table_18_0_T & _table_18_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_18_0_T_3 = _table_18_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_18_0 = _table_18_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_18_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_18_1_T_1 = input_ll_symbols_1 == 8'h12; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_18_1_T_2 = _table_18_1_T & _table_18_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_18_1_T_3 = _table_18_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_18_1 = _table_18_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_18_2_T_1 = input_ll_symbols_2 == 8'h12; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_18_2_T_2 = _table_18_2_T & _table_18_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_18_2_T_3 = _table_18_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_18_2 = _table_18_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_18_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_18_3_T_1 = input_ll_symbols_3 == 8'h12; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_18_3_T_2 = _table_18_3_T & _table_18_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_18_3_T_3 = _table_18_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_18_3 = _table_18_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_19_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_19_0_T_1 = input_ll_symbols_0 == 8'h13; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_19_0_T_2 = _table_19_0_T & _table_19_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_19_0_T_3 = _table_19_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_19_0 = _table_19_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_19_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_19_1_T_1 = input_ll_symbols_1 == 8'h13; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_19_1_T_2 = _table_19_1_T & _table_19_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_19_1_T_3 = _table_19_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_19_1 = _table_19_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_19_2_T_1 = input_ll_symbols_2 == 8'h13; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_19_2_T_2 = _table_19_2_T & _table_19_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_19_2_T_3 = _table_19_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_19_2 = _table_19_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_19_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_19_3_T_1 = input_ll_symbols_3 == 8'h13; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_19_3_T_2 = _table_19_3_T & _table_19_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_19_3_T_3 = _table_19_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_19_3 = _table_19_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_20_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_20_0_T_1 = input_ll_symbols_0 == 8'h14; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_20_0_T_2 = _table_20_0_T & _table_20_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_20_0_T_3 = _table_20_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_20_0 = _table_20_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_20_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_20_1_T_1 = input_ll_symbols_1 == 8'h14; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_20_1_T_2 = _table_20_1_T & _table_20_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_20_1_T_3 = _table_20_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_20_1 = _table_20_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_20_2_T_1 = input_ll_symbols_2 == 8'h14; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_20_2_T_2 = _table_20_2_T & _table_20_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_20_2_T_3 = _table_20_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_20_2 = _table_20_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_20_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_20_3_T_1 = input_ll_symbols_3 == 8'h14; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_20_3_T_2 = _table_20_3_T & _table_20_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_20_3_T_3 = _table_20_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_20_3 = _table_20_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_21_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_21_0_T_1 = input_ll_symbols_0 == 8'h15; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_21_0_T_2 = _table_21_0_T & _table_21_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_21_0_T_3 = _table_21_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_21_0 = _table_21_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_21_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_21_1_T_1 = input_ll_symbols_1 == 8'h15; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_21_1_T_2 = _table_21_1_T & _table_21_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_21_1_T_3 = _table_21_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_21_1 = _table_21_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_21_2_T_1 = input_ll_symbols_2 == 8'h15; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_21_2_T_2 = _table_21_2_T & _table_21_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_21_2_T_3 = _table_21_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_21_2 = _table_21_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_21_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_21_3_T_1 = input_ll_symbols_3 == 8'h15; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_21_3_T_2 = _table_21_3_T & _table_21_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_21_3_T_3 = _table_21_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_21_3 = _table_21_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_22_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_22_0_T_1 = input_ll_symbols_0 == 8'h16; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_22_0_T_2 = _table_22_0_T & _table_22_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_22_0_T_3 = _table_22_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_22_0 = _table_22_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_22_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_22_1_T_1 = input_ll_symbols_1 == 8'h16; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_22_1_T_2 = _table_22_1_T & _table_22_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_22_1_T_3 = _table_22_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_22_1 = _table_22_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_22_2_T_1 = input_ll_symbols_2 == 8'h16; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_22_2_T_2 = _table_22_2_T & _table_22_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_22_2_T_3 = _table_22_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_22_2 = _table_22_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_22_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_22_3_T_1 = input_ll_symbols_3 == 8'h16; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_22_3_T_2 = _table_22_3_T & _table_22_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_22_3_T_3 = _table_22_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_22_3 = _table_22_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_23_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_23_0_T_1 = input_ll_symbols_0 == 8'h17; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_23_0_T_2 = _table_23_0_T & _table_23_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_23_0_T_3 = _table_23_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_23_0 = _table_23_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_23_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_23_1_T_1 = input_ll_symbols_1 == 8'h17; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_23_1_T_2 = _table_23_1_T & _table_23_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_23_1_T_3 = _table_23_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_23_1 = _table_23_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_23_2_T_1 = input_ll_symbols_2 == 8'h17; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_23_2_T_2 = _table_23_2_T & _table_23_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_23_2_T_3 = _table_23_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_23_2 = _table_23_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_23_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_23_3_T_1 = input_ll_symbols_3 == 8'h17; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_23_3_T_2 = _table_23_3_T & _table_23_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_23_3_T_3 = _table_23_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_23_3 = _table_23_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_24_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_24_0_T_1 = input_ll_symbols_0 == 8'h18; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_24_0_T_2 = _table_24_0_T & _table_24_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_24_0_T_3 = _table_24_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_24_0 = _table_24_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_24_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_24_1_T_1 = input_ll_symbols_1 == 8'h18; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_24_1_T_2 = _table_24_1_T & _table_24_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_24_1_T_3 = _table_24_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_24_1 = _table_24_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_24_2_T_1 = input_ll_symbols_2 == 8'h18; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_24_2_T_2 = _table_24_2_T & _table_24_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_24_2_T_3 = _table_24_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_24_2 = _table_24_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_24_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_24_3_T_1 = input_ll_symbols_3 == 8'h18; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_24_3_T_2 = _table_24_3_T & _table_24_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_24_3_T_3 = _table_24_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_24_3 = _table_24_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_25_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_25_0_T_1 = input_ll_symbols_0 == 8'h19; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_25_0_T_2 = _table_25_0_T & _table_25_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_25_0_T_3 = _table_25_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_25_0 = _table_25_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_25_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_25_1_T_1 = input_ll_symbols_1 == 8'h19; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_25_1_T_2 = _table_25_1_T & _table_25_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_25_1_T_3 = _table_25_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_25_1 = _table_25_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_25_2_T_1 = input_ll_symbols_2 == 8'h19; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_25_2_T_2 = _table_25_2_T & _table_25_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_25_2_T_3 = _table_25_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_25_2 = _table_25_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_25_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_25_3_T_1 = input_ll_symbols_3 == 8'h19; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_25_3_T_2 = _table_25_3_T & _table_25_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_25_3_T_3 = _table_25_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_25_3 = _table_25_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_26_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_26_0_T_1 = input_ll_symbols_0 == 8'h1A; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_26_0_T_2 = _table_26_0_T & _table_26_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_26_0_T_3 = _table_26_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_26_0 = _table_26_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_26_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_26_1_T_1 = input_ll_symbols_1 == 8'h1A; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_26_1_T_2 = _table_26_1_T & _table_26_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_26_1_T_3 = _table_26_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_26_1 = _table_26_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_26_2_T_1 = input_ll_symbols_2 == 8'h1A; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_26_2_T_2 = _table_26_2_T & _table_26_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_26_2_T_3 = _table_26_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_26_2 = _table_26_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_26_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_26_3_T_1 = input_ll_symbols_3 == 8'h1A; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_26_3_T_2 = _table_26_3_T & _table_26_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_26_3_T_3 = _table_26_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_26_3 = _table_26_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_27_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_27_0_T_1 = input_ll_symbols_0 == 8'h1B; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_27_0_T_2 = _table_27_0_T & _table_27_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_27_0_T_3 = _table_27_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_27_0 = _table_27_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_27_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_27_1_T_1 = input_ll_symbols_1 == 8'h1B; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_27_1_T_2 = _table_27_1_T & _table_27_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_27_1_T_3 = _table_27_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_27_1 = _table_27_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_27_2_T_1 = input_ll_symbols_2 == 8'h1B; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_27_2_T_2 = _table_27_2_T & _table_27_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_27_2_T_3 = _table_27_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_27_2 = _table_27_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_27_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_27_3_T_1 = input_ll_symbols_3 == 8'h1B; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_27_3_T_2 = _table_27_3_T & _table_27_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_27_3_T_3 = _table_27_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_27_3 = _table_27_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_28_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_28_0_T_1 = input_ll_symbols_0 == 8'h1C; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_28_0_T_2 = _table_28_0_T & _table_28_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_28_0_T_3 = _table_28_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_28_0 = _table_28_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_28_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_28_1_T_1 = input_ll_symbols_1 == 8'h1C; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_28_1_T_2 = _table_28_1_T & _table_28_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_28_1_T_3 = _table_28_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_28_1 = _table_28_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_28_2_T_1 = input_ll_symbols_2 == 8'h1C; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_28_2_T_2 = _table_28_2_T & _table_28_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_28_2_T_3 = _table_28_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_28_2 = _table_28_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_28_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_28_3_T_1 = input_ll_symbols_3 == 8'h1C; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_28_3_T_2 = _table_28_3_T & _table_28_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_28_3_T_3 = _table_28_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_28_3 = _table_28_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_29_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_29_0_T_1 = input_ll_symbols_0 == 8'h1D; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_29_0_T_2 = _table_29_0_T & _table_29_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_29_0_T_3 = _table_29_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_29_0 = _table_29_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_29_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_29_1_T_1 = input_ll_symbols_1 == 8'h1D; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_29_1_T_2 = _table_29_1_T & _table_29_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_29_1_T_3 = _table_29_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_29_1 = _table_29_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_29_2_T_1 = input_ll_symbols_2 == 8'h1D; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_29_2_T_2 = _table_29_2_T & _table_29_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_29_2_T_3 = _table_29_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_29_2 = _table_29_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_29_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_29_3_T_1 = input_ll_symbols_3 == 8'h1D; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_29_3_T_2 = _table_29_3_T & _table_29_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_29_3_T_3 = _table_29_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_29_3 = _table_29_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_30_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_30_0_T_1 = input_ll_symbols_0 == 8'h1E; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_30_0_T_2 = _table_30_0_T & _table_30_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_30_0_T_3 = _table_30_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_30_0 = _table_30_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_30_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_30_1_T_1 = input_ll_symbols_1 == 8'h1E; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_30_1_T_2 = _table_30_1_T & _table_30_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_30_1_T_3 = _table_30_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_30_1 = _table_30_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_30_2_T_1 = input_ll_symbols_2 == 8'h1E; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_30_2_T_2 = _table_30_2_T & _table_30_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_30_2_T_3 = _table_30_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_30_2 = _table_30_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_30_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_30_3_T_1 = input_ll_symbols_3 == 8'h1E; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_30_3_T_2 = _table_30_3_T & _table_30_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_30_3_T_3 = _table_30_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_30_3 = _table_30_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_31_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_31_0_T_1 = input_ll_symbols_0 == 8'h1F; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_31_0_T_2 = _table_31_0_T & _table_31_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_31_0_T_3 = _table_31_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_31_0 = _table_31_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_31_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_31_1_T_1 = input_ll_symbols_1 == 8'h1F; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_31_1_T_2 = _table_31_1_T & _table_31_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_31_1_T_3 = _table_31_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_31_1 = _table_31_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_31_2_T_1 = input_ll_symbols_2 == 8'h1F; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_31_2_T_2 = _table_31_2_T & _table_31_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_31_2_T_3 = _table_31_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_31_2 = _table_31_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_31_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_31_3_T_1 = input_ll_symbols_3 == 8'h1F; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_31_3_T_2 = _table_31_3_T & _table_31_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_31_3_T_3 = _table_31_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_31_3 = _table_31_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire [2:0] stat_sum_0; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_1; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_2; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_3; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_4; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_5; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_6; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_7; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_8; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_9; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_10; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_11; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_12; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_13; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_14; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_15; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_16; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_17; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_18; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_19; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_20; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_21; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_22; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_23; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_24; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_25; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_26; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_27; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_28; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_29; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_30; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_31; // @[FSECompressorDicBuilder.scala:186:26] wire [1:0] _stat_sum_0_T = {1'h0, table_0_0} + {1'h0, table_0_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_0_T_1 = {1'h0, _stat_sum_0_T} + {2'h0, table_0_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_0_T_2 = {1'h0, _stat_sum_0_T_1} + {3'h0, table_0_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_0 = _stat_sum_0_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_1_T = {1'h0, table_1_0} + {1'h0, table_1_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_1_T_1 = {1'h0, _stat_sum_1_T} + {2'h0, table_1_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_1_T_2 = {1'h0, _stat_sum_1_T_1} + {3'h0, table_1_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_1 = _stat_sum_1_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_2_T = {1'h0, table_2_0} + {1'h0, table_2_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_2_T_1 = {1'h0, _stat_sum_2_T} + {2'h0, table_2_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_2_T_2 = {1'h0, _stat_sum_2_T_1} + {3'h0, table_2_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_2 = _stat_sum_2_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_3_T = {1'h0, table_3_0} + {1'h0, table_3_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_3_T_1 = {1'h0, _stat_sum_3_T} + {2'h0, table_3_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_3_T_2 = {1'h0, _stat_sum_3_T_1} + {3'h0, table_3_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_3 = _stat_sum_3_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_4_T = {1'h0, table_4_0} + {1'h0, table_4_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_4_T_1 = {1'h0, _stat_sum_4_T} + {2'h0, table_4_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_4_T_2 = {1'h0, _stat_sum_4_T_1} + {3'h0, table_4_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_4 = _stat_sum_4_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_5_T = {1'h0, table_5_0} + {1'h0, table_5_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_5_T_1 = {1'h0, _stat_sum_5_T} + {2'h0, table_5_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_5_T_2 = {1'h0, _stat_sum_5_T_1} + {3'h0, table_5_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_5 = _stat_sum_5_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_6_T = {1'h0, table_6_0} + {1'h0, table_6_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_6_T_1 = {1'h0, _stat_sum_6_T} + {2'h0, table_6_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_6_T_2 = {1'h0, _stat_sum_6_T_1} + {3'h0, table_6_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_6 = _stat_sum_6_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_7_T = {1'h0, table_7_0} + {1'h0, table_7_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_7_T_1 = {1'h0, _stat_sum_7_T} + {2'h0, table_7_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_7_T_2 = {1'h0, _stat_sum_7_T_1} + {3'h0, table_7_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_7 = _stat_sum_7_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_8_T = {1'h0, table_8_0} + {1'h0, table_8_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_8_T_1 = {1'h0, _stat_sum_8_T} + {2'h0, table_8_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_8_T_2 = {1'h0, _stat_sum_8_T_1} + {3'h0, table_8_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_8 = _stat_sum_8_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_9_T = {1'h0, table_9_0} + {1'h0, table_9_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_9_T_1 = {1'h0, _stat_sum_9_T} + {2'h0, table_9_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_9_T_2 = {1'h0, _stat_sum_9_T_1} + {3'h0, table_9_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_9 = _stat_sum_9_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_10_T = {1'h0, table_10_0} + {1'h0, table_10_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_10_T_1 = {1'h0, _stat_sum_10_T} + {2'h0, table_10_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_10_T_2 = {1'h0, _stat_sum_10_T_1} + {3'h0, table_10_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_10 = _stat_sum_10_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_11_T = {1'h0, table_11_0} + {1'h0, table_11_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_11_T_1 = {1'h0, _stat_sum_11_T} + {2'h0, table_11_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_11_T_2 = {1'h0, _stat_sum_11_T_1} + {3'h0, table_11_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_11 = _stat_sum_11_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_12_T = {1'h0, table_12_0} + {1'h0, table_12_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_12_T_1 = {1'h0, _stat_sum_12_T} + {2'h0, table_12_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_12_T_2 = {1'h0, _stat_sum_12_T_1} + {3'h0, table_12_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_12 = _stat_sum_12_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_13_T = {1'h0, table_13_0} + {1'h0, table_13_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_13_T_1 = {1'h0, _stat_sum_13_T} + {2'h0, table_13_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_13_T_2 = {1'h0, _stat_sum_13_T_1} + {3'h0, table_13_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_13 = _stat_sum_13_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_14_T = {1'h0, table_14_0} + {1'h0, table_14_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_14_T_1 = {1'h0, _stat_sum_14_T} + {2'h0, table_14_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_14_T_2 = {1'h0, _stat_sum_14_T_1} + {3'h0, table_14_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_14 = _stat_sum_14_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_15_T = {1'h0, table_15_0} + {1'h0, table_15_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_15_T_1 = {1'h0, _stat_sum_15_T} + {2'h0, table_15_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_15_T_2 = {1'h0, _stat_sum_15_T_1} + {3'h0, table_15_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_15 = _stat_sum_15_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_16_T = {1'h0, table_16_0} + {1'h0, table_16_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_16_T_1 = {1'h0, _stat_sum_16_T} + {2'h0, table_16_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_16_T_2 = {1'h0, _stat_sum_16_T_1} + {3'h0, table_16_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_16 = _stat_sum_16_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_17_T = {1'h0, table_17_0} + {1'h0, table_17_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_17_T_1 = {1'h0, _stat_sum_17_T} + {2'h0, table_17_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_17_T_2 = {1'h0, _stat_sum_17_T_1} + {3'h0, table_17_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_17 = _stat_sum_17_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_18_T = {1'h0, table_18_0} + {1'h0, table_18_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_18_T_1 = {1'h0, _stat_sum_18_T} + {2'h0, table_18_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_18_T_2 = {1'h0, _stat_sum_18_T_1} + {3'h0, table_18_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_18 = _stat_sum_18_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_19_T = {1'h0, table_19_0} + {1'h0, table_19_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_19_T_1 = {1'h0, _stat_sum_19_T} + {2'h0, table_19_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_19_T_2 = {1'h0, _stat_sum_19_T_1} + {3'h0, table_19_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_19 = _stat_sum_19_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_20_T = {1'h0, table_20_0} + {1'h0, table_20_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_20_T_1 = {1'h0, _stat_sum_20_T} + {2'h0, table_20_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_20_T_2 = {1'h0, _stat_sum_20_T_1} + {3'h0, table_20_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_20 = _stat_sum_20_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_21_T = {1'h0, table_21_0} + {1'h0, table_21_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_21_T_1 = {1'h0, _stat_sum_21_T} + {2'h0, table_21_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_21_T_2 = {1'h0, _stat_sum_21_T_1} + {3'h0, table_21_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_21 = _stat_sum_21_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_22_T = {1'h0, table_22_0} + {1'h0, table_22_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_22_T_1 = {1'h0, _stat_sum_22_T} + {2'h0, table_22_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_22_T_2 = {1'h0, _stat_sum_22_T_1} + {3'h0, table_22_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_22 = _stat_sum_22_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_23_T = {1'h0, table_23_0} + {1'h0, table_23_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_23_T_1 = {1'h0, _stat_sum_23_T} + {2'h0, table_23_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_23_T_2 = {1'h0, _stat_sum_23_T_1} + {3'h0, table_23_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_23 = _stat_sum_23_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_24_T = {1'h0, table_24_0} + {1'h0, table_24_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_24_T_1 = {1'h0, _stat_sum_24_T} + {2'h0, table_24_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_24_T_2 = {1'h0, _stat_sum_24_T_1} + {3'h0, table_24_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_24 = _stat_sum_24_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_25_T = {1'h0, table_25_0} + {1'h0, table_25_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_25_T_1 = {1'h0, _stat_sum_25_T} + {2'h0, table_25_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_25_T_2 = {1'h0, _stat_sum_25_T_1} + {3'h0, table_25_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_25 = _stat_sum_25_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_26_T = {1'h0, table_26_0} + {1'h0, table_26_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_26_T_1 = {1'h0, _stat_sum_26_T} + {2'h0, table_26_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_26_T_2 = {1'h0, _stat_sum_26_T_1} + {3'h0, table_26_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_26 = _stat_sum_26_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_27_T = {1'h0, table_27_0} + {1'h0, table_27_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_27_T_1 = {1'h0, _stat_sum_27_T} + {2'h0, table_27_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_27_T_2 = {1'h0, _stat_sum_27_T_1} + {3'h0, table_27_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_27 = _stat_sum_27_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_28_T = {1'h0, table_28_0} + {1'h0, table_28_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_28_T_1 = {1'h0, _stat_sum_28_T} + {2'h0, table_28_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_28_T_2 = {1'h0, _stat_sum_28_T_1} + {3'h0, table_28_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_28 = _stat_sum_28_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_29_T = {1'h0, table_29_0} + {1'h0, table_29_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_29_T_1 = {1'h0, _stat_sum_29_T} + {2'h0, table_29_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_29_T_2 = {1'h0, _stat_sum_29_T_1} + {3'h0, table_29_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_29 = _stat_sum_29_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_30_T = {1'h0, table_30_0} + {1'h0, table_30_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_30_T_1 = {1'h0, _stat_sum_30_T} + {2'h0, table_30_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_30_T_2 = {1'h0, _stat_sum_30_T_1} + {3'h0, table_30_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_30 = _stat_sum_30_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_31_T = {1'h0, table_31_0} + {1'h0, table_31_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_31_T_1 = {1'h0, _stat_sum_31_T} + {2'h0, table_31_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_31_T_2 = {1'h0, _stat_sum_31_T_1} + {3'h0, table_31_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_31 = _stat_sum_31_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire _has_value_0_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_1_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_2_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_3_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_4_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_5_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_6_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_7_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_8_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_9_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_10_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_11_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_12_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_13_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_14_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_15_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_16_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_17_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_18_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_19_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_20_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_21_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_22_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_23_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_24_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_25_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_26_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_27_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_28_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_29_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_30_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_31_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire has_value_0; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_1; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_2; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_3; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_4; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_5; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_6; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_7; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_8; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_9; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_10; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_11; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_12; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_13; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_14; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_15; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_16; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_17; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_18; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_19; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_20; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_21; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_22; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_23; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_24; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_25; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_26; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_27; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_28; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_29; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_30; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_31; // @[FSECompressorDicBuilder.scala:191:27] wire _has_value_0_T = \|stat_sum_0; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_0_T_1 = _has_value_0_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_0 = _has_value_0_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_1_T = \|stat_sum_1; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_1_T_1 = _has_value_1_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_1 = _has_value_1_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_2_T = \|stat_sum_2; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_2_T_1 = _has_value_2_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_2 = _has_value_2_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_3_T = \|stat_sum_3; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_3_T_1 = _has_value_3_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_3 = _has_value_3_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_4_T = \|stat_sum_4; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_4_T_1 = _has_value_4_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_4 = _has_value_4_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_5_T = \|stat_sum_5; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_5_T_1 = _has_value_5_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_5 = _has_value_5_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_6_T = \|stat_sum_6; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_6_T_1 = _has_value_6_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_6 = _has_value_6_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_7_T = \|stat_sum_7; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_7_T_1 = _has_value_7_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_7 = _has_value_7_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_8_T = \|stat_sum_8; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_8_T_1 = _has_value_8_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_8 = _has_value_8_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_9_T = \|stat_sum_9; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_9_T_1 = _has_value_9_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_9 = _has_value_9_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_10_T = \|stat_sum_10; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_10_T_1 = _has_value_10_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_10 = _has_value_10_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_11_T = \|stat_sum_11; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_11_T_1 = _has_value_11_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_11 = _has_value_11_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_12_T = \|stat_sum_12; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_12_T_1 = _has_value_12_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_12 = _has_value_12_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_13_T = \|stat_sum_13; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_13_T_1 = _has_value_13_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_13 = _has_value_13_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_14_T = \|stat_sum_14; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_14_T_1 = _has_value_14_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_14 = _has_value_14_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_15_T = \|stat_sum_15; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_15_T_1 = _has_value_15_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_15 = _has_value_15_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_16_T = \|stat_sum_16; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_16_T_1 = _has_value_16_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_16 = _has_value_16_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_17_T = \|stat_sum_17; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_17_T_1 = _has_value_17_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_17 = _has_value_17_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_18_T = \|stat_sum_18; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_18_T_1 = _has_value_18_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_18 = _has_value_18_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_19_T = \|stat_sum_19; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_19_T_1 = _has_value_19_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_19 = _has_value_19_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_20_T = \|stat_sum_20; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_20_T_1 = _has_value_20_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_20 = _has_value_20_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_21_T = \|stat_sum_21; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_21_T_1 = _has_value_21_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_21 = _has_value_21_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_22_T = \|stat_sum_22; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_22_T_1 = _has_value_22_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_22 = _has_value_22_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_23_T = \|stat_sum_23; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_23_T_1 = _has_value_23_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_23 = _has_value_23_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_24_T = \|stat_sum_24; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_24_T_1 = _has_value_24_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_24 = _has_value_24_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_25_T = \|stat_sum_25; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_25_T_1 = _has_value_25_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_25 = _has_value_25_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_26_T = \|stat_sum_26; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_26_T_1 = _has_value_26_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_26 = _has_value_26_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_27_T = \|stat_sum_27; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_27_T_1 = _has_value_27_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_27 = _has_value_27_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_28_T = \|stat_sum_28; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_28_T_1 = _has_value_28_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_28 = _has_value_28_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_29_T = \|stat_sum_29; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_29_T_1 = _has_value_29_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_29 = _has_value_29_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_30_T = \|stat_sum_30; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_30_T_1 = _has_value_30_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_30 = _has_value_30_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_31_T = \|stat_sum_31; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_31_T_1 = _has_value_31_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_31 = _has_value_31_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire [1:0] has_value_cat_lo_lo_lo_lo = {has_value_30, has_value_31}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_lo_lo_lo_hi = {has_value_28, has_value_29}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_lo_lo_lo = {has_value_cat_lo_lo_lo_hi, has_value_cat_lo_lo_lo_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [1:0] has_value_cat_lo_lo_hi_lo = {has_value_26, has_value_27}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_lo_lo_hi_hi = {has_value_24, has_value_25}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_lo_lo_hi = {has_value_cat_lo_lo_hi_hi, has_value_cat_lo_lo_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [7:0] has_value_cat_lo_lo = {has_value_cat_lo_lo_hi, has_value_cat_lo_lo_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [1:0] has_value_cat_lo_hi_lo_lo = {has_value_22, has_value_23}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_lo_hi_lo_hi = {has_value_20, has_value_21}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_lo_hi_lo = {has_value_cat_lo_hi_lo_hi, has_value_cat_lo_hi_lo_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [1:0] has_value_cat_lo_hi_hi_lo = {has_value_18, has_value_19}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_lo_hi_hi_hi = {has_value_16, has_value_17}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_lo_hi_hi = {has_value_cat_lo_hi_hi_hi, has_value_cat_lo_hi_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [7:0] has_value_cat_lo_hi = {has_value_cat_lo_hi_hi, has_value_cat_lo_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [15:0] has_value_cat_lo = {has_value_cat_lo_hi, has_value_cat_lo_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [1:0] has_value_cat_hi_lo_lo_lo = {has_value_14, has_value_15}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_hi_lo_lo_hi = {has_value_12, has_value_13}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_hi_lo_lo = {has_value_cat_hi_lo_lo_hi, has_value_cat_hi_lo_lo_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [1:0] has_value_cat_hi_lo_hi_lo = {has_value_10, has_value_11}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_hi_lo_hi_hi = {has_value_8, has_value_9}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_hi_lo_hi = {has_value_cat_hi_lo_hi_hi, has_value_cat_hi_lo_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [7:0] has_value_cat_hi_lo = {has_value_cat_hi_lo_hi, has_value_cat_hi_lo_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [1:0] has_value_cat_hi_hi_lo_lo = {has_value_6, has_value_7}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_hi_hi_lo_hi = {has_value_4, has_value_5}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_hi_hi_lo = {has_value_cat_hi_hi_lo_hi, has_value_cat_hi_hi_lo_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [1:0] has_value_cat_hi_hi_hi_lo = {has_value_2, has_value_3}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_hi_hi_hi_hi = {has_value_0, has_value_1}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_hi_hi_hi = {has_value_cat_hi_hi_hi_hi, has_value_cat_hi_hi_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [7:0] has_value_cat_hi_hi = {has_value_cat_hi_hi_hi, has_value_cat_hi_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [15:0] has_value_cat_hi = {has_value_cat_hi_hi, has_value_cat_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [31:0] has_value_cat = {has_value_cat_hi, has_value_cat_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire _cur_max_value_T = has_value_cat[0]; // @[OneHot.scala:48:45] wire _cur_max_value_T_1 = has_value_cat[1]; // @[OneHot.scala:48:45] wire _cur_max_value_T_2 = has_value_cat[2]; // @[OneHot.scala:48:45] wire _cur_max_value_T_3 = has_value_cat[3]; // @[OneHot.scala:48:45] wire _cur_max_value_T_4 = has_value_cat[4]; // @[OneHot.scala:48:45] wire _cur_max_value_T_5 = has_value_cat[5]; // @[OneHot.scala:48:45] wire _cur_max_value_T_6 = has_value_cat[6]; // @[OneHot.scala:48:45] wire _cur_max_value_T_7 = has_value_cat[7]; // @[OneHot.scala:48:45] wire _cur_max_value_T_8 = has_value_cat[8]; // @[OneHot.scala:48:45] wire _cur_max_value_T_9 = has_value_cat[9]; // @[OneHot.scala:48:45] wire _cur_max_value_T_10 = has_value_cat[10]; // @[OneHot.scala:48:45] wire _cur_max_value_T_11 = has_value_cat[11]; // @[OneHot.scala:48:45] wire _cur_max_value_T_12 = has_value_cat[12]; // @[OneHot.scala:48:45] wire _cur_max_value_T_13 = has_value_cat[13]; // @[OneHot.scala:48:45] wire _cur_max_value_T_14 = has_value_cat[14]; // @[OneHot.scala:48:45] wire _cur_max_value_T_15 = has_value_cat[15]; // @[OneHot.scala:48:45] wire _cur_max_value_T_16 = has_value_cat[16]; // @[OneHot.scala:48:45] wire _cur_max_value_T_17 = has_value_cat[17]; // @[OneHot.scala:48:45] wire _cur_max_value_T_18 = has_value_cat[18]; // @[OneHot.scala:48:45] wire _cur_max_value_T_19 = has_value_cat[19]; // @[OneHot.scala:48:45] wire _cur_max_value_T_20 = has_value_cat[20]; // @[OneHot.scala:48:45] wire _cur_max_value_T_21 = has_value_cat[21]; // @[OneHot.scala:48:45] wire _cur_max_value_T_22 = has_value_cat[22]; // @[OneHot.scala:48:45] wire _cur_max_value_T_23 = has_value_cat[23]; // @[OneHot.scala:48:45] wire _cur_max_value_T_24 = has_value_cat[24]; // @[OneHot.scala:48:45] wire _cur_max_value_T_25 = has_value_cat[25]; // @[OneHot.scala:48:45] wire _cur_max_value_T_26 = has_value_cat[26]; // @[OneHot.scala:48:45] wire _cur_max_value_T_27 = has_value_cat[27]; // @[OneHot.scala:48:45] wire _cur_max_value_T_28 = has_value_cat[28]; // @[OneHot.scala:48:45] wire _cur_max_value_T_29 = has_value_cat[29]; // @[OneHot.scala:48:45] wire _cur_max_value_T_30 = has_value_cat[30]; // @[OneHot.scala:48:45] wire _cur_max_value_T_31 = has_value_cat[31]; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_32 = {4'hF, ~_cur_max_value_T_30}; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_33 = _cur_max_value_T_29 ? 5'h1D : _cur_max_value_T_32; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_34 = _cur_max_value_T_28 ? 5'h1C : _cur_max_value_T_33; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_35 = _cur_max_value_T_27 ? 5'h1B : _cur_max_value_T_34; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_36 = _cur_max_value_T_26 ? 5'h1A : _cur_max_value_T_35; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_37 = _cur_max_value_T_25 ? 5'h19 : _cur_max_value_T_36; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_38 = _cur_max_value_T_24 ? 5'h18 : _cur_max_value_T_37; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_39 = _cur_max_value_T_23 ? 5'h17 : _cur_max_value_T_38; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_40 = _cur_max_value_T_22 ? 5'h16 : _cur_max_value_T_39; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_41 = _cur_max_value_T_21 ? 5'h15 : _cur_max_value_T_40; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_42 = _cur_max_value_T_20 ? 5'h14 : _cur_max_value_T_41; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_43 = _cur_max_value_T_19 ? 5'h13 : _cur_max_value_T_42; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_44 = _cur_max_value_T_18 ? 5'h12 : _cur_max_value_T_43; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_45 = _cur_max_value_T_17 ? 5'h11 : _cur_max_value_T_44; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_46 = _cur_max_value_T_16 ? 5'h10 : _cur_max_value_T_45; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_47 = _cur_max_value_T_15 ? 5'hF : _cur_max_value_T_46; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_48 = _cur_max_value_T_14 ? 5'hE : _cur_max_value_T_47; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_49 = _cur_max_value_T_13 ? 5'hD : _cur_max_value_T_48; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_50 = _cur_max_value_T_12 ? 5'hC : _cur_max_value_T_49; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_51 = _cur_max_value_T_11 ? 5'hB : _cur_max_value_T_50; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_52 = _cur_max_value_T_10 ? 5'hA : _cur_max_value_T_51; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_53 = _cur_max_value_T_9 ? 5'h9 : _cur_max_value_T_52; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_54 = _cur_max_value_T_8 ? 5'h8 : _cur_max_value_T_53; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_55 = _cur_max_value_T_7 ? 5'h7 : _cur_max_value_T_54; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_56 = _cur_max_value_T_6 ? 5'h6 : _cur_max_value_T_55; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_57 = _cur_max_value_T_5 ? 5'h5 : _cur_max_value_T_56; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_58 = _cur_max_value_T_4 ? 5'h4 : _cur_max_value_T_57; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_59 = _cur_max_value_T_3 ? 5'h3 : _cur_max_value_T_58; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_60 = _cur_max_value_T_2 ? 5'h2 : _cur_max_value_T_59; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_61 = _cur_max_value_T_1 ? 5'h1 : _cur_max_value_T_60; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_62 = _cur_max_value_T ? 5'h0 : _cur_max_value_T_61; // @[OneHot.scala:48:45] wire [5:0] _cur_max_value_T_63 = 6'h1F - {1'h0, _cur_max_value_T_62}; // @[Mux.scala:50:70] wire [4:0] cur_max_value = _cur_max_value_T_63[4:0]; // @[FSECompressorDicBuilder.scala:196:48] wire _T_839 = dicBuilderState == 4'h1; // @[FSECompressorDicBuilder.scala:156:32, :198:25] wire [32:0] _GEN_0 = {1'h0, ll_count_0} + {30'h0, stat_sum_0}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_0_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_0_T = _GEN_0; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_0_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_0_T_2 = _GEN_0; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_0_T_1 = _ll_count_0_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_1 = {1'h0, ll_count_1} + {30'h0, stat_sum_1}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_1_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_1_T = _GEN_1; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_1_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_1_T_2 = _GEN_1; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_1_T_1 = _ll_count_1_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_2 = {1'h0, ll_count_2} + {30'h0, stat_sum_2}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_2_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_2_T = _GEN_2; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_2_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_2_T_2 = _GEN_2; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_2_T_1 = _ll_count_2_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_3 = {1'h0, ll_count_3} + {30'h0, stat_sum_3}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_3_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_3_T = _GEN_3; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_3_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_3_T_2 = _GEN_3; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_3_T_1 = _ll_count_3_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_4 = {1'h0, ll_count_4} + {30'h0, stat_sum_4}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_4_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_4_T = _GEN_4; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_4_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_4_T_2 = _GEN_4; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_4_T_1 = _ll_count_4_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_5 = {1'h0, ll_count_5} + {30'h0, stat_sum_5}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_5_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_5_T = _GEN_5; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_5_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_5_T_2 = _GEN_5; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_5_T_1 = _ll_count_5_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_6 = {1'h0, ll_count_6} + {30'h0, stat_sum_6}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_6_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_6_T = _GEN_6; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_6_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_6_T_2 = _GEN_6; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_6_T_1 = _ll_count_6_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_7 = {1'h0, ll_count_7} + {30'h0, stat_sum_7}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_7_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_7_T = _GEN_7; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_7_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_7_T_2 = _GEN_7; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_7_T_1 = _ll_count_7_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_8 = {1'h0, ll_count_8} + {30'h0, stat_sum_8}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_8_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_8_T = _GEN_8; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_8_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_8_T_2 = _GEN_8; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_8_T_1 = _ll_count_8_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_9 = {1'h0, ll_count_9} + {30'h0, stat_sum_9}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_9_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_9_T = _GEN_9; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_9_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_9_T_2 = _GEN_9; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_9_T_1 = _ll_count_9_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_10 = {1'h0, ll_count_10} + {30'h0, stat_sum_10}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_10_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_10_T = _GEN_10; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_10_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_10_T_2 = _GEN_10; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_10_T_1 = _ll_count_10_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_11 = {1'h0, ll_count_11} + {30'h0, stat_sum_11}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_11_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_11_T = _GEN_11; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_11_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_11_T_2 = _GEN_11; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_11_T_1 = _ll_count_11_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_12 = {1'h0, ll_count_12} + {30'h0, stat_sum_12}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_12_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_12_T = _GEN_12; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_12_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_12_T_2 = _GEN_12; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_12_T_1 = _ll_count_12_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_13 = {1'h0, ll_count_13} + {30'h0, stat_sum_13}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_13_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_13_T = _GEN_13; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_13_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_13_T_2 = _GEN_13; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_13_T_1 = _ll_count_13_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_14 = {1'h0, ll_count_14} + {30'h0, stat_sum_14}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_14_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_14_T = _GEN_14; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_14_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_14_T_2 = _GEN_14; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_14_T_1 = _ll_count_14_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_15 = {1'h0, ll_count_15} + {30'h0, stat_sum_15}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_15_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_15_T = _GEN_15; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_15_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_15_T_2 = _GEN_15; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_15_T_1 = _ll_count_15_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_16 = {1'h0, ll_count_16} + {30'h0, stat_sum_16}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_16_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_16_T = _GEN_16; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_16_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_16_T_2 = _GEN_16; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_16_T_1 = _ll_count_16_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_17 = {1'h0, ll_count_17} + {30'h0, stat_sum_17}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_17_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_17_T = _GEN_17; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_17_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_17_T_2 = _GEN_17; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_17_T_1 = _ll_count_17_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_18 = {1'h0, ll_count_18} + {30'h0, stat_sum_18}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_18_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_18_T = _GEN_18; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_18_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_18_T_2 = _GEN_18; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_18_T_1 = _ll_count_18_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_19 = {1'h0, ll_count_19} + {30'h0, stat_sum_19}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_19_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_19_T = _GEN_19; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_19_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_19_T_2 = _GEN_19; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_19_T_1 = _ll_count_19_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_20 = {1'h0, ll_count_20} + {30'h0, stat_sum_20}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_20_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_20_T = _GEN_20; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_20_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_20_T_2 = _GEN_20; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_20_T_1 = _ll_count_20_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_21 = {1'h0, ll_count_21} + {30'h0, stat_sum_21}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_21_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_21_T = _GEN_21; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_21_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_21_T_2 = _GEN_21; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_21_T_1 = _ll_count_21_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_22 = {1'h0, ll_count_22} + {30'h0, stat_sum_22}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_22_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_22_T = _GEN_22; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_22_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_22_T_2 = _GEN_22; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_22_T_1 = _ll_count_22_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_23 = {1'h0, ll_count_23} + {30'h0, stat_sum_23}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_23_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_23_T = _GEN_23; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_23_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_23_T_2 = _GEN_23; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_23_T_1 = _ll_count_23_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_24 = {1'h0, ll_count_24} + {30'h0, stat_sum_24}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_24_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_24_T = _GEN_24; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_24_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_24_T_2 = _GEN_24; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_24_T_1 = _ll_count_24_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_25 = {1'h0, ll_count_25} + {30'h0, stat_sum_25}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_25_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_25_T = _GEN_25; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_25_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_25_T_2 = _GEN_25; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_25_T_1 = _ll_count_25_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_26 = {1'h0, ll_count_26} + {30'h0, stat_sum_26}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_26_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_26_T = _GEN_26; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_26_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_26_T_2 = _GEN_26; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_26_T_1 = _ll_count_26_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_27 = {1'h0, ll_count_27} + {30'h0, stat_sum_27}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_27_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_27_T = _GEN_27; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_27_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_27_T_2 = _GEN_27; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_27_T_1 = _ll_count_27_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_28 = {1'h0, ll_count_28} + {30'h0, stat_sum_28}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_28_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_28_T = _GEN_28; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_28_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_28_T_2 = _GEN_28; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_28_T_1 = _ll_count_28_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_29 = {1'h0, ll_count_29} + {30'h0, stat_sum_29}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_29_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_29_T = _GEN_29; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_29_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_29_T_2 = _GEN_29; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_29_T_1 = _ll_count_29_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_30 = {1'h0, ll_count_30} + {30'h0, stat_sum_30}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_30_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_30_T = _GEN_30; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_30_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_30_T_2 = _GEN_30; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_30_T_1 = _ll_count_30_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_31 = {1'h0, ll_count_31} + {30'h0, stat_sum_31}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_31_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_31_T = _GEN_31; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_31_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_31_T_2 = _GEN_31; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_31_T_1 = _ll_count_31_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [31:0] _GEN_32 = {27'h0, cur_max_value}; // @[FSECompressorDicBuilder.scala:196:48, :204:54] wire _GEN_33 = ll_max_symbol_value > _GEN_32; // @[FSECompressorDicBuilder.scala:170:36, :204:54] wire _ll_max_symbol_value_T; // @[FSECompressorDicBuilder.scala:204:54] assign _ll_max_symbol_value_T = _GEN_33; // @[FSECompressorDicBuilder.scala:204:54] wire _ll_max_symbol_value_T_2; // @[FSECompressorDicBuilder.scala:569:56] assign _ll_max_symbol_value_T_2 = _GEN_33; // @[FSECompressorDicBuilder.scala:204:54, :569:56] wire [31:0] _ll_max_symbol_value_T_1 = _ll_max_symbol_value_T ? ll_max_symbol_value : _GEN_32; // @[FSECompressorDicBuilder.scala:170:36, :204:{33,54}] wire ll_useLowProbCount = ll_nbseq_1 > 64'hFFFFFFFE; // @[FSECompressorDicBuilder.scala:171:27, :248:39] wire [15:0] _ll_lowProbCount_T; // @[FSECompressorDicBuilder.scala:250:25] wire [15:0] ll_lowProbCount; // @[FSECompressorDicBuilder.scala:249:29] assign _ll_lowProbCount_T = ll_useLowProbCount ? 16'hFFFF : 16'h1; // @[FSECompressorDicBuilder.scala:248:39, :250:25] assign ll_lowProbCount = _ll_lowProbCount_T; // @[FSECompressorDicBuilder.scala:249:29, :250:25] wire [63:0] ll_step; // @[FSECompressorDicBuilder.scala:253:21] wire [63:0] _GEN_34 = 64'h4000000000000000 / ll_nbseq_1; // @[FSECompressorDicBuilder.scala:171:27, :254:47] wire [62:0] _ll_step_T = _GEN_34[62:0]; // @[FSECompressorDicBuilder.scala:254:47] assign ll_step = {1'h0, _ll_step_T}; // @[FSECompressorDicBuilder.scala:253:21, :254:{11,47}] wire [31:0] ll_lowThreshold; // @[FSECompressorDicBuilder.scala:260:29] wire [63:0] _ll_lowThreshold_T = {6'h0, ll_nbseq_1[63:6]}; // @[FSECompressorDicBuilder.scala:171:27, :261:33] assign ll_lowThreshold = _ll_lowThreshold_T[31:0]; // @[FSECompressorDicBuilder.scala:260:29, :261:{19,33}] wire [15:0] ll_proba_base_0; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_1; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_2; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_3; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_4; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_5; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_6; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_7; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_8; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_9; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_10; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_11; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_12; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_13; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_14; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_15; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_16; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_17; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_18; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_19; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_20; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_21; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_22; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_23; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_24; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_25; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_26; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_27; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_28; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_29; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_30; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_31; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] _ll_proba_0_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_1_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_2_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_3_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_4_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_5_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_6_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_7_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_8_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_9_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_10_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_11_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_12_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_13_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_14_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_15_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_16_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_17_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_18_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_19_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_20_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_21_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_22_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_23_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_24_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_25_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_26_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_27_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_28_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_29_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_30_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_31_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] ll_proba_0; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_1; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_2; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_3; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_4; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_5; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_6; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_7; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_8; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_9; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_10; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_11; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_12; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_13; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_14; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_15; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_16; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_17; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_18; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_19; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_20; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_21; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_22; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_23; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_24; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_25; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_26; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_27; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_28; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_29; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_30; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_31; // @[FSECompressorDicBuilder.scala:265:26] wire [63:0] ll_count_times_step_0; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_1; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_2; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_3; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_4; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_5; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_6; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_7; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_8; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_9; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_10; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_11; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_12; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_13; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_14; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_15; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_16; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_17; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_18; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_19; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_20; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_21; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_22; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_23; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_24; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_25; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_26; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_27; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_28; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_29; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_30; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_31; // @[FSECompressorDicBuilder.scala:266:37] wire [95:0] _GEN_35 = {32'h0, ll_step}; // @[FSECompressorDicBuilder.scala:253:21, :268:43] wire [95:0] _GEN_36 = {64'h0, ll_count_0} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_0_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_0_T = _GEN_36; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T = _GEN_36; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_0 = _ll_count_times_step_0_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_0_T = {56'h0, ll_count_times_step_0[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_0 = _ll_proba_base_0_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T = ll_proba_base_0[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [7:0][31:0] _GEN_37 = {{rtbTable_7}, {rtbTable_6}, {rtbTable_5}, {rtbTable_4}, {rtbTable_3}, {rtbTable_2}, {rtbTable_1}, {32'h0}}; // @[FSECompressorDicBuilder.scala:57:25, :271:31] wire [95:0] restToBeat = {28'h0, _GEN_37[_restToBeat_T], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_1 = {71'h0, ll_proba_base_0, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_2 = {48'h0, _ll_add_to_proba_base_T} - {1'h0, _ll_add_to_proba_base_T_1}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_3 = _ll_add_to_proba_base_T_2[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_4 = _ll_add_to_proba_base_T_3 > {47'h0, restToBeat}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base = _ll_add_to_proba_base_T_4; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_0_T = ll_proba_base_0 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_0_T_1 = {1'h0, ll_proba_base_0} + {16'h0, ll_add_to_proba_base}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_0_T_2 = _ll_proba_0_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_0_T_3 = _ll_proba_0_T ? _ll_proba_0_T_2 : ll_proba_base_0; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_0 = _ll_proba_0_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_38 = {64'h0, ll_count_1} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_1_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_1_T = _GEN_38; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_5; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_5 = _GEN_38; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_1 = _ll_count_times_step_1_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_1_T = {56'h0, ll_count_times_step_1[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_1 = _ll_proba_base_1_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_1 = ll_proba_base_1[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_1 = {28'h0, _GEN_37[_restToBeat_T_1], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_6 = {71'h0, ll_proba_base_1, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_7 = {48'h0, _ll_add_to_proba_base_T_5} - {1'h0, _ll_add_to_proba_base_T_6}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_8 = _ll_add_to_proba_base_T_7[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_9 = _ll_add_to_proba_base_T_8 > {47'h0, restToBeat_1}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_1 = _ll_add_to_proba_base_T_9; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_1_T = ll_proba_base_1 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_1_T_1 = {1'h0, ll_proba_base_1} + {16'h0, ll_add_to_proba_base_1}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_1_T_2 = _ll_proba_1_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_1_T_3 = _ll_proba_1_T ? _ll_proba_1_T_2 : ll_proba_base_1; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_1 = _ll_proba_1_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_39 = {64'h0, ll_count_2} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_2_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_2_T = _GEN_39; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_10; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_10 = _GEN_39; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_2 = _ll_count_times_step_2_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_2_T = {56'h0, ll_count_times_step_2[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_2 = _ll_proba_base_2_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_2 = ll_proba_base_2[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_2 = {28'h0, _GEN_37[_restToBeat_T_2], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_11 = {71'h0, ll_proba_base_2, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_12 = {48'h0, _ll_add_to_proba_base_T_10} - {1'h0, _ll_add_to_proba_base_T_11}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_13 = _ll_add_to_proba_base_T_12[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_14 = _ll_add_to_proba_base_T_13 > {47'h0, restToBeat_2}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_2 = _ll_add_to_proba_base_T_14; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_2_T = ll_proba_base_2 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_2_T_1 = {1'h0, ll_proba_base_2} + {16'h0, ll_add_to_proba_base_2}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_2_T_2 = _ll_proba_2_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_2_T_3 = _ll_proba_2_T ? _ll_proba_2_T_2 : ll_proba_base_2; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_2 = _ll_proba_2_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_40 = {64'h0, ll_count_3} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_3_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_3_T = _GEN_40; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_15; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_15 = _GEN_40; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_3 = _ll_count_times_step_3_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_3_T = {56'h0, ll_count_times_step_3[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_3 = _ll_proba_base_3_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_3 = ll_proba_base_3[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_3 = {28'h0, _GEN_37[_restToBeat_T_3], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_16 = {71'h0, ll_proba_base_3, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_17 = {48'h0, _ll_add_to_proba_base_T_15} - {1'h0, _ll_add_to_proba_base_T_16}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_18 = _ll_add_to_proba_base_T_17[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_19 = _ll_add_to_proba_base_T_18 > {47'h0, restToBeat_3}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_3 = _ll_add_to_proba_base_T_19; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_3_T = ll_proba_base_3 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_3_T_1 = {1'h0, ll_proba_base_3} + {16'h0, ll_add_to_proba_base_3}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_3_T_2 = _ll_proba_3_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_3_T_3 = _ll_proba_3_T ? _ll_proba_3_T_2 : ll_proba_base_3; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_3 = _ll_proba_3_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_41 = {64'h0, ll_count_4} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_4_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_4_T = _GEN_41; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_20; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_20 = _GEN_41; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_4 = _ll_count_times_step_4_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_4_T = {56'h0, ll_count_times_step_4[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_4 = _ll_proba_base_4_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_4 = ll_proba_base_4[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_4 = {28'h0, _GEN_37[_restToBeat_T_4], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_21 = {71'h0, ll_proba_base_4, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_22 = {48'h0, _ll_add_to_proba_base_T_20} - {1'h0, _ll_add_to_proba_base_T_21}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_23 = _ll_add_to_proba_base_T_22[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_24 = _ll_add_to_proba_base_T_23 > {47'h0, restToBeat_4}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_4 = _ll_add_to_proba_base_T_24; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_4_T = ll_proba_base_4 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_4_T_1 = {1'h0, ll_proba_base_4} + {16'h0, ll_add_to_proba_base_4}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_4_T_2 = _ll_proba_4_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_4_T_3 = _ll_proba_4_T ? _ll_proba_4_T_2 : ll_proba_base_4; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_4 = _ll_proba_4_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_42 = {64'h0, ll_count_5} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_5_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_5_T = _GEN_42; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_25; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_25 = _GEN_42; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_5 = _ll_count_times_step_5_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_5_T = {56'h0, ll_count_times_step_5[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_5 = _ll_proba_base_5_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_5 = ll_proba_base_5[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_5 = {28'h0, _GEN_37[_restToBeat_T_5], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_26 = {71'h0, ll_proba_base_5, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_27 = {48'h0, _ll_add_to_proba_base_T_25} - {1'h0, _ll_add_to_proba_base_T_26}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_28 = _ll_add_to_proba_base_T_27[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_29 = _ll_add_to_proba_base_T_28 > {47'h0, restToBeat_5}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_5 = _ll_add_to_proba_base_T_29; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_5_T = ll_proba_base_5 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_5_T_1 = {1'h0, ll_proba_base_5} + {16'h0, ll_add_to_proba_base_5}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_5_T_2 = _ll_proba_5_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_5_T_3 = _ll_proba_5_T ? _ll_proba_5_T_2 : ll_proba_base_5; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_5 = _ll_proba_5_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_43 = {64'h0, ll_count_6} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_6_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_6_T = _GEN_43; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_30; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_30 = _GEN_43; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_6 = _ll_count_times_step_6_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_6_T = {56'h0, ll_count_times_step_6[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_6 = _ll_proba_base_6_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_6 = ll_proba_base_6[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_6 = {28'h0, _GEN_37[_restToBeat_T_6], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_31 = {71'h0, ll_proba_base_6, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_32 = {48'h0, _ll_add_to_proba_base_T_30} - {1'h0, _ll_add_to_proba_base_T_31}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_33 = _ll_add_to_proba_base_T_32[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_34 = _ll_add_to_proba_base_T_33 > {47'h0, restToBeat_6}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_6 = _ll_add_to_proba_base_T_34; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_6_T = ll_proba_base_6 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_6_T_1 = {1'h0, ll_proba_base_6} + {16'h0, ll_add_to_proba_base_6}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_6_T_2 = _ll_proba_6_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_6_T_3 = _ll_proba_6_T ? _ll_proba_6_T_2 : ll_proba_base_6; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_6 = _ll_proba_6_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_44 = {64'h0, ll_count_7} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_7_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_7_T = _GEN_44; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_35; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_35 = _GEN_44; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_7 = _ll_count_times_step_7_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_7_T = {56'h0, ll_count_times_step_7[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_7 = _ll_proba_base_7_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_7 = ll_proba_base_7[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_7 = {28'h0, _GEN_37[_restToBeat_T_7], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_36 = {71'h0, ll_proba_base_7, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_37 = {48'h0, _ll_add_to_proba_base_T_35} - {1'h0, _ll_add_to_proba_base_T_36}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_38 = _ll_add_to_proba_base_T_37[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_39 = _ll_add_to_proba_base_T_38 > {47'h0, restToBeat_7}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_7 = _ll_add_to_proba_base_T_39; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_7_T = ll_proba_base_7 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_7_T_1 = {1'h0, ll_proba_base_7} + {16'h0, ll_add_to_proba_base_7}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_7_T_2 = _ll_proba_7_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_7_T_3 = _ll_proba_7_T ? _ll_proba_7_T_2 : ll_proba_base_7; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_7 = _ll_proba_7_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_45 = {64'h0, ll_count_8} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_8_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_8_T = _GEN_45; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_40; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_40 = _GEN_45; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_8 = _ll_count_times_step_8_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_8_T = {56'h0, ll_count_times_step_8[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_8 = _ll_proba_base_8_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_8 = ll_proba_base_8[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_8 = {28'h0, _GEN_37[_restToBeat_T_8], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_41 = {71'h0, ll_proba_base_8, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_42 = {48'h0, _ll_add_to_proba_base_T_40} - {1'h0, _ll_add_to_proba_base_T_41}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_43 = _ll_add_to_proba_base_T_42[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_44 = _ll_add_to_proba_base_T_43 > {47'h0, restToBeat_8}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_8 = _ll_add_to_proba_base_T_44; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_8_T = ll_proba_base_8 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_8_T_1 = {1'h0, ll_proba_base_8} + {16'h0, ll_add_to_proba_base_8}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_8_T_2 = _ll_proba_8_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_8_T_3 = _ll_proba_8_T ? _ll_proba_8_T_2 : ll_proba_base_8; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_8 = _ll_proba_8_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_46 = {64'h0, ll_count_9} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_9_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_9_T = _GEN_46; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_45; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_45 = _GEN_46; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_9 = _ll_count_times_step_9_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_9_T = {56'h0, ll_count_times_step_9[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_9 = _ll_proba_base_9_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_9 = ll_proba_base_9[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_9 = {28'h0, _GEN_37[_restToBeat_T_9], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_46 = {71'h0, ll_proba_base_9, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_47 = {48'h0, _ll_add_to_proba_base_T_45} - {1'h0, _ll_add_to_proba_base_T_46}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_48 = _ll_add_to_proba_base_T_47[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_49 = _ll_add_to_proba_base_T_48 > {47'h0, restToBeat_9}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_9 = _ll_add_to_proba_base_T_49; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_9_T = ll_proba_base_9 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_9_T_1 = {1'h0, ll_proba_base_9} + {16'h0, ll_add_to_proba_base_9}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_9_T_2 = _ll_proba_9_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_9_T_3 = _ll_proba_9_T ? _ll_proba_9_T_2 : ll_proba_base_9; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_9 = _ll_proba_9_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_47 = {64'h0, ll_count_10} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_10_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_10_T = _GEN_47; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_50; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_50 = _GEN_47; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_10 = _ll_count_times_step_10_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_10_T = {56'h0, ll_count_times_step_10[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_10 = _ll_proba_base_10_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_10 = ll_proba_base_10[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_10 = {28'h0, _GEN_37[_restToBeat_T_10], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_51 = {71'h0, ll_proba_base_10, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_52 = {48'h0, _ll_add_to_proba_base_T_50} - {1'h0, _ll_add_to_proba_base_T_51}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_53 = _ll_add_to_proba_base_T_52[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_54 = _ll_add_to_proba_base_T_53 > {47'h0, restToBeat_10}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_10 = _ll_add_to_proba_base_T_54; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_10_T = ll_proba_base_10 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_10_T_1 = {1'h0, ll_proba_base_10} + {16'h0, ll_add_to_proba_base_10}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_10_T_2 = _ll_proba_10_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_10_T_3 = _ll_proba_10_T ? _ll_proba_10_T_2 : ll_proba_base_10; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_10 = _ll_proba_10_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_48 = {64'h0, ll_count_11} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_11_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_11_T = _GEN_48; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_55; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_55 = _GEN_48; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_11 = _ll_count_times_step_11_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_11_T = {56'h0, ll_count_times_step_11[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_11 = _ll_proba_base_11_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_11 = ll_proba_base_11[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_11 = {28'h0, _GEN_37[_restToBeat_T_11], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_56 = {71'h0, ll_proba_base_11, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_57 = {48'h0, _ll_add_to_proba_base_T_55} - {1'h0, _ll_add_to_proba_base_T_56}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_58 = _ll_add_to_proba_base_T_57[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_59 = _ll_add_to_proba_base_T_58 > {47'h0, restToBeat_11}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_11 = _ll_add_to_proba_base_T_59; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_11_T = ll_proba_base_11 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_11_T_1 = {1'h0, ll_proba_base_11} + {16'h0, ll_add_to_proba_base_11}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_11_T_2 = _ll_proba_11_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_11_T_3 = _ll_proba_11_T ? _ll_proba_11_T_2 : ll_proba_base_11; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_11 = _ll_proba_11_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_49 = {64'h0, ll_count_12} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_12_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_12_T = _GEN_49; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_60; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_60 = _GEN_49; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_12 = _ll_count_times_step_12_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_12_T = {56'h0, ll_count_times_step_12[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_12 = _ll_proba_base_12_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_12 = ll_proba_base_12[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_12 = {28'h0, _GEN_37[_restToBeat_T_12], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_61 = {71'h0, ll_proba_base_12, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_62 = {48'h0, _ll_add_to_proba_base_T_60} - {1'h0, _ll_add_to_proba_base_T_61}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_63 = _ll_add_to_proba_base_T_62[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_64 = _ll_add_to_proba_base_T_63 > {47'h0, restToBeat_12}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_12 = _ll_add_to_proba_base_T_64; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_12_T = ll_proba_base_12 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_12_T_1 = {1'h0, ll_proba_base_12} + {16'h0, ll_add_to_proba_base_12}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_12_T_2 = _ll_proba_12_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_12_T_3 = _ll_proba_12_T ? _ll_proba_12_T_2 : ll_proba_base_12; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_12 = _ll_proba_12_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_50 = {64'h0, ll_count_13} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_13_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_13_T = _GEN_50; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_65; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_65 = _GEN_50; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_13 = _ll_count_times_step_13_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_13_T = {56'h0, ll_count_times_step_13[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_13 = _ll_proba_base_13_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_13 = ll_proba_base_13[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_13 = {28'h0, _GEN_37[_restToBeat_T_13], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_66 = {71'h0, ll_proba_base_13, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_67 = {48'h0, _ll_add_to_proba_base_T_65} - {1'h0, _ll_add_to_proba_base_T_66}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_68 = _ll_add_to_proba_base_T_67[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_69 = _ll_add_to_proba_base_T_68 > {47'h0, restToBeat_13}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_13 = _ll_add_to_proba_base_T_69; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_13_T = ll_proba_base_13 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_13_T_1 = {1'h0, ll_proba_base_13} + {16'h0, ll_add_to_proba_base_13}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_13_T_2 = _ll_proba_13_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_13_T_3 = _ll_proba_13_T ? _ll_proba_13_T_2 : ll_proba_base_13; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_13 = _ll_proba_13_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_51 = {64'h0, ll_count_14} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_14_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_14_T = _GEN_51; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_70; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_70 = _GEN_51; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_14 = _ll_count_times_step_14_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_14_T = {56'h0, ll_count_times_step_14[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_14 = _ll_proba_base_14_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_14 = ll_proba_base_14[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_14 = {28'h0, _GEN_37[_restToBeat_T_14], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_71 = {71'h0, ll_proba_base_14, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_72 = {48'h0, _ll_add_to_proba_base_T_70} - {1'h0, _ll_add_to_proba_base_T_71}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_73 = _ll_add_to_proba_base_T_72[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_74 = _ll_add_to_proba_base_T_73 > {47'h0, restToBeat_14}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_14 = _ll_add_to_proba_base_T_74; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_14_T = ll_proba_base_14 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_14_T_1 = {1'h0, ll_proba_base_14} + {16'h0, ll_add_to_proba_base_14}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_14_T_2 = _ll_proba_14_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_14_T_3 = _ll_proba_14_T ? _ll_proba_14_T_2 : ll_proba_base_14; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_14 = _ll_proba_14_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_52 = {64'h0, ll_count_15} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_15_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_15_T = _GEN_52; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_75; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_75 = _GEN_52; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_15 = _ll_count_times_step_15_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_15_T = {56'h0, ll_count_times_step_15[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_15 = _ll_proba_base_15_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_15 = ll_proba_base_15[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_15 = {28'h0, _GEN_37[_restToBeat_T_15], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_76 = {71'h0, ll_proba_base_15, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_77 = {48'h0, _ll_add_to_proba_base_T_75} - {1'h0, _ll_add_to_proba_base_T_76}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_78 = _ll_add_to_proba_base_T_77[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_79 = _ll_add_to_proba_base_T_78 > {47'h0, restToBeat_15}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_15 = _ll_add_to_proba_base_T_79; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_15_T = ll_proba_base_15 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_15_T_1 = {1'h0, ll_proba_base_15} + {16'h0, ll_add_to_proba_base_15}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_15_T_2 = _ll_proba_15_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_15_T_3 = _ll_proba_15_T ? _ll_proba_15_T_2 : ll_proba_base_15; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_15 = _ll_proba_15_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_53 = {64'h0, ll_count_16} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_16_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_16_T = _GEN_53; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_80; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_80 = _GEN_53; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_16 = _ll_count_times_step_16_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_16_T = {56'h0, ll_count_times_step_16[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_16 = _ll_proba_base_16_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_16 = ll_proba_base_16[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_16 = {28'h0, _GEN_37[_restToBeat_T_16], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_81 = {71'h0, ll_proba_base_16, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_82 = {48'h0, _ll_add_to_proba_base_T_80} - {1'h0, _ll_add_to_proba_base_T_81}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_83 = _ll_add_to_proba_base_T_82[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_84 = _ll_add_to_proba_base_T_83 > {47'h0, restToBeat_16}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_16 = _ll_add_to_proba_base_T_84; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_16_T = ll_proba_base_16 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_16_T_1 = {1'h0, ll_proba_base_16} + {16'h0, ll_add_to_proba_base_16}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_16_T_2 = _ll_proba_16_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_16_T_3 = _ll_proba_16_T ? _ll_proba_16_T_2 : ll_proba_base_16; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_16 = _ll_proba_16_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_54 = {64'h0, ll_count_17} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_17_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_17_T = _GEN_54; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_85; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_85 = _GEN_54; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_17 = _ll_count_times_step_17_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_17_T = {56'h0, ll_count_times_step_17[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_17 = _ll_proba_base_17_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_17 = ll_proba_base_17[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_17 = {28'h0, _GEN_37[_restToBeat_T_17], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_86 = {71'h0, ll_proba_base_17, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_87 = {48'h0, _ll_add_to_proba_base_T_85} - {1'h0, _ll_add_to_proba_base_T_86}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_88 = _ll_add_to_proba_base_T_87[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_89 = _ll_add_to_proba_base_T_88 > {47'h0, restToBeat_17}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_17 = _ll_add_to_proba_base_T_89; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_17_T = ll_proba_base_17 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_17_T_1 = {1'h0, ll_proba_base_17} + {16'h0, ll_add_to_proba_base_17}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_17_T_2 = _ll_proba_17_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_17_T_3 = _ll_proba_17_T ? _ll_proba_17_T_2 : ll_proba_base_17; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_17 = _ll_proba_17_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_55 = {64'h0, ll_count_18} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_18_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_18_T = _GEN_55; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_90; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_90 = _GEN_55; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_18 = _ll_count_times_step_18_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_18_T = {56'h0, ll_count_times_step_18[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_18 = _ll_proba_base_18_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_18 = ll_proba_base_18[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_18 = {28'h0, _GEN_37[_restToBeat_T_18], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_91 = {71'h0, ll_proba_base_18, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_92 = {48'h0, _ll_add_to_proba_base_T_90} - {1'h0, _ll_add_to_proba_base_T_91}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_93 = _ll_add_to_proba_base_T_92[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_94 = _ll_add_to_proba_base_T_93 > {47'h0, restToBeat_18}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_18 = _ll_add_to_proba_base_T_94; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_18_T = ll_proba_base_18 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_18_T_1 = {1'h0, ll_proba_base_18} + {16'h0, ll_add_to_proba_base_18}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_18_T_2 = _ll_proba_18_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_18_T_3 = _ll_proba_18_T ? _ll_proba_18_T_2 : ll_proba_base_18; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_18 = _ll_proba_18_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_56 = {64'h0, ll_count_19} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_19_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_19_T = _GEN_56; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_95; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_95 = _GEN_56; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_19 = _ll_count_times_step_19_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_19_T = {56'h0, ll_count_times_step_19[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_19 = _ll_proba_base_19_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_19 = ll_proba_base_19[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_19 = {28'h0, _GEN_37[_restToBeat_T_19], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_96 = {71'h0, ll_proba_base_19, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_97 = {48'h0, _ll_add_to_proba_base_T_95} - {1'h0, _ll_add_to_proba_base_T_96}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_98 = _ll_add_to_proba_base_T_97[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_99 = _ll_add_to_proba_base_T_98 > {47'h0, restToBeat_19}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_19 = _ll_add_to_proba_base_T_99; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_19_T = ll_proba_base_19 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_19_T_1 = {1'h0, ll_proba_base_19} + {16'h0, ll_add_to_proba_base_19}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_19_T_2 = _ll_proba_19_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_19_T_3 = _ll_proba_19_T ? _ll_proba_19_T_2 : ll_proba_base_19; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_19 = _ll_proba_19_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_57 = {64'h0, ll_count_20} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_20_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_20_T = _GEN_57; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_100; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_100 = _GEN_57; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_20 = _ll_count_times_step_20_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_20_T = {56'h0, ll_count_times_step_20[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_20 = _ll_proba_base_20_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_20 = ll_proba_base_20[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_20 = {28'h0, _GEN_37[_restToBeat_T_20], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_101 = {71'h0, ll_proba_base_20, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_102 = {48'h0, _ll_add_to_proba_base_T_100} - {1'h0, _ll_add_to_proba_base_T_101}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_103 = _ll_add_to_proba_base_T_102[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_104 = _ll_add_to_proba_base_T_103 > {47'h0, restToBeat_20}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_20 = _ll_add_to_proba_base_T_104; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_20_T = ll_proba_base_20 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_20_T_1 = {1'h0, ll_proba_base_20} + {16'h0, ll_add_to_proba_base_20}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_20_T_2 = _ll_proba_20_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_20_T_3 = _ll_proba_20_T ? _ll_proba_20_T_2 : ll_proba_base_20; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_20 = _ll_proba_20_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_58 = {64'h0, ll_count_21} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_21_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_21_T = _GEN_58; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_105; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_105 = _GEN_58; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_21 = _ll_count_times_step_21_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_21_T = {56'h0, ll_count_times_step_21[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_21 = _ll_proba_base_21_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_21 = ll_proba_base_21[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_21 = {28'h0, _GEN_37[_restToBeat_T_21], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_106 = {71'h0, ll_proba_base_21, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_107 = {48'h0, _ll_add_to_proba_base_T_105} - {1'h0, _ll_add_to_proba_base_T_106}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_108 = _ll_add_to_proba_base_T_107[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_109 = _ll_add_to_proba_base_T_108 > {47'h0, restToBeat_21}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_21 = _ll_add_to_proba_base_T_109; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_21_T = ll_proba_base_21 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_21_T_1 = {1'h0, ll_proba_base_21} + {16'h0, ll_add_to_proba_base_21}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_21_T_2 = _ll_proba_21_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_21_T_3 = _ll_proba_21_T ? _ll_proba_21_T_2 : ll_proba_base_21; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_21 = _ll_proba_21_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_59 = {64'h0, ll_count_22} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_22_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_22_T = _GEN_59; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_110; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_110 = _GEN_59; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_22 = _ll_count_times_step_22_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_22_T = {56'h0, ll_count_times_step_22[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_22 = _ll_proba_base_22_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_22 = ll_proba_base_22[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_22 = {28'h0, _GEN_37[_restToBeat_T_22], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_111 = {71'h0, ll_proba_base_22, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_112 = {48'h0, _ll_add_to_proba_base_T_110} - {1'h0, _ll_add_to_proba_base_T_111}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_113 = _ll_add_to_proba_base_T_112[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_114 = _ll_add_to_proba_base_T_113 > {47'h0, restToBeat_22}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_22 = _ll_add_to_proba_base_T_114; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_22_T = ll_proba_base_22 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_22_T_1 = {1'h0, ll_proba_base_22} + {16'h0, ll_add_to_proba_base_22}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_22_T_2 = _ll_proba_22_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_22_T_3 = _ll_proba_22_T ? _ll_proba_22_T_2 : ll_proba_base_22; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_22 = _ll_proba_22_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_60 = {64'h0, ll_count_23} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_23_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_23_T = _GEN_60; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_115; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_115 = _GEN_60; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_23 = _ll_count_times_step_23_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_23_T = {56'h0, ll_count_times_step_23[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_23 = _ll_proba_base_23_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_23 = ll_proba_base_23[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_23 = {28'h0, _GEN_37[_restToBeat_T_23], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_116 = {71'h0, ll_proba_base_23, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_117 = {48'h0, _ll_add_to_proba_base_T_115} - {1'h0, _ll_add_to_proba_base_T_116}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_118 = _ll_add_to_proba_base_T_117[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_119 = _ll_add_to_proba_base_T_118 > {47'h0, restToBeat_23}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_23 = _ll_add_to_proba_base_T_119; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_23_T = ll_proba_base_23 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_23_T_1 = {1'h0, ll_proba_base_23} + {16'h0, ll_add_to_proba_base_23}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_23_T_2 = _ll_proba_23_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_23_T_3 = _ll_proba_23_T ? _ll_proba_23_T_2 : ll_proba_base_23; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_23 = _ll_proba_23_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_61 = {64'h0, ll_count_24} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_24_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_24_T = _GEN_61; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_120; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_120 = _GEN_61; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_24 = _ll_count_times_step_24_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_24_T = {56'h0, ll_count_times_step_24[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_24 = _ll_proba_base_24_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_24 = ll_proba_base_24[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_24 = {28'h0, _GEN_37[_restToBeat_T_24], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_121 = {71'h0, ll_proba_base_24, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_122 = {48'h0, _ll_add_to_proba_base_T_120} - {1'h0, _ll_add_to_proba_base_T_121}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_123 = _ll_add_to_proba_base_T_122[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_124 = _ll_add_to_proba_base_T_123 > {47'h0, restToBeat_24}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_24 = _ll_add_to_proba_base_T_124; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_24_T = ll_proba_base_24 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_24_T_1 = {1'h0, ll_proba_base_24} + {16'h0, ll_add_to_proba_base_24}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_24_T_2 = _ll_proba_24_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_24_T_3 = _ll_proba_24_T ? _ll_proba_24_T_2 : ll_proba_base_24; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_24 = _ll_proba_24_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_62 = {64'h0, ll_count_25} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_25_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_25_T = _GEN_62; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_125; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_125 = _GEN_62; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_25 = _ll_count_times_step_25_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_25_T = {56'h0, ll_count_times_step_25[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_25 = _ll_proba_base_25_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_25 = ll_proba_base_25[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_25 = {28'h0, _GEN_37[_restToBeat_T_25], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_126 = {71'h0, ll_proba_base_25, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_127 = {48'h0, _ll_add_to_proba_base_T_125} - {1'h0, _ll_add_to_proba_base_T_126}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_128 = _ll_add_to_proba_base_T_127[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_129 = _ll_add_to_proba_base_T_128 > {47'h0, restToBeat_25}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_25 = _ll_add_to_proba_base_T_129; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_25_T = ll_proba_base_25 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_25_T_1 = {1'h0, ll_proba_base_25} + {16'h0, ll_add_to_proba_base_25}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_25_T_2 = _ll_proba_25_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_25_T_3 = _ll_proba_25_T ? _ll_proba_25_T_2 : ll_proba_base_25; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_25 = _ll_proba_25_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_63 = {64'h0, ll_count_26} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_26_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_26_T = _GEN_63; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_130; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_130 = _GEN_63; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_26 = _ll_count_times_step_26_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_26_T = {56'h0, ll_count_times_step_26[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_26 = _ll_proba_base_26_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_26 = ll_proba_base_26[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_26 = {28'h0, _GEN_37[_restToBeat_T_26], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_131 = {71'h0, ll_proba_base_26, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_132 = {48'h0, _ll_add_to_proba_base_T_130} - {1'h0, _ll_add_to_proba_base_T_131}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_133 = _ll_add_to_proba_base_T_132[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_134 = _ll_add_to_proba_base_T_133 > {47'h0, restToBeat_26}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_26 = _ll_add_to_proba_base_T_134; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_26_T = ll_proba_base_26 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_26_T_1 = {1'h0, ll_proba_base_26} + {16'h0, ll_add_to_proba_base_26}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_26_T_2 = _ll_proba_26_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_26_T_3 = _ll_proba_26_T ? _ll_proba_26_T_2 : ll_proba_base_26; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_26 = _ll_proba_26_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_64 = {64'h0, ll_count_27} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_27_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_27_T = _GEN_64; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_135; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_135 = _GEN_64; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_27 = _ll_count_times_step_27_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_27_T = {56'h0, ll_count_times_step_27[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_27 = _ll_proba_base_27_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_27 = ll_proba_base_27[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_27 = {28'h0, _GEN_37[_restToBeat_T_27], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_136 = {71'h0, ll_proba_base_27, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_137 = {48'h0, _ll_add_to_proba_base_T_135} - {1'h0, _ll_add_to_proba_base_T_136}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_138 = _ll_add_to_proba_base_T_137[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_139 = _ll_add_to_proba_base_T_138 > {47'h0, restToBeat_27}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_27 = _ll_add_to_proba_base_T_139; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_27_T = ll_proba_base_27 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_27_T_1 = {1'h0, ll_proba_base_27} + {16'h0, ll_add_to_proba_base_27}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_27_T_2 = _ll_proba_27_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_27_T_3 = _ll_proba_27_T ? _ll_proba_27_T_2 : ll_proba_base_27; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_27 = _ll_proba_27_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_65 = {64'h0, ll_count_28} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_28_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_28_T = _GEN_65; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_140; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_140 = _GEN_65; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_28 = _ll_count_times_step_28_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_28_T = {56'h0, ll_count_times_step_28[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_28 = _ll_proba_base_28_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_28 = ll_proba_base_28[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_28 = {28'h0, _GEN_37[_restToBeat_T_28], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_141 = {71'h0, ll_proba_base_28, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_142 = {48'h0, _ll_add_to_proba_base_T_140} - {1'h0, _ll_add_to_proba_base_T_141}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_143 = _ll_add_to_proba_base_T_142[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_144 = _ll_add_to_proba_base_T_143 > {47'h0, restToBeat_28}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_28 = _ll_add_to_proba_base_T_144; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_28_T = ll_proba_base_28 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_28_T_1 = {1'h0, ll_proba_base_28} + {16'h0, ll_add_to_proba_base_28}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_28_T_2 = _ll_proba_28_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_28_T_3 = _ll_proba_28_T ? _ll_proba_28_T_2 : ll_proba_base_28; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_28 = _ll_proba_28_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_66 = {64'h0, ll_count_29} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_29_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_29_T = _GEN_66; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_145; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_145 = _GEN_66; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_29 = _ll_count_times_step_29_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_29_T = {56'h0, ll_count_times_step_29[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_29 = _ll_proba_base_29_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_29 = ll_proba_base_29[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_29 = {28'h0, _GEN_37[_restToBeat_T_29], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_146 = {71'h0, ll_proba_base_29, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_147 = {48'h0, _ll_add_to_proba_base_T_145} - {1'h0, _ll_add_to_proba_base_T_146}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_148 = _ll_add_to_proba_base_T_147[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_149 = _ll_add_to_proba_base_T_148 > {47'h0, restToBeat_29}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_29 = _ll_add_to_proba_base_T_149; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_29_T = ll_proba_base_29 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_29_T_1 = {1'h0, ll_proba_base_29} + {16'h0, ll_add_to_proba_base_29}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_29_T_2 = _ll_proba_29_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_29_T_3 = _ll_proba_29_T ? _ll_proba_29_T_2 : ll_proba_base_29; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_29 = _ll_proba_29_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_67 = {64'h0, ll_count_30} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_30_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_30_T = _GEN_67; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_150; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_150 = _GEN_67; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_30 = _ll_count_times_step_30_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_30_T = {56'h0, ll_count_times_step_30[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_30 = _ll_proba_base_30_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_30 = ll_proba_base_30[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_30 = {28'h0, _GEN_37[_restToBeat_T_30], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_151 = {71'h0, ll_proba_base_30, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_152 = {48'h0, _ll_add_to_proba_base_T_150} - {1'h0, _ll_add_to_proba_base_T_151}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_153 = _ll_add_to_proba_base_T_152[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_154 = _ll_add_to_proba_base_T_153 > {47'h0, restToBeat_30}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_30 = _ll_add_to_proba_base_T_154; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_30_T = ll_proba_base_30 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_30_T_1 = {1'h0, ll_proba_base_30} + {16'h0, ll_add_to_proba_base_30}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_30_T_2 = _ll_proba_30_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_30_T_3 = _ll_proba_30_T ? _ll_proba_30_T_2 : ll_proba_base_30; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_30 = _ll_proba_30_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_68 = {64'h0, ll_count_31} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_31_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_31_T = _GEN_68; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_155; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_155 = _GEN_68; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_31 = _ll_count_times_step_31_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_31_T = {56'h0, ll_count_times_step_31[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_31 = _ll_proba_base_31_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_31 = ll_proba_base_31[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_31 = {28'h0, _GEN_37[_restToBeat_T_31], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_156 = {71'h0, ll_proba_base_31, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_157 = {48'h0, _ll_add_to_proba_base_T_155} - {1'h0, _ll_add_to_proba_base_T_156}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_158 = _ll_add_to_proba_base_T_157[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_159 = _ll_add_to_proba_base_T_158 > {47'h0, restToBeat_31}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_31 = _ll_add_to_proba_base_T_159; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_31_T = ll_proba_base_31 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_31_T_1 = {1'h0, ll_proba_base_31} + {16'h0, ll_add_to_proba_base_31}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_31_T_2 = _ll_proba_31_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_31_T_3 = _ll_proba_31_T ? _ll_proba_31_T_2 : ll_proba_base_31; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_31 = _ll_proba_31_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [15:0] _ll_normalizedCounter_0_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_normalizedCounter_1_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T = ll_normalizedCounter_0; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_2_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_4 = ll_normalizedCounter_1; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_3_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_8 = ll_normalizedCounter_2; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_4_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_12 = ll_normalizedCounter_3; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_5_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_16 = ll_normalizedCounter_4; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_6_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_20 = ll_normalizedCounter_5; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_7_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_24 = ll_normalizedCounter_6; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_8_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_28 = ll_normalizedCounter_7; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_9_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_32 = ll_normalizedCounter_8; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_10_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_36 = ll_normalizedCounter_9; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_11_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_40 = ll_normalizedCounter_10; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_12_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_44 = ll_normalizedCounter_11; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_13_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_48 = ll_normalizedCounter_12; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_14_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_52 = ll_normalizedCounter_13; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_15_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_56 = ll_normalizedCounter_14; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_16_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_60 = ll_normalizedCounter_15; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_17_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_64 = ll_normalizedCounter_16; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_18_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_68 = ll_normalizedCounter_17; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_19_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_72 = ll_normalizedCounter_18; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_20_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_76 = ll_normalizedCounter_19; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_21_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_80 = ll_normalizedCounter_20; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_22_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_84 = ll_normalizedCounter_21; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_23_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_88 = ll_normalizedCounter_22; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_24_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_92 = ll_normalizedCounter_23; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_25_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_96 = ll_normalizedCounter_24; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_26_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_100 = ll_normalizedCounter_25; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_27_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_104 = ll_normalizedCounter_26; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_28_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_108 = ll_normalizedCounter_27; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_29_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_112 = ll_normalizedCounter_28; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_30_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_116 = ll_normalizedCounter_29; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_31_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_120 = ll_normalizedCounter_30; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] ll_normalizedCounter_31; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] _ll_ncountSumStill2Dist_T_124 = ll_normalizedCounter_31; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] ll_normalizedCounterMaxAdjusted_0; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_1; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_2; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_3; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_4; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_5; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_6; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_7; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_8; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_9; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_10; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_11; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_12; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_13; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_14; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_15; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_16; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_17; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_18; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_19; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_20; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_21; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_22; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_23; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_24; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_25; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_26; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_27; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_28; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_29; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_30; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_31; // @[FSECompressorDicBuilder.scala:278:49] wire _GEN_69 = {32'h0, ll_count_0} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T = _GEN_69; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T = _GEN_69; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_70 = {32'h0, ll_count_1} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_1; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_1 = _GEN_70; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_6; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_6 = _GEN_70; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_71 = {32'h0, ll_count_2} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_2; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_2 = _GEN_71; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_12; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_12 = _GEN_71; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_72 = {32'h0, ll_count_3} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_3; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_3 = _GEN_72; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_18; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_18 = _GEN_72; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_73 = {32'h0, ll_count_4} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_4; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_4 = _GEN_73; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_24; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_24 = _GEN_73; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_74 = {32'h0, ll_count_5} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_5; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_5 = _GEN_74; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_30; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_30 = _GEN_74; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_75 = {32'h0, ll_count_6} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_6; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_6 = _GEN_75; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_36; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_36 = _GEN_75; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_76 = {32'h0, ll_count_7} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_7; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_7 = _GEN_76; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_42; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_42 = _GEN_76; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_77 = {32'h0, ll_count_8} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_8; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_8 = _GEN_77; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_48; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_48 = _GEN_77; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_78 = {32'h0, ll_count_9} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_9; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_9 = _GEN_78; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_54; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_54 = _GEN_78; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_79 = {32'h0, ll_count_10} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_10; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_10 = _GEN_79; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_60; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_60 = _GEN_79; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_80 = {32'h0, ll_count_11} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_11; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_11 = _GEN_80; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_66; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_66 = _GEN_80; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_81 = {32'h0, ll_count_12} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_12; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_12 = _GEN_81; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_72; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_72 = _GEN_81; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_82 = {32'h0, ll_count_13} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_13; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_13 = _GEN_82; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_78; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_78 = _GEN_82; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_83 = {32'h0, ll_count_14} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_14; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_14 = _GEN_83; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_84; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_84 = _GEN_83; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_84 = {32'h0, ll_count_15} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_15; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_15 = _GEN_84; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_90; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_90 = _GEN_84; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_85 = {32'h0, ll_count_16} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_16; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_16 = _GEN_85; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_96; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_96 = _GEN_85; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_86 = {32'h0, ll_count_17} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_17; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_17 = _GEN_86; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_102; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_102 = _GEN_86; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_87 = {32'h0, ll_count_18} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_18; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_18 = _GEN_87; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_108; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_108 = _GEN_87; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_88 = {32'h0, ll_count_19} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_19; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_19 = _GEN_88; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_114; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_114 = _GEN_88; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_89 = {32'h0, ll_count_20} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_20; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_20 = _GEN_89; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_120; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_120 = _GEN_89; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_90 = {32'h0, ll_count_21} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_21; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_21 = _GEN_90; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_126; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_126 = _GEN_90; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_91 = {32'h0, ll_count_22} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_22; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_22 = _GEN_91; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_132; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_132 = _GEN_91; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_92 = {32'h0, ll_count_23} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_23; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_23 = _GEN_92; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_138; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_138 = _GEN_92; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_93 = {32'h0, ll_count_24} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_24; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_24 = _GEN_93; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_144; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_144 = _GEN_93; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_94 = {32'h0, ll_count_25} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_25; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_25 = _GEN_94; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_150; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_150 = _GEN_94; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_95 = {32'h0, ll_count_26} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_26; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_26 = _GEN_95; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_156; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_156 = _GEN_95; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_96 = {32'h0, ll_count_27} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_27; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_27 = _GEN_96; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_162; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_162 = _GEN_96; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_97 = {32'h0, ll_count_28} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_28; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_28 = _GEN_97; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_168; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_168 = _GEN_97; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_98 = {32'h0, ll_count_29} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_29; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_29 = _GEN_98; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_174; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_174 = _GEN_98; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_99 = {32'h0, ll_count_30} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_30; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_30 = _GEN_99; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_180; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_180 = _GEN_99; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_100 = {32'h0, ll_count_31} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_31; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_31 = _GEN_100; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_186; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_186 = _GEN_100; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _ll_count_has_nbseq_1_as_value_T_32 = _ll_count_has_nbseq_1_as_value_T \| _ll_count_has_nbseq_1_as_value_T_1; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_33 = _ll_count_has_nbseq_1_as_value_T_32 \| _ll_count_has_nbseq_1_as_value_T_2; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_34 = _ll_count_has_nbseq_1_as_value_T_33 \| _ll_count_has_nbseq_1_as_value_T_3; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_35 = _ll_count_has_nbseq_1_as_value_T_34 \| _ll_count_has_nbseq_1_as_value_T_4; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_36 = _ll_count_has_nbseq_1_as_value_T_35 \| _ll_count_has_nbseq_1_as_value_T_5; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_37 = _ll_count_has_nbseq_1_as_value_T_36 \| _ll_count_has_nbseq_1_as_value_T_6; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_38 = _ll_count_has_nbseq_1_as_value_T_37 \| _ll_count_has_nbseq_1_as_value_T_7; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_39 = _ll_count_has_nbseq_1_as_value_T_38 \| _ll_count_has_nbseq_1_as_value_T_8; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_40 = _ll_count_has_nbseq_1_as_value_T_39 \| _ll_count_has_nbseq_1_as_value_T_9; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_41 = _ll_count_has_nbseq_1_as_value_T_40 \| _ll_count_has_nbseq_1_as_value_T_10; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_42 = _ll_count_has_nbseq_1_as_value_T_41 \| _ll_count_has_nbseq_1_as_value_T_11; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_43 = _ll_count_has_nbseq_1_as_value_T_42 \| _ll_count_has_nbseq_1_as_value_T_12; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_44 = _ll_count_has_nbseq_1_as_value_T_43 \| _ll_count_has_nbseq_1_as_value_T_13; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_45 = _ll_count_has_nbseq_1_as_value_T_44 \| _ll_count_has_nbseq_1_as_value_T_14; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_46 = _ll_count_has_nbseq_1_as_value_T_45 \| _ll_count_has_nbseq_1_as_value_T_15; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_47 = _ll_count_has_nbseq_1_as_value_T_46 \| _ll_count_has_nbseq_1_as_value_T_16; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_48 = _ll_count_has_nbseq_1_as_value_T_47 \| _ll_count_has_nbseq_1_as_value_T_17; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_49 = _ll_count_has_nbseq_1_as_value_T_48 \| _ll_count_has_nbseq_1_as_value_T_18; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_50 = _ll_count_has_nbseq_1_as_value_T_49 \| _ll_count_has_nbseq_1_as_value_T_19; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_51 = _ll_count_has_nbseq_1_as_value_T_50 \| _ll_count_has_nbseq_1_as_value_T_20; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_52 = _ll_count_has_nbseq_1_as_value_T_51 \| _ll_count_has_nbseq_1_as_value_T_21; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_53 = _ll_count_has_nbseq_1_as_value_T_52 \| _ll_count_has_nbseq_1_as_value_T_22; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_54 = _ll_count_has_nbseq_1_as_value_T_53 \| _ll_count_has_nbseq_1_as_value_T_23; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_55 = _ll_count_has_nbseq_1_as_value_T_54 \| _ll_count_has_nbseq_1_as_value_T_24; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_56 = _ll_count_has_nbseq_1_as_value_T_55 \| _ll_count_has_nbseq_1_as_value_T_25; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_57 = _ll_count_has_nbseq_1_as_value_T_56 \| _ll_count_has_nbseq_1_as_value_T_26; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_58 = _ll_count_has_nbseq_1_as_value_T_57 \| _ll_count_has_nbseq_1_as_value_T_27; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_59 = _ll_count_has_nbseq_1_as_value_T_58 \| _ll_count_has_nbseq_1_as_value_T_28; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_60 = _ll_count_has_nbseq_1_as_value_T_59 \| _ll_count_has_nbseq_1_as_value_T_29; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_61 = _ll_count_has_nbseq_1_as_value_T_60 \| _ll_count_has_nbseq_1_as_value_T_30; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire ll_count_has_nbseq_1_as_value = _ll_count_has_nbseq_1_as_value_T_61 \| _ll_count_has_nbseq_1_as_value_T_31; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _GEN_101 = ll_count_0 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_0_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_0_T = _GEN_101; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_1; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_1 = _GEN_101; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_102 = ll_count_0 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_0_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_0_T_1 = _GEN_102; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T = _GEN_102; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_3; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_3 = _GEN_102; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_0_T_2 = _ll_normalizedCounter_0_T_1 ? ll_lowProbCount : ll_proba_0; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_0_T_3 = _ll_normalizedCounter_0_T ? 16'h0 : _ll_normalizedCounter_0_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_0 = _ll_normalizedCounter_0_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_103 = ll_count_1 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_1_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_1_T = _GEN_103; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_7; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_7 = _GEN_103; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_104 = ll_count_1 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_1_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_1_T_1 = _GEN_104; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_3; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_3 = _GEN_104; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_9; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_9 = _GEN_104; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_1_T_2 = _ll_normalizedCounter_1_T_1 ? ll_lowProbCount : ll_proba_1; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_1_T_3 = _ll_normalizedCounter_1_T ? 16'h0 : _ll_normalizedCounter_1_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_1 = _ll_normalizedCounter_1_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_105 = ll_count_2 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_2_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_2_T = _GEN_105; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_13; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_13 = _GEN_105; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_106 = ll_count_2 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_2_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_2_T_1 = _GEN_106; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_6; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_6 = _GEN_106; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_15; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_15 = _GEN_106; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_2_T_2 = _ll_normalizedCounter_2_T_1 ? ll_lowProbCount : ll_proba_2; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_2_T_3 = _ll_normalizedCounter_2_T ? 16'h0 : _ll_normalizedCounter_2_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_2 = _ll_normalizedCounter_2_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_107 = ll_count_3 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_3_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_3_T = _GEN_107; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_19; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_19 = _GEN_107; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_108 = ll_count_3 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_3_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_3_T_1 = _GEN_108; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_9; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_9 = _GEN_108; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_21; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_21 = _GEN_108; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_3_T_2 = _ll_normalizedCounter_3_T_1 ? ll_lowProbCount : ll_proba_3; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_3_T_3 = _ll_normalizedCounter_3_T ? 16'h0 : _ll_normalizedCounter_3_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_3 = _ll_normalizedCounter_3_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_109 = ll_count_4 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_4_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_4_T = _GEN_109; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_25; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_25 = _GEN_109; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_110 = ll_count_4 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_4_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_4_T_1 = _GEN_110; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_12; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_12 = _GEN_110; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_27; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_27 = _GEN_110; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_4_T_2 = _ll_normalizedCounter_4_T_1 ? ll_lowProbCount : ll_proba_4; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_4_T_3 = _ll_normalizedCounter_4_T ? 16'h0 : _ll_normalizedCounter_4_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_4 = _ll_normalizedCounter_4_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_111 = ll_count_5 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_5_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_5_T = _GEN_111; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_31; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_31 = _GEN_111; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_112 = ll_count_5 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_5_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_5_T_1 = _GEN_112; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_15; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_15 = _GEN_112; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_33; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_33 = _GEN_112; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_5_T_2 = _ll_normalizedCounter_5_T_1 ? ll_lowProbCount : ll_proba_5; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_5_T_3 = _ll_normalizedCounter_5_T ? 16'h0 : _ll_normalizedCounter_5_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_5 = _ll_normalizedCounter_5_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_113 = ll_count_6 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_6_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_6_T = _GEN_113; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_37; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_37 = _GEN_113; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_114 = ll_count_6 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_6_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_6_T_1 = _GEN_114; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_18; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_18 = _GEN_114; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_39; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_39 = _GEN_114; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_6_T_2 = _ll_normalizedCounter_6_T_1 ? ll_lowProbCount : ll_proba_6; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_6_T_3 = _ll_normalizedCounter_6_T ? 16'h0 : _ll_normalizedCounter_6_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_6 = _ll_normalizedCounter_6_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_115 = ll_count_7 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_7_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_7_T = _GEN_115; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_43; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_43 = _GEN_115; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_116 = ll_count_7 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_7_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_7_T_1 = _GEN_116; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_21; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_21 = _GEN_116; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_45; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_45 = _GEN_116; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_7_T_2 = _ll_normalizedCounter_7_T_1 ? ll_lowProbCount : ll_proba_7; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_7_T_3 = _ll_normalizedCounter_7_T ? 16'h0 : _ll_normalizedCounter_7_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_7 = _ll_normalizedCounter_7_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_117 = ll_count_8 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_8_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_8_T = _GEN_117; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_49; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_49 = _GEN_117; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_118 = ll_count_8 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_8_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_8_T_1 = _GEN_118; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_24; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_24 = _GEN_118; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_51; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_51 = _GEN_118; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_8_T_2 = _ll_normalizedCounter_8_T_1 ? ll_lowProbCount : ll_proba_8; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_8_T_3 = _ll_normalizedCounter_8_T ? 16'h0 : _ll_normalizedCounter_8_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_8 = _ll_normalizedCounter_8_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_119 = ll_count_9 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_9_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_9_T = _GEN_119; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_55; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_55 = _GEN_119; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_120 = ll_count_9 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_9_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_9_T_1 = _GEN_120; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_27; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_27 = _GEN_120; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_57; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_57 = _GEN_120; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_9_T_2 = _ll_normalizedCounter_9_T_1 ? ll_lowProbCount : ll_proba_9; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_9_T_3 = _ll_normalizedCounter_9_T ? 16'h0 : _ll_normalizedCounter_9_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_9 = _ll_normalizedCounter_9_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_121 = ll_count_10 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_10_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_10_T = _GEN_121; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_61; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_61 = _GEN_121; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_122 = ll_count_10 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_10_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_10_T_1 = _GEN_122; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_30; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_30 = _GEN_122; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_63; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_63 = _GEN_122; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_10_T_2 = _ll_normalizedCounter_10_T_1 ? ll_lowProbCount : ll_proba_10; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_10_T_3 = _ll_normalizedCounter_10_T ? 16'h0 : _ll_normalizedCounter_10_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_10 = _ll_normalizedCounter_10_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_123 = ll_count_11 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_11_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_11_T = _GEN_123; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_67; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_67 = _GEN_123; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_124 = ll_count_11 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_11_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_11_T_1 = _GEN_124; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_33; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_33 = _GEN_124; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_69; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_69 = _GEN_124; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_11_T_2 = _ll_normalizedCounter_11_T_1 ? ll_lowProbCount : ll_proba_11; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_11_T_3 = _ll_normalizedCounter_11_T ? 16'h0 : _ll_normalizedCounter_11_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_11 = _ll_normalizedCounter_11_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_125 = ll_count_12 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_12_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_12_T = _GEN_125; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_73; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_73 = _GEN_125; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_126 = ll_count_12 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_12_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_12_T_1 = _GEN_126; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_36; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_36 = _GEN_126; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_75; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_75 = _GEN_126; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_12_T_2 = _ll_normalizedCounter_12_T_1 ? ll_lowProbCount : ll_proba_12; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_12_T_3 = _ll_normalizedCounter_12_T ? 16'h0 : _ll_normalizedCounter_12_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_12 = _ll_normalizedCounter_12_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_127 = ll_count_13 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_13_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_13_T = _GEN_127; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_79; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_79 = _GEN_127; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_128 = ll_count_13 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_13_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_13_T_1 = _GEN_128; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_39; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_39 = _GEN_128; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_81; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_81 = _GEN_128; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_13_T_2 = _ll_normalizedCounter_13_T_1 ? ll_lowProbCount : ll_proba_13; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_13_T_3 = _ll_normalizedCounter_13_T ? 16'h0 : _ll_normalizedCounter_13_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_13 = _ll_normalizedCounter_13_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_129 = ll_count_14 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_14_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_14_T = _GEN_129; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_85; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_85 = _GEN_129; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_130 = ll_count_14 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_14_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_14_T_1 = _GEN_130; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_42; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_42 = _GEN_130; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_87; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_87 = _GEN_130; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_14_T_2 = _ll_normalizedCounter_14_T_1 ? ll_lowProbCount : ll_proba_14; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_14_T_3 = _ll_normalizedCounter_14_T ? 16'h0 : _ll_normalizedCounter_14_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_14 = _ll_normalizedCounter_14_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_131 = ll_count_15 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_15_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_15_T = _GEN_131; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_91; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_91 = _GEN_131; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_132 = ll_count_15 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_15_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_15_T_1 = _GEN_132; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_45; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_45 = _GEN_132; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_93; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_93 = _GEN_132; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_15_T_2 = _ll_normalizedCounter_15_T_1 ? ll_lowProbCount : ll_proba_15; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_15_T_3 = _ll_normalizedCounter_15_T ? 16'h0 : _ll_normalizedCounter_15_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_15 = _ll_normalizedCounter_15_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_133 = ll_count_16 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_16_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_16_T = _GEN_133; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_97; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_97 = _GEN_133; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_134 = ll_count_16 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_16_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_16_T_1 = _GEN_134; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_48; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_48 = _GEN_134; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_99; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_99 = _GEN_134; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_16_T_2 = _ll_normalizedCounter_16_T_1 ? ll_lowProbCount : ll_proba_16; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_16_T_3 = _ll_normalizedCounter_16_T ? 16'h0 : _ll_normalizedCounter_16_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_16 = _ll_normalizedCounter_16_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_135 = ll_count_17 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_17_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_17_T = _GEN_135; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_103; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_103 = _GEN_135; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_136 = ll_count_17 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_17_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_17_T_1 = _GEN_136; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_51; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_51 = _GEN_136; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_105; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_105 = _GEN_136; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_17_T_2 = _ll_normalizedCounter_17_T_1 ? ll_lowProbCount : ll_proba_17; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_17_T_3 = _ll_normalizedCounter_17_T ? 16'h0 : _ll_normalizedCounter_17_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_17 = _ll_normalizedCounter_17_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_137 = ll_count_18 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_18_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_18_T = _GEN_137; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_109; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_109 = _GEN_137; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_138 = ll_count_18 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_18_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_18_T_1 = _GEN_138; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_54; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_54 = _GEN_138; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_111; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_111 = _GEN_138; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_18_T_2 = _ll_normalizedCounter_18_T_1 ? ll_lowProbCount : ll_proba_18; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_18_T_3 = _ll_normalizedCounter_18_T ? 16'h0 : _ll_normalizedCounter_18_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_18 = _ll_normalizedCounter_18_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_139 = ll_count_19 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_19_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_19_T = _GEN_139; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_115; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_115 = _GEN_139; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_140 = ll_count_19 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_19_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_19_T_1 = _GEN_140; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_57; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_57 = _GEN_140; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_117; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_117 = _GEN_140; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_19_T_2 = _ll_normalizedCounter_19_T_1 ? ll_lowProbCount : ll_proba_19; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_19_T_3 = _ll_normalizedCounter_19_T ? 16'h0 : _ll_normalizedCounter_19_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_19 = _ll_normalizedCounter_19_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_141 = ll_count_20 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_20_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_20_T = _GEN_141; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_121; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_121 = _GEN_141; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_142 = ll_count_20 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_20_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_20_T_1 = _GEN_142; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_60; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_60 = _GEN_142; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_123; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_123 = _GEN_142; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_20_T_2 = _ll_normalizedCounter_20_T_1 ? ll_lowProbCount : ll_proba_20; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_20_T_3 = _ll_normalizedCounter_20_T ? 16'h0 : _ll_normalizedCounter_20_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_20 = _ll_normalizedCounter_20_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_143 = ll_count_21 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_21_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_21_T = _GEN_143; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_127; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_127 = _GEN_143; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_144 = ll_count_21 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_21_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_21_T_1 = _GEN_144; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_63; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_63 = _GEN_144; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_129; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_129 = _GEN_144; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_21_T_2 = _ll_normalizedCounter_21_T_1 ? ll_lowProbCount : ll_proba_21; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_21_T_3 = _ll_normalizedCounter_21_T ? 16'h0 : _ll_normalizedCounter_21_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_21 = _ll_normalizedCounter_21_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_145 = ll_count_22 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_22_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_22_T = _GEN_145; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_133; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_133 = _GEN_145; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_146 = ll_count_22 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_22_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_22_T_1 = _GEN_146; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_66; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_66 = _GEN_146; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_135; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_135 = _GEN_146; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_22_T_2 = _ll_normalizedCounter_22_T_1 ? ll_lowProbCount : ll_proba_22; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_22_T_3 = _ll_normalizedCounter_22_T ? 16'h0 : _ll_normalizedCounter_22_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_22 = _ll_normalizedCounter_22_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_147 = ll_count_23 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_23_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_23_T = _GEN_147; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_139; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_139 = _GEN_147; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_148 = ll_count_23 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_23_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_23_T_1 = _GEN_148; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_69; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_69 = _GEN_148; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_141; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_141 = _GEN_148; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_23_T_2 = _ll_normalizedCounter_23_T_1 ? ll_lowProbCount : ll_proba_23; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_23_T_3 = _ll_normalizedCounter_23_T ? 16'h0 : _ll_normalizedCounter_23_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_23 = _ll_normalizedCounter_23_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_149 = ll_count_24 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_24_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_24_T = _GEN_149; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_145; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_145 = _GEN_149; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_150 = ll_count_24 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_24_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_24_T_1 = _GEN_150; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_72; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_72 = _GEN_150; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_147; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_147 = _GEN_150; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_24_T_2 = _ll_normalizedCounter_24_T_1 ? ll_lowProbCount : ll_proba_24; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_24_T_3 = _ll_normalizedCounter_24_T ? 16'h0 : _ll_normalizedCounter_24_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_24 = _ll_normalizedCounter_24_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_151 = ll_count_25 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_25_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_25_T = _GEN_151; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_151; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_151 = _GEN_151; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_152 = ll_count_25 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_25_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_25_T_1 = _GEN_152; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_75; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_75 = _GEN_152; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_153; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_153 = _GEN_152; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_25_T_2 = _ll_normalizedCounter_25_T_1 ? ll_lowProbCount : ll_proba_25; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_25_T_3 = _ll_normalizedCounter_25_T ? 16'h0 : _ll_normalizedCounter_25_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_25 = _ll_normalizedCounter_25_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_153 = ll_count_26 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_26_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_26_T = _GEN_153; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_157; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_157 = _GEN_153; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_154 = ll_count_26 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_26_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_26_T_1 = _GEN_154; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_78; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_78 = _GEN_154; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_159; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_159 = _GEN_154; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_26_T_2 = _ll_normalizedCounter_26_T_1 ? ll_lowProbCount : ll_proba_26; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_26_T_3 = _ll_normalizedCounter_26_T ? 16'h0 : _ll_normalizedCounter_26_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_26 = _ll_normalizedCounter_26_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_155 = ll_count_27 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_27_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_27_T = _GEN_155; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_163; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_163 = _GEN_155; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_156 = ll_count_27 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_27_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_27_T_1 = _GEN_156; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_81; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_81 = _GEN_156; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_165; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_165 = _GEN_156; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_27_T_2 = _ll_normalizedCounter_27_T_1 ? ll_lowProbCount : ll_proba_27; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_27_T_3 = _ll_normalizedCounter_27_T ? 16'h0 : _ll_normalizedCounter_27_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_27 = _ll_normalizedCounter_27_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_157 = ll_count_28 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_28_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_28_T = _GEN_157; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_169; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_169 = _GEN_157; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_158 = ll_count_28 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_28_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_28_T_1 = _GEN_158; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_84; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_84 = _GEN_158; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_171; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_171 = _GEN_158; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_28_T_2 = _ll_normalizedCounter_28_T_1 ? ll_lowProbCount : ll_proba_28; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_28_T_3 = _ll_normalizedCounter_28_T ? 16'h0 : _ll_normalizedCounter_28_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_28 = _ll_normalizedCounter_28_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_159 = ll_count_29 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_29_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_29_T = _GEN_159; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_175; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_175 = _GEN_159; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_160 = ll_count_29 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_29_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_29_T_1 = _GEN_160; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_87; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_87 = _GEN_160; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_177; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_177 = _GEN_160; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_29_T_2 = _ll_normalizedCounter_29_T_1 ? ll_lowProbCount : ll_proba_29; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_29_T_3 = _ll_normalizedCounter_29_T ? 16'h0 : _ll_normalizedCounter_29_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_29 = _ll_normalizedCounter_29_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_161 = ll_count_30 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_30_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_30_T = _GEN_161; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_181; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_181 = _GEN_161; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_162 = ll_count_30 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_30_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_30_T_1 = _GEN_162; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_90; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_90 = _GEN_162; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_183; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_183 = _GEN_162; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_30_T_2 = _ll_normalizedCounter_30_T_1 ? ll_lowProbCount : ll_proba_30; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_30_T_3 = _ll_normalizedCounter_30_T ? 16'h0 : _ll_normalizedCounter_30_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_30 = _ll_normalizedCounter_30_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_163 = ll_count_31 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_31_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_31_T = _GEN_163; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_187; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_187 = _GEN_163; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_164 = ll_count_31 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_31_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_31_T_1 = _GEN_164; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_93; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_93 = _GEN_164; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_189; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_189 = _GEN_164; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_31_T_2 = _ll_normalizedCounter_31_T_1 ? ll_lowProbCount : ll_proba_31; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_31_T_3 = _ll_normalizedCounter_31_T ? 16'h0 : _ll_normalizedCounter_31_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_31 = _ll_normalizedCounter_31_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _ll_smallOrEqToLowThresholdCount_T_1 = \|ll_count_0; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_2 = _ll_smallOrEqToLowThresholdCount_T & _ll_smallOrEqToLowThresholdCount_T_1; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_4 = \|ll_count_1; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_5 = _ll_smallOrEqToLowThresholdCount_T_3 & _ll_smallOrEqToLowThresholdCount_T_4; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_7 = \|ll_count_2; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_8 = _ll_smallOrEqToLowThresholdCount_T_6 & _ll_smallOrEqToLowThresholdCount_T_7; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_10 = \|ll_count_3; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_11 = _ll_smallOrEqToLowThresholdCount_T_9 & _ll_smallOrEqToLowThresholdCount_T_10; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_13 = \|ll_count_4; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_14 = _ll_smallOrEqToLowThresholdCount_T_12 & _ll_smallOrEqToLowThresholdCount_T_13; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_16 = \|ll_count_5; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_17 = _ll_smallOrEqToLowThresholdCount_T_15 & _ll_smallOrEqToLowThresholdCount_T_16; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_19 = \|ll_count_6; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_20 = _ll_smallOrEqToLowThresholdCount_T_18 & _ll_smallOrEqToLowThresholdCount_T_19; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_22 = \|ll_count_7; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_23 = _ll_smallOrEqToLowThresholdCount_T_21 & _ll_smallOrEqToLowThresholdCount_T_22; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_25 = \|ll_count_8; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_26 = _ll_smallOrEqToLowThresholdCount_T_24 & _ll_smallOrEqToLowThresholdCount_T_25; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_28 = \|ll_count_9; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_29 = _ll_smallOrEqToLowThresholdCount_T_27 & _ll_smallOrEqToLowThresholdCount_T_28; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_31 = \|ll_count_10; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_32 = _ll_smallOrEqToLowThresholdCount_T_30 & _ll_smallOrEqToLowThresholdCount_T_31; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_34 = \|ll_count_11; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_35 = _ll_smallOrEqToLowThresholdCount_T_33 & _ll_smallOrEqToLowThresholdCount_T_34; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_37 = \|ll_count_12; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_38 = _ll_smallOrEqToLowThresholdCount_T_36 & _ll_smallOrEqToLowThresholdCount_T_37; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_40 = \|ll_count_13; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_41 = _ll_smallOrEqToLowThresholdCount_T_39 & _ll_smallOrEqToLowThresholdCount_T_40; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_43 = \|ll_count_14; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_44 = _ll_smallOrEqToLowThresholdCount_T_42 & _ll_smallOrEqToLowThresholdCount_T_43; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_46 = \|ll_count_15; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_47 = _ll_smallOrEqToLowThresholdCount_T_45 & _ll_smallOrEqToLowThresholdCount_T_46; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_49 = \|ll_count_16; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_50 = _ll_smallOrEqToLowThresholdCount_T_48 & _ll_smallOrEqToLowThresholdCount_T_49; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_52 = \|ll_count_17; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_53 = _ll_smallOrEqToLowThresholdCount_T_51 & _ll_smallOrEqToLowThresholdCount_T_52; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_55 = \|ll_count_18; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_56 = _ll_smallOrEqToLowThresholdCount_T_54 & _ll_smallOrEqToLowThresholdCount_T_55; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_58 = \|ll_count_19; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_59 = _ll_smallOrEqToLowThresholdCount_T_57 & _ll_smallOrEqToLowThresholdCount_T_58; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_61 = \|ll_count_20; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_62 = _ll_smallOrEqToLowThresholdCount_T_60 & _ll_smallOrEqToLowThresholdCount_T_61; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_64 = \|ll_count_21; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_65 = _ll_smallOrEqToLowThresholdCount_T_63 & _ll_smallOrEqToLowThresholdCount_T_64; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_67 = \|ll_count_22; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_68 = _ll_smallOrEqToLowThresholdCount_T_66 & _ll_smallOrEqToLowThresholdCount_T_67; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_70 = \|ll_count_23; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_71 = _ll_smallOrEqToLowThresholdCount_T_69 & _ll_smallOrEqToLowThresholdCount_T_70; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_73 = \|ll_count_24; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_74 = _ll_smallOrEqToLowThresholdCount_T_72 & _ll_smallOrEqToLowThresholdCount_T_73; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_76 = \|ll_count_25; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_77 = _ll_smallOrEqToLowThresholdCount_T_75 & _ll_smallOrEqToLowThresholdCount_T_76; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_79 = \|ll_count_26; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_80 = _ll_smallOrEqToLowThresholdCount_T_78 & _ll_smallOrEqToLowThresholdCount_T_79; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_82 = \|ll_count_27; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_83 = _ll_smallOrEqToLowThresholdCount_T_81 & _ll_smallOrEqToLowThresholdCount_T_82; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_85 = \|ll_count_28; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_86 = _ll_smallOrEqToLowThresholdCount_T_84 & _ll_smallOrEqToLowThresholdCount_T_85; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_88 = \|ll_count_29; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_89 = _ll_smallOrEqToLowThresholdCount_T_87 & _ll_smallOrEqToLowThresholdCount_T_88; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_91 = \|ll_count_30; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_92 = _ll_smallOrEqToLowThresholdCount_T_90 & _ll_smallOrEqToLowThresholdCount_T_91; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_94 = \|ll_count_31; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_95 = _ll_smallOrEqToLowThresholdCount_T_93 & _ll_smallOrEqToLowThresholdCount_T_94; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire [1:0] _ll_smallOrEqToLowThresholdCount_T_96 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_2} + {1'h0, _ll_smallOrEqToLowThresholdCount_T_5}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [2:0] _ll_smallOrEqToLowThresholdCount_T_97 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_96} + {2'h0, _ll_smallOrEqToLowThresholdCount_T_8}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [3:0] _ll_smallOrEqToLowThresholdCount_T_98 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_97} + {3'h0, _ll_smallOrEqToLowThresholdCount_T_11}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [4:0] _ll_smallOrEqToLowThresholdCount_T_99 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_98} + {4'h0, _ll_smallOrEqToLowThresholdCount_T_14}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [5:0] _ll_smallOrEqToLowThresholdCount_T_100 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_99} + {5'h0, _ll_smallOrEqToLowThresholdCount_T_17}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [6:0] _ll_smallOrEqToLowThresholdCount_T_101 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_100} + {6'h0, _ll_smallOrEqToLowThresholdCount_T_20}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [7:0] _ll_smallOrEqToLowThresholdCount_T_102 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_101} + {7'h0, _ll_smallOrEqToLowThresholdCount_T_23}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [8:0] _ll_smallOrEqToLowThresholdCount_T_103 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_102} + {8'h0, _ll_smallOrEqToLowThresholdCount_T_26}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [9:0] _ll_smallOrEqToLowThresholdCount_T_104 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_103} + {9'h0, _ll_smallOrEqToLowThresholdCount_T_29}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [10:0] _ll_smallOrEqToLowThresholdCount_T_105 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_104} + {10'h0, _ll_smallOrEqToLowThresholdCount_T_32}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [11:0] _ll_smallOrEqToLowThresholdCount_T_106 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_105} + {11'h0, _ll_smallOrEqToLowThresholdCount_T_35}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [12:0] _ll_smallOrEqToLowThresholdCount_T_107 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_106} + {12'h0, _ll_smallOrEqToLowThresholdCount_T_38}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [13:0] _ll_smallOrEqToLowThresholdCount_T_108 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_107} + {13'h0, _ll_smallOrEqToLowThresholdCount_T_41}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [14:0] _ll_smallOrEqToLowThresholdCount_T_109 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_108} + {14'h0, _ll_smallOrEqToLowThresholdCount_T_44}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [15:0] _ll_smallOrEqToLowThresholdCount_T_110 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_109} + {15'h0, _ll_smallOrEqToLowThresholdCount_T_47}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [16:0] _ll_smallOrEqToLowThresholdCount_T_111 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_110} + {16'h0, _ll_smallOrEqToLowThresholdCount_T_50}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [17:0] _ll_smallOrEqToLowThresholdCount_T_112 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_111} + {17'h0, _ll_smallOrEqToLowThresholdCount_T_53}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [18:0] _ll_smallOrEqToLowThresholdCount_T_113 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_112} + {18'h0, _ll_smallOrEqToLowThresholdCount_T_56}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [19:0] _ll_smallOrEqToLowThresholdCount_T_114 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_113} + {19'h0, _ll_smallOrEqToLowThresholdCount_T_59}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [20:0] _ll_smallOrEqToLowThresholdCount_T_115 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_114} + {20'h0, _ll_smallOrEqToLowThresholdCount_T_62}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [21:0] _ll_smallOrEqToLowThresholdCount_T_116 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_115} + {21'h0, _ll_smallOrEqToLowThresholdCount_T_65}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [22:0] _ll_smallOrEqToLowThresholdCount_T_117 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_116} + {22'h0, _ll_smallOrEqToLowThresholdCount_T_68}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [23:0] _ll_smallOrEqToLowThresholdCount_T_118 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_117} + {23'h0, _ll_smallOrEqToLowThresholdCount_T_71}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [24:0] _ll_smallOrEqToLowThresholdCount_T_119 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_118} + {24'h0, _ll_smallOrEqToLowThresholdCount_T_74}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [25:0] _ll_smallOrEqToLowThresholdCount_T_120 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_119} + {25'h0, _ll_smallOrEqToLowThresholdCount_T_77}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [26:0] _ll_smallOrEqToLowThresholdCount_T_121 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_120} + {26'h0, _ll_smallOrEqToLowThresholdCount_T_80}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [27:0] _ll_smallOrEqToLowThresholdCount_T_122 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_121} + {27'h0, _ll_smallOrEqToLowThresholdCount_T_83}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [28:0] _ll_smallOrEqToLowThresholdCount_T_123 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_122} + {28'h0, _ll_smallOrEqToLowThresholdCount_T_86}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [29:0] _ll_smallOrEqToLowThresholdCount_T_124 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_123} + {29'h0, _ll_smallOrEqToLowThresholdCount_T_89}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [30:0] _ll_smallOrEqToLowThresholdCount_T_125 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_124} + {30'h0, _ll_smallOrEqToLowThresholdCount_T_92}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [31:0] ll_smallOrEqToLowThresholdCount = {1'h0, _ll_smallOrEqToLowThresholdCount_T_125} + {31'h0, _ll_smallOrEqToLowThresholdCount_T_95}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire _ll_largerThanLowThresholdProbaSum_T_2 = _ll_largerThanLowThresholdProbaSum_T \| _ll_largerThanLowThresholdProbaSum_T_1; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_4 = _ll_largerThanLowThresholdProbaSum_T_2 \| _ll_largerThanLowThresholdProbaSum_T_3; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_5 = _ll_largerThanLowThresholdProbaSum_T_4 ? 16'h0 : ll_proba_0; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_8 = _ll_largerThanLowThresholdProbaSum_T_6 \| _ll_largerThanLowThresholdProbaSum_T_7; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_10 = _ll_largerThanLowThresholdProbaSum_T_8 \| _ll_largerThanLowThresholdProbaSum_T_9; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_11 = _ll_largerThanLowThresholdProbaSum_T_10 ? 16'h0 : ll_proba_1; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_14 = _ll_largerThanLowThresholdProbaSum_T_12 \| _ll_largerThanLowThresholdProbaSum_T_13; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_16 = _ll_largerThanLowThresholdProbaSum_T_14 \| _ll_largerThanLowThresholdProbaSum_T_15; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_17 = _ll_largerThanLowThresholdProbaSum_T_16 ? 16'h0 : ll_proba_2; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_20 = _ll_largerThanLowThresholdProbaSum_T_18 \| _ll_largerThanLowThresholdProbaSum_T_19; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_22 = _ll_largerThanLowThresholdProbaSum_T_20 \| _ll_largerThanLowThresholdProbaSum_T_21; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_23 = _ll_largerThanLowThresholdProbaSum_T_22 ? 16'h0 : ll_proba_3; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_26 = _ll_largerThanLowThresholdProbaSum_T_24 \| _ll_largerThanLowThresholdProbaSum_T_25; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_28 = _ll_largerThanLowThresholdProbaSum_T_26 \| _ll_largerThanLowThresholdProbaSum_T_27; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_29 = _ll_largerThanLowThresholdProbaSum_T_28 ? 16'h0 : ll_proba_4; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_32 = _ll_largerThanLowThresholdProbaSum_T_30 \| _ll_largerThanLowThresholdProbaSum_T_31; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_34 = _ll_largerThanLowThresholdProbaSum_T_32 \| _ll_largerThanLowThresholdProbaSum_T_33; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_35 = _ll_largerThanLowThresholdProbaSum_T_34 ? 16'h0 : ll_proba_5; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_38 = _ll_largerThanLowThresholdProbaSum_T_36 \| _ll_largerThanLowThresholdProbaSum_T_37; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_40 = _ll_largerThanLowThresholdProbaSum_T_38 \| _ll_largerThanLowThresholdProbaSum_T_39; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_41 = _ll_largerThanLowThresholdProbaSum_T_40 ? 16'h0 : ll_proba_6; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_44 = _ll_largerThanLowThresholdProbaSum_T_42 \| _ll_largerThanLowThresholdProbaSum_T_43; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_46 = _ll_largerThanLowThresholdProbaSum_T_44 \| _ll_largerThanLowThresholdProbaSum_T_45; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_47 = _ll_largerThanLowThresholdProbaSum_T_46 ? 16'h0 : ll_proba_7; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_50 = _ll_largerThanLowThresholdProbaSum_T_48 \| _ll_largerThanLowThresholdProbaSum_T_49; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_52 = _ll_largerThanLowThresholdProbaSum_T_50 \| _ll_largerThanLowThresholdProbaSum_T_51; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_53 = _ll_largerThanLowThresholdProbaSum_T_52 ? 16'h0 : ll_proba_8; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_56 = _ll_largerThanLowThresholdProbaSum_T_54 \| _ll_largerThanLowThresholdProbaSum_T_55; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_58 = _ll_largerThanLowThresholdProbaSum_T_56 \| _ll_largerThanLowThresholdProbaSum_T_57; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_59 = _ll_largerThanLowThresholdProbaSum_T_58 ? 16'h0 : ll_proba_9; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_62 = _ll_largerThanLowThresholdProbaSum_T_60 \| _ll_largerThanLowThresholdProbaSum_T_61; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_64 = _ll_largerThanLowThresholdProbaSum_T_62 \| _ll_largerThanLowThresholdProbaSum_T_63; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_65 = _ll_largerThanLowThresholdProbaSum_T_64 ? 16'h0 : ll_proba_10; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_68 = _ll_largerThanLowThresholdProbaSum_T_66 \| _ll_largerThanLowThresholdProbaSum_T_67; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_70 = _ll_largerThanLowThresholdProbaSum_T_68 \| _ll_largerThanLowThresholdProbaSum_T_69; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_71 = _ll_largerThanLowThresholdProbaSum_T_70 ? 16'h0 : ll_proba_11; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_74 = _ll_largerThanLowThresholdProbaSum_T_72 \| _ll_largerThanLowThresholdProbaSum_T_73; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_76 = _ll_largerThanLowThresholdProbaSum_T_74 \| _ll_largerThanLowThresholdProbaSum_T_75; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_77 = _ll_largerThanLowThresholdProbaSum_T_76 ? 16'h0 : ll_proba_12; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_80 = _ll_largerThanLowThresholdProbaSum_T_78 \| _ll_largerThanLowThresholdProbaSum_T_79; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_82 = _ll_largerThanLowThresholdProbaSum_T_80 \| _ll_largerThanLowThresholdProbaSum_T_81; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_83 = _ll_largerThanLowThresholdProbaSum_T_82 ? 16'h0 : ll_proba_13; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_86 = _ll_largerThanLowThresholdProbaSum_T_84 \| _ll_largerThanLowThresholdProbaSum_T_85; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_88 = _ll_largerThanLowThresholdProbaSum_T_86 \| _ll_largerThanLowThresholdProbaSum_T_87; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_89 = _ll_largerThanLowThresholdProbaSum_T_88 ? 16'h0 : ll_proba_14; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_92 = _ll_largerThanLowThresholdProbaSum_T_90 \| _ll_largerThanLowThresholdProbaSum_T_91; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_94 = _ll_largerThanLowThresholdProbaSum_T_92 \| _ll_largerThanLowThresholdProbaSum_T_93; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_95 = _ll_largerThanLowThresholdProbaSum_T_94 ? 16'h0 : ll_proba_15; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_98 = _ll_largerThanLowThresholdProbaSum_T_96 \| _ll_largerThanLowThresholdProbaSum_T_97; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_100 = _ll_largerThanLowThresholdProbaSum_T_98 \| _ll_largerThanLowThresholdProbaSum_T_99; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_101 = _ll_largerThanLowThresholdProbaSum_T_100 ? 16'h0 : ll_proba_16; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_104 = _ll_largerThanLowThresholdProbaSum_T_102 \| _ll_largerThanLowThresholdProbaSum_T_103; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_106 = _ll_largerThanLowThresholdProbaSum_T_104 \| _ll_largerThanLowThresholdProbaSum_T_105; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_107 = _ll_largerThanLowThresholdProbaSum_T_106 ? 16'h0 : ll_proba_17; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_110 = _ll_largerThanLowThresholdProbaSum_T_108 \| _ll_largerThanLowThresholdProbaSum_T_109; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_112 = _ll_largerThanLowThresholdProbaSum_T_110 \| _ll_largerThanLowThresholdProbaSum_T_111; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_113 = _ll_largerThanLowThresholdProbaSum_T_112 ? 16'h0 : ll_proba_18; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_116 = _ll_largerThanLowThresholdProbaSum_T_114 \| _ll_largerThanLowThresholdProbaSum_T_115; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_118 = _ll_largerThanLowThresholdProbaSum_T_116 \| _ll_largerThanLowThresholdProbaSum_T_117; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_119 = _ll_largerThanLowThresholdProbaSum_T_118 ? 16'h0 : ll_proba_19; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_122 = _ll_largerThanLowThresholdProbaSum_T_120 \| _ll_largerThanLowThresholdProbaSum_T_121; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_124 = _ll_largerThanLowThresholdProbaSum_T_122 \| _ll_largerThanLowThresholdProbaSum_T_123; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_125 = _ll_largerThanLowThresholdProbaSum_T_124 ? 16'h0 : ll_proba_20; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_128 = _ll_largerThanLowThresholdProbaSum_T_126 \| _ll_largerThanLowThresholdProbaSum_T_127; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_130 = _ll_largerThanLowThresholdProbaSum_T_128 \| _ll_largerThanLowThresholdProbaSum_T_129; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_131 = _ll_largerThanLowThresholdProbaSum_T_130 ? 16'h0 : ll_proba_21; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_134 = _ll_largerThanLowThresholdProbaSum_T_132 \| _ll_largerThanLowThresholdProbaSum_T_133; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_136 = _ll_largerThanLowThresholdProbaSum_T_134 \| _ll_largerThanLowThresholdProbaSum_T_135; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_137 = _ll_largerThanLowThresholdProbaSum_T_136 ? 16'h0 : ll_proba_22; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_140 = _ll_largerThanLowThresholdProbaSum_T_138 \| _ll_largerThanLowThresholdProbaSum_T_139; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_142 = _ll_largerThanLowThresholdProbaSum_T_140 \| _ll_largerThanLowThresholdProbaSum_T_141; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_143 = _ll_largerThanLowThresholdProbaSum_T_142 ? 16'h0 : ll_proba_23; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_146 = _ll_largerThanLowThresholdProbaSum_T_144 \| _ll_largerThanLowThresholdProbaSum_T_145; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_148 = _ll_largerThanLowThresholdProbaSum_T_146 \| _ll_largerThanLowThresholdProbaSum_T_147; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_149 = _ll_largerThanLowThresholdProbaSum_T_148 ? 16'h0 : ll_proba_24; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_152 = _ll_largerThanLowThresholdProbaSum_T_150 \| _ll_largerThanLowThresholdProbaSum_T_151; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_154 = _ll_largerThanLowThresholdProbaSum_T_152 \| _ll_largerThanLowThresholdProbaSum_T_153; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_155 = _ll_largerThanLowThresholdProbaSum_T_154 ? 16'h0 : ll_proba_25; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_158 = _ll_largerThanLowThresholdProbaSum_T_156 \| _ll_largerThanLowThresholdProbaSum_T_157; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_160 = _ll_largerThanLowThresholdProbaSum_T_158 \| _ll_largerThanLowThresholdProbaSum_T_159; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_161 = _ll_largerThanLowThresholdProbaSum_T_160 ? 16'h0 : ll_proba_26; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_164 = _ll_largerThanLowThresholdProbaSum_T_162 \| _ll_largerThanLowThresholdProbaSum_T_163; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_166 = _ll_largerThanLowThresholdProbaSum_T_164 \| _ll_largerThanLowThresholdProbaSum_T_165; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_167 = _ll_largerThanLowThresholdProbaSum_T_166 ? 16'h0 : ll_proba_27; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_170 = _ll_largerThanLowThresholdProbaSum_T_168 \| _ll_largerThanLowThresholdProbaSum_T_169; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_172 = _ll_largerThanLowThresholdProbaSum_T_170 \| _ll_largerThanLowThresholdProbaSum_T_171; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_173 = _ll_largerThanLowThresholdProbaSum_T_172 ? 16'h0 : ll_proba_28; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_176 = _ll_largerThanLowThresholdProbaSum_T_174 \| _ll_largerThanLowThresholdProbaSum_T_175; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_178 = _ll_largerThanLowThresholdProbaSum_T_176 \| _ll_largerThanLowThresholdProbaSum_T_177; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_179 = _ll_largerThanLowThresholdProbaSum_T_178 ? 16'h0 : ll_proba_29; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_182 = _ll_largerThanLowThresholdProbaSum_T_180 \| _ll_largerThanLowThresholdProbaSum_T_181; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_184 = _ll_largerThanLowThresholdProbaSum_T_182 \| _ll_largerThanLowThresholdProbaSum_T_183; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_185 = _ll_largerThanLowThresholdProbaSum_T_184 ? 16'h0 : ll_proba_30; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_188 = _ll_largerThanLowThresholdProbaSum_T_186 \| _ll_largerThanLowThresholdProbaSum_T_187; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_190 = _ll_largerThanLowThresholdProbaSum_T_188 \| _ll_largerThanLowThresholdProbaSum_T_189; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_191 = _ll_largerThanLowThresholdProbaSum_T_190 ? 16'h0 : ll_proba_31; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire [16:0] _ll_largerThanLowThresholdProbaSum_T_192 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_5} + {1'h0, _ll_largerThanLowThresholdProbaSum_T_11}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [17:0] _ll_largerThanLowThresholdProbaSum_T_193 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_192} + {2'h0, _ll_largerThanLowThresholdProbaSum_T_17}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [18:0] _ll_largerThanLowThresholdProbaSum_T_194 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_193} + {3'h0, _ll_largerThanLowThresholdProbaSum_T_23}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [19:0] _ll_largerThanLowThresholdProbaSum_T_195 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_194} + {4'h0, _ll_largerThanLowThresholdProbaSum_T_29}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [20:0] _ll_largerThanLowThresholdProbaSum_T_196 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_195} + {5'h0, _ll_largerThanLowThresholdProbaSum_T_35}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [21:0] _ll_largerThanLowThresholdProbaSum_T_197 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_196} + {6'h0, _ll_largerThanLowThresholdProbaSum_T_41}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [22:0] _ll_largerThanLowThresholdProbaSum_T_198 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_197} + {7'h0, _ll_largerThanLowThresholdProbaSum_T_47}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [23:0] _ll_largerThanLowThresholdProbaSum_T_199 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_198} + {8'h0, _ll_largerThanLowThresholdProbaSum_T_53}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [24:0] _ll_largerThanLowThresholdProbaSum_T_200 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_199} + {9'h0, _ll_largerThanLowThresholdProbaSum_T_59}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [25:0] _ll_largerThanLowThresholdProbaSum_T_201 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_200} + {10'h0, _ll_largerThanLowThresholdProbaSum_T_65}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [26:0] _ll_largerThanLowThresholdProbaSum_T_202 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_201} + {11'h0, _ll_largerThanLowThresholdProbaSum_T_71}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [27:0] _ll_largerThanLowThresholdProbaSum_T_203 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_202} + {12'h0, _ll_largerThanLowThresholdProbaSum_T_77}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [28:0] _ll_largerThanLowThresholdProbaSum_T_204 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_203} + {13'h0, _ll_largerThanLowThresholdProbaSum_T_83}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [29:0] _ll_largerThanLowThresholdProbaSum_T_205 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_204} + {14'h0, _ll_largerThanLowThresholdProbaSum_T_89}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [30:0] _ll_largerThanLowThresholdProbaSum_T_206 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_205} + {15'h0, _ll_largerThanLowThresholdProbaSum_T_95}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [31:0] _ll_largerThanLowThresholdProbaSum_T_207 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_206} + {16'h0, _ll_largerThanLowThresholdProbaSum_T_101}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [32:0] _ll_largerThanLowThresholdProbaSum_T_208 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_207} + {17'h0, _ll_largerThanLowThresholdProbaSum_T_107}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [33:0] _ll_largerThanLowThresholdProbaSum_T_209 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_208} + {18'h0, _ll_largerThanLowThresholdProbaSum_T_113}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [34:0] _ll_largerThanLowThresholdProbaSum_T_210 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_209} + {19'h0, _ll_largerThanLowThresholdProbaSum_T_119}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [35:0] _ll_largerThanLowThresholdProbaSum_T_211 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_210} + {20'h0, _ll_largerThanLowThresholdProbaSum_T_125}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [36:0] _ll_largerThanLowThresholdProbaSum_T_212 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_211} + {21'h0, _ll_largerThanLowThresholdProbaSum_T_131}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [37:0] _ll_largerThanLowThresholdProbaSum_T_213 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_212} + {22'h0, _ll_largerThanLowThresholdProbaSum_T_137}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [38:0] _ll_largerThanLowThresholdProbaSum_T_214 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_213} + {23'h0, _ll_largerThanLowThresholdProbaSum_T_143}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [39:0] _ll_largerThanLowThresholdProbaSum_T_215 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_214} + {24'h0, _ll_largerThanLowThresholdProbaSum_T_149}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [40:0] _ll_largerThanLowThresholdProbaSum_T_216 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_215} + {25'h0, _ll_largerThanLowThresholdProbaSum_T_155}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [41:0] _ll_largerThanLowThresholdProbaSum_T_217 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_216} + {26'h0, _ll_largerThanLowThresholdProbaSum_T_161}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [42:0] _ll_largerThanLowThresholdProbaSum_T_218 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_217} + {27'h0, _ll_largerThanLowThresholdProbaSum_T_167}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [43:0] _ll_largerThanLowThresholdProbaSum_T_219 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_218} + {28'h0, _ll_largerThanLowThresholdProbaSum_T_173}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [44:0] _ll_largerThanLowThresholdProbaSum_T_220 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_219} + {29'h0, _ll_largerThanLowThresholdProbaSum_T_179}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [45:0] _ll_largerThanLowThresholdProbaSum_T_221 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_220} + {30'h0, _ll_largerThanLowThresholdProbaSum_T_185}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [46:0] ll_largerThanLowThresholdProbaSum = {1'h0, _ll_largerThanLowThresholdProbaSum_T_221} + {31'h0, _ll_largerThanLowThresholdProbaSum_T_191}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire _ll_normalizedCounterMax_T = ll_normalizedCounter_0 > ll_normalizedCounter_1; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_1 = _ll_normalizedCounterMax_T ? ll_normalizedCounter_0 : ll_normalizedCounter_1; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_2 = ll_normalizedCounter_2 > ll_normalizedCounter_3; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_3 = _ll_normalizedCounterMax_T_2 ? ll_normalizedCounter_2 : ll_normalizedCounter_3; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_4 = ll_normalizedCounter_4 > ll_normalizedCounter_5; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_5 = _ll_normalizedCounterMax_T_4 ? ll_normalizedCounter_4 : ll_normalizedCounter_5; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_6 = ll_normalizedCounter_6 > ll_normalizedCounter_7; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_7 = _ll_normalizedCounterMax_T_6 ? ll_normalizedCounter_6 : ll_normalizedCounter_7; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_8 = ll_normalizedCounter_8 > ll_normalizedCounter_9; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_9 = _ll_normalizedCounterMax_T_8 ? ll_normalizedCounter_8 : ll_normalizedCounter_9; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_10 = ll_normalizedCounter_10 > ll_normalizedCounter_11; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_11 = _ll_normalizedCounterMax_T_10 ? ll_normalizedCounter_10 : ll_normalizedCounter_11; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_12 = ll_normalizedCounter_12 > ll_normalizedCounter_13; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_13 = _ll_normalizedCounterMax_T_12 ? ll_normalizedCounter_12 : ll_normalizedCounter_13; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_14 = ll_normalizedCounter_14 > ll_normalizedCounter_15; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_15 = _ll_normalizedCounterMax_T_14 ? ll_normalizedCounter_14 : ll_normalizedCounter_15; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_16 = ll_normalizedCounter_16 > ll_normalizedCounter_17; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_17 = _ll_normalizedCounterMax_T_16 ? ll_normalizedCounter_16 : ll_normalizedCounter_17; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_18 = ll_normalizedCounter_18 > ll_normalizedCounter_19; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_19 = _ll_normalizedCounterMax_T_18 ? ll_normalizedCounter_18 : ll_normalizedCounter_19; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_20 = ll_normalizedCounter_20 > ll_normalizedCounter_21; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_21 = _ll_normalizedCounterMax_T_20 ? ll_normalizedCounter_20 : ll_normalizedCounter_21; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_22 = ll_normalizedCounter_22 > ll_normalizedCounter_23; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_23 = _ll_normalizedCounterMax_T_22 ? ll_normalizedCounter_22 : ll_normalizedCounter_23; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_24 = ll_normalizedCounter_24 > ll_normalizedCounter_25; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_25 = _ll_normalizedCounterMax_T_24 ? ll_normalizedCounter_24 : ll_normalizedCounter_25; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_26 = ll_normalizedCounter_26 > ll_normalizedCounter_27; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_27 = _ll_normalizedCounterMax_T_26 ? ll_normalizedCounter_26 : ll_normalizedCounter_27; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_28 = ll_normalizedCounter_28 > ll_normalizedCounter_29; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_29 = _ll_normalizedCounterMax_T_28 ? ll_normalizedCounter_28 : ll_normalizedCounter_29; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_30 = ll_normalizedCounter_30 > ll_normalizedCounter_31; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_31 = _ll_normalizedCounterMax_T_30 ? ll_normalizedCounter_30 : ll_normalizedCounter_31; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_32 = _ll_normalizedCounterMax_T_1 > _ll_normalizedCounterMax_T_3; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_33 = _ll_normalizedCounterMax_T_32 ? _ll_normalizedCounterMax_T_1 : _ll_normalizedCounterMax_T_3; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_34 = _ll_normalizedCounterMax_T_5 > _ll_normalizedCounterMax_T_7; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_35 = _ll_normalizedCounterMax_T_34 ? _ll_normalizedCounterMax_T_5 : _ll_normalizedCounterMax_T_7; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_36 = _ll_normalizedCounterMax_T_9 > _ll_normalizedCounterMax_T_11; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_37 = _ll_normalizedCounterMax_T_36 ? _ll_normalizedCounterMax_T_9 : _ll_normalizedCounterMax_T_11; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_38 = _ll_normalizedCounterMax_T_13 > _ll_normalizedCounterMax_T_15; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_39 = _ll_normalizedCounterMax_T_38 ? _ll_normalizedCounterMax_T_13 : _ll_normalizedCounterMax_T_15; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_40 = _ll_normalizedCounterMax_T_17 > _ll_normalizedCounterMax_T_19; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_41 = _ll_normalizedCounterMax_T_40 ? _ll_normalizedCounterMax_T_17 : _ll_normalizedCounterMax_T_19; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_42 = _ll_normalizedCounterMax_T_21 > _ll_normalizedCounterMax_T_23; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_43 = _ll_normalizedCounterMax_T_42 ? _ll_normalizedCounterMax_T_21 : _ll_normalizedCounterMax_T_23; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_44 = _ll_normalizedCounterMax_T_25 > _ll_normalizedCounterMax_T_27; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_45 = _ll_normalizedCounterMax_T_44 ? _ll_normalizedCounterMax_T_25 : _ll_normalizedCounterMax_T_27; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_46 = _ll_normalizedCounterMax_T_29 > _ll_normalizedCounterMax_T_31; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_47 = _ll_normalizedCounterMax_T_46 ? _ll_normalizedCounterMax_T_29 : _ll_normalizedCounterMax_T_31; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_48 = _ll_normalizedCounterMax_T_33 > _ll_normalizedCounterMax_T_35; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_49 = _ll_normalizedCounterMax_T_48 ? _ll_normalizedCounterMax_T_33 : _ll_normalizedCounterMax_T_35; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_50 = _ll_normalizedCounterMax_T_37 > _ll_normalizedCounterMax_T_39; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_51 = _ll_normalizedCounterMax_T_50 ? _ll_normalizedCounterMax_T_37 : _ll_normalizedCounterMax_T_39; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_52 = _ll_normalizedCounterMax_T_41 > _ll_normalizedCounterMax_T_43; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_53 = _ll_normalizedCounterMax_T_52 ? _ll_normalizedCounterMax_T_41 : _ll_normalizedCounterMax_T_43; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_54 = _ll_normalizedCounterMax_T_45 > _ll_normalizedCounterMax_T_47; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_55 = _ll_normalizedCounterMax_T_54 ? _ll_normalizedCounterMax_T_45 : _ll_normalizedCounterMax_T_47; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_56 = _ll_normalizedCounterMax_T_49 > _ll_normalizedCounterMax_T_51; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_57 = _ll_normalizedCounterMax_T_56 ? _ll_normalizedCounterMax_T_49 : _ll_normalizedCounterMax_T_51; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_58 = _ll_normalizedCounterMax_T_53 > _ll_normalizedCounterMax_T_55; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_59 = _ll_normalizedCounterMax_T_58 ? _ll_normalizedCounterMax_T_53 : _ll_normalizedCounterMax_T_55; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_60 = _ll_normalizedCounterMax_T_57 > _ll_normalizedCounterMax_T_59; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] ll_normalizedCounterMax = _ll_normalizedCounterMax_T_60 ? _ll_normalizedCounterMax_T_57 : _ll_normalizedCounterMax_T_59; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _GEN_165 = ll_normalizedCounter_0 < ll_normalizedCounter_1; // @[FSECompressorDicBuilder.scala:277:38, :307:15] wire _ll_normalizedCounterMaxIdx_T; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T = _GEN_165; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_2; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_2 = _GEN_165; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_1 = _ll_normalizedCounterMaxIdx_T ? ll_normalizedCounter_1 : ll_normalizedCounter_0; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_3 = {15'h0, _ll_normalizedCounterMaxIdx_T_2}; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_166 = _ll_normalizedCounterMaxIdx_T_1 < ll_normalizedCounter_2; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_4; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_4 = _GEN_166; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_6; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_6 = _GEN_166; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_5 = _ll_normalizedCounterMaxIdx_T_4 ? ll_normalizedCounter_2 : _ll_normalizedCounterMaxIdx_T_1; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_7 = _ll_normalizedCounterMaxIdx_T_6 ? 16'h2 : _ll_normalizedCounterMaxIdx_T_3; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_167 = _ll_normalizedCounterMaxIdx_T_5 < ll_normalizedCounter_3; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_8; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_8 = _GEN_167; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_10; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_10 = _GEN_167; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_9 = _ll_normalizedCounterMaxIdx_T_8 ? ll_normalizedCounter_3 : _ll_normalizedCounterMaxIdx_T_5; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_11 = _ll_normalizedCounterMaxIdx_T_10 ? 16'h3 : _ll_normalizedCounterMaxIdx_T_7; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_168 = _ll_normalizedCounterMaxIdx_T_9 < ll_normalizedCounter_4; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_12; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_12 = _GEN_168; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_14; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_14 = _GEN_168; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_13 = _ll_normalizedCounterMaxIdx_T_12 ? ll_normalizedCounter_4 : _ll_normalizedCounterMaxIdx_T_9; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_15 = _ll_normalizedCounterMaxIdx_T_14 ? 16'h4 : _ll_normalizedCounterMaxIdx_T_11; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_169 = _ll_normalizedCounterMaxIdx_T_13 < ll_normalizedCounter_5; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_16; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_16 = _GEN_169; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_18; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_18 = _GEN_169; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_17 = _ll_normalizedCounterMaxIdx_T_16 ? ll_normalizedCounter_5 : _ll_normalizedCounterMaxIdx_T_13; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_19 = _ll_normalizedCounterMaxIdx_T_18 ? 16'h5 : _ll_normalizedCounterMaxIdx_T_15; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_170 = _ll_normalizedCounterMaxIdx_T_17 < ll_normalizedCounter_6; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_20; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_20 = _GEN_170; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_22; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_22 = _GEN_170; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_21 = _ll_normalizedCounterMaxIdx_T_20 ? ll_normalizedCounter_6 : _ll_normalizedCounterMaxIdx_T_17; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_23 = _ll_normalizedCounterMaxIdx_T_22 ? 16'h6 : _ll_normalizedCounterMaxIdx_T_19; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_171 = _ll_normalizedCounterMaxIdx_T_21 < ll_normalizedCounter_7; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_24; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_24 = _GEN_171; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_26; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_26 = _GEN_171; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_25 = _ll_normalizedCounterMaxIdx_T_24 ? ll_normalizedCounter_7 : _ll_normalizedCounterMaxIdx_T_21; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_27 = _ll_normalizedCounterMaxIdx_T_26 ? 16'h7 : _ll_normalizedCounterMaxIdx_T_23; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_172 = _ll_normalizedCounterMaxIdx_T_25 < ll_normalizedCounter_8; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_28; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_28 = _GEN_172; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_30; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_30 = _GEN_172; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_29 = _ll_normalizedCounterMaxIdx_T_28 ? ll_normalizedCounter_8 : _ll_normalizedCounterMaxIdx_T_25; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_31 = _ll_normalizedCounterMaxIdx_T_30 ? 16'h8 : _ll_normalizedCounterMaxIdx_T_27; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_173 = _ll_normalizedCounterMaxIdx_T_29 < ll_normalizedCounter_9; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_32; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_32 = _GEN_173; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_34; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_34 = _GEN_173; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_33 = _ll_normalizedCounterMaxIdx_T_32 ? ll_normalizedCounter_9 : _ll_normalizedCounterMaxIdx_T_29; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_35 = _ll_normalizedCounterMaxIdx_T_34 ? 16'h9 : _ll_normalizedCounterMaxIdx_T_31; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_174 = _ll_normalizedCounterMaxIdx_T_33 < ll_normalizedCounter_10; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_36; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_36 = _GEN_174; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_38; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_38 = _GEN_174; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_37 = _ll_normalizedCounterMaxIdx_T_36 ? ll_normalizedCounter_10 : _ll_normalizedCounterMaxIdx_T_33; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_39 = _ll_normalizedCounterMaxIdx_T_38 ? 16'hA : _ll_normalizedCounterMaxIdx_T_35; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_175 = _ll_normalizedCounterMaxIdx_T_37 < ll_normalizedCounter_11; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_40; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_40 = _GEN_175; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_42; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_42 = _GEN_175; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_41 = _ll_normalizedCounterMaxIdx_T_40 ? ll_normalizedCounter_11 : _ll_normalizedCounterMaxIdx_T_37; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_43 = _ll_normalizedCounterMaxIdx_T_42 ? 16'hB : _ll_normalizedCounterMaxIdx_T_39; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_176 = _ll_normalizedCounterMaxIdx_T_41 < ll_normalizedCounter_12; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_44; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_44 = _GEN_176; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_46; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_46 = _GEN_176; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_45 = _ll_normalizedCounterMaxIdx_T_44 ? ll_normalizedCounter_12 : _ll_normalizedCounterMaxIdx_T_41; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_47 = _ll_normalizedCounterMaxIdx_T_46 ? 16'hC : _ll_normalizedCounterMaxIdx_T_43; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_177 = _ll_normalizedCounterMaxIdx_T_45 < ll_normalizedCounter_13; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_48; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_48 = _GEN_177; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_50; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_50 = _GEN_177; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_49 = _ll_normalizedCounterMaxIdx_T_48 ? ll_normalizedCounter_13 : _ll_normalizedCounterMaxIdx_T_45; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_51 = _ll_normalizedCounterMaxIdx_T_50 ? 16'hD : _ll_normalizedCounterMaxIdx_T_47; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_178 = _ll_normalizedCounterMaxIdx_T_49 < ll_normalizedCounter_14; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_52; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_52 = _GEN_178; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_54; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_54 = _GEN_178; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_53 = _ll_normalizedCounterMaxIdx_T_52 ? ll_normalizedCounter_14 : _ll_normalizedCounterMaxIdx_T_49; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_55 = _ll_normalizedCounterMaxIdx_T_54 ? 16'hE : _ll_normalizedCounterMaxIdx_T_51; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_179 = _ll_normalizedCounterMaxIdx_T_53 < ll_normalizedCounter_15; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_56; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_56 = _GEN_179; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_58; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_58 = _GEN_179; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_57 = _ll_normalizedCounterMaxIdx_T_56 ? ll_normalizedCounter_15 : _ll_normalizedCounterMaxIdx_T_53; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_59 = _ll_normalizedCounterMaxIdx_T_58 ? 16'hF : _ll_normalizedCounterMaxIdx_T_55; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_180 = _ll_normalizedCounterMaxIdx_T_57 < ll_normalizedCounter_16; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_60; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_60 = _GEN_180; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_62; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_62 = _GEN_180; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_61 = _ll_normalizedCounterMaxIdx_T_60 ? ll_normalizedCounter_16 : _ll_normalizedCounterMaxIdx_T_57; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_63 = _ll_normalizedCounterMaxIdx_T_62 ? 16'h10 : _ll_normalizedCounterMaxIdx_T_59; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_181 = _ll_normalizedCounterMaxIdx_T_61 < ll_normalizedCounter_17; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_64; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_64 = _GEN_181; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_66; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_66 = _GEN_181; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_65 = _ll_normalizedCounterMaxIdx_T_64 ? ll_normalizedCounter_17 : _ll_normalizedCounterMaxIdx_T_61; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_67 = _ll_normalizedCounterMaxIdx_T_66 ? 16'h11 : _ll_normalizedCounterMaxIdx_T_63; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_182 = _ll_normalizedCounterMaxIdx_T_65 < ll_normalizedCounter_18; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_68; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_68 = _GEN_182; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_70; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_70 = _GEN_182; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_69 = _ll_normalizedCounterMaxIdx_T_68 ? ll_normalizedCounter_18 : _ll_normalizedCounterMaxIdx_T_65; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_71 = _ll_normalizedCounterMaxIdx_T_70 ? 16'h12 : _ll_normalizedCounterMaxIdx_T_67; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_183 = _ll_normalizedCounterMaxIdx_T_69 < ll_normalizedCounter_19; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_72; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_72 = _GEN_183; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_74; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_74 = _GEN_183; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_73 = _ll_normalizedCounterMaxIdx_T_72 ? ll_normalizedCounter_19 : _ll_normalizedCounterMaxIdx_T_69; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_75 = _ll_normalizedCounterMaxIdx_T_74 ? 16'h13 : _ll_normalizedCounterMaxIdx_T_71; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_184 = _ll_normalizedCounterMaxIdx_T_73 < ll_normalizedCounter_20; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_76; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_76 = _GEN_184; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_78; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_78 = _GEN_184; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_77 = _ll_normalizedCounterMaxIdx_T_76 ? ll_normalizedCounter_20 : _ll_normalizedCounterMaxIdx_T_73; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_79 = _ll_normalizedCounterMaxIdx_T_78 ? 16'h14 : _ll_normalizedCounterMaxIdx_T_75; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_185 = _ll_normalizedCounterMaxIdx_T_77 < ll_normalizedCounter_21; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_80; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_80 = _GEN_185; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_82; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_82 = _GEN_185; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_81 = _ll_normalizedCounterMaxIdx_T_80 ? ll_normalizedCounter_21 : _ll_normalizedCounterMaxIdx_T_77; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_83 = _ll_normalizedCounterMaxIdx_T_82 ? 16'h15 : _ll_normalizedCounterMaxIdx_T_79; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_186 = _ll_normalizedCounterMaxIdx_T_81 < ll_normalizedCounter_22; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_84; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_84 = _GEN_186; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_86; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_86 = _GEN_186; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_85 = _ll_normalizedCounterMaxIdx_T_84 ? ll_normalizedCounter_22 : _ll_normalizedCounterMaxIdx_T_81; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_87 = _ll_normalizedCounterMaxIdx_T_86 ? 16'h16 : _ll_normalizedCounterMaxIdx_T_83; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_187 = _ll_normalizedCounterMaxIdx_T_85 < ll_normalizedCounter_23; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_88; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_88 = _GEN_187; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_90; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_90 = _GEN_187; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_89 = _ll_normalizedCounterMaxIdx_T_88 ? ll_normalizedCounter_23 : _ll_normalizedCounterMaxIdx_T_85; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_91 = _ll_normalizedCounterMaxIdx_T_90 ? 16'h17 : _ll_normalizedCounterMaxIdx_T_87; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_188 = _ll_normalizedCounterMaxIdx_T_89 < ll_normalizedCounter_24; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_92; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_92 = _GEN_188; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_94; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_94 = _GEN_188; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_93 = _ll_normalizedCounterMaxIdx_T_92 ? ll_normalizedCounter_24 : _ll_normalizedCounterMaxIdx_T_89; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_95 = _ll_normalizedCounterMaxIdx_T_94 ? 16'h18 : _ll_normalizedCounterMaxIdx_T_91; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_189 = _ll_normalizedCounterMaxIdx_T_93 < ll_normalizedCounter_25; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_96; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_96 = _GEN_189; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_98; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_98 = _GEN_189; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_97 = _ll_normalizedCounterMaxIdx_T_96 ? ll_normalizedCounter_25 : _ll_normalizedCounterMaxIdx_T_93; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_99 = _ll_normalizedCounterMaxIdx_T_98 ? 16'h19 : _ll_normalizedCounterMaxIdx_T_95; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_190 = _ll_normalizedCounterMaxIdx_T_97 < ll_normalizedCounter_26; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_100; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_100 = _GEN_190; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_102; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_102 = _GEN_190; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_101 = _ll_normalizedCounterMaxIdx_T_100 ? ll_normalizedCounter_26 : _ll_normalizedCounterMaxIdx_T_97; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_103 = _ll_normalizedCounterMaxIdx_T_102 ? 16'h1A : _ll_normalizedCounterMaxIdx_T_99; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_191 = _ll_normalizedCounterMaxIdx_T_101 < ll_normalizedCounter_27; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_104; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_104 = _GEN_191; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_106; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_106 = _GEN_191; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_105 = _ll_normalizedCounterMaxIdx_T_104 ? ll_normalizedCounter_27 : _ll_normalizedCounterMaxIdx_T_101; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_107 = _ll_normalizedCounterMaxIdx_T_106 ? 16'h1B : _ll_normalizedCounterMaxIdx_T_103; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_192 = _ll_normalizedCounterMaxIdx_T_105 < ll_normalizedCounter_28; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_108; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_108 = _GEN_192; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_110; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_110 = _GEN_192; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_109 = _ll_normalizedCounterMaxIdx_T_108 ? ll_normalizedCounter_28 : _ll_normalizedCounterMaxIdx_T_105; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_111 = _ll_normalizedCounterMaxIdx_T_110 ? 16'h1C : _ll_normalizedCounterMaxIdx_T_107; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_193 = _ll_normalizedCounterMaxIdx_T_109 < ll_normalizedCounter_29; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_112; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_112 = _GEN_193; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_114; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_114 = _GEN_193; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_113 = _ll_normalizedCounterMaxIdx_T_112 ? ll_normalizedCounter_29 : _ll_normalizedCounterMaxIdx_T_109; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_115 = _ll_normalizedCounterMaxIdx_T_114 ? 16'h1D : _ll_normalizedCounterMaxIdx_T_111; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_194 = _ll_normalizedCounterMaxIdx_T_113 < ll_normalizedCounter_30; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_116; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_116 = _GEN_194; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_118; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_118 = _GEN_194; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_117 = _ll_normalizedCounterMaxIdx_T_116 ? ll_normalizedCounter_30 : _ll_normalizedCounterMaxIdx_T_113; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_119 = _ll_normalizedCounterMaxIdx_T_118 ? 16'h1E : _ll_normalizedCounterMaxIdx_T_115; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_195 = _ll_normalizedCounterMaxIdx_T_117 < ll_normalizedCounter_31; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_120; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_120 = _GEN_195; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_122; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_122 = _GEN_195; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_121 = _ll_normalizedCounterMaxIdx_T_120 ? ll_normalizedCounter_31 : _ll_normalizedCounterMaxIdx_T_117; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] ll_normalizedCounterMaxIdx = _ll_normalizedCounterMaxIdx_T_122 ? 16'h1F : _ll_normalizedCounterMaxIdx_T_119; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire [47:0] _ll_nxtStillToDistribute_T = 48'h40 - {1'h0, ll_largerThanLowThresholdProbaSum}; // @[FSECompressorDicBuilder.scala:298:14, :310:57] wire [46:0] _ll_nxtStillToDistribute_T_1 = _ll_nxtStillToDistribute_T[46:0]; // @[FSECompressorDicBuilder.scala:310:57] wire [47:0] _ll_nxtStillToDistribute_T_2 = {1'h0, _ll_nxtStillToDistribute_T_1} - {16'h0, ll_smallOrEqToLowThresholdCount}; // @[FSECompressorDicBuilder.scala:292:14, :310:{57,93}] wire [46:0] _ll_nxtStillToDistribute_T_3 = _ll_nxtStillToDistribute_T_2[46:0]; // @[FSECompressorDicBuilder.scala:310:93] wire [46:0] ll_nxtStillToDistribute = _ll_nxtStillToDistribute_T_3; // @[FSECompressorDicBuilder.scala:310:{93,128}] wire [47:0] _GEN_196 = {ll_nxtStillToDistribute[46], ll_nxtStillToDistribute}; // @[FSECompressorDicBuilder.scala:310:128, :311:43] wire [47:0] ll_negNxtStillToDistribute = _GEN_196 * 48'hFFFFFFFFFFFF; // @[FSECompressorDicBuilder.scala:311:43] wire [15:0] _fse_normalize_corner_case_T = {1'h0, ll_normalizedCounterMax[15:1]}; // @[FSECompressorDicBuilder.scala:300:78, :313:90] wire [15:0] _fse_normalize_corner_case_T_1 = _fse_normalize_corner_case_T; // @[FSECompressorDicBuilder.scala:313:{90,98}] wire fse_normalize_corner_case = $signed(ll_negNxtStillToDistribute) >= $signed({{32{_fse_normalize_corner_case_T_1[15]}}, _fse_normalize_corner_case_T_1}); // @[FSECompressorDicBuilder.scala:311:43, :313:{62,98}] reg fse_normalize_corner_case_reg; // @[FSECompressorDicBuilder.scala:314:46] wire _T_846 = dicBuilderState == 4'h2; // @[FSECompressorDicBuilder.scala:156:32, :316:25] wire _T_3 = _T_846 & _predefined_mode_q_io_enq_ready; // @[FSECompressorDicBuilder.scala:141:33, :316:{25,45}] wire [47:0] _ll_ncountSumStill2Dist_T_1 = {{32{_ll_ncountSumStill2Dist_T[15]}}, _ll_ncountSumStill2Dist_T} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_2 = _ll_ncountSumStill2Dist_T_1[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_3 = _ll_ncountSumStill2Dist_T_2; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist = _ll_ncountSumStill2Dist_T_3; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_0_T = ll_normalizedCounterMaxIdx == 16'h0; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_0_T_1 = _ll_normalizedCounterMaxAdjusted_0_T ? ll_ncountSumStill2Dist : {31'h0, ll_normalizedCounter_0}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_0 = _T_3 ? _ll_normalizedCounterMaxAdjusted_0_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_5 = {{32{_ll_ncountSumStill2Dist_T_4[15]}}, _ll_ncountSumStill2Dist_T_4} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_6 = _ll_ncountSumStill2Dist_T_5[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_7 = _ll_ncountSumStill2Dist_T_6; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_1 = _ll_ncountSumStill2Dist_T_7; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_1_T = ll_normalizedCounterMaxIdx == 16'h1; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_1_T_1 = _ll_normalizedCounterMaxAdjusted_1_T ? ll_ncountSumStill2Dist_1 : {31'h0, ll_normalizedCounter_1}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_1 = _T_3 ? _ll_normalizedCounterMaxAdjusted_1_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_9 = {{32{_ll_ncountSumStill2Dist_T_8[15]}}, _ll_ncountSumStill2Dist_T_8} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_10 = _ll_ncountSumStill2Dist_T_9[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_11 = _ll_ncountSumStill2Dist_T_10; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_2 = _ll_ncountSumStill2Dist_T_11; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_2_T = ll_normalizedCounterMaxIdx == 16'h2; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_2_T_1 = _ll_normalizedCounterMaxAdjusted_2_T ? ll_ncountSumStill2Dist_2 : {31'h0, ll_normalizedCounter_2}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_2 = _T_3 ? _ll_normalizedCounterMaxAdjusted_2_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_13 = {{32{_ll_ncountSumStill2Dist_T_12[15]}}, _ll_ncountSumStill2Dist_T_12} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_14 = _ll_ncountSumStill2Dist_T_13[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_15 = _ll_ncountSumStill2Dist_T_14; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_3 = _ll_ncountSumStill2Dist_T_15; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_3_T = ll_normalizedCounterMaxIdx == 16'h3; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_3_T_1 = _ll_normalizedCounterMaxAdjusted_3_T ? ll_ncountSumStill2Dist_3 : {31'h0, ll_normalizedCounter_3}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_3 = _T_3 ? _ll_normalizedCounterMaxAdjusted_3_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_17 = {{32{_ll_ncountSumStill2Dist_T_16[15]}}, _ll_ncountSumStill2Dist_T_16} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_18 = _ll_ncountSumStill2Dist_T_17[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_19 = _ll_ncountSumStill2Dist_T_18; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_4 = _ll_ncountSumStill2Dist_T_19; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_4_T = ll_normalizedCounterMaxIdx == 16'h4; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_4_T_1 = _ll_normalizedCounterMaxAdjusted_4_T ? ll_ncountSumStill2Dist_4 : {31'h0, ll_normalizedCounter_4}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_4 = _T_3 ? _ll_normalizedCounterMaxAdjusted_4_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_21 = {{32{_ll_ncountSumStill2Dist_T_20[15]}}, _ll_ncountSumStill2Dist_T_20} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_22 = _ll_ncountSumStill2Dist_T_21[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_23 = _ll_ncountSumStill2Dist_T_22; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_5 = _ll_ncountSumStill2Dist_T_23; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_5_T = ll_normalizedCounterMaxIdx == 16'h5; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_5_T_1 = _ll_normalizedCounterMaxAdjusted_5_T ? ll_ncountSumStill2Dist_5 : {31'h0, ll_normalizedCounter_5}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_5 = _T_3 ? _ll_normalizedCounterMaxAdjusted_5_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_25 = {{32{_ll_ncountSumStill2Dist_T_24[15]}}, _ll_ncountSumStill2Dist_T_24} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_26 = _ll_ncountSumStill2Dist_T_25[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_27 = _ll_ncountSumStill2Dist_T_26; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_6 = _ll_ncountSumStill2Dist_T_27; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_6_T = ll_normalizedCounterMaxIdx == 16'h6; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_6_T_1 = _ll_normalizedCounterMaxAdjusted_6_T ? ll_ncountSumStill2Dist_6 : {31'h0, ll_normalizedCounter_6}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_6 = _T_3 ? _ll_normalizedCounterMaxAdjusted_6_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_29 = {{32{_ll_ncountSumStill2Dist_T_28[15]}}, _ll_ncountSumStill2Dist_T_28} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_30 = _ll_ncountSumStill2Dist_T_29[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_31 = _ll_ncountSumStill2Dist_T_30; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_7 = _ll_ncountSumStill2Dist_T_31; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_7_T = ll_normalizedCounterMaxIdx == 16'h7; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_7_T_1 = _ll_normalizedCounterMaxAdjusted_7_T ? ll_ncountSumStill2Dist_7 : {31'h0, ll_normalizedCounter_7}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_7 = _T_3 ? _ll_normalizedCounterMaxAdjusted_7_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_33 = {{32{_ll_ncountSumStill2Dist_T_32[15]}}, _ll_ncountSumStill2Dist_T_32} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_34 = _ll_ncountSumStill2Dist_T_33[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_35 = _ll_ncountSumStill2Dist_T_34; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_8 = _ll_ncountSumStill2Dist_T_35; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_8_T = ll_normalizedCounterMaxIdx == 16'h8; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_8_T_1 = _ll_normalizedCounterMaxAdjusted_8_T ? ll_ncountSumStill2Dist_8 : {31'h0, ll_normalizedCounter_8}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_8 = _T_3 ? _ll_normalizedCounterMaxAdjusted_8_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_37 = {{32{_ll_ncountSumStill2Dist_T_36[15]}}, _ll_ncountSumStill2Dist_T_36} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_38 = _ll_ncountSumStill2Dist_T_37[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_39 = _ll_ncountSumStill2Dist_T_38; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_9 = _ll_ncountSumStill2Dist_T_39; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_9_T = ll_normalizedCounterMaxIdx == 16'h9; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_9_T_1 = _ll_normalizedCounterMaxAdjusted_9_T ? ll_ncountSumStill2Dist_9 : {31'h0, ll_normalizedCounter_9}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_9 = _T_3 ? _ll_normalizedCounterMaxAdjusted_9_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_41 = {{32{_ll_ncountSumStill2Dist_T_40[15]}}, _ll_ncountSumStill2Dist_T_40} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_42 = _ll_ncountSumStill2Dist_T_41[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_43 = _ll_ncountSumStill2Dist_T_42; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_10 = _ll_ncountSumStill2Dist_T_43; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_10_T = ll_normalizedCounterMaxIdx == 16'hA; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_10_T_1 = _ll_normalizedCounterMaxAdjusted_10_T ? ll_ncountSumStill2Dist_10 : {31'h0, ll_normalizedCounter_10}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_10 = _T_3 ? _ll_normalizedCounterMaxAdjusted_10_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_45 = {{32{_ll_ncountSumStill2Dist_T_44[15]}}, _ll_ncountSumStill2Dist_T_44} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_46 = _ll_ncountSumStill2Dist_T_45[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_47 = _ll_ncountSumStill2Dist_T_46; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_11 = _ll_ncountSumStill2Dist_T_47; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_11_T = ll_normalizedCounterMaxIdx == 16'hB; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_11_T_1 = _ll_normalizedCounterMaxAdjusted_11_T ? ll_ncountSumStill2Dist_11 : {31'h0, ll_normalizedCounter_11}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_11 = _T_3 ? _ll_normalizedCounterMaxAdjusted_11_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_49 = {{32{_ll_ncountSumStill2Dist_T_48[15]}}, _ll_ncountSumStill2Dist_T_48} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_50 = _ll_ncountSumStill2Dist_T_49[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_51 = _ll_ncountSumStill2Dist_T_50; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_12 = _ll_ncountSumStill2Dist_T_51; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_12_T = ll_normalizedCounterMaxIdx == 16'hC; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_12_T_1 = _ll_normalizedCounterMaxAdjusted_12_T ? ll_ncountSumStill2Dist_12 : {31'h0, ll_normalizedCounter_12}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_12 = _T_3 ? _ll_normalizedCounterMaxAdjusted_12_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_53 = {{32{_ll_ncountSumStill2Dist_T_52[15]}}, _ll_ncountSumStill2Dist_T_52} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_54 = _ll_ncountSumStill2Dist_T_53[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_55 = _ll_ncountSumStill2Dist_T_54; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_13 = _ll_ncountSumStill2Dist_T_55; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_13_T = ll_normalizedCounterMaxIdx == 16'hD; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_13_T_1 = _ll_normalizedCounterMaxAdjusted_13_T ? ll_ncountSumStill2Dist_13 : {31'h0, ll_normalizedCounter_13}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_13 = _T_3 ? _ll_normalizedCounterMaxAdjusted_13_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_57 = {{32{_ll_ncountSumStill2Dist_T_56[15]}}, _ll_ncountSumStill2Dist_T_56} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_58 = _ll_ncountSumStill2Dist_T_57[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_59 = _ll_ncountSumStill2Dist_T_58; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_14 = _ll_ncountSumStill2Dist_T_59; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_14_T = ll_normalizedCounterMaxIdx == 16'hE; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_14_T_1 = _ll_normalizedCounterMaxAdjusted_14_T ? ll_ncountSumStill2Dist_14 : {31'h0, ll_normalizedCounter_14}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_14 = _T_3 ? _ll_normalizedCounterMaxAdjusted_14_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_61 = {{32{_ll_ncountSumStill2Dist_T_60[15]}}, _ll_ncountSumStill2Dist_T_60} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_62 = _ll_ncountSumStill2Dist_T_61[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_63 = _ll_ncountSumStill2Dist_T_62; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_15 = _ll_ncountSumStill2Dist_T_63; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_15_T = ll_normalizedCounterMaxIdx == 16'hF; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_15_T_1 = _ll_normalizedCounterMaxAdjusted_15_T ? ll_ncountSumStill2Dist_15 : {31'h0, ll_normalizedCounter_15}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_15 = _T_3 ? _ll_normalizedCounterMaxAdjusted_15_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_65 = {{32{_ll_ncountSumStill2Dist_T_64[15]}}, _ll_ncountSumStill2Dist_T_64} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_66 = _ll_ncountSumStill2Dist_T_65[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_67 = _ll_ncountSumStill2Dist_T_66; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_16 = _ll_ncountSumStill2Dist_T_67; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_16_T = ll_normalizedCounterMaxIdx == 16'h10; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_16_T_1 = _ll_normalizedCounterMaxAdjusted_16_T ? ll_ncountSumStill2Dist_16 : {31'h0, ll_normalizedCounter_16}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_16 = _T_3 ? _ll_normalizedCounterMaxAdjusted_16_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_69 = {{32{_ll_ncountSumStill2Dist_T_68[15]}}, _ll_ncountSumStill2Dist_T_68} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_70 = _ll_ncountSumStill2Dist_T_69[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_71 = _ll_ncountSumStill2Dist_T_70; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_17 = _ll_ncountSumStill2Dist_T_71; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_17_T = ll_normalizedCounterMaxIdx == 16'h11; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_17_T_1 = _ll_normalizedCounterMaxAdjusted_17_T ? ll_ncountSumStill2Dist_17 : {31'h0, ll_normalizedCounter_17}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_17 = _T_3 ? _ll_normalizedCounterMaxAdjusted_17_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_73 = {{32{_ll_ncountSumStill2Dist_T_72[15]}}, _ll_ncountSumStill2Dist_T_72} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_74 = _ll_ncountSumStill2Dist_T_73[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_75 = _ll_ncountSumStill2Dist_T_74; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_18 = _ll_ncountSumStill2Dist_T_75; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_18_T = ll_normalizedCounterMaxIdx == 16'h12; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_18_T_1 = _ll_normalizedCounterMaxAdjusted_18_T ? ll_ncountSumStill2Dist_18 : {31'h0, ll_normalizedCounter_18}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_18 = _T_3 ? _ll_normalizedCounterMaxAdjusted_18_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_77 = {{32{_ll_ncountSumStill2Dist_T_76[15]}}, _ll_ncountSumStill2Dist_T_76} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_78 = _ll_ncountSumStill2Dist_T_77[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_79 = _ll_ncountSumStill2Dist_T_78; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_19 = _ll_ncountSumStill2Dist_T_79; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_19_T = ll_normalizedCounterMaxIdx == 16'h13; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_19_T_1 = _ll_normalizedCounterMaxAdjusted_19_T ? ll_ncountSumStill2Dist_19 : {31'h0, ll_normalizedCounter_19}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_19 = _T_3 ? _ll_normalizedCounterMaxAdjusted_19_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_81 = {{32{_ll_ncountSumStill2Dist_T_80[15]}}, _ll_ncountSumStill2Dist_T_80} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_82 = _ll_ncountSumStill2Dist_T_81[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_83 = _ll_ncountSumStill2Dist_T_82; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_20 = _ll_ncountSumStill2Dist_T_83; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_20_T = ll_normalizedCounterMaxIdx == 16'h14; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_20_T_1 = _ll_normalizedCounterMaxAdjusted_20_T ? ll_ncountSumStill2Dist_20 : {31'h0, ll_normalizedCounter_20}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_20 = _T_3 ? _ll_normalizedCounterMaxAdjusted_20_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_85 = {{32{_ll_ncountSumStill2Dist_T_84[15]}}, _ll_ncountSumStill2Dist_T_84} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_86 = _ll_ncountSumStill2Dist_T_85[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_87 = _ll_ncountSumStill2Dist_T_86; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_21 = _ll_ncountSumStill2Dist_T_87; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_21_T = ll_normalizedCounterMaxIdx == 16'h15; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_21_T_1 = _ll_normalizedCounterMaxAdjusted_21_T ? ll_ncountSumStill2Dist_21 : {31'h0, ll_normalizedCounter_21}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_21 = _T_3 ? _ll_normalizedCounterMaxAdjusted_21_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_89 = {{32{_ll_ncountSumStill2Dist_T_88[15]}}, _ll_ncountSumStill2Dist_T_88} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_90 = _ll_ncountSumStill2Dist_T_89[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_91 = _ll_ncountSumStill2Dist_T_90; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_22 = _ll_ncountSumStill2Dist_T_91; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_22_T = ll_normalizedCounterMaxIdx == 16'h16; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_22_T_1 = _ll_normalizedCounterMaxAdjusted_22_T ? ll_ncountSumStill2Dist_22 : {31'h0, ll_normalizedCounter_22}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_22 = _T_3 ? _ll_normalizedCounterMaxAdjusted_22_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_93 = {{32{_ll_ncountSumStill2Dist_T_92[15]}}, _ll_ncountSumStill2Dist_T_92} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_94 = _ll_ncountSumStill2Dist_T_93[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_95 = _ll_ncountSumStill2Dist_T_94; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_23 = _ll_ncountSumStill2Dist_T_95; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_23_T = ll_normalizedCounterMaxIdx == 16'h17; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_23_T_1 = _ll_normalizedCounterMaxAdjusted_23_T ? ll_ncountSumStill2Dist_23 : {31'h0, ll_normalizedCounter_23}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_23 = _T_3 ? _ll_normalizedCounterMaxAdjusted_23_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_97 = {{32{_ll_ncountSumStill2Dist_T_96[15]}}, _ll_ncountSumStill2Dist_T_96} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_98 = _ll_ncountSumStill2Dist_T_97[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_99 = _ll_ncountSumStill2Dist_T_98; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_24 = _ll_ncountSumStill2Dist_T_99; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_24_T = ll_normalizedCounterMaxIdx == 16'h18; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_24_T_1 = _ll_normalizedCounterMaxAdjusted_24_T ? ll_ncountSumStill2Dist_24 : {31'h0, ll_normalizedCounter_24}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_24 = _T_3 ? _ll_normalizedCounterMaxAdjusted_24_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_101 = {{32{_ll_ncountSumStill2Dist_T_100[15]}}, _ll_ncountSumStill2Dist_T_100} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_102 = _ll_ncountSumStill2Dist_T_101[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_103 = _ll_ncountSumStill2Dist_T_102; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_25 = _ll_ncountSumStill2Dist_T_103; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_25_T = ll_normalizedCounterMaxIdx == 16'h19; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_25_T_1 = _ll_normalizedCounterMaxAdjusted_25_T ? ll_ncountSumStill2Dist_25 : {31'h0, ll_normalizedCounter_25}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_25 = _T_3 ? _ll_normalizedCounterMaxAdjusted_25_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_105 = {{32{_ll_ncountSumStill2Dist_T_104[15]}}, _ll_ncountSumStill2Dist_T_104} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_106 = _ll_ncountSumStill2Dist_T_105[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_107 = _ll_ncountSumStill2Dist_T_106; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_26 = _ll_ncountSumStill2Dist_T_107; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_26_T = ll_normalizedCounterMaxIdx == 16'h1A; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_26_T_1 = _ll_normalizedCounterMaxAdjusted_26_T ? ll_ncountSumStill2Dist_26 : {31'h0, ll_normalizedCounter_26}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_26 = _T_3 ? _ll_normalizedCounterMaxAdjusted_26_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_109 = {{32{_ll_ncountSumStill2Dist_T_108[15]}}, _ll_ncountSumStill2Dist_T_108} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_110 = _ll_ncountSumStill2Dist_T_109[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_111 = _ll_ncountSumStill2Dist_T_110; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_27 = _ll_ncountSumStill2Dist_T_111; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_27_T = ll_normalizedCounterMaxIdx == 16'h1B; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_27_T_1 = _ll_normalizedCounterMaxAdjusted_27_T ? ll_ncountSumStill2Dist_27 : {31'h0, ll_normalizedCounter_27}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_27 = _T_3 ? _ll_normalizedCounterMaxAdjusted_27_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_113 = {{32{_ll_ncountSumStill2Dist_T_112[15]}}, _ll_ncountSumStill2Dist_T_112} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_114 = _ll_ncountSumStill2Dist_T_113[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_115 = _ll_ncountSumStill2Dist_T_114; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_28 = _ll_ncountSumStill2Dist_T_115; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_28_T = ll_normalizedCounterMaxIdx == 16'h1C; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_28_T_1 = _ll_normalizedCounterMaxAdjusted_28_T ? ll_ncountSumStill2Dist_28 : {31'h0, ll_normalizedCounter_28}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_28 = _T_3 ? _ll_normalizedCounterMaxAdjusted_28_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_117 = {{32{_ll_ncountSumStill2Dist_T_116[15]}}, _ll_ncountSumStill2Dist_T_116} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_118 = _ll_ncountSumStill2Dist_T_117[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_119 = _ll_ncountSumStill2Dist_T_118; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_29 = _ll_ncountSumStill2Dist_T_119; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_29_T = ll_normalizedCounterMaxIdx == 16'h1D; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_29_T_1 = _ll_normalizedCounterMaxAdjusted_29_T ? ll_ncountSumStill2Dist_29 : {31'h0, ll_normalizedCounter_29}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_29 = _T_3 ? _ll_normalizedCounterMaxAdjusted_29_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_121 = {{32{_ll_ncountSumStill2Dist_T_120[15]}}, _ll_ncountSumStill2Dist_T_120} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_122 = _ll_ncountSumStill2Dist_T_121[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_123 = _ll_ncountSumStill2Dist_T_122; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_30 = _ll_ncountSumStill2Dist_T_123; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_30_T = ll_normalizedCounterMaxIdx == 16'h1E; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_30_T_1 = _ll_normalizedCounterMaxAdjusted_30_T ? ll_ncountSumStill2Dist_30 : {31'h0, ll_normalizedCounter_30}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_30 = _T_3 ? _ll_normalizedCounterMaxAdjusted_30_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_125 = {{32{_ll_ncountSumStill2Dist_T_124[15]}}, _ll_ncountSumStill2Dist_T_124} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_126 = _ll_ncountSumStill2Dist_T_125[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_127 = _ll_ncountSumStill2Dist_T_126; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_31 = _ll_ncountSumStill2Dist_T_127; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_31_T = ll_normalizedCounterMaxIdx == 16'h1F; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_31_T_1 = _ll_normalizedCounterMaxAdjusted_31_T ? ll_ncountSumStill2Dist_31 : {31'h0, ll_normalizedCounter_31}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_31 = _T_3 ? _ll_normalizedCounterMaxAdjusted_31_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [15:0] ll_normalizedCounterReg_0; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_1; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_2; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_3; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_4; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_5; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_6; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_7; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_8; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_9; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_10; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_11; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_12; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_13; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_14; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_15; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_16; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_17; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_18; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_19; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_20; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_21; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_22; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_23; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_24; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_25; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_26; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_27; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_28; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_29; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_30; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_31; // @[FSECompressorDicBuilder.scala:337:40] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_43; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_86 = {1'h0, loginfo_cycles_43} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_87 = _loginfo_cycles_T_86[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_44; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_88 = {1'h0, loginfo_cycles_44} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_89 = _loginfo_cycles_T_88[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_45; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_90 = {1'h0, loginfo_cycles_45} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_91 = _loginfo_cycles_T_90[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_46; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_92 = {1'h0, loginfo_cycles_46} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_93 = _loginfo_cycles_T_92[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_47; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_94 = {1'h0, loginfo_cycles_47} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_95 = _loginfo_cycles_T_94[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_48; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_96 = {1'h0, loginfo_cycles_48} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_97 = _loginfo_cycles_T_96[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_49; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_98 = {1'h0, loginfo_cycles_49} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_99 = _loginfo_cycles_T_98[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_50; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_100 = {1'h0, loginfo_cycles_50} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_101 = _loginfo_cycles_T_100[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_51; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_102 = {1'h0, loginfo_cycles_51} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_103 = _loginfo_cycles_T_102[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_52; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_104 = {1'h0, loginfo_cycles_52} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_105 = _loginfo_cycles_T_104[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_53; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_106 = {1'h0, loginfo_cycles_53} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_107 = _loginfo_cycles_T_106[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_54; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_108 = {1'h0, loginfo_cycles_54} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_109 = _loginfo_cycles_T_108[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_55; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_110 = {1'h0, loginfo_cycles_55} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_111 = _loginfo_cycles_T_110[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_56; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_112 = {1'h0, loginfo_cycles_56} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_113 = _loginfo_cycles_T_112[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_57; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_114 = {1'h0, loginfo_cycles_57} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_115 = _loginfo_cycles_T_114[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_58; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_116 = {1'h0, loginfo_cycles_58} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_117 = _loginfo_cycles_T_116[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_59; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_118 = {1'h0, loginfo_cycles_59} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_119 = _loginfo_cycles_T_118[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_60; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_120 = {1'h0, loginfo_cycles_60} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_121 = _loginfo_cycles_T_120[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_61; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_122 = {1'h0, loginfo_cycles_61} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_123 = _loginfo_cycles_T_122[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_62; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_124 = {1'h0, loginfo_cycles_62} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_125 = _loginfo_cycles_T_124[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_63; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_126 = {1'h0, loginfo_cycles_63} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_127 = _loginfo_cycles_T_126[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_64; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_128 = {1'h0, loginfo_cycles_64} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_129 = _loginfo_cycles_T_128[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_65; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_130 = {1'h0, loginfo_cycles_65} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_131 = _loginfo_cycles_T_130[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_66; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_132 = {1'h0, loginfo_cycles_66} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_133 = _loginfo_cycles_T_132[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_67; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_134 = {1'h0, loginfo_cycles_67} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_135 = _loginfo_cycles_T_134[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_68; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_136 = {1'h0, loginfo_cycles_68} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_137 = _loginfo_cycles_T_136[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_69; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_138 = {1'h0, loginfo_cycles_69} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_139 = _loginfo_cycles_T_138[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_70; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_140 = {1'h0, loginfo_cycles_70} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_141 = _loginfo_cycles_T_140[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_71; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_142 = {1'h0, loginfo_cycles_71} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_143 = _loginfo_cycles_T_142[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_72; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_144 = {1'h0, loginfo_cycles_72} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_145 = _loginfo_cycles_T_144[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_73; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_146 = {1'h0, loginfo_cycles_73} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_147 = _loginfo_cycles_T_146[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_74; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_148 = {1'h0, loginfo_cycles_74} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_149 = _loginfo_cycles_T_148[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_75; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_150 = {1'h0, loginfo_cycles_75} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_151 = _loginfo_cycles_T_150[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_76; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_152 = {1'h0, loginfo_cycles_76} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_153 = _loginfo_cycles_T_152[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_77; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_154 = {1'h0, loginfo_cycles_77} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_155 = _loginfo_cycles_T_154[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_78; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_156 = {1'h0, loginfo_cycles_78} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_157 = _loginfo_cycles_T_156[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_79; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_158 = {1'h0, loginfo_cycles_79} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_159 = _loginfo_cycles_T_158[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_80; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_160 = {1'h0, loginfo_cycles_80} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_161 = _loginfo_cycles_T_160[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_81; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_162 = {1'h0, loginfo_cycles_81} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_163 = _loginfo_cycles_T_162[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_82; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_164 = {1'h0, loginfo_cycles_82} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_165 = _loginfo_cycles_T_164[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_83; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_166 = {1'h0, loginfo_cycles_83} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_167 = _loginfo_cycles_T_166[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_84; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_168 = {1'h0, loginfo_cycles_84} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_169 = _loginfo_cycles_T_168[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_85; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_170 = {1'h0, loginfo_cycles_85} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_171 = _loginfo_cycles_T_170[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_86; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_172 = {1'h0, loginfo_cycles_86} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_173 = _loginfo_cycles_T_172[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_87; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_174 = {1'h0, loginfo_cycles_87} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_175 = _loginfo_cycles_T_174[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_88; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_176 = {1'h0, loginfo_cycles_88} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_177 = _loginfo_cycles_T_176[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_89; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_178 = {1'h0, loginfo_cycles_89} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_179 = _loginfo_cycles_T_178[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_90; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_180 = {1'h0, loginfo_cycles_90} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_181 = _loginfo_cycles_T_180[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_91; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_182 = {1'h0, loginfo_cycles_91} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_183 = _loginfo_cycles_T_182[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_92; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_184 = {1'h0, loginfo_cycles_92} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_185 = _loginfo_cycles_T_184[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_93; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_186 = {1'h0, loginfo_cycles_93} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_187 = _loginfo_cycles_T_186[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_94; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_188 = {1'h0, loginfo_cycles_94} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_189 = _loginfo_cycles_T_188[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_95; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_190 = {1'h0, loginfo_cycles_95} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_191 = _loginfo_cycles_T_190[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_96; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_192 = {1'h0, loginfo_cycles_96} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_193 = _loginfo_cycles_T_192[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_97; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_194 = {1'h0, loginfo_cycles_97} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_195 = _loginfo_cycles_T_194[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_98; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_196 = {1'h0, loginfo_cycles_98} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_197 = _loginfo_cycles_T_196[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_99; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_198 = {1'h0, loginfo_cycles_99} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_199 = _loginfo_cycles_T_198[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_100; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_200 = {1'h0, loginfo_cycles_100} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_201 = _loginfo_cycles_T_200[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_101; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_202 = {1'h0, loginfo_cycles_101} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_203 = _loginfo_cycles_T_202[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_102; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_204 = {1'h0, loginfo_cycles_102} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_205 = _loginfo_cycles_T_204[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_103; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_206 = {1'h0, loginfo_cycles_103} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_207 = _loginfo_cycles_T_206[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_104; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_208 = {1'h0, loginfo_cycles_104} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_209 = _loginfo_cycles_T_208[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_105; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_210 = {1'h0, loginfo_cycles_105} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_211 = _loginfo_cycles_T_210[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_106; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_212 = {1'h0, loginfo_cycles_106} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_213 = _loginfo_cycles_T_212[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_107; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_214 = {1'h0, loginfo_cycles_107} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_215 = _loginfo_cycles_T_214[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_108; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_216 = {1'h0, loginfo_cycles_108} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_217 = _loginfo_cycles_T_216[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_109; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_218 = {1'h0, loginfo_cycles_109} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_219 = _loginfo_cycles_T_218[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_110; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_220 = {1'h0, loginfo_cycles_110} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_221 = _loginfo_cycles_T_220[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_111; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_222 = {1'h0, loginfo_cycles_111} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_223 = _loginfo_cycles_T_222[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_112; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_224 = {1'h0, loginfo_cycles_112} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_225 = _loginfo_cycles_T_224[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_113; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_226 = {1'h0, loginfo_cycles_113} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_227 = _loginfo_cycles_T_226[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_114; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_228 = {1'h0, loginfo_cycles_114} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_229 = _loginfo_cycles_T_228[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_115; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_230 = {1'h0, loginfo_cycles_115} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_231 = _loginfo_cycles_T_230[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_116; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_232 = {1'h0, loginfo_cycles_116} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_233 = _loginfo_cycles_T_232[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_117; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_234 = {1'h0, loginfo_cycles_117} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_235 = _loginfo_cycles_T_234[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_118; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_236 = {1'h0, loginfo_cycles_118} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_237 = _loginfo_cycles_T_236[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_119; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_238 = {1'h0, loginfo_cycles_119} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_239 = _loginfo_cycles_T_238[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_120; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_240 = {1'h0, loginfo_cycles_120} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_241 = _loginfo_cycles_T_240[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_121; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_242 = {1'h0, loginfo_cycles_121} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_243 = _loginfo_cycles_T_242[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_122; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_244 = {1'h0, loginfo_cycles_122} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_245 = _loginfo_cycles_T_244[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_123; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_246 = {1'h0, loginfo_cycles_123} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_247 = _loginfo_cycles_T_246[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_124; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_248 = {1'h0, loginfo_cycles_124} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_249 = _loginfo_cycles_T_248[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_125; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_250 = {1'h0, loginfo_cycles_125} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_251 = _loginfo_cycles_T_250[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_126; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_252 = {1'h0, loginfo_cycles_126} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_253 = _loginfo_cycles_T_252[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_127; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_254 = {1'h0, loginfo_cycles_127} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_255 = _loginfo_cycles_T_254[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_128; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_256 = {1'h0, loginfo_cycles_128} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_257 = _loginfo_cycles_T_256[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_129; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_258 = {1'h0, loginfo_cycles_129} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_259 = _loginfo_cycles_T_258[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_130; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_260 = {1'h0, loginfo_cycles_130} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_261 = _loginfo_cycles_T_260[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_131; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_262 = {1'h0, loginfo_cycles_131} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_263 = _loginfo_cycles_T_262[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_132; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_264 = {1'h0, loginfo_cycles_132} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_265 = _loginfo_cycles_T_264[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_133; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_266 = {1'h0, loginfo_cycles_133} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_267 = _loginfo_cycles_T_266[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_134; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_268 = {1'h0, loginfo_cycles_134} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_269 = _loginfo_cycles_T_268[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_135; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_270 = {1'h0, loginfo_cycles_135} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_271 = _loginfo_cycles_T_270[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_136; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_272 = {1'h0, loginfo_cycles_136} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_273 = _loginfo_cycles_T_272[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_137; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_274 = {1'h0, loginfo_cycles_137} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_275 = _loginfo_cycles_T_274[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_138; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_276 = {1'h0, loginfo_cycles_138} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_277 = _loginfo_cycles_T_276[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_139; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_278 = {1'h0, loginfo_cycles_139} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_279 = _loginfo_cycles_T_278[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_140; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_280 = {1'h0, loginfo_cycles_140} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_281 = _loginfo_cycles_T_280[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_141; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_282 = {1'h0, loginfo_cycles_141} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_283 = _loginfo_cycles_T_282[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_142; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_284 = {1'h0, loginfo_cycles_142} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_285 = _loginfo_cycles_T_284[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_143; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_286 = {1'h0, loginfo_cycles_143} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_287 = _loginfo_cycles_T_286[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_144; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_288 = {1'h0, loginfo_cycles_144} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_289 = _loginfo_cycles_T_288[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_145; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_290 = {1'h0, loginfo_cycles_145} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_291 = _loginfo_cycles_T_290[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_146; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_292 = {1'h0, loginfo_cycles_146} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_293 = _loginfo_cycles_T_292[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_147; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_294 = {1'h0, loginfo_cycles_147} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_295 = _loginfo_cycles_T_294[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_148; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_296 = {1'h0, loginfo_cycles_148} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_297 = _loginfo_cycles_T_296[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_149; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_298 = {1'h0, loginfo_cycles_149} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_299 = _loginfo_cycles_T_298[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_150; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_300 = {1'h0, loginfo_cycles_150} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_301 = _loginfo_cycles_T_300[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_151; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_302 = {1'h0, loginfo_cycles_151} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_303 = _loginfo_cycles_T_302[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_152; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_304 = {1'h0, loginfo_cycles_152} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_305 = _loginfo_cycles_T_304[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_153; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_306 = {1'h0, loginfo_cycles_153} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_307 = _loginfo_cycles_T_306[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_154; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_308 = {1'h0, loginfo_cycles_154} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_309 = _loginfo_cycles_T_308[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_155; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_310 = {1'h0, loginfo_cycles_155} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_311 = _loginfo_cycles_T_310[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_156; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_312 = {1'h0, loginfo_cycles_156} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_313 = _loginfo_cycles_T_312[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_157; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_314 = {1'h0, loginfo_cycles_157} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_315 = _loginfo_cycles_T_314[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_158; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_316 = {1'h0, loginfo_cycles_158} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_317 = _loginfo_cycles_T_316[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_159; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_318 = {1'h0, loginfo_cycles_159} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_319 = _loginfo_cycles_T_318[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_160; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_320 = {1'h0, loginfo_cycles_160} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_321 = _loginfo_cycles_T_320[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_161; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_322 = {1'h0, loginfo_cycles_161} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_323 = _loginfo_cycles_T_322[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_162; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_324 = {1'h0, loginfo_cycles_162} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_325 = _loginfo_cycles_T_324[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_163; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_326 = {1'h0, loginfo_cycles_163} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_327 = _loginfo_cycles_T_326[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_164; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_328 = {1'h0, loginfo_cycles_164} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_329 = _loginfo_cycles_T_328[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_165; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_330 = {1'h0, loginfo_cycles_165} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_331 = _loginfo_cycles_T_330[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_166; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_332 = {1'h0, loginfo_cycles_166} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_333 = _loginfo_cycles_T_332[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_167; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_334 = {1'h0, loginfo_cycles_167} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_335 = _loginfo_cycles_T_334[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_168; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_336 = {1'h0, loginfo_cycles_168} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_337 = _loginfo_cycles_T_336[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_169; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_338 = {1'h0, loginfo_cycles_169} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_339 = _loginfo_cycles_T_338[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_170; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_340 = {1'h0, loginfo_cycles_170} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_341 = _loginfo_cycles_T_340[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_171; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_342 = {1'h0, loginfo_cycles_171} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_343 = _loginfo_cycles_T_342[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_172; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_344 = {1'h0, loginfo_cycles_172} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_345 = _loginfo_cycles_T_344[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_173; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_346 = {1'h0, loginfo_cycles_173} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_347 = _loginfo_cycles_T_346[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_174; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_348 = {1'h0, loginfo_cycles_174} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_349 = _loginfo_cycles_T_348[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_175; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_350 = {1'h0, loginfo_cycles_175} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_351 = _loginfo_cycles_T_350[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_176; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_352 = {1'h0, loginfo_cycles_176} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_353 = _loginfo_cycles_T_352[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_177; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_354 = {1'h0, loginfo_cycles_177} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_355 = _loginfo_cycles_T_354[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_178; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_356 = {1'h0, loginfo_cycles_178} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_357 = _loginfo_cycles_T_356[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_179; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_358 = {1'h0, loginfo_cycles_179} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_359 = _loginfo_cycles_T_358[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_180; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_360 = {1'h0, loginfo_cycles_180} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_361 = _loginfo_cycles_T_360[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_181; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_362 = {1'h0, loginfo_cycles_181} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_363 = _loginfo_cycles_T_362[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_182; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_364 = {1'h0, loginfo_cycles_182} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_365 = _loginfo_cycles_T_364[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_183; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_366 = {1'h0, loginfo_cycles_183} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_367 = _loginfo_cycles_T_366[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_184; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_368 = {1'h0, loginfo_cycles_184} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_369 = _loginfo_cycles_T_368[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_185; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_370 = {1'h0, loginfo_cycles_185} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_371 = _loginfo_cycles_T_370[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_186; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_372 = {1'h0, loginfo_cycles_186} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_373 = _loginfo_cycles_T_372[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_187; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_374 = {1'h0, loginfo_cycles_187} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_375 = _loginfo_cycles_T_374[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_188; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_376 = {1'h0, loginfo_cycles_188} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_377 = _loginfo_cycles_T_376[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_189; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_378 = {1'h0, loginfo_cycles_189} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_379 = _loginfo_cycles_T_378[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_190; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_380 = {1'h0, loginfo_cycles_190} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_381 = _loginfo_cycles_T_380[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_191; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_382 = {1'h0, loginfo_cycles_191} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_383 = _loginfo_cycles_T_382[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_192; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_384 = {1'h0, loginfo_cycles_192} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_385 = _loginfo_cycles_T_384[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_193; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_386 = {1'h0, loginfo_cycles_193} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_387 = _loginfo_cycles_T_386[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_194; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_388 = {1'h0, loginfo_cycles_194} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_389 = _loginfo_cycles_T_388[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_195; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_390 = {1'h0, loginfo_cycles_195} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_391 = _loginfo_cycles_T_390[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_196; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_392 = {1'h0, loginfo_cycles_196} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_393 = _loginfo_cycles_T_392[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_197; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_394 = {1'h0, loginfo_cycles_197} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_395 = _loginfo_cycles_T_394[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_198; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_396 = {1'h0, loginfo_cycles_198} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_397 = _loginfo_cycles_T_396[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_199; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_398 = {1'h0, loginfo_cycles_199} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_399 = _loginfo_cycles_T_398[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_200; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_400 = {1'h0, loginfo_cycles_200} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_401 = _loginfo_cycles_T_400[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_201; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_402 = {1'h0, loginfo_cycles_201} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_403 = _loginfo_cycles_T_402[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_202; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_404 = {1'h0, loginfo_cycles_202} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_405 = _loginfo_cycles_T_404[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_203; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_406 = {1'h0, loginfo_cycles_203} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_407 = _loginfo_cycles_T_406[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_204; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_408 = {1'h0, loginfo_cycles_204} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_409 = _loginfo_cycles_T_408[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_205; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_410 = {1'h0, loginfo_cycles_205} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_411 = _loginfo_cycles_T_410[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_206; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_412 = {1'h0, loginfo_cycles_206} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_413 = _loginfo_cycles_T_412[63:0]; // @[Util.scala:19:38] wire [32:0] _GEN_197 = {1'h0, ll_max_symbol_value} + 33'h1; // @[FSECompressorDicBuilder.scala:170:36, :379:39] wire [32:0] _ll_maxSV1_T; // @[FSECompressorDicBuilder.scala:379:39] assign _ll_maxSV1_T = _GEN_197; // @[FSECompressorDicBuilder.scala:379:39] wire [32:0] _alphabetSize_T; // @[FSECompressorDicBuilder.scala:466:42] assign _alphabetSize_T = _GEN_197; // @[FSECompressorDicBuilder.scala:379:39, :466:42] wire [31:0] ll_maxSV1 = _ll_maxSV1_T[31:0]; // @[FSECompressorDicBuilder.scala:379:39] wire [15:0] ll_cumul_0; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_1; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_2; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_3; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_4; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_5; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_6; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_7; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_8; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_9; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_10; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_11; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_12; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_13; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_14; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_15; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_16; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_17; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_18; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_19; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_20; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_21; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_22; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_23; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_24; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_25; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_26; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_27; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_28; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_29; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_30; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_31; // @[FSECompressorDicBuilder.scala:382:26] reg [7:0] ll_tableSymbol_0; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_1; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_2; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_3; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_4; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_5; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_6; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_7; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_8; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_9; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_10; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_11; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_12; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_13; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_14; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_15; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_16; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_17; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_18; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_19; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_20; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_21; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_22; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_23; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_24; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_25; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_26; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_27; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_28; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_29; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_30; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_31; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_32; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_33; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_34; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_35; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_36; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_37; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_38; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_39; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_40; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_41; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_42; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_43; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_44; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_45; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_46; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_47; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_48; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_49; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_50; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_51; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_52; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_53; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_54; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_55; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_56; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_57; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_58; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_59; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_60; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_61; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_62; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_63; // @[FSECompressorDicBuilder.scala:383:31] wire [7:0] ll_normCountEqsNegOne_0; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_1; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_2; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_3; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_4; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_5; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_6; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_7; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_8; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_9; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_10; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_11; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_12; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_13; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_14; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_15; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_16; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_17; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_18; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_19; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_20; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_21; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_22; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_23; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_24; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_25; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_26; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_27; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_28; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_29; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_30; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOneCumul_0; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_1; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_2; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_3; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_4; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_5; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_6; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_7; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_8; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_9; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_10; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_11; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_12; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_13; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_14; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_15; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_16; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_17; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_18; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_19; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_20; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_21; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_22; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_23; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_24; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_25; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_26; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_27; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_28; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_29; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_30; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_31; // @[FSECompressorDicBuilder.scala:389:44] wire [8:0] _GEN_198 = {1'h0, ll_normCountEqsNegOne_1}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [8:0] _ll_normCountEqsNegOneSum_T = {1'h0, ll_normCountEqsNegOne_0} + _GEN_198; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [9:0] _ll_normCountEqsNegOneSum_T_1 = {1'h0, _ll_normCountEqsNegOneSum_T} + {2'h0, ll_normCountEqsNegOne_2}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [10:0] _ll_normCountEqsNegOneSum_T_2 = {1'h0, _ll_normCountEqsNegOneSum_T_1} + {3'h0, ll_normCountEqsNegOne_3}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [11:0] _ll_normCountEqsNegOneSum_T_3 = {1'h0, _ll_normCountEqsNegOneSum_T_2} + {4'h0, ll_normCountEqsNegOne_4}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [12:0] _ll_normCountEqsNegOneSum_T_4 = {1'h0, _ll_normCountEqsNegOneSum_T_3} + {5'h0, ll_normCountEqsNegOne_5}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [13:0] _ll_normCountEqsNegOneSum_T_5 = {1'h0, _ll_normCountEqsNegOneSum_T_4} + {6'h0, ll_normCountEqsNegOne_6}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [14:0] _ll_normCountEqsNegOneSum_T_6 = {1'h0, _ll_normCountEqsNegOneSum_T_5} + {7'h0, ll_normCountEqsNegOne_7}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [15:0] _ll_normCountEqsNegOneSum_T_7 = {1'h0, _ll_normCountEqsNegOneSum_T_6} + {8'h0, ll_normCountEqsNegOne_8}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [16:0] _ll_normCountEqsNegOneSum_T_8 = {1'h0, _ll_normCountEqsNegOneSum_T_7} + {9'h0, ll_normCountEqsNegOne_9}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [17:0] _ll_normCountEqsNegOneSum_T_9 = {1'h0, _ll_normCountEqsNegOneSum_T_8} + {10'h0, ll_normCountEqsNegOne_10}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [18:0] _ll_normCountEqsNegOneSum_T_10 = {1'h0, _ll_normCountEqsNegOneSum_T_9} + {11'h0, ll_normCountEqsNegOne_11}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [19:0] _ll_normCountEqsNegOneSum_T_11 = {1'h0, _ll_normCountEqsNegOneSum_T_10} + {12'h0, ll_normCountEqsNegOne_12}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [20:0] _ll_normCountEqsNegOneSum_T_12 = {1'h0, _ll_normCountEqsNegOneSum_T_11} + {13'h0, ll_normCountEqsNegOne_13}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [21:0] _ll_normCountEqsNegOneSum_T_13 = {1'h0, _ll_normCountEqsNegOneSum_T_12} + {14'h0, ll_normCountEqsNegOne_14}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [22:0] _ll_normCountEqsNegOneSum_T_14 = {1'h0, _ll_normCountEqsNegOneSum_T_13} + {15'h0, ll_normCountEqsNegOne_15}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [23:0] _ll_normCountEqsNegOneSum_T_15 = {1'h0, _ll_normCountEqsNegOneSum_T_14} + {16'h0, ll_normCountEqsNegOne_16}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [24:0] _ll_normCountEqsNegOneSum_T_16 = {1'h0, _ll_normCountEqsNegOneSum_T_15} + {17'h0, ll_normCountEqsNegOne_17}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [25:0] _ll_normCountEqsNegOneSum_T_17 = {1'h0, _ll_normCountEqsNegOneSum_T_16} + {18'h0, ll_normCountEqsNegOne_18}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [26:0] _ll_normCountEqsNegOneSum_T_18 = {1'h0, _ll_normCountEqsNegOneSum_T_17} + {19'h0, ll_normCountEqsNegOne_19}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [27:0] _ll_normCountEqsNegOneSum_T_19 = {1'h0, _ll_normCountEqsNegOneSum_T_18} + {20'h0, ll_normCountEqsNegOne_20}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [28:0] _ll_normCountEqsNegOneSum_T_20 = {1'h0, _ll_normCountEqsNegOneSum_T_19} + {21'h0, ll_normCountEqsNegOne_21}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [29:0] _ll_normCountEqsNegOneSum_T_21 = {1'h0, _ll_normCountEqsNegOneSum_T_20} + {22'h0, ll_normCountEqsNegOne_22}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [30:0] _ll_normCountEqsNegOneSum_T_22 = {1'h0, _ll_normCountEqsNegOneSum_T_21} + {23'h0, ll_normCountEqsNegOne_23}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [31:0] _ll_normCountEqsNegOneSum_T_23 = {1'h0, _ll_normCountEqsNegOneSum_T_22} + {24'h0, ll_normCountEqsNegOne_24}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [32:0] _ll_normCountEqsNegOneSum_T_24 = {1'h0, _ll_normCountEqsNegOneSum_T_23} + {25'h0, ll_normCountEqsNegOne_25}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [33:0] _ll_normCountEqsNegOneSum_T_25 = {1'h0, _ll_normCountEqsNegOneSum_T_24} + {26'h0, ll_normCountEqsNegOne_26}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [34:0] _ll_normCountEqsNegOneSum_T_26 = {1'h0, _ll_normCountEqsNegOneSum_T_25} + {27'h0, ll_normCountEqsNegOne_27}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [35:0] _ll_normCountEqsNegOneSum_T_27 = {1'h0, _ll_normCountEqsNegOneSum_T_26} + {28'h0, ll_normCountEqsNegOne_28}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [36:0] _ll_normCountEqsNegOneSum_T_28 = {1'h0, _ll_normCountEqsNegOneSum_T_27} + {29'h0, ll_normCountEqsNegOne_29}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [37:0] _ll_normCountEqsNegOneSum_T_29 = {1'h0, _ll_normCountEqsNegOneSum_T_28} + {30'h0, ll_normCountEqsNegOne_30}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [38:0] ll_normCountEqsNegOneSum = {1'h0, _ll_normCountEqsNegOneSum_T_29}; // @[FSECompressorDicBuilder.scala:390:65] reg [31:0] ll_highThresholdAfterCumul; // @[FSECompressorDicBuilder.scala:392:43] reg [15:0] ll_cumulReg_0; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_1; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_2; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_3; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_4; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_5; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_6; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_7; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_8; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_9; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_10; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_11; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_12; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_13; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_14; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_15; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_16; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_17; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_18; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_19; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_20; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_21; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_22; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_23; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_24; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_25; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_26; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_27; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_28; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_29; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_30; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_31; // @[FSECompressorDicBuilder.scala:394:28] reg [7:0] ll_spread_0; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_1; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_2; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_3; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_4; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_5; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_6; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_7; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_8; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_9; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_10; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_11; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_12; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_13; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_14; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_15; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_16; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_17; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_18; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_19; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_20; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_21; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_22; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_23; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_24; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_25; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_26; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_27; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_28; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_29; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_30; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_31; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_32; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_33; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_34; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_35; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_36; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_37; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_38; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_39; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_40; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_41; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_42; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_43; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_44; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_45; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_46; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_47; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_48; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_49; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_50; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_51; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_52; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_53; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_54; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_55; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_56; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_57; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_58; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_59; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_60; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_61; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_62; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_63; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_64; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_65; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_66; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_67; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_68; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_69; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_70; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_71; // @[FSECompressorDicBuilder.scala:400:26] reg [63:0] ll_pos; // @[FSECompressorDicBuilder.scala:402:23] reg [63:0] ll_s; // @[FSECompressorDicBuilder.scala:403:21] reg [63:0] ll_sv; // @[FSECompressorDicBuilder.scala:404:22] reg [15:0] ll_tableU16_0; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_1; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_2; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_3; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_4; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_5; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_6; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_7; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_8; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_9; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_10; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_11; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_12; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_13; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_14; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_15; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_16; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_17; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_18; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_19; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_20; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_21; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_22; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_23; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_24; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_25; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_26; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_27; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_28; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_29; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_30; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_31; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_32; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_33; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_34; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_35; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_36; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_37; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_38; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_39; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_40; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_41; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_42; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_43; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_44; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_45; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_46; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_47; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_48; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_49; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_50; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_51; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_52; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_53; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_54; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_55; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_56; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_57; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_58; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_59; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_60; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_61; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_62; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_63; // @[FSECompressorDicBuilder.scala:411:28] reg [31:0] ll_symbolTTDeltaNbBits_0; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_1; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_2; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_3; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_4; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_5; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_6; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_7; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_8; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_9; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_10; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_11; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_12; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_13; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_14; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_15; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_16; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_17; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_18; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_19; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_20; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_21; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_22; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_23; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_24; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_25; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_26; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_27; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_28; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_29; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_30; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_31; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaFindState_0; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_1; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_2; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_3; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_4; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_5; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_6; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_7; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_8; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_9; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_10; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_11; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_12; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_13; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_14; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_15; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_16; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_17; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_18; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_19; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_20; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_21; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_22; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_23; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_24; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_25; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_26; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_27; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_28; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_29; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_30; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_31; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_total; // @[FSECompressorDicBuilder.scala:414:25] wire [31:0] normCount; // @[FSECompressorDicBuilder.scala:415:23] wire [4:0] _normCount_T = ll_s[4:0]; // @[FSECompressorDicBuilder.scala:403:21] wire [4:0] _n_T = ll_s[4:0]; // @[FSECompressorDicBuilder.scala:403:21] wire [31:0][15:0] _GEN_199 = {{ll_normalizedCounterReg_31}, {ll_normalizedCounterReg_30}, {ll_normalizedCounterReg_29}, {ll_normalizedCounterReg_28}, {ll_normalizedCounterReg_27}, {ll_normalizedCounterReg_26}, {ll_normalizedCounterReg_25}, {ll_normalizedCounterReg_24}, {ll_normalizedCounterReg_23}, {ll_normalizedCounterReg_22}, {ll_normalizedCounterReg_21}, {ll_normalizedCounterReg_20}, {ll_normalizedCounterReg_19}, {ll_normalizedCounterReg_18}, {ll_normalizedCounterReg_17}, {ll_normalizedCounterReg_16}, {ll_normalizedCounterReg_15}, {ll_normalizedCounterReg_14}, {ll_normalizedCounterReg_13}, {ll_normalizedCounterReg_12}, {ll_normalizedCounterReg_11}, {ll_normalizedCounterReg_10}, {ll_normalizedCounterReg_9}, {ll_normalizedCounterReg_8}, {ll_normalizedCounterReg_7}, {ll_normalizedCounterReg_6}, {ll_normalizedCounterReg_5}, {ll_normalizedCounterReg_4}, {ll_normalizedCounterReg_3}, {ll_normalizedCounterReg_2}, {ll_normalizedCounterReg_1}, {ll_normalizedCounterReg_0}}; // @[FSECompressorDicBuilder.scala:337:40, :416:13] assign normCount = {16'h0, _GEN_199[_normCount_T]}; // @[FSECompressorDicBuilder.scala:415:23, :416:13] wire _symbolTT_lookup_fire_and_last_vec_0_T_2; // @[FSECompressorDicBuilder.scala:441:71] wire symbolTT_lookup_fire_and_last_vec_0; // @[FSECompressorDicBuilder.scala:422:51] wire _T_2517 = dicBuilderState == 4'h8; // @[FSECompressorDicBuilder.scala:156:32, :429:23] assign _io_new_state_0_valid_T = _T_2517; // @[FSECompressorDicBuilder.scala:429:23, :438:47] wire _io_ll_table_log_valid_T_1; // @[FSECompressorDicBuilder.scala:453:68] assign _io_ll_table_log_valid_T_1 = _T_2517; // @[FSECompressorDicBuilder.scala:429:23, :453:68] assign _io_symbol_info_0_ready_T = io_symbolTT_info_0_ready_0 & _T_2517; // @[Misc.scala:26:53] assign io_symbol_info_0_ready_0 = _io_symbol_info_0_ready_T; // @[Misc.scala:26:53] assign _io_symbolTT_info_0_valid_T = io_symbol_info_0_valid_0 & _T_2517; // @[Misc.scala:26:53] assign io_symbolTT_info_0_valid_0 = _io_symbolTT_info_0_valid_T; // @[Misc.scala:26:53] wire [4:0] _io_symbolTT_info_0_bits_nbbit_T = io_symbol_info_0_bits_symbol_0[4:0]; // @[FSECompressorDicBuilder.scala:39:7] wire [4:0] _io_symbolTT_info_0_bits_findstate_T = io_symbol_info_0_bits_symbol_0[4:0]; // @[FSECompressorDicBuilder.scala:39:7] wire [31:0][31:0] _GEN_200 = {{ll_symbolTTDeltaNbBits_31}, {ll_symbolTTDeltaNbBits_30}, {ll_symbolTTDeltaNbBits_29}, {ll_symbolTTDeltaNbBits_28}, {ll_symbolTTDeltaNbBits_27}, {ll_symbolTTDeltaNbBits_26}, {ll_symbolTTDeltaNbBits_25}, {ll_symbolTTDeltaNbBits_24}, {ll_symbolTTDeltaNbBits_23}, {ll_symbolTTDeltaNbBits_22}, {ll_symbolTTDeltaNbBits_21}, {ll_symbolTTDeltaNbBits_20}, {ll_symbolTTDeltaNbBits_19}, {ll_symbolTTDeltaNbBits_18}, {ll_symbolTTDeltaNbBits_17}, {ll_symbolTTDeltaNbBits_16}, {ll_symbolTTDeltaNbBits_15}, {ll_symbolTTDeltaNbBits_14}, {ll_symbolTTDeltaNbBits_13}, {ll_symbolTTDeltaNbBits_12}, {ll_symbolTTDeltaNbBits_11}, {ll_symbolTTDeltaNbBits_10}, {ll_symbolTTDeltaNbBits_9}, {ll_symbolTTDeltaNbBits_8}, {ll_symbolTTDeltaNbBits_7}, {ll_symbolTTDeltaNbBits_6}, {ll_symbolTTDeltaNbBits_5}, {ll_symbolTTDeltaNbBits_4}, {ll_symbolTTDeltaNbBits_3}, {ll_symbolTTDeltaNbBits_2}, {ll_symbolTTDeltaNbBits_1}, {ll_symbolTTDeltaNbBits_0}}; // @[FSECompressorDicBuilder.scala:412:39, :434:36] assign io_symbolTT_info_0_bits_nbbit_0 = _GEN_200[_io_symbolTT_info_0_bits_nbbit_T]; // @[FSECompressorDicBuilder.scala:39:7, :434:36] wire [31:0][31:0] _GEN_201 = {{ll_symbolTTDeltaFindState_31}, {ll_symbolTTDeltaFindState_30}, {ll_symbolTTDeltaFindState_29}, {ll_symbolTTDeltaFindState_28}, {ll_symbolTTDeltaFindState_27}, {ll_symbolTTDeltaFindState_26}, {ll_symbolTTDeltaFindState_25}, {ll_symbolTTDeltaFindState_24}, {ll_symbolTTDeltaFindState_23}, {ll_symbolTTDeltaFindState_22}, {ll_symbolTTDeltaFindState_21}, {ll_symbolTTDeltaFindState_20}, {ll_symbolTTDeltaFindState_19}, {ll_symbolTTDeltaFindState_18}, {ll_symbolTTDeltaFindState_17}, {ll_symbolTTDeltaFindState_16}, {ll_symbolTTDeltaFindState_15}, {ll_symbolTTDeltaFindState_14}, {ll_symbolTTDeltaFindState_13}, {ll_symbolTTDeltaFindState_12}, {ll_symbolTTDeltaFindState_11}, {ll_symbolTTDeltaFindState_10}, {ll_symbolTTDeltaFindState_9}, {ll_symbolTTDeltaFindState_8}, {ll_symbolTTDeltaFindState_7}, {ll_symbolTTDeltaFindState_6}, {ll_symbolTTDeltaFindState_5}, {ll_symbolTTDeltaFindState_4}, {ll_symbolTTDeltaFindState_3}, {ll_symbolTTDeltaFindState_2}, {ll_symbolTTDeltaFindState_1}, {ll_symbolTTDeltaFindState_0}}; // @[FSECompressorDicBuilder.scala:413:42, :435:81] assign _io_symbolTT_info_0_bits_findstate_T_1 = _GEN_201[_io_symbolTT_info_0_bits_findstate_T]; // @[FSECompressorDicBuilder.scala:435:81] assign io_symbolTT_info_0_bits_findstate_0 = _io_symbolTT_info_0_bits_findstate_T_1; // @[FSECompressorDicBuilder.scala:39:7, :435:81] assign io_new_state_0_valid_0 = _io_new_state_0_valid_T; // @[FSECompressorDicBuilder.scala:39:7, :438:47] wire [5:0] _io_new_state_0_bits_T = io_state_table_idx_0_0[5:0]; // @[FSECompressorDicBuilder.scala:39:7] wire [63:0][15:0] _GEN_202 = {{ll_tableU16_63}, {ll_tableU16_62}, {ll_tableU16_61}, {ll_tableU16_60}, {ll_tableU16_59}, {ll_tableU16_58}, {ll_tableU16_57}, {ll_tableU16_56}, {ll_tableU16_55}, {ll_tableU16_54}, {ll_tableU16_53}, {ll_tableU16_52}, {ll_tableU16_51}, {ll_tableU16_50}, {ll_tableU16_49}, {ll_tableU16_48}, {ll_tableU16_47}, {ll_tableU16_46}, {ll_tableU16_45}, {ll_tableU16_44}, {ll_tableU16_43}, {ll_tableU16_42}, {ll_tableU16_41}, {ll_tableU16_40}, {ll_tableU16_39}, {ll_tableU16_38}, {ll_tableU16_37}, {ll_tableU16_36}, {ll_tableU16_35}, {ll_tableU16_34}, {ll_tableU16_33}, {ll_tableU16_32}, {ll_tableU16_31}, {ll_tableU16_30}, {ll_tableU16_29}, {ll_tableU16_28}, {ll_tableU16_27}, {ll_tableU16_26}, {ll_tableU16_25}, {ll_tableU16_24}, {ll_tableU16_23}, {ll_tableU16_22}, {ll_tableU16_21}, {ll_tableU16_20}, {ll_tableU16_19}, {ll_tableU16_18}, {ll_tableU16_17}, {ll_tableU16_16}, {ll_tableU16_15}, {ll_tableU16_14}, {ll_tableU16_13}, {ll_tableU16_12}, {ll_tableU16_11}, {ll_tableU16_10}, {ll_tableU16_9}, {ll_tableU16_8}, {ll_tableU16_7}, {ll_tableU16_6}, {ll_tableU16_5}, {ll_tableU16_4}, {ll_tableU16_3}, {ll_tableU16_2}, {ll_tableU16_1}, {ll_tableU16_0}}; // @[FSECompressorDicBuilder.scala:411:28, :439:26] assign io_new_state_0_bits_0 = _GEN_202[_io_new_state_0_bits_T]; // @[FSECompressorDicBuilder.scala:39:7, :439:26] wire _symbolTT_lookup_fire_and_last_vec_0_T = io_symbol_info_0_valid_0 & io_symbolTT_info_0_ready_0; // @[Misc.scala:29:18] wire _symbolTT_lookup_fire_and_last_vec_0_T_1 = _symbolTT_lookup_fire_and_last_vec_0_T & _T_2517; // @[Misc.scala:29:18] assign _symbolTT_lookup_fire_and_last_vec_0_T_2 = _symbolTT_lookup_fire_and_last_vec_0_T_1 & io_symbol_info_0_bits_last_symbol_0; // @[Misc.scala:29:18] assign symbolTT_lookup_fire_and_last_vec_0 = _symbolTT_lookup_fire_and_last_vec_0_T_2; // @[FSECompressorDicBuilder.scala:422:51, :441:71] wire _use_predefined_mode_T = io_nb_seq_bits_0 < 64'h15; // @[FSECompressorDicBuilder.scala:39:7, :449:45] wire use_predefined_mode = _use_predefined_mode_T \| fse_normalize_corner_case_reg; // @[FSECompressorDicBuilder.scala:314:46, :449:{45,87}] reg ll_table_log_fired; // @[FSECompressorDicBuilder.scala:451:35] wire [2:0] _io_ll_table_log_bits_T = use_predefined_mode ? 3'h5 : 3'h6; // @[FSECompressorDicBuilder.scala:449:87, :452:30] assign io_ll_table_log_bits_0 = {1'h0, _io_ll_table_log_bits_T}; // @[FSECompressorDicBuilder.scala:39:7, :452:{24,30}] wire _io_ll_table_log_valid_T = ~ll_table_log_fired; // @[FSECompressorDicBuilder.scala:451:35, :453:28] assign _io_ll_table_log_valid_T_2 = _io_ll_table_log_valid_T & _io_ll_table_log_valid_T_1; // @[FSECompressorDicBuilder.scala:453:{28,48,68}] assign io_ll_table_log_valid_0 = _io_ll_table_log_valid_T_2; // @[FSECompressorDicBuilder.scala:39:7, :453:48] reg print_table; // @[FSECompressorDicBuilder.scala:458:28] reg write_header_started; // @[FSECompressorDicBuilder.scala:461:37] reg [31:0] nbBits; // @[FSECompressorDicBuilder.scala:462:23] reg [31:0] remaining; // @[FSECompressorDicBuilder.scala:463:26] reg [31:0] threshold; // @[FSECompressorDicBuilder.scala:464:26] wire [31:0] shifted_thresholds_0 = threshold; // @[FSECompressorDicBuilder.scala:464:26, :484:36] reg [31:0] symbol; // @[FSECompressorDicBuilder.scala:465:23] wire [31:0] alphabetSize = _alphabetSize_T[31:0]; // @[FSECompressorDicBuilder.scala:466:42] reg previousIs0; // @[FSECompressorDicBuilder.scala:467:28] reg [63:0] bitStream; // @[FSECompressorDicBuilder.scala:468:26] reg [6:0] bitCount; // @[FSECompressorDicBuilder.scala:469:25] reg writeBitStream; // @[FSECompressorDicBuilder.scala:470:31] reg [31:0] start; // @[FSECompressorDicBuilder.scala:471:22] reg start_initialized; // @[FSECompressorDicBuilder.scala:472:34] reg skip_zeros_done; // @[FSECompressorDicBuilder.scala:473:32] reg skip_24_done; // @[FSECompressorDicBuilder.scala:474:29] reg skip_3_done; // @[FSECompressorDicBuilder.scala:475:28] reg writeBitStreamPrev0; // @[FSECompressorDicBuilder.scala:476:36] wire [31:0] _shifted_thresholds_1_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] _shifted_thresholds_2_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] _shifted_thresholds_3_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] _shifted_thresholds_4_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] _shifted_thresholds_5_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] _shifted_thresholds_6_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] shifted_thresholds_1; // @[FSECompressorDicBuilder.scala:484:36] wire [31:0] shifted_thresholds_2; // @[FSECompressorDicBuilder.scala:484:36] wire [31:0] shifted_thresholds_3; // @[FSECompressorDicBuilder.scala:484:36] wire [31:0] shifted_thresholds_4; // @[FSECompressorDicBuilder.scala:484:36] wire [31:0] shifted_thresholds_5; // @[FSECompressorDicBuilder.scala:484:36] wire [31:0] shifted_thresholds_6; // @[FSECompressorDicBuilder.scala:484:36] assign _shifted_thresholds_1_T = {1'h0, shifted_thresholds_0[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_1 = _shifted_thresholds_1_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign _shifted_thresholds_2_T = {1'h0, shifted_thresholds_1[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_2 = _shifted_thresholds_2_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign _shifted_thresholds_3_T = {1'h0, shifted_thresholds_2[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_3 = _shifted_thresholds_3_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign _shifted_thresholds_4_T = {1'h0, shifted_thresholds_3[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_4 = _shifted_thresholds_4_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign _shifted_thresholds_5_T = {1'h0, shifted_thresholds_4[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_5 = _shifted_thresholds_5_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign _shifted_thresholds_6_T = {1'h0, shifted_thresholds_5[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_6 = _shifted_thresholds_6_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] wire [31:0] shifted_threshold_small_or_eq_remaining_0; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_1; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_2; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_3; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_4; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_5; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_6; // @[FSECompressorDicBuilder.scala:490:57] wire [32:0] _nxt_shifted_threshold_idx_T = {1'h0, shifted_threshold_small_or_eq_remaining_0} + {1'h0, shifted_threshold_small_or_eq_remaining_1}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] _nxt_shifted_threshold_idx_T_1 = _nxt_shifted_threshold_idx_T[31:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nxt_shifted_threshold_idx_T_2 = {1'h0, _nxt_shifted_threshold_idx_T_1} + {1'h0, shifted_threshold_small_or_eq_remaining_2}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] _nxt_shifted_threshold_idx_T_3 = _nxt_shifted_threshold_idx_T_2[31:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nxt_shifted_threshold_idx_T_4 = {1'h0, _nxt_shifted_threshold_idx_T_3} + {1'h0, shifted_threshold_small_or_eq_remaining_3}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] _nxt_shifted_threshold_idx_T_5 = _nxt_shifted_threshold_idx_T_4[31:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nxt_shifted_threshold_idx_T_6 = {1'h0, _nxt_shifted_threshold_idx_T_5} + {1'h0, shifted_threshold_small_or_eq_remaining_4}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] _nxt_shifted_threshold_idx_T_7 = _nxt_shifted_threshold_idx_T_6[31:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nxt_shifted_threshold_idx_T_8 = {1'h0, _nxt_shifted_threshold_idx_T_7} + {1'h0, shifted_threshold_small_or_eq_remaining_5}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] _nxt_shifted_threshold_idx_T_9 = _nxt_shifted_threshold_idx_T_8[31:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nxt_shifted_threshold_idx_T_10 = {1'h0, _nxt_shifted_threshold_idx_T_9} + {1'h0, shifted_threshold_small_or_eq_remaining_6}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] nxt_shifted_threshold_idx = _nxt_shifted_threshold_idx_T_10[31:0]; // @[FSECompressorDicBuilder.scala:491:84] assign io_ll_stream_output_ready_0 = (\|dicBuilderState) & _T_839 & _predefined_mode_q_io_enq_ready; // @[FSECompressorDicBuilder.scala:39:7, :137:29, :141:33, :156:32, :198:25, :551:28, :559:33] wire _io_ll_stream_user_consumed_bytes_T = io_ll_stream_available_output_bytes_0 < 6'h4; // @[FSECompressorDicBuilder.scala:39:7, :560:83] wire [5:0] _io_ll_stream_user_consumed_bytes_T_1 = _io_ll_stream_user_consumed_bytes_T ? io_ll_stream_available_output_bytes_0 : 6'h4; // @[FSECompressorDicBuilder.scala:39:7, :560:{46,83}] wire _GEN_203 = (\|dicBuilderState) & _T_839; // @[FSECompressorDicBuilder.scala:138:36, :156:32, :198:25, :551:28] assign io_ll_stream_user_consumed_bytes_0 = _GEN_203 ? _io_ll_stream_user_consumed_bytes_T_1 : 6'h0; // @[FSECompressorDicBuilder.scala:39:7, :138:36, :551:28, :560:46] wire [31:0] _ll_count_0_T_3 = _ll_count_0_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_1_T_3 = _ll_count_1_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_2_T_3 = _ll_count_2_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_3_T_3 = _ll_count_3_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_4_T_3 = _ll_count_4_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_5_T_3 = _ll_count_5_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_6_T_3 = _ll_count_6_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_7_T_3 = _ll_count_7_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_8_T_3 = _ll_count_8_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_9_T_3 = _ll_count_9_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_10_T_3 = _ll_count_10_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_11_T_3 = _ll_count_11_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_12_T_3 = _ll_count_12_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_13_T_3 = _ll_count_13_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_14_T_3 = _ll_count_14_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_15_T_3 = _ll_count_15_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_16_T_3 = _ll_count_16_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_17_T_3 = _ll_count_17_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_18_T_3 = _ll_count_18_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_19_T_3 = _ll_count_19_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_20_T_3 = _ll_count_20_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_21_T_3 = _ll_count_21_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_22_T_3 = _ll_count_22_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_23_T_3 = _ll_count_23_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_24_T_3 = _ll_count_24_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_25_T_3 = _ll_count_25_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_26_T_3 = _ll_count_26_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_27_T_3 = _ll_count_27_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_28_T_3 = _ll_count_28_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_29_T_3 = _ll_count_29_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_30_T_3 = _ll_count_30_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_31_T_3 = _ll_count_31_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_max_symbol_value_T_3 = _ll_max_symbol_value_T_2 ? ll_max_symbol_value : _GEN_32; // @[FSECompressorDicBuilder.scala:170:36, :204:54, :569:{35,56}] wire _T_843 = _predefined_mode_q_io_enq_ready & io_ll_stream_output_valid_0 & io_ll_stream_output_last_chunk_0 & io_ll_stream_user_consumed_bytes_0 == io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :141:33, :572:{44,73,107,144}] wire [6:0] _ll_last_codetable_T = {1'h0, io_ll_stream_user_consumed_bytes_0} - 7'h1; // @[FSECompressorDicBuilder.scala:39:7, :579:85] wire [5:0] _ll_last_codetable_T_1 = _ll_last_codetable_T[5:0]; // @[FSECompressorDicBuilder.scala:579:85] wire [1:0] _ll_last_codetable_T_2 = _ll_last_codetable_T_1[1:0]; // @[FSECompressorDicBuilder.scala:579:85] wire [3:0][7:0] _GEN_204 = {{input_ll_symbols_3}, {input_ll_symbols_2}, {input_ll_symbols_1}, {input_ll_symbols_0}}; // @[FSECompressorDicBuilder.scala:172:34] wire [4:0] _ll_count_last_codetable_T = _GEN_204[_ll_last_codetable_T_2][4:0]; wire [4:0] _ll_last_statcount_T = _GEN_204[_ll_last_codetable_T_2][4:0]; wire [31:0][31:0] _GEN_205 = {{ll_count_31}, {ll_count_30}, {ll_count_29}, {ll_count_28}, {ll_count_27}, {ll_count_26}, {ll_count_25}, {ll_count_24}, {ll_count_23}, {ll_count_22}, {ll_count_21}, {ll_count_20}, {ll_count_19}, {ll_count_18}, {ll_count_17}, {ll_count_16}, {ll_count_15}, {ll_count_14}, {ll_count_13}, {ll_count_12}, {ll_count_11}, {ll_count_10}, {ll_count_9}, {ll_count_8}, {ll_count_7}, {ll_count_6}, {ll_count_5}, {ll_count_4}, {ll_count_3}, {ll_count_2}, {ll_count_1}, {ll_count_0}}; // @[FSECompressorDicBuilder.scala:169:25, :583:55] wire [31:0][2:0] _GEN_206 = {{stat_sum_31}, {stat_sum_30}, {stat_sum_29}, {stat_sum_28}, {stat_sum_27}, {stat_sum_26}, {stat_sum_25}, {stat_sum_24}, {stat_sum_23}, {stat_sum_22}, {stat_sum_21}, {stat_sum_20}, {stat_sum_19}, {stat_sum_18}, {stat_sum_17}, {stat_sum_16}, {stat_sum_15}, {stat_sum_14}, {stat_sum_13}, {stat_sum_12}, {stat_sum_11}, {stat_sum_10}, {stat_sum_9}, {stat_sum_8}, {stat_sum_7}, {stat_sum_6}, {stat_sum_5}, {stat_sum_4}, {stat_sum_3}, {stat_sum_2}, {stat_sum_1}, {stat_sum_0}}; // @[FSECompressorDicBuilder.scala:186:26, :583:55] wire [32:0] _ll_last_count_T = {1'h0, _GEN_205[_ll_count_last_codetable_T]} + {30'h0, _GEN_206[_ll_last_statcount_T]}; // @[FSECompressorDicBuilder.scala:583:55] wire [31:0] ll_last_count = _ll_last_count_T[31:0]; // @[FSECompressorDicBuilder.scala:583:55] wire do_subtract = \|(ll_last_count[31:1]); // @[FSECompressorDicBuilder.scala:583:55, :584:43] wire [64:0] _ll_nbseq_1_T = {1'h0, io_nb_seq_bits_0} - 65'h1; // @[FSECompressorDicBuilder.scala:39:7, :585:57] wire [63:0] _ll_nbseq_1_T_1 = _ll_nbseq_1_T[63:0]; // @[FSECompressorDicBuilder.scala:585:57] wire [63:0] _ll_nbseq_1_T_2 = do_subtract ? _ll_nbseq_1_T_1 : io_nb_seq_bits_0; // @[FSECompressorDicBuilder.scala:39:7, :584:43, :585:{28,57}] wire _GEN_207 = _T_839 & _T_843; // @[FSECompressorDicBuilder.scala:198:25, :494:31, :551:28, :572:{44,73,107,186}, :585:22] wire [32:0] _ll_count_T = {1'h0, ll_last_count} - 33'h1; // @[FSECompressorDicBuilder.scala:583:55, :586:73] wire [31:0] _ll_count_T_1 = _ll_count_T[31:0]; // @[FSECompressorDicBuilder.scala:586:73] wire [31:0] _ll_count_T_2 = do_subtract ? _ll_count_T_1 : ll_last_count; // @[FSECompressorDicBuilder.scala:583:55, :584:43, :586:{45,73}] wire _GEN_208 = (\|dicBuilderState) & _GEN_207 & use_predefined_mode; // @[FSECompressorDicBuilder.scala:156:32, :316:80, :449:87, :494:31, :551:28, :572:186, :585:22, :591:37] reg [63:0] loginfo_cycles_207; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_414 = {1'h0, loginfo_cycles_207} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_415 = _loginfo_cycles_T_414[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_208; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_416 = {1'h0, loginfo_cycles_208} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_417 = _loginfo_cycles_T_416[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_209; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_418 = {1'h0, loginfo_cycles_209} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_419 = _loginfo_cycles_T_418[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_210; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_420 = {1'h0, loginfo_cycles_210} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_421 = _loginfo_cycles_T_420[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_211; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_422 = {1'h0, loginfo_cycles_211} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_423 = _loginfo_cycles_T_422[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_212; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_424 = {1'h0, loginfo_cycles_212} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_425 = _loginfo_cycles_T_424[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_213; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_426 = {1'h0, loginfo_cycles_213} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_427 = _loginfo_cycles_T_426[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_214; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_428 = {1'h0, loginfo_cycles_214} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_429 = _loginfo_cycles_T_428[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_215; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_430 = {1'h0, loginfo_cycles_215} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_431 = _loginfo_cycles_T_430[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_216; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_432 = {1'h0, loginfo_cycles_216} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_433 = _loginfo_cycles_T_432[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_217; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_434 = {1'h0, loginfo_cycles_217} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_435 = _loginfo_cycles_T_434[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_218; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_436 = {1'h0, loginfo_cycles_218} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_437 = _loginfo_cycles_T_436[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_219; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_438 = {1'h0, loginfo_cycles_219} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_439 = _loginfo_cycles_T_438[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_220; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_440 = {1'h0, loginfo_cycles_220} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_441 = _loginfo_cycles_T_440[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_221; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_442 = {1'h0, loginfo_cycles_221} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_443 = _loginfo_cycles_T_442[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_222; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_444 = {1'h0, loginfo_cycles_222} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_445 = _loginfo_cycles_T_444[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_223; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_446 = {1'h0, loginfo_cycles_223} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_447 = _loginfo_cycles_T_446[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_224; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_448 = {1'h0, loginfo_cycles_224} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_449 = _loginfo_cycles_T_448[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_225; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_450 = {1'h0, loginfo_cycles_225} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_451 = _loginfo_cycles_T_450[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_226; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_452 = {1'h0, loginfo_cycles_226} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_453 = _loginfo_cycles_T_452[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_227; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_454 = {1'h0, loginfo_cycles_227} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_455 = _loginfo_cycles_T_454[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_228; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_456 = {1'h0, loginfo_cycles_228} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_457 = _loginfo_cycles_T_456[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_229; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_458 = {1'h0, loginfo_cycles_229} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_459 = _loginfo_cycles_T_458[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_230; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_460 = {1'h0, loginfo_cycles_230} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_461 = _loginfo_cycles_T_460[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_231; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_462 = {1'h0, loginfo_cycles_231} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_463 = _loginfo_cycles_T_462[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_232; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_464 = {1'h0, loginfo_cycles_232} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_465 = _loginfo_cycles_T_464[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_233; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_466 = {1'h0, loginfo_cycles_233} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_467 = _loginfo_cycles_T_466[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_234; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_468 = {1'h0, loginfo_cycles_234} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_469 = _loginfo_cycles_T_468[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_235; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_470 = {1'h0, loginfo_cycles_235} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_471 = _loginfo_cycles_T_470[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_236; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_472 = {1'h0, loginfo_cycles_236} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_473 = _loginfo_cycles_T_472[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_237; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_474 = {1'h0, loginfo_cycles_237} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_475 = _loginfo_cycles_T_474[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_238; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_476 = {1'h0, loginfo_cycles_238} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_477 = _loginfo_cycles_T_476[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_239; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_478 = {1'h0, loginfo_cycles_239} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_479 = _loginfo_cycles_T_478[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_240; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_480 = {1'h0, loginfo_cycles_240} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_481 = _loginfo_cycles_T_480[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_241; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_482 = {1'h0, loginfo_cycles_241} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_483 = _loginfo_cycles_T_482[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_242; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_484 = {1'h0, loginfo_cycles_242} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_485 = _loginfo_cycles_T_484[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_243; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_486 = {1'h0, loginfo_cycles_243} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_487 = _loginfo_cycles_T_486[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_244; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_488 = {1'h0, loginfo_cycles_244} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_489 = _loginfo_cycles_T_488[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_245; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_490 = {1'h0, loginfo_cycles_245} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_491 = _loginfo_cycles_T_490[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_246; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_492 = {1'h0, loginfo_cycles_246} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_493 = _loginfo_cycles_T_492[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_247; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_494 = {1'h0, loginfo_cycles_247} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_495 = _loginfo_cycles_T_494[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_248; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_496 = {1'h0, loginfo_cycles_248} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_497 = _loginfo_cycles_T_496[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_249; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_498 = {1'h0, loginfo_cycles_249} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_499 = _loginfo_cycles_T_498[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_250; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_500 = {1'h0, loginfo_cycles_250} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_501 = _loginfo_cycles_T_500[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_251; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_502 = {1'h0, loginfo_cycles_251} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_503 = _loginfo_cycles_T_502[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_252; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_504 = {1'h0, loginfo_cycles_252} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_505 = _loginfo_cycles_T_504[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_253; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_506 = {1'h0, loginfo_cycles_253} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_507 = _loginfo_cycles_T_506[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_254; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_508 = {1'h0, loginfo_cycles_254} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_509 = _loginfo_cycles_T_508[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_255; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_510 = {1'h0, loginfo_cycles_255} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_511 = _loginfo_cycles_T_510[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_256; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_512 = {1'h0, loginfo_cycles_256} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_513 = _loginfo_cycles_T_512[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_257; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_514 = {1'h0, loginfo_cycles_257} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_515 = _loginfo_cycles_T_514[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_258; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_516 = {1'h0, loginfo_cycles_258} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_517 = _loginfo_cycles_T_516[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_259; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_518 = {1'h0, loginfo_cycles_259} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_519 = _loginfo_cycles_T_518[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_260; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_520 = {1'h0, loginfo_cycles_260} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_521 = _loginfo_cycles_T_520[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_261; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_522 = {1'h0, loginfo_cycles_261} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_523 = _loginfo_cycles_T_522[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_262; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_524 = {1'h0, loginfo_cycles_262} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_525 = _loginfo_cycles_T_524[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_263; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_526 = {1'h0, loginfo_cycles_263} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_527 = _loginfo_cycles_T_526[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_264; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_528 = {1'h0, loginfo_cycles_264} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_529 = _loginfo_cycles_T_528[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_265; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_530 = {1'h0, loginfo_cycles_265} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_531 = _loginfo_cycles_T_530[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_266; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_532 = {1'h0, loginfo_cycles_266} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_533 = _loginfo_cycles_T_532[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_267; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_534 = {1'h0, loginfo_cycles_267} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_535 = _loginfo_cycles_T_534[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_268; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_536 = {1'h0, loginfo_cycles_268} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_537 = _loginfo_cycles_T_536[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_269; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_538 = {1'h0, loginfo_cycles_269} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_539 = _loginfo_cycles_T_538[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_270; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_540 = {1'h0, loginfo_cycles_270} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_541 = _loginfo_cycles_T_540[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_271; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_542 = {1'h0, loginfo_cycles_271} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_543 = _loginfo_cycles_T_542[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_272; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_544 = {1'h0, loginfo_cycles_272} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_545 = _loginfo_cycles_T_544[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_273; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_546 = {1'h0, loginfo_cycles_273} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_547 = _loginfo_cycles_T_546[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_274; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_548 = {1'h0, loginfo_cycles_274} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_549 = _loginfo_cycles_T_548[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_275; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_550 = {1'h0, loginfo_cycles_275} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_551 = _loginfo_cycles_T_550[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_276; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_552 = {1'h0, loginfo_cycles_276} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_553 = _loginfo_cycles_T_552[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_277; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_554 = {1'h0, loginfo_cycles_277} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_555 = _loginfo_cycles_T_554[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_278; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_556 = {1'h0, loginfo_cycles_278} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_557 = _loginfo_cycles_T_556[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_279; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_558 = {1'h0, loginfo_cycles_279} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_559 = _loginfo_cycles_T_558[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_280; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_560 = {1'h0, loginfo_cycles_280} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_561 = _loginfo_cycles_T_560[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_281; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_562 = {1'h0, loginfo_cycles_281} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_563 = _loginfo_cycles_T_562[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_282; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_564 = {1'h0, loginfo_cycles_282} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_565 = _loginfo_cycles_T_564[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_283; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_566 = {1'h0, loginfo_cycles_283} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_567 = _loginfo_cycles_T_566[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_284; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_568 = {1'h0, loginfo_cycles_284} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_569 = _loginfo_cycles_T_568[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_285; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_570 = {1'h0, loginfo_cycles_285} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_571 = _loginfo_cycles_T_570[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_286; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_572 = {1'h0, loginfo_cycles_286} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_573 = _loginfo_cycles_T_572[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_287; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_574 = {1'h0, loginfo_cycles_287} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_575 = _loginfo_cycles_T_574[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_288; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_576 = {1'h0, loginfo_cycles_288} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_577 = _loginfo_cycles_T_576[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_289; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_578 = {1'h0, loginfo_cycles_289} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_579 = _loginfo_cycles_T_578[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_290; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_580 = {1'h0, loginfo_cycles_290} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_581 = _loginfo_cycles_T_580[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_291; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_582 = {1'h0, loginfo_cycles_291} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_583 = _loginfo_cycles_T_582[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_292; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_584 = {1'h0, loginfo_cycles_292} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_585 = _loginfo_cycles_T_584[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_293; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_586 = {1'h0, loginfo_cycles_293} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_587 = _loginfo_cycles_T_586[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_294; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_588 = {1'h0, loginfo_cycles_294} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_589 = _loginfo_cycles_T_588[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_295; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_590 = {1'h0, loginfo_cycles_295} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_591 = _loginfo_cycles_T_590[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_296; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_592 = {1'h0, loginfo_cycles_296} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_593 = _loginfo_cycles_T_592[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_297; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_594 = {1'h0, loginfo_cycles_297} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_595 = _loginfo_cycles_T_594[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_298; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_596 = {1'h0, loginfo_cycles_298} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_597 = _loginfo_cycles_T_596[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_299; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_598 = {1'h0, loginfo_cycles_299} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_599 = _loginfo_cycles_T_598[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_300; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_600 = {1'h0, loginfo_cycles_300} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_601 = _loginfo_cycles_T_600[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_301; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_602 = {1'h0, loginfo_cycles_301} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_603 = _loginfo_cycles_T_602[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_302; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_604 = {1'h0, loginfo_cycles_302} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_605 = _loginfo_cycles_T_604[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_303; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_606 = {1'h0, loginfo_cycles_303} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_607 = _loginfo_cycles_T_606[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_304; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_608 = {1'h0, loginfo_cycles_304} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_609 = _loginfo_cycles_T_608[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_305; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_610 = {1'h0, loginfo_cycles_305} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_611 = _loginfo_cycles_T_610[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_306; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_612 = {1'h0, loginfo_cycles_306} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_613 = _loginfo_cycles_T_612[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_307; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_614 = {1'h0, loginfo_cycles_307} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_615 = _loginfo_cycles_T_614[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_308; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_616 = {1'h0, loginfo_cycles_308} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_617 = _loginfo_cycles_T_616[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_309; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_618 = {1'h0, loginfo_cycles_309} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_619 = _loginfo_cycles_T_618[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_310; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_620 = {1'h0, loginfo_cycles_310} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_621 = _loginfo_cycles_T_620[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_311; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_622 = {1'h0, loginfo_cycles_311} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_623 = _loginfo_cycles_T_622[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_312; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_624 = {1'h0, loginfo_cycles_312} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_625 = _loginfo_cycles_T_624[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_313; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_626 = {1'h0, loginfo_cycles_313} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_627 = _loginfo_cycles_T_626[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_314; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_628 = {1'h0, loginfo_cycles_314} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_629 = _loginfo_cycles_T_628[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_315; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_630 = {1'h0, loginfo_cycles_315} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_631 = _loginfo_cycles_T_630[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_316; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_632 = {1'h0, loginfo_cycles_316} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_633 = _loginfo_cycles_T_632[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_317; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_634 = {1'h0, loginfo_cycles_317} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_635 = _loginfo_cycles_T_634[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_318; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_636 = {1'h0, loginfo_cycles_318} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_637 = _loginfo_cycles_T_636[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_319; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_638 = {1'h0, loginfo_cycles_319} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_639 = _loginfo_cycles_T_638[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_320; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_640 = {1'h0, loginfo_cycles_320} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_641 = _loginfo_cycles_T_640[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_321; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_642 = {1'h0, loginfo_cycles_321} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_643 = _loginfo_cycles_T_642[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_322; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_644 = {1'h0, loginfo_cycles_322} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_645 = _loginfo_cycles_T_644[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_323; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_646 = {1'h0, loginfo_cycles_323} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_647 = _loginfo_cycles_T_646[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_324; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_648 = {1'h0, loginfo_cycles_324} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_649 = _loginfo_cycles_T_648[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_325; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_650 = {1'h0, loginfo_cycles_325} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_651 = _loginfo_cycles_T_650[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_326; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_652 = {1'h0, loginfo_cycles_326} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_653 = _loginfo_cycles_T_652[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_327; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_654 = {1'h0, loginfo_cycles_327} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_655 = _loginfo_cycles_T_654[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_328; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_656 = {1'h0, loginfo_cycles_328} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_657 = _loginfo_cycles_T_656[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_329; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_658 = {1'h0, loginfo_cycles_329} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_659 = _loginfo_cycles_T_658[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_330; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_660 = {1'h0, loginfo_cycles_330} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_661 = _loginfo_cycles_T_660[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_331; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_662 = {1'h0, loginfo_cycles_331} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_663 = _loginfo_cycles_T_662[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_332; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_664 = {1'h0, loginfo_cycles_332} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_665 = _loginfo_cycles_T_664[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_333; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_666 = {1'h0, loginfo_cycles_333} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_667 = _loginfo_cycles_T_666[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_334; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_668 = {1'h0, loginfo_cycles_334} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_669 = _loginfo_cycles_T_668[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_335; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_670 = {1'h0, loginfo_cycles_335} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_671 = _loginfo_cycles_T_670[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_336; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_672 = {1'h0, loginfo_cycles_336} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_673 = _loginfo_cycles_T_672[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_337; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_674 = {1'h0, loginfo_cycles_337} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_675 = _loginfo_cycles_T_674[63:0]; // @[Util.scala:19:38] wire _T_1371 = dicBuilderState == 4'h3; // @[FSECompressorDicBuilder.scala:156:32, :551:28] wire _GEN_209 = ~(\|dicBuilderState) \| _T_839 \| _T_846; // @[FSECompressorDicBuilder.scala:156:32, :198:25, :316:25, :389:44, :551:28] wire _GEN_210 = _GEN_209 \| ~_T_1371; // @[FSECompressorDicBuilder.scala:389:44, :551:28] assign ll_normCountEqsNegOneCumul_0 = _GEN_210 ? 8'h0 : ll_normCountEqsNegOne_0; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :551:28] assign ll_normCountEqsNegOne_0 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_0)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_211 = {1'h0, ll_cumul_0}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_1_T = _GEN_211 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_1_T_1 = _ll_cumul_1_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_1_T_2 = _GEN_211 + {1'h0, ll_normalizedCounterReg_0}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_1_T_3 = _ll_cumul_1_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_1_T = {1'h0, ll_normCountEqsNegOneCumul_0} + _GEN_198; // @[FSECompressorDicBuilder.scala:389:44, :390:65, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_1_T_1 = _ll_normCountEqsNegOneCumul_1_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_1 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_1_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_1 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_1)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_212 = {1'h0, ll_cumul_1}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_2_T = _GEN_212 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_2_T_1 = _ll_cumul_2_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_2_T_2 = _GEN_212 + {1'h0, ll_normalizedCounterReg_1}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_2_T_3 = _ll_cumul_2_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_2_T = {1'h0, ll_normCountEqsNegOneCumul_1} + {1'h0, ll_normCountEqsNegOne_2}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_2_T_1 = _ll_normCountEqsNegOneCumul_2_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_2 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_2_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_2 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_2)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_213 = {1'h0, ll_cumul_2}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_3_T = _GEN_213 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_3_T_1 = _ll_cumul_3_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_3_T_2 = _GEN_213 + {1'h0, ll_normalizedCounterReg_2}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_3_T_3 = _ll_cumul_3_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_3_T = {1'h0, ll_normCountEqsNegOneCumul_2} + {1'h0, ll_normCountEqsNegOne_3}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_3_T_1 = _ll_normCountEqsNegOneCumul_3_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_3 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_3_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_3 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_3)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_214 = {1'h0, ll_cumul_3}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_4_T = _GEN_214 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_4_T_1 = _ll_cumul_4_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_4_T_2 = _GEN_214 + {1'h0, ll_normalizedCounterReg_3}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_4_T_3 = _ll_cumul_4_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_4_T = {1'h0, ll_normCountEqsNegOneCumul_3} + {1'h0, ll_normCountEqsNegOne_4}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_4_T_1 = _ll_normCountEqsNegOneCumul_4_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_4 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_4_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_4 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_4)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_215 = {1'h0, ll_cumul_4}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_5_T = _GEN_215 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_5_T_1 = _ll_cumul_5_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_5_T_2 = _GEN_215 + {1'h0, ll_normalizedCounterReg_4}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_5_T_3 = _ll_cumul_5_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_5_T = {1'h0, ll_normCountEqsNegOneCumul_4} + {1'h0, ll_normCountEqsNegOne_5}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_5_T_1 = _ll_normCountEqsNegOneCumul_5_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_5 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_5_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_5 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_5)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_216 = {1'h0, ll_cumul_5}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_6_T = _GEN_216 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_6_T_1 = _ll_cumul_6_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_6_T_2 = _GEN_216 + {1'h0, ll_normalizedCounterReg_5}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_6_T_3 = _ll_cumul_6_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_6_T = {1'h0, ll_normCountEqsNegOneCumul_5} + {1'h0, ll_normCountEqsNegOne_6}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_6_T_1 = _ll_normCountEqsNegOneCumul_6_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_6 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_6_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_6 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_6)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_217 = {1'h0, ll_cumul_6}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_7_T = _GEN_217 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_7_T_1 = _ll_cumul_7_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_7_T_2 = _GEN_217 + {1'h0, ll_normalizedCounterReg_6}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_7_T_3 = _ll_cumul_7_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_7_T = {1'h0, ll_normCountEqsNegOneCumul_6} + {1'h0, ll_normCountEqsNegOne_7}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_7_T_1 = _ll_normCountEqsNegOneCumul_7_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_7 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_7_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_7 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_7)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_218 = {1'h0, ll_cumul_7}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_8_T = _GEN_218 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_8_T_1 = _ll_cumul_8_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_8_T_2 = _GEN_218 + {1'h0, ll_normalizedCounterReg_7}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_8_T_3 = _ll_cumul_8_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_8_T = {1'h0, ll_normCountEqsNegOneCumul_7} + {1'h0, ll_normCountEqsNegOne_8}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_8_T_1 = _ll_normCountEqsNegOneCumul_8_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_8 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_8_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_8 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_8)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_219 = {1'h0, ll_cumul_8}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_9_T = _GEN_219 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_9_T_1 = _ll_cumul_9_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_9_T_2 = _GEN_219 + {1'h0, ll_normalizedCounterReg_8}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_9_T_3 = _ll_cumul_9_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_9_T = {1'h0, ll_normCountEqsNegOneCumul_8} + {1'h0, ll_normCountEqsNegOne_9}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_9_T_1 = _ll_normCountEqsNegOneCumul_9_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_9 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_9_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_9 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_9)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_220 = {1'h0, ll_cumul_9}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_10_T = _GEN_220 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_10_T_1 = _ll_cumul_10_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_10_T_2 = _GEN_220 + {1'h0, ll_normalizedCounterReg_9}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_10_T_3 = _ll_cumul_10_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_10_T = {1'h0, ll_normCountEqsNegOneCumul_9} + {1'h0, ll_normCountEqsNegOne_10}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_10_T_1 = _ll_normCountEqsNegOneCumul_10_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_10 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_10_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_10 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_10)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_221 = {1'h0, ll_cumul_10}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_11_T = _GEN_221 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_11_T_1 = _ll_cumul_11_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_11_T_2 = _GEN_221 + {1'h0, ll_normalizedCounterReg_10}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_11_T_3 = _ll_cumul_11_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_11_T = {1'h0, ll_normCountEqsNegOneCumul_10} + {1'h0, ll_normCountEqsNegOne_11}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_11_T_1 = _ll_normCountEqsNegOneCumul_11_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_11 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_11_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_11 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_11)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_222 = {1'h0, ll_cumul_11}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_12_T = _GEN_222 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_12_T_1 = _ll_cumul_12_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_12_T_2 = _GEN_222 + {1'h0, ll_normalizedCounterReg_11}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_12_T_3 = _ll_cumul_12_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_12_T = {1'h0, ll_normCountEqsNegOneCumul_11} + {1'h0, ll_normCountEqsNegOne_12}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_12_T_1 = _ll_normCountEqsNegOneCumul_12_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_12 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_12_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_12 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_12)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_223 = {1'h0, ll_cumul_12}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_13_T = _GEN_223 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_13_T_1 = _ll_cumul_13_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_13_T_2 = _GEN_223 + {1'h0, ll_normalizedCounterReg_12}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_13_T_3 = _ll_cumul_13_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_13_T = {1'h0, ll_normCountEqsNegOneCumul_12} + {1'h0, ll_normCountEqsNegOne_13}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_13_T_1 = _ll_normCountEqsNegOneCumul_13_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_13 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_13_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_13 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_13)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_224 = {1'h0, ll_cumul_13}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_14_T = _GEN_224 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_14_T_1 = _ll_cumul_14_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_14_T_2 = _GEN_224 + {1'h0, ll_normalizedCounterReg_13}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_14_T_3 = _ll_cumul_14_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_14_T = {1'h0, ll_normCountEqsNegOneCumul_13} + {1'h0, ll_normCountEqsNegOne_14}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_14_T_1 = _ll_normCountEqsNegOneCumul_14_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_14 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_14_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_14 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_14)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_225 = {1'h0, ll_cumul_14}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_15_T = _GEN_225 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_15_T_1 = _ll_cumul_15_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_15_T_2 = _GEN_225 + {1'h0, ll_normalizedCounterReg_14}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_15_T_3 = _ll_cumul_15_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_15_T = {1'h0, ll_normCountEqsNegOneCumul_14} + {1'h0, ll_normCountEqsNegOne_15}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_15_T_1 = _ll_normCountEqsNegOneCumul_15_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_15 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_15_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_15 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_15)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_226 = {1'h0, ll_cumul_15}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_16_T = _GEN_226 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_16_T_1 = _ll_cumul_16_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_16_T_2 = _GEN_226 + {1'h0, ll_normalizedCounterReg_15}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_16_T_3 = _ll_cumul_16_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_16_T = {1'h0, ll_normCountEqsNegOneCumul_15} + {1'h0, ll_normCountEqsNegOne_16}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_16_T_1 = _ll_normCountEqsNegOneCumul_16_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_16 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_16_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_16 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_16)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_227 = {1'h0, ll_cumul_16}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_17_T = _GEN_227 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_17_T_1 = _ll_cumul_17_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_17_T_2 = _GEN_227 + {1'h0, ll_normalizedCounterReg_16}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_17_T_3 = _ll_cumul_17_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_17_T = {1'h0, ll_normCountEqsNegOneCumul_16} + {1'h0, ll_normCountEqsNegOne_17}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_17_T_1 = _ll_normCountEqsNegOneCumul_17_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_17 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_17_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_17 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_17)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_228 = {1'h0, ll_cumul_17}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_18_T = _GEN_228 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_18_T_1 = _ll_cumul_18_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_18_T_2 = _GEN_228 + {1'h0, ll_normalizedCounterReg_17}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_18_T_3 = _ll_cumul_18_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_18_T = {1'h0, ll_normCountEqsNegOneCumul_17} + {1'h0, ll_normCountEqsNegOne_18}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_18_T_1 = _ll_normCountEqsNegOneCumul_18_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_18 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_18_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_18 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_18)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_229 = {1'h0, ll_cumul_18}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_19_T = _GEN_229 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_19_T_1 = _ll_cumul_19_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_19_T_2 = _GEN_229 + {1'h0, ll_normalizedCounterReg_18}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_19_T_3 = _ll_cumul_19_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_19_T = {1'h0, ll_normCountEqsNegOneCumul_18} + {1'h0, ll_normCountEqsNegOne_19}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_19_T_1 = _ll_normCountEqsNegOneCumul_19_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_19 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_19_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_19 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_19)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_230 = {1'h0, ll_cumul_19}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_20_T = _GEN_230 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_20_T_1 = _ll_cumul_20_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_20_T_2 = _GEN_230 + {1'h0, ll_normalizedCounterReg_19}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_20_T_3 = _ll_cumul_20_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_20_T = {1'h0, ll_normCountEqsNegOneCumul_19} + {1'h0, ll_normCountEqsNegOne_20}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_20_T_1 = _ll_normCountEqsNegOneCumul_20_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_20 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_20_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_20 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_20)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_231 = {1'h0, ll_cumul_20}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_21_T = _GEN_231 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_21_T_1 = _ll_cumul_21_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_21_T_2 = _GEN_231 + {1'h0, ll_normalizedCounterReg_20}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_21_T_3 = _ll_cumul_21_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_21_T = {1'h0, ll_normCountEqsNegOneCumul_20} + {1'h0, ll_normCountEqsNegOne_21}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_21_T_1 = _ll_normCountEqsNegOneCumul_21_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_21 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_21_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_21 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_21)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_232 = {1'h0, ll_cumul_21}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_22_T = _GEN_232 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_22_T_1 = _ll_cumul_22_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_22_T_2 = _GEN_232 + {1'h0, ll_normalizedCounterReg_21}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_22_T_3 = _ll_cumul_22_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_22_T = {1'h0, ll_normCountEqsNegOneCumul_21} + {1'h0, ll_normCountEqsNegOne_22}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_22_T_1 = _ll_normCountEqsNegOneCumul_22_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_22 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_22_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_22 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_22)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_233 = {1'h0, ll_cumul_22}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_23_T = _GEN_233 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_23_T_1 = _ll_cumul_23_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_23_T_2 = _GEN_233 + {1'h0, ll_normalizedCounterReg_22}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_23_T_3 = _ll_cumul_23_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_23_T = {1'h0, ll_normCountEqsNegOneCumul_22} + {1'h0, ll_normCountEqsNegOne_23}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_23_T_1 = _ll_normCountEqsNegOneCumul_23_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_23 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_23_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_23 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_23)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_234 = {1'h0, ll_cumul_23}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_24_T = _GEN_234 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_24_T_1 = _ll_cumul_24_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_24_T_2 = _GEN_234 + {1'h0, ll_normalizedCounterReg_23}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_24_T_3 = _ll_cumul_24_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_24_T = {1'h0, ll_normCountEqsNegOneCumul_23} + {1'h0, ll_normCountEqsNegOne_24}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_24_T_1 = _ll_normCountEqsNegOneCumul_24_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_24 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_24_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_24 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_24)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_235 = {1'h0, ll_cumul_24}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_25_T = _GEN_235 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_25_T_1 = _ll_cumul_25_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_25_T_2 = _GEN_235 + {1'h0, ll_normalizedCounterReg_24}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_25_T_3 = _ll_cumul_25_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_25_T = {1'h0, ll_normCountEqsNegOneCumul_24} + {1'h0, ll_normCountEqsNegOne_25}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_25_T_1 = _ll_normCountEqsNegOneCumul_25_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_25 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_25_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_25 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_25)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_236 = {1'h0, ll_cumul_25}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_26_T = _GEN_236 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_26_T_1 = _ll_cumul_26_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_26_T_2 = _GEN_236 + {1'h0, ll_normalizedCounterReg_25}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_26_T_3 = _ll_cumul_26_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_26_T = {1'h0, ll_normCountEqsNegOneCumul_25} + {1'h0, ll_normCountEqsNegOne_26}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_26_T_1 = _ll_normCountEqsNegOneCumul_26_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_26 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_26_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_26 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_26)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_237 = {1'h0, ll_cumul_26}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_27_T = _GEN_237 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_27_T_1 = _ll_cumul_27_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_27_T_2 = _GEN_237 + {1'h0, ll_normalizedCounterReg_26}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_27_T_3 = _ll_cumul_27_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_27_T = {1'h0, ll_normCountEqsNegOneCumul_26} + {1'h0, ll_normCountEqsNegOne_27}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_27_T_1 = _ll_normCountEqsNegOneCumul_27_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_27 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_27_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_27 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_27)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_238 = {1'h0, ll_cumul_27}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_28_T = _GEN_238 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_28_T_1 = _ll_cumul_28_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_28_T_2 = _GEN_238 + {1'h0, ll_normalizedCounterReg_27}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_28_T_3 = _ll_cumul_28_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_28_T = {1'h0, ll_normCountEqsNegOneCumul_27} + {1'h0, ll_normCountEqsNegOne_28}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_28_T_1 = _ll_normCountEqsNegOneCumul_28_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_28 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_28_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_28 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_28)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_239 = {1'h0, ll_cumul_28}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_29_T = _GEN_239 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_29_T_1 = _ll_cumul_29_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_29_T_2 = _GEN_239 + {1'h0, ll_normalizedCounterReg_28}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_29_T_3 = _ll_cumul_29_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_29_T = {1'h0, ll_normCountEqsNegOneCumul_28} + {1'h0, ll_normCountEqsNegOne_29}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_29_T_1 = _ll_normCountEqsNegOneCumul_29_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_29 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_29_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_29 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_29)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_240 = {1'h0, ll_cumul_29}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_30_T = _GEN_240 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_30_T_1 = _ll_cumul_30_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_30_T_2 = _GEN_240 + {1'h0, ll_normalizedCounterReg_29}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_30_T_3 = _ll_cumul_30_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_30_T = {1'h0, ll_normCountEqsNegOneCumul_29} + {1'h0, ll_normCountEqsNegOne_30}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_30_T_1 = _ll_normCountEqsNegOneCumul_30_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_30 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_30_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_30 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_30)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_241 = {1'h0, ll_cumul_30}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_31_T = _GEN_241 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_31_T_1 = _ll_cumul_31_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_31_T_2 = _GEN_241 + {1'h0, ll_normalizedCounterReg_30}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_31_T_3 = _ll_cumul_31_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_31_T = {1'h0, ll_normCountEqsNegOneCumul_30}; // @[FSECompressorDicBuilder.scala:389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_31_T_1 = _ll_normCountEqsNegOneCumul_31_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_31 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_31_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_cumul_0 = _GEN_209 \| ~(_T_1371 & ll_maxSV1[4:0] == 5'h0) ? 16'h0 : 16'h41; // @[FSECompressorDicBuilder.scala:379:39, :382:26, :389:44, :551:28, :703:27] assign ll_cumul_1 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h1 ? 16'h41 : (&ll_normalizedCounterReg_0) ? _ll_cumul_1_T_1 : _ll_cumul_1_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_2 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h2 ? 16'h41 : (&ll_normalizedCounterReg_1) ? _ll_cumul_2_T_1 : _ll_cumul_2_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_3 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h3 ? 16'h41 : (&ll_normalizedCounterReg_2) ? _ll_cumul_3_T_1 : _ll_cumul_3_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_4 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h4 ? 16'h41 : (&ll_normalizedCounterReg_3) ? _ll_cumul_4_T_1 : _ll_cumul_4_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_5 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h5 ? 16'h41 : (&ll_normalizedCounterReg_4) ? _ll_cumul_5_T_1 : _ll_cumul_5_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_6 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h6 ? 16'h41 : (&ll_normalizedCounterReg_5) ? _ll_cumul_6_T_1 : _ll_cumul_6_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_7 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h7 ? 16'h41 : (&ll_normalizedCounterReg_6) ? _ll_cumul_7_T_1 : _ll_cumul_7_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_8 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h8 ? 16'h41 : (&ll_normalizedCounterReg_7) ? _ll_cumul_8_T_1 : _ll_cumul_8_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_9 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h9 ? 16'h41 : (&ll_normalizedCounterReg_8) ? _ll_cumul_9_T_1 : _ll_cumul_9_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_10 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'hA ? 16'h41 : (&ll_normalizedCounterReg_9) ? _ll_cumul_10_T_1 : _ll_cumul_10_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_11 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'hB ? 16'h41 : (&ll_normalizedCounterReg_10) ? _ll_cumul_11_T_1 : _ll_cumul_11_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_12 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'hC ? 16'h41 : (&ll_normalizedCounterReg_11) ? _ll_cumul_12_T_1 : _ll_cumul_12_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_13 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'hD ? 16'h41 : (&ll_normalizedCounterReg_12) ? _ll_cumul_13_T_1 : _ll_cumul_13_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_14 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'hE ? 16'h41 : (&ll_normalizedCounterReg_13) ? _ll_cumul_14_T_1 : _ll_cumul_14_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_15 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'hF ? 16'h41 : (&ll_normalizedCounterReg_14) ? _ll_cumul_15_T_1 : _ll_cumul_15_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_16 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h10 ? 16'h41 : (&ll_normalizedCounterReg_15) ? _ll_cumul_16_T_1 : _ll_cumul_16_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_17 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h11 ? 16'h41 : (&ll_normalizedCounterReg_16) ? _ll_cumul_17_T_1 : _ll_cumul_17_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_18 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h12 ? 16'h41 : (&ll_normalizedCounterReg_17) ? _ll_cumul_18_T_1 : _ll_cumul_18_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_19 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h13 ? 16'h41 : (&ll_normalizedCounterReg_18) ? _ll_cumul_19_T_1 : _ll_cumul_19_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_20 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h14 ? 16'h41 : (&ll_normalizedCounterReg_19) ? _ll_cumul_20_T_1 : _ll_cumul_20_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_21 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h15 ? 16'h41 : (&ll_normalizedCounterReg_20) ? _ll_cumul_21_T_1 : _ll_cumul_21_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_22 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h16 ? 16'h41 : (&ll_normalizedCounterReg_21) ? _ll_cumul_22_T_1 : _ll_cumul_22_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_23 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h17 ? 16'h41 : (&ll_normalizedCounterReg_22) ? _ll_cumul_23_T_1 : _ll_cumul_23_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_24 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h18 ? 16'h41 : (&ll_normalizedCounterReg_23) ? _ll_cumul_24_T_1 : _ll_cumul_24_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_25 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h19 ? 16'h41 : (&ll_normalizedCounterReg_24) ? _ll_cumul_25_T_1 : _ll_cumul_25_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_26 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h1A ? 16'h41 : (&ll_normalizedCounterReg_25) ? _ll_cumul_26_T_1 : _ll_cumul_26_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_27 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h1B ? 16'h41 : (&ll_normalizedCounterReg_26) ? _ll_cumul_27_T_1 : _ll_cumul_27_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_28 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h1C ? 16'h41 : (&ll_normalizedCounterReg_27) ? _ll_cumul_28_T_1 : _ll_cumul_28_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_29 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h1D ? 16'h41 : (&ll_normalizedCounterReg_28) ? _ll_cumul_29_T_1 : _ll_cumul_29_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_30 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h1E ? 16'h41 : (&ll_normalizedCounterReg_29) ? _ll_cumul_30_T_1 : _ll_cumul_30_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_31 = _GEN_210 ? 16'h0 : (&(ll_maxSV1[4:0])) ? 16'h41 : (&ll_normalizedCounterReg_30) ? _ll_cumul_31_T_1 : _ll_cumul_31_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] wire [39:0] _ll_highThresholdAfterCumul_T = 40'h3F - {1'h0, ll_normCountEqsNegOneSum}; // @[FSECompressorDicBuilder.scala:390:65, :704:65] wire [38:0] _ll_highThresholdAfterCumul_T_1 = _ll_highThresholdAfterCumul_T[38:0]; // @[FSECompressorDicBuilder.scala:704:65] wire _T_1559 = dicBuilderState == 4'h4; // @[FSECompressorDicBuilder.scala:156:32, :551:28] wire [64:0] _GEN_242 = {1'h0, ll_s}; // @[FSECompressorDicBuilder.scala:403:21, :716:22] wire [64:0] _GEN_243 = _GEN_242 + 65'h1; // @[FSECompressorDicBuilder.scala:716:22] wire [64:0] _ll_s_T; // @[FSECompressorDicBuilder.scala:716:22] assign _ll_s_T = _GEN_243; // @[FSECompressorDicBuilder.scala:716:22] wire [64:0] _ll_s_T_2; // @[FSECompressorDicBuilder.scala:757:20] assign _ll_s_T_2 = _GEN_243; // @[FSECompressorDicBuilder.scala:716:22, :757:20] wire [64:0] _ll_s_T_4; // @[FSECompressorDicBuilder.scala:768:20] assign _ll_s_T_4 = _GEN_243; // @[FSECompressorDicBuilder.scala:716:22, :768:20] wire [63:0] _ll_s_T_1 = _ll_s_T[63:0]; // @[FSECompressorDicBuilder.scala:716:22] wire [64:0] _ll_sv_T = {1'h0, ll_sv} + 65'h101010101010101; // @[FSECompressorDicBuilder.scala:404:22, :717:24] wire [63:0] _ll_sv_T_1 = _ll_sv_T[63:0]; // @[FSECompressorDicBuilder.scala:717:24] wire [15:0] write_spread_cnt = {3'h0, _GEN_199[_n_T][15:3]}; // @[FSECompressorDicBuilder.scala:416:13, :719:34] wire [15:0] _write_extra_T = {13'h0, _GEN_199[_n_T][2:0]}; // @[FSECompressorDicBuilder.scala:416:13, :719:34, :720:30] wire write_extra = \|_write_extra_T; // @[FSECompressorDicBuilder.scala:720:{30,37}] wire [16:0] write_spread_cnt_wrapped = {1'h0, write_spread_cnt} + {16'h0, write_extra}; // @[FSECompressorDicBuilder.scala:719:34, :720:37, :721:57] wire [19:0] write_spread_bytes = {write_spread_cnt_wrapped, 3'h0}; // @[FSECompressorDicBuilder.scala:721:57, :722:59] wire [64:0] _GEN_244 = {1'h0, ll_pos}; // @[FSECompressorDicBuilder.scala:402:23, :723:26] wire [64:0] _ll_pos_T = _GEN_244 + {49'h0, _GEN_199[_n_T]}; // @[FSECompressorDicBuilder.scala:416:13, :719:34, :723:26] wire [63:0] _ll_pos_T_1 = _ll_pos_T[63:0]; // @[FSECompressorDicBuilder.scala:723:26] wire [64:0] _GEN_245 = 65'h0 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T = _GEN_245; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_144; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_144 = _GEN_245; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_1 = _shift_bytes_T[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes = _shift_bytes_T_1[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits = {shift_bytes, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_0_T = ll_sv >> shift_bits; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_246 = 65'h1 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_2; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_2 = _GEN_246; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_146; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_146 = _GEN_246; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_3 = _shift_bytes_T_2[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_1 = _shift_bytes_T_3[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_1 = {shift_bytes_1, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_1_T = ll_sv >> shift_bits_1; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_247 = 65'h2 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_4; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_4 = _GEN_247; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_148; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_148 = _GEN_247; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_5 = _shift_bytes_T_4[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_2 = _shift_bytes_T_5[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_2 = {shift_bytes_2, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_2_T = ll_sv >> shift_bits_2; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_248 = 65'h3 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_6; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_6 = _GEN_248; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_150; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_150 = _GEN_248; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_7 = _shift_bytes_T_6[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_3 = _shift_bytes_T_7[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_3 = {shift_bytes_3, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_3_T = ll_sv >> shift_bits_3; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_249 = 65'h4 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_8; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_8 = _GEN_249; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_152; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_152 = _GEN_249; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_9 = _shift_bytes_T_8[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_4 = _shift_bytes_T_9[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_4 = {shift_bytes_4, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_4_T = ll_sv >> shift_bits_4; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_250 = 65'h5 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_10; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_10 = _GEN_250; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_154; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_154 = _GEN_250; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_11 = _shift_bytes_T_10[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_5 = _shift_bytes_T_11[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_5 = {shift_bytes_5, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_5_T = ll_sv >> shift_bits_5; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_251 = 65'h6 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_12; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_12 = _GEN_251; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_156; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_156 = _GEN_251; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_13 = _shift_bytes_T_12[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_6 = _shift_bytes_T_13[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_6 = {shift_bytes_6, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_6_T = ll_sv >> shift_bits_6; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_252 = 65'h7 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_14; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_14 = _GEN_252; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_158; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_158 = _GEN_252; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_15 = _shift_bytes_T_14[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_7 = _shift_bytes_T_15[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_7 = {shift_bytes_7, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_7_T = ll_sv >> shift_bits_7; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_253 = 65'h8 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_16; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_16 = _GEN_253; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_160; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_160 = _GEN_253; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_17 = _shift_bytes_T_16[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_8 = _shift_bytes_T_17[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_8 = {shift_bytes_8, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_8_T = ll_sv >> shift_bits_8; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_254 = 65'h9 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_18; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_18 = _GEN_254; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_162; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_162 = _GEN_254; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_19 = _shift_bytes_T_18[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_9 = _shift_bytes_T_19[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_9 = {shift_bytes_9, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_9_T = ll_sv >> shift_bits_9; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_255 = 65'hA - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_20; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_20 = _GEN_255; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_164; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_164 = _GEN_255; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_21 = _shift_bytes_T_20[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_10 = _shift_bytes_T_21[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_10 = {shift_bytes_10, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_10_T = ll_sv >> shift_bits_10; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_256 = 65'hB - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_22; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_22 = _GEN_256; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_166; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_166 = _GEN_256; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_23 = _shift_bytes_T_22[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_11 = _shift_bytes_T_23[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_11 = {shift_bytes_11, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_11_T = ll_sv >> shift_bits_11; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_257 = 65'hC - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_24; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_24 = _GEN_257; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_168; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_168 = _GEN_257; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_25 = _shift_bytes_T_24[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_12 = _shift_bytes_T_25[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_12 = {shift_bytes_12, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_12_T = ll_sv >> shift_bits_12; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_258 = 65'hD - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_26; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_26 = _GEN_258; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_170; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_170 = _GEN_258; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_27 = _shift_bytes_T_26[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_13 = _shift_bytes_T_27[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_13 = {shift_bytes_13, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_13_T = ll_sv >> shift_bits_13; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_259 = 65'hE - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_28; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_28 = _GEN_259; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_172; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_172 = _GEN_259; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_29 = _shift_bytes_T_28[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_14 = _shift_bytes_T_29[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_14 = {shift_bytes_14, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_14_T = ll_sv >> shift_bits_14; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_260 = 65'hF - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_30; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_30 = _GEN_260; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_174; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_174 = _GEN_260; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_31 = _shift_bytes_T_30[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_15 = _shift_bytes_T_31[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_15 = {shift_bytes_15, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_15_T = ll_sv >> shift_bits_15; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_261 = 65'h10 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_32; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_32 = _GEN_261; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_176; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_176 = _GEN_261; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_33 = _shift_bytes_T_32[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_16 = _shift_bytes_T_33[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_16 = {shift_bytes_16, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_16_T = ll_sv >> shift_bits_16; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_262 = 65'h11 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_34; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_34 = _GEN_262; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_178; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_178 = _GEN_262; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_35 = _shift_bytes_T_34[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_17 = _shift_bytes_T_35[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_17 = {shift_bytes_17, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_17_T = ll_sv >> shift_bits_17; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_263 = 65'h12 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_36; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_36 = _GEN_263; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_180; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_180 = _GEN_263; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_37 = _shift_bytes_T_36[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_18 = _shift_bytes_T_37[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_18 = {shift_bytes_18, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_18_T = ll_sv >> shift_bits_18; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_264 = 65'h13 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_38; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_38 = _GEN_264; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_182; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_182 = _GEN_264; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_39 = _shift_bytes_T_38[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_19 = _shift_bytes_T_39[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_19 = {shift_bytes_19, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_19_T = ll_sv >> shift_bits_19; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_265 = 65'h14 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_40; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_40 = _GEN_265; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_184; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_184 = _GEN_265; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_41 = _shift_bytes_T_40[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_20 = _shift_bytes_T_41[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_20 = {shift_bytes_20, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_20_T = ll_sv >> shift_bits_20; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_266 = 65'h15 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_42; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_42 = _GEN_266; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_186; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_186 = _GEN_266; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_43 = _shift_bytes_T_42[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_21 = _shift_bytes_T_43[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_21 = {shift_bytes_21, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_21_T = ll_sv >> shift_bits_21; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_267 = 65'h16 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_44; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_44 = _GEN_267; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_188; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_188 = _GEN_267; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_45 = _shift_bytes_T_44[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_22 = _shift_bytes_T_45[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_22 = {shift_bytes_22, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_22_T = ll_sv >> shift_bits_22; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_268 = 65'h17 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_46; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_46 = _GEN_268; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_190; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_190 = _GEN_268; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_47 = _shift_bytes_T_46[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_23 = _shift_bytes_T_47[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_23 = {shift_bytes_23, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_23_T = ll_sv >> shift_bits_23; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_269 = 65'h18 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_48; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_48 = _GEN_269; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_192; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_192 = _GEN_269; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_49 = _shift_bytes_T_48[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_24 = _shift_bytes_T_49[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_24 = {shift_bytes_24, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_24_T = ll_sv >> shift_bits_24; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_270 = 65'h19 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_50; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_50 = _GEN_270; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_194; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_194 = _GEN_270; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_51 = _shift_bytes_T_50[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_25 = _shift_bytes_T_51[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_25 = {shift_bytes_25, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_25_T = ll_sv >> shift_bits_25; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_271 = 65'h1A - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_52; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_52 = _GEN_271; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_196; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_196 = _GEN_271; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_53 = _shift_bytes_T_52[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_26 = _shift_bytes_T_53[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_26 = {shift_bytes_26, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_26_T = ll_sv >> shift_bits_26; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_272 = 65'h1B - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_54; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_54 = _GEN_272; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_198; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_198 = _GEN_272; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_55 = _shift_bytes_T_54[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_27 = _shift_bytes_T_55[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_27 = {shift_bytes_27, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_27_T = ll_sv >> shift_bits_27; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_273 = 65'h1C - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_56; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_56 = _GEN_273; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_200; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_200 = _GEN_273; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_57 = _shift_bytes_T_56[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_28 = _shift_bytes_T_57[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_28 = {shift_bytes_28, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_28_T = ll_sv >> shift_bits_28; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_274 = 65'h1D - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_58; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_58 = _GEN_274; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_202; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_202 = _GEN_274; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_59 = _shift_bytes_T_58[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_29 = _shift_bytes_T_59[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_29 = {shift_bytes_29, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_29_T = ll_sv >> shift_bits_29; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_275 = 65'h1E - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_60; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_60 = _GEN_275; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_204; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_204 = _GEN_275; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_61 = _shift_bytes_T_60[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_30 = _shift_bytes_T_61[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_30 = {shift_bytes_30, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_30_T = ll_sv >> shift_bits_30; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_276 = 65'h1F - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_62; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_62 = _GEN_276; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_206; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_206 = _GEN_276; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_63 = _shift_bytes_T_62[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_31 = _shift_bytes_T_63[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_31 = {shift_bytes_31, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_31_T = ll_sv >> shift_bits_31; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_277 = 65'h20 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_64; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_64 = _GEN_277; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_208; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_208 = _GEN_277; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_65 = _shift_bytes_T_64[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_32 = _shift_bytes_T_65[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_32 = {shift_bytes_32, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_32_T = ll_sv >> shift_bits_32; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_278 = 65'h21 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_66; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_66 = _GEN_278; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_210; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_210 = _GEN_278; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_67 = _shift_bytes_T_66[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_33 = _shift_bytes_T_67[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_33 = {shift_bytes_33, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_33_T = ll_sv >> shift_bits_33; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_279 = 65'h22 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_68; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_68 = _GEN_279; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_212; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_212 = _GEN_279; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_69 = _shift_bytes_T_68[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_34 = _shift_bytes_T_69[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_34 = {shift_bytes_34, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_34_T = ll_sv >> shift_bits_34; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_280 = 65'h23 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_70; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_70 = _GEN_280; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_214; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_214 = _GEN_280; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_71 = _shift_bytes_T_70[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_35 = _shift_bytes_T_71[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_35 = {shift_bytes_35, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_35_T = ll_sv >> shift_bits_35; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_281 = 65'h24 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_72; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_72 = _GEN_281; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_216; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_216 = _GEN_281; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_73 = _shift_bytes_T_72[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_36 = _shift_bytes_T_73[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_36 = {shift_bytes_36, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_36_T = ll_sv >> shift_bits_36; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_282 = 65'h25 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_74; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_74 = _GEN_282; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_218; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_218 = _GEN_282; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_75 = _shift_bytes_T_74[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_37 = _shift_bytes_T_75[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_37 = {shift_bytes_37, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_37_T = ll_sv >> shift_bits_37; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_283 = 65'h26 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_76; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_76 = _GEN_283; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_220; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_220 = _GEN_283; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_77 = _shift_bytes_T_76[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_38 = _shift_bytes_T_77[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_38 = {shift_bytes_38, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_38_T = ll_sv >> shift_bits_38; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_284 = 65'h27 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_78; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_78 = _GEN_284; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_222; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_222 = _GEN_284; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_79 = _shift_bytes_T_78[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_39 = _shift_bytes_T_79[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_39 = {shift_bytes_39, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_39_T = ll_sv >> shift_bits_39; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_285 = 65'h28 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_80; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_80 = _GEN_285; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_224; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_224 = _GEN_285; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_81 = _shift_bytes_T_80[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_40 = _shift_bytes_T_81[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_40 = {shift_bytes_40, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_40_T = ll_sv >> shift_bits_40; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_286 = 65'h29 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_82; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_82 = _GEN_286; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_226; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_226 = _GEN_286; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_83 = _shift_bytes_T_82[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_41 = _shift_bytes_T_83[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_41 = {shift_bytes_41, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_41_T = ll_sv >> shift_bits_41; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_287 = 65'h2A - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_84; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_84 = _GEN_287; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_228; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_228 = _GEN_287; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_85 = _shift_bytes_T_84[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_42 = _shift_bytes_T_85[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_42 = {shift_bytes_42, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_42_T = ll_sv >> shift_bits_42; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_288 = 65'h2B - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_86; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_86 = _GEN_288; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_230; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_230 = _GEN_288; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_87 = _shift_bytes_T_86[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_43 = _shift_bytes_T_87[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_43 = {shift_bytes_43, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_43_T = ll_sv >> shift_bits_43; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_289 = 65'h2C - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_88; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_88 = _GEN_289; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_232; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_232 = _GEN_289; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_89 = _shift_bytes_T_88[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_44 = _shift_bytes_T_89[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_44 = {shift_bytes_44, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_44_T = ll_sv >> shift_bits_44; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_290 = 65'h2D - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_90; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_90 = _GEN_290; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_234; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_234 = _GEN_290; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_91 = _shift_bytes_T_90[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_45 = _shift_bytes_T_91[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_45 = {shift_bytes_45, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_45_T = ll_sv >> shift_bits_45; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_291 = 65'h2E - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_92; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_92 = _GEN_291; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_236; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_236 = _GEN_291; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_93 = _shift_bytes_T_92[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_46 = _shift_bytes_T_93[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_46 = {shift_bytes_46, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_46_T = ll_sv >> shift_bits_46; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_292 = 65'h2F - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_94; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_94 = _GEN_292; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_238; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_238 = _GEN_292; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_95 = _shift_bytes_T_94[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_47 = _shift_bytes_T_95[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_47 = {shift_bytes_47, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_47_T = ll_sv >> shift_bits_47; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_293 = 65'h30 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_96; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_96 = _GEN_293; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_240; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_240 = _GEN_293; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_97 = _shift_bytes_T_96[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_48 = _shift_bytes_T_97[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_48 = {shift_bytes_48, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_48_T = ll_sv >> shift_bits_48; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_294 = 65'h31 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_98; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_98 = _GEN_294; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_242; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_242 = _GEN_294; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_99 = _shift_bytes_T_98[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_49 = _shift_bytes_T_99[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_49 = {shift_bytes_49, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_49_T = ll_sv >> shift_bits_49; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_295 = 65'h32 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_100; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_100 = _GEN_295; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_244; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_244 = _GEN_295; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_101 = _shift_bytes_T_100[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_50 = _shift_bytes_T_101[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_50 = {shift_bytes_50, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_50_T = ll_sv >> shift_bits_50; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_296 = 65'h33 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_102; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_102 = _GEN_296; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_246; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_246 = _GEN_296; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_103 = _shift_bytes_T_102[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_51 = _shift_bytes_T_103[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_51 = {shift_bytes_51, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_51_T = ll_sv >> shift_bits_51; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_297 = 65'h34 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_104; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_104 = _GEN_297; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_248; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_248 = _GEN_297; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_105 = _shift_bytes_T_104[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_52 = _shift_bytes_T_105[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_52 = {shift_bytes_52, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_52_T = ll_sv >> shift_bits_52; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_298 = 65'h35 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_106; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_106 = _GEN_298; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_250; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_250 = _GEN_298; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_107 = _shift_bytes_T_106[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_53 = _shift_bytes_T_107[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_53 = {shift_bytes_53, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_53_T = ll_sv >> shift_bits_53; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_299 = 65'h36 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_108; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_108 = _GEN_299; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_252; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_252 = _GEN_299; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_109 = _shift_bytes_T_108[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_54 = _shift_bytes_T_109[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_54 = {shift_bytes_54, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_54_T = ll_sv >> shift_bits_54; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_300 = 65'h37 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_110; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_110 = _GEN_300; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_254; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_254 = _GEN_300; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_111 = _shift_bytes_T_110[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_55 = _shift_bytes_T_111[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_55 = {shift_bytes_55, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_55_T = ll_sv >> shift_bits_55; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_301 = 65'h38 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_112; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_112 = _GEN_301; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_256; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_256 = _GEN_301; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_113 = _shift_bytes_T_112[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_56 = _shift_bytes_T_113[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_56 = {shift_bytes_56, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_56_T = ll_sv >> shift_bits_56; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_302 = 65'h39 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_114; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_114 = _GEN_302; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_258; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_258 = _GEN_302; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_115 = _shift_bytes_T_114[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_57 = _shift_bytes_T_115[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_57 = {shift_bytes_57, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_57_T = ll_sv >> shift_bits_57; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_303 = 65'h3A - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_116; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_116 = _GEN_303; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_260; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_260 = _GEN_303; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_117 = _shift_bytes_T_116[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_58 = _shift_bytes_T_117[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_58 = {shift_bytes_58, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_58_T = ll_sv >> shift_bits_58; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_304 = 65'h3B - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_118; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_118 = _GEN_304; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_262; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_262 = _GEN_304; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_119 = _shift_bytes_T_118[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_59 = _shift_bytes_T_119[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_59 = {shift_bytes_59, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_59_T = ll_sv >> shift_bits_59; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_305 = 65'h3C - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_120; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_120 = _GEN_305; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_264; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_264 = _GEN_305; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_121 = _shift_bytes_T_120[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_60 = _shift_bytes_T_121[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_60 = {shift_bytes_60, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_60_T = ll_sv >> shift_bits_60; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_306 = 65'h3D - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_122; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_122 = _GEN_306; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_266; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_266 = _GEN_306; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_123 = _shift_bytes_T_122[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_61 = _shift_bytes_T_123[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_61 = {shift_bytes_61, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_61_T = ll_sv >> shift_bits_61; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_307 = 65'h3E - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_124; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_124 = _GEN_307; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_268; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_268 = _GEN_307; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_125 = _shift_bytes_T_124[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_62 = _shift_bytes_T_125[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_62 = {shift_bytes_62, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_62_T = ll_sv >> shift_bits_62; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_308 = 65'h3F - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_126; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_126 = _GEN_308; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_270; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_270 = _GEN_308; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_127 = _shift_bytes_T_126[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_63 = _shift_bytes_T_127[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_63 = {shift_bytes_63, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_63_T = ll_sv >> shift_bits_63; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_128 = 65'h40 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_129 = _shift_bytes_T_128[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_64 = _shift_bytes_T_129[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_64 = {shift_bytes_64, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_64_T = ll_sv >> shift_bits_64; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_130 = 65'h41 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_131 = _shift_bytes_T_130[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_65 = _shift_bytes_T_131[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_65 = {shift_bytes_65, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_65_T = ll_sv >> shift_bits_65; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_132 = 65'h42 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_133 = _shift_bytes_T_132[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_66 = _shift_bytes_T_133[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_66 = {shift_bytes_66, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_66_T = ll_sv >> shift_bits_66; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_134 = 65'h43 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_135 = _shift_bytes_T_134[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_67 = _shift_bytes_T_135[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_67 = {shift_bytes_67, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_67_T = ll_sv >> shift_bits_67; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_136 = 65'h44 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_137 = _shift_bytes_T_136[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_68 = _shift_bytes_T_137[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_68 = {shift_bytes_68, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_68_T = ll_sv >> shift_bits_68; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_138 = 65'h45 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_139 = _shift_bytes_T_138[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_69 = _shift_bytes_T_139[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_69 = {shift_bytes_69, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_69_T = ll_sv >> shift_bits_69; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_140 = 65'h46 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_141 = _shift_bytes_T_140[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_70 = _shift_bytes_T_141[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_70 = {shift_bytes_70, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_70_T = ll_sv >> shift_bits_70; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_142 = 65'h47 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_143 = _shift_bytes_T_142[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_71 = _shift_bytes_T_143[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_71 = {shift_bytes_71, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_71_T = ll_sv >> shift_bits_71; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [63:0] _shift_bytes_T_145 = _shift_bytes_T_144[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_72 = _shift_bytes_T_145[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_72 = {shift_bytes_72, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T = ll_sv >> shift_bits_72; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_147 = _shift_bytes_T_146[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_73 = _shift_bytes_T_147[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_73 = {shift_bytes_73, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_1 = ll_sv >> shift_bits_73; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_149 = _shift_bytes_T_148[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_74 = _shift_bytes_T_149[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_74 = {shift_bytes_74, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_2 = ll_sv >> shift_bits_74; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_151 = _shift_bytes_T_150[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_75 = _shift_bytes_T_151[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_75 = {shift_bytes_75, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_3 = ll_sv >> shift_bits_75; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_153 = _shift_bytes_T_152[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_76 = _shift_bytes_T_153[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_76 = {shift_bytes_76, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_4 = ll_sv >> shift_bits_76; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_155 = _shift_bytes_T_154[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_77 = _shift_bytes_T_155[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_77 = {shift_bytes_77, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_5 = ll_sv >> shift_bits_77; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_157 = _shift_bytes_T_156[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_78 = _shift_bytes_T_157[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_78 = {shift_bytes_78, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_6 = ll_sv >> shift_bits_78; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_159 = _shift_bytes_T_158[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_79 = _shift_bytes_T_159[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_79 = {shift_bytes_79, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_7 = ll_sv >> shift_bits_79; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_161 = _shift_bytes_T_160[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_80 = _shift_bytes_T_161[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_80 = {shift_bytes_80, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_8 = ll_sv >> shift_bits_80; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_163 = _shift_bytes_T_162[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_81 = _shift_bytes_T_163[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_81 = {shift_bytes_81, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_9 = ll_sv >> shift_bits_81; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_165 = _shift_bytes_T_164[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_82 = _shift_bytes_T_165[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_82 = {shift_bytes_82, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_10 = ll_sv >> shift_bits_82; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_167 = _shift_bytes_T_166[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_83 = _shift_bytes_T_167[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_83 = {shift_bytes_83, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_11 = ll_sv >> shift_bits_83; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_169 = _shift_bytes_T_168[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_84 = _shift_bytes_T_169[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_84 = {shift_bytes_84, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_12 = ll_sv >> shift_bits_84; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_171 = _shift_bytes_T_170[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_85 = _shift_bytes_T_171[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_85 = {shift_bytes_85, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_13 = ll_sv >> shift_bits_85; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_173 = _shift_bytes_T_172[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_86 = _shift_bytes_T_173[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_86 = {shift_bytes_86, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_14 = ll_sv >> shift_bits_86; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_175 = _shift_bytes_T_174[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_87 = _shift_bytes_T_175[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_87 = {shift_bytes_87, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_15 = ll_sv >> shift_bits_87; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_177 = _shift_bytes_T_176[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_88 = _shift_bytes_T_177[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_88 = {shift_bytes_88, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_16 = ll_sv >> shift_bits_88; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_179 = _shift_bytes_T_178[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_89 = _shift_bytes_T_179[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_89 = {shift_bytes_89, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_17 = ll_sv >> shift_bits_89; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_181 = _shift_bytes_T_180[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_90 = _shift_bytes_T_181[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_90 = {shift_bytes_90, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_18 = ll_sv >> shift_bits_90; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_183 = _shift_bytes_T_182[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_91 = _shift_bytes_T_183[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_91 = {shift_bytes_91, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_19 = ll_sv >> shift_bits_91; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_185 = _shift_bytes_T_184[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_92 = _shift_bytes_T_185[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_92 = {shift_bytes_92, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_20 = ll_sv >> shift_bits_92; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_187 = _shift_bytes_T_186[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_93 = _shift_bytes_T_187[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_93 = {shift_bytes_93, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_21 = ll_sv >> shift_bits_93; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_189 = _shift_bytes_T_188[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_94 = _shift_bytes_T_189[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_94 = {shift_bytes_94, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_22 = ll_sv >> shift_bits_94; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_191 = _shift_bytes_T_190[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_95 = _shift_bytes_T_191[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_95 = {shift_bytes_95, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_23 = ll_sv >> shift_bits_95; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_193 = _shift_bytes_T_192[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_96 = _shift_bytes_T_193[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_96 = {shift_bytes_96, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_24 = ll_sv >> shift_bits_96; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_195 = _shift_bytes_T_194[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_97 = _shift_bytes_T_195[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_97 = {shift_bytes_97, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_25 = ll_sv >> shift_bits_97; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_197 = _shift_bytes_T_196[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_98 = _shift_bytes_T_197[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_98 = {shift_bytes_98, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_26 = ll_sv >> shift_bits_98; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_199 = _shift_bytes_T_198[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_99 = _shift_bytes_T_199[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_99 = {shift_bytes_99, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_27 = ll_sv >> shift_bits_99; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_201 = _shift_bytes_T_200[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_100 = _shift_bytes_T_201[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_100 = {shift_bytes_100, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_28 = ll_sv >> shift_bits_100; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_203 = _shift_bytes_T_202[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_101 = _shift_bytes_T_203[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_101 = {shift_bytes_101, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_29 = ll_sv >> shift_bits_101; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_205 = _shift_bytes_T_204[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_102 = _shift_bytes_T_205[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_102 = {shift_bytes_102, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_30 = ll_sv >> shift_bits_102; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_207 = _shift_bytes_T_206[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_103 = _shift_bytes_T_207[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_103 = {shift_bytes_103, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_31 = ll_sv >> shift_bits_103; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_209 = _shift_bytes_T_208[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_104 = _shift_bytes_T_209[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_104 = {shift_bytes_104, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_32 = ll_sv >> shift_bits_104; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_211 = _shift_bytes_T_210[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_105 = _shift_bytes_T_211[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_105 = {shift_bytes_105, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_33 = ll_sv >> shift_bits_105; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_213 = _shift_bytes_T_212[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_106 = _shift_bytes_T_213[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_106 = {shift_bytes_106, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_34 = ll_sv >> shift_bits_106; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_215 = _shift_bytes_T_214[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_107 = _shift_bytes_T_215[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_107 = {shift_bytes_107, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_35 = ll_sv >> shift_bits_107; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_217 = _shift_bytes_T_216[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_108 = _shift_bytes_T_217[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_108 = {shift_bytes_108, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_36 = ll_sv >> shift_bits_108; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_219 = _shift_bytes_T_218[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_109 = _shift_bytes_T_219[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_109 = {shift_bytes_109, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_37 = ll_sv >> shift_bits_109; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_221 = _shift_bytes_T_220[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_110 = _shift_bytes_T_221[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_110 = {shift_bytes_110, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_38 = ll_sv >> shift_bits_110; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_223 = _shift_bytes_T_222[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_111 = _shift_bytes_T_223[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_111 = {shift_bytes_111, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_39 = ll_sv >> shift_bits_111; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_225 = _shift_bytes_T_224[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_112 = _shift_bytes_T_225[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_112 = {shift_bytes_112, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_40 = ll_sv >> shift_bits_112; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_227 = _shift_bytes_T_226[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_113 = _shift_bytes_T_227[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_113 = {shift_bytes_113, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_41 = ll_sv >> shift_bits_113; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_229 = _shift_bytes_T_228[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_114 = _shift_bytes_T_229[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_114 = {shift_bytes_114, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_42 = ll_sv >> shift_bits_114; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_231 = _shift_bytes_T_230[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_115 = _shift_bytes_T_231[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_115 = {shift_bytes_115, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_43 = ll_sv >> shift_bits_115; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_233 = _shift_bytes_T_232[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_116 = _shift_bytes_T_233[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_116 = {shift_bytes_116, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_44 = ll_sv >> shift_bits_116; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_235 = _shift_bytes_T_234[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_117 = _shift_bytes_T_235[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_117 = {shift_bytes_117, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_45 = ll_sv >> shift_bits_117; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_237 = _shift_bytes_T_236[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_118 = _shift_bytes_T_237[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_118 = {shift_bytes_118, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_46 = ll_sv >> shift_bits_118; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_239 = _shift_bytes_T_238[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_119 = _shift_bytes_T_239[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_119 = {shift_bytes_119, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_47 = ll_sv >> shift_bits_119; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_241 = _shift_bytes_T_240[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_120 = _shift_bytes_T_241[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_120 = {shift_bytes_120, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_48 = ll_sv >> shift_bits_120; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_243 = _shift_bytes_T_242[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_121 = _shift_bytes_T_243[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_121 = {shift_bytes_121, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_49 = ll_sv >> shift_bits_121; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_245 = _shift_bytes_T_244[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_122 = _shift_bytes_T_245[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_122 = {shift_bytes_122, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_50 = ll_sv >> shift_bits_122; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_247 = _shift_bytes_T_246[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_123 = _shift_bytes_T_247[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_123 = {shift_bytes_123, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_51 = ll_sv >> shift_bits_123; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_249 = _shift_bytes_T_248[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_124 = _shift_bytes_T_249[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_124 = {shift_bytes_124, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_52 = ll_sv >> shift_bits_124; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_251 = _shift_bytes_T_250[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_125 = _shift_bytes_T_251[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_125 = {shift_bytes_125, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_53 = ll_sv >> shift_bits_125; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_253 = _shift_bytes_T_252[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_126 = _shift_bytes_T_253[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_126 = {shift_bytes_126, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_54 = ll_sv >> shift_bits_126; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_255 = _shift_bytes_T_254[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_127 = _shift_bytes_T_255[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_127 = {shift_bytes_127, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_55 = ll_sv >> shift_bits_127; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_257 = _shift_bytes_T_256[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_128 = _shift_bytes_T_257[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_128 = {shift_bytes_128, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_56 = ll_sv >> shift_bits_128; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_259 = _shift_bytes_T_258[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_129 = _shift_bytes_T_259[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_129 = {shift_bytes_129, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_57 = ll_sv >> shift_bits_129; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_261 = _shift_bytes_T_260[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_130 = _shift_bytes_T_261[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_130 = {shift_bytes_130, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_58 = ll_sv >> shift_bits_130; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_263 = _shift_bytes_T_262[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_131 = _shift_bytes_T_263[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_131 = {shift_bytes_131, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_59 = ll_sv >> shift_bits_131; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_265 = _shift_bytes_T_264[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_132 = _shift_bytes_T_265[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_132 = {shift_bytes_132, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_60 = ll_sv >> shift_bits_132; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_267 = _shift_bytes_T_266[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_133 = _shift_bytes_T_267[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_133 = {shift_bytes_133, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_61 = ll_sv >> shift_bits_133; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_269 = _shift_bytes_T_268[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_134 = _shift_bytes_T_269[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_134 = {shift_bytes_134, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_62 = ll_sv >> shift_bits_134; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_271 = _shift_bytes_T_270[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_135 = _shift_bytes_T_271[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_135 = {shift_bytes_135, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_63 = ll_sv >> shift_bits_135; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] reg [63:0] loginfo_cycles_338; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_676 = {1'h0, loginfo_cycles_338} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_677 = _loginfo_cycles_T_676[63:0]; // @[Util.scala:19:38] wire _T_2379 = dicBuilderState == 4'h5; // @[FSECompressorDicBuilder.scala:156:32, :551:28] wire [63:0] _ll_s_T_3 = _ll_s_T_2[63:0]; // @[FSECompressorDicBuilder.scala:757:20] wire [5:0] _s_T = ll_s[5:0]; // @[FSECompressorDicBuilder.scala:403:21] wire [63:0][7:0] _GEN_309 = {{ll_tableSymbol_63}, {ll_tableSymbol_62}, {ll_tableSymbol_61}, {ll_tableSymbol_60}, {ll_tableSymbol_59}, {ll_tableSymbol_58}, {ll_tableSymbol_57}, {ll_tableSymbol_56}, {ll_tableSymbol_55}, {ll_tableSymbol_54}, {ll_tableSymbol_53}, {ll_tableSymbol_52}, {ll_tableSymbol_51}, {ll_tableSymbol_50}, {ll_tableSymbol_49}, {ll_tableSymbol_48}, {ll_tableSymbol_47}, {ll_tableSymbol_46}, {ll_tableSymbol_45}, {ll_tableSymbol_44}, {ll_tableSymbol_43}, {ll_tableSymbol_42}, {ll_tableSymbol_41}, {ll_tableSymbol_40}, {ll_tableSymbol_39}, {ll_tableSymbol_38}, {ll_tableSymbol_37}, {ll_tableSymbol_36}, {ll_tableSymbol_35}, {ll_tableSymbol_34}, {ll_tableSymbol_33}, {ll_tableSymbol_32}, {ll_tableSymbol_31}, {ll_tableSymbol_30}, {ll_tableSymbol_29}, {ll_tableSymbol_28}, {ll_tableSymbol_27}, {ll_tableSymbol_26}, {ll_tableSymbol_25}, {ll_tableSymbol_24}, {ll_tableSymbol_23}, {ll_tableSymbol_22}, {ll_tableSymbol_21}, {ll_tableSymbol_20}, {ll_tableSymbol_19}, {ll_tableSymbol_18}, {ll_tableSymbol_17}, {ll_tableSymbol_16}, {ll_tableSymbol_15}, {ll_tableSymbol_14}, {ll_tableSymbol_13}, {ll_tableSymbol_12}, {ll_tableSymbol_11}, {ll_tableSymbol_10}, {ll_tableSymbol_9}, {ll_tableSymbol_8}, {ll_tableSymbol_7}, {ll_tableSymbol_6}, {ll_tableSymbol_5}, {ll_tableSymbol_4}, {ll_tableSymbol_3}, {ll_tableSymbol_2}, {ll_tableSymbol_1}, {ll_tableSymbol_0}}; // @[FSECompressorDicBuilder.scala:383:31] wire [4:0] _ll_cumulReg_T = _GEN_309[_s_T][4:0]; wire [31:0][15:0] _GEN_310 = {{ll_cumulReg_31}, {ll_cumulReg_30}, {ll_cumulReg_29}, {ll_cumulReg_28}, {ll_cumulReg_27}, {ll_cumulReg_26}, {ll_cumulReg_25}, {ll_cumulReg_24}, {ll_cumulReg_23}, {ll_cumulReg_22}, {ll_cumulReg_21}, {ll_cumulReg_20}, {ll_cumulReg_19}, {ll_cumulReg_18}, {ll_cumulReg_17}, {ll_cumulReg_16}, {ll_cumulReg_15}, {ll_cumulReg_14}, {ll_cumulReg_13}, {ll_cumulReg_12}, {ll_cumulReg_11}, {ll_cumulReg_10}, {ll_cumulReg_9}, {ll_cumulReg_8}, {ll_cumulReg_7}, {ll_cumulReg_6}, {ll_cumulReg_5}, {ll_cumulReg_4}, {ll_cumulReg_3}, {ll_cumulReg_2}, {ll_cumulReg_1}, {ll_cumulReg_0}}; // @[FSECompressorDicBuilder.scala:394:28, :759:40] wire [16:0] _ll_cumulReg_T_1 = {1'h0, _GEN_310[_ll_cumulReg_T]} + 17'h1; // @[FSECompressorDicBuilder.scala:759:40] wire [15:0] _ll_cumulReg_T_2 = _ll_cumulReg_T_1[15:0]; // @[FSECompressorDicBuilder.scala:759:40] wire [64:0] _ll_tableU16_T = _GEN_242 + 65'h40; // @[FSECompressorDicBuilder.scala:716:22, :760:51] wire [63:0] _ll_tableU16_T_1 = _ll_tableU16_T[63:0]; // @[FSECompressorDicBuilder.scala:760:51] wire _T_2386 = dicBuilderState == 4'h6; // @[FSECompressorDicBuilder.scala:156:32, :551:28] wire [63:0] _ll_s_T_5 = _ll_s_T_4[63:0]; // @[FSECompressorDicBuilder.scala:768:20] wire [32:0] _GEN_311 = {1'h0, ll_total}; // @[FSECompressorDicBuilder.scala:414:25, :774:54] wire [32:0] _ll_symbolTTDeltaFindState_T = _GEN_311 - 33'h1; // @[FSECompressorDicBuilder.scala:774:54] wire [31:0] _ll_symbolTTDeltaFindState_T_1 = _ll_symbolTTDeltaFindState_T[31:0]; // @[FSECompressorDicBuilder.scala:774:54] wire [31:0] _ll_symbolTTDeltaFindState_T_2 = _ll_symbolTTDeltaFindState_T_1; // @[FSECompressorDicBuilder.scala:774:{54,61}] wire [32:0] _ll_total_T = _GEN_311 + 33'h1; // @[FSECompressorDicBuilder.scala:774:54, :775:30] wire [31:0] _ll_total_T_1 = _ll_total_T[31:0]; // @[FSECompressorDicBuilder.scala:775:30] wire [32:0] _GEN_312 = {1'h0, normCount}; // @[FSECompressorDicBuilder.scala:415:23, :777:65] wire [32:0] _maxBitsOut_T = _GEN_312 - 33'h1; // @[FSECompressorDicBuilder.scala:777:65] wire [31:0] _maxBitsOut_T_1 = _maxBitsOut_T[31:0]; // @[FSECompressorDicBuilder.scala:777:65] wire [15:0] _maxBitsOut_highBit_T_2 = _maxBitsOut_T_1[31:16]; // @[FSECompressorDicBuilder.scala:52:49, :777:65] wire [31:0] _maxBitsOut_highBit_T_3 = {16'h0, _maxBitsOut_highBit_T_2}; // @[FSECompressorDicBuilder.scala:52:49] wire [15:0] _maxBitsOut_highBit_T_4 = _maxBitsOut_T_1[15:0]; // @[FSECompressorDicBuilder.scala:52:49, :777:65] wire [31:0] _maxBitsOut_highBit_T_5 = {_maxBitsOut_highBit_T_4, 16'h0}; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_7 = _maxBitsOut_highBit_T_5 & 32'hFFFF0000; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_8 = _maxBitsOut_highBit_T_3 \| _maxBitsOut_highBit_T_7; // @[FSECompressorDicBuilder.scala:52:49] wire [23:0] _maxBitsOut_highBit_T_12 = _maxBitsOut_highBit_T_8[31:8]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_13 = {8'h0, _maxBitsOut_highBit_T_12 & 24'hFF00FF}; // @[FSECompressorDicBuilder.scala:52:49] wire [23:0] _maxBitsOut_highBit_T_14 = _maxBitsOut_highBit_T_8[23:0]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_15 = {_maxBitsOut_highBit_T_14, 8'h0}; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_17 = _maxBitsOut_highBit_T_15 & 32'hFF00FF00; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_18 = _maxBitsOut_highBit_T_13 \| _maxBitsOut_highBit_T_17; // @[FSECompressorDicBuilder.scala:52:49] wire [27:0] _maxBitsOut_highBit_T_22 = _maxBitsOut_highBit_T_18[31:4]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_23 = {4'h0, _maxBitsOut_highBit_T_22 & 28'hF0F0F0F}; // @[FSECompressorDicBuilder.scala:52:49] wire [27:0] _maxBitsOut_highBit_T_24 = _maxBitsOut_highBit_T_18[27:0]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_25 = {_maxBitsOut_highBit_T_24, 4'h0}; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_27 = _maxBitsOut_highBit_T_25 & 32'hF0F0F0F0; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_28 = _maxBitsOut_highBit_T_23 \| _maxBitsOut_highBit_T_27; // @[FSECompressorDicBuilder.scala:52:49] wire [29:0] _maxBitsOut_highBit_T_32 = _maxBitsOut_highBit_T_28[31:2]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_33 = {2'h0, _maxBitsOut_highBit_T_32 & 30'h33333333}; // @[FSECompressorDicBuilder.scala:52:49] wire [29:0] _maxBitsOut_highBit_T_34 = _maxBitsOut_highBit_T_28[29:0]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_35 = {_maxBitsOut_highBit_T_34, 2'h0}; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_37 = _maxBitsOut_highBit_T_35 & 32'hCCCCCCCC; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_38 = _maxBitsOut_highBit_T_33 \| _maxBitsOut_highBit_T_37; // @[FSECompressorDicBuilder.scala:52:49] wire [30:0] _maxBitsOut_highBit_T_42 = _maxBitsOut_highBit_T_38[31:1]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_43 = {1'h0, _maxBitsOut_highBit_T_42 & 31'h55555555}; // @[FSECompressorDicBuilder.scala:52:49] wire [30:0] _maxBitsOut_highBit_T_44 = _maxBitsOut_highBit_T_38[30:0]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_45 = {_maxBitsOut_highBit_T_44, 1'h0}; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_47 = _maxBitsOut_highBit_T_45 & 32'hAAAAAAAA; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_48 = _maxBitsOut_highBit_T_43 \| _maxBitsOut_highBit_T_47; // @[FSECompressorDicBuilder.scala:52:49] wire _maxBitsOut_highBit_T_49 = _maxBitsOut_highBit_T_48[0]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_50 = _maxBitsOut_highBit_T_48[1]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_51 = _maxBitsOut_highBit_T_48[2]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_52 = _maxBitsOut_highBit_T_48[3]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_53 = _maxBitsOut_highBit_T_48[4]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_54 = _maxBitsOut_highBit_T_48[5]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_55 = _maxBitsOut_highBit_T_48[6]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_56 = _maxBitsOut_highBit_T_48[7]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_57 = _maxBitsOut_highBit_T_48[8]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_58 = _maxBitsOut_highBit_T_48[9]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_59 = _maxBitsOut_highBit_T_48[10]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_60 = _maxBitsOut_highBit_T_48[11]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_61 = _maxBitsOut_highBit_T_48[12]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_62 = _maxBitsOut_highBit_T_48[13]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_63 = _maxBitsOut_highBit_T_48[14]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_64 = _maxBitsOut_highBit_T_48[15]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_65 = _maxBitsOut_highBit_T_48[16]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_66 = _maxBitsOut_highBit_T_48[17]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_67 = _maxBitsOut_highBit_T_48[18]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_68 = _maxBitsOut_highBit_T_48[19]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_69 = _maxBitsOut_highBit_T_48[20]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_70 = _maxBitsOut_highBit_T_48[21]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_71 = _maxBitsOut_highBit_T_48[22]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_72 = _maxBitsOut_highBit_T_48[23]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_73 = _maxBitsOut_highBit_T_48[24]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_74 = _maxBitsOut_highBit_T_48[25]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_75 = _maxBitsOut_highBit_T_48[26]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_76 = _maxBitsOut_highBit_T_48[27]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_77 = _maxBitsOut_highBit_T_48[28]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_78 = _maxBitsOut_highBit_T_48[29]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_79 = _maxBitsOut_highBit_T_48[30]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_80 = _maxBitsOut_highBit_T_48[31]; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_81 = {4'hF, ~_maxBitsOut_highBit_T_79}; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_82 = _maxBitsOut_highBit_T_78 ? 5'h1D : _maxBitsOut_highBit_T_81; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_83 = _maxBitsOut_highBit_T_77 ? 5'h1C : _maxBitsOut_highBit_T_82; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_84 = _maxBitsOut_highBit_T_76 ? 5'h1B : _maxBitsOut_highBit_T_83; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_85 = _maxBitsOut_highBit_T_75 ? 5'h1A : _maxBitsOut_highBit_T_84; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_86 = _maxBitsOut_highBit_T_74 ? 5'h19 : _maxBitsOut_highBit_T_85; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_87 = _maxBitsOut_highBit_T_73 ? 5'h18 : _maxBitsOut_highBit_T_86; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_88 = _maxBitsOut_highBit_T_72 ? 5'h17 : _maxBitsOut_highBit_T_87; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_89 = _maxBitsOut_highBit_T_71 ? 5'h16 : _maxBitsOut_highBit_T_88; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_90 = _maxBitsOut_highBit_T_70 ? 5'h15 : _maxBitsOut_highBit_T_89; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_91 = _maxBitsOut_highBit_T_69 ? 5'h14 : _maxBitsOut_highBit_T_90; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_92 = _maxBitsOut_highBit_T_68 ? 5'h13 : _maxBitsOut_highBit_T_91; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_93 = _maxBitsOut_highBit_T_67 ? 5'h12 : _maxBitsOut_highBit_T_92; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_94 = _maxBitsOut_highBit_T_66 ? 5'h11 : _maxBitsOut_highBit_T_93; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_95 = _maxBitsOut_highBit_T_65 ? 5'h10 : _maxBitsOut_highBit_T_94; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_96 = _maxBitsOut_highBit_T_64 ? 5'hF : _maxBitsOut_highBit_T_95; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_97 = _maxBitsOut_highBit_T_63 ? 5'hE : _maxBitsOut_highBit_T_96; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_98 = _maxBitsOut_highBit_T_62 ? 5'hD : _maxBitsOut_highBit_T_97; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_99 = _maxBitsOut_highBit_T_61 ? 5'hC : _maxBitsOut_highBit_T_98; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_100 = _maxBitsOut_highBit_T_60 ? 5'hB : _maxBitsOut_highBit_T_99; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_101 = _maxBitsOut_highBit_T_59 ? 5'hA : _maxBitsOut_highBit_T_100; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_102 = _maxBitsOut_highBit_T_58 ? 5'h9 : _maxBitsOut_highBit_T_101; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_103 = _maxBitsOut_highBit_T_57 ? 5'h8 : _maxBitsOut_highBit_T_102; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_104 = _maxBitsOut_highBit_T_56 ? 5'h7 : _maxBitsOut_highBit_T_103; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_105 = _maxBitsOut_highBit_T_55 ? 5'h6 : _maxBitsOut_highBit_T_104; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_106 = _maxBitsOut_highBit_T_54 ? 5'h5 : _maxBitsOut_highBit_T_105; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_107 = _maxBitsOut_highBit_T_53 ? 5'h4 : _maxBitsOut_highBit_T_106; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_108 = _maxBitsOut_highBit_T_52 ? 5'h3 : _maxBitsOut_highBit_T_107; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_109 = _maxBitsOut_highBit_T_51 ? 5'h2 : _maxBitsOut_highBit_T_108; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_110 = _maxBitsOut_highBit_T_50 ? 5'h1 : _maxBitsOut_highBit_T_109; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_111 = _maxBitsOut_highBit_T_49 ? 5'h0 : _maxBitsOut_highBit_T_110; // @[OneHot.scala:48:45] wire [5:0] _maxBitsOut_highBit_T_112 = 6'h1F - {1'h0, _maxBitsOut_highBit_T_111}; // @[Mux.scala:50:70] wire [4:0] maxBitsOut_highBit = _maxBitsOut_highBit_T_112[4:0]; // @[FSECompressorDicBuilder.scala:52:24] wire [5:0] _maxBitsOut_T_2 = 6'h6 - {1'h0, maxBitsOut_highBit}; // @[FSECompressorDicBuilder.scala:52:24, :777:39] wire [4:0] maxBitsOut = _maxBitsOut_T_2[4:0]; // @[FSECompressorDicBuilder.scala:777:39] wire [3:0] _minStatePlus_T = maxBitsOut[3:0]; // @[FSECompressorDicBuilder.scala:777:39, :778:51] wire [46:0] minStatePlus = {15'h0, normCount} << _minStatePlus_T; // @[FSECompressorDicBuilder.scala:415:23, :778:{38,51}] wire [35:0] _ll_symbolTTDeltaNbBits_T = {15'h0, maxBitsOut, 16'h0}; // @[FSECompressorDicBuilder.scala:777:39, :779:53] wire [47:0] _ll_symbolTTDeltaNbBits_T_1 = {12'h0, _ll_symbolTTDeltaNbBits_T} - {1'h0, minStatePlus}; // @[FSECompressorDicBuilder.scala:778:38, :779:{53,62}] wire [46:0] _ll_symbolTTDeltaNbBits_T_2 = _ll_symbolTTDeltaNbBits_T_1[46:0]; // @[FSECompressorDicBuilder.scala:779:62] wire [32:0] _ll_symbolTTDeltaFindState_T_3 = _GEN_311 - _GEN_312; // @[FSECompressorDicBuilder.scala:774:54, :777:65, :780:54] wire [31:0] _ll_symbolTTDeltaFindState_T_4 = _ll_symbolTTDeltaFindState_T_3[31:0]; // @[FSECompressorDicBuilder.scala:780:54] wire [31:0] _ll_symbolTTDeltaFindState_T_5 = _ll_symbolTTDeltaFindState_T_4; // @[FSECompressorDicBuilder.scala:780:{54,67}] wire [32:0] _ll_total_T_2 = _GEN_311 + _GEN_312; // @[FSECompressorDicBuilder.scala:774:54, :777:65, :781:30] wire [31:0] _ll_total_T_3 = _ll_total_T_2[31:0]; // @[FSECompressorDicBuilder.scala:781:30] wire _T_2396 = dicBuilderState == 4'h7; // @[FSECompressorDicBuilder.scala:156:32, :551:28] wire _GEN_313 = ~(\|dicBuilderState) \| _T_839 \| _T_846 \| _T_1371 \| _T_1559 \| _T_2379 \| _T_2386; // @[FSECompressorDicBuilder.scala:156:32, :198:25, :316:25, :494:31, :551:28] wire _T_2400 = symbol < alphabetSize & (\|(remaining[31:1])); // @[FSECompressorDicBuilder.scala:463:26, :465:23, :466:42, :799:{23,39,53}] wire [63:0] _GEN_314 = {16'h0, bitStream[63:16]}; // @[FSECompressorDicBuilder.scala:468:26, :803:38] wire [63:0] _bitStream_T; // @[FSECompressorDicBuilder.scala:803:38] assign _bitStream_T = _GEN_314; // @[FSECompressorDicBuilder.scala:803:38] wire [63:0] _bitStream_T_1; // @[FSECompressorDicBuilder.scala:816:38] assign _bitStream_T_1 = _GEN_314; // @[FSECompressorDicBuilder.scala:803:38, :816:38] wire [7:0] _GEN_315 = {1'h0, bitCount}; // @[FSECompressorDicBuilder.scala:469:25, :804:36] wire [7:0] _bitCount_T = _GEN_315 - 8'h10; // @[FSECompressorDicBuilder.scala:804:36] wire [6:0] _bitCount_T_1 = _bitCount_T[6:0]; // @[FSECompressorDicBuilder.scala:804:36] reg [63:0] loginfo_cycles_339; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_678 = {1'h0, loginfo_cycles_339} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_679 = _loginfo_cycles_T_678[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_340; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_680 = {1'h0, loginfo_cycles_340} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_681 = _loginfo_cycles_T_680[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_341; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_682 = {1'h0, loginfo_cycles_341} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_683 = _loginfo_cycles_T_682[63:0]; // @[Util.scala:19:38] wire _GEN_316 = writeBitStream \| writeBitStreamPrev0; // @[FSECompressorDicBuilder.scala:470:31, :476:36, :481:36, :800:32, :812:46, :813:45, :823:46] reg [63:0] loginfo_cycles_342; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_684 = {1'h0, loginfo_cycles_342} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_685 = _loginfo_cycles_T_684[63:0]; // @[Util.scala:19:38] wire [4:0] _cur_norm_count_T = symbol[4:0]; // @[FSECompressorDicBuilder.scala:465:23] wire [4:0] _count_T = symbol[4:0]; // @[FSECompressorDicBuilder.scala:465:23] reg [63:0] loginfo_cycles_343; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_686 = {1'h0, loginfo_cycles_343} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_687 = _loginfo_cycles_T_686[63:0]; // @[Util.scala:19:38] wire [32:0] _GEN_317 = {1'h0, symbol}; // @[FSECompressorDicBuilder.scala:465:23, :835:34] wire [32:0] _symbol_T = _GEN_317 + 33'h1; // @[FSECompressorDicBuilder.scala:835:34] wire [31:0] _symbol_T_1 = _symbol_T[31:0]; // @[FSECompressorDicBuilder.scala:835:34] wire [32:0] _GEN_318 = {1'h0, start}; // @[FSECompressorDicBuilder.scala:471:22, :842:37] wire [32:0] _start_T = _GEN_318 + 33'h18; // @[FSECompressorDicBuilder.scala:842:37, :843:32] wire [31:0] _start_T_1 = _start_T[31:0]; // @[FSECompressorDicBuilder.scala:843:32] wire [142:0] _bitStream_T_2 = 143'hFFFF << bitCount; // @[FSECompressorDicBuilder.scala:469:25, :844:64] wire [143:0] _bitStream_T_3 = {80'h0, bitStream} + {1'h0, _bitStream_T_2}; // @[FSECompressorDicBuilder.scala:468:26, :844:{40,64}] wire [142:0] _bitStream_T_4 = _bitStream_T_3[142:0]; // @[FSECompressorDicBuilder.scala:844:40] reg [63:0] loginfo_cycles_344; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_688 = {1'h0, loginfo_cycles_344} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_689 = _loginfo_cycles_T_688[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_345; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_690 = {1'h0, loginfo_cycles_345} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_691 = _loginfo_cycles_T_690[63:0]; // @[Util.scala:19:38] wire [32:0] _start_T_2 = _GEN_318 + 33'h3; // @[FSECompressorDicBuilder.scala:842:37, :852:37, :853:32] wire [31:0] _start_T_3 = _start_T_2[31:0]; // @[FSECompressorDicBuilder.scala:853:32] wire [128:0] _bitStream_T_5 = 129'h3 << bitCount; // @[FSECompressorDicBuilder.scala:469:25, :854:47] wire [129:0] _bitStream_T_6 = {66'h0, bitStream} + {1'h0, _bitStream_T_5}; // @[FSECompressorDicBuilder.scala:468:26, :854:{40,47}] wire [128:0] _bitStream_T_7 = _bitStream_T_6[128:0]; // @[FSECompressorDicBuilder.scala:854:40] wire [7:0] _GEN_319 = _GEN_315 + 8'h2; // @[FSECompressorDicBuilder.scala:804:36, :855:38] wire [7:0] _bitCount_T_2; // @[FSECompressorDicBuilder.scala:855:38] assign _bitCount_T_2 = _GEN_319; // @[FSECompressorDicBuilder.scala:855:38] wire [7:0] _bitCount_T_4; // @[FSECompressorDicBuilder.scala:863:36] assign _bitCount_T_4 = _GEN_319; // @[FSECompressorDicBuilder.scala:855:38, :863:36] wire [6:0] _bitCount_T_3 = _bitCount_T_2[6:0]; // @[FSECompressorDicBuilder.scala:855:38] reg [63:0] loginfo_cycles_346; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_692 = {1'h0, loginfo_cycles_346} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_693 = _loginfo_cycles_T_692[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_347; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_694 = {1'h0, loginfo_cycles_347} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_695 = _loginfo_cycles_T_694[63:0]; // @[Util.scala:19:38] wire [32:0] _bitStream_T_8 = _GEN_317 - _GEN_318; // @[FSECompressorDicBuilder.scala:835:34, :842:37, :862:49] wire [31:0] _bitStream_T_9 = _bitStream_T_8[31:0]; // @[FSECompressorDicBuilder.scala:862:49] wire [158:0] _bitStream_T_10 = {127'h0, _bitStream_T_9} << bitCount; // @[FSECompressorDicBuilder.scala:469:25, :844:64, :862:{49,58}] wire [159:0] _GEN_320 = {96'h0, bitStream}; // @[FSECompressorDicBuilder.scala:468:26, :862:38] wire [159:0] _bitStream_T_11 = _GEN_320 + {1'h0, _bitStream_T_10}; // @[FSECompressorDicBuilder.scala:862:{38,58}] wire [158:0] _bitStream_T_12 = _bitStream_T_11[158:0]; // @[FSECompressorDicBuilder.scala:862:38] wire [6:0] _bitCount_T_5 = _bitCount_T_4[6:0]; // @[FSECompressorDicBuilder.scala:863:36] reg [63:0] loginfo_cycles_348; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_696 = {1'h0, loginfo_cycles_348} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_697 = _loginfo_cycles_T_696[63:0]; // @[Util.scala:19:38] wire [32:0] _symbol_T_2 = _GEN_317 + 33'h1; // @[FSECompressorDicBuilder.scala:835:34, :878:30] wire [31:0] _symbol_T_3 = _symbol_T_2[31:0]; // @[FSECompressorDicBuilder.scala:878:30] wire [32:0] _max_T = {threshold, 1'h0}; // @[FSECompressorDicBuilder.scala:464:26, :879:35] wire [33:0] _max_T_1 = {1'h0, _max_T} - 34'h1; // @[FSECompressorDicBuilder.scala:879:{35,43}] wire [32:0] _max_T_2 = _max_T_1[32:0]; // @[FSECompressorDicBuilder.scala:879:43] wire [33:0] _max_T_3 = {1'h0, _max_T_2} - {2'h0, remaining}; // @[FSECompressorDicBuilder.scala:463:26, :879:{43,50}] wire [32:0] max = _max_T_3[32:0]; // @[FSECompressorDicBuilder.scala:879:50] wire [32:0] _nxt_remaining_T = {1'h0, remaining} - {17'h0, _GEN_199[_count_T]}; // @[FSECompressorDicBuilder.scala:416:13, :463:26, :882:43] wire [31:0] nxt_remaining = _nxt_remaining_T[31:0]; // @[FSECompressorDicBuilder.scala:882:43] wire _GEN_321 = writeBitStream \| writeBitStreamPrev0 \| previousIs0; // @[FSECompressorDicBuilder.scala:467:28, :470:31, :476:36, :494:31, :800:32, :813:45, :824:37, :883:23] wire [16:0] _count1_T = {1'h0, _GEN_199[_count_T]} + 17'h1; // @[FSECompressorDicBuilder.scala:416:13, :882:43, :885:32] wire [15:0] count1 = _count1_T[15:0]; // @[FSECompressorDicBuilder.scala:885:32] wire _count1_max_T = {16'h0, count1} >= threshold; // @[FSECompressorDicBuilder.scala:464:26, :885:32, :886:41] wire [33:0] _count1_max_T_1 = {18'h0, count1} + {1'h0, max}; // @[FSECompressorDicBuilder.scala:879:50, :885:32, :886:62] wire [32:0] _count1_max_T_2 = _count1_max_T_1[32:0]; // @[FSECompressorDicBuilder.scala:886:62] wire [32:0] count1_max = _count1_max_T ? _count1_max_T_2 : {17'h0, count1}; // @[FSECompressorDicBuilder.scala:885:32, :886:{33,41,62}] wire [32:0] _GEN_322 = {1'h0, nbBits}; // @[FSECompressorDicBuilder.scala:462:23, :887:41] wire [32:0] _nxt_bitCount_T = {26'h0, bitCount} + _GEN_322; // @[FSECompressorDicBuilder.scala:469:25, :887:41] wire [31:0] _nxt_bitCount_T_1 = _nxt_bitCount_T[31:0]; // @[FSECompressorDicBuilder.scala:887:41] wire _nxt_bitCount_T_2 = count1_max < max; // @[FSECompressorDicBuilder.scala:879:50, :886:33, :887:67] wire _nxt_bitCount_T_3 = _nxt_bitCount_T_2; // @[FSECompressorDicBuilder.scala:887:{55,67}] wire [32:0] _nxt_bitCount_T_4 = {1'h0, _nxt_bitCount_T_1} - {32'h0, _nxt_bitCount_T_3}; // @[FSECompressorDicBuilder.scala:887:{41,50,55}] wire [31:0] nxt_bitCount = _nxt_bitCount_T_4[31:0]; // @[FSECompressorDicBuilder.scala:887:50] wire [159:0] _bitStream_T_13 = {127'h0, count1_max} << bitCount; // @[FSECompressorDicBuilder.scala:469:25, :844:64, :886:33, :888:50] wire [160:0] _bitStream_T_14 = {97'h0, bitStream} + {1'h0, _bitStream_T_13}; // @[FSECompressorDicBuilder.scala:468:26, :888:{36,50}] wire [159:0] _bitStream_T_15 = _bitStream_T_14[159:0]; // @[FSECompressorDicBuilder.scala:888:36] wire _writeBitStream_T = nxt_bitCount > 32'h10; // @[FSECompressorDicBuilder.scala:887:50, :890:44] wire _previousIs0_T = count1_max == 33'h1; // @[FSECompressorDicBuilder.scala:886:33, :892:40] reg [63:0] loginfo_cycles_349; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_698 = {1'h0, loginfo_cycles_349} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_699 = _loginfo_cycles_T_698[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_350; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_700 = {1'h0, loginfo_cycles_350} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_701 = _loginfo_cycles_T_700[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_351; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_702 = {1'h0, loginfo_cycles_351} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_703 = _loginfo_cycles_T_702[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_352; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_704 = {1'h0, loginfo_cycles_352} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_705 = _loginfo_cycles_T_704[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_353; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_706 = {1'h0, loginfo_cycles_353} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_707 = _loginfo_cycles_T_706[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_354; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_708 = {1'h0, loginfo_cycles_354} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_709 = _loginfo_cycles_T_708[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_355; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_710 = {1'h0, loginfo_cycles_355} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_711 = _loginfo_cycles_T_710[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_356; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_712 = {1'h0, loginfo_cycles_356} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_713 = _loginfo_cycles_T_712[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_357; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_714 = {1'h0, loginfo_cycles_357} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_715 = _loginfo_cycles_T_714[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_358; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_716 = {1'h0, loginfo_cycles_358} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_717 = _loginfo_cycles_T_716[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_359; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_718 = {1'h0, loginfo_cycles_359} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_719 = _loginfo_cycles_T_718[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_360; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_720 = {1'h0, loginfo_cycles_360} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_721 = _loginfo_cycles_T_720[63:0]; // @[Util.scala:19:38] wire _shifted_threshold_small_or_eq_remaining_0_T = nxt_remaining < shifted_thresholds_0; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_0_T_1 = _shifted_threshold_small_or_eq_remaining_0_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] wire _GEN_323 = _GEN_313 \| ~_T_2396 \| ~write_header_started \| ~_T_2400 \| _GEN_321; // @[FSECompressorDicBuilder.scala:461:37, :490:57, :494:31, :551:28, :791:36, :799:{39,61}, :800:32, :813:45, :824:37, :883:23] assign shifted_threshold_small_or_eq_remaining_0 = _GEN_323 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_0_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_1_T = nxt_remaining < shifted_thresholds_1; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_1_T_1 = _shifted_threshold_small_or_eq_remaining_1_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_1 = _GEN_323 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_1_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_2_T = nxt_remaining < shifted_thresholds_2; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_2_T_1 = _shifted_threshold_small_or_eq_remaining_2_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_2 = _GEN_323 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_2_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_3_T = nxt_remaining < shifted_thresholds_3; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_3_T_1 = _shifted_threshold_small_or_eq_remaining_3_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_3 = _GEN_323 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_3_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_4_T = nxt_remaining < shifted_thresholds_4; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_4_T_1 = _shifted_threshold_small_or_eq_remaining_4_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_4 = _GEN_323 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_4_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_5_T = nxt_remaining < shifted_thresholds_5; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_5_T_1 = _shifted_threshold_small_or_eq_remaining_5_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_5 = _GEN_323 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_5_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_6_T = nxt_remaining < shifted_thresholds_6; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_6_T_1 = _shifted_threshold_small_or_eq_remaining_6_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_6 = _GEN_323 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_6_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire [2:0] _threshold_T = nxt_shifted_threshold_idx[2:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nbBits_T = _GEN_322 - {1'h0, nxt_shifted_threshold_idx}; // @[FSECompressorDicBuilder.scala:491:84, :887:41, :911:30] wire [31:0] _nbBits_T_1 = _nbBits_T[31:0]; // @[FSECompressorDicBuilder.scala:911:30] wire _GEN_324 = ~_T_2400 \| writeBitStream \| writeBitStreamPrev0; // @[FSECompressorDicBuilder.scala:470:31, :476:36, :494:31, :799:{39,61}, :800:32, :810:36, :813:45, :914:34] assign io_header_writes_valid_0 = ~_GEN_313 & _T_2396 & write_header_started & _GEN_324; // @[FSECompressorDicBuilder.scala:39:7, :461:37, :479:26, :494:31, :551:28, :791:36, :799:61, :800:32, :810:36, :813:45, :914:34] assign io_header_writes_bits_data_0 = _GEN_313 \| ~(_T_2396 & write_header_started & _GEN_324) ? 256'h0 : {192'h0, bitStream}; // @[FSECompressorDicBuilder.scala:39:7, :461:37, :468:26, :480:30, :494:31, :551:28, :791:36, :799:61, :800:32, :810:36, :811:40, :813:45, :914:34] wire [7:0] _io_header_writes_bits_validbytes_T = _GEN_315 + 8'h7; // @[FSECompressorDicBuilder.scala:804:36, :916:58] wire [6:0] _io_header_writes_bits_validbytes_T_1 = _io_header_writes_bits_validbytes_T[6:0]; // @[FSECompressorDicBuilder.scala:916:58] wire [6:0] _io_header_writes_bits_validbytes_T_2 = {3'h0, _io_header_writes_bits_validbytes_T_1[6:3]}; // @[FSECompressorDicBuilder.scala:916:{58,65}] assign io_header_writes_bits_validbytes_0 = _GEN_313 \| ~(_T_2396 & write_header_started) ? 6'h0 : _T_2400 ? {4'h0, _GEN_316, 1'h0} : _io_header_writes_bits_validbytes_T_2[5:0]; // @[FSECompressorDicBuilder.scala:39:7, :461:37, :481:36, :494:31, :551:28, :791:36, :799:{39,61}, :800:32, :812:46, :813:45, :823:46, :916:{44,65}] assign io_header_writes_bits_end_of_message_0 = ~_GEN_313 & _T_2396 & write_header_started & ~_T_2400; // @[FSECompressorDicBuilder.scala:39:7, :461:37, :482:40, :494:31, :551:28, :791:36, :799:{39,61}, :919:50] wire _GEN_325 = ~(\|dicBuilderState) \| _T_839 \| _T_846 \| _T_1371 \| _T_1559 \| _T_2379 \| _T_2386 \| _T_2396; // @[FSECompressorDicBuilder.scala:156:32, :198:25, :316:25, :494:31, :551:28] reg [63:0] loginfo_cycles_361; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_722 = {1'h0, loginfo_cycles_361} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_723 = _loginfo_cycles_T_722[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_362; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_724 = {1'h0, loginfo_cycles_362} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_725 = _loginfo_cycles_T_724[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_363; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_726 = {1'h0, loginfo_cycles_363} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_727 = _loginfo_cycles_T_726[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_364; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_728 = {1'h0, loginfo_cycles_364} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_729 = _loginfo_cycles_T_728[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_365; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_730 = {1'h0, loginfo_cycles_365} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_731 = _loginfo_cycles_T_730[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_366; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_732 = {1'h0, loginfo_cycles_366} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_733 = _loginfo_cycles_T_732[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_367; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_734 = {1'h0, loginfo_cycles_367} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_735 = _loginfo_cycles_T_734[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_368; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_736 = {1'h0, loginfo_cycles_368} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_737 = _loginfo_cycles_T_736[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_369; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_738 = {1'h0, loginfo_cycles_369} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_739 = _loginfo_cycles_T_738[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_370; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_740 = {1'h0, loginfo_cycles_370} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_741 = _loginfo_cycles_T_740[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_371; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_742 = {1'h0, loginfo_cycles_371} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_743 = _loginfo_cycles_T_742[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_372; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_744 = {1'h0, loginfo_cycles_372} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_745 = _loginfo_cycles_T_744[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_373; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_746 = {1'h0, loginfo_cycles_373} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_747 = _loginfo_cycles_T_746[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_374; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_748 = {1'h0, loginfo_cycles_374} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_749 = _loginfo_cycles_T_748[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_375; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_750 = {1'h0, loginfo_cycles_375} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_751 = _loginfo_cycles_T_750[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_376; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_752 = {1'h0, loginfo_cycles_376} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_753 = _loginfo_cycles_T_752[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_377; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_754 = {1'h0, loginfo_cycles_377} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_755 = _loginfo_cycles_T_754[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_378; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_756 = {1'h0, loginfo_cycles_378} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_757 = _loginfo_cycles_T_756[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_379; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_758 = {1'h0, loginfo_cycles_379} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_759 = _loginfo_cycles_T_758[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_380; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_760 = {1'h0, loginfo_cycles_380} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_761 = _loginfo_cycles_T_760[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_381; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_762 = {1'h0, loginfo_cycles_381} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_763 = _loginfo_cycles_T_762[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_382; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_764 = {1'h0, loginfo_cycles_382} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_765 = _loginfo_cycles_T_764[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_383; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_766 = {1'h0, loginfo_cycles_383} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_767 = _loginfo_cycles_T_766[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_384; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_768 = {1'h0, loginfo_cycles_384} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_769 = _loginfo_cycles_T_768[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_385; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_770 = {1'h0, loginfo_cycles_385} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_771 = _loginfo_cycles_T_770[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_386; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_772 = {1'h0, loginfo_cycles_386} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_773 = _loginfo_cycles_T_772[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_387; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_774 = {1'h0, loginfo_cycles_387} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_775 = _loginfo_cycles_T_774[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_388; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_776 = {1'h0, loginfo_cycles_388} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_777 = _loginfo_cycles_T_776[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_389; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_778 = {1'h0, loginfo_cycles_389} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_779 = _loginfo_cycles_T_778[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_390; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_780 = {1'h0, loginfo_cycles_390} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_781 = _loginfo_cycles_T_780[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_391; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_782 = {1'h0, loginfo_cycles_391} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_783 = _loginfo_cycles_T_782[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_392; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_784 = {1'h0, loginfo_cycles_392} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_785 = _loginfo_cycles_T_784[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_393; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_786 = {1'h0, loginfo_cycles_393} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_787 = _loginfo_cycles_T_786[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_394; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_788 = {1'h0, loginfo_cycles_394} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_789 = _loginfo_cycles_T_788[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_395; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_790 = {1'h0, loginfo_cycles_395} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_791 = _loginfo_cycles_T_790[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_396; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_792 = {1'h0, loginfo_cycles_396} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_793 = _loginfo_cycles_T_792[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_397; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_794 = {1'h0, loginfo_cycles_397} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_795 = _loginfo_cycles_T_794[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_398; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_796 = {1'h0, loginfo_cycles_398} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_797 = _loginfo_cycles_T_796[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_399; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_798 = {1'h0, loginfo_cycles_399} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_799 = _loginfo_cycles_T_798[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_400; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_800 = {1'h0, loginfo_cycles_400} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_801 = _loginfo_cycles_T_800[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_401; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_802 = {1'h0, loginfo_cycles_401} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_803 = _loginfo_cycles_T_802[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_402; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_804 = {1'h0, loginfo_cycles_402} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_805 = _loginfo_cycles_T_804[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_403; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_806 = {1'h0, loginfo_cycles_403} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_807 = _loginfo_cycles_T_806[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_404; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_808 = {1'h0, loginfo_cycles_404} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_809 = _loginfo_cycles_T_808[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_405; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_810 = {1'h0, loginfo_cycles_405} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_811 = _loginfo_cycles_T_810[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_406; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_812 = {1'h0, loginfo_cycles_406} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_813 = _loginfo_cycles_T_812[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_407; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_814 = {1'h0, loginfo_cycles_407} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_815 = _loginfo_cycles_T_814[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_408; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_816 = {1'h0, loginfo_cycles_408} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_817 = _loginfo_cycles_T_816[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_409; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_818 = {1'h0, loginfo_cycles_409} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_819 = _loginfo_cycles_T_818[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_410; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_820 = {1'h0, loginfo_cycles_410} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_821 = _loginfo_cycles_T_820[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_411; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_822 = {1'h0, loginfo_cycles_411} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_823 = _loginfo_cycles_T_822[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_412; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_824 = {1'h0, loginfo_cycles_412} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_825 = _loginfo_cycles_T_824[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_413; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_826 = {1'h0, loginfo_cycles_413} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_827 = _loginfo_cycles_T_826[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_414; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_828 = {1'h0, loginfo_cycles_414} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_829 = _loginfo_cycles_T_828[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_415; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_830 = {1'h0, loginfo_cycles_415} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_831 = _loginfo_cycles_T_830[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_416; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_832 = {1'h0, loginfo_cycles_416} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_833 = _loginfo_cycles_T_832[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_417; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_834 = {1'h0, loginfo_cycles_417} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_835 = _loginfo_cycles_T_834[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_418; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_836 = {1'h0, loginfo_cycles_418} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_837 = _loginfo_cycles_T_836[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_419; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_838 = {1'h0, loginfo_cycles_419} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_839 = _loginfo_cycles_T_838[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_420; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_840 = {1'h0, loginfo_cycles_420} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_841 = _loginfo_cycles_T_840[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_421; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_842 = {1'h0, loginfo_cycles_421} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_843 = _loginfo_cycles_T_842[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_422; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_844 = {1'h0, loginfo_cycles_422} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_845 = _loginfo_cycles_T_844[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_423; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_846 = {1'h0, loginfo_cycles_423} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_847 = _loginfo_cycles_T_846[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_424; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_848 = {1'h0, loginfo_cycles_424} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_849 = _loginfo_cycles_T_848[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_425; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_850 = {1'h0, loginfo_cycles_425} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_851 = _loginfo_cycles_T_850[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_426; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_852 = {1'h0, loginfo_cycles_426} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_853 = _loginfo_cycles_T_852[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_427; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_854 = {1'h0, loginfo_cycles_427} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_855 = _loginfo_cycles_T_854[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_428; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_856 = {1'h0, loginfo_cycles_428} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_857 = _loginfo_cycles_T_856[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_429; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_858 = {1'h0, loginfo_cycles_429} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_859 = _loginfo_cycles_T_858[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_430; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_860 = {1'h0, loginfo_cycles_430} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_861 = _loginfo_cycles_T_860[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_431; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_862 = {1'h0, loginfo_cycles_431} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_863 = _loginfo_cycles_T_862[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_432; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_864 = {1'h0, loginfo_cycles_432} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_865 = _loginfo_cycles_T_864[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_433; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_866 = {1'h0, loginfo_cycles_433} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_867 = _loginfo_cycles_T_866[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_434; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_868 = {1'h0, loginfo_cycles_434} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_869 = _loginfo_cycles_T_868[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_435; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_870 = {1'h0, loginfo_cycles_435} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_871 = _loginfo_cycles_T_870[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_436; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_872 = {1'h0, loginfo_cycles_436} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_873 = _loginfo_cycles_T_872[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_437; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_874 = {1'h0, loginfo_cycles_437} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_875 = _loginfo_cycles_T_874[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_438; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_876 = {1'h0, loginfo_cycles_438} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_877 = _loginfo_cycles_T_876[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_439; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_878 = {1'h0, loginfo_cycles_439} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_879 = _loginfo_cycles_T_878[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_440; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_880 = {1'h0, loginfo_cycles_440} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_881 = _loginfo_cycles_T_880[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_441; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_882 = {1'h0, loginfo_cycles_441} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_883 = _loginfo_cycles_T_882[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_442; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_884 = {1'h0, loginfo_cycles_442} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_885 = _loginfo_cycles_T_884[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_443; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_886 = {1'h0, loginfo_cycles_443} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_887 = _loginfo_cycles_T_886[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_444; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_888 = {1'h0, loginfo_cycles_444} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_889 = _loginfo_cycles_T_888[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_445; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_890 = {1'h0, loginfo_cycles_445} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_891 = _loginfo_cycles_T_890[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_446; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_892 = {1'h0, loginfo_cycles_446} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_893 = _loginfo_cycles_T_892[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_447; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_894 = {1'h0, loginfo_cycles_447} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_895 = _loginfo_cycles_T_894[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_448; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_896 = {1'h0, loginfo_cycles_448} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_897 = _loginfo_cycles_T_896[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_449; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_898 = {1'h0, loginfo_cycles_449} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_899 = _loginfo_cycles_T_898[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_450; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_900 = {1'h0, loginfo_cycles_450} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_901 = _loginfo_cycles_T_900[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_451; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_902 = {1'h0, loginfo_cycles_451} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_903 = _loginfo_cycles_T_902[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_452; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_904 = {1'h0, loginfo_cycles_452} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_905 = _loginfo_cycles_T_904[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_453; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_906 = {1'h0, loginfo_cycles_453} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_907 = _loginfo_cycles_T_906[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_454; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_908 = {1'h0, loginfo_cycles_454} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_909 = _loginfo_cycles_T_908[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_455; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_910 = {1'h0, loginfo_cycles_455} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_911 = _loginfo_cycles_T_910[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_456; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_912 = {1'h0, loginfo_cycles_456} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_913 = _loginfo_cycles_T_912[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_457; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_914 = {1'h0, loginfo_cycles_457} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_915 = _loginfo_cycles_T_914[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_458; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_916 = {1'h0, loginfo_cycles_458} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_917 = _loginfo_cycles_T_916[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_459; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_918 = {1'h0, loginfo_cycles_459} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_919 = _loginfo_cycles_T_918[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_460; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_920 = {1'h0, loginfo_cycles_460} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_921 = _loginfo_cycles_T_920[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_461; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_922 = {1'h0, loginfo_cycles_461} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_923 = _loginfo_cycles_T_922[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_462; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_924 = {1'h0, loginfo_cycles_462} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_925 = _loginfo_cycles_T_924[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_463; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_926 = {1'h0, loginfo_cycles_463} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_927 = _loginfo_cycles_T_926[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_464; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_928 = {1'h0, loginfo_cycles_464} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_929 = _loginfo_cycles_T_928[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_465; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_930 = {1'h0, loginfo_cycles_465} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_931 = _loginfo_cycles_T_930[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_466; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_932 = {1'h0, loginfo_cycles_466} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_933 = _loginfo_cycles_T_932[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_467; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_934 = {1'h0, loginfo_cycles_467} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_935 = _loginfo_cycles_T_934[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_468; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_936 = {1'h0, loginfo_cycles_468} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_937 = _loginfo_cycles_T_936[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_469; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_938 = {1'h0, loginfo_cycles_469} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_939 = _loginfo_cycles_T_938[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_470; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_940 = {1'h0, loginfo_cycles_470} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_941 = _loginfo_cycles_T_940[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_471; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_942 = {1'h0, loginfo_cycles_471} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_943 = _loginfo_cycles_T_942[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_472; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_944 = {1'h0, loginfo_cycles_472} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_945 = _loginfo_cycles_T_944[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_473; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_946 = {1'h0, loginfo_cycles_473} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_947 = _loginfo_cycles_T_946[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_474; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_948 = {1'h0, loginfo_cycles_474} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_949 = _loginfo_cycles_T_948[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_475; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_950 = {1'h0, loginfo_cycles_475} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_951 = _loginfo_cycles_T_950[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_476; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_952 = {1'h0, loginfo_cycles_476} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_953 = _loginfo_cycles_T_952[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_477; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_954 = {1'h0, loginfo_cycles_477} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_955 = _loginfo_cycles_T_954[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_478; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_956 = {1'h0, loginfo_cycles_478} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_957 = _loginfo_cycles_T_956[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_479; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_958 = {1'h0, loginfo_cycles_479} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_959 = _loginfo_cycles_T_958[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_480; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_960 = {1'h0, loginfo_cycles_480} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_961 = _loginfo_cycles_T_960[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_481; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_962 = {1'h0, loginfo_cycles_481} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_963 = _loginfo_cycles_T_962[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_482; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_964 = {1'h0, loginfo_cycles_482} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_965 = _loginfo_cycles_T_964[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_483; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_966 = {1'h0, loginfo_cycles_483} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_967 = _loginfo_cycles_T_966[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_484; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_968 = {1'h0, loginfo_cycles_484} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_969 = _loginfo_cycles_T_968[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_485; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_970 = {1'h0, loginfo_cycles_485} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_971 = _loginfo_cycles_T_970[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_486; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_972 = {1'h0, loginfo_cycles_486} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_973 = _loginfo_cycles_T_972[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_487; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_974 = {1'h0, loginfo_cycles_487} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_975 = _loginfo_cycles_T_974[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_488; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_976 = {1'h0, loginfo_cycles_488} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_977 = _loginfo_cycles_T_976[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_489; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_978 = {1'h0, loginfo_cycles_489} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_979 = _loginfo_cycles_T_978[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_490; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_980 = {1'h0, loginfo_cycles_490} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_981 = _loginfo_cycles_T_980[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_491; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_982 = {1'h0, loginfo_cycles_491} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_983 = _loginfo_cycles_T_982[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_492; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_984 = {1'h0, loginfo_cycles_492} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_985 = _loginfo_cycles_T_984[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_493; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_986 = {1'h0, loginfo_cycles_493} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_987 = _loginfo_cycles_T_986[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_494; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_988 = {1'h0, loginfo_cycles_494} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_989 = _loginfo_cycles_T_988[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_495; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_990 = {1'h0, loginfo_cycles_495} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_991 = _loginfo_cycles_T_990[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_496; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_992 = {1'h0, loginfo_cycles_496} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_993 = _loginfo_cycles_T_992[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_497; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_994 = {1'h0, loginfo_cycles_497} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_995 = _loginfo_cycles_T_994[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_498; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_996 = {1'h0, loginfo_cycles_498} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_997 = _loginfo_cycles_T_996[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_499; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_998 = {1'h0, loginfo_cycles_499} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_999 = _loginfo_cycles_T_998[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_500; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1000 = {1'h0, loginfo_cycles_500} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1001 = _loginfo_cycles_T_1000[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_501; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1002 = {1'h0, loginfo_cycles_501} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1003 = _loginfo_cycles_T_1002[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_502; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1004 = {1'h0, loginfo_cycles_502} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1005 = _loginfo_cycles_T_1004[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_503; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1006 = {1'h0, loginfo_cycles_503} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1007 = _loginfo_cycles_T_1006[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_504; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1008 = {1'h0, loginfo_cycles_504} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1009 = _loginfo_cycles_T_1008[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_505; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1010 = {1'h0, loginfo_cycles_505} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1011 = _loginfo_cycles_T_1010[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_506; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1012 = {1'h0, loginfo_cycles_506} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1013 = _loginfo_cycles_T_1012[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_507; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1014 = {1'h0, loginfo_cycles_507} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1015 = _loginfo_cycles_T_1014[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_508; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1016 = {1'h0, loginfo_cycles_508} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1017 = _loginfo_cycles_T_1016[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_509; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1018 = {1'h0, loginfo_cycles_509} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1019 = _loginfo_cycles_T_1018[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_510; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1020 = {1'h0, loginfo_cycles_510} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1021 = _loginfo_cycles_T_1020[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_511; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1022 = {1'h0, loginfo_cycles_511} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1023 = _loginfo_cycles_T_1022[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_512; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1024 = {1'h0, loginfo_cycles_512} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1025 = _loginfo_cycles_T_1024[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_513; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1026 = {1'h0, loginfo_cycles_513} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1027 = _loginfo_cycles_T_1026[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_514; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1028 = {1'h0, loginfo_cycles_514} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1029 = _loginfo_cycles_T_1028[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_515; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1030 = {1'h0, loginfo_cycles_515} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1031 = _loginfo_cycles_T_1030[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_516; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1032 = {1'h0, loginfo_cycles_516} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1033 = _loginfo_cycles_T_1032[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_517; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1034 = {1'h0, loginfo_cycles_517} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1035 = _loginfo_cycles_T_1034[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_518; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1036 = {1'h0, loginfo_cycles_518} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1037 = _loginfo_cycles_T_1036[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_519; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1038 = {1'h0, loginfo_cycles_519} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1039 = _loginfo_cycles_T_1038[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_520; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1040 = {1'h0, loginfo_cycles_520} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1041 = _loginfo_cycles_T_1040[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_521; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1042 = {1'h0, loginfo_cycles_521} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1043 = _loginfo_cycles_T_1042[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_522; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1044 = {1'h0, loginfo_cycles_522} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1045 = _loginfo_cycles_T_1044[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_523; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1046 = {1'h0, loginfo_cycles_523} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1047 = _loginfo_cycles_T_1046[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_524; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1048 = {1'h0, loginfo_cycles_524} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1049 = _loginfo_cycles_T_1048[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_525; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1050 = {1'h0, loginfo_cycles_525} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1051 = _loginfo_cycles_T_1050[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_526; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1052 = {1'h0, loginfo_cycles_526} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1053 = _loginfo_cycles_T_1052[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_527; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1054 = {1'h0, loginfo_cycles_527} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1055 = _loginfo_cycles_T_1054[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_528; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1056 = {1'h0, loginfo_cycles_528} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1057 = _loginfo_cycles_T_1056[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_529; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1058 = {1'h0, loginfo_cycles_529} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1059 = _loginfo_cycles_T_1058[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_530; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1060 = {1'h0, loginfo_cycles_530} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1061 = _loginfo_cycles_T_1060[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_531; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1062 = {1'h0, loginfo_cycles_531} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1063 = _loginfo_cycles_T_1062[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_532; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1064 = {1'h0, loginfo_cycles_532} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1065 = _loginfo_cycles_T_1064[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_533; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1066 = {1'h0, loginfo_cycles_533} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1067 = _loginfo_cycles_T_1066[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_534; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1068 = {1'h0, loginfo_cycles_534} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1069 = _loginfo_cycles_T_1068[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_535; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1070 = {1'h0, loginfo_cycles_535} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1071 = _loginfo_cycles_T_1070[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_536; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1072 = {1'h0, loginfo_cycles_536} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1073 = _loginfo_cycles_T_1072[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_537; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1074 = {1'h0, loginfo_cycles_537} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1075 = _loginfo_cycles_T_1074[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_538; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1076 = {1'h0, loginfo_cycles_538} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1077 = _loginfo_cycles_T_1076[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_539; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1078 = {1'h0, loginfo_cycles_539} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1079 = _loginfo_cycles_T_1078[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_540; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1080 = {1'h0, loginfo_cycles_540} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1081 = _loginfo_cycles_T_1080[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_541; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1082 = {1'h0, loginfo_cycles_541} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1083 = _loginfo_cycles_T_1082[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_542; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1084 = {1'h0, loginfo_cycles_542} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1085 = _loginfo_cycles_T_1084[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_543; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1086 = {1'h0, loginfo_cycles_543} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1087 = _loginfo_cycles_T_1086[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_544; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1088 = {1'h0, loginfo_cycles_544} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1089 = _loginfo_cycles_T_1088[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_545; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1090 = {1'h0, loginfo_cycles_545} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1091 = _loginfo_cycles_T_1090[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_546; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1092 = {1'h0, loginfo_cycles_546} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1093 = _loginfo_cycles_T_1092[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_547; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1094 = {1'h0, loginfo_cycles_547} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1095 = _loginfo_cycles_T_1094[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_548; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1096 = {1'h0, loginfo_cycles_548} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1097 = _loginfo_cycles_T_1096[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_549; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1098 = {1'h0, loginfo_cycles_549} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1099 = _loginfo_cycles_T_1098[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_550; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1100 = {1'h0, loginfo_cycles_550} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1101 = _loginfo_cycles_T_1100[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_551; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1102 = {1'h0, loginfo_cycles_551} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1103 = _loginfo_cycles_T_1102[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_552; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1104 = {1'h0, loginfo_cycles_552} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1105 = _loginfo_cycles_T_1104[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_553; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1106 = {1'h0, loginfo_cycles_553} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1107 = _loginfo_cycles_T_1106[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_554; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1108 = {1'h0, loginfo_cycles_554} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1109 = _loginfo_cycles_T_1108[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_555; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1110 = {1'h0, loginfo_cycles_555} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1111 = _loginfo_cycles_T_1110[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_556; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1112 = {1'h0, loginfo_cycles_556} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1113 = _loginfo_cycles_T_1112[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_557; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1114 = {1'h0, loginfo_cycles_557} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1115 = _loginfo_cycles_T_1114[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_558; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1116 = {1'h0, loginfo_cycles_558} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1117 = _loginfo_cycles_T_1116[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_559; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1118 = {1'h0, loginfo_cycles_559} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1119 = _loginfo_cycles_T_1118[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_560; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1120 = {1'h0, loginfo_cycles_560} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1121 = _loginfo_cycles_T_1120[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_561; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1122 = {1'h0, loginfo_cycles_561} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1123 = _loginfo_cycles_T_1122[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_562; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1124 = {1'h0, loginfo_cycles_562} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1125 = _loginfo_cycles_T_1124[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_563; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1126 = {1'h0, loginfo_cycles_563} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1127 = _loginfo_cycles_T_1126[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_564; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1128 = {1'h0, loginfo_cycles_564} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1129 = _loginfo_cycles_T_1128[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_565; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1130 = {1'h0, loginfo_cycles_565} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1131 = _loginfo_cycles_T_1130[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_566; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1132 = {1'h0, loginfo_cycles_566} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1133 = _loginfo_cycles_T_1132[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_567; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1134 = {1'h0, loginfo_cycles_567} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1135 = _loginfo_cycles_T_1134[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_568; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1136 = {1'h0, loginfo_cycles_568} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1137 = _loginfo_cycles_T_1136[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_569; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1138 = {1'h0, loginfo_cycles_569} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1139 = _loginfo_cycles_T_1138[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_570; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1140 = {1'h0, loginfo_cycles_570} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1141 = _loginfo_cycles_T_1140[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_571; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1142 = {1'h0, loginfo_cycles_571} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1143 = _loginfo_cycles_T_1142[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_572; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1144 = {1'h0, loginfo_cycles_572} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1145 = _loginfo_cycles_T_1144[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_573; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1146 = {1'h0, loginfo_cycles_573} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1147 = _loginfo_cycles_T_1146[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_574; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1148 = {1'h0, loginfo_cycles_574} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1149 = _loginfo_cycles_T_1148[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_575; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1150 = {1'h0, loginfo_cycles_575} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1151 = _loginfo_cycles_T_1150[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_576; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1152 = {1'h0, loginfo_cycles_576} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1153 = _loginfo_cycles_T_1152[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_577; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1154 = {1'h0, loginfo_cycles_577} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1155 = _loginfo_cycles_T_1154[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_578; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1156 = {1'h0, loginfo_cycles_578} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1157 = _loginfo_cycles_T_1156[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_579; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1158 = {1'h0, loginfo_cycles_579} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1159 = _loginfo_cycles_T_1158[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_580; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1160 = {1'h0, loginfo_cycles_580} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1161 = _loginfo_cycles_T_1160[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_581; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1162 = {1'h0, loginfo_cycles_581} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1163 = _loginfo_cycles_T_1162[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_582; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1164 = {1'h0, loginfo_cycles_582} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1165 = _loginfo_cycles_T_1164[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_583; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1166 = {1'h0, loginfo_cycles_583} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1167 = _loginfo_cycles_T_1166[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_584; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1168 = {1'h0, loginfo_cycles_584} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1169 = _loginfo_cycles_T_1168[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_585; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1170 = {1'h0, loginfo_cycles_585} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1171 = _loginfo_cycles_T_1170[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_586; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1172 = {1'h0, loginfo_cycles_586} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1173 = _loginfo_cycles_T_1172[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_587; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1174 = {1'h0, loginfo_cycles_587} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1175 = _loginfo_cycles_T_1174[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_588; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1176 = {1'h0, loginfo_cycles_588} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1177 = _loginfo_cycles_T_1176[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_589; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1178 = {1'h0, loginfo_cycles_589} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1179 = _loginfo_cycles_T_1178[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_590; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1180 = {1'h0, loginfo_cycles_590} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1181 = _loginfo_cycles_T_1180[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_591; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1182 = {1'h0, loginfo_cycles_591} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1183 = _loginfo_cycles_T_1182[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_592; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1184 = {1'h0, loginfo_cycles_592} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1185 = _loginfo_cycles_T_1184[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_593; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1186 = {1'h0, loginfo_cycles_593} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1187 = _loginfo_cycles_T_1186[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_594; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1188 = {1'h0, loginfo_cycles_594} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1189 = _loginfo_cycles_T_1188[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_595; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1190 = {1'h0, loginfo_cycles_595} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1191 = _loginfo_cycles_T_1190[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_596; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1192 = {1'h0, loginfo_cycles_596} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1193 = _loginfo_cycles_T_1192[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_597; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1194 = {1'h0, loginfo_cycles_597} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1195 = _loginfo_cycles_T_1194[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_598; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1196 = {1'h0, loginfo_cycles_598} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1197 = _loginfo_cycles_T_1196[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_599; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1198 = {1'h0, loginfo_cycles_599} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1199 = _loginfo_cycles_T_1198[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_600; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1200 = {1'h0, loginfo_cycles_600} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1201 = _loginfo_cycles_T_1200[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_601; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1202 = {1'h0, loginfo_cycles_601} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1203 = _loginfo_cycles_T_1202[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_602; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1204 = {1'h0, loginfo_cycles_602} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1205 = _loginfo_cycles_T_1204[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_603; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1206 = {1'h0, loginfo_cycles_603} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1207 = _loginfo_cycles_T_1206[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_604; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1208 = {1'h0, loginfo_cycles_604} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1209 = _loginfo_cycles_T_1208[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_605; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1210 = {1'h0, loginfo_cycles_605} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1211 = _loginfo_cycles_T_1210[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_606; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1212 = {1'h0, loginfo_cycles_606} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1213 = _loginfo_cycles_T_1212[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_607; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1214 = {1'h0, loginfo_cycles_607} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1215 = _loginfo_cycles_T_1214[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_608; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1216 = {1'h0, loginfo_cycles_608} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1217 = _loginfo_cycles_T_1216[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_609; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1218 = {1'h0, loginfo_cycles_609} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1219 = _loginfo_cycles_T_1218[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_610; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1220 = {1'h0, loginfo_cycles_610} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1221 = _loginfo_cycles_T_1220[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_611; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1222 = {1'h0, loginfo_cycles_611} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1223 = _loginfo_cycles_T_1222[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_612; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1224 = {1'h0, loginfo_cycles_612} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1225 = _loginfo_cycles_T_1224[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_613; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1226 = {1'h0, loginfo_cycles_613} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1227 = _loginfo_cycles_T_1226[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_614; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1228 = {1'h0, loginfo_cycles_614} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1229 = _loginfo_cycles_T_1228[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_615; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1230 = {1'h0, loginfo_cycles_615} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1231 = _loginfo_cycles_T_1230[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_616; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1232 = {1'h0, loginfo_cycles_616} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1233 = _loginfo_cycles_T_1232[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_617; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1234 = {1'h0, loginfo_cycles_617} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1235 = _loginfo_cycles_T_1234[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_618; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1236 = {1'h0, loginfo_cycles_618} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1237 = _loginfo_cycles_T_1236[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_619; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1238 = {1'h0, loginfo_cycles_619} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1239 = _loginfo_cycles_T_1238[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_620; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1240 = {1'h0, loginfo_cycles_620} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1241 = _loginfo_cycles_T_1240[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_621; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1242 = {1'h0, loginfo_cycles_621} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1243 = _loginfo_cycles_T_1242[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_622; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1244 = {1'h0, loginfo_cycles_622} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1245 = _loginfo_cycles_T_1244[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_623; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1246 = {1'h0, loginfo_cycles_623} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1247 = _loginfo_cycles_T_1246[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_624; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1248 = {1'h0, loginfo_cycles_624} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1249 = _loginfo_cycles_T_1248[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_625; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1250 = {1'h0, loginfo_cycles_625} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1251 = _loginfo_cycles_T_1250[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_626; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1252 = {1'h0, loginfo_cycles_626} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1253 = _loginfo_cycles_T_1252[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_627; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1254 = {1'h0, loginfo_cycles_627} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1255 = _loginfo_cycles_T_1254[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U \|\| codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn \|\| codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U \|\| expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 \|\| FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty \|\| floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) \| Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) \|\| helper(unswizzled, prevT) val curOK = !t.isNaN(x) \|\| x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger \| ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) \| (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL/fmv..x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) \| x, maxType) } // implement NaN unboxing and un-recoding for FS/fmv.x. def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out \| (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR \| (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) \|\| narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt \|\| (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) \|\| maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 \|\| in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B \|\| outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma \|\| cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid \|\| io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm \|\| io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx \|\| mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx \|\| ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm \|\| mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) \| (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint \|\| ex_ctrl.div \|\| ex_ctrl.sqrt \|\| (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_\|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_\|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma \|\| mem_ctrl.fastpipe \|\| mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR \|\| (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 \| memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) \|\| divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid \|\| divSqrt_wen \|\| wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) \| Mux(divSqrt_wen, divSqrt_flags, 0.U) \| Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div \|\| mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags \|\| mem_reg_valid && mem_ctrl.wflags \|\| wb_reg_valid && wb_ctrl.toint \|\| wen.orR \|\| divSqrt_inFlight) io.nack_mem := (write_port_busy \|\| divSqrt_write_port_busy \|\| divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_\|\|_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) \|\| mem_ctrl.div \|\| mem_ctrl.sqrt \|\| mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen \|\| (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) \|\| io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div \|\| divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div \|\| id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B \|\| io.keep_clock_enabled \|\| // chicken bit io.valid \|\| // ID stage req_valid \|\| // EX stage mem_reg_valid \|\| mem_cp_valid \|\| // MEM stage wb_reg_valid \|\| wb_cp_valid \|\| // WB stage wen.orR \|\| divSqrt_inFlight \|\| // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) } File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /* * Object to get the FP rounding mode out of a packed immediate. / object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /* * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) / object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File functional-unit.scala: //**************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Functional Units //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // If regfile bypassing is disabled, then the functional unit must do its own // bypassing in here on the WB stage (i.e., bypassing the io.resp.data) // // TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass? package boom.v3.exu import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ import freechips.rocketchip.tile import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR} import boom.v3.common._ import boom.v3.ifu._ import boom.v3.util._ /t * Functional unit constants / object FUConstants { // bit mask, since a given execution pipeline may support multiple functional units val FUC_SZ = 10 val FU_X = BitPat.dontCare(FUC_SZ) val FU_ALU = 1.U(FUC_SZ.W) val FU_JMP = 2.U(FUC_SZ.W) val FU_MEM = 4.U(FUC_SZ.W) val FU_MUL = 8.U(FUC_SZ.W) val FU_DIV = 16.U(FUC_SZ.W) val FU_CSR = 32.U(FUC_SZ.W) val FU_FPU = 64.U(FUC_SZ.W) val FU_FDV = 128.U(FUC_SZ.W) val FU_I2F = 256.U(FUC_SZ.W) val FU_F2I = 512.U(FUC_SZ.W) // FP stores generate data through FP F2I, and generate address through MemAddrCalc val FU_F2IMEM = 516.U(FUC_SZ.W) } import FUConstants._ /* * Class to tell the FUDecoders what units it needs to support * * @param alu support alu unit? * @param bru support br unit? * @param mem support mem unit? * @param muld support multiple div unit? * @param fpu support FP unit? * @param csr support csr writing unit? * @param fdiv support FP div unit? * @param ifpu support int to FP unit? / class SupportedFuncUnits( val alu: Boolean = false, val jmp: Boolean = false, val mem: Boolean = false, val muld: Boolean = false, val fpu: Boolean = false, val csr: Boolean = false, val fdiv: Boolean = false, val ifpu: Boolean = false) { } /* * Bundle for signals sent to the functional unit * * @param dataWidth width of the data sent to the functional unit / class FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val numOperands = 3 val rs1_data = UInt(dataWidth.W) val rs2_data = UInt(dataWidth.W) val rs3_data = UInt(dataWidth.W) // only used for FMA units val pred_data = Bool() val kill = Bool() // kill everything } /* * Bundle for the signals sent out of the function unit * * @param dataWidth data sent from the functional unit / class FuncUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val predicated = Bool() // Was this response from a predicated-off instruction val data = UInt(dataWidth.W) val fflags = new ValidIO(new FFlagsResp) val addr = UInt((vaddrBits+1).W) // only for maddr -> LSU val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc } /* * Branch resolution information given from the branch unit / class BrResolutionInfo(implicit p: Parameters) extends BoomBundle { val uop = new MicroOp val valid = Bool() val mispredict = Bool() val taken = Bool() // which direction did the branch go? val cfi_type = UInt(CFI_SZ.W) // Info for recalculating the pc for this branch val pc_sel = UInt(2.W) val jalr_target = UInt(vaddrBitsExtended.W) val target_offset = SInt() } class BrUpdateInfo(implicit p: Parameters) extends BoomBundle { // On the first cycle we get masks to kill registers val b1 = new BrUpdateMasks // On the second cycle we get indices to reset pointers val b2 = new BrResolutionInfo } class BrUpdateMasks(implicit p: Parameters) extends BoomBundle { val resolve_mask = UInt(maxBrCount.W) val mispredict_mask = UInt(maxBrCount.W) } /* * Abstract top level functional unit class that wraps a lower level hand made functional unit * * @param isPipelined is the functional unit pipelined? * @param numStages how many pipeline stages does the functional unit have * @param numBypassStages how many bypass stages does the function unit have * @param dataWidth width of the data being operated on in the functional unit * @param hasBranchUnit does this functional unit have a branch unit? / abstract class FunctionalUnit( val isPipelined: Boolean, val numStages: Int, val numBypassStages: Int, val dataWidth: Int, val isJmpUnit: Boolean = false, val isAluUnit: Boolean = false, val isMemAddrCalcUnit: Boolean = false, val needsFcsr: Boolean = false) (implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth))) val resp = (new DecoupledIO(new FuncUnitResp(dataWidth))) val brupdate = Input(new BrUpdateInfo()) val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth)))) // only used by the fpu unit val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null // only used by branch unit val brinfo = if (isAluUnit) Output(new BrResolutionInfo()) else null val get_ftq_pc = if (isJmpUnit) Flipped(new GetPCFromFtqIO()) else null val status = if (isMemAddrCalcUnit) Input(new freechips.rocketchip.rocket.MStatus()) else null // only used by memaddr calc unit val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null }) io.bypass.foreach { b => b.valid := false.B; b.bits := DontCare } io.resp.valid := false.B io.resp.bits := DontCare if (isJmpUnit) { io.get_ftq_pc.ftq_idx := DontCare } } /* * Abstract top level pipelined functional unit * * Note: this helps track which uops get killed while in intermediate stages, * but it is the job of the consumer to check for kills on the same cycle as consumption!!! * * @param numStages how many pipeline stages does the functional unit have * @param numBypassStages how many bypass stages does the function unit have * @param earliestBypassStage first stage that you can start bypassing from * @param dataWidth width of the data being operated on in the functional unit * @param hasBranchUnit does this functional unit have a branch unit? / abstract class PipelinedFunctionalUnit( numStages: Int, numBypassStages: Int, earliestBypassStage: Int, dataWidth: Int, isJmpUnit: Boolean = false, isAluUnit: Boolean = false, isMemAddrCalcUnit: Boolean = false, needsFcsr: Boolean = false )(implicit p: Parameters) extends FunctionalUnit( isPipelined = true, numStages = numStages, numBypassStages = numBypassStages, dataWidth = dataWidth, isJmpUnit = isJmpUnit, isAluUnit = isAluUnit, isMemAddrCalcUnit = isMemAddrCalcUnit, needsFcsr = needsFcsr) { // Pipelined functional unit is always ready. io.req.ready := true.B if (numStages > 0) { val r_valids = RegInit(VecInit(Seq.fill(numStages) { false.B })) val r_uops = Reg(Vec(numStages, new MicroOp())) // handle incoming request r_valids(0) := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill r_uops(0) := io.req.bits.uop r_uops(0).br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop) // handle middle of the pipeline for (i <- 1 until numStages) { r_valids(i) := r_valids(i-1) && !IsKilledByBranch(io.brupdate, r_uops(i-1)) && !io.req.bits.kill r_uops(i) := r_uops(i-1) r_uops(i).br_mask := GetNewBrMask(io.brupdate, r_uops(i-1)) if (numBypassStages > 0) { io.bypass(i-1).bits.uop := r_uops(i-1) } } // handle outgoing (branch could still kill it) // consumer must also check for pipeline flushes (kills) io.resp.valid := r_valids(numStages-1) && !IsKilledByBranch(io.brupdate, r_uops(numStages-1)) io.resp.bits.predicated := false.B io.resp.bits.uop := r_uops(numStages-1) io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_uops(numStages-1)) // bypassing (TODO allow bypass vector to have a different size from numStages) if (numBypassStages > 0 && earliestBypassStage == 0) { io.bypass(0).bits.uop := io.req.bits.uop for (i <- 1 until numBypassStages) { io.bypass(i).bits.uop := r_uops(i-1) } } } else { require (numStages == 0) // pass req straight through to response // valid doesn't check kill signals, let consumer deal with it. // The LSU already handles it and this hurts critical path. io.resp.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) io.resp.bits.predicated := false.B io.resp.bits.uop := io.req.bits.uop io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop) } } /* * Functional unit that wraps RocketChips ALU * * @param isBranchUnit is this a branch unit? * @param numStages how many pipeline stages does the functional unit have * @param dataWidth width of the data being operated on in the functional unit / class ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = numStages, numBypassStages = numStages, isAluUnit = true, earliestBypassStage = 0, dataWidth = dataWidth, isJmpUnit = isJmpUnit) with boom.v3.ifu.HasBoomFrontendParameters { val uop = io.req.bits.uop // immediate generation val imm_xprlen = ImmGen(uop.imm_packed, uop.ctrl.imm_sel) // operand 1 select var op1_data: UInt = null if (isJmpUnit) { // Get the uop PC for jumps val block_pc = AlignPCToBoundary(io.get_ftq_pc.pc, icBlockBytes) val uop_pc = (block_pc \| uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U) op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data, Mux(uop.ctrl.op1_sel.asUInt === OP1_PC , Sext(uop_pc, xLen), 0.U)) } else { op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data, 0.U) } // operand 2 select val op2_data = Mux(uop.ctrl.op2_sel === OP2_IMM, Sext(imm_xprlen.asUInt, xLen), Mux(uop.ctrl.op2_sel === OP2_IMMC, io.req.bits.uop.prs1(4,0), Mux(uop.ctrl.op2_sel === OP2_RS2 , io.req.bits.rs2_data, Mux(uop.ctrl.op2_sel === OP2_NEXT, Mux(uop.is_rvc, 2.U, 4.U), 0.U)))) val alu = Module(new freechips.rocketchip.rocket.ALU()) alu.io.in1 := op1_data.asUInt alu.io.in2 := op2_data.asUInt alu.io.fn := uop.ctrl.op_fcn alu.io.dw := uop.ctrl.fcn_dw // Did I just get killed by the previous cycle's branch, // or by a flush pipeline? val killed = WireInit(false.B) when (io.req.bits.kill \|\| IsKilledByBranch(io.brupdate, uop)) { killed := true.B } val rs1 = io.req.bits.rs1_data val rs2 = io.req.bits.rs2_data val br_eq = (rs1 === rs2) val br_ltu = (rs1.asUInt < rs2.asUInt) val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu \| rs1(xLen-1) & ~rs2(xLen-1)).asBool val pc_sel = MuxLookup(uop.ctrl.br_type, PC_PLUS4)( Seq( BR_N -> PC_PLUS4, BR_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4), BR_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4), BR_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4), BR_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4), BR_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4), BR_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4), BR_J -> PC_BRJMP, BR_JR -> PC_JALR )) val is_taken = io.req.valid && !killed && (uop.is_br \|\| uop.is_jalr \|\| uop.is_jal) && (pc_sel =/= PC_PLUS4) // "mispredict" means that a branch has been resolved and it must be killed val mispredict = WireInit(false.B) val is_br = io.req.valid && !killed && uop.is_br && !uop.is_sfb val is_jal = io.req.valid && !killed && uop.is_jal val is_jalr = io.req.valid && !killed && uop.is_jalr when (is_br \|\| is_jalr) { if (!isJmpUnit) { assert (pc_sel =/= PC_JALR) } when (pc_sel === PC_PLUS4) { mispredict := uop.taken } when (pc_sel === PC_BRJMP) { mispredict := !uop.taken } } val brinfo = Wire(new BrResolutionInfo) // note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit brinfo.valid := is_br \|\| is_jalr brinfo.mispredict := mispredict brinfo.uop := uop brinfo.cfi_type := Mux(is_jalr, CFI_JALR, Mux(is_br , CFI_BR, CFI_X)) brinfo.taken := is_taken brinfo.pc_sel := pc_sel brinfo.jalr_target := DontCare // Branch/Jump Target Calculation // For jumps we read the FTQ, and can calculate the target // For branches we emit the offset for the core to redirect if necessary val target_offset = imm_xprlen(20,0).asSInt brinfo.jalr_target := DontCare if (isJmpUnit) { def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) { ea } else { // Efficient means to compress 64-bit VA into vaddrBits+1 bits. // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)). val a = a0.asSInt >> vaddrBits val msb = Mux(a === 0.S \|\| a === -1.S, ea(vaddrBits), !ea(vaddrBits-1)) Cat(msb, ea(vaddrBits-1,0)) } val jalr_target_base = io.req.bits.rs1_data.asSInt val jalr_target_xlen = Wire(UInt(xLen.W)) jalr_target_xlen := (jalr_target_base + target_offset).asUInt val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt brinfo.jalr_target := jalr_target val cfi_idx = ((uop.pc_lob ^ Mux(io.get_ftq_pc.entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1) when (pc_sel === PC_JALR) { mispredict := !io.get_ftq_pc.next_val \|\| (io.get_ftq_pc.next_pc =/= jalr_target) \|\| !io.get_ftq_pc.entry.cfi_idx.valid \|\| (io.get_ftq_pc.entry.cfi_idx.bits =/= cfi_idx) } } brinfo.target_offset := target_offset io.brinfo := brinfo // Response // TODO add clock gate on resp bits from functional units // io.resp.bits.data := RegEnable(alu.io.out, io.req.valid) // val reg_data = Reg(outType = Bits(width = xLen)) // reg_data := alu.io.out // io.resp.bits.data := reg_data val r_val = RegInit(VecInit(Seq.fill(numStages) { false.B })) val r_data = Reg(Vec(numStages, UInt(xLen.W))) val r_pred = Reg(Vec(numStages, Bool())) val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data, Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data), Mux(io.req.bits.uop.uopc === uopMOV, io.req.bits.rs2_data, alu.io.out)) r_val (0) := io.req.valid r_data(0) := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out) r_pred(0) := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data for (i <- 1 until numStages) { r_val(i) := r_val(i-1) r_data(i) := r_data(i-1) r_pred(i) := r_pred(i-1) } io.resp.bits.data := r_data(numStages-1) io.resp.bits.predicated := r_pred(numStages-1) // Bypass // for the ALU, we can bypass same cycle as compute require (numStages >= 1) require (numBypassStages >= 1) io.bypass(0).valid := io.req.valid io.bypass(0).bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out) for (i <- 1 until numStages) { io.bypass(i).valid := r_val(i-1) io.bypass(i).bits.data := r_data(i-1) } // Exceptions io.resp.bits.fflags.valid := false.B } /* * Functional unit that passes in base+imm to calculate addresses, and passes store data * to the LSU. * For floating point, 65bit FP store-data needs to be decoded into 64bit FP form / class MemAddrCalcUnit(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = 0, numBypassStages = 0, earliestBypassStage = 0, dataWidth = 65, // TODO enable this only if FP is enabled? isMemAddrCalcUnit = true) with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { // perform address calculation val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U, sum(63,vaddrBits) =/= 0.U) val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt val store_data = io.req.bits.rs2_data io.resp.bits.addr := effective_address io.resp.bits.data := store_data if (dataWidth > 63) { assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.resp.bits.data(64).asBool === true.B), "65th bit set in MemAddrCalcUnit.") assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val), "FP store-data should now be going through a different unit.") } assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/= uopLD && io.req.bits.uop.uopc =/= uopSTA), "[maddrcalc] assert we never get store data in here.") // Handle misaligned exceptions val size = io.req.bits.uop.mem_size val misaligned = (size === 1.U && (effective_address(0) =/= 0.U)) \|\| (size === 2.U && (effective_address(1,0) =/= 0.U)) \|\| (size === 3.U && (effective_address(2,0) =/= 0.U)) val bkptu = Module(new BreakpointUnit(nBreakpoints)) bkptu.io.status := io.status bkptu.io.bp := io.bp bkptu.io.pc := DontCare bkptu.io.ea := effective_address bkptu.io.mcontext := io.mcontext bkptu.io.scontext := io.scontext val ma_ld = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned val ma_st = io.req.valid && (io.req.bits.uop.uopc === uopSTA \|\| io.req.bits.uop.uopc === uopAMO_AG) && misaligned val dbg_bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.debug_ld) \|\| (io.req.bits.uop.uopc === uopSTA && bkptu.io.debug_st)) val bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.xcpt_ld) \|\| (io.req.bits.uop.uopc === uopSTA && bkptu.io.xcpt_st)) def checkExceptions(x: Seq[(Bool, UInt)]) = (x.map(_._1).reduce(_\|\|_), PriorityMux(x)) val (xcpt_val, xcpt_cause) = checkExceptions(List( (ma_ld, (Causes.misaligned_load).U), (ma_st, (Causes.misaligned_store).U), (dbg_bp, (CSR.debugTriggerCause).U), (bp, (Causes.breakpoint).U))) io.resp.bits.mxcpt.valid := xcpt_val io.resp.bits.mxcpt.bits := xcpt_cause assert (!(ma_ld && ma_st), "Mutually-exclusive exceptions are firing.") io.resp.bits.sfence.valid := io.req.valid && io.req.bits.uop.mem_cmd === M_SFENCE io.resp.bits.sfence.bits.rs1 := io.req.bits.uop.mem_size(0) io.resp.bits.sfence.bits.rs2 := io.req.bits.uop.mem_size(1) io.resp.bits.sfence.bits.addr := io.req.bits.rs1_data io.resp.bits.sfence.bits.asid := io.req.bits.rs2_data } /* * Functional unit to wrap lower level FPU * * Currently, bypassing is unsupported! * All FP instructions are padded out to the max latency unit for easy * write-port scheduling. / class FPUUnit(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = p(tile.TileKey).core.fpu.get.dfmaLatency, numBypassStages = 0, earliestBypassStage = 0, dataWidth = 65, needsFcsr = true) { val fpu = Module(new FPU()) fpu.io.req.valid := io.req.valid fpu.io.req.bits.uop := io.req.bits.uop fpu.io.req.bits.rs1_data := io.req.bits.rs1_data fpu.io.req.bits.rs2_data := io.req.bits.rs2_data fpu.io.req.bits.rs3_data := io.req.bits.rs3_data fpu.io.req.bits.fcsr_rm := io.fcsr_rm io.resp.bits.data := fpu.io.resp.bits.data io.resp.bits.fflags.valid := fpu.io.resp.bits.fflags.valid io.resp.bits.fflags.bits.uop := io.resp.bits.uop io.resp.bits.fflags.bits.flags := fpu.io.resp.bits.fflags.bits.flags // kill me now } /* * Int to FP conversion functional unit * * @param latency the amount of stages to delay by / class IntToFPUnit(latency: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = latency, numBypassStages = 0, earliestBypassStage = 0, dataWidth = 65, needsFcsr = true) with tile.HasFPUParameters { val fp_decoder = Module(new UOPCodeFPUDecoder) // TODO use a simpler decoder val io_req = io.req.bits fp_decoder.io.uopc := io_req.uop.uopc val fp_ctrl = fp_decoder.io.sigs val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io_req.uop.imm_packed)) val req = Wire(new tile.FPInput) val tag = fp_ctrl.typeTagIn req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl req.rm := fp_rm req.in1 := unbox(io_req.rs1_data, tag, None) req.in2 := unbox(io_req.rs2_data, tag, None) req.in3 := DontCare req.typ := ImmGenTyp(io_req.uop.imm_packed) req.fmt := DontCare // FIXME: this may not be the right thing to do here req.fmaCmd := DontCare assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool), "[func] IntToFP integer input has 65th high-order bit set!") assert (!(io.req.valid && !fp_ctrl.fromint), "[func] Only support fromInt micro-ops.") val ifpu = Module(new tile.IntToFP(intToFpLatency)) ifpu.io.in.valid := io.req.valid ifpu.io.in.bits := req ifpu.io.in.bits.in1 := io_req.rs1_data val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits //io.resp.bits.data := box(ifpu.io.out.bits.data, !io.resp.bits.uop.fp_single) io.resp.bits.data := box(ifpu.io.out.bits.data, out_double) io.resp.bits.fflags.valid := ifpu.io.out.valid io.resp.bits.fflags.bits.uop := io.resp.bits.uop io.resp.bits.fflags.bits.flags := ifpu.io.out.bits.exc } /* * Iterative/unpipelined functional unit, can only hold a single MicroOp at a time * assumes at least one register between request and response * * TODO allow up to N micro-ops simultaneously. * * @param dataWidth width of the data to be passed into the functional unit / abstract class IterativeFunctionalUnit(dataWidth: Int)(implicit p: Parameters) extends FunctionalUnit( isPipelined = false, numStages = 1, numBypassStages = 0, dataWidth = dataWidth) { val r_uop = Reg(new MicroOp()) val do_kill = Wire(Bool()) do_kill := io.req.bits.kill // irrelevant default when (io.req.fire) { // update incoming uop do_kill := IsKilledByBranch(io.brupdate, io.req.bits.uop) \|\| io.req.bits.kill r_uop := io.req.bits.uop r_uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop) } .otherwise { do_kill := IsKilledByBranch(io.brupdate, r_uop) \|\| io.req.bits.kill r_uop.br_mask := GetNewBrMask(io.brupdate, r_uop) } // assumes at least one pipeline register between request and response io.resp.bits.uop := r_uop } /* * Divide functional unit. * * @param dataWidth data to be passed into the functional unit / class DivUnit(dataWidth: Int)(implicit p: Parameters) extends IterativeFunctionalUnit(dataWidth) { // We don't use the iterative multiply functionality here. // Instead we use the PipelinedMultiplier val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth)) // request div.io.req.valid := io.req.valid && !this.do_kill div.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw div.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn div.io.req.bits.in1 := io.req.bits.rs1_data div.io.req.bits.in2 := io.req.bits.rs2_data div.io.req.bits.tag := DontCare io.req.ready := div.io.req.ready // handle pipeline kills and branch misspeculations div.io.kill := this.do_kill // response io.resp.valid := div.io.resp.valid && !this.do_kill div.io.resp.ready := io.resp.ready io.resp.bits.data := div.io.resp.bits.data } /* * Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier * * @param numStages number of pipeline stages * @param dataWidth size of the data being passed into the functional unit */ class PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = numStages, numBypassStages = 0, earliestBypassStage = 0, dataWidth = dataWidth) { val imul = Module(new PipelinedMultiplier(xLen, numStages)) // request imul.io.req.valid := io.req.valid imul.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn imul.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw imul.io.req.bits.in1 := io.req.bits.rs1_data imul.io.req.bits.in2 := io.req.bits.rs2_data imul.io.req.bits.tag := DontCare // response io.resp.bits.data := imul.io.resp.bits.data }	module IntToFPUnit_1( // @[functional-unit.scala:591:7] input clock, // @[functional-unit.scala:591:7] input reset, // @[functional-unit.scala:591:7] input io_req_valid, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14] input [7:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14] input io_req_bits_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_req_bits_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14] input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14] input io_req_bits_kill, // @[functional-unit.scala:168:14] output io_resp_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [7:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [64:0] io_resp_bits_data, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_fflags_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_fflags_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [7:0] io_resp_bits_fflags_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_fflags_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_fflags_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_pdst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_prs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_prs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_prs3, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_fflags_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_flags, // @[functional-unit.scala:168:14] input [7:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14] input io_brupdate_b2_valid, // @[functional-unit.scala:168:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14] input io_brupdate_b2_taken, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14] input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14] input [2:0] io_fcsr_rm // @[functional-unit.scala:168:14] ); wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:591:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:591:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:591:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:591:7] wire [7:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_br_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:591:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:591:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[functional-unit.scala:591:7] wire [64:0] _ifpu_io_out_bits_data; // @[functional-unit.scala:624:20] wire [1:0] _fp_decoder_io_sigs_typeTagIn; // @[functional-unit.scala:600:26] wire [1:0] _fp_decoder_io_sigs_typeTagOut; // @[functional-unit.scala:600:26] wire _fp_decoder_io_sigs_fromint; // @[functional-unit.scala:600:26] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:591:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:591:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:591:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:591:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:591:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:591:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:591:7] wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:591:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:591:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:591:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:591:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:591:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:591:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:591:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:591:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:591:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:591:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:591:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:591:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:591:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:591:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:591:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:591:7] wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:591:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:591:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:591:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:591:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:591:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:591:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:591:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:591:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:591:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:591:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:591:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:591:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:591:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:591:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:591:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:591:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[functional-unit.scala:591:7] wire io_req_ready = 1'h1; // @[functional-unit.scala:591:7] wire _io_resp_bits_data_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42] wire _io_resp_bits_data_opts_bigger_T = 1'h1; // @[FPU.scala:249:56] wire [64:0] io_req_bits_rs3_data = 65'h0; // @[functional-unit.scala:591:7] wire [64:0] req_in3 = 65'h0; // @[functional-unit.scala:605:17] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_ready = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_mxcpt_valid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_valid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_asid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:591:7] wire _r_valids_WIRE_0 = 1'h0; // @[functional-unit.scala:236:35] wire _r_valids_WIRE_1 = 1'h0; // @[functional-unit.scala:236:35] wire req_vec = 1'h0; // @[functional-unit.scala:605:17] wire [39:0] io_resp_bits_addr = 40'h0; // @[functional-unit.scala:591:7] wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[functional-unit.scala:591:7] wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26] wire [1:0] req_fmaCmd = 2'h0; // @[functional-unit.scala:605:17] wire [1:0] req_fmt = 2'h0; // @[functional-unit.scala:605:17] wire _io_resp_valid_T_3; // @[functional-unit.scala:257:47] wire [6:0] io_resp_bits_fflags_bits_uop_uopc_0 = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_fflags_bits_uop_inst_0 = io_resp_bits_uop_inst_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst_0 = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_rvc_0 = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:591:7] wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc_0 = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:591:7] wire [9:0] io_resp_bits_fflags_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type_0 = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_load_0 = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_sta_0 = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_std_0 = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_iw_state_0 = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_br_0 = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_jalr_0 = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_jal_0 = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_sfb_0 = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:591:7] wire [7:0] _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [7:0] io_resp_bits_fflags_bits_uop_br_mask_0 = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_br_tag_0 = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_ftq_idx_0 = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_edge_inst_0 = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob_0 = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_taken_0 = io_resp_bits_uop_taken_0; // @[functional-unit.scala:591:7] wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed_0 = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:591:7] wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr_0 = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_rob_idx_0 = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ldq_idx_0 = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_stq_idx_0 = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx_0 = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_pdst_0 = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_prs1_0 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_prs2_0 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_prs3_0 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_ppred_0 = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs1_busy_0 = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs2_busy_0 = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs3_busy_0 = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ppred_busy_0 = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_stale_pdst_0 = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_exception_0 = io_resp_bits_uop_exception_0; // @[functional-unit.scala:591:7] wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause_0 = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bypassable_0 = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd_0 = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_mem_size_0 = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_mem_signed_0 = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_fence_0 = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_fencei_0 = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_amo_0 = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_uses_ldq_0 = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_uses_stq_0 = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_unique_0 = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_flush_on_commit_0 = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ldst_is_rs1_0 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_ldst_0 = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs1_0 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs2_0 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs3_0 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ldst_val_0 = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype_0 = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype_0 = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype_0 = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_frs3_en_0 = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_fp_val_0 = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_fp_single_0 = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_pf_if_0 = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_ae_if_0 = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_ma_if_0 = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bp_debug_if_0 = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bp_xcpt_if_0 = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc_0 = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc_0 = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:591:7] wire [64:0] _io_resp_bits_data_T_1; // @[package.scala:39:76] wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_valid_0; // @[functional-unit.scala:591:7] wire [64:0] io_resp_bits_data_0; // @[functional-unit.scala:591:7] wire io_resp_valid_0; // @[functional-unit.scala:591:7] reg r_valids_0; // @[functional-unit.scala:236:27] reg r_valids_1; // @[functional-unit.scala:236:27] reg [6:0] r_uops_0_uopc; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_inst; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_debug_inst; // @[functional-unit.scala:237:23] reg r_uops_0_is_rvc; // @[functional-unit.scala:237:23] reg [39:0] r_uops_0_debug_pc; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_iq_type; // @[functional-unit.scala:237:23] reg [9:0] r_uops_0_fu_code; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_iw_state; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_is_br; // @[functional-unit.scala:237:23] reg r_uops_0_is_jalr; // @[functional-unit.scala:237:23] reg r_uops_0_is_jal; // @[functional-unit.scala:237:23] reg r_uops_0_is_sfb; // @[functional-unit.scala:237:23] reg [7:0] r_uops_0_br_mask; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_br_tag; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ftq_idx; // @[functional-unit.scala:237:23] reg r_uops_0_edge_inst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_pc_lob; // @[functional-unit.scala:237:23] reg r_uops_0_taken; // @[functional-unit.scala:237:23] reg [19:0] r_uops_0_imm_packed; // @[functional-unit.scala:237:23] reg [11:0] r_uops_0_csr_addr; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_rob_idx; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ldq_idx; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_stq_idx; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_rxq_idx; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_pdst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_prs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_prs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_prs3; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ppred; // @[functional-unit.scala:237:23] reg r_uops_0_prs1_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs2_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs3_busy; // @[functional-unit.scala:237:23] reg r_uops_0_ppred_busy; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_stale_pdst; // @[functional-unit.scala:237:23] reg r_uops_0_exception; // @[functional-unit.scala:237:23] reg [63:0] r_uops_0_exc_cause; // @[functional-unit.scala:237:23] reg r_uops_0_bypassable; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_mem_cmd; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_mem_size; // @[functional-unit.scala:237:23] reg r_uops_0_mem_signed; // @[functional-unit.scala:237:23] reg r_uops_0_is_fence; // @[functional-unit.scala:237:23] reg r_uops_0_is_fencei; // @[functional-unit.scala:237:23] reg r_uops_0_is_amo; // @[functional-unit.scala:237:23] reg r_uops_0_uses_ldq; // @[functional-unit.scala:237:23] reg r_uops_0_uses_stq; // @[functional-unit.scala:237:23] reg r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23] reg r_uops_0_is_unique; // @[functional-unit.scala:237:23] reg r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_ldst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs3; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_val; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_dst_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23] reg r_uops_0_frs3_en; // @[functional-unit.scala:237:23] reg r_uops_0_fp_val; // @[functional-unit.scala:237:23] reg r_uops_0_fp_single; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_uopc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uopc_0 = r_uops_1_uopc; // @[functional-unit.scala:237:23, :591:7] reg [31:0] r_uops_1_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_inst_0 = r_uops_1_inst; // @[functional-unit.scala:237:23, :591:7] reg [31:0] r_uops_1_debug_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_inst_0 = r_uops_1_debug_inst; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_rvc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_rvc_0 = r_uops_1_is_rvc; // @[functional-unit.scala:237:23, :591:7] reg [39:0] r_uops_1_debug_pc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_pc_0 = r_uops_1_debug_pc; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_iq_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iq_type_0 = r_uops_1_iq_type; // @[functional-unit.scala:237:23, :591:7] reg [9:0] r_uops_1_fu_code; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fu_code_0 = r_uops_1_fu_code; // @[functional-unit.scala:237:23, :591:7] reg [3:0] r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_br_type_0 = r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_load_0 = r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_sta_0 = r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_std_0 = r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_iw_state; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_state_0 = r_uops_1_iw_state; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_br; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_br_0 = r_uops_1_is_br; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_jalr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jalr_0 = r_uops_1_is_jalr; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_jal; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jal_0 = r_uops_1_is_jal; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_sfb; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sfb_0 = r_uops_1_is_sfb; // @[functional-unit.scala:237:23, :591:7] reg [7:0] r_uops_1_br_mask; // @[functional-unit.scala:237:23] reg [2:0] r_uops_1_br_tag; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_br_tag_0 = r_uops_1_br_tag; // @[functional-unit.scala:237:23, :591:7] reg [3:0] r_uops_1_ftq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ftq_idx_0 = r_uops_1_ftq_idx; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_edge_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_edge_inst_0 = r_uops_1_edge_inst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_pc_lob; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pc_lob_0 = r_uops_1_pc_lob; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_taken; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_taken_0 = r_uops_1_taken; // @[functional-unit.scala:237:23, :591:7] reg [19:0] r_uops_1_imm_packed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_imm_packed_0 = r_uops_1_imm_packed; // @[functional-unit.scala:237:23, :591:7] reg [11:0] r_uops_1_csr_addr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_csr_addr_0 = r_uops_1_csr_addr; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_rob_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rob_idx_0 = r_uops_1_rob_idx; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ldq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldq_idx_0 = r_uops_1_ldq_idx; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_stq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stq_idx_0 = r_uops_1_stq_idx; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_rxq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rxq_idx_0 = r_uops_1_rxq_idx; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pdst_0 = r_uops_1_pdst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_prs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_0 = r_uops_1_prs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_prs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_0 = r_uops_1_prs2; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_prs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_0 = r_uops_1_prs3; // @[functional-unit.scala:237:23, :591:7] reg [3:0] r_uops_1_ppred; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_0 = r_uops_1_ppred; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs1_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_busy_0 = r_uops_1_prs1_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs2_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_busy_0 = r_uops_1_prs2_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs3_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_busy_0 = r_uops_1_prs3_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ppred_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_busy_0 = r_uops_1_ppred_busy; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_stale_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stale_pdst_0 = r_uops_1_stale_pdst; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_exception; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exception_0 = r_uops_1_exception; // @[functional-unit.scala:237:23, :591:7] reg [63:0] r_uops_1_exc_cause; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exc_cause_0 = r_uops_1_exc_cause; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bypassable; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bypassable_0 = r_uops_1_bypassable; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_mem_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_cmd_0 = r_uops_1_mem_cmd; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_mem_size; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_size_0 = r_uops_1_mem_size; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_mem_signed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_signed_0 = r_uops_1_mem_signed; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_fence; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fence_0 = r_uops_1_is_fence; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_fencei; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fencei_0 = r_uops_1_is_fencei; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_amo; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_amo_0 = r_uops_1_is_amo; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_uses_ldq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_ldq_0 = r_uops_1_uses_ldq; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_uses_stq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_stq_0 = r_uops_1_uses_stq; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_unique; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_unique_0 = r_uops_1_is_unique; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_flush_on_commit_0 = r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_is_rs1_0 = r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_ldst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_0 = r_uops_1_ldst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_0 = r_uops_1_lrs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_0 = r_uops_1_lrs2; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs3_0 = r_uops_1_lrs3; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ldst_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_val_0 = r_uops_1_ldst_val; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_dst_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_dst_rtype_0 = r_uops_1_dst_rtype; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_rtype_0 = r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_rtype_0 = r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_frs3_en; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_frs3_en_0 = r_uops_1_frs3_en; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_fp_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_val_0 = r_uops_1_fp_val; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_fp_single; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_single_0 = r_uops_1_fp_single; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_pf_if_0 = r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ae_if_0 = r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ma_if_0 = r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_debug_if_0 = r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_xcpt_if_0 = r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_fsrc_0 = r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_tsrc_0 = r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23, :591:7] wire [7:0] _r_valids_0_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51] wire _r_valids_0_T_1 = \|_r_valids_0_T; // @[util.scala:118:{51,59}] wire _r_valids_0_T_2 = ~_r_valids_0_T_1; // @[util.scala:118:59] wire _r_valids_0_T_3 = io_req_valid_0 & _r_valids_0_T_2; // @[functional-unit.scala:240:{33,36}, :591:7] wire _r_valids_0_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :591:7] wire _r_valids_0_T_5 = _r_valids_0_T_3 & _r_valids_0_T_4; // @[functional-unit.scala:240:{33,84,87}] wire [7:0] _r_uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_uops_0_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uops_0_br_mask_T; // @[util.scala:85:{25,27}] wire [7:0] _r_valids_1_T = io_brupdate_b1_mispredict_mask_0 & r_uops_0_br_mask; // @[util.scala:118:51] wire _r_valids_1_T_1 = \|_r_valids_1_T; // @[util.scala:118:{51,59}] wire _r_valids_1_T_2 = ~_r_valids_1_T_1; // @[util.scala:118:59] wire _r_valids_1_T_3 = r_valids_0 & _r_valids_1_T_2; // @[functional-unit.scala:236:27, :246:{36,39}] wire _r_valids_1_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :591:7] wire _r_valids_1_T_5 = _r_valids_1_T_3 & _r_valids_1_T_4; // @[functional-unit.scala:246:{36,83,86}] wire [7:0] _r_uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_uops_1_br_mask_T_1 = r_uops_0_br_mask & _r_uops_1_br_mask_T; // @[util.scala:85:{25,27}] wire [7:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_uops_1_br_mask; // @[util.scala:118:51] wire _io_resp_valid_T_1 = \|_io_resp_valid_T; // @[util.scala:118:{51,59}] wire _io_resp_valid_T_2 = ~_io_resp_valid_T_1; // @[util.scala:118:59] assign _io_resp_valid_T_3 = r_valids_1 & _io_resp_valid_T_2; // @[functional-unit.scala:236:27, :257:{47,50}] assign io_resp_valid_0 = _io_resp_valid_T_3; // @[functional-unit.scala:257:47, :591:7] wire [7:0] _io_resp_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _io_resp_bits_uop_br_mask_T_1 = r_uops_1_br_mask & _io_resp_bits_uop_br_mask_T; // @[util.scala:85:{25,27}] assign io_resp_bits_uop_br_mask_0 = _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [2:0] _fp_rm_T = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire [2:0] _fp_rm_T_2 = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire _fp_rm_T_1 = &_fp_rm_T; // @[util.scala:289:58] wire [2:0] fp_rm = _fp_rm_T_1 ? io_fcsr_rm_0 : _fp_rm_T_2; // @[util.scala:289:58] wire [2:0] req_rm = fp_rm; // @[functional-unit.scala:604:18, :605:17] wire [1:0] _req_typ_T; // @[util.scala:295:59] wire [64:0] _req_in1_T_4; // @[FPU.scala:369:10] wire [64:0] _req_in2_T_4; // @[FPU.scala:369:10] wire req_ldst; // @[functional-unit.scala:605:17] wire req_wen; // @[functional-unit.scala:605:17] wire req_ren1; // @[functional-unit.scala:605:17] wire req_ren2; // @[functional-unit.scala:605:17] wire req_ren3; // @[functional-unit.scala:605:17] wire req_swap12; // @[functional-unit.scala:605:17] wire req_swap23; // @[functional-unit.scala:605:17] wire [1:0] req_typeTagIn; // @[functional-unit.scala:605:17] wire [1:0] req_typeTagOut; // @[functional-unit.scala:605:17] wire req_fromint; // @[functional-unit.scala:605:17] wire req_toint; // @[functional-unit.scala:605:17] wire req_fastpipe; // @[functional-unit.scala:605:17] wire req_fma; // @[functional-unit.scala:605:17] wire req_div; // @[functional-unit.scala:605:17] wire req_sqrt; // @[functional-unit.scala:605:17] wire req_wflags; // @[functional-unit.scala:605:17] wire [1:0] req_typ; // @[functional-unit.scala:605:17] wire [64:0] req_in1; // @[functional-unit.scala:605:17] wire [64:0] req_in2; // @[functional-unit.scala:605:17] wire _req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] req_in1_prev_unswizzled_hi = {_req_in1_prev_unswizzled_T, _req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] req_in1_prev_unswizzled = {req_in1_prev_unswizzled_hi, _req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire req_in1_prev_prev_sign = req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] req_in1_prev_prev_fractIn = req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] req_in1_prev_prev_expIn = req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _req_in1_prev_prev_fractOut_T = {req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] req_in1_prev_prev_fractOut = _req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] req_in1_prev_prev_expOut_expCode = req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _req_in1_prev_prev_expOut_commonCase_T = {4'h0, req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _req_in1_prev_prev_expOut_commonCase_T_1 = _req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] req_in1_prev_prev_expOut_commonCase = _req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _req_in1_prev_prev_expOut_T_5 = req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _req_in1_prev_prev_expOut_T = req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _req_in1_prev_prev_expOut_T_1 = req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _req_in1_prev_prev_expOut_T_2 = _req_in1_prev_prev_expOut_T \| _req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _req_in1_prev_prev_expOut_T_3 = req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _req_in1_prev_prev_expOut_T_4 = {req_in1_prev_prev_expOut_expCode, _req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] req_in1_prev_prev_expOut = _req_in1_prev_prev_expOut_T_2 ? _req_in1_prev_prev_expOut_T_4 : _req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] req_in1_prev_prev_hi = {req_in1_prev_prev_sign, req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] req_in1_floats_0 = {req_in1_prev_prev_hi, req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire req_in1_prev_isbox = &_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire req_in1_oks_0 = req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _req_in1_truncIdx_T; // @[package.scala:38:21] wire req_in1_truncIdx = _req_in1_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _req_in1_T = req_in1_truncIdx; // @[package.scala:38:47, :39:86] wire _req_in1_T_1 = _req_in1_T \| req_in1_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _req_in1_truncIdx_T_1; // @[package.scala:38:21] wire req_in1_truncIdx_1 = _req_in1_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _req_in1_T_2 = req_in1_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _req_in1_T_3 = _req_in1_T_2 ? io_req_bits_rs1_data_0 : req_in1_floats_0; // @[package.scala:39:{76,86}] assign _req_in1_T_4 = _req_in1_T_1 ? _req_in1_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign req_in1 = _req_in1_T_4; // @[FPU.scala:369:10] wire _req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] req_in2_prev_unswizzled_hi = {_req_in2_prev_unswizzled_T, _req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] req_in2_prev_unswizzled = {req_in2_prev_unswizzled_hi, _req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire req_in2_prev_prev_sign = req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] req_in2_prev_prev_fractIn = req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] req_in2_prev_prev_expIn = req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _req_in2_prev_prev_fractOut_T = {req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] req_in2_prev_prev_fractOut = _req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] req_in2_prev_prev_expOut_expCode = req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _req_in2_prev_prev_expOut_commonCase_T = {4'h0, req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _req_in2_prev_prev_expOut_commonCase_T_1 = _req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] req_in2_prev_prev_expOut_commonCase = _req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _req_in2_prev_prev_expOut_T_5 = req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _req_in2_prev_prev_expOut_T = req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _req_in2_prev_prev_expOut_T_1 = req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _req_in2_prev_prev_expOut_T_2 = _req_in2_prev_prev_expOut_T \| _req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _req_in2_prev_prev_expOut_T_3 = req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _req_in2_prev_prev_expOut_T_4 = {req_in2_prev_prev_expOut_expCode, _req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] req_in2_prev_prev_expOut = _req_in2_prev_prev_expOut_T_2 ? _req_in2_prev_prev_expOut_T_4 : _req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] req_in2_prev_prev_hi = {req_in2_prev_prev_sign, req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] req_in2_floats_0 = {req_in2_prev_prev_hi, req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire req_in2_prev_isbox = &_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire req_in2_oks_0 = req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _req_in2_truncIdx_T; // @[package.scala:38:21] wire req_in2_truncIdx = _req_in2_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _req_in2_T = req_in2_truncIdx; // @[package.scala:38:47, :39:86] wire _req_in2_T_1 = _req_in2_T \| req_in2_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _req_in2_truncIdx_T_1; // @[package.scala:38:21] wire req_in2_truncIdx_1 = _req_in2_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _req_in2_T_2 = req_in2_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _req_in2_T_3 = _req_in2_T_2 ? io_req_bits_rs2_data_0 : req_in2_floats_0; // @[package.scala:39:{76,86}] assign _req_in2_T_4 = _req_in2_T_1 ? _req_in2_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign req_in2 = _req_in2_T_4; // @[FPU.scala:369:10] assign _req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59] assign req_typ = _req_typ_T; // @[util.scala:295:59]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_112( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_192 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_181( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_198 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }	module rockettile_icache_data_arrays_2( // @[DescribedSRAM.scala:17:26] input [6:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [255:0] RW0_wdata, output [255:0] RW0_rdata, input [7:0] RW0_wmask ); rockettile_icache_data_arrays_0_ext rockettile_icache_data_arrays_0_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_5( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [8:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [64:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [64:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [53:0] _roundMask_T = 54'h0; // @[RoundAnyRawFNToRecFN.scala:153:36] wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [55:0] roundMask = 56'h3; // @[RoundAnyRawFNToRecFN.scala:153:55] wire [56:0] _shiftedRoundMask_T = 57'h3; // @[RoundAnyRawFNToRecFN.scala:162:41] wire [55:0] shiftedRoundMask = 56'h1; // @[RoundAnyRawFNToRecFN.scala:162:53] wire [55:0] _roundPosMask_T = 56'hFFFFFFFFFFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28] wire [55:0] roundPosMask = 56'h2; // @[RoundAnyRawFNToRecFN.scala:163:46] wire [55:0] _roundedSig_T_10 = 56'hFFFFFFFFFFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32] wire [54:0] _roundedSig_T_6 = 55'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [54:0] _roundedSig_T_14 = 55'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [11:0] _expOut_T_6 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [11:0] _expOut_T_9 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [11:0] _expOut_T_12 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [11:0] _expOut_T_5 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [11:0] _expOut_T_8 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [11:0] _expOut_T_11 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:265:18] wire [11:0] _expOut_T_14 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [11:0] _expOut_T_16 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [11:0] _expOut_T_18 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:277:16] wire [11:0] _expOut_T_20 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:278:16] wire [51:0] _fractOut_T_2 = 52'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [51:0] _fractOut_T_4 = 52'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:288:41] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32] wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22] wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22] wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53, :288:41] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T \| _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire [12:0] _sAdjustedExp_T = {{4{io_in_sExp_0[8]}}, io_in_sExp_0} + 13'h780; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25] wire [11:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[11:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14] wire [12:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}] wire [54:0] _adjustedSig_T = io_in_sig_0[64:10]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23] wire [9:0] _adjustedSig_T_1 = io_in_sig_0[9:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26] wire _adjustedSig_T_2 = \|_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}] wire [55:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60] wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [55:0] _roundPosBit_T = adjustedSig & 56'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [55:0] _anyRoundExtra_T = adjustedSig & 56'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49] wire _GEN = roundingMode_near_even \| roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 \| _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [55:0] _roundedSig_T = adjustedSig \| 56'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32] wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [54:0] _roundedSig_T_7 = {54'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}] wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [55:0] _roundedSig_T_11 = adjustedSig & 56'hFFFFFFFFFFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}] wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [54:0] _roundedSig_T_15 = {54'h0, _roundedSig_T_13}; // @[RoundAnyRawFNToRecFN.scala:181:{24,42}] wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} \| _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [13:0] sRoundedExp = {sAdjustedExp[12], sAdjustedExp} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}] assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 \| _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T \| roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T_1 = roundMagUp \| roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [11:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [11:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [11:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17] wire [11:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [11:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [11:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15] wire [11:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73] wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}] wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? 52'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13] wire [51:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_175( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_431 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_191( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_447 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_175( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth2 - 1)) }) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) \|\| (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf \|\| io.b.isInf val notNaN_isZeroOut = io.a.isZero \|\| io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth2 - 1, 0) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ io.invalidExc := isSigNaNRawFloat(io.a) \|\| isSigNaNRawFloat(io.b) \|\| notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN \|\| io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module MulRecFN_39( // @[MulRecFN.scala:100:7] input [32:0] io_a, // @[MulRecFN.scala:102:16] input [32:0] io_b, // @[MulRecFN.scala:102:16] output [32:0] io_out // @[MulRecFN.scala:102:16] ); wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26] wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26] wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26] wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7] wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7] wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [32:0] io_out_0; // @[MulRecFN.scala:100:7] wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7] wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] MulRawFN_39 mulRawFN ( // @[MulRecFN.scala:113:26] .io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_invalidExc (_mulRawFN_io_invalidExc), .io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN), .io_rawOut_isInf (_mulRawFN_io_rawOut_isInf), .io_rawOut_isZero (_mulRawFN_io_rawOut_isZero), .io_rawOut_sign (_mulRawFN_io_rawOut_sign), .io_rawOut_sExp (_mulRawFN_io_rawOut_sExp), .io_rawOut_sig (_mulRawFN_io_rawOut_sig) ); // @[MulRecFN.scala:113:26] RoundRawFNToRecFN_e8_s24_111 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15] .io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26] .io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26] .io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26] .io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26] .io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26] .io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26] .io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulRecFN.scala:121:15] assign io_out = io_out_0; // @[MulRecFN.scala:100:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_79( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_92 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in \|\| corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ \|\| !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready \|\| !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel \| count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)outByteswidth-1, ioutByteswidth) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes8-1, edgeOut.manager.beatBytes8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid \|\| full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLWidthWidget32_12( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [255:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [255:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [255:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [255:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [255:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [255:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [255:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] wire [255:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] cated_bits_source; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] cated_bits_address; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_2 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_3 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25] wire [255:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [31:0] cated_bits_mask; // @[WidthWidget.scala:161:25] wire [255:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [191:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[255:64]; // @[Repeater.scala:36:26] wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25] wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [19:0] _repeat_limit_T = 20'h1F << cated_bits_size; // @[package.scala:243:71] wire [4:0] _repeat_limit_T_1 = _repeat_limit_T[4:0]; // @[package.scala:243:{71,76}] wire [4:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire [1:0] repeat_limit = _repeat_limit_T_2[4:3]; // @[package.scala:243:46] reg [1:0] repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = repeat_count == 2'h0; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T \| _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35] wire [2:0] _repeat_count_T = {1'h0, repeat_count} + 3'h1; // @[WidthWidget.scala:105:26, :110:24] wire [1:0] _repeat_count_T_1 = _repeat_count_T[1:0]; // @[WidthWidget.scala:110:24] wire [1:0] repeat_sel = cated_bits_address[4:3]; // @[WidthWidget.scala:116:39, :161:25] wire [1:0] repeat_index = repeat_sel \| repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24] wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_2 = cated_bits_data[191:128]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_2 = _repeat_anonOut_a_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_3 = cated_bits_data[255:192]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_3 = _repeat_anonOut_a_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [3:0][63:0] _GEN = {{repeat_anonOut_a_bits_data_mux_3}, {repeat_anonOut_a_bits_data_mux_2}, {repeat_anonOut_a_bits_data_mux_1}, {repeat_anonOut_a_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30] assign anonOut_a_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_2 = cated_bits_mask[23:16]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_2 = _repeat_anonOut_a_bits_mask_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_3 = cated_bits_mask[31:24]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_3 = _repeat_anonOut_a_bits_mask_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [3:0][7:0] _GEN_0 = {{repeat_anonOut_a_bits_mask_mux_3}, {repeat_anonOut_a_bits_mask_mux_2}, {repeat_anonOut_a_bits_mask_mux_1}, {repeat_anonOut_a_bits_mask_mux_0}}; // @[WidthWidget.scala:128:43, :140:53] assign anonOut_a_bits_mask = _GEN_0[repeat_index]; // @[WidthWidget.scala:126:24, :140:53] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [19:0] _limit_T = 20'h1F << anonOut_d_bits_size; // @[package.scala:243:71] wire [4:0] _limit_T_1 = _limit_T[4:0]; // @[package.scala:243:{71,76}] wire [4:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire [1:0] limit = _limit_T_2[4:3]; // @[package.scala:243:46] reg [1:0] count; // @[WidthWidget.scala:40:27] wire [1:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = count == 2'h0; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T \| _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire [1:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = \|_enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_3 = {count[1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = \|_enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_6 = count ^ 2'h2; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_8 = \|_enable_T_7; // @[WidthWidget.scala:43:{63,72}] wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_9 = ~count; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_11 = \|_enable_T_10; // @[WidthWidget.scala:43:{63,72}] wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = anonOut_d_bits_corrupt \| corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [2:0] _count_T = {1'h0, count} + 3'h1; // @[WidthWidget.scala:40:27, :50:24] wire [1:0] _count_T_1 = _count_T[1:0]; // @[WidthWidget.scala:50:24] wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonOut_d_ready_T_1 = anonIn_d_ready \| _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_0 = enable_0 \| _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_1 = enable_1 \| _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_2 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_2 = enable_2 \| _anonIn_d_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_3 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_3 = enable_3 \| _anonIn_d_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:66:24] wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_2 = anonIn_d_bits_data_masked_enable_2 ? anonIn_d_bits_data_odata_2 : anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_3 = anonIn_d_bits_data_masked_enable_3 ? anonIn_d_bits_data_odata_3 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35] wire [127:0] anonIn_d_bits_data_lo = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [127:0] anonIn_d_bits_data_hi = {anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_hi, anonIn_d_bits_data_lo}; // @[WidthWidget.scala:73:12] assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] repeat_count <= 2'h0; // @[WidthWidget.scala:105:26] count <= 2'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] end else begin // @[WidthWidget.scala:27:9] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= repeat_last ? 2'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35] count <= last ? 2'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23] end anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 \| anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] end if (_anonIn_d_bits_data_T_2) begin // @[WidthWidget.scala:69:23] anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_1 <= anonIn_d_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_2 <= anonIn_d_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88] end always @(posedge) TLMonitor_70 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleA_a32d256s5k3z4u_8 repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonIn_a_ready), .io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_source (cated_bits_source), .io_deq_bits_address (cated_bits_address), .io_deq_bits_mask (cated_bits_mask), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w4_d3_i0_60( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_521 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_522 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_523 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_524 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module InputUnit_54( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_4_1, // @[InputUnit.scala:170:14] input io_out_credit_available_4_2, // @[InputUnit.scala:170:14] input io_out_credit_available_4_3, // @[InputUnit.scala:170:14] input io_out_credit_available_4_4, // @[InputUnit.scala:170:14] input io_out_credit_available_4_5, // @[InputUnit.scala:170:14] input io_out_credit_available_4_6, // @[InputUnit.scala:170:14] input io_out_credit_available_4_7, // @[InputUnit.scala:170:14] input io_out_credit_available_3_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_2, // @[InputUnit.scala:170:14] input io_out_credit_available_3_3, // @[InputUnit.scala:170:14] input io_out_credit_available_3_4, // @[InputUnit.scala:170:14] input io_out_credit_available_3_5, // @[InputUnit.scala:170:14] input io_out_credit_available_3_6, // @[InputUnit.scala:170:14] input io_out_credit_available_3_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [7:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_7; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_7; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_7; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [7:0] mask; // @[InputUnit.scala:250:21] wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] vcalloc_sel = vcalloc_filter[7:0] \| vcalloc_filter[15:8]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_1 \| vcalloc_vals_2 \| vcalloc_vals_3 \| vcalloc_vals_4 \| vcalloc_vals_5 \| vcalloc_vals_6 \| vcalloc_vals_7; // @[package.scala:81:59] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_42( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLFragmenter( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [28:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9] wire [28:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36] wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50] wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50] wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49] wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59] wire find_0 = 1'h1; // @[Parameters.scala:616:12] wire [29:0] _find_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _find_T_3 = 30'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [28:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [11:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [11:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [28:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9] assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9] wire [7:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9] wire [11:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9] wire [28:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49] assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire [2:0] dFragnum = anonOut_d_bits_source[2:0]; // @[Fragmenter.scala:204:41] wire [2:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala:204:41, :206:30] wire _drop_T_1 = dLast; // @[Fragmenter.scala:206:30, :234:37] wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] dsizeOH = _dsizeOH_T; // @[OneHot.scala:65:{12,27}] wire [5:0] _dsizeOH1_T = 6'h7 << anonOut_d_bits_size; // @[package.scala:243:71] wire [2:0] _dsizeOH1_T_1 = _dsizeOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}] wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45] wire _ack_decrement_T = dsizeOH[3]; // @[OneHot.scala:65:27] wire ack_decrement = dHasData \| _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}] wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala:204:41, :218:47] wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:3], _dFirst_size_T[2:0] \| dsizeOH1}; // @[package.scala:243:46] wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35] wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}] wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53] wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}] wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}] wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18] wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18] wire _dFirst_size_T_7 = \|dFirst_size_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} \| dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28] wire _dFirst_size_T_9 = \|dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 \| dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28] wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}] wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}] wire [3:0] _acknum_T = {1'h0, acknum} - {3'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55] wire [2:0] _acknum_T_1 = _acknum_T[2:0]; // @[Fragmenter.scala:221:55] wire [2:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}] wire _dToggle_T = anonOut_d_bits_source[3]; // @[Fragmenter.scala:224:41] wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20] wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}] wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}] assign _anonOut_d_ready_T = anonIn_d_ready \| drop; // @[Fragmenter.scala:234:30, :235:35] assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39] assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}] assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign _anonIn_d_bits_source_T = anonOut_d_bits_source[11:4]; // @[Fragmenter.scala:238:47] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] wire [28:0] _find_T; // @[Parameters.scala:137:31] wire [29:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}] wire _limit_T = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49] wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31] wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}] wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71] wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}] wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30] wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46] wire [3:0] _old_gennum1_T_1 = {1'h0, gennum} - 4'h1; // @[Fragmenter.scala:303:29, :305:79] wire [2:0] _old_gennum1_T_2 = _old_gennum1_T_1[2:0]; // @[Fragmenter.scala:305:79] wire [2:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}] wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40] wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28] wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}] wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}] wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}] wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}] wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}] wire aLast = ~(\|aFragnum); // @[Fragmenter.scala:307:24, :308:30] reg aToggle_r; // @[Fragmenter.scala:309:54] wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}] wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}] wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31] wire _repeater_io_repeat_T_1 = \|aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53] wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}] wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65] wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T \| _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}] wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] \| aFragOH1}; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}] wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}] assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[28:6], _repeater_io_deq_bits_address[5:0] \| _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}] assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] wire [8:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aToggle}; // @[Fragmenter.scala:274:30, :309:23, :317:33] assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, aFragnum}; // @[Fragmenter.scala:307:24, :317:33] assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25]
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_413( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File LoopConv.scala: package gemmini import chisel3._ import chisel3.util._ import chisel3.experimental._ import freechips.rocketchip.tile.RoCCCommand import org.chipsalliance.cde.config.Parameters import GemminiISA._ import LocalAddr._ import Util._ class LoopConvOuterBounds(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int) extends Bundle { val batch_size = UInt(large_iterator_bitwidth.W) val in_row_dim = UInt(small_iterator_bitwidth.W) val in_col_dim = UInt(small_iterator_bitwidth.W) val in_channels = UInt(large_iterator_bitwidth.W) val out_channels = UInt(large_iterator_bitwidth.W) val out_col_dim = UInt(large_iterator_bitwidth.W) val out_row_dim = UInt(large_iterator_bitwidth.W) val out_stride = UInt(large_iterator_bitwidth.W) //stride for output activation val in_stride = UInt(large_iterator_bitwidth.W) //stride for input activation val weight_stride = UInt(large_iterator_bitwidth.W) //stride for weight val pool_out_row_dim = UInt(small_iterator_bitwidth.W) val pool_out_col_dim = UInt(small_iterator_bitwidth.W) val stride = UInt(tiny_iterator_bitwidth.W) val padding = UInt(tiny_iterator_bitwidth.W) val kernel_dim = UInt(tiny_iterator_bitwidth.W) val kernel_dilation = UInt(tiny_iterator_bitwidth.W) val pool_size = UInt(tiny_iterator_bitwidth.W) val pool_stride = UInt(tiny_iterator_bitwidth.W) val pool_padding = UInt(tiny_iterator_bitwidth.W) } class LoopConvInnerBounds(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int) extends Bundle { val batches = UInt(large_iterator_bitwidth.W) val porows = UInt(small_iterator_bitwidth.W) val pocols = UInt(small_iterator_bitwidth.W) val pochs = UInt(large_iterator_bitwidth.W) val krows = UInt(tiny_iterator_bitwidth.W) val kcols = UInt(tiny_iterator_bitwidth.W) val kchs = UInt(large_iterator_bitwidth.W) val lpad = UInt(tiny_iterator_bitwidth.W) val rpad = UInt(tiny_iterator_bitwidth.W) val upad = UInt(tiny_iterator_bitwidth.W) val dpad = UInt(tiny_iterator_bitwidth.W) val plpad = UInt(tiny_iterator_bitwidth.W) val prad = UInt(tiny_iterator_bitwidth.W) val pupad = UInt(tiny_iterator_bitwidth.W) val pdpad = UInt(tiny_iterator_bitwidth.W) val orows = UInt(small_iterator_bitwidth.W) val ocols = UInt(small_iterator_bitwidth.W) } class LoopConvDerivedParams(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int) extends Bundle { val ochs = UInt(large_iterator_bitwidth.W) val irows = UInt(small_iterator_bitwidth.W) val icols = UInt(small_iterator_bitwidth.W) val irows_unpadded = UInt(small_iterator_bitwidth.W) val icols_unpadded = UInt(small_iterator_bitwidth.W) val ichs = UInt(large_iterator_bitwidth.W) val out_channels_per_bank = UInt(small_iterator_bitwidth.W) // TODO this won't work for systolic arrays above 256 in size val in_channels_per_bank = UInt(small_iterator_bitwidth.W) // TODO this won't work for systolic arrays above 256 in size val bias_spad_stride = UInt(large_iterator_bitwidth.W) val input_spad_stride = UInt(large_iterator_bitwidth.W) val weight_spad_stride = UInt(large_iterator_bitwidth.W) // val ex_overwrite = Bool() } class LoopConvLdBiasReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_start = UInt(log2Up(max_acc_addr).W) val dram_addr = UInt(coreMaxAddrBits.W) val no_bias = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvLdBias(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_acc_addr: Int, acc_w: Int, max_block_len_acc: Int, concurrent_loops: Int, latency: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2)(implicit p: Parameters) extends Module { val MVIN_SCALE_IDENTITY = 0x3f800000.U // TODO get this from configs somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvLdBiasReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val wait_for_prev_loop = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, ld = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvLdBiasReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops)) import req.inner_bounds._ import req.derived_params._ val acc_addr_start = req.addr_start // Derived parameters val max_ochs_per_mvin = Mux(ochs < (max_block_len_acc * block_size).U, ochs, (max_block_len_acc * block_size).U) val skip = req.dram_addr === 0.U // Iterators val b = Reg(UInt(large_iterator_bitwidth.W)) val orow = Reg(UInt(small_iterator_bitwidth.W)) val ocol = Reg(UInt(small_iterator_bitwidth.W)) val och = Reg(UInt(large_iterator_bitwidth.W)) // Addresses val dram_offset = och * (acc_w/8).U val dram_addr = Mux(req.no_bias, 0.U, req.dram_addr + LoopConv.castDramOffset(dram_offset)) val spad_addr = acc_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol // Sizes val I = Mux(ocols - ocol > block_size.U, block_size.U, ocols - ocol) val J = Mux(ochs - och > max_ochs_per_mvin, max_ochs_per_mvin, ochs - och) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = UInt() val I = UInt() val J = UInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_mvin_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.scale := MVIN_SCALE_IDENTITY config_cmd_rs1.stride := req.derived_params.bias_spad_stride config_cmd_rs1.pixel_repeats := 1.U config_cmd_rs1.state_id := 2.U config_cmd_rs1.shrink := 0.U config_cmd_rs1._unused := 1.U config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := 0.U val mvin_cmd = Wire(new RoCCCommand) mvin_cmd := DontCare mvin_cmd.inst.funct := LOAD3_CMD mvin_cmd.rs1 := 0.U mvin_cmd.rs2 := 0.U // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !io.wait_for_prev_loop && !skip command_p.io.in.bits.cmd := Mux(state === config, config_cmd, mvin_cmd) command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.I := I command_p.io.in.bits.J := J command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === LOAD3_CMD) { val o = command_p.io.out.bits io.cmd.bits.rs1 := o.dram_addr val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType) mvin_cmd_rs2 := DontCare mvin_cmd_rs2.num_rows := o.I.asUInt mvin_cmd_rs2.num_cols := o.J.asUInt mvin_cmd_rs2.local_addr := cast_to_acc_addr(mvin_cmd_rs2.local_addr, o.spad_addr, accumulate = false.B, read_full = false.B) io.cmd.bits.rs2 := mvin_cmd_rs2.asUInt } // Sending outputs when (skip) { state := idle }.elsewhen(command_p.io.in.fire) { when (state === config) { state := ld }.otherwise { val next_och = floorAdd(och, max_ochs_per_mvin, ochs) val next_ocol = floorAdd(ocol, block_size.U, ocols, next_och === 0.U) val next_orow = floorAdd(orow, 1.U, orows, next_ocol === 0.U && next_och === 0.U) val next_b = floorAdd(b, 1.U, batches, next_orow === 0.U && next_ocol === 0.U && next_och === 0.U) och := next_och ocol := next_ocol orow := next_orow b := next_b state := Mux(next_b === 0.U && next_orow === 0.U && next_ocol === 0.U && next_och === 0.U, idle, ld) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := config b := 0.U orow := 0.U ocol := 0.U och := 0.U } } class LoopConvLdInputReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_start = UInt(log2Up(max_acc_addr).W) val dram_addr = UInt(coreMaxAddrBits.W) val downsample = Bool() val max_pixels_per_row = UInt(small_iterator_bitwidth.W) val input_dilated = Bool() val trans_input_3120 = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvLdInput(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_addr: Int, input_w: Int, max_block_len: Int, concurrent_loops: Int, latency: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2) (implicit p: Parameters) extends Module { val MVIN_SCALE_IDENTITY = 0x3f800000.U // TODO get this from configs somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvLdInputReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val wait_for_prev_loop = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, ld = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvLdInputReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ def undilated(x: UInt): UInt = (x +& req.input_dilated) >> req.input_dilated // Derived parameters val max_ichs_per_mvin = Mux(ichs < (max_block_len * block_size).U, ichs, (max_block_len * block_size).U).zext val max_batches_per_mvin = Mux(batches < (max_block_len * block_size).U, batches, (max_block_len * block_size).U).zext val max_chs_per_mvin = Mux(req.trans_input_3120, max_batches_per_mvin, max_ichs_per_mvin) // Iterators val b = Reg(SInt(large_iterator_bitwidth.W)) val irow = Reg(SInt(small_iterator_bitwidth.W)) val icol = Reg(SInt(small_iterator_bitwidth.W)) val ich = Reg(SInt(large_iterator_bitwidth.W)) // Calculated params val irow_padded = irow +& undilated(upad).zext val icol_padded = icol +& undilated(lpad).zext val is_zeros = irow < 0.S \|\| irow >= irows_unpadded.zext \|\| icol < 0.S \|\| icol >= icols_unpadded.zext val dram_stride = Mux(req.trans_input_3120, batch_size * (input_w/8).U, in_stride * (input_w/8).U) // Addresses val dram_offset = Mux(req.trans_input_3120, (((ich * in_col_dim * in_row_dim +& irowin_col_dim +& icol) batches +& b) * (input_w/8).U).asUInt, (((b * in_row_dim * in_col_dim +& irowin_col_dim +& icol) in_stride +& ich) * (input_w/8).U).asUInt) val dram_addr = Mux(is_zeros, 0.U, req.dram_addr + LoopConv.castDramOffset(dram_offset)) val spad_addr = Mux(req.trans_input_3120, // To prevent Verilator errors, we replace some "/ block_size.U" calls here with ">> log2Up(block_size)" req.addr_start.zext +& (b >> log2Up(block_size)) * input_spad_stride +& ich * (irows >> req.downsample) * (icols >> req.downsample) +& (irow_padded >> req.downsample) * (icols >> req.downsample) +& (icol_padded >> req.downsample), req.addr_start.zext +& (ich >> log2Up(block_size)) * input_spad_stride +& b * (irows >> req.downsample) * (icols >> req.downsample) +& (irow_padded >> req.downsample) * (icols >> req.downsample) +& (icol_padded >> req.downsample)) // Sizes val block_size_downsampled = (block_size.U << req.downsample).asUInt.zext val I = MuxCase( Mux(icols_unpadded.zext -& icol > block_size_downsampled, block_size_downsampled, icols_unpadded.zext -& icol), Seq( (icol < 0.S) -> Mux((0.S-&icol) > block_size.S, block_size.S, 0.S-&icol), (icol >= icols_unpadded.zext) -> Mux(icols_unpadded.zext +& undilated(rpad).zext -& icol > block_size.S, block_size.S, icols_unpadded.zext +& undilated(rpad).zext -& icol) ) ) val K = Mux(req.trans_input_3120, Mux(batches.zext -& b > max_chs_per_mvin, max_chs_per_mvin, batches.zext -& b), Mux(ichs.zext -& ich > max_chs_per_mvin, max_chs_per_mvin, ichs.zext -& ich)) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = SInt() val I = SInt() val K = SInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_mvin_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.scale := MVIN_SCALE_IDENTITY config_cmd_rs1.stride := input_spad_stride config_cmd_rs1.pixel_repeats := req.max_pixels_per_row config_cmd_rs1.state_id := 0.U config_cmd_rs1.shrink := 0.U config_cmd_rs1._unused := 1.U config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := dram_stride << req.downsample val mvin_cmd = Wire(new RoCCCommand) mvin_cmd := DontCare mvin_cmd.inst.funct := LOAD_CMD mvin_cmd.rs1 := 0.U // dram_addr mvin_cmd.rs2 := 0.U // mvin_cmd_rs2 // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !io.wait_for_prev_loop && (req.dram_addr =/= 0.U) command_p.io.in.bits.cmd := Mux(state === config, config_cmd, mvin_cmd) command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.I := I command_p.io.in.bits.K := K command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === LOAD_CMD) { val o = command_p.io.out.bits io.cmd.bits.rs1 := o.dram_addr val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType) mvin_cmd_rs2 := DontCare mvin_cmd_rs2.num_rows := (o.I >> req.downsample).asUInt mvin_cmd_rs2.num_cols := o.K.asUInt mvin_cmd_rs2.local_addr := cast_to_sp_addr(mvin_cmd_rs2.local_addr, o.spad_addr) io.cmd.bits.rs2 := mvin_cmd_rs2.asUInt } // Sending outputs when(req.dram_addr === 0.U){ state := idle }.elsewhen(command_p.io.in.fire) { when (state === config) { state := ld }.otherwise { val b_it = Mux(req.trans_input_3120, max_chs_per_mvin.asUInt, 1.U) val ich_it = Mux(req.trans_input_3120, 1.U, max_chs_per_mvin.asUInt) val next_ich = sFloorAdd(ich, ich_it, ichs.zext, 0.S) val next_icol = sFloorAdd(icol, I.asUInt, (icols_unpadded +& undilated(rpad)).zext, 0.S-&undilated(lpad).zext, next_ich === 0.S) val next_irow = sFloorAdd(irow, 1.U << req.downsample, (irows_unpadded +& undilated(dpad)).zext, 0.S-&undilated(upad).zext, next_icol === 0.S-&undilated(lpad).zext && next_ich === 0.S) val next_b = sFloorAdd(b, b_it, batches.zext, 0.S, next_irow === 0.S-&undilated(upad).zext && next_icol === 0.S-&undilated(lpad).zext && next_ich === 0.S) ich := next_ich icol := next_icol irow := next_irow b := next_b state := Mux(next_b === 0.S && next_irow === 0.S-&undilated(upad).zext && next_icol === 0.S-&undilated(lpad).zext && next_ich === 0.S, idle, ld) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := config b := 0.S irow := 0.S -& ((io.req.bits.inner_bounds.upad +& io.req.bits.input_dilated) >> io.req.bits.input_dilated).zext icol := 0.S -& ((io.req.bits.inner_bounds.lpad +& io.req.bits.input_dilated) >> io.req.bits.input_dilated).zext ich := 0.S } } class LoopConvLdWeightReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_end = UInt(log2Up(max_addr+1).W) val dram_addr = UInt(coreMaxAddrBits.W) val trans_weight_1203 = Bool() val trans_weight_0132 = Bool() val dw = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvLdWeight(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_addr: Int, input_w: Int, max_block_len: Int, concurrent_loops: Int, latency: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2)(implicit p: Parameters) extends Module { val MVIN_SCALE_IDENTITY = 0x3f800000.U // TODO get this from configs somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvLdWeightReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val wait_for_prev_loop = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, ld = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvLdWeightReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ // Derived parameters val max_chs_per_mvin = { val max_ochs_per_mvin = Mux(ochs < (max_block_len * block_size).U, ochs, (max_block_len * block_size).U) val max_kchs_per_mvin = Mux(kchs < (max_block_len * block_size).U, kchs, (max_block_len * block_size).U) Mux(req.trans_weight_0132, max_kchs_per_mvin, max_ochs_per_mvin) } val B_rows = Mux(req.trans_weight_0132, in_channels_per_bank * kcols * krows * ochs, out_channels_per_bank * kcols * krows * kchs) val addr_start = req.addr_end - B_rows val dram_stride = MuxCase(weight_stride, Seq( req.dw -> 1.U, req.trans_weight_1203 -> (kernel_dim * kernel_dim * out_channels), req.trans_weight_0132 -> in_channels )) * (input_w/8).U // Iterators val och = Reg(UInt(large_iterator_bitwidth.W)) val krow = Reg(UInt(tiny_iterator_bitwidth.W)) val kcol = Reg(UInt(tiny_iterator_bitwidth.W)) val kch = Reg(UInt(large_iterator_bitwidth.W)) // Addresses val dram_offset = MuxCase(((krowkernel_dimin_channels +& kcolin_channels +& kch) weight_stride +& och) * (input_w/8).U, Seq( req.dw -> (krow * kernel_dim +& kcol) * (input_w/8).U, req.trans_weight_1203 -> (((kchkernel_dimkernel_dim +& krowkernel_dim +& kcol) out_channels +& och) * (input_w/8).U), req.trans_weight_0132 -> (((krowkernel_dimout_channels +& kcolout_channels +& och) in_channels +& kch) * (input_w/8).U) )) val dram_addr = req.dram_addr + LoopConv.castDramOffset(dram_offset) val spad_addr = Mux(req.trans_weight_0132, // The width expansions are added here solely to prevent Verilator's "WIDTH" warnings, despite making the code uglier addr_start + (kch / block_size.U(kch.getWidth.W)) * krows * kcols * ochs + krow * kcols * ochs + kcol * ochs + och, addr_start + (och / block_size.U(och.getWidth.W)) * krows * kcols * kchs + krow * kcols * kchs + kcol * kchs + kch) // Sizes val J = Mux(req.trans_weight_0132, Mux(kchs - kch > max_chs_per_mvin, max_chs_per_mvin, kchs - kch), Mux(ochs - och > max_chs_per_mvin, max_chs_per_mvin, ochs - och)) val K = Mux(req.trans_weight_0132, Mux(ochs - och > block_size.U, block_size.U, ochs - och), Mux(kchs - kch > block_size.U, block_size.U, kchs - kch)) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = UInt() val K = UInt() val J = UInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_mvin_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.scale := MVIN_SCALE_IDENTITY config_cmd_rs1.stride := req.derived_params.weight_spad_stride config_cmd_rs1.pixel_repeats := 1.U config_cmd_rs1.state_id := 1.U config_cmd_rs1.shrink := 0.U config_cmd_rs1._unused := 1.U config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := dram_stride val mvin_cmd = Wire(new RoCCCommand) mvin_cmd := DontCare mvin_cmd.inst.funct := LOAD2_CMD mvin_cmd.rs1 := 0.U // dram_addr mvin_cmd.rs2 := 0.U // mvin_cmd_rs2 // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !io.wait_for_prev_loop && (req.dram_addr =/= 0.U) command_p.io.in.bits.cmd := Mux(state === config, config_cmd, mvin_cmd) command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.K := K command_p.io.in.bits.J := J command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === LOAD2_CMD) { val o = command_p.io.out.bits io.cmd.bits.rs1 := o.dram_addr val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType) mvin_cmd_rs2 := DontCare mvin_cmd_rs2.num_rows := o.K mvin_cmd_rs2.num_cols := o.J mvin_cmd_rs2.local_addr := cast_to_sp_addr(mvin_cmd_rs2.local_addr, o.spad_addr) io.cmd.bits.rs2 := mvin_cmd_rs2.asUInt } // Sending outputs when(req.dram_addr === 0.U){ state := idle }.elsewhen(command_p.io.in.fire) { when (state === config) { state := ld }.otherwise { val och_it = Mux(req.trans_weight_0132, block_size.U, max_chs_per_mvin) val kch_it = Mux(req.trans_weight_0132, max_chs_per_mvin, block_size.U) val next_kch = floorAdd(kch, kch_it, kchs) val next_kcol = floorAdd(kcol, 1.U, kcols, next_kch === 0.U) val next_krow = floorAdd(krow, 1.U, krows, next_kcol === 0.U && next_kch === 0.U) val next_och = floorAdd(och, och_it, ochs, next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U) kch := next_kch kcol := next_kcol krow := next_krow och := next_och state := Mux(next_och === 0.U && next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U, idle, ld) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := config kch := 0.U kcol := 0.U krow := 0.U och := 0.U } } class LoopConvExecuteReq(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_addr: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val a_addr_start = UInt(log2Up(max_addr).W) val b_addr_end = UInt(log2Up(max_addr+1).W) val c_addr_start = UInt(log2Up(max_acc_addr).W) val wrot180 = Bool() val downsample = Bool() val max_pixels_per_row = UInt(small_iterator_bitwidth.W) val input_dilated = Bool() val trans_weight_0132 = Bool() val trans_input_3120 = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvExecute(block_size: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_addr: Int, max_acc_addr: Int, concurrent_loops: Int, latency: Int, config_ex_rs1_t: ConfigExRs1, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs, compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs)(implicit p: Parameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvExecuteReq(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val lda_completed = Input(Bool()) val ldb_completed = Input(Bool()) val ldd_completed = Input(Bool()) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, pre, comp = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvExecuteReq(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ def undilated(x: UInt): UInt = (x +& req.input_dilated) >> req.input_dilated // Derived parameters val B_rows = Mux(req.trans_weight_0132, in_channels_per_bank * kcols * krows * ochs, out_channels_per_bank * kcols * krows * kchs) val a_addr_start = req.a_addr_start val b_addr_start = req.b_addr_end - B_rows val c_addr_start = /(BigInt(3) << 30).U \|/ req.c_addr_start // Iterators val och = Reg(UInt(large_iterator_bitwidth.W)) val krow = Reg(UInt(tiny_iterator_bitwidth.W)) val kcol = Reg(UInt(tiny_iterator_bitwidth.W)) val kch = Reg(UInt(large_iterator_bitwidth.W)) val b = Reg(UInt(large_iterator_bitwidth.W)) val orow = Reg(UInt(small_iterator_bitwidth.W)) val ocol = Reg(UInt(small_iterator_bitwidth.W)) // TODO kernel-dilation and input-dilation can never be activated at the same time, so we can optimize out some multiplications by kernel_dilation val skip_iteration = state >= pre && req.input_dilated && (((krow * kernel_dilation +& orow -& upad)(0) & req.input_dilated).asBool \|\| ((kcol * kernel_dilation +& ocol -& lpad)(0) & req.input_dilated).asBool) val pixels = Mux(kcols - kcol > req.max_pixels_per_row, req.max_pixels_per_row, kcols - kcol) val irow = undilated(orow * stride +& krow * kernel_dilation) val icol = undilated(ocol * stride +& kcol * kernel_dilation) val I = Mux(req.trans_input_3120, Mux(batches - b > block_size.U, block_size.U, batches - b), undilated(Mux(ocols - ocol > (block_size.U << req.input_dilated).asUInt, (block_size.U << req.input_dilated).asUInt, ocols - ocol))) val J = Mux(ochs - och > block_size.U, block_size.U, ochs - och) val K = pixels * Mux(kchs - kch > block_size.U, block_size.U, kchs - kch) // Addresses val a_addr = Mux(req.trans_input_3120, a_addr_start +& (b / block_size.U) * input_spad_stride +& kch * (irows >> req.downsample) * (icols >> req.downsample) +& (irow >> req.downsample) * (icols >> req.downsample) +& (icol >> req.downsample), a_addr_start +& (kch / block_size.U(kch.getWidth.W)) * input_spad_stride +& b * (irows >> req.downsample) * (icols >> req.downsample) +& (irow >> req.downsample) * (icols >> req.downsample) +& (icol >> req.downsample)) // val c_addr = Mux(ex_overwrite && krow === 0.U && kcol === 0.U && kch === 0.U, d_addr_start, c_addr_start) +& // (och / block_size.U) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol // The width expansions are added here solely to prevent Verilator's "WIDTH" warnings, despite making the code uglier val c_addr = c_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol // val new_weights = b === 0.U && orow === 0.U && ocol === 0.U val new_weights = Reg(Bool()) val krow_rot = Mux(req.wrot180, krows - krow - 1.U, krow) val kcol_rot = Mux(req.wrot180, kcols - kcol - 1.U, kcol) val b_addr = Mux(req.trans_weight_0132, b_addr_start +& (kch / block_size.U(och.getWidth.W)) * krows * kcols * ochs +& krow_rot * kcols * ochs +& kcol_rot * ochs +& och, b_addr_start +& (och / block_size.U(och.getWidth.W)) * krows * kcols * kchs +& krow_rot * kcols * kchs +& kcol_rot * kchs +& kch) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val a_addr = UInt() val b_addr = UInt() val c_addr = UInt() val I = UInt() val J = UInt() val K = UInt() val new_weights = Bool() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_ex_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.a_stride := (irows * icols).asUInt config_cmd_rs1.set_only_strides := 1.U config_cmd_rs1.cmd_type := 0.U val config_cmd_rs2 = Wire(new ConfigExRs2) config_cmd_rs2 := DontCare config_cmd_rs2.c_stride := (orows * ocols).asUInt config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := config_cmd_rs2.asUInt val pre_cmd = Wire(new RoCCCommand) // preload pre_cmd := DontCare pre_cmd.inst.funct := PRELOAD_CMD pre_cmd.rs1 := 0.U//(K << 48) \| (J << 32) \| pre_addr pre_cmd.rs2 := 0.U//(I << 48) \| (J << 32) \| c_addr val comp_cmd = Wire(new RoCCCommand()) // compute.preloaded comp_cmd := DontCare comp_cmd.inst.funct := Mux(new_weights, COMPUTE_AND_FLIP_CMD, COMPUTE_AND_STAY_CMD) comp_cmd.rs1 := 0.U//(I << 48) \| (K << 32) \| a_addr comp_cmd.rs2 := 0.U//(I << 48) \| (J << 32) \| GARBAGE_ADDR val ld_ahead = io.lda_completed && io.ldb_completed && io.ldd_completed // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !skip_iteration && ld_ahead command_p.io.in.bits.cmd := MuxCase(config_cmd, Seq((state === pre) -> pre_cmd, (state === comp) -> comp_cmd)) command_p.io.in.bits.a_addr := a_addr command_p.io.in.bits.b_addr := b_addr command_p.io.in.bits.c_addr := c_addr command_p.io.in.bits.I := I command_p.io.in.bits.J := J command_p.io.in.bits.K := K command_p.io.in.bits.new_weights := new_weights command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === PRELOAD_CMD) { val o = command_p.io.out.bits val pre_cmd_rs1 = Wire(preload_rs1_t.cloneType) pre_cmd_rs1 := DontCare pre_cmd_rs1.num_rows := o.K.asUInt pre_cmd_rs1.num_cols := o.J.asUInt pre_cmd_rs1.local_addr := Mux(o.new_weights, cast_to_sp_addr(pre_cmd_rs1.local_addr, o.b_addr), garbage_addr(pre_cmd_rs1.local_addr)) val pre_cmd_rs2 = Wire(preload_rs2_t.cloneType) pre_cmd_rs2 := DontCare pre_cmd_rs2.num_rows := o.I.asUInt pre_cmd_rs2.num_cols := o.J.asUInt pre_cmd_rs2.local_addr := cast_to_acc_addr(pre_cmd_rs2.local_addr, o.c_addr, accumulate = true.B, read_full = false.B) io.cmd.bits.rs1 := pre_cmd_rs1.asUInt io.cmd.bits.rs2 := pre_cmd_rs2.asUInt }.elsewhen(command_p.io.out.bits.cmd.inst.funct =/= CONFIG_CMD) { val o = command_p.io.out.bits val comp_cmd_rs1 = Wire(compute_rs1_t.cloneType) comp_cmd_rs1 := DontCare comp_cmd_rs1.num_rows := o.I.asUInt comp_cmd_rs1.num_cols := o.K.asUInt comp_cmd_rs1.local_addr := cast_to_sp_addr(comp_cmd_rs1.local_addr, o.a_addr) val comp_cmd_rs2 = Wire(compute_rs2_t.cloneType) comp_cmd_rs2 := DontCare comp_cmd_rs2.num_rows := o.I.asUInt comp_cmd_rs2.num_cols := o.J.asUInt comp_cmd_rs2.local_addr := garbage_addr(comp_cmd_rs2.local_addr) io.cmd.bits.rs1 := comp_cmd_rs1.asUInt io.cmd.bits.rs2 := comp_cmd_rs2.asUInt } // Updating "new_weights" when (state === comp && command_p.io.in.fire) { new_weights := false.B } // Sending outputs when (command_p.io.in.fire \|\| skip_iteration) { when (state === config) { state := pre }.elsewhen (state === pre) { state := comp }.otherwise { val b_it = Mux(req.trans_input_3120, block_size.U, 1.U) val ocol_it = Mux(skip_iteration \|\| req.trans_input_3120, 1.U, block_size.U << req.input_dilated).asUInt val next_ocol = floorAdd(ocol, ocol_it, ocols) val next_orow = floorAdd(orow, 1.U, orows, next_ocol === 0.U) val next_b = floorAdd(b, b_it, batches, next_orow === 0.U && next_ocol === 0.U) val next_kch = floorAdd(kch, block_size.U, kchs, next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) val next_kcol = floorAdd(kcol, req.max_pixels_per_row, kcols, next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) val next_krow = floorAdd(krow, 1.U, krows, next_kcol === 0.U && next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) val next_och = floorAdd(och, block_size.U, ochs, next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) ocol := next_ocol orow := next_orow b := next_b kch := next_kch kcol := next_kcol krow := next_krow och := next_och when (next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) { new_weights := true.B } state := Mux(next_och === 0.U && next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U, idle, pre) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := Mux(io.req.bits.trans_input_3120, config, pre) b := 0.U orow := 0.U ocol := 0.U och := 0.U krow := 0.U kcol := 0.U kch := 0.U new_weights := true.B } } class LoopConvStReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_start = UInt(log2Up(max_acc_addr).W) val dram_addr = UInt(coreMaxAddrBits.W) val no_pool = Bool() val activation = UInt(2.W) // TODO magic number val trans_output_1203 = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvSt(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_acc_addr: Int, input_w: Int, concurrent_loops: Int, latency: Int, config_mvout_rs2_t: ConfigMvoutRs2, mvout_rs2_t: MvoutRs2)(implicit p: Parameters) extends Module { val ACC_SCALE_NO_CHANGE = ~(0.U(32.W)) // TODO get this from ISA description somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvStReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val ex_completed = Input(Bool()) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, st, pre_pool_config, pool, post_pool_config = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvStReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ val acc_addr_start = req.addr_start // Derived parameters val skip = req.dram_addr === 0.U // Iterators val b = Reg(UInt(large_iterator_bitwidth.W)) val orow = Reg(UInt(small_iterator_bitwidth.W)) val ocol = Reg(UInt(small_iterator_bitwidth.W)) val och = Reg(UInt(large_iterator_bitwidth.W)) // Addresses val dram_offset = Mux(req.trans_output_1203, ((orowout_col_dimbatch_size +& ocolbatch_size +& b) out_channels +& och) * (input_w/8).U, ((bout_row_dimout_col_dim +& orowout_col_dim +& ocol) out_stride +& och) * (input_w/8).U) val dram_addr = req.dram_addr + LoopConv.castDramOffset(dram_offset) val spad_addr = acc_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol val pool_dram_addr = req.dram_addr + ((b * pool_out_col_dim * pool_out_row_dim) * out_stride + och) * (input_w/8).U val pool_spad_addr = acc_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols // Sizes val I = Mux(ocols - ocol > block_size.U, block_size.U, ocols - ocol) val J = Mux(ochs - och > block_size.U, block_size.U, ochs - och) val channels = J class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = UInt() val pool_dram_addr = UInt() val pool_spad_addr = UInt() val channels = UInt() val is_pool = Bool() val I = UInt() val J = UInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val mvout_cmd = Wire(new RoCCCommand) mvout_cmd := DontCare mvout_cmd.inst.funct := STORE_CMD mvout_cmd.rs1 := 0.U // dram_addr mvout_cmd.rs2 := 0.U // mvout_cmd_rs2 val pre_pool_config_cmd = Wire(new RoCCCommand) pre_pool_config_cmd := DontCare pre_pool_config_cmd.inst.funct := CONFIG_CMD val pre_pool_config_cmd_rs1 = Wire(new ConfigMvoutRs1) pre_pool_config_cmd_rs1 := DontCare pre_pool_config_cmd_rs1.ocols := ocols pre_pool_config_cmd_rs1.orows := orows pre_pool_config_cmd_rs1.pocols := pocols pre_pool_config_cmd_rs1.porows := porows pre_pool_config_cmd_rs1.pool_out_dim := pool_out_col_dim pre_pool_config_cmd_rs1.lpad := plpad pre_pool_config_cmd_rs1.upad := pupad pre_pool_config_cmd_rs1.pool_size := pool_size pre_pool_config_cmd_rs1.pool_stride := pool_stride pre_pool_config_cmd_rs1.activation := req.activation pre_pool_config_cmd_rs1.cmd_type := CONFIG_STORE pre_pool_config_cmd.rs1 := pre_pool_config_cmd_rs1.asUInt val pre_pool_config_cmd_rs2 = Wire(config_mvout_rs2_t.cloneType) pre_pool_config_cmd_rs2 := DontCare pre_pool_config_cmd_rs2.acc_scale := ACC_SCALE_NO_CHANGE pre_pool_config_cmd_rs2.stride := out_stride * (input_w / 8).U pre_pool_config_cmd.rs2 := pre_pool_config_cmd_rs2.asUInt val post_pool_config_cmd = Wire(new RoCCCommand) post_pool_config_cmd := DontCare post_pool_config_cmd.inst.funct := CONFIG_CMD val post_pool_config_cmd_rs1 = Wire(new ConfigMvoutRs1) post_pool_config_cmd_rs1 := DontCare post_pool_config_cmd_rs1.activation := req.activation post_pool_config_cmd_rs1.cmd_type := CONFIG_STORE post_pool_config_cmd.rs1 := post_pool_config_cmd_rs1.asUInt val post_pool_config_cmd_rs2 = Wire(config_mvout_rs2_t.cloneType) post_pool_config_cmd_rs2 := DontCare post_pool_config_cmd_rs2.acc_scale := ACC_SCALE_NO_CHANGE post_pool_config_cmd_rs2.stride := out_stride * (input_w / 8).U post_pool_config_cmd.rs2 := post_pool_config_cmd_rs2.asUInt val pool_cmd = Wire(new RoCCCommand) pool_cmd := DontCare pool_cmd.inst.funct := STORE_CMD pool_cmd.rs1 := 0.U//pool_dram_addr pool_cmd.rs2 := 0.U//(channels << 32.U) \| pool_spad_addr // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !skip && io.ex_completed command_p.io.in.bits.cmd := MuxLookup(state.asUInt, mvout_cmd)(Seq( pre_pool_config.asUInt -> pre_pool_config_cmd, pool.asUInt -> pool_cmd, post_pool_config.asUInt -> post_pool_config_cmd) ) command_p.io.in.bits.is_pool := state === pool command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.pool_spad_addr := pool_spad_addr command_p.io.in.bits.pool_dram_addr := pool_dram_addr command_p.io.in.bits.channels := channels command_p.io.in.bits.I := I command_p.io.in.bits.J := J command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === STORE_CMD) { val o = command_p.io.out.bits when (o.is_pool) { val pool_mvout_cmd_rs2 = Wire(mvout_rs2_t.cloneType) pool_mvout_cmd_rs2 := DontCare pool_mvout_cmd_rs2.num_cols := o.channels pool_mvout_cmd_rs2.local_addr := cast_to_acc_addr(pool_mvout_cmd_rs2.local_addr, o.pool_spad_addr, accumulate = false.B, read_full = false.B) io.cmd.bits.rs1 := o.pool_dram_addr io.cmd.bits.rs2 := pool_mvout_cmd_rs2.asUInt } .otherwise { val mvout_cmd_rs2 = Wire(mvout_rs2_t.cloneType) mvout_cmd_rs2 := DontCare mvout_cmd_rs2.num_rows := o.I.asUInt mvout_cmd_rs2.num_cols := o.J.asUInt mvout_cmd_rs2.local_addr := cast_to_acc_addr(mvout_cmd_rs2.local_addr, o.spad_addr, accumulate = false.B, read_full = false.B) io.cmd.bits.rs1 := o.dram_addr io.cmd.bits.rs2 := mvout_cmd_rs2.asUInt } } // Sending outputs when (skip) { state := idle }.elsewhen(command_p.io.in.fire) { when (req.no_pool) { val next_och = floorAdd(och, block_size.U, ochs) val next_ocol = floorAdd(ocol, block_size.U, ocols, next_och === 0.U) val next_orow = floorAdd(orow, 1.U, orows, next_ocol === 0.U && next_och === 0.U) val next_b = floorAdd(b, 1.U, batches, next_orow === 0.U && next_ocol === 0.U && next_och === 0.U) och := next_och ocol := next_ocol orow := next_orow b := next_b state := Mux(next_b === 0.U && next_orow === 0.U && next_ocol === 0.U && next_och === 0.U, idle, st) }.elsewhen(state === pre_pool_config) { state := pool }.elsewhen(state === post_pool_config) { state := idle }.otherwise { val next_och = floorAdd(och, block_size.U, ochs) val next_b = floorAdd(b, 1.U, batches, next_och === 0.U) och := next_och b := next_b state := Mux(next_b === 0.U && next_och === 0.U, post_pool_config, pool) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := Mux(io.req.bits.no_pool, st, pre_pool_config) b := 0.U orow := 0.U ocol := 0.U och := 0.U } } class LoopConvState(val block_size: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val coreMaxAddrBits: Int, val max_addr: Int, val max_acc_addr: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val bias_dram_addr = UInt(coreMaxAddrBits.W) val weights_dram_addr = UInt(coreMaxAddrBits.W) val input_dram_addr = UInt(coreMaxAddrBits.W) val output_dram_addr = UInt(coreMaxAddrBits.W) val no_bias = Bool() val wrot180 = Bool() val no_pool = Bool() val downsample = Bool() val input_dilated = Bool() val activation = UInt(2.W) // TODO magic number val trans_output_1203 = Bool() val trans_weight_1203 = Bool() val trans_weight_0132 = Bool() val trans_input_3120 = Bool() val dw = Bool() val max_pixels_per_row = UInt(small_iterator_bitwidth.W) val a_ex_spad_id = UInt(2.W) val b_ex_spad_id = UInt(2.W) val configured = Bool() val running = Bool() val ld_bias_started = Bool() val ld_input_started = Bool() val ld_weights_started = Bool() val ex_started = Bool() val st_started = Bool() val ld_bias_completed = Bool() val ld_input_completed = Bool() val ld_weights_completed = Bool() val ex_completed = Bool() val st_completed = Bool() def all_completed(dummy: Int=0): Bool = ld_bias_completed && ld_input_completed && ld_weights_completed && ex_completed && st_completed val a_addr_start = UInt(log2Up(max_addr).W) val b_addr_end = UInt(log2Up(max_addr+1).W) def derived_params(dummy: Int=0): LoopConvDerivedParams = { import outer_bounds.{stride, kernel_dilation} import inner_bounds.{batches, pochs, orows, ocols, krows, kcols, upad, dpad, lpad, rpad, kchs} val result = Wire(new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)) result.ochs := pochs val dilated_krows = krows + (kernel_dilation - 1.U)(krows - 1.U) val dilated_kcols = kcols + (kernel_dilation - 1.U)(kcols - 1.U) val irows_without_dilation = orows * stride +& dilated_krows -& 1.U val icols_without_dilation = ocols * stride +& dilated_kcols -& 1.U val irows_unpadded_without_dilation = irows_without_dilation -& upad -& dpad val icols_unpadded_without_dilation = icols_without_dilation -& lpad -& rpad def undilated(x: UInt): UInt = (x +& input_dilated) >> input_dilated val irows_unpadded = undilated(irows_unpadded_without_dilation) val icols_unpadded = undilated(icols_unpadded_without_dilation) result.irows := Mux(input_dilated, irows_unpadded +& undilated(upad) +& undilated(dpad), irows_without_dilation) result.icols := Mux(input_dilated, icols_unpadded +& undilated(lpad) +& undilated(rpad), icols_without_dilation) result.irows_unpadded := irows_unpadded result.icols_unpadded := icols_unpadded result.ichs := kchs result.out_channels_per_bank := result.ochs / block_size.U(result.ochs.getWidth.W) +& (result.ochs % block_size.U =/= 0.U) result.in_channels_per_bank := result.ichs / block_size.U(result.ochs.getWidth.W) +& (result.ichs % block_size.U =/= 0.U) result.bias_spad_stride := batches * orows * ocols result.input_spad_stride := Mux(trans_input_3120, result.ichs * (result.irows >> downsample) * (result.icols >> downsample), batches * (result.irows >> downsample) * (result.icols >> downsample)) result.weight_spad_stride := Mux(trans_weight_0132, krows * kcols * pochs, krows * kcols * kchs) // result.ex_overwrite := bias_dram_addr =/= 0.U && no_bias result } def reset(): Unit = { configured := false.B running := false.B ld_bias_started := false.B ld_input_started := false.B ld_weights_started := false.B ex_started := false.B st_started := false.B ld_bias_completed := false.B ld_input_completed := false.B ld_weights_completed := false.B ex_completed := false.B st_completed := false.B } } class LoopConv (block_size: Int, coreMaxAddrBits: Int, reservation_station_size: Int, max_lds: Int, max_exs: Int, max_sts: Int, max_addr: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, dma_max_bytes: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2, config_mvout_rs2_t: ConfigMvoutRs2, mvout_rs2_t: MvoutRs2, config_ex_rs1_t: ConfigExRs1, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs, compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs, has_training_convs: Boolean, has_max_pool: Boolean, has_first_layer_optimizations: Boolean, has_dw_convs: Boolean) (implicit p: Parameters) extends Module { val large_iterator_bitwidth = 16 val small_iterator_bitwidth = 16 // 8 val tiny_iterator_bitwidth = 16 // 4 val max_block_len = (dma_max_bytes / (block_size * (input_w / 8))) max 1 val max_block_len_acc = (dma_max_bytes / (block_size * (acc_w / 8))) max 1 val io = IO(new Bundle { val in = Flipped(Decoupled(new GemminiCmd(reservation_station_size))) val out = Decoupled(new GemminiCmd(reservation_station_size)) val ld_completed = Input(UInt(log2Up(reservation_station_size+1).W)) val st_completed = Input(UInt(log2Up(reservation_station_size+1).W)) val ex_completed = Input(UInt(log2Up(reservation_station_size+1).W)) val busy = Output(Bool()) }) // Create states val concurrent_loops = 2 val loops = Reg(Vec(concurrent_loops, new LoopConvState(block_size, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, coreMaxAddrBits, max_addr, max_acc_addr))) val head_loop_id = RegInit(0.U(log2Up(concurrent_loops).W)) val tail_loop_id = (~head_loop_id).asUInt // This is the loop that we always try to configure if available val head_loop = loops(head_loop_id) val tail_loop = loops(tail_loop_id) val loop_configured = loops.map(_.configured).reduce(_ \|\| _) val loop_being_configured_id = Mux(head_loop.configured, tail_loop_id, head_loop_id) val loop_being_configured = loops(loop_being_configured_id) // Create inner modules val latency = 2 val ld_bias = Module(new LoopConvLdBias(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_acc_addr, acc_w, max_block_len_acc, concurrent_loops, latency, config_mvin_rs1_t, mvin_rs2_t)) val ld_input = Module(new LoopConvLdInput(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, input_w, max_block_len, concurrent_loops, latency, config_mvin_rs1_t, mvin_rs2_t)) val ld_weights = Module(new LoopConvLdWeight(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, input_w, max_block_len, concurrent_loops, latency, config_mvin_rs1_t, mvin_rs2_t)) val ex = Module(new LoopConvExecute(block_size, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops, latency, config_ex_rs1_t, preload_rs1_t, preload_rs2_t, compute_rs1_t, compute_rs2_t)) val st = Module(new LoopConvSt(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_acc_addr, input_w, concurrent_loops, latency, config_mvout_rs2_t, mvout_rs2_t)) // Create command queue val cmd = Queue(io.in) io.busy := cmd.valid \|\| loop_configured // Create arbiter val arb = Module(new Arbiter(new RoCCCommand, 5)) arb.io.in(0) <> st.io.cmd arb.io.in(1) <> ex.io.cmd arb.io.in(2) <> ld_bias.io.cmd arb.io.in(3) <> ld_weights.io.cmd arb.io.in(4) <> ld_input.io.cmd val unrolled_cmd = arb.io.out // Create reservation station utilization counters val ld_utilization = RegInit(0.U(log2Up(max_lds+1).W)) val st_utilization = RegInit(0.U(log2Up(max_sts+1).W)) val ex_utilization = RegInit(0.U(log2Up(max_exs+1).W)) ld_utilization := ld_utilization +& (ld_bias.io.cmd.fire \|\| ld_weights.io.cmd.fire \|\| ld_input.io.cmd.fire) -& io.ld_completed st_utilization := st_utilization +& st.io.cmd.fire -& io.st_completed ex_utilization := ex_utilization +& ex.io.cmd.fire -& io.ex_completed assert(ld_utilization >= io.ld_completed, "ld utilization underflow") assert(st_utilization >= io.st_completed, "st utilization underflow") assert(ex_utilization >= io.ex_completed, "ex utilization underflow") // Wire up unrolled command output val is_loop_run_cmd = cmd.bits.cmd.inst.funct === LOOP_CONV_WS val is_loop_config_cmd = cmd.bits.cmd.inst.funct >= LOOP_CONV_WS_CONFIG_1 && cmd.bits.cmd.inst.funct <= LOOP_CONV_WS_CONFIG_6 val is_loop_cmd = is_loop_run_cmd \|\| is_loop_config_cmd io.out.bits.cmd := Mux(loop_configured, unrolled_cmd.bits, cmd.bits.cmd) io.out.bits.cmd.status := cmd.bits.cmd.status // TODO This is not guaranteed to be the correct fix! We must fix this io.out.bits.rob_id := DontCare io.out.bits.from_matmul_fsm := Mux(loop_configured, false.B, cmd.bits.from_matmul_fsm) io.out.bits.from_conv_fsm := Mux(loop_configured, true.B, cmd.bits.from_conv_fsm) io.out.valid := Mux(loop_configured, unrolled_cmd.valid, cmd.valid && !is_loop_config_cmd && !is_loop_run_cmd) cmd.ready := Mux(is_loop_cmd, !loop_being_configured.configured, !loop_configured && io.out.ready) arb.io.out.ready := io.out.ready // Wire up waiting-for-loads signals val ex_is_waiting_for_loads = loops(ex.io.loop_id).ex_started && !loops(ex.io.loop_id).ex_completed && !(loops(ex.io.loop_id).ld_input_completed && loops(ex.io.loop_id).ld_weights_completed && loops(ex.io.loop_id).ld_bias_completed) ld_bias.io.wait_for_prev_loop := ex_is_waiting_for_loads && ld_bias.io.loop_id =/= ex.io.loop_id ld_weights.io.wait_for_prev_loop := ex_is_waiting_for_loads && ld_weights.io.loop_id =/= ex.io.loop_id ld_input.io.wait_for_prev_loop := ex_is_waiting_for_loads && ld_input.io.loop_id =/= ex.io.loop_id // Wire up overloaded signals ld_bias.io.rob_overloaded := ld_utilization >= max_lds.U ld_input.io.rob_overloaded := ld_utilization >= max_lds.U ld_weights.io.rob_overloaded := ld_utilization >= max_lds.U ex.io.rob_overloaded := ex_utilization >= max_exs.U st.io.rob_overloaded := st_utilization >= max_sts.U // Wire up iterator inputs ex.io.lda_completed := (ld_input.io.loop_id =/= ex.io.loop_id) \|\| ld_input.io.idle ex.io.ldb_completed := (ld_weights.io.loop_id =/= ex.io.loop_id) \|\| ld_weights.io.idle ex.io.ldd_completed := (ld_bias.io.loop_id =/= ex.io.loop_id) \|\| ld_bias.io.idle st.io.ex_completed := (ex.io.loop_id =/= st.io.loop_id) \|\| ex.io.idle // Create config registers when(cmd.valid && is_loop_cmd && !loop_being_configured.configured) { switch (cmd.bits.cmd.inst.funct) { is (LOOP_CONV_WS_CONFIG_1) { loop_being_configured.outer_bounds.out_channels := cmd.bits.cmd.rs1(63, 48) loop_being_configured.outer_bounds.in_channels := cmd.bits.cmd.rs1(47, 32) loop_being_configured.outer_bounds.in_row_dim := cmd.bits.cmd.rs1(31, 16) loop_being_configured.outer_bounds.batch_size := cmd.bits.cmd.rs1(15, 0) loop_being_configured.outer_bounds.padding := cmd.bits.cmd.rs2(63, 56) loop_being_configured.outer_bounds.stride := cmd.bits.cmd.rs2(55, 48) loop_being_configured.outer_bounds.out_col_dim := cmd.bits.cmd.rs2(47, 32) loop_being_configured.outer_bounds.pool_out_row_dim := cmd.bits.cmd.rs2(31, 16) loop_being_configured.outer_bounds.out_row_dim := cmd.bits.cmd.rs2(15, 0) } is (LOOP_CONV_WS_CONFIG_2) { loop_being_configured.outer_bounds.kernel_dim := cmd.bits.cmd.rs1(63, 48) loop_being_configured.outer_bounds.pool_out_col_dim := cmd.bits.cmd.rs1(47, 32) loop_being_configured.outer_bounds.pool_size := (if (!has_max_pool) 1.U else cmd.bits.cmd.rs1(31, 16)) loop_being_configured.outer_bounds.pool_stride := (if (!has_max_pool) 1.U else cmd.bits.cmd.rs1(15, 8)) loop_being_configured.outer_bounds.pool_padding := (if (!has_max_pool) 0.U else cmd.bits.cmd.rs1(7, 0)) loop_being_configured.inner_bounds.batches := cmd.bits.cmd.rs2(63, 48) loop_being_configured.inner_bounds.porows := cmd.bits.cmd.rs2(47, 32) loop_being_configured.inner_bounds.pocols := cmd.bits.cmd.rs2(31, 16) loop_being_configured.inner_bounds.pochs := cmd.bits.cmd.rs2(15, 0) } is (LOOP_CONV_WS_CONFIG_3) { loop_being_configured.inner_bounds.krows := cmd.bits.cmd.rs1(63, 48) loop_being_configured.inner_bounds.kcols := cmd.bits.cmd.rs1(47, 32) loop_being_configured.inner_bounds.kchs := cmd.bits.cmd.rs1(31, 16) loop_being_configured.inner_bounds.lpad := cmd.bits.cmd.rs1(15, 0) loop_being_configured.inner_bounds.rpad := cmd.bits.cmd.rs2(63, 48) loop_being_configured.inner_bounds.upad := cmd.bits.cmd.rs2(47, 32) loop_being_configured.inner_bounds.dpad := cmd.bits.cmd.rs2(31, 24) loop_being_configured.inner_bounds.plpad := cmd.bits.cmd.rs2(23, 16) loop_being_configured.outer_bounds.in_col_dim := cmd.bits.cmd.rs2(15, 0) } is (LOOP_CONV_WS_CONFIG_4) { loop_being_configured.inner_bounds.orows := cmd.bits.cmd.rs1(63, 48) loop_being_configured.inner_bounds.prad := cmd.bits.cmd.rs1(47, 32) loop_being_configured.inner_bounds.pupad := cmd.bits.cmd.rs1(31, 21) loop_being_configured.inner_bounds.pdpad := cmd.bits.cmd.rs1(20, 10) loop_being_configured.outer_bounds.kernel_dilation := cmd.bits.cmd.rs1(9, 0) loop_being_configured.inner_bounds.ocols := cmd.bits.cmd.rs2(15, 0) loop_being_configured.outer_bounds.in_stride := cmd.bits.cmd.rs2(63, 48) loop_being_configured.outer_bounds.weight_stride := cmd.bits.cmd.rs2(47, 32) loop_being_configured.outer_bounds.out_stride := cmd.bits.cmd.rs2(31, 16) } is (LOOP_CONV_WS_CONFIG_5) { loop_being_configured.weights_dram_addr := cmd.bits.cmd.rs1 loop_being_configured.output_dram_addr := cmd.bits.cmd.rs2 } is (LOOP_CONV_WS_CONFIG_6) { loop_being_configured.bias_dram_addr := cmd.bits.cmd.rs1 loop_being_configured.input_dram_addr := cmd.bits.cmd.rs2 } is (LOOP_CONV_WS) { loop_being_configured.no_bias := cmd.bits.cmd.rs1(0) // TODO we added a default value for max_pixels_per_row just to maintain backwards compatibility. we should deprecate and remove it later val config_max_pixels_per_row = cmd.bits.cmd.rs1(15, 8) loop_being_configured.max_pixels_per_row := Mux( !has_first_layer_optimizations.B \|\| config_max_pixels_per_row === 0.U, 1.U, config_max_pixels_per_row) loop_being_configured.a_ex_spad_id := cmd.bits.cmd.rs1(19, 18) loop_being_configured.b_ex_spad_id := cmd.bits.cmd.rs1(17, 16) loop_being_configured.wrot180 := has_training_convs.B && cmd.bits.cmd.rs1(1) loop_being_configured.input_dilated := has_training_convs.B && cmd.bits.cmd.rs2(2) loop_being_configured.trans_output_1203 := has_training_convs.B && cmd.bits.cmd.rs1(2) loop_being_configured.trans_weight_1203 := has_training_convs.B && cmd.bits.cmd.rs1(3) loop_being_configured.trans_weight_0132 := has_training_convs.B && cmd.bits.cmd.rs1(4) loop_being_configured.trans_input_3120 := has_training_convs.B && cmd.bits.cmd.rs1(5) loop_being_configured.dw := has_dw_convs.B && cmd.bits.cmd.rs1(6) loop_being_configured.no_pool := !has_max_pool.B \|\| cmd.bits.cmd.rs2(0) loop_being_configured.activation := cmd.bits.cmd.rs2(4,3) loop_being_configured.downsample := cmd.bits.cmd.rs2(1) loop_being_configured.configured := true.B // assert(!loop_being_configured.input_dilated \|\| loop_being_configured.outer_bounds.stride === 1.U) // assert(!loop_being_configured.downsample \|\| (loop_being_configured.outer_bounds.kernel_dim === 1.U && loop_being_configured.outer_bounds.stride === 2.U)) // TODO add the rest of the conditions that must be true for "downsample" to be enabled } } } // Wire up request signals val ld_bias_addr_start = RegInit(0.U(log2Up(max_acc_addr).W)) val ex_c_addr_start = RegInit(0.U(log2Up(max_acc_addr).W)) val st_addr_start = RegInit(0.U(log2Up(max_acc_addr).W)) val loop_requesting_ld_bias_id = Mux(head_loop.ld_bias_started, tail_loop_id, head_loop_id) val loop_requesting_ld_bias = loops(loop_requesting_ld_bias_id) ld_bias.io.req.bits.outer_bounds := loop_requesting_ld_bias.outer_bounds ld_bias.io.req.bits.inner_bounds := loop_requesting_ld_bias.inner_bounds ld_bias.io.req.bits.derived_params := loop_requesting_ld_bias.derived_params() ld_bias.io.req.bits.addr_start := ld_bias_addr_start ld_bias.io.req.bits.dram_addr := loop_requesting_ld_bias.bias_dram_addr ld_bias.io.req.bits.no_bias := loop_requesting_ld_bias.no_bias ld_bias.io.req.bits.loop_id := loop_requesting_ld_bias_id ld_bias.io.req.valid := !loop_requesting_ld_bias.ld_bias_started && loop_requesting_ld_bias.configured when (ld_bias.io.req.fire) { loop_requesting_ld_bias.running := true.B loop_requesting_ld_bias.ld_bias_started := true.B // when (loop_requesting_ld_bias.bias_dram_addr =/= 0.U) { when (loop_requesting_ld_bias.output_dram_addr =/= 0.U) { ld_bias_addr_start := floorAdd(ld_bias_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U) } } val loop_requesting_ld_input_id = Mux(head_loop.ld_input_started, tail_loop_id, head_loop_id) val loop_requesting_ld_input = loops(loop_requesting_ld_input_id) ld_input.io.req.bits.outer_bounds := loop_requesting_ld_input.outer_bounds ld_input.io.req.bits.inner_bounds := loop_requesting_ld_input.inner_bounds ld_input.io.req.bits.derived_params := loop_requesting_ld_input.derived_params() ld_input.io.req.bits.addr_start := Mux(loop_requesting_ld_input.a_ex_spad_id === 0.U, loop_requesting_ld_input.a_addr_start, (loop_requesting_ld_input.a_ex_spad_id - 1.U) * (max_addr / concurrent_loops).U) ld_input.io.req.bits.dram_addr := loop_requesting_ld_input.input_dram_addr ld_input.io.req.bits.downsample := loop_requesting_ld_input.downsample ld_input.io.req.bits.max_pixels_per_row := loop_requesting_ld_input.max_pixels_per_row ld_input.io.req.bits.input_dilated := loop_requesting_ld_input.input_dilated ld_input.io.req.bits.trans_input_3120 := loop_requesting_ld_input.trans_input_3120 ld_input.io.req.bits.loop_id := loop_requesting_ld_input_id ld_input.io.req.valid := !loop_requesting_ld_input.ld_input_started && loop_requesting_ld_input.configured when (ld_input.io.req.fire) { loop_requesting_ld_input.running := true.B loop_requesting_ld_input.ld_input_started := true.B } val loop_requesting_ld_weights_id = Mux(head_loop.ld_weights_started, tail_loop_id, head_loop_id) val loop_requesting_ld_weights = loops(loop_requesting_ld_weights_id) ld_weights.io.req.bits.outer_bounds := loop_requesting_ld_weights.outer_bounds ld_weights.io.req.bits.inner_bounds := loop_requesting_ld_weights.inner_bounds ld_weights.io.req.bits.derived_params := loop_requesting_ld_weights.derived_params() ld_weights.io.req.bits.addr_end := Mux(loop_requesting_ld_weights.b_ex_spad_id === 0.U, loop_requesting_ld_weights.b_addr_end, (loop_requesting_ld_weights.b_ex_spad_id) * (max_addr / concurrent_loops).U) ld_weights.io.req.bits.dram_addr := loop_requesting_ld_weights.weights_dram_addr ld_weights.io.req.bits.trans_weight_1203 := loop_requesting_ld_weights.trans_weight_1203 ld_weights.io.req.bits.trans_weight_0132 := loop_requesting_ld_weights.trans_weight_0132 ld_weights.io.req.bits.dw := loop_requesting_ld_weights.dw ld_weights.io.req.bits.loop_id := loop_requesting_ld_weights_id ld_weights.io.req.valid := !loop_requesting_ld_weights.ld_weights_started && loop_requesting_ld_weights.configured when (ld_weights.io.req.fire) { loop_requesting_ld_weights.running := true.B loop_requesting_ld_weights.ld_weights_started := true.B } val loop_requesting_ex_id = Mux(head_loop.ex_started, tail_loop_id, head_loop_id) val loop_requesting_ex = loops(loop_requesting_ex_id) ex.io.req.bits.outer_bounds := loop_requesting_ex.outer_bounds ex.io.req.bits.inner_bounds := loop_requesting_ex.inner_bounds ex.io.req.bits.derived_params := loop_requesting_ex.derived_params() ex.io.req.bits.a_addr_start := Mux(loop_requesting_ex.a_ex_spad_id === 0.U, loop_requesting_ex.a_addr_start, (loop_requesting_ex.a_ex_spad_id - 1.U) * (max_addr / concurrent_loops).U) ex.io.req.bits.b_addr_end := Mux(loop_requesting_ex.b_ex_spad_id === 0.U, loop_requesting_ex.b_addr_end, (loop_requesting_ex.b_ex_spad_id) * (max_addr / concurrent_loops).U) ex.io.req.bits.c_addr_start := ex_c_addr_start ex.io.req.bits.wrot180 := loop_requesting_ex.wrot180 ex.io.req.bits.downsample := loop_requesting_ex.downsample ex.io.req.bits.max_pixels_per_row := loop_requesting_ex.max_pixels_per_row ex.io.req.bits.input_dilated := loop_requesting_ex.input_dilated ex.io.req.bits.trans_weight_0132 := loop_requesting_ex.trans_weight_0132 ex.io.req.bits.trans_input_3120 := loop_requesting_ex.trans_input_3120 ex.io.req.bits.loop_id := loop_requesting_ex_id ex.io.req.valid := !loop_requesting_ex.ex_started && loop_requesting_ex.ld_bias_started && loop_requesting_ex.ld_input_started && loop_requesting_ex.ld_weights_started && loop_requesting_ex.configured when (ex.io.req.fire) { loop_requesting_ex.running := true.B loop_requesting_ex.ex_started := true.B when (loop_requesting_ex.output_dram_addr =/= 0.U) { ex_c_addr_start := floorAdd(ex_c_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U) } } val loop_requesting_st_id = Mux(head_loop.st_started, tail_loop_id, head_loop_id) val loop_requesting_st = loops(loop_requesting_st_id) st.io.req.bits.outer_bounds := loop_requesting_st.outer_bounds st.io.req.bits.inner_bounds := loop_requesting_st.inner_bounds st.io.req.bits.derived_params := loop_requesting_st.derived_params() st.io.req.bits.addr_start := st_addr_start st.io.req.bits.dram_addr := loop_requesting_st.output_dram_addr st.io.req.bits.no_pool := loop_requesting_st.no_pool st.io.req.bits.activation := loop_requesting_st.activation st.io.req.bits.trans_output_1203 := loop_requesting_st.trans_output_1203 st.io.req.bits.loop_id := loop_requesting_st_id st.io.req.valid := !loop_requesting_st.st_started && loop_requesting_st.ex_started && loop_requesting_st.configured when (st.io.req.fire) { loop_requesting_st.running := true.B loop_requesting_st.st_started := true.B when (loop_requesting_st.output_dram_addr =/= 0.U) { st_addr_start := floorAdd(st_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U) } } // Handle completed signals when (ld_bias.io.idle && loops(ld_bias.io.loop_id).running && loops(ld_bias.io.loop_id).ld_bias_started) { loops(ld_bias.io.loop_id).ld_bias_completed := true.B } when (ld_input.io.idle && loops(ld_input.io.loop_id).running && loops(ld_input.io.loop_id).ld_input_started) { loops(ld_input.io.loop_id).ld_input_completed := true.B } when (ld_weights.io.idle && loops(ld_weights.io.loop_id).running && loops(ld_weights.io.loop_id).ld_weights_started) { loops(ld_weights.io.loop_id).ld_weights_completed := true.B } when (ex.io.idle && loops(ex.io.loop_id).running && loops(ex.io.loop_id).ex_started) { loops(ex.io.loop_id).ex_completed := true.B } when (st.io.idle && loops(st.io.loop_id).running && loops(st.io.loop_id).st_started) { loops(st.io.loop_id).st_completed := true.B } when (head_loop.running && head_loop.all_completed()) { head_loop.reset() head_loop_id := ~head_loop_id } // Resets when (reset.asBool) { loops.zipWithIndex.foreach { case (l, i) => l.reset() l.a_addr_start := (i * (max_addr / concurrent_loops)).U l.b_addr_end := ((i+1) * (max_addr / concurrent_loops)).U } } } object LoopConv { def apply(in: DecoupledIO[GemminiCmd], ld_completed: UInt, st_completed: UInt, ex_completed: UInt, block_size: Int, coreMaxAddrBits: Int, rob_size: Int, max_lds: Int, max_exs: Int, max_sts: Int, max_addr: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, dma_max_bytes: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2, config_mvout_rs2_t: ConfigMvoutRs2, mvout_rs2_t: MvoutRs2, config_ex_rs1_t: ConfigExRs1, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs, compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs, has_training_convs: Boolean, has_max_pool: Boolean, has_first_layer_optimizations: Boolean, has_dw_convs: Boolean) (implicit p: Parameters): (DecoupledIO[GemminiCmd], Bool) = { val mod = Module(new LoopConv(block_size, coreMaxAddrBits, rob_size, max_lds, max_exs, max_sts, max_addr, max_acc_addr, input_w, acc_w, dma_max_bytes, config_mvin_rs1_t, mvin_rs2_t, config_mvout_rs2_t, mvout_rs2_t, config_ex_rs1_t, preload_rs1_t, preload_rs2_t, compute_rs1_t, compute_rs2_t, has_training_convs, has_max_pool, has_first_layer_optimizations, has_dw_convs)) mod.io.in <> in mod.io.ld_completed := ld_completed mod.io.st_completed := st_completed mod.io.ex_completed := ex_completed (mod.io.out, mod.io.busy) } def castDramOffset(dram_offset: UInt): UInt = { // Cast dram offsets to 32 bits max dram_offset & "hFFFFFFFF".U } } File LocalAddr.scala: package gemmini import chisel3._ import chisel3.util._ class LocalAddr(sp_banks: Int, sp_bank_entries: Int, acc_banks: Int, acc_bank_entries: Int) extends Bundle { private val localAddrBits = 32 // TODO magic number private val spAddrBits = log2Ceil(sp_banks * sp_bank_entries) private val accAddrBits = log2Ceil(acc_banks * acc_bank_entries) private val maxAddrBits = spAddrBits max accAddrBits private val spBankBits = log2Up(sp_banks) private val spBankRowBits = log2Up(sp_bank_entries) private val accBankBits = log2Up(acc_banks) val accBankRowBits = log2Up(acc_bank_entries) val spRows = sp_banks * sp_bank_entries val is_acc_addr = Bool() val accumulate = Bool() val read_full_acc_row = Bool() val norm_cmd = NormCmd() private val metadata_w = is_acc_addr.getWidth + accumulate.getWidth + read_full_acc_row.getWidth + norm_cmd.getWidth assert(maxAddrBits + metadata_w < 32) val garbage = UInt(((localAddrBits - maxAddrBits - metadata_w - 1) max 0).W) val garbage_bit = if (localAddrBits - maxAddrBits >= metadata_w + 1) UInt(1.W) else UInt(0.W) val data = UInt(maxAddrBits.W) def sp_bank(dummy: Int = 0) = if (spAddrBits == spBankRowBits) 0.U else data(spAddrBits - 1, spBankRowBits) def sp_row(dummy: Int = 0) = data(spBankRowBits - 1, 0) def acc_bank(dummy: Int = 0) = if (accAddrBits == accBankRowBits) 0.U else data(accAddrBits - 1, accBankRowBits) def acc_row(dummy: Int = 0) = data(accBankRowBits - 1, 0) def full_sp_addr(dummy: Int = 0) = data(spAddrBits - 1, 0) def full_acc_addr(dummy: Int = 0) = data(accAddrBits - 1, 0) def is_same_address(other: LocalAddr): Bool = is_acc_addr === other.is_acc_addr && data === other.data def is_same_address(other: UInt): Bool = is_same_address(other.asTypeOf(this)) def is_garbage(dummy: Int = 0) = is_acc_addr && accumulate && read_full_acc_row && data.andR && (if (garbage_bit.getWidth > 0) garbage_bit.asBool else true.B) def +(other: UInt) = { require(isPow2(sp_bank_entries)) // TODO remove this requirement require(isPow2(acc_bank_entries)) // TODO remove this requirement val result = WireInit(this) result.data := data + other result } def <=(other: LocalAddr) = is_acc_addr === other.is_acc_addr && Mux(is_acc_addr, full_acc_addr() <= other.full_acc_addr(), full_sp_addr() <= other.full_sp_addr()) def <(other: LocalAddr) = is_acc_addr === other.is_acc_addr && Mux(is_acc_addr, full_acc_addr() < other.full_acc_addr(), full_sp_addr() < other.full_sp_addr()) def >(other: LocalAddr) = is_acc_addr === other.is_acc_addr && Mux(is_acc_addr, full_acc_addr() > other.full_acc_addr(), full_sp_addr() > other.full_sp_addr()) def add_with_overflow(other: UInt): Tuple2[LocalAddr, Bool] = { require(isPow2(sp_bank_entries)) // TODO remove this requirement require(isPow2(acc_bank_entries)) // TODO remove this requirement val sum = data +& other val overflow = Mux(is_acc_addr, sum(accAddrBits), sum(spAddrBits)) val result = WireInit(this) result.data := sum(maxAddrBits - 1, 0) (result, overflow) } // This function can only be used with non-accumulator addresses. Returns both new address and underflow def floorSub(other: UInt, floor: UInt): (LocalAddr, Bool) = { require(isPow2(sp_bank_entries)) // TODO remove this requirement require(isPow2(acc_bank_entries)) // TODO remove this requirement val underflow = data < (floor +& other) val result = WireInit(this) result.data := Mux(underflow, floor, data - other) (result, underflow) } def make_this_garbage(dummy: Int = 0): Unit = { is_acc_addr := true.B accumulate := true.B read_full_acc_row := true.B garbage_bit := 1.U data := ~(0.U(maxAddrBits.W)) } } object LocalAddr { def cast_to_local_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = { // This convenience function is basically the same as calling "asTypeOf(local_addr_t)". However, this convenience // function will also cast unnecessary garbage bits to 0, which may help reduce multiplier/adder bitwidths val result = WireInit(t.asTypeOf(local_addr_t)) if (result.garbage_bit.getWidth > 0) result.garbage := 0.U result } def cast_to_sp_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = { // This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage // address val result = WireInit(cast_to_local_addr(local_addr_t, t)) result.is_acc_addr := false.B result.accumulate := false.B result.read_full_acc_row := false.B // assert(!result.garbage_bit, "cast_to_sp_addr doesn't work on garbage addresses") result } def cast_to_acc_addr[T <: Data](local_addr_t: LocalAddr, t: T, accumulate: Bool, read_full: Bool): LocalAddr = { // This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage // address val result = WireInit(cast_to_local_addr(local_addr_t, t)) result.is_acc_addr := true.B result.accumulate := accumulate result.read_full_acc_row := read_full // assert(!result.garbage_bit, "cast_to_acc_addr doesn't work on garbage addresses") result } def garbage_addr(local_addr_t: LocalAddr): LocalAddr = { val result = Wire(chiselTypeOf(local_addr_t)) result := DontCare result.make_this_garbage() result } } File Util.scala: package gemmini import chisel3._ import chisel3.util._ object Util { def wrappingAdd(u: UInt, n: UInt, max_plus_one: Int): UInt = { val max = max_plus_one - 1 if (max == 0) { 0.U } else { assert(n <= max.U, "cannot wrapAdd when n is larger than max") Mux(u >= max.U - n + 1.U && n =/= 0.U, n - (max.U - u) - 1.U, u + n) } } def wrappingAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = { val max = max_plus_one - 1.U assert(n <= max \|\| max === 0.U, "cannot wrapAdd when n is larger than max, unless max is 0") /* Mux(!en, u, Mux (max === 0.U, 0.U, Mux(u >= max - n + 1.U && n =/= 0.U, n - (max - u) - 1.U, u + n))) */ MuxCase(u + n, Seq( (!en) -> u, (max === 0.U) -> 0.U, (u >= max - n + 1.U && n =/= 0.U) -> (n - (max - u) - 1.U) )) } def satAdd(u: UInt, v: UInt, max: UInt): UInt = { Mux(u +& v > max, max, u + v) } def floorAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = { val max = max_plus_one - 1.U MuxCase(u + n, Seq( (!en) -> u, ((u +& n) > max) -> 0.U )) } def sFloorAdd(s: SInt, n: UInt, max_plus_one: SInt, min: SInt, en: Bool = true.B): SInt = { val max = max_plus_one - 1.S MuxCase(s + n.zext, Seq( (!en) -> s, ((s +& n.zext) > max) -> min )) } def wrappingSub(u: UInt, n: UInt, max_plus_one: Int): UInt = { val max = max_plus_one - 1 assert(n <= max.U, "cannot wrapSub when n is larger than max") Mux(u < n, max.U - (n-u) + 1.U, u - n) } def ceilingDivide(numer: Int, denom: Int): Int = { if (numer % denom == 0) { numer / denom } else { numer / denom + 1} } def closestLowerPowerOf2(u: UInt): UInt = { // TODO figure out a more efficient way of doing this. Is this many muxes really necessary? val exp = u.asBools.zipWithIndex.map { case (b, i) => Mux(b, i.U, 0.U) }.reduce((acc, u) => Mux(acc > u, acc, u)) (1.U << exp).asUInt } def closestAlignedLowerPowerOf2(u: UInt, addr: UInt, stride: UInt, rowBytes: Int): UInt = { val lgRowBytes = log2Ceil(rowBytes) // TODO figure out a more efficient way of doing this. Is this many muxes really necessary? val exp = u.asBools.zipWithIndex.map { case (b, i) => Mux(b && addr(i + lgRowBytes - 1, 0) === 0.U && stride(i + lgRowBytes - 1, 0) === 0.U, i.U, 0.U) }.reduce((acc, u) => Mux(acc > u, acc, u)) (1.U << exp).asUInt } // This function will return "next" with a 0-cycle delay when the "enable" signal is high. It's like a queue with // the "pipe" and "flow" parameters set to "true" def RegEnableThru[T <: Data](next: T, enable: Bool): T = { val buf = RegEnable(next, enable) Mux(enable, next, buf) } def RegEnableThru[T <: Data](next: T, init: T, enable: Bool): T = { val buf = RegEnable(next, init, enable) Mux(enable, next, buf) } def maxOf(u1: UInt, u2: UInt): UInt = { Mux(u1 > u2, u1, u2) } def maxOf[T <: Data](x: T, y: T)(implicit ev: Arithmetic[T]): T = { import ev._ Mux(x > y, x, y) } def minOf(u1: UInt, u2: UInt): UInt = { Mux(u1 < u2, u1, u2) } def accumulateTree[T <: Data](xs: Seq[T])(implicit ev: Arithmetic[T]): T = { import ev._ assert(xs.nonEmpty, "can't accumulate 0 elements") if (xs.length == 1) { xs.head } else { val upperRowLen = 1 << log2Ceil(xs.length) val upperRow = xs.padTo(upperRowLen, xs.head.zero) val pairs = upperRow.grouped(2) val lowerRow = pairs.map { case Seq(a, b) => a + b } accumulateTree(lowerRow.toSeq) } } // An undirectioned Valid bundle class UDValid[T <: Data](t: T) extends Bundle { val valid = Bool() val bits = t.cloneType def push(b: T): Unit = { valid := true.B bits := b } def pop(dummy: Int = 0): T = { valid := false.B bits } } object UDValid { def apply[T <: Data](t: T): UDValid[T] = new UDValid(t) } // creates a Reg and the next-state Wire, and returns both def regwire(bits: Int) = { val wire = Wire(UInt(bits.W)) val reg = RegNext(wire) wire := reg // default wire to read from reg (reg, wire) } }	module LoopConvLdInput( // @[LoopConv.scala:235:7] input clock, // @[LoopConv.scala:235:7] input reset, // @[LoopConv.scala:235:7] output io_req_ready, // @[LoopConv.scala:241:14] input io_req_valid, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_batch_size, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_in_row_dim, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_in_col_dim, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_in_channels, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_out_channels, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_out_col_dim, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_out_row_dim, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_out_stride, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_in_stride, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_weight_stride, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_pool_out_row_dim, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_pool_out_col_dim, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_stride, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_padding, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_kernel_dim, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_kernel_dilation, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_pool_size, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_pool_stride, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_pool_padding, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_batches, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_porows, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_pocols, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_pochs, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_krows, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_kcols, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_kchs, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_lpad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_rpad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_upad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_dpad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_plpad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_prad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_pupad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_pdpad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_orows, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_ocols, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_ochs, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_irows, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_icols, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_irows_unpadded, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_icols_unpadded, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_ichs, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_out_channels_per_bank, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_in_channels_per_bank, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_bias_spad_stride, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_input_spad_stride, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_weight_spad_stride, // @[LoopConv.scala:241:14] input [13:0] io_req_bits_addr_start, // @[LoopConv.scala:241:14] input [39:0] io_req_bits_dram_addr, // @[LoopConv.scala:241:14] input io_req_bits_downsample, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_max_pixels_per_row, // @[LoopConv.scala:241:14] input io_req_bits_input_dilated, // @[LoopConv.scala:241:14] input io_req_bits_trans_input_3120, // @[LoopConv.scala:241:14] input io_req_bits_loop_id, // @[LoopConv.scala:241:14] input io_cmd_ready, // @[LoopConv.scala:241:14] output io_cmd_valid, // @[LoopConv.scala:241:14] output [6:0] io_cmd_bits_inst_funct, // @[LoopConv.scala:241:14] output [4:0] io_cmd_bits_inst_rs2, // @[LoopConv.scala:241:14] output [4:0] io_cmd_bits_inst_rs1, // @[LoopConv.scala:241:14] output io_cmd_bits_inst_xd, // @[LoopConv.scala:241:14] output io_cmd_bits_inst_xs1, // @[LoopConv.scala:241:14] output io_cmd_bits_inst_xs2, // @[LoopConv.scala:241:14] output [4:0] io_cmd_bits_inst_rd, // @[LoopConv.scala:241:14] output [6:0] io_cmd_bits_inst_opcode, // @[LoopConv.scala:241:14] output [63:0] io_cmd_bits_rs1, // @[LoopConv.scala:241:14] output [63:0] io_cmd_bits_rs2, // @[LoopConv.scala:241:14] output io_cmd_bits_status_debug, // @[LoopConv.scala:241:14] output io_cmd_bits_status_cease, // @[LoopConv.scala:241:14] output io_cmd_bits_status_wfi, // @[LoopConv.scala:241:14] output [31:0] io_cmd_bits_status_isa, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_dprv, // @[LoopConv.scala:241:14] output io_cmd_bits_status_dv, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_prv, // @[LoopConv.scala:241:14] output io_cmd_bits_status_v, // @[LoopConv.scala:241:14] output io_cmd_bits_status_sd, // @[LoopConv.scala:241:14] output [22:0] io_cmd_bits_status_zero2, // @[LoopConv.scala:241:14] output io_cmd_bits_status_mpv, // @[LoopConv.scala:241:14] output io_cmd_bits_status_gva, // @[LoopConv.scala:241:14] output io_cmd_bits_status_mbe, // @[LoopConv.scala:241:14] output io_cmd_bits_status_sbe, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_sxl, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_uxl, // @[LoopConv.scala:241:14] output io_cmd_bits_status_sd_rv32, // @[LoopConv.scala:241:14] output [7:0] io_cmd_bits_status_zero1, // @[LoopConv.scala:241:14] output io_cmd_bits_status_tsr, // @[LoopConv.scala:241:14] output io_cmd_bits_status_tw, // @[LoopConv.scala:241:14] output io_cmd_bits_status_tvm, // @[LoopConv.scala:241:14] output io_cmd_bits_status_mxr, // @[LoopConv.scala:241:14] output io_cmd_bits_status_sum, // @[LoopConv.scala:241:14] output io_cmd_bits_status_mprv, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_xs, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_fs, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_mpp, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_vs, // @[LoopConv.scala:241:14] output io_cmd_bits_status_spp, // @[LoopConv.scala:241:14] output io_cmd_bits_status_mpie, // @[LoopConv.scala:241:14] output io_cmd_bits_status_ube, // @[LoopConv.scala:241:14] output io_cmd_bits_status_spie, // @[LoopConv.scala:241:14] output io_cmd_bits_status_upie, // @[LoopConv.scala:241:14] output io_cmd_bits_status_mie, // @[LoopConv.scala:241:14] output io_cmd_bits_status_hie, // @[LoopConv.scala:241:14] output io_cmd_bits_status_sie, // @[LoopConv.scala:241:14] output io_cmd_bits_status_uie, // @[LoopConv.scala:241:14] output io_idle, // @[LoopConv.scala:241:14] input io_rob_overloaded, // @[LoopConv.scala:241:14] input io_wait_for_prev_loop, // @[LoopConv.scala:241:14] output io_loop_id // @[LoopConv.scala:241:14] ); wire _mvin_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:37] wire [13:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:37] wire [6:0] mvin_cmd_rs2_num_cols; // @[LoopConv.scala:355:28] wire [2:0] mvin_cmd_rs2_local_addr_norm_cmd; // @[LoopConv.scala:355:28] wire _command_p_io_in_ready; // @[LoopConv.scala:313:25] wire _command_p_io_out_valid; // @[LoopConv.scala:313:25] wire [6:0] _command_p_io_out_bits_cmd_inst_funct; // @[LoopConv.scala:313:25] wire [63:0] _command_p_io_out_bits_cmd_rs1; // @[LoopConv.scala:313:25] wire [63:0] _command_p_io_out_bits_cmd_rs2; // @[LoopConv.scala:313:25] wire [67:0] _command_p_io_out_bits_dram_addr; // @[LoopConv.scala:313:25] wire [19:0] _command_p_io_out_bits_I; // @[LoopConv.scala:313:25] wire _command_p_io_busy; // @[LoopConv.scala:313:25] wire io_req_valid_0 = io_req_valid; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_batch_size_0 = io_req_bits_outer_bounds_batch_size; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_in_row_dim_0 = io_req_bits_outer_bounds_in_row_dim; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_in_col_dim_0 = io_req_bits_outer_bounds_in_col_dim; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_in_channels_0 = io_req_bits_outer_bounds_in_channels; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_out_channels_0 = io_req_bits_outer_bounds_out_channels; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_out_col_dim_0 = io_req_bits_outer_bounds_out_col_dim; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_out_row_dim_0 = io_req_bits_outer_bounds_out_row_dim; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_out_stride_0 = io_req_bits_outer_bounds_out_stride; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_in_stride_0 = io_req_bits_outer_bounds_in_stride; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_weight_stride_0 = io_req_bits_outer_bounds_weight_stride; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_pool_out_row_dim_0 = io_req_bits_outer_bounds_pool_out_row_dim; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_pool_out_col_dim_0 = io_req_bits_outer_bounds_pool_out_col_dim; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_stride_0 = io_req_bits_outer_bounds_stride; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_padding_0 = io_req_bits_outer_bounds_padding; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_kernel_dim_0 = io_req_bits_outer_bounds_kernel_dim; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_kernel_dilation_0 = io_req_bits_outer_bounds_kernel_dilation; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_pool_size_0 = io_req_bits_outer_bounds_pool_size; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_pool_stride_0 = io_req_bits_outer_bounds_pool_stride; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_pool_padding_0 = io_req_bits_outer_bounds_pool_padding; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_batches_0 = io_req_bits_inner_bounds_batches; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_porows_0 = io_req_bits_inner_bounds_porows; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_pocols_0 = io_req_bits_inner_bounds_pocols; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_pochs_0 = io_req_bits_inner_bounds_pochs; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_krows_0 = io_req_bits_inner_bounds_krows; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_kcols_0 = io_req_bits_inner_bounds_kcols; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_kchs_0 = io_req_bits_inner_bounds_kchs; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_lpad_0 = io_req_bits_inner_bounds_lpad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_rpad_0 = io_req_bits_inner_bounds_rpad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_upad_0 = io_req_bits_inner_bounds_upad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_dpad_0 = io_req_bits_inner_bounds_dpad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_plpad_0 = io_req_bits_inner_bounds_plpad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_prad_0 = io_req_bits_inner_bounds_prad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_pupad_0 = io_req_bits_inner_bounds_pupad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_pdpad_0 = io_req_bits_inner_bounds_pdpad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_orows_0 = io_req_bits_inner_bounds_orows; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_ocols_0 = io_req_bits_inner_bounds_ocols; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_ochs_0 = io_req_bits_derived_params_ochs; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_irows_0 = io_req_bits_derived_params_irows; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_icols_0 = io_req_bits_derived_params_icols; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_irows_unpadded_0 = io_req_bits_derived_params_irows_unpadded; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_icols_unpadded_0 = io_req_bits_derived_params_icols_unpadded; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_ichs_0 = io_req_bits_derived_params_ichs; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_out_channels_per_bank_0 = io_req_bits_derived_params_out_channels_per_bank; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_in_channels_per_bank_0 = io_req_bits_derived_params_in_channels_per_bank; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_bias_spad_stride_0 = io_req_bits_derived_params_bias_spad_stride; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_input_spad_stride_0 = io_req_bits_derived_params_input_spad_stride; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_weight_spad_stride_0 = io_req_bits_derived_params_weight_spad_stride; // @[LoopConv.scala:235:7] wire [13:0] io_req_bits_addr_start_0 = io_req_bits_addr_start; // @[LoopConv.scala:235:7] wire [39:0] io_req_bits_dram_addr_0 = io_req_bits_dram_addr; // @[LoopConv.scala:235:7] wire io_req_bits_downsample_0 = io_req_bits_downsample; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_max_pixels_per_row_0 = io_req_bits_max_pixels_per_row; // @[LoopConv.scala:235:7] wire io_req_bits_input_dilated_0 = io_req_bits_input_dilated; // @[LoopConv.scala:235:7] wire io_req_bits_trans_input_3120_0 = io_req_bits_trans_input_3120; // @[LoopConv.scala:235:7] wire io_req_bits_loop_id_0 = io_req_bits_loop_id; // @[LoopConv.scala:235:7] wire io_cmd_ready_0 = io_cmd_ready; // @[LoopConv.scala:235:7] wire io_rob_overloaded_0 = io_rob_overloaded; // @[LoopConv.scala:235:7] wire io_wait_for_prev_loop_0 = io_wait_for_prev_loop; // @[LoopConv.scala:235:7] wire [2:0] config_cmd_rs1__spacer1 = 3'h0; // @[LoopConv.scala:319:28] wire [2:0] config_cmd_rs1__spacer0 = 3'h0; // @[LoopConv.scala:319:28] wire [1:0] config_cmd_rs1__unused = 2'h1; // @[LoopConv.scala:319:28, :343:41] wire [2:0] config_cmd_rs1_lo_lo = 3'h1; // @[LoopConv.scala:327:36] wire [31:0] config_cmd_rs1_scale = 32'h3F800000; // @[LoopConv.scala:319:28] wire [31:0] config_cmd_rs1_hi_hi_hi = 32'h3F800000; // @[LoopConv.scala:327:36] wire [33:0] config_cmd_rs1_hi_hi = 34'hFE000000; // @[LoopConv.scala:327:36] wire [6:0] mvin_cmd_inst_funct = 7'h2; // @[LoopConv.scala:331:22, :352:46] wire [63:0] mvin_cmd_rs1 = 64'h0; // @[LoopConv.scala:331:22] wire [63:0] mvin_cmd_rs2 = 64'h0; // @[LoopConv.scala:331:22] wire [4:0] config_cmd_inst_rs2 = 5'h0; // @[LoopConv.scala:315:24] wire [4:0] config_cmd_inst_rs1 = 5'h0; // @[LoopConv.scala:315:24] wire [4:0] config_cmd_inst_rd = 5'h0; // @[LoopConv.scala:315:24] wire [4:0] mvin_cmd_inst_rs2 = 5'h0; // @[LoopConv.scala:331:22] wire [4:0] mvin_cmd_inst_rs1 = 5'h0; // @[LoopConv.scala:331:22] wire [4:0] mvin_cmd_inst_rd = 5'h0; // @[LoopConv.scala:331:22] wire [4:0] _command_p_io_in_bits_cmd_T_1_inst_rs2 = 5'h0; // @[LoopConv.scala:343:34] wire [4:0] _command_p_io_in_bits_cmd_T_1_inst_rs1 = 5'h0; // @[LoopConv.scala:343:34] wire [4:0] _command_p_io_in_bits_cmd_T_1_inst_rd = 5'h0; // @[LoopConv.scala:343:34] wire [6:0] config_cmd_inst_funct = 7'h0; // @[LoopConv.scala:315:24] wire [6:0] config_cmd_inst_opcode = 7'h0; // @[LoopConv.scala:315:24] wire [6:0] mvin_cmd_inst_opcode = 7'h0; // @[LoopConv.scala:331:22] wire [6:0] _command_p_io_in_bits_cmd_T_1_inst_opcode = 7'h0; // @[LoopConv.scala:343:34] wire [31:0] config_cmd_status_isa = 32'h0; // @[LoopConv.scala:315:24] wire [31:0] mvin_cmd_status_isa = 32'h0; // @[LoopConv.scala:331:22] wire [31:0] _command_p_io_in_bits_cmd_T_1_status_isa = 32'h0; // @[LoopConv.scala:343:34] wire [22:0] config_cmd_status_zero2 = 23'h0; // @[LoopConv.scala:315:24] wire [22:0] mvin_cmd_status_zero2 = 23'h0; // @[LoopConv.scala:331:22] wire [22:0] _command_p_io_in_bits_cmd_T_1_status_zero2 = 23'h0; // @[LoopConv.scala:343:34] wire [7:0] config_cmd_status_zero1 = 8'h0; // @[LoopConv.scala:315:24] wire [7:0] mvin_cmd_status_zero1 = 8'h0; // @[LoopConv.scala:331:22] wire [7:0] _command_p_io_in_bits_cmd_T_1_status_zero1 = 8'h0; // @[LoopConv.scala:343:34] wire [8:0] mvin_cmd_rs2__spacer1 = 9'h0; // @[LoopConv.scala:355:28] wire [10:0] mvin_cmd_rs2__spacer2 = 11'h0; // @[LoopConv.scala:355:28] wire [10:0] mvin_cmd_rs2_local_addr_garbage = 11'h0; // @[LoopConv.scala:355:28] wire [10:0] mvin_cmd_rs2_local_addr_result_result_garbage = 11'h0; // @[LocalAddr.scala:108:26] wire [10:0] mvin_cmd_rs2_local_addr_result_garbage = 11'h0; // @[LocalAddr.scala:116:26] wire [1:0] config_cmd_status_dprv = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_status_prv = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_status_sxl = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_status_uxl = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_status_xs = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_status_fs = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_status_mpp = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_status_vs = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_rs1__spacer2 = 2'h0; // @[LoopConv.scala:256:22, :319:28] wire [1:0] config_cmd_rs1_state_id = 2'h0; // @[LoopConv.scala:256:22, :319:28] wire [1:0] mvin_cmd_status_dprv = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] mvin_cmd_status_prv = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] mvin_cmd_status_sxl = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] mvin_cmd_status_uxl = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] mvin_cmd_status_xs = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] mvin_cmd_status_fs = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] mvin_cmd_status_mpp = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] mvin_cmd_status_vs = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_dprv = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_prv = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_sxl = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_uxl = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_xs = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_fs = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_mpp = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_vs = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] io_cmd_bits_rs2_hi_hi = 2'h0; // @[LoopConv.scala:256:22, :360:37] wire config_cmd_inst_xd = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_inst_xs1 = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_inst_xs2 = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_debug = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_cease = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_wfi = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_dv = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_v = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_sd = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_mpv = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_gva = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_mbe = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_sbe = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_sd_rv32 = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_tsr = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_tw = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_tvm = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_mxr = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_sum = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_mprv = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_spp = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_mpie = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_ube = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_spie = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_upie = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_mie = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_hie = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_sie = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_uie = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_rs1_shrink = 1'h0; // @[LoopConv.scala:319:28] wire mvin_cmd_inst_xd = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_inst_xs1 = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_inst_xs2 = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_debug = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_cease = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_wfi = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_dv = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_v = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_sd = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_mpv = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_gva = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_mbe = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_sbe = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_sd_rv32 = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_tsr = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_tw = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_tvm = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_mxr = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_sum = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_mprv = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_spp = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_mpie = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_ube = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_spie = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_upie = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_mie = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_hie = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_sie = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_uie = 1'h0; // @[LoopConv.scala:331:22] wire _io_req_ready_T_2; // @[LoopConv.scala:338:34] wire _command_p_io_in_bits_cmd_T_1_inst_xd = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_inst_xs1 = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_inst_xs2 = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_debug = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_cease = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_wfi = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_dv = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_v = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_sd = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_mpv = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_gva = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_mbe = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_sbe = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_sd_rv32 = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_tsr = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_tw = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_tvm = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_mxr = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_sum = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_mprv = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_spp = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_mpie = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_ube = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_spie = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_upie = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_mie = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_hie = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_sie = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_uie = 1'h0; // @[LoopConv.scala:343:34] wire mvin_cmd_rs2_local_addr_is_acc_addr = 1'h0; // @[LoopConv.scala:355:28] wire mvin_cmd_rs2_local_addr_accumulate = 1'h0; // @[LoopConv.scala:355:28] wire mvin_cmd_rs2_local_addr_read_full_acc_row = 1'h0; // @[LoopConv.scala:355:28] wire mvin_cmd_rs2_local_addr_result_is_acc_addr = 1'h0; // @[LocalAddr.scala:116:26] wire mvin_cmd_rs2_local_addr_result_accumulate = 1'h0; // @[LocalAddr.scala:116:26] wire mvin_cmd_rs2_local_addr_result_read_full_acc_row = 1'h0; // @[LocalAddr.scala:116:26] wire _next_ich_T_5 = 1'h0; // @[Util.scala:51:8] wire _io_cmd_valid_T_1; // @[LoopConv.scala:350:42] wire _io_idle_T_2; // @[LoopConv.scala:339:29] wire io_req_ready_0; // @[LoopConv.scala:235:7] wire [6:0] io_cmd_bits_inst_funct_0; // @[LoopConv.scala:235:7] wire [4:0] io_cmd_bits_inst_rs2_0; // @[LoopConv.scala:235:7] wire [4:0] io_cmd_bits_inst_rs1_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_inst_xd_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_inst_xs1_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_inst_xs2_0; // @[LoopConv.scala:235:7] wire [4:0] io_cmd_bits_inst_rd_0; // @[LoopConv.scala:235:7] wire [6:0] io_cmd_bits_inst_opcode_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_debug_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_cease_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_wfi_0; // @[LoopConv.scala:235:7] wire [31:0] io_cmd_bits_status_isa_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_dprv_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_dv_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_prv_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_v_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_sd_0; // @[LoopConv.scala:235:7] wire [22:0] io_cmd_bits_status_zero2_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_mpv_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_gva_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_mbe_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_sbe_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_sxl_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_uxl_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_sd_rv32_0; // @[LoopConv.scala:235:7] wire [7:0] io_cmd_bits_status_zero1_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_tsr_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_tw_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_tvm_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_mxr_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_sum_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_mprv_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_xs_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_fs_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_mpp_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_vs_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_spp_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_mpie_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_ube_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_spie_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_upie_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_mie_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_hie_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_sie_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_uie_0; // @[LoopConv.scala:235:7] wire [63:0] io_cmd_bits_rs1_0; // @[LoopConv.scala:235:7] wire [63:0] io_cmd_bits_rs2_0; // @[LoopConv.scala:235:7] wire io_cmd_valid_0; // @[LoopConv.scala:235:7] wire io_idle_0; // @[LoopConv.scala:235:7] wire io_loop_id_0; // @[LoopConv.scala:235:7] reg [1:0] state; // @[LoopConv.scala:256:22] reg [15:0] req_outer_bounds_batch_size; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_in_row_dim; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_in_col_dim; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_in_channels; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_out_channels; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_out_col_dim; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_out_row_dim; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_out_stride; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_in_stride; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_weight_stride; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_pool_out_row_dim; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_pool_out_col_dim; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_stride; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_padding; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_kernel_dim; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_kernel_dilation; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_pool_size; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_pool_stride; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_pool_padding; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_batches; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_porows; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_pocols; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_pochs; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_krows; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_kcols; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_kchs; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_lpad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_rpad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_upad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_dpad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_plpad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_prad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_pupad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_pdpad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_orows; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_ocols; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_ochs; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_irows; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_icols; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_irows_unpadded; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_icols_unpadded; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_ichs; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_out_channels_per_bank; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_in_channels_per_bank; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_bias_spad_stride; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_input_spad_stride; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_weight_spad_stride; // @[LoopConv.scala:258:16] reg [13:0] req_addr_start; // @[LoopConv.scala:258:16] reg [39:0] req_dram_addr; // @[LoopConv.scala:258:16] reg req_downsample; // @[LoopConv.scala:258:16] reg [15:0] req_max_pixels_per_row; // @[LoopConv.scala:258:16] reg req_input_dilated; // @[LoopConv.scala:258:16] reg req_trans_input_3120; // @[LoopConv.scala:258:16] reg req_loop_id; // @[LoopConv.scala:258:16] assign io_loop_id_0 = req_loop_id; // @[LoopConv.scala:235:7, :258:16] wire _max_ichs_per_mvin_T = req_derived_params_ichs < 16'h40; // @[LoopConv.scala:258:16, :266:36] wire [15:0] _max_ichs_per_mvin_T_1 = _max_ichs_per_mvin_T ? req_derived_params_ichs : 16'h40; // @[LoopConv.scala:258:16, :266:{30,36}] wire [16:0] max_ichs_per_mvin = {1'h0, _max_ichs_per_mvin_T_1}; // @[LoopConv.scala:266:{30,108}] wire _max_batches_per_mvin_T = req_inner_bounds_batches < 16'h40; // @[LoopConv.scala:258:16, :266:36, :267:42] wire [15:0] _max_batches_per_mvin_T_1 = _max_batches_per_mvin_T ? req_inner_bounds_batches : 16'h40; // @[LoopConv.scala:258:16, :266:36, :267:{33,42}] wire [16:0] max_batches_per_mvin = {1'h0, _max_batches_per_mvin_T_1}; // @[LoopConv.scala:267:{33,117}] wire [16:0] max_chs_per_mvin = req_trans_input_3120 ? max_batches_per_mvin : max_ichs_per_mvin; // @[LoopConv.scala:258:16, :266:108, :267:117, :268:29] wire [16:0] _b_it_T = max_chs_per_mvin; // @[LoopConv.scala:268:29, :370:61] wire [16:0] _ich_it_T = max_chs_per_mvin; // @[LoopConv.scala:268:29, :371:68] reg [15:0] b; // @[LoopConv.scala:271:14] reg [15:0] irow; // @[LoopConv.scala:272:17] reg [15:0] icol; // @[LoopConv.scala:273:17] reg [15:0] ich; // @[LoopConv.scala:274:16] wire [16:0] _GEN = {16'h0, req_input_dilated}; // @[LoopConv.scala:258:16, :263:37, :279:23] wire [16:0] _GEN_0 = {1'h0, req_inner_bounds_upad} + _GEN; // @[LoopConv.scala:258:16, :263:37] wire [16:0] _irow_padded_T; // @[LoopConv.scala:263:37] assign _irow_padded_T = _GEN_0; // @[LoopConv.scala:263:37] wire [16:0] _next_irow_T_5; // @[LoopConv.scala:263:37] assign _next_irow_T_5 = _GEN_0; // @[LoopConv.scala:263:37] wire [16:0] _next_b_T_1; // @[LoopConv.scala:263:37] assign _next_b_T_1 = _GEN_0; // @[LoopConv.scala:263:37] wire [16:0] _state_T_1; // @[LoopConv.scala:263:37] assign _state_T_1 = _GEN_0; // @[LoopConv.scala:263:37] wire [16:0] _irow_padded_T_1 = _irow_padded_T >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _irow_padded_T_2 = {1'h0, _irow_padded_T_1}; // @[LoopConv.scala:263:59, :277:45] wire [18:0] _GEN_1 = {{3{irow[15]}}, irow}; // @[LoopConv.scala:272:17, :277:26] wire [18:0] irow_padded = _GEN_1 + {_irow_padded_T_2[17], _irow_padded_T_2}; // @[LoopConv.scala:277:{26,45}] wire [16:0] _GEN_2 = {1'h0, req_inner_bounds_lpad} + _GEN; // @[LoopConv.scala:258:16, :263:37] wire [16:0] _icol_padded_T; // @[LoopConv.scala:263:37] assign _icol_padded_T = _GEN_2; // @[LoopConv.scala:263:37] wire [16:0] _next_icol_T_5; // @[LoopConv.scala:263:37] assign _next_icol_T_5 = _GEN_2; // @[LoopConv.scala:263:37] wire [16:0] _next_irow_T_9; // @[LoopConv.scala:263:37] assign _next_irow_T_9 = _GEN_2; // @[LoopConv.scala:263:37] wire [16:0] _next_b_T_6; // @[LoopConv.scala:263:37] assign _next_b_T_6 = _GEN_2; // @[LoopConv.scala:263:37] wire [16:0] _state_T_7; // @[LoopConv.scala:263:37] assign _state_T_7 = _GEN_2; // @[LoopConv.scala:263:37] wire [16:0] _icol_padded_T_1 = _icol_padded_T >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _icol_padded_T_2 = {1'h0, _icol_padded_T_1}; // @[LoopConv.scala:263:59, :278:45] wire [18:0] icol_padded = {{3{icol[15]}}, icol} + {_icol_padded_T_2[17], _icol_padded_T_2}; // @[LoopConv.scala:273:17, :278:{26,45}] wire _is_zeros_T = $signed(irow) < 16'sh0; // @[LoopConv.scala:272:17, :279:23] wire [16:0] _is_zeros_T_1 = {1'h0, req_derived_params_irows_unpadded}; // @[LoopConv.scala:258:16, :279:55] wire [16:0] _GEN_3 = {irow[15], irow}; // @[LoopConv.scala:272:17, :277:26, :279:37] wire _is_zeros_T_2 = $signed(_GEN_3) >= $signed(_is_zeros_T_1); // @[LoopConv.scala:279:{37,55}] wire _is_zeros_T_3 = _is_zeros_T \| _is_zeros_T_2; // @[LoopConv.scala:279:{23,29,37}] wire _GEN_4 = $signed(icol) < 16'sh0; // @[LoopConv.scala:273:17, :279:{23,68}] wire _is_zeros_T_4; // @[LoopConv.scala:279:68] assign _is_zeros_T_4 = _GEN_4; // @[LoopConv.scala:279:68] wire _I_T_6; // @[LoopConv.scala:298:13] assign _I_T_6 = _GEN_4; // @[LoopConv.scala:279:68, :298:13] wire _is_zeros_T_5 = _is_zeros_T_3 \| _is_zeros_T_4; // @[LoopConv.scala:279:{29,60,68}] wire [16:0] _GEN_5 = {1'h0, req_derived_params_icols_unpadded}; // @[LoopConv.scala:258:16, :279:100] wire [16:0] _is_zeros_T_6; // @[LoopConv.scala:279:100] assign _is_zeros_T_6 = _GEN_5; // @[LoopConv.scala:279:100] wire [16:0] _I_T; // @[LoopConv.scala:296:24] assign _I_T = _GEN_5; // @[LoopConv.scala:279:100, :296:24] wire [16:0] _I_T_3; // @[LoopConv.scala:296:102] assign _I_T_3 = _GEN_5; // @[LoopConv.scala:279:100, :296:102] wire [16:0] _I_T_11; // @[LoopConv.scala:299:31] assign _I_T_11 = _GEN_5; // @[LoopConv.scala:279:100, :299:31] wire [16:0] _I_T_13; // @[LoopConv.scala:299:59] assign _I_T_13 = _GEN_5; // @[LoopConv.scala:279:100, :299:59] wire [16:0] _I_T_20; // @[LoopConv.scala:299:141] assign _I_T_20 = _GEN_5; // @[LoopConv.scala:279:100, :299:141] wire [16:0] _GEN_6 = {icol[15], icol}; // @[LoopConv.scala:273:17, :278:26, :279:82] wire _is_zeros_T_7 = $signed(_GEN_6) >= $signed(_is_zeros_T_6); // @[LoopConv.scala:279:{82,100}] wire is_zeros = _is_zeros_T_5 \| _is_zeros_T_7; // @[LoopConv.scala:279:{60,74,82}] wire [16:0] _dram_stride_T = {1'h0, req_outer_bounds_batch_size}; // @[LoopConv.scala:258:16, :281:58] wire [16:0] _GEN_7 = {1'h0, req_outer_bounds_in_stride}; // @[LoopConv.scala:258:16, :281:85] wire [16:0] _dram_stride_T_1; // @[LoopConv.scala:281:85] assign _dram_stride_T_1 = _GEN_7; // @[LoopConv.scala:281:85] wire [16:0] _dram_offset_T_37; // @[LoopConv.scala:285:64] assign _dram_offset_T_37 = _GEN_7; // @[LoopConv.scala:281:85, :285:64] wire [16:0] dram_stride = req_trans_input_3120 ? _dram_stride_T : _dram_stride_T_1; // @[LoopConv.scala:258:16, :281:{24,58,85}] wire [16:0] _GEN_8 = {1'h0, req_outer_bounds_in_col_dim}; // @[LoopConv.scala:258:16, :284:54] wire [16:0] _dram_offset_T; // @[LoopConv.scala:284:54] assign _dram_offset_T = _GEN_8; // @[LoopConv.scala:284:54] wire [16:0] _dram_offset_T_8; // @[LoopConv.scala:284:87] assign _dram_offset_T_8 = _GEN_8; // @[LoopConv.scala:284:{54,87}] wire [16:0] _dram_offset_T_27; // @[LoopConv.scala:285:23] assign _dram_offset_T_27 = _GEN_8; // @[LoopConv.scala:284:54, :285:23] wire [16:0] _dram_offset_T_31; // @[LoopConv.scala:285:43] assign _dram_offset_T_31 = _GEN_8; // @[LoopConv.scala:284:54, :285:43] wire [32:0] _GEN_9 = {{17{ich[15]}}, ich}; // @[LoopConv.scala:274:16, :284:54] wire [32:0] _dram_offset_T_1 = _GEN_9 * {{16{_dram_offset_T[16]}}, _dram_offset_T}; // @[LoopConv.scala:284:54] wire [31:0] _dram_offset_T_2 = _dram_offset_T_1[31:0]; // @[LoopConv.scala:284:54] wire [31:0] _dram_offset_T_3 = _dram_offset_T_2; // @[LoopConv.scala:284:54] wire [16:0] _GEN_10 = {1'h0, req_outer_bounds_in_row_dim}; // @[LoopConv.scala:258:16, :284:67] wire [16:0] _dram_offset_T_4; // @[LoopConv.scala:284:67] assign _dram_offset_T_4 = _GEN_10; // @[LoopConv.scala:284:67] wire [16:0] _dram_offset_T_23; // @[LoopConv.scala:285:10] assign _dram_offset_T_23 = _GEN_10; // @[LoopConv.scala:284:67, :285:10] wire [48:0] _dram_offset_T_5 = {{17{_dram_offset_T_3[31]}}, _dram_offset_T_3} * {{32{_dram_offset_T_4[16]}}, _dram_offset_T_4}; // @[LoopConv.scala:284:{54,67}] wire [47:0] _dram_offset_T_6 = _dram_offset_T_5[47:0]; // @[LoopConv.scala:284:67] wire [47:0] _dram_offset_T_7 = _dram_offset_T_6; // @[LoopConv.scala:284:67] wire [32:0] _GEN_11 = {{17{irow[15]}}, irow}; // @[LoopConv.scala:272:17, :277:26, :284:87] wire [32:0] _dram_offset_T_9 = _GEN_11 * {{16{_dram_offset_T_8[16]}}, _dram_offset_T_8}; // @[LoopConv.scala:284:87] wire [31:0] _dram_offset_T_10 = _dram_offset_T_9[31:0]; // @[LoopConv.scala:284:87] wire [31:0] _dram_offset_T_11 = _dram_offset_T_10; // @[LoopConv.scala:284:87] wire [48:0] _dram_offset_T_12 = {_dram_offset_T_7[47], _dram_offset_T_7} + {{17{_dram_offset_T_11[31]}}, _dram_offset_T_11}; // @[LoopConv.scala:284:{67,80,87}] wire [49:0] _GEN_12 = {{34{icol[15]}}, icol}; // @[LoopConv.scala:273:17, :278:26, :284:99] wire [49:0] _dram_offset_T_13 = {_dram_offset_T_12[48], _dram_offset_T_12} + _GEN_12; // @[LoopConv.scala:284:{80,99}] wire [16:0] _GEN_13 = {1'h0, req_inner_bounds_batches}; // @[LoopConv.scala:258:16, :284:108] wire [16:0] _dram_offset_T_14; // @[LoopConv.scala:284:108] assign _dram_offset_T_14 = _GEN_13; // @[LoopConv.scala:284:108] wire [16:0] _K_T; // @[LoopConv.scala:303:17] assign _K_T = _GEN_13; // @[LoopConv.scala:284:108, :303:17] wire [16:0] _K_T_3; // @[LoopConv.scala:303:73] assign _K_T_3 = _GEN_13; // @[LoopConv.scala:284:108, :303:73] wire [16:0] _next_b_T; // @[LoopConv.scala:378:47] assign _next_b_T = _GEN_13; // @[LoopConv.scala:284:108, :378:47] wire [66:0] _dram_offset_T_15 = {{17{_dram_offset_T_13[49]}}, _dram_offset_T_13} * {{50{_dram_offset_T_14[16]}}, _dram_offset_T_14}; // @[LoopConv.scala:284:{99,108}] wire [65:0] _dram_offset_T_16 = _dram_offset_T_15[65:0]; // @[LoopConv.scala:284:108] wire [65:0] _dram_offset_T_17 = _dram_offset_T_16; // @[LoopConv.scala:284:108] wire [66:0] _dram_offset_T_18 = {_dram_offset_T_17[65], _dram_offset_T_17} + {{51{b[15]}}, b}; // @[LoopConv.scala:271:14, :284:{108,118}] wire [68:0] _dram_offset_T_19 = {{2{_dram_offset_T_18[66]}}, _dram_offset_T_18}; // @[LoopConv.scala:284:{118,124}] wire [67:0] _dram_offset_T_20 = _dram_offset_T_19[67:0]; // @[LoopConv.scala:284:124] wire [67:0] _dram_offset_T_21 = _dram_offset_T_20; // @[LoopConv.scala:284:124] wire [67:0] _dram_offset_T_22 = _dram_offset_T_21; // @[LoopConv.scala:284:{124,141}] wire [32:0] _GEN_14 = {{17{b[15]}}, b}; // @[LoopConv.scala:271:14, :284:118, :285:10] wire [32:0] _dram_offset_T_24 = _GEN_14 * {{16{_dram_offset_T_23[16]}}, _dram_offset_T_23}; // @[LoopConv.scala:285:10] wire [31:0] _dram_offset_T_25 = _dram_offset_T_24[31:0]; // @[LoopConv.scala:285:10] wire [31:0] _dram_offset_T_26 = _dram_offset_T_25; // @[LoopConv.scala:285:10] wire [48:0] _dram_offset_T_28 = {{17{_dram_offset_T_26[31]}}, _dram_offset_T_26} * {{32{_dram_offset_T_27[16]}}, _dram_offset_T_27}; // @[LoopConv.scala:285:{10,23}] wire [47:0] _dram_offset_T_29 = _dram_offset_T_28[47:0]; // @[LoopConv.scala:285:23] wire [47:0] _dram_offset_T_30 = _dram_offset_T_29; // @[LoopConv.scala:285:23] wire [32:0] _dram_offset_T_32 = _GEN_11 * {{16{_dram_offset_T_31[16]}}, _dram_offset_T_31}; // @[LoopConv.scala:284:87, :285:43] wire [31:0] _dram_offset_T_33 = _dram_offset_T_32[31:0]; // @[LoopConv.scala:285:43] wire [31:0] _dram_offset_T_34 = _dram_offset_T_33; // @[LoopConv.scala:285:43] wire [48:0] _dram_offset_T_35 = {_dram_offset_T_30[47], _dram_offset_T_30} + {{17{_dram_offset_T_34[31]}}, _dram_offset_T_34}; // @[LoopConv.scala:285:{23,36,43}] wire [49:0] _dram_offset_T_36 = {_dram_offset_T_35[48], _dram_offset_T_35} + _GEN_12; // @[LoopConv.scala:284:99, :285:{36,55}] wire [66:0] _dram_offset_T_38 = {{17{_dram_offset_T_36[49]}}, _dram_offset_T_36} * {{50{_dram_offset_T_37[16]}}, _dram_offset_T_37}; // @[LoopConv.scala:285:{55,64}] wire [65:0] _dram_offset_T_39 = _dram_offset_T_38[65:0]; // @[LoopConv.scala:285:64] wire [65:0] _dram_offset_T_40 = _dram_offset_T_39; // @[LoopConv.scala:285:64] wire [66:0] _dram_offset_T_41 = {_dram_offset_T_40[65], _dram_offset_T_40} + {{51{ich[15]}}, ich}; // @[LoopConv.scala:274:16, :284:54, :285:{64,76}] wire [68:0] _dram_offset_T_42 = {{2{_dram_offset_T_41[66]}}, _dram_offset_T_41}; // @[LoopConv.scala:285:{76,84}] wire [67:0] _dram_offset_T_43 = _dram_offset_T_42[67:0]; // @[LoopConv.scala:285:84] wire [67:0] _dram_offset_T_44 = _dram_offset_T_43; // @[LoopConv.scala:285:84] wire [67:0] _dram_offset_T_45 = _dram_offset_T_44; // @[LoopConv.scala:285:{84,101}] wire [67:0] dram_offset = req_trans_input_3120 ? _dram_offset_T_22 : _dram_offset_T_45; // @[LoopConv.scala:258:16, :284:{24,141}, :285:101] wire [67:0] _dram_addr_T = {36'h0, dram_offset[31:0]}; // @[LoopConv.scala:284:24, :1556:17] wire [68:0] _dram_addr_T_1 = {29'h0, req_dram_addr} + {1'h0, _dram_addr_T}; // @[LoopConv.scala:258:16, :286:52, :1556:17] wire [67:0] _dram_addr_T_2 = _dram_addr_T_1[67:0]; // @[LoopConv.scala:286:52] wire [67:0] dram_addr = is_zeros ? 68'h0 : _dram_addr_T_2; // @[LoopConv.scala:279:74, :286:{22,52}] wire [14:0] _GEN_15 = {1'h0, req_addr_start}; // @[LoopConv.scala:258:16, :289:20] wire [14:0] _spad_addr_T; // @[LoopConv.scala:289:20] assign _spad_addr_T = _GEN_15; // @[LoopConv.scala:289:20] wire [14:0] _spad_addr_T_27; // @[LoopConv.scala:290:20] assign _spad_addr_T_27 = _GEN_15; // @[LoopConv.scala:289:20, :290:20] wire [11:0] _spad_addr_T_1 = b[15:4]; // @[LoopConv.scala:271:14, :289:31] wire [16:0] _GEN_16 = {1'h0, req_derived_params_input_spad_stride}; // @[LoopConv.scala:258:16, :289:54] wire [16:0] _spad_addr_T_2; // @[LoopConv.scala:289:54] assign _spad_addr_T_2 = _GEN_16; // @[LoopConv.scala:289:54] wire [16:0] _spad_addr_T_29; // @[LoopConv.scala:290:56] assign _spad_addr_T_29 = _GEN_16; // @[LoopConv.scala:289:54, :290:56] wire [28:0] _spad_addr_T_3 = {{17{_spad_addr_T_1[11]}}, _spad_addr_T_1} * {{12{_spad_addr_T_2[16]}}, _spad_addr_T_2}; // @[LoopConv.scala:289:{31,54}] wire [27:0] _spad_addr_T_4 = _spad_addr_T_3[27:0]; // @[LoopConv.scala:289:54] wire [27:0] _spad_addr_T_5 = _spad_addr_T_4; // @[LoopConv.scala:289:54] wire [28:0] _spad_addr_T_6 = {{14{_spad_addr_T[14]}}, _spad_addr_T} + {_spad_addr_T_5[27], _spad_addr_T_5}; // @[LoopConv.scala:289:{20,25,54}] wire [15:0] _GEN_17 = {15'h0, req_downsample}; // @[LoopConv.scala:258:16, :289:90] wire [15:0] _GEN_18 = req_derived_params_irows >> _GEN_17; // @[LoopConv.scala:258:16, :289:90] wire [15:0] _spad_addr_T_7; // @[LoopConv.scala:289:90] assign _spad_addr_T_7 = _GEN_18; // @[LoopConv.scala:289:90] wire [15:0] _spad_addr_T_34; // @[LoopConv.scala:290:90] assign _spad_addr_T_34 = _GEN_18; // @[LoopConv.scala:289:90, :290:90] wire [16:0] _spad_addr_T_8 = {1'h0, _spad_addr_T_7}; // @[LoopConv.scala:289:{81,90}] wire [32:0] _spad_addr_T_9 = _GEN_9 * {{16{_spad_addr_T_8[16]}}, _spad_addr_T_8}; // @[LoopConv.scala:284:54, :289:81] wire [31:0] _spad_addr_T_10 = _spad_addr_T_9[31:0]; // @[LoopConv.scala:289:81] wire [31:0] _spad_addr_T_11 = _spad_addr_T_10; // @[LoopConv.scala:289:81] wire [15:0] _GEN_19 = req_derived_params_icols >> _GEN_17; // @[LoopConv.scala:258:16, :289:{90,118}] wire [15:0] _spad_addr_T_12; // @[LoopConv.scala:289:118] assign _spad_addr_T_12 = _GEN_19; // @[LoopConv.scala:289:118] wire [15:0] _spad_addr_T_19; // @[LoopConv.scala:289:181] assign _spad_addr_T_19 = _GEN_19; // @[LoopConv.scala:289:{118,181}] wire [15:0] _spad_addr_T_39; // @[LoopConv.scala:290:118] assign _spad_addr_T_39 = _GEN_19; // @[LoopConv.scala:289:118, :290:118] wire [15:0] _spad_addr_T_46; // @[LoopConv.scala:290:181] assign _spad_addr_T_46 = _GEN_19; // @[LoopConv.scala:289:118, :290:181] wire [16:0] _spad_addr_T_13 = {1'h0, _spad_addr_T_12}; // @[LoopConv.scala:289:{109,118}] wire [48:0] _spad_addr_T_14 = {{17{_spad_addr_T_11[31]}}, _spad_addr_T_11} * {{32{_spad_addr_T_13[16]}}, _spad_addr_T_13}; // @[LoopConv.scala:289:{81,109}] wire [47:0] _spad_addr_T_15 = _spad_addr_T_14[47:0]; // @[LoopConv.scala:289:109] wire [47:0] _spad_addr_T_16 = _spad_addr_T_15; // @[LoopConv.scala:289:109] wire [48:0] _spad_addr_T_17 = {{20{_spad_addr_T_6[28]}}, _spad_addr_T_6} + {_spad_addr_T_16[47], _spad_addr_T_16}; // @[LoopConv.scala:289:{25,74,109}] wire [18:0] _GEN_20 = {18'h0, req_downsample}; // @[LoopConv.scala:258:16, :289:153] wire [18:0] _GEN_21 = $signed($signed(irow_padded) >>> _GEN_20); // @[LoopConv.scala:277:26, :289:153] wire [18:0] _spad_addr_T_18; // @[LoopConv.scala:289:153] assign _spad_addr_T_18 = _GEN_21; // @[LoopConv.scala:289:153] wire [18:0] _spad_addr_T_45; // @[LoopConv.scala:290:153] assign _spad_addr_T_45 = _GEN_21; // @[LoopConv.scala:289:153, :290:153] wire [16:0] _spad_addr_T_20 = {1'h0, _spad_addr_T_19}; // @[LoopConv.scala:289:{172,181}] wire [35:0] _spad_addr_T_21 = {{17{_spad_addr_T_18[18]}}, _spad_addr_T_18} * {{19{_spad_addr_T_20[16]}}, _spad_addr_T_20}; // @[LoopConv.scala:289:{153,172}] wire [34:0] _spad_addr_T_22 = _spad_addr_T_21[34:0]; // @[LoopConv.scala:289:172] wire [34:0] _spad_addr_T_23 = _spad_addr_T_22; // @[LoopConv.scala:289:172] wire [49:0] _spad_addr_T_24 = {_spad_addr_T_17[48], _spad_addr_T_17} + {{15{_spad_addr_T_23[34]}}, _spad_addr_T_23}; // @[LoopConv.scala:289:{74,137,172}] wire [18:0] _GEN_22 = $signed($signed(icol_padded) >>> _GEN_20); // @[LoopConv.scala:278:26, :289:{153,216}] wire [18:0] _spad_addr_T_25; // @[LoopConv.scala:289:216] assign _spad_addr_T_25 = _GEN_22; // @[LoopConv.scala:289:216] wire [18:0] _spad_addr_T_52; // @[LoopConv.scala:290:216] assign _spad_addr_T_52 = _GEN_22; // @[LoopConv.scala:289:216, :290:216] wire [50:0] _spad_addr_T_26 = {_spad_addr_T_24[49], _spad_addr_T_24} + {{32{_spad_addr_T_25[18]}}, _spad_addr_T_25}; // @[LoopConv.scala:289:{137,200,216}] wire [11:0] _spad_addr_T_28 = ich[15:4]; // @[LoopConv.scala:274:16, :290:33] wire [28:0] _spad_addr_T_30 = {{17{_spad_addr_T_28[11]}}, _spad_addr_T_28} * {{12{_spad_addr_T_29[16]}}, _spad_addr_T_29}; // @[LoopConv.scala:290:{33,56}] wire [27:0] _spad_addr_T_31 = _spad_addr_T_30[27:0]; // @[LoopConv.scala:290:56] wire [27:0] _spad_addr_T_32 = _spad_addr_T_31; // @[LoopConv.scala:290:56] wire [28:0] _spad_addr_T_33 = {{14{_spad_addr_T_27[14]}}, _spad_addr_T_27} + {_spad_addr_T_32[27], _spad_addr_T_32}; // @[LoopConv.scala:290:{20,25,56}] wire [16:0] _spad_addr_T_35 = {1'h0, _spad_addr_T_34}; // @[LoopConv.scala:290:{81,90}] wire [32:0] _spad_addr_T_36 = _GEN_14 * {{16{_spad_addr_T_35[16]}}, _spad_addr_T_35}; // @[LoopConv.scala:285:10, :290:81] wire [31:0] _spad_addr_T_37 = _spad_addr_T_36[31:0]; // @[LoopConv.scala:290:81] wire [31:0] _spad_addr_T_38 = _spad_addr_T_37; // @[LoopConv.scala:290:81] wire [16:0] _spad_addr_T_40 = {1'h0, _spad_addr_T_39}; // @[LoopConv.scala:290:{109,118}] wire [48:0] _spad_addr_T_41 = {{17{_spad_addr_T_38[31]}}, _spad_addr_T_38} * {{32{_spad_addr_T_40[16]}}, _spad_addr_T_40}; // @[LoopConv.scala:290:{81,109}] wire [47:0] _spad_addr_T_42 = _spad_addr_T_41[47:0]; // @[LoopConv.scala:290:109] wire [47:0] _spad_addr_T_43 = _spad_addr_T_42; // @[LoopConv.scala:290:109] wire [48:0] _spad_addr_T_44 = {{20{_spad_addr_T_33[28]}}, _spad_addr_T_33} + {_spad_addr_T_43[47], _spad_addr_T_43}; // @[LoopConv.scala:290:{25,76,109}] wire [16:0] _spad_addr_T_47 = {1'h0, _spad_addr_T_46}; // @[LoopConv.scala:290:{172,181}] wire [35:0] _spad_addr_T_48 = {{17{_spad_addr_T_45[18]}}, _spad_addr_T_45} * {{19{_spad_addr_T_47[16]}}, _spad_addr_T_47}; // @[LoopConv.scala:290:{153,172}] wire [34:0] _spad_addr_T_49 = _spad_addr_T_48[34:0]; // @[LoopConv.scala:290:172] wire [34:0] _spad_addr_T_50 = _spad_addr_T_49; // @[LoopConv.scala:290:172] wire [49:0] _spad_addr_T_51 = {_spad_addr_T_44[48], _spad_addr_T_44} + {{15{_spad_addr_T_50[34]}}, _spad_addr_T_50}; // @[LoopConv.scala:290:{76,137,172}] wire [50:0] _spad_addr_T_53 = {_spad_addr_T_51[49], _spad_addr_T_51} + {{32{_spad_addr_T_52[18]}}, _spad_addr_T_52}; // @[LoopConv.scala:290:{137,200,216}] wire [50:0] spad_addr = req_trans_input_3120 ? _spad_addr_T_26 : _spad_addr_T_53; // @[LoopConv.scala:258:16, :287:22, :289:200, :290:200] wire [5:0] _block_size_downsampled_T = 6'h10 << req_downsample; // @[LoopConv.scala:258:16, :293:46] wire [6:0] block_size_downsampled = {1'h0, _block_size_downsampled_T}; // @[LoopConv.scala:293:{46,72}] wire [17:0] _GEN_23 = {{2{icol[15]}}, icol}; // @[LoopConv.scala:273:17, :278:26, :296:29] wire [17:0] _I_T_1 = {_I_T[16], _I_T} - _GEN_23; // @[LoopConv.scala:296:{24,29}] wire [17:0] _GEN_24 = {{11{block_size_downsampled[6]}}, block_size_downsampled}; // @[LoopConv.scala:293:72, :296:37] wire _I_T_2 = $signed(_I_T_1) > $signed(_GEN_24); // @[LoopConv.scala:296:{29,37}] wire [17:0] _I_T_4 = {_I_T_3[16], _I_T_3} - _GEN_23; // @[LoopConv.scala:296:{29,102,107}] wire [17:0] _I_T_5 = _I_T_2 ? _GEN_24 : _I_T_4; // @[LoopConv.scala:296:{8,37,107}] wire [16:0] _GEN_25 = 17'h0 - _GEN_6; // @[LoopConv.scala:279:{23,82}, :298:31] wire [16:0] _I_T_7; // @[LoopConv.scala:298:31] assign _I_T_7 = _GEN_25; // @[LoopConv.scala:279:23, :298:31] wire [16:0] _I_T_9; // @[LoopConv.scala:298:72] assign _I_T_9 = _GEN_25; // @[LoopConv.scala:279:23, :298:{31,72}] wire _I_T_8 = $signed(_I_T_7) > 17'sh10; // @[LoopConv.scala:298:{31,39}] wire [16:0] _I_T_10 = _I_T_8 ? 17'h10 : _I_T_9; // @[LoopConv.scala:298:{26,39,72}] wire _I_T_12 = $signed(_GEN_6) >= $signed(_I_T_11); // @[LoopConv.scala:279:82, :299:{13,31}] wire [16:0] _GEN_26 = {1'h0, req_inner_bounds_rpad} + _GEN; // @[LoopConv.scala:258:16, :263:37] wire [16:0] _I_T_14; // @[LoopConv.scala:263:37] assign _I_T_14 = _GEN_26; // @[LoopConv.scala:263:37] wire [16:0] _I_T_21; // @[LoopConv.scala:263:37] assign _I_T_21 = _GEN_26; // @[LoopConv.scala:263:37] wire [16:0] _next_icol_T_1; // @[LoopConv.scala:263:37] assign _next_icol_T_1 = _GEN_26; // @[LoopConv.scala:263:37] wire [16:0] _I_T_15 = _I_T_14 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _I_T_16 = {1'h0, _I_T_15}; // @[LoopConv.scala:263:59, :299:83] wire [18:0] _I_T_17 = {{2{_I_T_13[16]}}, _I_T_13} + {_I_T_16[17], _I_T_16}; // @[LoopConv.scala:299:{59,64,83}] wire [19:0] _GEN_27 = {{4{icol[15]}}, icol}; // @[LoopConv.scala:273:17, :278:26, :299:88] wire [19:0] _I_T_18 = {_I_T_17[18], _I_T_17} - _GEN_27; // @[LoopConv.scala:299:{64,88}] wire _I_T_19 = $signed(_I_T_18) > 20'sh10; // @[LoopConv.scala:299:{88,96}] wire [16:0] _I_T_22 = _I_T_21 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _I_T_23 = {1'h0, _I_T_22}; // @[LoopConv.scala:263:59, :299:165] wire [18:0] _I_T_24 = {{2{_I_T_20[16]}}, _I_T_20} + {_I_T_23[17], _I_T_23}; // @[LoopConv.scala:299:{141,146,165}] wire [19:0] _I_T_25 = {_I_T_24[18], _I_T_24} - _GEN_27; // @[LoopConv.scala:299:{88,146,170}] wire [19:0] _I_T_26 = _I_T_19 ? 20'h10 : _I_T_25; // @[LoopConv.scala:299:{43,96,170}] wire [19:0] _I_T_27 = _I_T_12 ? _I_T_26 : {{2{_I_T_5[17]}}, _I_T_5}; // @[Mux.scala:126:16] wire [19:0] I = _I_T_6 ? {{3{_I_T_10[16]}}, _I_T_10} : _I_T_27; // @[Mux.scala:126:16] wire [19:0] _next_icol_T = I; // @[Mux.scala:126:16] wire [17:0] _GEN_28 = {{2{b[15]}}, b}; // @[LoopConv.scala:271:14, :284:118, :303:22] wire [17:0] _K_T_1 = {_K_T[16], _K_T} - _GEN_28; // @[LoopConv.scala:303:{17,22}] wire [17:0] _GEN_29 = {max_chs_per_mvin[16], max_chs_per_mvin}; // @[LoopConv.scala:268:29, :303:27] wire _K_T_2 = $signed(_K_T_1) > $signed(_GEN_29); // @[LoopConv.scala:303:{22,27}] wire [17:0] _K_T_4 = {_K_T_3[16], _K_T_3} - _GEN_28; // @[LoopConv.scala:303:{22,73,78}] wire [17:0] _K_T_5 = _K_T_2 ? _GEN_29 : _K_T_4; // @[LoopConv.scala:303:{8,27,78}] wire [16:0] _GEN_30 = {1'h0, req_derived_params_ichs}; // @[LoopConv.scala:258:16, :304:14] wire [16:0] _K_T_6; // @[LoopConv.scala:304:14] assign _K_T_6 = _GEN_30; // @[LoopConv.scala:304:14] wire [16:0] _K_T_9; // @[LoopConv.scala:304:69] assign _K_T_9 = _GEN_30; // @[LoopConv.scala:304:{14,69}] wire [16:0] _next_ich_T; // @[LoopConv.scala:373:50] assign _next_ich_T = _GEN_30; // @[LoopConv.scala:304:14, :373:50] wire [17:0] _GEN_31 = {{2{ich[15]}}, ich}; // @[LoopConv.scala:274:16, :284:54, :304:19] wire [17:0] _K_T_7 = {_K_T_6[16], _K_T_6} - _GEN_31; // @[LoopConv.scala:304:{14,19}] wire _K_T_8 = $signed(_K_T_7) > $signed(_GEN_29); // @[LoopConv.scala:303:27, :304:{19,26}] wire [17:0] _K_T_10 = {_K_T_9[16], _K_T_9} - _GEN_31; // @[LoopConv.scala:304:{19,69,74}] wire [17:0] _K_T_11 = _K_T_8 ? _GEN_29 : _K_T_10; // @[LoopConv.scala:303:27, :304:{8,26,74}] wire [17:0] K = req_trans_input_3120 ? _K_T_5 : _K_T_11; // @[LoopConv.scala:258:16, :302:14, :303:8, :304:8] wire [63:0] _config_cmd_rs1_T; // @[LoopConv.scala:327:36] wire [63:0] config_cmd_rs1; // @[LoopConv.scala:315:24] wire [63:0] config_cmd_rs2; // @[LoopConv.scala:315:24] wire [13:0] config_cmd_rs1_stride; // @[LoopConv.scala:319:28] wire [4:0] config_cmd_rs1_pixel_repeats; // @[LoopConv.scala:319:28] assign config_cmd_rs1_stride = req_derived_params_input_spad_stride[13:0]; // @[LoopConv.scala:258:16, :319:28, :322:25] assign config_cmd_rs1_pixel_repeats = req_max_pixels_per_row[4:0]; // @[LoopConv.scala:258:16, :319:28, :323:32] wire [7:0] config_cmd_rs1_lo_hi_hi = {config_cmd_rs1_pixel_repeats, 3'h0}; // @[LoopConv.scala:319:28, :327:36] wire [9:0] config_cmd_rs1_lo_hi = {config_cmd_rs1_lo_hi_hi, 2'h0}; // @[LoopConv.scala:256:22, :327:36] wire [12:0] config_cmd_rs1_lo = {config_cmd_rs1_lo_hi, 3'h1}; // @[LoopConv.scala:327:36] wire [16:0] config_cmd_rs1_hi_lo = {config_cmd_rs1_stride, 3'h0}; // @[LoopConv.scala:319:28, :327:36] wire [50:0] config_cmd_rs1_hi = {34'hFE000000, config_cmd_rs1_hi_lo}; // @[LoopConv.scala:327:36] assign _config_cmd_rs1_T = {config_cmd_rs1_hi, config_cmd_rs1_lo}; // @[LoopConv.scala:327:36] assign config_cmd_rs1 = _config_cmd_rs1_T; // @[LoopConv.scala:315:24, :327:36] wire [17:0] _config_cmd_rs2_T = {1'h0, dram_stride} << req_downsample; // @[LoopConv.scala:258:16, :281:24, :329:33] assign config_cmd_rs2 = {46'h0, _config_cmd_rs2_T}; // @[LoopConv.scala:315:24, :329:{18,33}] wire _io_req_ready_T = ~(\|state); // @[LoopConv.scala:256:22, :338:25] wire _io_req_ready_T_1 = ~_command_p_io_busy; // @[LoopConv.scala:313:25, :338:37] assign _io_req_ready_T_2 = _io_req_ready_T & _io_req_ready_T_1; // @[LoopConv.scala:338:{25,34,37}] assign io_req_ready_0 = _io_req_ready_T_2; // @[LoopConv.scala:235:7, :338:34] wire _io_idle_T = ~(\|state); // @[LoopConv.scala:256:22, :338:25, :339:20] wire _io_idle_T_1 = ~_command_p_io_busy; // @[LoopConv.scala:313:25, :338:37, :339:32] assign _io_idle_T_2 = _io_idle_T & _io_idle_T_1; // @[LoopConv.scala:339:{20,29,32}] assign io_idle_0 = _io_idle_T_2; // @[LoopConv.scala:235:7, :339:29] wire _command_p_io_in_valid_T = \|state; // @[LoopConv.scala:256:22, :338:25, :342:34] wire _command_p_io_in_valid_T_1 = ~io_wait_for_prev_loop_0; // @[LoopConv.scala:235:7, :342:46] wire _command_p_io_in_valid_T_2 = _command_p_io_in_valid_T & _command_p_io_in_valid_T_1; // @[LoopConv.scala:342:{34,43,46}] wire _command_p_io_in_valid_T_3 = \|req_dram_addr; // @[LoopConv.scala:258:16, :342:87] wire _command_p_io_in_valid_T_4 = _command_p_io_in_valid_T_2 & _command_p_io_in_valid_T_3; // @[LoopConv.scala:342:{43,69,87}] wire _command_p_io_in_bits_cmd_T = state == 2'h1; // @[LoopConv.scala:256:22, :343:41] wire [6:0] _command_p_io_in_bits_cmd_T_1_inst_funct = {5'h0, ~_command_p_io_in_bits_cmd_T, 1'h0}; // @[LoopConv.scala:343:{34,41}] wire [63:0] _command_p_io_in_bits_cmd_T_1_rs1 = _command_p_io_in_bits_cmd_T ? config_cmd_rs1 : 64'h0; // @[LoopConv.scala:315:24, :343:{34,41}] wire [63:0] _command_p_io_in_bits_cmd_T_1_rs2 = _command_p_io_in_bits_cmd_T ? config_cmd_rs2 : 64'h0; // @[LoopConv.scala:315:24, :343:{34,41}] wire _command_p_io_out_ready_T = ~io_rob_overloaded_0; // @[LoopConv.scala:235:7, :349:45] wire _command_p_io_out_ready_T_1 = io_cmd_ready_0 & _command_p_io_out_ready_T; // @[LoopConv.scala:235:7, :349:{42,45}] wire _io_cmd_valid_T = ~io_rob_overloaded_0; // @[LoopConv.scala:235:7, :349:45, :350:45] assign _io_cmd_valid_T_1 = _command_p_io_out_valid & _io_cmd_valid_T; // @[LoopConv.scala:313:25, :350:{42,45}] assign io_cmd_valid_0 = _io_cmd_valid_T_1; // @[LoopConv.scala:235:7, :350:42] wire _T = _command_p_io_out_bits_cmd_inst_funct == 7'h2; // @[LoopConv.scala:313:25, :352:46] assign io_cmd_bits_rs1_0 = _T ? _command_p_io_out_bits_dram_addr[63:0] : _command_p_io_out_bits_cmd_rs1; // @[LoopConv.scala:235:7, :313:25, :351:15, :352:{46,60}, :354:21] wire [6:0] io_cmd_bits_rs2_lo_hi_1 = mvin_cmd_rs2_num_cols; // @[LoopConv.scala:355:28, :360:37] wire [2:0] mvin_cmd_rs2_local_addr_result_norm_cmd; // @[LocalAddr.scala:116:26] wire [2:0] _io_cmd_bits_rs2_T = mvin_cmd_rs2_local_addr_norm_cmd; // @[LoopConv.scala:355:28, :360:37] wire mvin_cmd_rs2_local_addr_result_garbage_bit; // @[LocalAddr.scala:116:26] wire [13:0] mvin_cmd_rs2_local_addr_result_data; // @[LocalAddr.scala:116:26] wire mvin_cmd_rs2_local_addr_garbage_bit; // @[LoopConv.scala:355:28] wire [13:0] mvin_cmd_rs2_local_addr_data; // @[LoopConv.scala:355:28] wire [4:0] mvin_cmd_rs2_num_rows; // @[LoopConv.scala:355:28] wire [19:0] _mvin_cmd_rs2_num_rows_T = $signed($signed(_command_p_io_out_bits_I) >>> req_downsample); // @[LoopConv.scala:258:16, :313:25, :357:35] wire [19:0] _mvin_cmd_rs2_num_rows_T_1 = _mvin_cmd_rs2_num_rows_T; // @[LoopConv.scala:357:{35,54}] assign mvin_cmd_rs2_num_rows = _mvin_cmd_rs2_num_rows_T_1[4:0]; // @[LoopConv.scala:355:28, :357:{27,54}] wire [17:0] _mvin_cmd_rs2_num_cols_T; // @[LoopConv.scala:358:34] assign mvin_cmd_rs2_num_cols = _mvin_cmd_rs2_num_cols_T[6:0]; // @[LoopConv.scala:355:28, :358:{27,34}] wire _mvin_cmd_rs2_local_addr_result_result_T_7; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_is_acc_addr = _mvin_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:{26,37}] wire _mvin_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_accumulate = _mvin_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:{26,37}] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_read_full_acc_row = _mvin_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:{26,37}] wire [10:0] _mvin_cmd_rs2_local_addr_result_result_T_3; // @[LocalAddr.scala:108:37] wire [2:0] mvin_cmd_rs2_local_addr_result_result_norm_cmd = _mvin_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:{26,37}] wire _mvin_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [13:0] _mvin_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_garbage_bit = _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:{26,37}] wire [13:0] mvin_cmd_rs2_local_addr_result_result_data = _mvin_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:{26,37}] wire [50:0] _mvin_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] wire [31:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_1 = _mvin_cmd_rs2_local_addr_result_result_T[31:0]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_1 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[13:0]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_data = _mvin_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_2 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[14]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage_bit = _mvin_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_3 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[25:15]; // @[LocalAddr.scala:108:37] wire [10:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage = _mvin_cmd_rs2_local_addr_result_result_T_3; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_T_4 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[28:26]; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_2 = _mvin_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_3 = _mvin_cmd_rs2_local_addr_result_result_WIRE_2; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_norm_cmd = _mvin_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_5 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[29]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row = _mvin_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_6 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[30]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_accumulate = _mvin_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_7 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[31]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr = _mvin_cmd_rs2_local_addr_result_result_T_7; // @[LocalAddr.scala:108:37] assign mvin_cmd_rs2_local_addr_result_norm_cmd = mvin_cmd_rs2_local_addr_result_result_norm_cmd; // @[LocalAddr.scala:108:26, :116:26] assign mvin_cmd_rs2_local_addr_result_garbage_bit = mvin_cmd_rs2_local_addr_result_result_garbage_bit; // @[LocalAddr.scala:108:26, :116:26] assign mvin_cmd_rs2_local_addr_result_data = mvin_cmd_rs2_local_addr_result_result_data; // @[LocalAddr.scala:108:26, :116:26] assign mvin_cmd_rs2_local_addr_norm_cmd = mvin_cmd_rs2_local_addr_result_norm_cmd; // @[LoopConv.scala:355:28] assign mvin_cmd_rs2_local_addr_garbage_bit = mvin_cmd_rs2_local_addr_result_garbage_bit; // @[LoopConv.scala:355:28] assign mvin_cmd_rs2_local_addr_data = mvin_cmd_rs2_local_addr_result_data; // @[LoopConv.scala:355:28] wire [11:0] io_cmd_bits_rs2_lo_hi = {11'h0, mvin_cmd_rs2_local_addr_garbage_bit}; // @[LoopConv.scala:355:28, :360:37] wire [25:0] io_cmd_bits_rs2_lo = {io_cmd_bits_rs2_lo_hi, mvin_cmd_rs2_local_addr_data}; // @[LoopConv.scala:355:28, :360:37] wire [3:0] io_cmd_bits_rs2_hi_lo = {1'h0, _io_cmd_bits_rs2_T}; // @[LoopConv.scala:360:37] wire [5:0] io_cmd_bits_rs2_hi = {2'h0, io_cmd_bits_rs2_hi_lo}; // @[LoopConv.scala:256:22, :360:37] wire [31:0] _io_cmd_bits_rs2_T_1 = {io_cmd_bits_rs2_hi, io_cmd_bits_rs2_lo}; // @[LoopConv.scala:360:37] wire [38:0] io_cmd_bits_rs2_lo_1 = {io_cmd_bits_rs2_lo_hi_1, _io_cmd_bits_rs2_T_1}; // @[LoopConv.scala:360:37] wire [15:0] io_cmd_bits_rs2_hi_hi_1 = {11'h0, mvin_cmd_rs2_num_rows}; // @[LoopConv.scala:355:28, :360:37] wire [24:0] io_cmd_bits_rs2_hi_1 = {io_cmd_bits_rs2_hi_hi_1, 9'h0}; // @[LoopConv.scala:360:37] wire [63:0] _io_cmd_bits_rs2_T_2 = {io_cmd_bits_rs2_hi_1, io_cmd_bits_rs2_lo_1}; // @[LoopConv.scala:360:37] assign io_cmd_bits_rs2_0 = _T ? _io_cmd_bits_rs2_T_2 : _command_p_io_out_bits_cmd_rs2; // @[LoopConv.scala:235:7, :313:25, :351:15, :352:{46,60}, :360:{21,37}] wire [16:0] b_it = req_trans_input_3120 ? _b_it_T : 17'h1; // @[LoopConv.scala:258:16, :281:58, :370:{21,61}] wire [16:0] ich_it = req_trans_input_3120 ? 17'h1 : _ich_it_T; // @[LoopConv.scala:258:16, :281:58, :371:{23,68}] wire [17:0] _next_ich_max_T = {_next_ich_T[16], _next_ich_T} - 18'h1; // @[Util.scala:48:28] wire [16:0] _next_ich_max_T_1 = _next_ich_max_T[16:0]; // @[Util.scala:48:28] wire [16:0] next_ich_max = _next_ich_max_T_1; // @[Util.scala:48:28] wire [17:0] _GEN_32 = {1'h0, ich_it}; // @[Util.scala:50:19] wire [17:0] _next_ich_T_1; // @[Util.scala:50:19] assign _next_ich_T_1 = _GEN_32; // @[Util.scala:50:19] wire [17:0] _next_ich_T_6; // @[Util.scala:52:16] assign _next_ich_T_6 = _GEN_32; // @[Util.scala:50:19, :52:16] wire [18:0] _GEN_33 = {{3{ich[15]}}, ich}; // @[Util.scala:50:15] wire [18:0] _next_ich_T_2 = _GEN_33 + {_next_ich_T_1[17], _next_ich_T_1}; // @[Util.scala:50:{15,19}] wire [17:0] _next_ich_T_3 = _next_ich_T_2[17:0]; // @[Util.scala:50:15] wire [17:0] _next_ich_T_4 = _next_ich_T_3; // @[Util.scala:50:15] wire [18:0] _next_ich_T_7 = _GEN_33 + {_next_ich_T_6[17], _next_ich_T_6}; // @[Util.scala:50:15, :52:{11,16}] wire _next_ich_T_8 = $signed(_next_ich_T_7) > $signed({{2{next_ich_max[16]}}, next_ich_max}); // @[Util.scala:48:28, :52:{11,22}] wire [17:0] _next_ich_T_9 = _next_ich_T_8 ? 18'h0 : _next_ich_T_4; // @[Mux.scala:126:16] wire [17:0] next_ich = _next_ich_T_9; // @[Mux.scala:126:16] wire [16:0] _next_icol_T_2 = _next_icol_T_1 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _next_icol_T_3 = {2'h0, req_derived_params_icols_unpadded} + {1'h0, _next_icol_T_2}; // @[LoopConv.scala:256:22, :258:16, :263:59, :374:65] wire [18:0] _next_icol_T_4 = {1'h0, _next_icol_T_3}; // @[LoopConv.scala:374:{65,85}] wire [16:0] _next_icol_T_6 = _next_icol_T_5 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _next_icol_T_7 = {1'h0, _next_icol_T_6}; // @[LoopConv.scala:263:59, :374:112] wire [18:0] _next_icol_T_8 = 19'h0 - {_next_icol_T_7[17], _next_icol_T_7}; // @[LoopConv.scala:279:23, :357:35, :374:{94,112}] wire _GEN_34 = next_ich == 18'h0; // @[Mux.scala:126:16] wire _next_icol_T_9; // @[LoopConv.scala:375:18] assign _next_icol_T_9 = _GEN_34; // @[LoopConv.scala:375:18] wire _next_irow_T_14; // @[LoopConv.scala:377:61] assign _next_irow_T_14 = _GEN_34; // @[LoopConv.scala:375:18, :377:61] wire _next_b_T_12; // @[LoopConv.scala:379:104] assign _next_b_T_12 = _GEN_34; // @[LoopConv.scala:375:18, :379:104] wire _state_T_13; // @[LoopConv.scala:386:133] assign _state_T_13 = _GEN_34; // @[LoopConv.scala:375:18, :386:133] wire [19:0] _next_icol_max_T = {_next_icol_T_4[18], _next_icol_T_4} - 20'h1; // @[Util.scala:48:28] wire [18:0] _next_icol_max_T_1 = _next_icol_max_T[18:0]; // @[Util.scala:48:28] wire [18:0] next_icol_max = _next_icol_max_T_1; // @[Util.scala:48:28] wire [20:0] _GEN_35 = {1'h0, _next_icol_T}; // @[Util.scala:50:19] wire [20:0] _next_icol_T_10; // @[Util.scala:50:19] assign _next_icol_T_10 = _GEN_35; // @[Util.scala:50:19] wire [20:0] _next_icol_T_15; // @[Util.scala:52:16] assign _next_icol_T_15 = _GEN_35; // @[Util.scala:50:19, :52:16] wire [21:0] _GEN_36 = {{6{icol[15]}}, icol}; // @[Util.scala:50:15] wire [21:0] _next_icol_T_11 = _GEN_36 + {_next_icol_T_10[20], _next_icol_T_10}; // @[Util.scala:50:{15,19}] wire [20:0] _next_icol_T_12 = _next_icol_T_11[20:0]; // @[Util.scala:50:15] wire [20:0] _next_icol_T_13 = _next_icol_T_12; // @[Util.scala:50:15] wire _next_icol_T_14 = ~_next_icol_T_9; // @[Util.scala:51:8] wire [21:0] _next_icol_T_16 = _GEN_36 + {_next_icol_T_15[20], _next_icol_T_15}; // @[Util.scala:50:15, :52:{11,16}] wire _next_icol_T_17 = $signed(_next_icol_T_16) > $signed({{3{next_icol_max[18]}}, next_icol_max}); // @[Util.scala:48:28, :52:{11,22}] wire [20:0] _next_icol_T_18 = _next_icol_T_17 ? {{2{_next_icol_T_8[18]}}, _next_icol_T_8} : _next_icol_T_13; // @[Mux.scala:126:16] wire [20:0] next_icol = _next_icol_T_14 ? {{5{icol[15]}}, icol} : _next_icol_T_18; // @[Mux.scala:126:16] wire [1:0] _next_irow_T = 2'h1 << req_downsample; // @[LoopConv.scala:258:16, :343:41, :376:43] wire [16:0] _next_irow_T_1 = {1'h0, req_inner_bounds_dpad} + _GEN; // @[LoopConv.scala:258:16, :263:37] wire [16:0] _next_irow_T_2 = _next_irow_T_1 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _next_irow_T_3 = {2'h0, req_derived_params_irows_unpadded} + {1'h0, _next_irow_T_2}; // @[LoopConv.scala:256:22, :258:16, :263:59, :376:78] wire [18:0] _next_irow_T_4 = {1'h0, _next_irow_T_3}; // @[LoopConv.scala:376:{78,98}] wire [16:0] _next_irow_T_6 = _next_irow_T_5 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _next_irow_T_7 = {1'h0, _next_irow_T_6}; // @[LoopConv.scala:263:59, :376:125] wire [18:0] _next_irow_T_8 = 19'h0 - {_next_irow_T_7[17], _next_irow_T_7}; // @[LoopConv.scala:279:23, :357:35, :376:{107,125}] wire [16:0] _next_irow_T_10 = _next_irow_T_9 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _next_irow_T_11 = {1'h0, _next_irow_T_10}; // @[LoopConv.scala:263:59, :377:44] wire [18:0] _next_irow_T_12 = 19'h0 - {_next_irow_T_11[17], _next_irow_T_11}; // @[LoopConv.scala:279:23, :357:35, :377:{26,44}] wire _next_irow_T_13 = next_icol == {{2{_next_irow_T_12[18]}}, _next_irow_T_12}; // @[Mux.scala:126:16] wire _next_irow_T_15 = _next_irow_T_13 & _next_irow_T_14; // @[LoopConv.scala:377:{19,49,61}] wire [19:0] _next_irow_max_T = {_next_irow_T_4[18], _next_irow_T_4} - 20'h1; // @[Util.scala:48:28] wire [18:0] _next_irow_max_T_1 = _next_irow_max_T[18:0]; // @[Util.scala:48:28] wire [18:0] next_irow_max = _next_irow_max_T_1; // @[Util.scala:48:28] wire [2:0] _GEN_37 = {1'h0, _next_irow_T}; // @[Util.scala:50:19] wire [2:0] _next_irow_T_16; // @[Util.scala:50:19] assign _next_irow_T_16 = _GEN_37; // @[Util.scala:50:19] wire [2:0] _next_irow_T_21; // @[Util.scala:52:16] assign _next_irow_T_21 = _GEN_37; // @[Util.scala:50:19, :52:16] wire [16:0] _next_irow_T_17 = _GEN_3 + {{14{_next_irow_T_16[2]}}, _next_irow_T_16}; // @[Util.scala:50:{15,19}] wire [15:0] _next_irow_T_18 = _next_irow_T_17[15:0]; // @[Util.scala:50:15] wire [15:0] _next_irow_T_19 = _next_irow_T_18; // @[Util.scala:50:15] wire _next_irow_T_20 = ~_next_irow_T_15; // @[Util.scala:51:8] wire [16:0] _next_irow_T_22 = _GEN_3 + {{14{_next_irow_T_21[2]}}, _next_irow_T_21}; // @[Util.scala:52:{11,16}] wire _next_irow_T_23 = $signed({{2{_next_irow_T_22[16]}}, _next_irow_T_22}) > $signed(next_irow_max); // @[Util.scala:48:28, :52:{11,22}] wire [18:0] _next_irow_T_24 = _next_irow_T_23 ? _next_irow_T_8 : {{3{_next_irow_T_19[15]}}, _next_irow_T_19}; // @[Mux.scala:126:16] wire [18:0] next_irow = _next_irow_T_20 ? _GEN_1 : _next_irow_T_24; // @[Mux.scala:126:16] wire [16:0] _next_b_T_2 = _next_b_T_1 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _next_b_T_3 = {1'h0, _next_b_T_2}; // @[LoopConv.scala:263:59, :379:44] wire [18:0] _next_b_T_4 = 19'h0 - {_next_b_T_3[17], _next_b_T_3}; // @[LoopConv.scala:279:23, :357:35, :379:{26,44}] wire _next_b_T_5 = next_irow == _next_b_T_4; // @[Mux.scala:126:16] wire [16:0] _next_b_T_7 = _next_b_T_6 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _next_b_T_8 = {1'h0, _next_b_T_7}; // @[LoopConv.scala:263:59, :379:87] wire [18:0] _next_b_T_9 = 19'h0 - {_next_b_T_8[17], _next_b_T_8}; // @[LoopConv.scala:279:23, :357:35, :379:{69,87}] wire _next_b_T_10 = next_icol == {{2{_next_b_T_9[18]}}, _next_b_T_9}; // @[Mux.scala:126:16] wire _next_b_T_11 = _next_b_T_5 & _next_b_T_10; // @[LoopConv.scala:379:{19,49,62}] wire _next_b_T_13 = _next_b_T_11 & _next_b_T_12; // @[LoopConv.scala:379:{49,92,104}] wire [17:0] _next_b_max_T = {_next_b_T[16], _next_b_T} - 18'h1; // @[Util.scala:48:28] wire [16:0] _next_b_max_T_1 = _next_b_max_T[16:0]; // @[Util.scala:48:28] wire [16:0] next_b_max = _next_b_max_T_1; // @[Util.scala:48:28] wire [17:0] _GEN_38 = {1'h0, b_it}; // @[Util.scala:50:19] wire [17:0] _next_b_T_14; // @[Util.scala:50:19] assign _next_b_T_14 = _GEN_38; // @[Util.scala:50:19] wire [17:0] _next_b_T_19; // @[Util.scala:52:16] assign _next_b_T_19 = _GEN_38; // @[Util.scala:50:19, :52:16] wire [18:0] _GEN_39 = {{3{b[15]}}, b}; // @[Util.scala:50:15] wire [18:0] _next_b_T_15 = _GEN_39 + {_next_b_T_14[17], _next_b_T_14}; // @[Util.scala:50:{15,19}] wire [17:0] _next_b_T_16 = _next_b_T_15[17:0]; // @[Util.scala:50:15] wire [17:0] _next_b_T_17 = _next_b_T_16; // @[Util.scala:50:15] wire _next_b_T_18 = ~_next_b_T_13; // @[Util.scala:51:8] wire [18:0] _next_b_T_20 = _GEN_39 + {_next_b_T_19[17], _next_b_T_19}; // @[Util.scala:50:15, :52:{11,16}] wire _next_b_T_21 = $signed(_next_b_T_20) > $signed({{2{next_b_max[16]}}, next_b_max}); // @[Util.scala:48:28, :52:{11,22}] wire [17:0] _next_b_T_22 = _next_b_T_21 ? 18'h0 : _next_b_T_17; // @[Mux.scala:126:16] wire [17:0] next_b = _next_b_T_18 ? _GEN_28 : _next_b_T_22; // @[Mux.scala:126:16] wire _state_T = next_b == 18'h0; // @[Mux.scala:126:16] wire [16:0] _state_T_2 = _state_T_1 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _state_T_3 = {1'h0, _state_T_2}; // @[LoopConv.scala:263:59, :386:73] wire [18:0] _state_T_4 = 19'h0 - {_state_T_3[17], _state_T_3}; // @[LoopConv.scala:279:23, :357:35, :386:{55,73}] wire _state_T_5 = next_irow == _state_T_4; // @[Mux.scala:126:16] wire _state_T_6 = _state_T & _state_T_5; // @[LoopConv.scala:386:{27,35,48}] wire [16:0] _state_T_8 = _state_T_7 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _state_T_9 = {1'h0, _state_T_8}; // @[LoopConv.scala:263:59, :386:116] wire [18:0] _state_T_10 = 19'h0 - {_state_T_9[17], _state_T_9}; // @[LoopConv.scala:279:23, :357:35, :386:{98,116}] wire _state_T_11 = next_icol == {{2{_state_T_10[18]}}, _state_T_10}; // @[Mux.scala:126:16] wire _state_T_12 = _state_T_6 & _state_T_11; // @[LoopConv.scala:386:{35,78,91}] wire _state_T_14 = _state_T_12 & _state_T_13; // @[LoopConv.scala:386:{78,121,133}] wire [1:0] _state_T_15 = {~_state_T_14, 1'h0}; // @[LoopConv.scala:386:{19,121}] wire [16:0] _GEN_40 = {16'h0, io_req_bits_input_dilated_0}; // @[LoopConv.scala:235:7, :279:23, :396:52] wire [16:0] _irow_T = {1'h0, io_req_bits_inner_bounds_upad_0} + _GEN_40; // @[LoopConv.scala:235:7, :396:52] wire [16:0] _irow_T_1 = _irow_T >> _GEN_40; // @[LoopConv.scala:396:{52,82}] wire [17:0] _irow_T_2 = {1'h0, _irow_T_1}; // @[LoopConv.scala:396:{82,112}] wire [18:0] _irow_T_3 = 19'h0 - {_irow_T_2[17], _irow_T_2}; // @[LoopConv.scala:279:23, :357:35, :396:{17,112}] wire [16:0] _icol_T = {1'h0, io_req_bits_inner_bounds_lpad_0} + _GEN_40; // @[LoopConv.scala:235:7, :396:52, :397:52] wire [16:0] _icol_T_1 = _icol_T >> _GEN_40; // @[LoopConv.scala:396:52, :397:{52,82}] wire [17:0] _icol_T_2 = {1'h0, _icol_T_1}; // @[LoopConv.scala:397:{82,112}] wire [18:0] _icol_T_3 = 19'h0 - {_icol_T_2[17], _icol_T_2}; // @[LoopConv.scala:279:23, :357:35, :397:{17,112}] wire _T_2 = _command_p_io_in_ready & _command_p_io_in_valid_T_4; // @[Decoupled.scala:51:35] wire _T_4 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[LoopConv.scala:235:7] if (reset) // @[LoopConv.scala:235:7] state <= 2'h0; // @[LoopConv.scala:256:22] else if (_T_4) // @[Decoupled.scala:51:35] state <= 2'h1; // @[LoopConv.scala:256:22, :343:41] else if (\|req_dram_addr) begin // @[LoopConv.scala:258:16, :342:87] if (_T_2) // @[Decoupled.scala:51:35] state <= _command_p_io_in_bits_cmd_T ? 2'h2 : _state_T_15; // @[LoopConv.scala:256:22, :343:41, :367:29, :368:13, :386:{13,19}] end else // @[LoopConv.scala:342:87] state <= 2'h0; // @[LoopConv.scala:256:22] if (_T_4) begin // @[Decoupled.scala:51:35] req_outer_bounds_batch_size <= io_req_bits_outer_bounds_batch_size_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_in_row_dim <= io_req_bits_outer_bounds_in_row_dim_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_in_col_dim <= io_req_bits_outer_bounds_in_col_dim_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_in_channels <= io_req_bits_outer_bounds_in_channels_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_out_channels <= io_req_bits_outer_bounds_out_channels_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_out_col_dim <= io_req_bits_outer_bounds_out_col_dim_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_out_row_dim <= io_req_bits_outer_bounds_out_row_dim_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_out_stride <= io_req_bits_outer_bounds_out_stride_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_in_stride <= io_req_bits_outer_bounds_in_stride_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_weight_stride <= io_req_bits_outer_bounds_weight_stride_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_pool_out_row_dim <= io_req_bits_outer_bounds_pool_out_row_dim_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_pool_out_col_dim <= io_req_bits_outer_bounds_pool_out_col_dim_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_stride <= io_req_bits_outer_bounds_stride_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_padding <= io_req_bits_outer_bounds_padding_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_kernel_dim <= io_req_bits_outer_bounds_kernel_dim_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_kernel_dilation <= io_req_bits_outer_bounds_kernel_dilation_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_pool_size <= io_req_bits_outer_bounds_pool_size_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_pool_stride <= io_req_bits_outer_bounds_pool_stride_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_pool_padding <= io_req_bits_outer_bounds_pool_padding_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_batches <= io_req_bits_inner_bounds_batches_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_porows <= io_req_bits_inner_bounds_porows_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_pocols <= io_req_bits_inner_bounds_pocols_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_pochs <= io_req_bits_inner_bounds_pochs_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_krows <= io_req_bits_inner_bounds_krows_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_kcols <= io_req_bits_inner_bounds_kcols_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_kchs <= io_req_bits_inner_bounds_kchs_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_lpad <= io_req_bits_inner_bounds_lpad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_rpad <= io_req_bits_inner_bounds_rpad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_upad <= io_req_bits_inner_bounds_upad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_dpad <= io_req_bits_inner_bounds_dpad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_plpad <= io_req_bits_inner_bounds_plpad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_prad <= io_req_bits_inner_bounds_prad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_pupad <= io_req_bits_inner_bounds_pupad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_pdpad <= io_req_bits_inner_bounds_pdpad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_orows <= io_req_bits_inner_bounds_orows_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_ocols <= io_req_bits_inner_bounds_ocols_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_ochs <= io_req_bits_derived_params_ochs_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_irows <= io_req_bits_derived_params_irows_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_icols <= io_req_bits_derived_params_icols_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_irows_unpadded <= io_req_bits_derived_params_irows_unpadded_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_icols_unpadded <= io_req_bits_derived_params_icols_unpadded_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_ichs <= io_req_bits_derived_params_ichs_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_out_channels_per_bank <= io_req_bits_derived_params_out_channels_per_bank_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_in_channels_per_bank <= io_req_bits_derived_params_in_channels_per_bank_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_bias_spad_stride <= io_req_bits_derived_params_bias_spad_stride_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_input_spad_stride <= io_req_bits_derived_params_input_spad_stride_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_weight_spad_stride <= io_req_bits_derived_params_weight_spad_stride_0; // @[LoopConv.scala:235:7, :258:16] req_addr_start <= io_req_bits_addr_start_0; // @[LoopConv.scala:235:7, :258:16] req_dram_addr <= io_req_bits_dram_addr_0; // @[LoopConv.scala:235:7, :258:16] req_downsample <= io_req_bits_downsample_0; // @[LoopConv.scala:235:7, :258:16] req_max_pixels_per_row <= io_req_bits_max_pixels_per_row_0; // @[LoopConv.scala:235:7, :258:16] req_input_dilated <= io_req_bits_input_dilated_0; // @[LoopConv.scala:235:7, :258:16] req_trans_input_3120 <= io_req_bits_trans_input_3120_0; // @[LoopConv.scala:235:7, :258:16] req_loop_id <= io_req_bits_loop_id_0; // @[LoopConv.scala:235:7, :258:16] b <= 16'h0; // @[LoopConv.scala:271:14, :279:23] irow <= _irow_T_3[15:0]; // @[LoopConv.scala:272:17, :396:{10,17}] icol <= _icol_T_3[15:0]; // @[LoopConv.scala:273:17, :397:{10,17}] ich <= 16'h0; // @[LoopConv.scala:274:16, :279:23] end else if (~(\|req_dram_addr) \| ~_T_2 \| _command_p_io_in_bits_cmd_T) begin // @[Decoupled.scala:51:35] end else begin // @[LoopConv.scala:274:16, :364:30, :366:36, :367:29] b <= next_b[15:0]; // @[Mux.scala:126:16] irow <= next_irow[15:0]; // @[Mux.scala:126:16] icol <= next_icol[15:0]; // @[Mux.scala:126:16] ich <= next_ich[15:0]; // @[Mux.scala:126:16] end always @(posedge) Pipeline_11 command_p ( // @[LoopConv.scala:313:25] .clock (clock), .reset (reset), .io_in_ready (_command_p_io_in_ready), .io_in_valid (_command_p_io_in_valid_T_4), // @[LoopConv.scala:342:69] .io_in_bits_cmd_inst_funct (_command_p_io_in_bits_cmd_T_1_inst_funct), // @[LoopConv.scala:343:34] .io_in_bits_cmd_rs1 (_command_p_io_in_bits_cmd_T_1_rs1), // @[LoopConv.scala:343:34] .io_in_bits_cmd_rs2 (_command_p_io_in_bits_cmd_T_1_rs2), // @[LoopConv.scala:343:34] .io_in_bits_dram_addr (dram_addr), // @[LoopConv.scala:286:22] .io_in_bits_spad_addr (spad_addr), // @[LoopConv.scala:287:22] .io_in_bits_I (I), // @[Mux.scala:126:16] .io_in_bits_K (K), // @[LoopConv.scala:302:14] .io_out_ready (_command_p_io_out_ready_T_1), // @[LoopConv.scala:349:42] .io_out_valid (_command_p_io_out_valid), .io_out_bits_cmd_inst_funct (_command_p_io_out_bits_cmd_inst_funct), .io_out_bits_cmd_inst_rs2 (io_cmd_bits_inst_rs2_0), .io_out_bits_cmd_inst_rs1 (io_cmd_bits_inst_rs1_0), .io_out_bits_cmd_inst_xd (io_cmd_bits_inst_xd_0), .io_out_bits_cmd_inst_xs1 (io_cmd_bits_inst_xs1_0), .io_out_bits_cmd_inst_xs2 (io_cmd_bits_inst_xs2_0), .io_out_bits_cmd_inst_rd (io_cmd_bits_inst_rd_0), .io_out_bits_cmd_inst_opcode (io_cmd_bits_inst_opcode_0), .io_out_bits_cmd_rs1 (_command_p_io_out_bits_cmd_rs1), .io_out_bits_cmd_rs2 (_command_p_io_out_bits_cmd_rs2), .io_out_bits_cmd_status_debug (io_cmd_bits_status_debug_0), .io_out_bits_cmd_status_cease (io_cmd_bits_status_cease_0), .io_out_bits_cmd_status_wfi (io_cmd_bits_status_wfi_0), .io_out_bits_cmd_status_isa (io_cmd_bits_status_isa_0), .io_out_bits_cmd_status_dprv (io_cmd_bits_status_dprv_0), .io_out_bits_cmd_status_dv (io_cmd_bits_status_dv_0), .io_out_bits_cmd_status_prv (io_cmd_bits_status_prv_0), .io_out_bits_cmd_status_v (io_cmd_bits_status_v_0), .io_out_bits_cmd_status_sd (io_cmd_bits_status_sd_0), .io_out_bits_cmd_status_zero2 (io_cmd_bits_status_zero2_0), .io_out_bits_cmd_status_mpv (io_cmd_bits_status_mpv_0), .io_out_bits_cmd_status_gva (io_cmd_bits_status_gva_0), .io_out_bits_cmd_status_mbe (io_cmd_bits_status_mbe_0), .io_out_bits_cmd_status_sbe (io_cmd_bits_status_sbe_0), .io_out_bits_cmd_status_sxl (io_cmd_bits_status_sxl_0), .io_out_bits_cmd_status_uxl (io_cmd_bits_status_uxl_0), .io_out_bits_cmd_status_sd_rv32 (io_cmd_bits_status_sd_rv32_0), .io_out_bits_cmd_status_zero1 (io_cmd_bits_status_zero1_0), .io_out_bits_cmd_status_tsr (io_cmd_bits_status_tsr_0), .io_out_bits_cmd_status_tw (io_cmd_bits_status_tw_0), .io_out_bits_cmd_status_tvm (io_cmd_bits_status_tvm_0), .io_out_bits_cmd_status_mxr (io_cmd_bits_status_mxr_0), .io_out_bits_cmd_status_sum (io_cmd_bits_status_sum_0), .io_out_bits_cmd_status_mprv (io_cmd_bits_status_mprv_0), .io_out_bits_cmd_status_xs (io_cmd_bits_status_xs_0), .io_out_bits_cmd_status_fs (io_cmd_bits_status_fs_0), .io_out_bits_cmd_status_mpp (io_cmd_bits_status_mpp_0), .io_out_bits_cmd_status_vs (io_cmd_bits_status_vs_0), .io_out_bits_cmd_status_spp (io_cmd_bits_status_spp_0), .io_out_bits_cmd_status_mpie (io_cmd_bits_status_mpie_0), .io_out_bits_cmd_status_ube (io_cmd_bits_status_ube_0), .io_out_bits_cmd_status_spie (io_cmd_bits_status_spie_0), .io_out_bits_cmd_status_upie (io_cmd_bits_status_upie_0), .io_out_bits_cmd_status_mie (io_cmd_bits_status_mie_0), .io_out_bits_cmd_status_hie (io_cmd_bits_status_hie_0), .io_out_bits_cmd_status_sie (io_cmd_bits_status_sie_0), .io_out_bits_cmd_status_uie (io_cmd_bits_status_uie_0), .io_out_bits_dram_addr (_command_p_io_out_bits_dram_addr), .io_out_bits_spad_addr (_mvin_cmd_rs2_local_addr_result_result_T), .io_out_bits_I (_command_p_io_out_bits_I), .io_out_bits_K (_mvin_cmd_rs2_num_cols_T), .io_busy (_command_p_io_busy) ); // @[LoopConv.scala:313:25] assign io_cmd_bits_inst_funct_0 = _command_p_io_out_bits_cmd_inst_funct; // @[LoopConv.scala:235:7, :313:25] assign io_req_ready = io_req_ready_0; // @[LoopConv.scala:235:7] assign io_cmd_valid = io_cmd_valid_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_funct = io_cmd_bits_inst_funct_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_rs2 = io_cmd_bits_inst_rs2_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_rs1 = io_cmd_bits_inst_rs1_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_xd = io_cmd_bits_inst_xd_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_xs1 = io_cmd_bits_inst_xs1_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_xs2 = io_cmd_bits_inst_xs2_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_rd = io_cmd_bits_inst_rd_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_opcode = io_cmd_bits_inst_opcode_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_rs1 = io_cmd_bits_rs1_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_rs2 = io_cmd_bits_rs2_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_debug = io_cmd_bits_status_debug_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_cease = io_cmd_bits_status_cease_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_wfi = io_cmd_bits_status_wfi_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_isa = io_cmd_bits_status_isa_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_dprv = io_cmd_bits_status_dprv_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_dv = io_cmd_bits_status_dv_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_prv = io_cmd_bits_status_prv_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_v = io_cmd_bits_status_v_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_sd = io_cmd_bits_status_sd_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_zero2 = io_cmd_bits_status_zero2_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_mpv = io_cmd_bits_status_mpv_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_gva = io_cmd_bits_status_gva_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_mbe = io_cmd_bits_status_mbe_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_sbe = io_cmd_bits_status_sbe_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_sxl = io_cmd_bits_status_sxl_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_uxl = io_cmd_bits_status_uxl_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_sd_rv32 = io_cmd_bits_status_sd_rv32_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_zero1 = io_cmd_bits_status_zero1_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_tsr = io_cmd_bits_status_tsr_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_tw = io_cmd_bits_status_tw_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_tvm = io_cmd_bits_status_tvm_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_mxr = io_cmd_bits_status_mxr_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_sum = io_cmd_bits_status_sum_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_mprv = io_cmd_bits_status_mprv_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_xs = io_cmd_bits_status_xs_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_fs = io_cmd_bits_status_fs_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_mpp = io_cmd_bits_status_mpp_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_vs = io_cmd_bits_status_vs_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_spp = io_cmd_bits_status_spp_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_mpie = io_cmd_bits_status_mpie_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_ube = io_cmd_bits_status_ube_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_spie = io_cmd_bits_status_spie_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_upie = io_cmd_bits_status_upie_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_mie = io_cmd_bits_status_mie_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_hie = io_cmd_bits_status_hie_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_sie = io_cmd_bits_status_sie_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_uie = io_cmd_bits_status_uie_0; // @[LoopConv.scala:235:7] assign io_idle = io_idle_0; // @[LoopConv.scala:235:7] assign io_loop_id = io_loop_id_0; // @[LoopConv.scala:235:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_40( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [26:0] _GEN_0 = {23'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [8:0] b_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [8:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [1:0] _GEN_1 = {1'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [1:0] _GEN_6 = {1'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [7:0] inflight_2; // @[Monitor.scala:828:27] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_9 = {5'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35] wire [7:0] d_set = _GEN_8 ? 8'h1 << _GEN_9 : 8'h0; // @[OneHot.scala:58:35] wire _GEN_10 = io_in_e_ready & io_in_e_valid; // @[Decoupled.scala:51:35] wire [7:0] _GEN_11 = {5'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File SourceE.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ class SourceERequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val sink = UInt(params.outer.bundle.sinkBits.W) } class SourceE(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceERequest(params))) val e = Decoupled(new TLBundleE(params.outer.bundle)) }) // ready must be a register, because we derive valid from ready require (!params.micro.outerBuf.e.pipe && params.micro.outerBuf.e.isDefined) val e = Wire(chiselTypeOf(io.e)) io.e <> params.micro.outerBuf.e(e) io.req.ready := e.ready e.valid := io.req.valid e.bits.sink := io.req.bits.sink // we can't cover valid+!ready, because no backpressure on E is common }	module SourceE_4( // @[SourceE.scala:29:7] input clock, // @[SourceE.scala:29:7] input reset, // @[SourceE.scala:29:7] output io_req_ready, // @[SourceE.scala:31:14] input io_req_valid, // @[SourceE.scala:31:14] input [2:0] io_req_bits_sink, // @[SourceE.scala:31:14] output io_e_valid, // @[SourceE.scala:31:14] output [2:0] io_e_bits_sink // @[SourceE.scala:31:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceE.scala:29:7] wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceE.scala:29:7] wire io_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire e_ready; // @[SourceE.scala:39:15] wire e_valid = io_req_valid_0; // @[SourceE.scala:29:7, :39:15] wire [2:0] e_bits_sink = io_req_bits_sink_0; // @[SourceE.scala:29:7, :39:15] wire io_req_ready_0; // @[SourceE.scala:29:7] wire [2:0] io_e_bits_sink_0; // @[SourceE.scala:29:7] wire io_e_valid_0; // @[SourceE.scala:29:7] assign io_req_ready_0 = e_ready; // @[SourceE.scala:29:7, :39:15] Queue2_TLBundleE_a32d64s4k3z3c_4 io_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (e_ready), .io_enq_valid (e_valid), // @[SourceE.scala:39:15] .io_enq_bits_sink (e_bits_sink), // @[SourceE.scala:39:15] .io_deq_valid (io_e_valid_0), .io_deq_bits_sink (io_e_bits_sink_0) ); // @[Decoupled.scala:362:21] assign io_req_ready = io_req_ready_0; // @[SourceE.scala:29:7] assign io_e_valid = io_e_valid_0; // @[SourceE.scala:29:7] assign io_e_bits_sink = io_e_bits_sink_0; // @[SourceE.scala:29:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLBuffer_a32d64s4k1z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire auto_in_a_bits_user_amba_prot_bufferable_0 = auto_in_a_bits_user_amba_prot_bufferable; // @[Buffer.scala:40:9] wire auto_in_a_bits_user_amba_prot_modifiable_0 = auto_in_a_bits_user_amba_prot_modifiable; // @[Buffer.scala:40:9] wire auto_in_a_bits_user_amba_prot_readalloc_0 = auto_in_a_bits_user_amba_prot_readalloc; // @[Buffer.scala:40:9] wire auto_in_a_bits_user_amba_prot_writealloc_0 = auto_in_a_bits_user_amba_prot_writealloc; // @[Buffer.scala:40:9] wire auto_in_a_bits_user_amba_prot_privileged_0 = auto_in_a_bits_user_amba_prot_privileged; // @[Buffer.scala:40:9] wire auto_in_a_bits_user_amba_prot_secure_0 = auto_in_a_bits_user_amba_prot_secure; // @[Buffer.scala:40:9] wire auto_in_a_bits_user_amba_prot_fetch_0 = auto_in_a_bits_user_amba_prot_fetch; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [2:0] auto_in_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_user_amba_prot_bufferable = auto_in_a_bits_user_amba_prot_bufferable_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_user_amba_prot_modifiable = auto_in_a_bits_user_amba_prot_modifiable_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_user_amba_prot_readalloc = auto_in_a_bits_user_amba_prot_readalloc_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_user_amba_prot_writealloc = auto_in_a_bits_user_amba_prot_writealloc_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_user_amba_prot_privileged = auto_in_a_bits_user_amba_prot_privileged_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_user_amba_prot_secure = auto_in_a_bits_user_amba_prot_secure_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_user_amba_prot_fetch = auto_in_a_bits_user_amba_prot_fetch_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_user_amba_prot_bufferable; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_user_amba_prot_modifiable; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_user_amba_prot_readalloc; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_user_amba_prot_writealloc; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_user_amba_prot_privileged; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_user_amba_prot_secure; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_user_amba_prot_fetch; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_user_amba_prot_bufferable_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_user_amba_prot_modifiable_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_user_amba_prot_readalloc_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_user_amba_prot_writealloc_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_user_amba_prot_privileged_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_user_amba_prot_secure_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_user_amba_prot_fetch_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_bufferable_0 = nodeOut_a_bits_user_amba_prot_bufferable; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_modifiable_0 = nodeOut_a_bits_user_amba_prot_modifiable; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_readalloc_0 = nodeOut_a_bits_user_amba_prot_readalloc; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_writealloc_0 = nodeOut_a_bits_user_amba_prot_writealloc; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_privileged_0 = nodeOut_a_bits_user_amba_prot_privileged; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_secure_0 = nodeOut_a_bits_user_amba_prot_secure; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_fetch_0 = nodeOut_a_bits_user_amba_prot_fetch; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_18 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_user_amba_prot_bufferable (nodeIn_a_bits_user_amba_prot_bufferable), // @[MixedNode.scala:551:17] .io_in_a_bits_user_amba_prot_modifiable (nodeIn_a_bits_user_amba_prot_modifiable), // @[MixedNode.scala:551:17] .io_in_a_bits_user_amba_prot_readalloc (nodeIn_a_bits_user_amba_prot_readalloc), // @[MixedNode.scala:551:17] .io_in_a_bits_user_amba_prot_writealloc (nodeIn_a_bits_user_amba_prot_writealloc), // @[MixedNode.scala:551:17] .io_in_a_bits_user_amba_prot_privileged (nodeIn_a_bits_user_amba_prot_privileged), // @[MixedNode.scala:551:17] .io_in_a_bits_user_amba_prot_secure (nodeIn_a_bits_user_amba_prot_secure), // @[MixedNode.scala:551:17] .io_in_a_bits_user_amba_prot_fetch (nodeIn_a_bits_user_amba_prot_fetch), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s4k1z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_user_amba_prot_bufferable (nodeIn_a_bits_user_amba_prot_bufferable), // @[MixedNode.scala:551:17] .io_enq_bits_user_amba_prot_modifiable (nodeIn_a_bits_user_amba_prot_modifiable), // @[MixedNode.scala:551:17] .io_enq_bits_user_amba_prot_readalloc (nodeIn_a_bits_user_amba_prot_readalloc), // @[MixedNode.scala:551:17] .io_enq_bits_user_amba_prot_writealloc (nodeIn_a_bits_user_amba_prot_writealloc), // @[MixedNode.scala:551:17] .io_enq_bits_user_amba_prot_privileged (nodeIn_a_bits_user_amba_prot_privileged), // @[MixedNode.scala:551:17] .io_enq_bits_user_amba_prot_secure (nodeIn_a_bits_user_amba_prot_secure), // @[MixedNode.scala:551:17] .io_enq_bits_user_amba_prot_fetch (nodeIn_a_bits_user_amba_prot_fetch), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_user_amba_prot_bufferable (nodeOut_a_bits_user_amba_prot_bufferable), .io_deq_bits_user_amba_prot_modifiable (nodeOut_a_bits_user_amba_prot_modifiable), .io_deq_bits_user_amba_prot_readalloc (nodeOut_a_bits_user_amba_prot_readalloc), .io_deq_bits_user_amba_prot_writealloc (nodeOut_a_bits_user_amba_prot_writealloc), .io_deq_bits_user_amba_prot_privileged (nodeOut_a_bits_user_amba_prot_privileged), .io_deq_bits_user_amba_prot_secure (nodeOut_a_bits_user_amba_prot_secure), .io_deq_bits_user_amba_prot_fetch (nodeOut_a_bits_user_amba_prot_fetch), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s4k1z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_bufferable = auto_out_a_bits_user_amba_prot_bufferable_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_modifiable = auto_out_a_bits_user_amba_prot_modifiable_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_readalloc = auto_out_a_bits_user_amba_prot_readalloc_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_writealloc = auto_out_a_bits_user_amba_prot_writealloc_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_privileged = auto_out_a_bits_user_amba_prot_privileged_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_secure = auto_out_a_bits_user_amba_prot_secure_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_fetch = auto_out_a_bits_user_amba_prot_fetch_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_1( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [4:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [26:0] _GEN_0 = {23'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [4:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [8:0] b_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [8:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [3:0] _GEN_1 = {2'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [3:0] _GEN_4 = {2'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [3:0] _GEN_6 = {2'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [31:0] inflight_2; // @[Monitor.scala:828:27] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [31:0] _GEN_9 = {27'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35] wire [31:0] d_set = _GEN_8 ? 32'h1 << _GEN_9 : 32'h0; // @[OneHot.scala:58:35] wire _GEN_10 = io_in_e_ready & io_in_e_valid; // @[Decoupled.scala:51:35] wire [31:0] _GEN_11 = {27'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_379( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid \|\| io.clear \|\| io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 \|\| rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_\|\|_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_\|\|_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready \|\| agen_ready \|\| dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }	module IssueSlot_40( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [1:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7] wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_327( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_236( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_253 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Protocol.scala: package rerocc.bus import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import rerocc.client.{ReRoCCClientParams} import rerocc.manager.{ReRoCCManagerParams} object ReRoCCProtocol { val width = 3 val mAcquire = 0.U(width.W) // beat0: data = inst // beat1: data = mstatus[63:0] // beat2: data = mstatus[127:64] val mInst = 1.U(width.W) // beat0: data = mstatus[63:0] // beat1: data = mstatus[127:0] val mUStatus = 2.U(width.W) // beat0: data = ptbr val mUPtbr = 3.U(width.W) val mRelease = 4.U(width.W) val mUnbusy = 5.U(width.W) // data // data = acquired val sAcqResp = 0.U(width.W) // data = 0 val sInstAck = 1.U(width.W) // beat0: data = data // beat1: data = rd val sWrite = 2.U(width.W) val sRelResp = 3.U(width.W) val sUnbusyAck = 4.U(width.W) val MAX_BEATS = 3 } class ReRoCCMsgBundle(val params: ReRoCCBundleParams) extends Bundle { val opcode = UInt(ReRoCCProtocol.width.W) val client_id = UInt(params.clientIdBits.W) val manager_id = UInt(params.managerIdBits.W) val data = UInt(64.W) } object ReRoCCMsgFirstLast { def apply(m: DecoupledIO[ReRoCCMsgBundle], isReq: Boolean): (Bool, Bool, UInt) = { val beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W)) val max_beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W)) val first = beat === 0.U val last = Wire(Bool()) val inst = m.bits.data.asTypeOf(new RoCCInstruction) when (m.fire && first) { max_beat := 0.U if (isReq) { when (m.bits.opcode === ReRoCCProtocol.mInst) { max_beat := inst.xs1 +& inst.xs2 } .elsewhen (m.bits.opcode === ReRoCCProtocol.mUStatus) { max_beat := 1.U } } else { when (m.bits.opcode === ReRoCCProtocol.sWrite) { max_beat := 1.U } } } last := true.B if (isReq) { when (m.bits.opcode === ReRoCCProtocol.mUStatus) { last := beat === max_beat && !first } .elsewhen (m.bits.opcode === ReRoCCProtocol.mInst) { last := Mux(first, !inst.xs1 && !inst.xs2, beat === max_beat) } } else { when (m.bits.opcode === ReRoCCProtocol.sWrite) { last := beat === max_beat && !first } } when (m.fire) { beat := beat + 1.U } when (m.fire && last) { max_beat := 0.U beat := 0.U } (first, last, beat) } } class ReRoCCBundle(val params: ReRoCCBundleParams) extends Bundle { val req = Decoupled(new ReRoCCMsgBundle(params)) val resp = Flipped(Decoupled(new ReRoCCMsgBundle(params))) } case class EmptyParams() object ReRoCCImp extends SimpleNodeImp[ReRoCCClientPortParams, ReRoCCManagerPortParams, ReRoCCEdgeParams, ReRoCCBundle] { def edge(pd: ReRoCCClientPortParams, pu: ReRoCCManagerPortParams, p: Parameters, sourceInfo: SourceInfo) = { ReRoCCEdgeParams(pu, pd) } def bundle(e: ReRoCCEdgeParams) = new ReRoCCBundle(e.bundle) def render(ei: ReRoCCEdgeParams) = RenderedEdge(colour = "#000000" /* black /) } case class ReRoCCClientNode(clientParams: ReRoCCClientParams)(implicit valName: ValName) extends SourceNode(ReRoCCImp)(Seq(ReRoCCClientPortParams(Seq(clientParams)))) case class ReRoCCManagerNode(managerParams: ReRoCCManagerParams)(implicit valName: ValName) extends SinkNode(ReRoCCImp)(Seq(ReRoCCManagerPortParams(Seq(managerParams)))) class ReRoCCBuffer(b: BufferParams = BufferParams.default)(implicit p: Parameters) extends LazyModule { val node = new AdapterNode(ReRoCCImp)({s => s}, {s => s}) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, _), (out, _)) => out.req <> b(in.req) in.resp <> b(out.resp) } } } object ReRoCCBuffer { def apply(b: BufferParams = BufferParams.default)(implicit p: Parameters) = { val rerocc_buffer = LazyModule(new ReRoCCBuffer(b)(p)) rerocc_buffer.node } } case class ReRoCCIdentityNode()(implicit valName: ValName) extends IdentityNode(ReRoCCImp)() File Arbiter.scala: package rerocc.bus import chisel3._ import chisel3.util._ import freechips.rocketchip.util.{HellaLockingArbiter} class ReRoCCMsgArbiter(bundle: ReRoCCBundleParams, arbN: Int, isReq: Boolean) extends HellaLockingArbiter(new ReRoCCMsgBundle(bundle), arbN, false) { when (io.out.fire) { when (!locked) { lockIdx := choice locked := true.B } when (ReRoCCMsgFirstLast(io.out, isReq)._2) { locked := false.B } } } File Arbiters.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters /* A generalized locking RR arbiter that addresses the limitations of the * version in the Chisel standard library / abstract class HellaLockingArbiter[T <: Data](typ: T, arbN: Int, rr: Boolean = false) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(arbN, Decoupled(typ.cloneType))) val out = Decoupled(typ.cloneType) }) def rotateLeft[T <: Data](norm: Vec[T], rot: UInt): Vec[T] = { val n = norm.size VecInit.tabulate(n) { i => Mux(rot < (n - i).U, norm(i.U + rot), norm(rot - (n - i).U)) } } val lockIdx = RegInit(0.U(log2Up(arbN).W)) val locked = RegInit(false.B) val choice = if (rr) { PriorityMux( rotateLeft(VecInit(io.in.map(_.valid)), lockIdx + 1.U), rotateLeft(VecInit((0 until arbN).map(_.U)), lockIdx + 1.U)) } else { PriorityEncoder(io.in.map(_.valid)) } val chosen = Mux(locked, lockIdx, choice) for (i <- 0 until arbN) { io.in(i).ready := io.out.ready && chosen === i.U } io.out.valid := io.in(chosen).valid io.out.bits := io.in(chosen).bits } /* This locking arbiter determines when it is safe to unlock * by peeking at the data / class HellaPeekingArbiter[T <: Data]( typ: T, arbN: Int, canUnlock: T => Bool, needsLock: Option[T => Bool] = None, rr: Boolean = false) extends HellaLockingArbiter(typ, arbN, rr) { def realNeedsLock(data: T): Bool = needsLock.map(_(data)).getOrElse(true.B) when (io.out.fire) { when (!locked && realNeedsLock(io.out.bits)) { lockIdx := choice locked := true.B } // the unlock statement takes precedent when (canUnlock(io.out.bits)) { locked := false.B } } } /* This arbiter determines when it is safe to unlock by counting transactions / class HellaCountingArbiter[T <: Data]( typ: T, arbN: Int, count: Int, val needsLock: Option[T => Bool] = None, rr: Boolean = false) extends HellaLockingArbiter(typ, arbN, rr) { def realNeedsLock(data: T): Bool = needsLock.map(_(data)).getOrElse(true.B) // if count is 1, you should use a non-locking arbiter require(count > 1, "CountingArbiter cannot have count <= 1") val lock_ctr = Counter(count) when (io.out.fire) { when (!locked && realNeedsLock(io.out.bits)) { lockIdx := choice locked := true.B lock_ctr.inc() } when (locked) { when (lock_ctr.inc()) { locked := false.B } } } } /* This arbiter preserves the order of responses */ class InOrderArbiter[T <: Data, U <: Data](reqTyp: T, respTyp: U, n: Int) (implicit p: Parameters) extends Module { val io = IO(new Bundle { val in_req = Flipped(Vec(n, Decoupled(reqTyp))) val in_resp = Vec(n, Decoupled(respTyp)) val out_req = Decoupled(reqTyp) val out_resp = Flipped(Decoupled(respTyp)) }) if (n > 1) { val route_q = Module(new Queue(UInt(log2Up(n).W), 2)) val req_arb = Module(new RRArbiter(reqTyp, n)) req_arb.io.in <> io.in_req val req_helper = DecoupledHelper( req_arb.io.out.valid, route_q.io.enq.ready, io.out_req.ready) io.out_req.bits := req_arb.io.out.bits io.out_req.valid := req_helper.fire(io.out_req.ready) route_q.io.enq.bits := req_arb.io.chosen route_q.io.enq.valid := req_helper.fire(route_q.io.enq.ready) req_arb.io.out.ready := req_helper.fire(req_arb.io.out.valid) val resp_sel = route_q.io.deq.bits val resp_ready = io.in_resp(resp_sel).ready val resp_helper = DecoupledHelper( resp_ready, route_q.io.deq.valid, io.out_resp.valid) val resp_valid = resp_helper.fire(resp_ready) for (i <- 0 until n) { io.in_resp(i).bits := io.out_resp.bits io.in_resp(i).valid := resp_valid && resp_sel === i.U } route_q.io.deq.ready := resp_helper.fire(route_q.io.deq.valid) io.out_resp.ready := resp_helper.fire(io.out_resp.valid) } else { io.out_req <> io.in_req.head io.in_resp.head <> io.out_resp } }	module ReRoCCMsgArbiter_7( // @[Arbiter.scala:7:7] input clock, // @[Arbiter.scala:7:7] input reset, // @[Arbiter.scala:7:7] output io_in_0_ready, // @[Arbiters.scala:14:14] input io_in_0_valid, // @[Arbiters.scala:14:14] input [2:0] io_in_0_bits_opcode, // @[Arbiters.scala:14:14] input [3:0] io_in_0_bits_client_id, // @[Arbiters.scala:14:14] input [2:0] io_in_0_bits_manager_id, // @[Arbiters.scala:14:14] input [63:0] io_in_0_bits_data, // @[Arbiters.scala:14:14] input io_out_ready, // @[Arbiters.scala:14:14] output io_out_valid, // @[Arbiters.scala:14:14] output [2:0] io_out_bits_opcode, // @[Arbiters.scala:14:14] output [3:0] io_out_bits_client_id, // @[Arbiters.scala:14:14] output [2:0] io_out_bits_manager_id, // @[Arbiters.scala:14:14] output [63:0] io_out_bits_data // @[Arbiters.scala:14:14] ); wire io_in_0_valid_0 = io_in_0_valid; // @[Arbiter.scala:7:7] wire [2:0] io_in_0_bits_opcode_0 = io_in_0_bits_opcode; // @[Arbiter.scala:7:7] wire [3:0] io_in_0_bits_client_id_0 = io_in_0_bits_client_id; // @[Arbiter.scala:7:7] wire [2:0] io_in_0_bits_manager_id_0 = io_in_0_bits_manager_id; // @[Arbiter.scala:7:7] wire [63:0] io_in_0_bits_data_0 = io_in_0_bits_data; // @[Arbiter.scala:7:7] wire io_out_ready_0 = io_out_ready; // @[Arbiter.scala:7:7] wire _io_in_0_ready_T = 1'h1; // @[Arbiters.scala:40:46] wire chosen = 1'h0; // @[Arbiters.scala:37:19] wire _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] wire _io_out_valid_WIRE = 1'h0; wire _io_out_bits_WIRE = 1'h0; wire io_out_valid_0 = io_in_0_valid_0; // @[Arbiter.scala:7:7] wire [2:0] io_out_bits_opcode_0 = io_in_0_bits_opcode_0; // @[Arbiter.scala:7:7] wire [3:0] io_out_bits_client_id_0 = io_in_0_bits_client_id_0; // @[Arbiter.scala:7:7] wire [2:0] io_out_bits_manager_id_0 = io_in_0_bits_manager_id_0; // @[Arbiter.scala:7:7] wire [63:0] io_out_bits_data_0 = io_in_0_bits_data_0; // @[Arbiter.scala:7:7] assign _io_in_0_ready_T_1 = io_out_ready_0; // @[Arbiters.scala:40:36] wire io_in_0_ready_0; // @[Arbiter.scala:7:7] reg locked; // @[Arbiters.scala:27:23] assign io_in_0_ready_0 = _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] reg [1:0] beat; // @[Protocol.scala:54:23] reg [1:0] max_beat; // @[Protocol.scala:55:27] wire first = beat == 2'h0; // @[Protocol.scala:54:23, :56:22] wire last; // @[Protocol.scala:57:20] wire [6:0] _inst_T_7; // @[Protocol.scala:58:36] wire [4:0] _inst_T_6; // @[Protocol.scala:58:36] wire [4:0] _inst_T_5; // @[Protocol.scala:58:36] wire _inst_T_4; // @[Protocol.scala:58:36] wire _inst_T_3; // @[Protocol.scala:58:36] wire _inst_T_2; // @[Protocol.scala:58:36] wire [4:0] _inst_T_1; // @[Protocol.scala:58:36] wire [6:0] _inst_T; // @[Protocol.scala:58:36] wire [6:0] inst_funct; // @[Protocol.scala:58:36] wire [4:0] inst_rs2; // @[Protocol.scala:58:36] wire [4:0] inst_rs1; // @[Protocol.scala:58:36] wire inst_xd; // @[Protocol.scala:58:36] wire inst_xs1; // @[Protocol.scala:58:36] wire inst_xs2; // @[Protocol.scala:58:36] wire [4:0] inst_rd; // @[Protocol.scala:58:36] wire [6:0] inst_opcode; // @[Protocol.scala:58:36] wire [31:0] _inst_WIRE = io_out_bits_data_0[31:0]; // @[Protocol.scala:58:36] assign _inst_T = _inst_WIRE[6:0]; // @[Protocol.scala:58:36] assign inst_opcode = _inst_T; // @[Protocol.scala:58:36] assign _inst_T_1 = _inst_WIRE[11:7]; // @[Protocol.scala:58:36] assign inst_rd = _inst_T_1; // @[Protocol.scala:58:36] assign _inst_T_2 = _inst_WIRE[12]; // @[Protocol.scala:58:36] assign inst_xs2 = _inst_T_2; // @[Protocol.scala:58:36] assign _inst_T_3 = _inst_WIRE[13]; // @[Protocol.scala:58:36] assign inst_xs1 = _inst_T_3; // @[Protocol.scala:58:36] assign _inst_T_4 = _inst_WIRE[14]; // @[Protocol.scala:58:36] assign inst_xd = _inst_T_4; // @[Protocol.scala:58:36] assign _inst_T_5 = _inst_WIRE[19:15]; // @[Protocol.scala:58:36] assign inst_rs1 = _inst_T_5; // @[Protocol.scala:58:36] assign _inst_T_6 = _inst_WIRE[24:20]; // @[Protocol.scala:58:36] assign inst_rs2 = _inst_T_6; // @[Protocol.scala:58:36] assign _inst_T_7 = _inst_WIRE[31:25]; // @[Protocol.scala:58:36] assign inst_funct = _inst_T_7; // @[Protocol.scala:58:36] wire [1:0] _max_beat_T = {1'h0, inst_xs1} + {1'h0, inst_xs2}; // @[Protocol.scala:58:36, :63:32] wire _GEN = beat == max_beat; // @[Protocol.scala:54:23, :55:27, :77:22] wire _last_T; // @[Protocol.scala:77:22] assign _last_T = _GEN; // @[Protocol.scala:77:22] wire _last_T_6; // @[Protocol.scala:79:57] assign _last_T_6 = _GEN; // @[Protocol.scala:77:22, :79:57] wire _last_T_1 = ~first; // @[Protocol.scala:56:22, :77:38] wire _last_T_2 = _last_T & _last_T_1; // @[Protocol.scala:77:{22,35,38}] wire _last_T_3 = ~inst_xs1; // @[Protocol.scala:58:36, :79:28] wire _last_T_4 = ~inst_xs2; // @[Protocol.scala:58:36, :79:41] wire _last_T_5 = _last_T_3 & _last_T_4; // @[Protocol.scala:79:{28,38,41}] wire _last_T_7 = first ? _last_T_5 : _last_T_6; // @[Protocol.scala:56:22, :79:{20,38,57}] assign last = io_out_bits_opcode_0 == 3'h2 ? _last_T_2 : io_out_bits_opcode_0 != 3'h1 \| _last_T_7; // @[Protocol.scala:57:20, :74:10, :76:{27,56}, :77:{14,35}, :78:{34,60}, :79:{14,20}, :87:34] wire [2:0] _beat_T = {1'h0, beat} + 3'h1; // @[Protocol.scala:54:23, :87:34] wire [1:0] _beat_T_1 = _beat_T[1:0]; // @[Protocol.scala:87:34] wire _T_9 = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Arbiter.scala:7:7] if (reset) begin // @[Arbiter.scala:7:7] locked <= 1'h0; // @[Arbiters.scala:27:23] beat <= 2'h0; // @[Protocol.scala:54:23] max_beat <= 2'h0; // @[Protocol.scala:55:27] end else begin // @[Arbiter.scala:7:7] if (_T_9) // @[Decoupled.scala:51:35] locked <= ~last; // @[Arbiters.scala:27:23] if (_T_9 & last) begin // @[Decoupled.scala:51:35] beat <= 2'h0; // @[Protocol.scala:54:23] max_beat <= 2'h0; // @[Protocol.scala:55:27] end else begin // @[Protocol.scala:88:18] if (_T_9) // @[Decoupled.scala:51:35] beat <= _beat_T_1; // @[Protocol.scala:54:23, :87:34] if (_T_9 & first) // @[Decoupled.scala:51:35] max_beat <= io_out_bits_opcode_0 == 3'h1 ? _max_beat_T : {1'h0, io_out_bits_opcode_0 == 3'h2}; // @[Protocol.scala:55:27, :60:16, :62:{29,55}, :63:{20,32}, :64:{36,65}, :65:20, :87:34] end end always @(posedge) assign io_in_0_ready = io_in_0_ready_0; // @[Arbiter.scala:7:7] assign io_out_valid = io_out_valid_0; // @[Arbiter.scala:7:7] assign io_out_bits_opcode = io_out_bits_opcode_0; // @[Arbiter.scala:7:7] assign io_out_bits_client_id = io_out_bits_client_id_0; // @[Arbiter.scala:7:7] assign io_out_bits_manager_id = io_out_bits_manager_id_0; // @[Arbiter.scala:7:7] assign io_out_bits_data = io_out_bits_data_0; // @[Arbiter.scala:7:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module mem_24x75( // @[InputUnit.scala:85:18] input [4:0] R0_addr, input R0_en, input R0_clk, output [74:0] R0_data, input [4:0] R1_addr, input R1_en, input R1_clk, output [74:0] R1_data, input [4:0] R2_addr, input R2_en, input R2_clk, output [74:0] R2_data, input [4:0] R3_addr, input R3_en, input R3_clk, output [74:0] R3_data, input [4:0] R4_addr, input R4_en, input R4_clk, output [74:0] R4_data, input [4:0] R5_addr, input R5_en, input R5_clk, output [74:0] R5_data, input [4:0] R6_addr, input R6_en, input R6_clk, output [74:0] R6_data, input [4:0] R7_addr, input R7_en, input R7_clk, output [74:0] R7_data, input [4:0] R8_addr, input R8_en, input R8_clk, output [74:0] R8_data, input [4:0] R9_addr, input R9_en, input R9_clk, output [74:0] R9_data, input [4:0] R10_addr, input R10_en, input R10_clk, output [74:0] R10_data, input [4:0] R11_addr, input R11_en, input R11_clk, output [74:0] R11_data, input [4:0] R12_addr, input R12_en, input R12_clk, output [74:0] R12_data, input [4:0] R13_addr, input R13_en, input R13_clk, output [74:0] R13_data, input [4:0] R14_addr, input R14_en, input R14_clk, output [74:0] R14_data, input [4:0] R15_addr, input R15_en, input R15_clk, output [74:0] R15_data, input [4:0] R16_addr, input R16_en, input R16_clk, output [74:0] R16_data, input [4:0] R17_addr, input R17_en, input R17_clk, output [74:0] R17_data, input [4:0] R18_addr, input R18_en, input R18_clk, output [74:0] R18_data, input [4:0] R19_addr, input R19_en, input R19_clk, output [74:0] R19_data, input [4:0] R20_addr, input R20_en, input R20_clk, output [74:0] R20_data, input [4:0] R21_addr, input R21_en, input R21_clk, output [74:0] R21_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [74:0] W0_data ); reg [74:0] Memory[0:23]; // @[InputUnit.scala:85:18] always @(posedge W0_clk) begin // @[InputUnit.scala:85:18] if (W0_en & 1'h1) // @[InputUnit.scala:85:18] Memory[W0_addr] <= W0_data; // @[InputUnit.scala:85:18] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_111( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

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Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /* This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }	module IntSyncCrossingSource_n1x1( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0 // @[LazyModuleImp.scala:107:25] ); AsyncResetRegVec_w1_i0 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d (auto_in_0), .io_q (auto_out_sync_0) ); // @[AsyncResetReg.scala:86:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_172( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_193 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_430( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_174 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Atomics.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ class Atomics(params: TLBundleParameters) extends Module { val io = IO(new Bundle { val write = Flipped(Bool()) // ignore opcode val a = Flipped(new TLBundleA(params)) val data_in = Flipped(UInt(params.dataBits.W)) val data_out = UInt(params.dataBits.W) }) // Arithmetic, what to do val adder = io.a.param(2) val unsigned = io.a.param(1) val take_max = io.a.param(0) val signBit = io.a.mask & Cat(1.U, ~io.a.mask >> 1) val inv_d = Mux(adder, io.data_in, ~io.data_in) val sum = (FillInterleaved(8, io.a.mask) & io.a.data) + inv_d def sign(x: UInt): Bool = (Cat(x.asBools.grouped(8).map(_.last).toList.reverse) & signBit).orR val sign_a = sign(io.a.data) val sign_d = sign(io.data_in) val sign_s = sign(sum) val a_bigger_uneq = unsigned === sign_a // result if high bits are unequal val a_bigger = Mux(sign_a === sign_d, !sign_s, a_bigger_uneq) val pick_a = take_max === a_bigger // Logical, what to do val lut = VecInit(Seq( (0x6).U, // XOR (0xe).U, // OR (0x8).U, // AND (0xc).U))( // SWAP io.a.param(1,0)) val logical = Cat((io.a.data.asBools zip io.data_in.asBools).map { case (a, d) => lut(Cat(a, d)) }.reverse) // Operation, what to do? (0=d, 1=a, 2=sum, 3=logical) val select = Mux(io.write, 1.U, VecInit(Seq( 1.U, // PutFullData 1.U, // PutPartialData Mux(adder, 2.U, Mux(pick_a, 1.U, 0.U)), // ArithmeticData 3.U, // LogicalData 0.U, // Get 0.U, // Hint 0.U, // AcquireBlock 0.U))( // AcquirePerm io.a.opcode)) // Only the masked bytes can be modified val selects = io.a.mask.asBools.map(b => Mux(b, select, 0.U)) io.data_out := Cat(selects.zipWithIndex.map { case (s, i) => VecInit(Seq(io.data_in, io.a.data, sum, logical).map(_((i + 1) * 8 - 1, i * 8)))(s) }.reverse) }	module Atomics( // @[Atomics.scala:8:7] input clock, // @[Atomics.scala:8:7] input reset, // @[Atomics.scala:8:7] input io_write, // @[Atomics.scala:10:14] input [2:0] io_a_opcode, // @[Atomics.scala:10:14] input [2:0] io_a_param, // @[Atomics.scala:10:14] input [15:0] io_a_mask, // @[Atomics.scala:10:14] input [127:0] io_a_data, // @[Atomics.scala:10:14] input [127:0] io_data_in, // @[Atomics.scala:10:14] output [127:0] io_data_out // @[Atomics.scala:10:14] ); wire io_write_0 = io_write; // @[Atomics.scala:8:7] wire [2:0] io_a_opcode_0 = io_a_opcode; // @[Atomics.scala:8:7] wire [2:0] io_a_param_0 = io_a_param; // @[Atomics.scala:8:7] wire [15:0] io_a_mask_0 = io_a_mask; // @[Atomics.scala:8:7] wire [127:0] io_a_data_0 = io_a_data; // @[Atomics.scala:8:7] wire [127:0] io_data_in_0 = io_data_in; // @[Atomics.scala:8:7] wire [3:0][3:0] _GEN = '{4'hC, 4'h8, 4'hE, 4'h6}; wire [3:0] _lut_WIRE_0 = 4'h6; // @[Atomics.scala:34:20] wire [3:0] _lut_WIRE_1 = 4'hE; // @[Atomics.scala:34:20] wire [3:0] _lut_WIRE_2 = 4'h8; // @[Atomics.scala:34:20] wire [3:0] _lut_WIRE_3 = 4'hC; // @[Atomics.scala:34:20] wire [1:0] _select_WIRE_0 = 2'h1; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_1 = 2'h1; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_3 = 2'h3; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_4 = 2'h0; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_5 = 2'h0; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_6 = 2'h0; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_7 = 2'h0; // @[Atomics.scala:45:42] wire io_a_corrupt = 1'h0; // @[Atomics.scala:8:7, :10:14] wire [31:0] io_a_address = 32'h0; // @[Atomics.scala:8:7, :10:14] wire [5:0] io_a_source = 6'h0; // @[Atomics.scala:8:7, :10:14] wire [2:0] io_a_size = 3'h0; // @[Atomics.scala:8:7, :10:14] wire [127:0] _io_data_out_T_64; // @[Atomics.scala:58:21] wire [127:0] io_data_out_0; // @[Atomics.scala:8:7] wire adder = io_a_param_0[2]; // @[Atomics.scala:8:7, :18:28] wire unsigned_0 = io_a_param_0[1]; // @[Atomics.scala:8:7, :19:28] wire take_max = io_a_param_0[0]; // @[Atomics.scala:8:7, :20:28] wire [15:0] _signBit_T = ~io_a_mask_0; // @[Atomics.scala:8:7, :22:38] wire [14:0] _signBit_T_1 = _signBit_T[15:1]; // @[Atomics.scala:22:{38,49}] wire [15:0] _signBit_T_2 = {1'h1, _signBit_T_1}; // @[Atomics.scala:22:{32,49}] wire [15:0] signBit = io_a_mask_0 & _signBit_T_2; // @[Atomics.scala:8:7, :22:{27,32}] wire [127:0] _inv_d_T = ~io_data_in_0; // @[Atomics.scala:8:7, :23:38] wire [127:0] inv_d = adder ? io_data_in_0 : _inv_d_T; // @[Atomics.scala:8:7, :18:28, :23:{18,38}] wire _sum_T = io_a_mask_0[0]; // @[Atomics.scala:8:7, :24:29] wire _selects_T = io_a_mask_0[0]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_1 = io_a_mask_0[1]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_1 = io_a_mask_0[1]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_2 = io_a_mask_0[2]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_2 = io_a_mask_0[2]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_3 = io_a_mask_0[3]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_3 = io_a_mask_0[3]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_4 = io_a_mask_0[4]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_4 = io_a_mask_0[4]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_5 = io_a_mask_0[5]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_5 = io_a_mask_0[5]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_6 = io_a_mask_0[6]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_6 = io_a_mask_0[6]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_7 = io_a_mask_0[7]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_7 = io_a_mask_0[7]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_8 = io_a_mask_0[8]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_8 = io_a_mask_0[8]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_9 = io_a_mask_0[9]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_9 = io_a_mask_0[9]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_10 = io_a_mask_0[10]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_10 = io_a_mask_0[10]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_11 = io_a_mask_0[11]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_11 = io_a_mask_0[11]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_12 = io_a_mask_0[12]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_12 = io_a_mask_0[12]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_13 = io_a_mask_0[13]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_13 = io_a_mask_0[13]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_14 = io_a_mask_0[14]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_14 = io_a_mask_0[14]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_15 = io_a_mask_0[15]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_15 = io_a_mask_0[15]; // @[Atomics.scala:8:7, :24:29, :57:27] wire [7:0] _sum_T_16 = {8{_sum_T}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_17 = {8{_sum_T_1}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_18 = {8{_sum_T_2}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_19 = {8{_sum_T_3}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_20 = {8{_sum_T_4}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_21 = {8{_sum_T_5}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_22 = {8{_sum_T_6}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_23 = {8{_sum_T_7}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_24 = {8{_sum_T_8}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_25 = {8{_sum_T_9}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_26 = {8{_sum_T_10}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_27 = {8{_sum_T_11}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_28 = {8{_sum_T_12}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_29 = {8{_sum_T_13}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_30 = {8{_sum_T_14}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_31 = {8{_sum_T_15}}; // @[Atomics.scala:24:29] wire [15:0] sum_lo_lo_lo = {_sum_T_17, _sum_T_16}; // @[Atomics.scala:24:29] wire [15:0] sum_lo_lo_hi = {_sum_T_19, _sum_T_18}; // @[Atomics.scala:24:29] wire [31:0] sum_lo_lo = {sum_lo_lo_hi, sum_lo_lo_lo}; // @[Atomics.scala:24:29] wire [15:0] sum_lo_hi_lo = {_sum_T_21, _sum_T_20}; // @[Atomics.scala:24:29] wire [15:0] sum_lo_hi_hi = {_sum_T_23, _sum_T_22}; // @[Atomics.scala:24:29] wire [31:0] sum_lo_hi = {sum_lo_hi_hi, sum_lo_hi_lo}; // @[Atomics.scala:24:29] wire [63:0] sum_lo = {sum_lo_hi, sum_lo_lo}; // @[Atomics.scala:24:29] wire [15:0] sum_hi_lo_lo = {_sum_T_25, _sum_T_24}; // @[Atomics.scala:24:29] wire [15:0] sum_hi_lo_hi = {_sum_T_27, _sum_T_26}; // @[Atomics.scala:24:29] wire [31:0] sum_hi_lo = {sum_hi_lo_hi, sum_hi_lo_lo}; // @[Atomics.scala:24:29] wire [15:0] sum_hi_hi_lo = {_sum_T_29, _sum_T_28}; // @[Atomics.scala:24:29] wire [15:0] sum_hi_hi_hi = {_sum_T_31, _sum_T_30}; // @[Atomics.scala:24:29] wire [31:0] sum_hi_hi = {sum_hi_hi_hi, sum_hi_hi_lo}; // @[Atomics.scala:24:29] wire [63:0] sum_hi = {sum_hi_hi, sum_hi_lo}; // @[Atomics.scala:24:29] wire [127:0] _sum_T_32 = {sum_hi, sum_lo}; // @[Atomics.scala:24:29] wire [127:0] _sum_T_33 = _sum_T_32 & io_a_data_0; // @[Atomics.scala:8:7, :24:{29,44}] wire [128:0] _sum_T_34 = {1'h0, _sum_T_33} + {1'h0, inv_d}; // @[Atomics.scala:8:7, :10:14, :23:18, :24:{44,57}] wire [127:0] sum = _sum_T_34[127:0]; // @[Atomics.scala:24:57] wire _sign_a_T = io_a_data_0[0]; // @[Atomics.scala:8:7, :25:36] wire _logical_T = io_a_data_0[0]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_1 = io_a_data_0[1]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_1 = io_a_data_0[1]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_2 = io_a_data_0[2]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_2 = io_a_data_0[2]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_3 = io_a_data_0[3]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_3 = io_a_data_0[3]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_4 = io_a_data_0[4]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_4 = io_a_data_0[4]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_5 = io_a_data_0[5]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_5 = io_a_data_0[5]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_6 = io_a_data_0[6]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_6 = io_a_data_0[6]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_7 = io_a_data_0[7]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_7 = io_a_data_0[7]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_8 = io_a_data_0[8]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_8 = io_a_data_0[8]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_9 = io_a_data_0[9]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_9 = io_a_data_0[9]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_10 = io_a_data_0[10]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_10 = io_a_data_0[10]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_11 = io_a_data_0[11]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_11 = io_a_data_0[11]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_12 = io_a_data_0[12]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_12 = io_a_data_0[12]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_13 = io_a_data_0[13]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_13 = io_a_data_0[13]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_14 = io_a_data_0[14]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_14 = io_a_data_0[14]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_15 = io_a_data_0[15]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_15 = io_a_data_0[15]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_16 = io_a_data_0[16]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_16 = io_a_data_0[16]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_17 = io_a_data_0[17]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_17 = io_a_data_0[17]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_18 = io_a_data_0[18]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_18 = io_a_data_0[18]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_19 = io_a_data_0[19]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_19 = io_a_data_0[19]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_20 = io_a_data_0[20]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_20 = io_a_data_0[20]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_21 = io_a_data_0[21]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_21 = io_a_data_0[21]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_22 = io_a_data_0[22]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_22 = io_a_data_0[22]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_23 = io_a_data_0[23]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_23 = io_a_data_0[23]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_24 = io_a_data_0[24]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_24 = io_a_data_0[24]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_25 = io_a_data_0[25]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_25 = io_a_data_0[25]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_26 = io_a_data_0[26]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_26 = io_a_data_0[26]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_27 = io_a_data_0[27]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_27 = io_a_data_0[27]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_28 = io_a_data_0[28]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_28 = io_a_data_0[28]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_29 = io_a_data_0[29]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_29 = io_a_data_0[29]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_30 = io_a_data_0[30]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_30 = io_a_data_0[30]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_31 = io_a_data_0[31]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_31 = io_a_data_0[31]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_32 = io_a_data_0[32]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_32 = io_a_data_0[32]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_33 = io_a_data_0[33]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_33 = io_a_data_0[33]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_34 = io_a_data_0[34]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_34 = io_a_data_0[34]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_35 = io_a_data_0[35]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_35 = io_a_data_0[35]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_36 = io_a_data_0[36]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_36 = io_a_data_0[36]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_37 = io_a_data_0[37]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_37 = io_a_data_0[37]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_38 = io_a_data_0[38]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_38 = io_a_data_0[38]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_39 = io_a_data_0[39]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_39 = io_a_data_0[39]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_40 = io_a_data_0[40]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_40 = io_a_data_0[40]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_41 = io_a_data_0[41]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_41 = io_a_data_0[41]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_42 = io_a_data_0[42]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_42 = io_a_data_0[42]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_43 = io_a_data_0[43]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_43 = io_a_data_0[43]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_44 = io_a_data_0[44]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_44 = io_a_data_0[44]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_45 = io_a_data_0[45]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_45 = io_a_data_0[45]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_46 = io_a_data_0[46]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_46 = io_a_data_0[46]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_47 = io_a_data_0[47]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_47 = io_a_data_0[47]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_48 = io_a_data_0[48]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_48 = io_a_data_0[48]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_49 = io_a_data_0[49]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_49 = io_a_data_0[49]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_50 = io_a_data_0[50]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_50 = io_a_data_0[50]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_51 = io_a_data_0[51]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_51 = io_a_data_0[51]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_52 = io_a_data_0[52]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_52 = io_a_data_0[52]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_53 = io_a_data_0[53]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_53 = io_a_data_0[53]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_54 = io_a_data_0[54]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_54 = io_a_data_0[54]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_55 = io_a_data_0[55]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_55 = io_a_data_0[55]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_56 = io_a_data_0[56]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_56 = io_a_data_0[56]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_57 = io_a_data_0[57]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_57 = io_a_data_0[57]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_58 = io_a_data_0[58]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_58 = io_a_data_0[58]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_59 = io_a_data_0[59]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_59 = io_a_data_0[59]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_60 = io_a_data_0[60]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_60 = io_a_data_0[60]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_61 = io_a_data_0[61]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_61 = io_a_data_0[61]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_62 = io_a_data_0[62]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_62 = io_a_data_0[62]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_63 = io_a_data_0[63]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_63 = io_a_data_0[63]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_64 = io_a_data_0[64]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_64 = io_a_data_0[64]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_65 = io_a_data_0[65]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_65 = io_a_data_0[65]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_66 = io_a_data_0[66]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_66 = io_a_data_0[66]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_67 = io_a_data_0[67]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_67 = io_a_data_0[67]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_68 = io_a_data_0[68]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_68 = io_a_data_0[68]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_69 = io_a_data_0[69]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_69 = io_a_data_0[69]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_70 = io_a_data_0[70]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_70 = io_a_data_0[70]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_71 = io_a_data_0[71]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_71 = io_a_data_0[71]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_72 = io_a_data_0[72]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_72 = io_a_data_0[72]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_73 = io_a_data_0[73]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_73 = io_a_data_0[73]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_74 = io_a_data_0[74]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_74 = io_a_data_0[74]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_75 = io_a_data_0[75]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_75 = io_a_data_0[75]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_76 = io_a_data_0[76]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_76 = io_a_data_0[76]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_77 = io_a_data_0[77]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_77 = io_a_data_0[77]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_78 = io_a_data_0[78]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_78 = io_a_data_0[78]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_79 = io_a_data_0[79]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_79 = io_a_data_0[79]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_80 = io_a_data_0[80]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_80 = io_a_data_0[80]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_81 = io_a_data_0[81]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_81 = io_a_data_0[81]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_82 = io_a_data_0[82]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_82 = io_a_data_0[82]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_83 = io_a_data_0[83]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_83 = io_a_data_0[83]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_84 = io_a_data_0[84]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_84 = io_a_data_0[84]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_85 = io_a_data_0[85]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_85 = io_a_data_0[85]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_86 = io_a_data_0[86]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_86 = io_a_data_0[86]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_87 = io_a_data_0[87]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_87 = io_a_data_0[87]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_88 = io_a_data_0[88]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_88 = io_a_data_0[88]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_89 = io_a_data_0[89]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_89 = io_a_data_0[89]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_90 = io_a_data_0[90]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_90 = io_a_data_0[90]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_91 = io_a_data_0[91]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_91 = io_a_data_0[91]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_92 = io_a_data_0[92]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_92 = io_a_data_0[92]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_93 = io_a_data_0[93]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_93 = io_a_data_0[93]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_94 = io_a_data_0[94]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_94 = io_a_data_0[94]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_95 = io_a_data_0[95]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_95 = io_a_data_0[95]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_96 = io_a_data_0[96]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_96 = io_a_data_0[96]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_97 = io_a_data_0[97]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_97 = io_a_data_0[97]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_98 = io_a_data_0[98]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_98 = io_a_data_0[98]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_99 = io_a_data_0[99]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_99 = io_a_data_0[99]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_100 = io_a_data_0[100]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_100 = io_a_data_0[100]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_101 = io_a_data_0[101]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_101 = io_a_data_0[101]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_102 = io_a_data_0[102]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_102 = io_a_data_0[102]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_103 = io_a_data_0[103]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_103 = io_a_data_0[103]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_104 = io_a_data_0[104]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_104 = io_a_data_0[104]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_105 = io_a_data_0[105]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_105 = io_a_data_0[105]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_106 = io_a_data_0[106]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_106 = io_a_data_0[106]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_107 = io_a_data_0[107]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_107 = io_a_data_0[107]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_108 = io_a_data_0[108]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_108 = io_a_data_0[108]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_109 = io_a_data_0[109]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_109 = io_a_data_0[109]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_110 = io_a_data_0[110]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_110 = io_a_data_0[110]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_111 = io_a_data_0[111]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_111 = io_a_data_0[111]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_112 = io_a_data_0[112]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_112 = io_a_data_0[112]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_113 = io_a_data_0[113]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_113 = io_a_data_0[113]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_114 = io_a_data_0[114]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_114 = io_a_data_0[114]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_115 = io_a_data_0[115]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_115 = io_a_data_0[115]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_116 = io_a_data_0[116]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_116 = io_a_data_0[116]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_117 = io_a_data_0[117]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_117 = io_a_data_0[117]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_118 = io_a_data_0[118]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_118 = io_a_data_0[118]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_119 = io_a_data_0[119]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_119 = io_a_data_0[119]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_120 = io_a_data_0[120]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_120 = io_a_data_0[120]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_121 = io_a_data_0[121]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_121 = io_a_data_0[121]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_122 = io_a_data_0[122]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_122 = io_a_data_0[122]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_123 = io_a_data_0[123]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_123 = io_a_data_0[123]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_124 = io_a_data_0[124]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_124 = io_a_data_0[124]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_125 = io_a_data_0[125]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_125 = io_a_data_0[125]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_126 = io_a_data_0[126]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_126 = io_a_data_0[126]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_127 = io_a_data_0[127]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_127 = io_a_data_0[127]; // @[Atomics.scala:8:7, :25:36, :40:32] wire [1:0] sign_a_lo_lo_lo = {_sign_a_T_15, _sign_a_T_7}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_a_lo_lo_hi = {_sign_a_T_31, _sign_a_T_23}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_a_lo_lo = {sign_a_lo_lo_hi, sign_a_lo_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_a_lo_hi_lo = {_sign_a_T_47, _sign_a_T_39}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_a_lo_hi_hi = {_sign_a_T_63, _sign_a_T_55}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_a_lo_hi = {sign_a_lo_hi_hi, sign_a_lo_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_a_lo = {sign_a_lo_hi, sign_a_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_a_hi_lo_lo = {_sign_a_T_79, _sign_a_T_71}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_a_hi_lo_hi = {_sign_a_T_95, _sign_a_T_87}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_a_hi_lo = {sign_a_hi_lo_hi, sign_a_hi_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_a_hi_hi_lo = {_sign_a_T_111, _sign_a_T_103}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_a_hi_hi_hi = {_sign_a_T_127, _sign_a_T_119}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_a_hi_hi = {sign_a_hi_hi_hi, sign_a_hi_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_a_hi = {sign_a_hi_hi, sign_a_hi_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_a_T_128 = {sign_a_hi, sign_a_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_a_T_129 = _sign_a_T_128 & signBit; // @[Atomics.scala:22:27, :25:{33,83}] wire sign_a = \|_sign_a_T_129; // @[Atomics.scala:25:{83,94}] wire _sign_d_T = io_data_in_0[0]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_128 = io_data_in_0[0]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_1 = io_data_in_0[1]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_129 = io_data_in_0[1]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_2 = io_data_in_0[2]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_130 = io_data_in_0[2]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_3 = io_data_in_0[3]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_131 = io_data_in_0[3]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_4 = io_data_in_0[4]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_132 = io_data_in_0[4]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_5 = io_data_in_0[5]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_133 = io_data_in_0[5]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_6 = io_data_in_0[6]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_134 = io_data_in_0[6]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_7 = io_data_in_0[7]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_135 = io_data_in_0[7]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_8 = io_data_in_0[8]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_136 = io_data_in_0[8]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_9 = io_data_in_0[9]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_137 = io_data_in_0[9]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_10 = io_data_in_0[10]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_138 = io_data_in_0[10]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_11 = io_data_in_0[11]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_139 = io_data_in_0[11]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_12 = io_data_in_0[12]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_140 = io_data_in_0[12]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_13 = io_data_in_0[13]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_141 = io_data_in_0[13]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_14 = io_data_in_0[14]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_142 = io_data_in_0[14]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_15 = io_data_in_0[15]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_143 = io_data_in_0[15]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_16 = io_data_in_0[16]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_144 = io_data_in_0[16]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_17 = io_data_in_0[17]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_145 = io_data_in_0[17]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_18 = io_data_in_0[18]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_146 = io_data_in_0[18]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_19 = io_data_in_0[19]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_147 = io_data_in_0[19]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_20 = io_data_in_0[20]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_148 = io_data_in_0[20]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_21 = io_data_in_0[21]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_149 = io_data_in_0[21]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_22 = io_data_in_0[22]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_150 = io_data_in_0[22]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_23 = io_data_in_0[23]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_151 = io_data_in_0[23]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_24 = io_data_in_0[24]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_152 = io_data_in_0[24]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_25 = io_data_in_0[25]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_153 = io_data_in_0[25]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_26 = io_data_in_0[26]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_154 = io_data_in_0[26]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_27 = io_data_in_0[27]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_155 = io_data_in_0[27]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_28 = io_data_in_0[28]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_156 = io_data_in_0[28]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_29 = io_data_in_0[29]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_157 = io_data_in_0[29]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_30 = io_data_in_0[30]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_158 = io_data_in_0[30]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_31 = io_data_in_0[31]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_159 = io_data_in_0[31]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_32 = io_data_in_0[32]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_160 = io_data_in_0[32]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_33 = io_data_in_0[33]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_161 = io_data_in_0[33]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_34 = io_data_in_0[34]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_162 = io_data_in_0[34]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_35 = io_data_in_0[35]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_163 = io_data_in_0[35]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_36 = io_data_in_0[36]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_164 = io_data_in_0[36]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_37 = io_data_in_0[37]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_165 = io_data_in_0[37]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_38 = io_data_in_0[38]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_166 = io_data_in_0[38]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_39 = io_data_in_0[39]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_167 = io_data_in_0[39]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_40 = io_data_in_0[40]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_168 = io_data_in_0[40]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_41 = io_data_in_0[41]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_169 = io_data_in_0[41]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_42 = io_data_in_0[42]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_170 = io_data_in_0[42]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_43 = io_data_in_0[43]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_171 = io_data_in_0[43]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_44 = io_data_in_0[44]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_172 = io_data_in_0[44]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_45 = io_data_in_0[45]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_173 = io_data_in_0[45]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_46 = io_data_in_0[46]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_174 = io_data_in_0[46]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_47 = io_data_in_0[47]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_175 = io_data_in_0[47]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_48 = io_data_in_0[48]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_176 = io_data_in_0[48]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_49 = io_data_in_0[49]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_177 = io_data_in_0[49]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_50 = io_data_in_0[50]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_178 = io_data_in_0[50]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_51 = io_data_in_0[51]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_179 = io_data_in_0[51]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_52 = io_data_in_0[52]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_180 = io_data_in_0[52]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_53 = io_data_in_0[53]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_181 = io_data_in_0[53]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_54 = io_data_in_0[54]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_182 = io_data_in_0[54]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_55 = io_data_in_0[55]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_183 = io_data_in_0[55]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_56 = io_data_in_0[56]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_184 = io_data_in_0[56]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_57 = io_data_in_0[57]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_185 = io_data_in_0[57]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_58 = io_data_in_0[58]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_186 = io_data_in_0[58]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_59 = io_data_in_0[59]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_187 = io_data_in_0[59]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_60 = io_data_in_0[60]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_188 = io_data_in_0[60]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_61 = io_data_in_0[61]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_189 = io_data_in_0[61]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_62 = io_data_in_0[62]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_190 = io_data_in_0[62]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_63 = io_data_in_0[63]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_191 = io_data_in_0[63]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_64 = io_data_in_0[64]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_192 = io_data_in_0[64]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_65 = io_data_in_0[65]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_193 = io_data_in_0[65]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_66 = io_data_in_0[66]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_194 = io_data_in_0[66]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_67 = io_data_in_0[67]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_195 = io_data_in_0[67]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_68 = io_data_in_0[68]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_196 = io_data_in_0[68]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_69 = io_data_in_0[69]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_197 = io_data_in_0[69]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_70 = io_data_in_0[70]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_198 = io_data_in_0[70]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_71 = io_data_in_0[71]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_199 = io_data_in_0[71]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_72 = io_data_in_0[72]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_200 = io_data_in_0[72]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_73 = io_data_in_0[73]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_201 = io_data_in_0[73]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_74 = io_data_in_0[74]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_202 = io_data_in_0[74]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_75 = io_data_in_0[75]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_203 = io_data_in_0[75]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_76 = io_data_in_0[76]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_204 = io_data_in_0[76]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_77 = io_data_in_0[77]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_205 = io_data_in_0[77]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_78 = io_data_in_0[78]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_206 = io_data_in_0[78]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_79 = io_data_in_0[79]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_207 = io_data_in_0[79]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_80 = io_data_in_0[80]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_208 = io_data_in_0[80]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_81 = io_data_in_0[81]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_209 = io_data_in_0[81]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_82 = io_data_in_0[82]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_210 = io_data_in_0[82]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_83 = io_data_in_0[83]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_211 = io_data_in_0[83]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_84 = io_data_in_0[84]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_212 = io_data_in_0[84]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_85 = io_data_in_0[85]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_213 = io_data_in_0[85]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_86 = io_data_in_0[86]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_214 = io_data_in_0[86]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_87 = io_data_in_0[87]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_215 = io_data_in_0[87]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_88 = io_data_in_0[88]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_216 = io_data_in_0[88]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_89 = io_data_in_0[89]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_217 = io_data_in_0[89]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_90 = io_data_in_0[90]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_218 = io_data_in_0[90]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_91 = io_data_in_0[91]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_219 = io_data_in_0[91]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_92 = io_data_in_0[92]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_220 = io_data_in_0[92]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_93 = io_data_in_0[93]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_221 = io_data_in_0[93]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_94 = io_data_in_0[94]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_222 = io_data_in_0[94]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_95 = io_data_in_0[95]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_223 = io_data_in_0[95]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_96 = io_data_in_0[96]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_224 = io_data_in_0[96]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_97 = io_data_in_0[97]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_225 = io_data_in_0[97]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_98 = io_data_in_0[98]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_226 = io_data_in_0[98]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_99 = io_data_in_0[99]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_227 = io_data_in_0[99]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_100 = io_data_in_0[100]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_228 = io_data_in_0[100]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_101 = io_data_in_0[101]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_229 = io_data_in_0[101]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_102 = io_data_in_0[102]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_230 = io_data_in_0[102]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_103 = io_data_in_0[103]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_231 = io_data_in_0[103]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_104 = io_data_in_0[104]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_232 = io_data_in_0[104]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_105 = io_data_in_0[105]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_233 = io_data_in_0[105]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_106 = io_data_in_0[106]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_234 = io_data_in_0[106]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_107 = io_data_in_0[107]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_235 = io_data_in_0[107]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_108 = io_data_in_0[108]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_236 = io_data_in_0[108]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_109 = io_data_in_0[109]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_237 = io_data_in_0[109]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_110 = io_data_in_0[110]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_238 = io_data_in_0[110]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_111 = io_data_in_0[111]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_239 = io_data_in_0[111]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_112 = io_data_in_0[112]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_240 = io_data_in_0[112]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_113 = io_data_in_0[113]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_241 = io_data_in_0[113]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_114 = io_data_in_0[114]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_242 = io_data_in_0[114]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_115 = io_data_in_0[115]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_243 = io_data_in_0[115]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_116 = io_data_in_0[116]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_244 = io_data_in_0[116]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_117 = io_data_in_0[117]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_245 = io_data_in_0[117]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_118 = io_data_in_0[118]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_246 = io_data_in_0[118]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_119 = io_data_in_0[119]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_247 = io_data_in_0[119]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_120 = io_data_in_0[120]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_248 = io_data_in_0[120]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_121 = io_data_in_0[121]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_249 = io_data_in_0[121]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_122 = io_data_in_0[122]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_250 = io_data_in_0[122]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_123 = io_data_in_0[123]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_251 = io_data_in_0[123]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_124 = io_data_in_0[124]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_252 = io_data_in_0[124]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_125 = io_data_in_0[125]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_253 = io_data_in_0[125]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_126 = io_data_in_0[126]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_254 = io_data_in_0[126]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_127 = io_data_in_0[127]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_255 = io_data_in_0[127]; // @[Atomics.scala:8:7, :25:36, :40:55] wire [1:0] sign_d_lo_lo_lo = {_sign_d_T_15, _sign_d_T_7}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_d_lo_lo_hi = {_sign_d_T_31, _sign_d_T_23}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_d_lo_lo = {sign_d_lo_lo_hi, sign_d_lo_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_d_lo_hi_lo = {_sign_d_T_47, _sign_d_T_39}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_d_lo_hi_hi = {_sign_d_T_63, _sign_d_T_55}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_d_lo_hi = {sign_d_lo_hi_hi, sign_d_lo_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_d_lo = {sign_d_lo_hi, sign_d_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_d_hi_lo_lo = {_sign_d_T_79, _sign_d_T_71}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_d_hi_lo_hi = {_sign_d_T_95, _sign_d_T_87}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_d_hi_lo = {sign_d_hi_lo_hi, sign_d_hi_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_d_hi_hi_lo = {_sign_d_T_111, _sign_d_T_103}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_d_hi_hi_hi = {_sign_d_T_127, _sign_d_T_119}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_d_hi_hi = {sign_d_hi_hi_hi, sign_d_hi_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_d_hi = {sign_d_hi_hi, sign_d_hi_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_d_T_128 = {sign_d_hi, sign_d_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_d_T_129 = _sign_d_T_128 & signBit; // @[Atomics.scala:22:27, :25:{33,83}] wire sign_d = \|_sign_d_T_129; // @[Atomics.scala:25:{83,94}] wire _sign_s_T = sum[0]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_1 = sum[1]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_2 = sum[2]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_3 = sum[3]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_4 = sum[4]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_5 = sum[5]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_6 = sum[6]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_7 = sum[7]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_8 = sum[8]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_9 = sum[9]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_10 = sum[10]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_11 = sum[11]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_12 = sum[12]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_13 = sum[13]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_14 = sum[14]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_15 = sum[15]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_16 = sum[16]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_17 = sum[17]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_18 = sum[18]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_19 = sum[19]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_20 = sum[20]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_21 = sum[21]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_22 = sum[22]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_23 = sum[23]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_24 = sum[24]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_25 = sum[25]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_26 = sum[26]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_27 = sum[27]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_28 = sum[28]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_29 = sum[29]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_30 = sum[30]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_31 = sum[31]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_32 = sum[32]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_33 = sum[33]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_34 = sum[34]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_35 = sum[35]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_36 = sum[36]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_37 = sum[37]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_38 = sum[38]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_39 = sum[39]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_40 = sum[40]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_41 = sum[41]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_42 = sum[42]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_43 = sum[43]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_44 = sum[44]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_45 = sum[45]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_46 = sum[46]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_47 = sum[47]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_48 = sum[48]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_49 = sum[49]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_50 = sum[50]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_51 = sum[51]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_52 = sum[52]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_53 = sum[53]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_54 = sum[54]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_55 = sum[55]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_56 = sum[56]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_57 = sum[57]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_58 = sum[58]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_59 = sum[59]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_60 = sum[60]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_61 = sum[61]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_62 = sum[62]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_63 = sum[63]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_64 = sum[64]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_65 = sum[65]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_66 = sum[66]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_67 = sum[67]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_68 = sum[68]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_69 = sum[69]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_70 = sum[70]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_71 = sum[71]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_72 = sum[72]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_73 = sum[73]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_74 = sum[74]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_75 = sum[75]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_76 = sum[76]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_77 = sum[77]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_78 = sum[78]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_79 = sum[79]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_80 = sum[80]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_81 = sum[81]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_82 = sum[82]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_83 = sum[83]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_84 = sum[84]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_85 = sum[85]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_86 = sum[86]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_87 = sum[87]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_88 = sum[88]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_89 = sum[89]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_90 = sum[90]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_91 = sum[91]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_92 = sum[92]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_93 = sum[93]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_94 = sum[94]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_95 = sum[95]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_96 = sum[96]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_97 = sum[97]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_98 = sum[98]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_99 = sum[99]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_100 = sum[100]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_101 = sum[101]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_102 = sum[102]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_103 = sum[103]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_104 = sum[104]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_105 = sum[105]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_106 = sum[106]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_107 = sum[107]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_108 = sum[108]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_109 = sum[109]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_110 = sum[110]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_111 = sum[111]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_112 = sum[112]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_113 = sum[113]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_114 = sum[114]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_115 = sum[115]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_116 = sum[116]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_117 = sum[117]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_118 = sum[118]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_119 = sum[119]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_120 = sum[120]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_121 = sum[121]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_122 = sum[122]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_123 = sum[123]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_124 = sum[124]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_125 = sum[125]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_126 = sum[126]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_127 = sum[127]; // @[Atomics.scala:24:57, :25:36] wire [1:0] sign_s_lo_lo_lo = {_sign_s_T_15, _sign_s_T_7}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_s_lo_lo_hi = {_sign_s_T_31, _sign_s_T_23}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_s_lo_lo = {sign_s_lo_lo_hi, sign_s_lo_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_s_lo_hi_lo = {_sign_s_T_47, _sign_s_T_39}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_s_lo_hi_hi = {_sign_s_T_63, _sign_s_T_55}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_s_lo_hi = {sign_s_lo_hi_hi, sign_s_lo_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_s_lo = {sign_s_lo_hi, sign_s_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_s_hi_lo_lo = {_sign_s_T_79, _sign_s_T_71}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_s_hi_lo_hi = {_sign_s_T_95, _sign_s_T_87}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_s_hi_lo = {sign_s_hi_lo_hi, sign_s_hi_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_s_hi_hi_lo = {_sign_s_T_111, _sign_s_T_103}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_s_hi_hi_hi = {_sign_s_T_127, _sign_s_T_119}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_s_hi_hi = {sign_s_hi_hi_hi, sign_s_hi_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_s_hi = {sign_s_hi_hi, sign_s_hi_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_s_T_128 = {sign_s_hi, sign_s_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_s_T_129 = _sign_s_T_128 & signBit; // @[Atomics.scala:22:27, :25:{33,83}] wire sign_s = \|_sign_s_T_129; // @[Atomics.scala:25:{83,94}] wire a_bigger_uneq = unsigned_0 == sign_a; // @[Atomics.scala:19:28, :25:94, :29:32] wire _a_bigger_T = sign_a == sign_d; // @[Atomics.scala:25:94, :30:29] wire _a_bigger_T_1 = ~sign_s; // @[Atomics.scala:25:94, :30:41] wire a_bigger = _a_bigger_T ? _a_bigger_T_1 : a_bigger_uneq; // @[Atomics.scala:29:32, :30:{21,29,41}] wire pick_a = take_max == a_bigger; // @[Atomics.scala:20:28, :30:21, :31:25] wire _select_T = pick_a; // @[Atomics.scala:31:25, :48:24] wire [1:0] _lut_T = io_a_param_0[1:0]; // @[Atomics.scala:8:7, :39:15] wire [1:0] _logical_T_256 = {_logical_T, _logical_T_128}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_257 = _GEN[_lut_T] >> _logical_T_256; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_258 = _logical_T_257[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_259 = {_logical_T_1, _logical_T_129}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_260 = _GEN[_lut_T] >> _logical_T_259; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_261 = _logical_T_260[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_262 = {_logical_T_2, _logical_T_130}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_263 = _GEN[_lut_T] >> _logical_T_262; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_264 = _logical_T_263[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_265 = {_logical_T_3, _logical_T_131}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_266 = _GEN[_lut_T] >> _logical_T_265; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_267 = _logical_T_266[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_268 = {_logical_T_4, _logical_T_132}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_269 = _GEN[_lut_T] >> _logical_T_268; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_270 = _logical_T_269[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_271 = {_logical_T_5, _logical_T_133}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_272 = _GEN[_lut_T] >> _logical_T_271; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_273 = _logical_T_272[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_274 = {_logical_T_6, _logical_T_134}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_275 = _GEN[_lut_T] >> _logical_T_274; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_276 = _logical_T_275[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_277 = {_logical_T_7, _logical_T_135}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_278 = _GEN[_lut_T] >> _logical_T_277; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_279 = _logical_T_278[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_280 = {_logical_T_8, _logical_T_136}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_281 = _GEN[_lut_T] >> _logical_T_280; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_282 = _logical_T_281[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_283 = {_logical_T_9, _logical_T_137}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_284 = _GEN[_lut_T] >> _logical_T_283; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_285 = _logical_T_284[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_286 = {_logical_T_10, _logical_T_138}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_287 = _GEN[_lut_T] >> _logical_T_286; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_288 = _logical_T_287[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_289 = {_logical_T_11, _logical_T_139}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_290 = _GEN[_lut_T] >> _logical_T_289; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_291 = _logical_T_290[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_292 = {_logical_T_12, _logical_T_140}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_293 = _GEN[_lut_T] >> _logical_T_292; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_294 = _logical_T_293[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_295 = {_logical_T_13, _logical_T_141}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_296 = _GEN[_lut_T] >> _logical_T_295; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_297 = _logical_T_296[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_298 = {_logical_T_14, _logical_T_142}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_299 = _GEN[_lut_T] >> _logical_T_298; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_300 = _logical_T_299[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_301 = {_logical_T_15, _logical_T_143}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_302 = _GEN[_lut_T] >> _logical_T_301; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_303 = _logical_T_302[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_304 = {_logical_T_16, _logical_T_144}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_305 = _GEN[_lut_T] >> _logical_T_304; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_306 = _logical_T_305[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_307 = {_logical_T_17, _logical_T_145}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_308 = _GEN[_lut_T] >> _logical_T_307; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_309 = _logical_T_308[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_310 = {_logical_T_18, _logical_T_146}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_311 = _GEN[_lut_T] >> _logical_T_310; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_312 = _logical_T_311[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_313 = {_logical_T_19, _logical_T_147}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_314 = _GEN[_lut_T] >> _logical_T_313; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_315 = _logical_T_314[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_316 = {_logical_T_20, _logical_T_148}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_317 = _GEN[_lut_T] >> _logical_T_316; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_318 = _logical_T_317[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_319 = {_logical_T_21, _logical_T_149}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_320 = _GEN[_lut_T] >> _logical_T_319; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_321 = _logical_T_320[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_322 = {_logical_T_22, _logical_T_150}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_323 = _GEN[_lut_T] >> _logical_T_322; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_324 = _logical_T_323[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_325 = {_logical_T_23, _logical_T_151}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_326 = _GEN[_lut_T] >> _logical_T_325; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_327 = _logical_T_326[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_328 = {_logical_T_24, _logical_T_152}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_329 = _GEN[_lut_T] >> _logical_T_328; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_330 = _logical_T_329[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_331 = {_logical_T_25, _logical_T_153}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_332 = _GEN[_lut_T] >> _logical_T_331; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_333 = _logical_T_332[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_334 = {_logical_T_26, _logical_T_154}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_335 = _GEN[_lut_T] >> _logical_T_334; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_336 = _logical_T_335[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_337 = {_logical_T_27, _logical_T_155}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_338 = _GEN[_lut_T] >> _logical_T_337; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_339 = _logical_T_338[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_340 = {_logical_T_28, _logical_T_156}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_341 = _GEN[_lut_T] >> _logical_T_340; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_342 = _logical_T_341[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_343 = {_logical_T_29, _logical_T_157}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_344 = _GEN[_lut_T] >> _logical_T_343; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_345 = _logical_T_344[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_346 = {_logical_T_30, _logical_T_158}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_347 = _GEN[_lut_T] >> _logical_T_346; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_348 = _logical_T_347[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_349 = {_logical_T_31, _logical_T_159}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_350 = _GEN[_lut_T] >> _logical_T_349; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_351 = _logical_T_350[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_352 = {_logical_T_32, _logical_T_160}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_353 = _GEN[_lut_T] >> _logical_T_352; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_354 = _logical_T_353[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_355 = {_logical_T_33, _logical_T_161}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_356 = _GEN[_lut_T] >> _logical_T_355; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_357 = _logical_T_356[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_358 = {_logical_T_34, _logical_T_162}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_359 = _GEN[_lut_T] >> _logical_T_358; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_360 = _logical_T_359[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_361 = {_logical_T_35, _logical_T_163}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_362 = _GEN[_lut_T] >> _logical_T_361; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_363 = _logical_T_362[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_364 = {_logical_T_36, _logical_T_164}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_365 = _GEN[_lut_T] >> _logical_T_364; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_366 = _logical_T_365[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_367 = {_logical_T_37, _logical_T_165}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_368 = _GEN[_lut_T] >> _logical_T_367; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_369 = _logical_T_368[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_370 = {_logical_T_38, _logical_T_166}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_371 = _GEN[_lut_T] >> _logical_T_370; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_372 = _logical_T_371[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_373 = {_logical_T_39, _logical_T_167}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_374 = _GEN[_lut_T] >> _logical_T_373; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_375 = _logical_T_374[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_376 = {_logical_T_40, _logical_T_168}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_377 = _GEN[_lut_T] >> _logical_T_376; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_378 = _logical_T_377[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_379 = {_logical_T_41, _logical_T_169}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_380 = _GEN[_lut_T] >> _logical_T_379; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_381 = _logical_T_380[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_382 = {_logical_T_42, _logical_T_170}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_383 = _GEN[_lut_T] >> _logical_T_382; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_384 = _logical_T_383[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_385 = {_logical_T_43, _logical_T_171}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_386 = _GEN[_lut_T] >> _logical_T_385; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_387 = _logical_T_386[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_388 = {_logical_T_44, _logical_T_172}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_389 = _GEN[_lut_T] >> _logical_T_388; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_390 = _logical_T_389[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_391 = {_logical_T_45, _logical_T_173}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_392 = _GEN[_lut_T] >> _logical_T_391; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_393 = _logical_T_392[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_394 = {_logical_T_46, _logical_T_174}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_395 = _GEN[_lut_T] >> _logical_T_394; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_396 = _logical_T_395[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_397 = {_logical_T_47, _logical_T_175}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_398 = _GEN[_lut_T] >> _logical_T_397; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_399 = _logical_T_398[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_400 = {_logical_T_48, _logical_T_176}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_401 = _GEN[_lut_T] >> _logical_T_400; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_402 = _logical_T_401[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_403 = {_logical_T_49, _logical_T_177}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_404 = _GEN[_lut_T] >> _logical_T_403; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_405 = _logical_T_404[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_406 = {_logical_T_50, _logical_T_178}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_407 = _GEN[_lut_T] >> _logical_T_406; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_408 = _logical_T_407[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_409 = {_logical_T_51, _logical_T_179}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_410 = _GEN[_lut_T] >> _logical_T_409; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_411 = _logical_T_410[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_412 = {_logical_T_52, _logical_T_180}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_413 = _GEN[_lut_T] >> _logical_T_412; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_414 = _logical_T_413[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_415 = {_logical_T_53, _logical_T_181}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_416 = _GEN[_lut_T] >> _logical_T_415; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_417 = _logical_T_416[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_418 = {_logical_T_54, _logical_T_182}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_419 = _GEN[_lut_T] >> _logical_T_418; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_420 = _logical_T_419[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_421 = {_logical_T_55, _logical_T_183}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_422 = _GEN[_lut_T] >> _logical_T_421; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_423 = _logical_T_422[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_424 = {_logical_T_56, _logical_T_184}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_425 = _GEN[_lut_T] >> _logical_T_424; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_426 = _logical_T_425[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_427 = {_logical_T_57, _logical_T_185}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_428 = _GEN[_lut_T] >> _logical_T_427; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_429 = _logical_T_428[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_430 = {_logical_T_58, _logical_T_186}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_431 = _GEN[_lut_T] >> _logical_T_430; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_432 = _logical_T_431[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_433 = {_logical_T_59, _logical_T_187}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_434 = _GEN[_lut_T] >> _logical_T_433; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_435 = _logical_T_434[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_436 = {_logical_T_60, _logical_T_188}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_437 = _GEN[_lut_T] >> _logical_T_436; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_438 = _logical_T_437[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_439 = {_logical_T_61, _logical_T_189}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_440 = _GEN[_lut_T] >> _logical_T_439; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_441 = _logical_T_440[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_442 = {_logical_T_62, _logical_T_190}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_443 = _GEN[_lut_T] >> _logical_T_442; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_444 = _logical_T_443[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_445 = {_logical_T_63, _logical_T_191}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_446 = _GEN[_lut_T] >> _logical_T_445; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_447 = _logical_T_446[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_448 = {_logical_T_64, _logical_T_192}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_449 = _GEN[_lut_T] >> _logical_T_448; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_450 = _logical_T_449[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_451 = {_logical_T_65, _logical_T_193}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_452 = _GEN[_lut_T] >> _logical_T_451; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_453 = _logical_T_452[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_454 = {_logical_T_66, _logical_T_194}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_455 = _GEN[_lut_T] >> _logical_T_454; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_456 = _logical_T_455[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_457 = {_logical_T_67, _logical_T_195}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_458 = _GEN[_lut_T] >> _logical_T_457; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_459 = _logical_T_458[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_460 = {_logical_T_68, _logical_T_196}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_461 = _GEN[_lut_T] >> _logical_T_460; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_462 = _logical_T_461[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_463 = {_logical_T_69, _logical_T_197}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_464 = _GEN[_lut_T] >> _logical_T_463; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_465 = _logical_T_464[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_466 = {_logical_T_70, _logical_T_198}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_467 = _GEN[_lut_T] >> _logical_T_466; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_468 = _logical_T_467[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_469 = {_logical_T_71, _logical_T_199}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_470 = _GEN[_lut_T] >> _logical_T_469; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_471 = _logical_T_470[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_472 = {_logical_T_72, _logical_T_200}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_473 = _GEN[_lut_T] >> _logical_T_472; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_474 = _logical_T_473[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_475 = {_logical_T_73, _logical_T_201}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_476 = _GEN[_lut_T] >> _logical_T_475; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_477 = _logical_T_476[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_478 = {_logical_T_74, _logical_T_202}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_479 = _GEN[_lut_T] >> _logical_T_478; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_480 = _logical_T_479[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_481 = {_logical_T_75, _logical_T_203}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_482 = _GEN[_lut_T] >> _logical_T_481; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_483 = _logical_T_482[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_484 = {_logical_T_76, _logical_T_204}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_485 = _GEN[_lut_T] >> _logical_T_484; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_486 = _logical_T_485[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_487 = {_logical_T_77, _logical_T_205}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_488 = _GEN[_lut_T] >> _logical_T_487; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_489 = _logical_T_488[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_490 = {_logical_T_78, _logical_T_206}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_491 = _GEN[_lut_T] >> _logical_T_490; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_492 = _logical_T_491[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_493 = {_logical_T_79, _logical_T_207}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_494 = _GEN[_lut_T] >> _logical_T_493; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_495 = _logical_T_494[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_496 = {_logical_T_80, _logical_T_208}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_497 = _GEN[_lut_T] >> _logical_T_496; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_498 = _logical_T_497[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_499 = {_logical_T_81, _logical_T_209}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_500 = _GEN[_lut_T] >> _logical_T_499; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_501 = _logical_T_500[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_502 = {_logical_T_82, _logical_T_210}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_503 = _GEN[_lut_T] >> _logical_T_502; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_504 = _logical_T_503[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_505 = {_logical_T_83, _logical_T_211}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_506 = _GEN[_lut_T] >> _logical_T_505; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_507 = _logical_T_506[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_508 = {_logical_T_84, _logical_T_212}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_509 = _GEN[_lut_T] >> _logical_T_508; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_510 = _logical_T_509[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_511 = {_logical_T_85, _logical_T_213}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_512 = _GEN[_lut_T] >> _logical_T_511; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_513 = _logical_T_512[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_514 = {_logical_T_86, _logical_T_214}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_515 = _GEN[_lut_T] >> _logical_T_514; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_516 = _logical_T_515[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_517 = {_logical_T_87, _logical_T_215}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_518 = _GEN[_lut_T] >> _logical_T_517; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_519 = _logical_T_518[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_520 = {_logical_T_88, _logical_T_216}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_521 = _GEN[_lut_T] >> _logical_T_520; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_522 = _logical_T_521[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_523 = {_logical_T_89, _logical_T_217}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_524 = _GEN[_lut_T] >> _logical_T_523; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_525 = _logical_T_524[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_526 = {_logical_T_90, _logical_T_218}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_527 = _GEN[_lut_T] >> _logical_T_526; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_528 = _logical_T_527[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_529 = {_logical_T_91, _logical_T_219}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_530 = _GEN[_lut_T] >> _logical_T_529; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_531 = _logical_T_530[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_532 = {_logical_T_92, _logical_T_220}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_533 = _GEN[_lut_T] >> _logical_T_532; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_534 = _logical_T_533[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_535 = {_logical_T_93, _logical_T_221}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_536 = _GEN[_lut_T] >> _logical_T_535; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_537 = _logical_T_536[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_538 = {_logical_T_94, _logical_T_222}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_539 = _GEN[_lut_T] >> _logical_T_538; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_540 = _logical_T_539[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_541 = {_logical_T_95, _logical_T_223}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_542 = _GEN[_lut_T] >> _logical_T_541; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_543 = _logical_T_542[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_544 = {_logical_T_96, _logical_T_224}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_545 = _GEN[_lut_T] >> _logical_T_544; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_546 = _logical_T_545[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_547 = {_logical_T_97, _logical_T_225}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_548 = _GEN[_lut_T] >> _logical_T_547; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_549 = _logical_T_548[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_550 = {_logical_T_98, _logical_T_226}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_551 = _GEN[_lut_T] >> _logical_T_550; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_552 = _logical_T_551[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_553 = {_logical_T_99, _logical_T_227}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_554 = _GEN[_lut_T] >> _logical_T_553; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_555 = _logical_T_554[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_556 = {_logical_T_100, _logical_T_228}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_557 = _GEN[_lut_T] >> _logical_T_556; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_558 = _logical_T_557[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_559 = {_logical_T_101, _logical_T_229}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_560 = _GEN[_lut_T] >> _logical_T_559; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_561 = _logical_T_560[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_562 = {_logical_T_102, _logical_T_230}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_563 = _GEN[_lut_T] >> _logical_T_562; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_564 = _logical_T_563[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_565 = {_logical_T_103, _logical_T_231}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_566 = _GEN[_lut_T] >> _logical_T_565; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_567 = _logical_T_566[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_568 = {_logical_T_104, _logical_T_232}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_569 = _GEN[_lut_T] >> _logical_T_568; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_570 = _logical_T_569[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_571 = {_logical_T_105, _logical_T_233}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_572 = _GEN[_lut_T] >> _logical_T_571; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_573 = _logical_T_572[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_574 = {_logical_T_106, _logical_T_234}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_575 = _GEN[_lut_T] >> _logical_T_574; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_576 = _logical_T_575[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_577 = {_logical_T_107, _logical_T_235}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_578 = _GEN[_lut_T] >> _logical_T_577; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_579 = _logical_T_578[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_580 = {_logical_T_108, _logical_T_236}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_581 = _GEN[_lut_T] >> _logical_T_580; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_582 = _logical_T_581[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_583 = {_logical_T_109, _logical_T_237}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_584 = _GEN[_lut_T] >> _logical_T_583; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_585 = _logical_T_584[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_586 = {_logical_T_110, _logical_T_238}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_587 = _GEN[_lut_T] >> _logical_T_586; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_588 = _logical_T_587[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_589 = {_logical_T_111, _logical_T_239}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_590 = _GEN[_lut_T] >> _logical_T_589; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_591 = _logical_T_590[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_592 = {_logical_T_112, _logical_T_240}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_593 = _GEN[_lut_T] >> _logical_T_592; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_594 = _logical_T_593[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_595 = {_logical_T_113, _logical_T_241}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_596 = _GEN[_lut_T] >> _logical_T_595; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_597 = _logical_T_596[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_598 = {_logical_T_114, _logical_T_242}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_599 = _GEN[_lut_T] >> _logical_T_598; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_600 = _logical_T_599[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_601 = {_logical_T_115, _logical_T_243}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_602 = _GEN[_lut_T] >> _logical_T_601; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_603 = _logical_T_602[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_604 = {_logical_T_116, _logical_T_244}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_605 = _GEN[_lut_T] >> _logical_T_604; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_606 = _logical_T_605[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_607 = {_logical_T_117, _logical_T_245}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_608 = _GEN[_lut_T] >> _logical_T_607; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_609 = _logical_T_608[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_610 = {_logical_T_118, _logical_T_246}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_611 = _GEN[_lut_T] >> _logical_T_610; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_612 = _logical_T_611[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_613 = {_logical_T_119, _logical_T_247}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_614 = _GEN[_lut_T] >> _logical_T_613; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_615 = _logical_T_614[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_616 = {_logical_T_120, _logical_T_248}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_617 = _GEN[_lut_T] >> _logical_T_616; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_618 = _logical_T_617[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_619 = {_logical_T_121, _logical_T_249}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_620 = _GEN[_lut_T] >> _logical_T_619; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_621 = _logical_T_620[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_622 = {_logical_T_122, _logical_T_250}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_623 = _GEN[_lut_T] >> _logical_T_622; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_624 = _logical_T_623[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_625 = {_logical_T_123, _logical_T_251}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_626 = _GEN[_lut_T] >> _logical_T_625; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_627 = _logical_T_626[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_628 = {_logical_T_124, _logical_T_252}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_629 = _GEN[_lut_T] >> _logical_T_628; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_630 = _logical_T_629[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_631 = {_logical_T_125, _logical_T_253}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_632 = _GEN[_lut_T] >> _logical_T_631; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_633 = _logical_T_632[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_634 = {_logical_T_126, _logical_T_254}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_635 = _GEN[_lut_T] >> _logical_T_634; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_636 = _logical_T_635[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_637 = {_logical_T_127, _logical_T_255}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_638 = _GEN[_lut_T] >> _logical_T_637; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_639 = _logical_T_638[0]; // @[Atomics.scala:41:8] wire [1:0] logical_lo_lo_lo_lo_lo_lo = {_logical_T_261, _logical_T_258}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_lo_lo_lo_hi = {_logical_T_267, _logical_T_264}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_lo_lo_lo = {logical_lo_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_lo_lo_hi_lo = {_logical_T_273, _logical_T_270}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_lo_lo_hi_hi = {_logical_T_279, _logical_T_276}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_lo_lo_hi = {logical_lo_lo_lo_lo_hi_hi, logical_lo_lo_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_lo_lo_lo = {logical_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_lo_hi_lo_lo = {_logical_T_285, _logical_T_282}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_lo_hi_lo_hi = {_logical_T_291, _logical_T_288}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_lo_hi_lo = {logical_lo_lo_lo_hi_lo_hi, logical_lo_lo_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_lo_hi_hi_lo = {_logical_T_297, _logical_T_294}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_lo_hi_hi_hi = {_logical_T_303, _logical_T_300}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_lo_hi_hi = {logical_lo_lo_lo_hi_hi_hi, logical_lo_lo_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_lo_lo_hi = {logical_lo_lo_lo_hi_hi, logical_lo_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_lo_lo_lo = {logical_lo_lo_lo_hi, logical_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_hi_lo_lo_lo = {_logical_T_309, _logical_T_306}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_hi_lo_lo_hi = {_logical_T_315, _logical_T_312}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_hi_lo_lo = {logical_lo_lo_hi_lo_lo_hi, logical_lo_lo_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_hi_lo_hi_lo = {_logical_T_321, _logical_T_318}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_hi_lo_hi_hi = {_logical_T_327, _logical_T_324}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_hi_lo_hi = {logical_lo_lo_hi_lo_hi_hi, logical_lo_lo_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_lo_hi_lo = {logical_lo_lo_hi_lo_hi, logical_lo_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_hi_hi_lo_lo = {_logical_T_333, _logical_T_330}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_hi_hi_lo_hi = {_logical_T_339, _logical_T_336}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_hi_hi_lo = {logical_lo_lo_hi_hi_lo_hi, logical_lo_lo_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_hi_hi_hi_lo = {_logical_T_345, _logical_T_342}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_hi_hi_hi_hi = {_logical_T_351, _logical_T_348}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_hi_hi_hi = {logical_lo_lo_hi_hi_hi_hi, logical_lo_lo_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_lo_hi_hi = {logical_lo_lo_hi_hi_hi, logical_lo_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_lo_lo_hi = {logical_lo_lo_hi_hi, logical_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [31:0] logical_lo_lo = {logical_lo_lo_hi, logical_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_lo_lo_lo_lo = {_logical_T_357, _logical_T_354}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_lo_lo_lo_hi = {_logical_T_363, _logical_T_360}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_lo_lo_lo = {logical_lo_hi_lo_lo_lo_hi, logical_lo_hi_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_lo_lo_hi_lo = {_logical_T_369, _logical_T_366}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_lo_lo_hi_hi = {_logical_T_375, _logical_T_372}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_lo_lo_hi = {logical_lo_hi_lo_lo_hi_hi, logical_lo_hi_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_hi_lo_lo = {logical_lo_hi_lo_lo_hi, logical_lo_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_lo_hi_lo_lo = {_logical_T_381, _logical_T_378}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_lo_hi_lo_hi = {_logical_T_387, _logical_T_384}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_lo_hi_lo = {logical_lo_hi_lo_hi_lo_hi, logical_lo_hi_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_lo_hi_hi_lo = {_logical_T_393, _logical_T_390}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_lo_hi_hi_hi = {_logical_T_399, _logical_T_396}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_lo_hi_hi = {logical_lo_hi_lo_hi_hi_hi, logical_lo_hi_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_hi_lo_hi = {logical_lo_hi_lo_hi_hi, logical_lo_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_lo_hi_lo = {logical_lo_hi_lo_hi, logical_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_hi_lo_lo_lo = {_logical_T_405, _logical_T_402}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_hi_lo_lo_hi = {_logical_T_411, _logical_T_408}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_hi_lo_lo = {logical_lo_hi_hi_lo_lo_hi, logical_lo_hi_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_hi_lo_hi_lo = {_logical_T_417, _logical_T_414}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_hi_lo_hi_hi = {_logical_T_423, _logical_T_420}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_hi_lo_hi = {logical_lo_hi_hi_lo_hi_hi, logical_lo_hi_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_hi_hi_lo = {logical_lo_hi_hi_lo_hi, logical_lo_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_hi_hi_lo_lo = {_logical_T_429, _logical_T_426}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_hi_hi_lo_hi = {_logical_T_435, _logical_T_432}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_hi_hi_lo = {logical_lo_hi_hi_hi_lo_hi, logical_lo_hi_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_hi_hi_hi_lo = {_logical_T_441, _logical_T_438}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_hi_hi_hi_hi = {_logical_T_447, _logical_T_444}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_hi_hi_hi = {logical_lo_hi_hi_hi_hi_hi, logical_lo_hi_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_hi_hi_hi = {logical_lo_hi_hi_hi_hi, logical_lo_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_lo_hi_hi = {logical_lo_hi_hi_hi, logical_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [31:0] logical_lo_hi = {logical_lo_hi_hi, logical_lo_hi_lo}; // @[Atomics.scala:40:20] wire [63:0] logical_lo = {logical_lo_hi, logical_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_lo_lo_lo_lo = {_logical_T_453, _logical_T_450}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_lo_lo_lo_hi = {_logical_T_459, _logical_T_456}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_lo_lo_lo = {logical_hi_lo_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_lo_lo_hi_lo = {_logical_T_465, _logical_T_462}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_lo_lo_hi_hi = {_logical_T_471, _logical_T_468}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_lo_lo_hi = {logical_hi_lo_lo_lo_hi_hi, logical_hi_lo_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_lo_lo_lo = {logical_hi_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_lo_hi_lo_lo = {_logical_T_477, _logical_T_474}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_lo_hi_lo_hi = {_logical_T_483, _logical_T_480}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_lo_hi_lo = {logical_hi_lo_lo_hi_lo_hi, logical_hi_lo_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_lo_hi_hi_lo = {_logical_T_489, _logical_T_486}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_lo_hi_hi_hi = {_logical_T_495, _logical_T_492}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_lo_hi_hi = {logical_hi_lo_lo_hi_hi_hi, logical_hi_lo_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_lo_lo_hi = {logical_hi_lo_lo_hi_hi, logical_hi_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_hi_lo_lo = {logical_hi_lo_lo_hi, logical_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_hi_lo_lo_lo = {_logical_T_501, _logical_T_498}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_hi_lo_lo_hi = {_logical_T_507, _logical_T_504}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_hi_lo_lo = {logical_hi_lo_hi_lo_lo_hi, logical_hi_lo_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_hi_lo_hi_lo = {_logical_T_513, _logical_T_510}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_hi_lo_hi_hi = {_logical_T_519, _logical_T_516}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_hi_lo_hi = {logical_hi_lo_hi_lo_hi_hi, logical_hi_lo_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_lo_hi_lo = {logical_hi_lo_hi_lo_hi, logical_hi_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_hi_hi_lo_lo = {_logical_T_525, _logical_T_522}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_hi_hi_lo_hi = {_logical_T_531, _logical_T_528}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_hi_hi_lo = {logical_hi_lo_hi_hi_lo_hi, logical_hi_lo_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_hi_hi_hi_lo = {_logical_T_537, _logical_T_534}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_hi_hi_hi_hi = {_logical_T_543, _logical_T_540}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_hi_hi_hi = {logical_hi_lo_hi_hi_hi_hi, logical_hi_lo_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_lo_hi_hi = {logical_hi_lo_hi_hi_hi, logical_hi_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_hi_lo_hi = {logical_hi_lo_hi_hi, logical_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [31:0] logical_hi_lo = {logical_hi_lo_hi, logical_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_lo_lo_lo_lo = {_logical_T_549, _logical_T_546}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_lo_lo_lo_hi = {_logical_T_555, _logical_T_552}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_lo_lo_lo = {logical_hi_hi_lo_lo_lo_hi, logical_hi_hi_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_lo_lo_hi_lo = {_logical_T_561, _logical_T_558}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_lo_lo_hi_hi = {_logical_T_567, _logical_T_564}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_lo_lo_hi = {logical_hi_hi_lo_lo_hi_hi, logical_hi_hi_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_hi_lo_lo = {logical_hi_hi_lo_lo_hi, logical_hi_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_lo_hi_lo_lo = {_logical_T_573, _logical_T_570}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_lo_hi_lo_hi = {_logical_T_579, _logical_T_576}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_lo_hi_lo = {logical_hi_hi_lo_hi_lo_hi, logical_hi_hi_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_lo_hi_hi_lo = {_logical_T_585, _logical_T_582}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_lo_hi_hi_hi = {_logical_T_591, _logical_T_588}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_lo_hi_hi = {logical_hi_hi_lo_hi_hi_hi, logical_hi_hi_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_hi_lo_hi = {logical_hi_hi_lo_hi_hi, logical_hi_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_hi_hi_lo = {logical_hi_hi_lo_hi, logical_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_hi_lo_lo_lo = {_logical_T_597, _logical_T_594}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_hi_lo_lo_hi = {_logical_T_603, _logical_T_600}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_hi_lo_lo = {logical_hi_hi_hi_lo_lo_hi, logical_hi_hi_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_hi_lo_hi_lo = {_logical_T_609, _logical_T_606}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_hi_lo_hi_hi = {_logical_T_615, _logical_T_612}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_hi_lo_hi = {logical_hi_hi_hi_lo_hi_hi, logical_hi_hi_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_hi_hi_lo = {logical_hi_hi_hi_lo_hi, logical_hi_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_hi_hi_lo_lo = {_logical_T_621, _logical_T_618}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_hi_hi_lo_hi = {_logical_T_627, _logical_T_624}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_hi_hi_lo = {logical_hi_hi_hi_hi_lo_hi, logical_hi_hi_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_hi_hi_hi_lo = {_logical_T_633, _logical_T_630}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_hi_hi_hi_hi = {_logical_T_639, _logical_T_636}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_hi_hi_hi = {logical_hi_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_hi_hi_hi = {logical_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_hi_hi_hi = {logical_hi_hi_hi_hi, logical_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [31:0] logical_hi_hi = {logical_hi_hi_hi, logical_hi_hi_lo}; // @[Atomics.scala:40:20] wire [63:0] logical_hi = {logical_hi_hi, logical_hi_lo}; // @[Atomics.scala:40:20] wire [127:0] logical = {logical_hi, logical_lo}; // @[Atomics.scala:40:20] wire [1:0] _select_T_1 = adder ? 2'h2 : {1'h0, _select_T}; // @[Atomics.scala:8:7, :10:14, :18:28, :48:{8,24}] wire [1:0] _select_WIRE_2 = _select_T_1; // @[Atomics.scala:45:42, :48:8] wire [7:0][1:0] _GEN_0 = {{2'h0}, {2'h0}, {2'h0}, {2'h0}, {2'h3}, {_select_WIRE_2}, {2'h1}, {2'h1}}; // @[Atomics.scala:45:{19,42}] wire [1:0] select = io_write_0 ? 2'h1 : _GEN_0[io_a_opcode_0]; // @[Atomics.scala:8:7, :45:19] wire [1:0] selects_0 = _selects_T ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_1 = _selects_T_1 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_2 = _selects_T_2 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_3 = _selects_T_3 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_4 = _selects_T_4 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_5 = _selects_T_5 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_6 = _selects_T_6 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_7 = _selects_T_7 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_8 = _selects_T_8 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_9 = _selects_T_9 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_10 = _selects_T_10 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_11 = _selects_T_11 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_12 = _selects_T_12 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_13 = _selects_T_13 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_14 = _selects_T_14 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_15 = _selects_T_15 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [7:0] _io_data_out_T = io_data_in_0[7:0]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_0 = _io_data_out_T; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_1 = io_a_data_0[7:0]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_1 = _io_data_out_T_1; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_2 = sum[7:0]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_2 = _io_data_out_T_2; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_3 = logical[7:0]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_3 = _io_data_out_T_3; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_4 = io_data_in_0[15:8]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_1_0 = _io_data_out_T_4; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_5 = io_a_data_0[15:8]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_1_1 = _io_data_out_T_5; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_6 = sum[15:8]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_1_2 = _io_data_out_T_6; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_7 = logical[15:8]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_1_3 = _io_data_out_T_7; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_8 = io_data_in_0[23:16]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_2_0 = _io_data_out_T_8; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_9 = io_a_data_0[23:16]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_2_1 = _io_data_out_T_9; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_10 = sum[23:16]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_2_2 = _io_data_out_T_10; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_11 = logical[23:16]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_2_3 = _io_data_out_T_11; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_12 = io_data_in_0[31:24]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_3_0 = _io_data_out_T_12; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_13 = io_a_data_0[31:24]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_3_1 = _io_data_out_T_13; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_14 = sum[31:24]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_3_2 = _io_data_out_T_14; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_15 = logical[31:24]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_3_3 = _io_data_out_T_15; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_16 = io_data_in_0[39:32]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_4_0 = _io_data_out_T_16; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_17 = io_a_data_0[39:32]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_4_1 = _io_data_out_T_17; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_18 = sum[39:32]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_4_2 = _io_data_out_T_18; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_19 = logical[39:32]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_4_3 = _io_data_out_T_19; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_20 = io_data_in_0[47:40]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_5_0 = _io_data_out_T_20; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_21 = io_a_data_0[47:40]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_5_1 = _io_data_out_T_21; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_22 = sum[47:40]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_5_2 = _io_data_out_T_22; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_23 = logical[47:40]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_5_3 = _io_data_out_T_23; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_24 = io_data_in_0[55:48]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_6_0 = _io_data_out_T_24; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_25 = io_a_data_0[55:48]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_6_1 = _io_data_out_T_25; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_26 = sum[55:48]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_6_2 = _io_data_out_T_26; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_27 = logical[55:48]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_6_3 = _io_data_out_T_27; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_28 = io_data_in_0[63:56]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_7_0 = _io_data_out_T_28; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_29 = io_a_data_0[63:56]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_7_1 = _io_data_out_T_29; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_30 = sum[63:56]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_7_2 = _io_data_out_T_30; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_31 = logical[63:56]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_7_3 = _io_data_out_T_31; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_32 = io_data_in_0[71:64]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_8_0 = _io_data_out_T_32; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_33 = io_a_data_0[71:64]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_8_1 = _io_data_out_T_33; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_34 = sum[71:64]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_8_2 = _io_data_out_T_34; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_35 = logical[71:64]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_8_3 = _io_data_out_T_35; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_36 = io_data_in_0[79:72]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_9_0 = _io_data_out_T_36; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_37 = io_a_data_0[79:72]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_9_1 = _io_data_out_T_37; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_38 = sum[79:72]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_9_2 = _io_data_out_T_38; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_39 = logical[79:72]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_9_3 = _io_data_out_T_39; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_40 = io_data_in_0[87:80]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_10_0 = _io_data_out_T_40; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_41 = io_a_data_0[87:80]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_10_1 = _io_data_out_T_41; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_42 = sum[87:80]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_10_2 = _io_data_out_T_42; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_43 = logical[87:80]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_10_3 = _io_data_out_T_43; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_44 = io_data_in_0[95:88]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_11_0 = _io_data_out_T_44; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_45 = io_a_data_0[95:88]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_11_1 = _io_data_out_T_45; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_46 = sum[95:88]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_11_2 = _io_data_out_T_46; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_47 = logical[95:88]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_11_3 = _io_data_out_T_47; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_48 = io_data_in_0[103:96]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_12_0 = _io_data_out_T_48; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_49 = io_a_data_0[103:96]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_12_1 = _io_data_out_T_49; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_50 = sum[103:96]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_12_2 = _io_data_out_T_50; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_51 = logical[103:96]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_12_3 = _io_data_out_T_51; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_52 = io_data_in_0[111:104]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_13_0 = _io_data_out_T_52; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_53 = io_a_data_0[111:104]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_13_1 = _io_data_out_T_53; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_54 = sum[111:104]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_13_2 = _io_data_out_T_54; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_55 = logical[111:104]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_13_3 = _io_data_out_T_55; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_56 = io_data_in_0[119:112]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_14_0 = _io_data_out_T_56; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_57 = io_a_data_0[119:112]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_14_1 = _io_data_out_T_57; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_58 = sum[119:112]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_14_2 = _io_data_out_T_58; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_59 = logical[119:112]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_14_3 = _io_data_out_T_59; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_60 = io_data_in_0[127:120]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_15_0 = _io_data_out_T_60; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_61 = io_a_data_0[127:120]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_15_1 = _io_data_out_T_61; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_62 = sum[127:120]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_15_2 = _io_data_out_T_62; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_63 = logical[127:120]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_15_3 = _io_data_out_T_63; // @[Atomics.scala:59:{12,59}] wire [3:0][7:0] _GEN_1 = {{_io_data_out_WIRE_1_3}, {_io_data_out_WIRE_1_2}, {_io_data_out_WIRE_1_1}, {_io_data_out_WIRE_1_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_2 = {{_io_data_out_WIRE_3}, {_io_data_out_WIRE_2}, {_io_data_out_WIRE_1}, {_io_data_out_WIRE_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_lo_lo_lo = {_GEN_1[selects_1], _GEN_2[selects_0]}; // @[Atomics.scala:57:47, :58:21] wire [3:0][7:0] _GEN_3 = {{_io_data_out_WIRE_3_3}, {_io_data_out_WIRE_3_2}, {_io_data_out_WIRE_3_1}, {_io_data_out_WIRE_3_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_4 = {{_io_data_out_WIRE_2_3}, {_io_data_out_WIRE_2_2}, {_io_data_out_WIRE_2_1}, {_io_data_out_WIRE_2_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_lo_lo_hi = {_GEN_3[selects_3], _GEN_4[selects_2]}; // @[Atomics.scala:57:47, :58:21] wire [31:0] io_data_out_lo_lo = {io_data_out_lo_lo_hi, io_data_out_lo_lo_lo}; // @[Atomics.scala:58:21] wire [3:0][7:0] _GEN_5 = {{_io_data_out_WIRE_5_3}, {_io_data_out_WIRE_5_2}, {_io_data_out_WIRE_5_1}, {_io_data_out_WIRE_5_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_6 = {{_io_data_out_WIRE_4_3}, {_io_data_out_WIRE_4_2}, {_io_data_out_WIRE_4_1}, {_io_data_out_WIRE_4_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_lo_hi_lo = {_GEN_5[selects_5], _GEN_6[selects_4]}; // @[Atomics.scala:57:47, :58:21] wire [3:0][7:0] _GEN_7 = {{_io_data_out_WIRE_7_3}, {_io_data_out_WIRE_7_2}, {_io_data_out_WIRE_7_1}, {_io_data_out_WIRE_7_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_8 = {{_io_data_out_WIRE_6_3}, {_io_data_out_WIRE_6_2}, {_io_data_out_WIRE_6_1}, {_io_data_out_WIRE_6_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_lo_hi_hi = {_GEN_7[selects_7], _GEN_8[selects_6]}; // @[Atomics.scala:57:47, :58:21] wire [31:0] io_data_out_lo_hi = {io_data_out_lo_hi_hi, io_data_out_lo_hi_lo}; // @[Atomics.scala:58:21] wire [63:0] io_data_out_lo = {io_data_out_lo_hi, io_data_out_lo_lo}; // @[Atomics.scala:58:21] wire [3:0][7:0] _GEN_9 = {{_io_data_out_WIRE_9_3}, {_io_data_out_WIRE_9_2}, {_io_data_out_WIRE_9_1}, {_io_data_out_WIRE_9_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_10 = {{_io_data_out_WIRE_8_3}, {_io_data_out_WIRE_8_2}, {_io_data_out_WIRE_8_1}, {_io_data_out_WIRE_8_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_hi_lo_lo = {_GEN_9[selects_9], _GEN_10[selects_8]}; // @[Atomics.scala:57:47, :58:21] wire [3:0][7:0] _GEN_11 = {{_io_data_out_WIRE_11_3}, {_io_data_out_WIRE_11_2}, {_io_data_out_WIRE_11_1}, {_io_data_out_WIRE_11_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_12 = {{_io_data_out_WIRE_10_3}, {_io_data_out_WIRE_10_2}, {_io_data_out_WIRE_10_1}, {_io_data_out_WIRE_10_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_hi_lo_hi = {_GEN_11[selects_11], _GEN_12[selects_10]}; // @[Atomics.scala:57:47, :58:21] wire [31:0] io_data_out_hi_lo = {io_data_out_hi_lo_hi, io_data_out_hi_lo_lo}; // @[Atomics.scala:58:21] wire [3:0][7:0] _GEN_13 = {{_io_data_out_WIRE_13_3}, {_io_data_out_WIRE_13_2}, {_io_data_out_WIRE_13_1}, {_io_data_out_WIRE_13_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_14 = {{_io_data_out_WIRE_12_3}, {_io_data_out_WIRE_12_2}, {_io_data_out_WIRE_12_1}, {_io_data_out_WIRE_12_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_hi_hi_lo = {_GEN_13[selects_13], _GEN_14[selects_12]}; // @[Atomics.scala:57:47, :58:21] wire [3:0][7:0] _GEN_15 = {{_io_data_out_WIRE_15_3}, {_io_data_out_WIRE_15_2}, {_io_data_out_WIRE_15_1}, {_io_data_out_WIRE_15_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_16 = {{_io_data_out_WIRE_14_3}, {_io_data_out_WIRE_14_2}, {_io_data_out_WIRE_14_1}, {_io_data_out_WIRE_14_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_hi_hi_hi = {_GEN_15[selects_15], _GEN_16[selects_14]}; // @[Atomics.scala:57:47, :58:21] wire [31:0] io_data_out_hi_hi = {io_data_out_hi_hi_hi, io_data_out_hi_hi_lo}; // @[Atomics.scala:58:21] wire [63:0] io_data_out_hi = {io_data_out_hi_hi, io_data_out_hi_lo}; // @[Atomics.scala:58:21] assign _io_data_out_T_64 = {io_data_out_hi, io_data_out_lo}; // @[Atomics.scala:58:21] assign io_data_out_0 = _io_data_out_T_64; // @[Atomics.scala:8:7, :58:21] assign io_data_out = io_data_out_0; // @[Atomics.scala:8:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_4( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_6 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RegisterFile.scala: package saturn.backend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.tile.{CoreModule} import freechips.rocketchip.util._ import saturn.common._ class OldestRRArbiter(val n: Int)(implicit p: Parameters) extends Module { val io = IO(new ArbiterIO(new VectorReadReq, n)) val arb = Module(new RRArbiter(new VectorReadReq, n)) io <> arb.io val oldest_oh = io.in.map(i => i.valid && i.bits.oldest) //assert(PopCount(oldest_oh) <= 1.U) when (oldest_oh.orR) { io.chosen := VecInit(oldest_oh).asUInt io.out.valid := true.B io.out.bits := Mux1H(oldest_oh, io.in.map(_.bits)) for (i <- 0 until n) { io.in(i).ready := oldest_oh(i) && io.out.ready } } } class RegisterReadXbar(n: Int, banks: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val in = Vec(n, Flipped(new VectorReadIO)) val out = Vec(banks, new VectorReadIO) }) val arbs = Seq.fill(banks) { Module(new OldestRRArbiter(n)) } for (i <- 0 until banks) { io.out(i).req <> arbs(i).io.out } val bankOffset = log2Ceil(banks) for (i <- 0 until n) { val bank_sel = if (bankOffset == 0) true.B else UIntToOH(io.in(i).req.bits.eg(bankOffset-1,0)) for (j <- 0 until banks) { arbs(j).io.in(i).valid := io.in(i).req.valid && bank_sel(j) arbs(j).io.in(i).bits.eg := io.in(i).req.bits.eg >> bankOffset arbs(j).io.in(i).bits.oldest := io.in(i).req.bits.oldest } io.in(i).req.ready := Mux1H(bank_sel, arbs.map(_.io.in(i).ready)) io.in(i).resp := Mux1H(bank_sel, io.out.map(_.resp)) } } class RegisterFileBank(reads: Int, maskReads: Int, rows: Int, maskRows: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val read = Vec(reads, Flipped(new VectorReadIO)) val mask_read = Vec(maskReads, Flipped(new VectorReadIO)) val write = Input(Valid(new VectorWrite(dLen))) val ll_write = Flipped(Decoupled(new VectorWrite(dLen))) }) val ll_write_valid = RegInit(false.B) val ll_write_bits = Reg(new VectorWrite(dLen)) val vrf = Mem(rows, Vec(dLen, Bool())) val v0_mask = Mem(maskRows, Vec(dLen, Bool())) for (read <- io.read) { read.req.ready := !(ll_write_valid && read.req.bits.eg === ll_write_bits.eg) read.resp := DontCare when (read.req.valid) { read.resp := vrf.read(read.req.bits.eg).asUInt } } for (mask_read <- io.mask_read) { mask_read.req.ready := !(ll_write_valid && mask_read.req.bits.eg === ll_write_bits.eg) mask_read.resp := DontCare when (mask_read.req.valid) { mask_read.resp := v0_mask.read(mask_read.req.bits.eg).asUInt } } val write = WireInit(io.write) io.ll_write.ready := false.B if (vParams.vrfHiccupBuffer) { when (!io.write.valid) { // drain hiccup buffer write.valid := ll_write_valid \|\| io.ll_write.valid write.bits := Mux(ll_write_valid, ll_write_bits, io.ll_write.bits) ll_write_valid := false.B when (io.ll_write.valid && ll_write_valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } .elsewhen (!ll_write_valid) { // fill hiccup buffer when (io.ll_write.valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } } else { when (!io.write.valid) { io.ll_write.ready := true.B write.valid := io.ll_write.valid write.bits := io.ll_write.bits } } when (write.valid) { vrf.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) when (write.bits.eg < maskRows.U) { v0_mask.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) } } } class RegisterFile(reads: Seq[Int], maskReads: Seq[Int], pipeWrites: Int, llWrites: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val nBanks = vParams.vrfBanking // Support 1, 2, and 4 banks for the VRF require(nBanks == 1 \|\| nBanks == 2 \|\| nBanks == 4) val io = IO(new Bundle { val read = MixedVec(reads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val mask_read = MixedVec(maskReads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val pipe_writes = Vec(pipeWrites, Input(Valid(new VectorWrite(dLen)))) val ll_writes = Vec(llWrites, Flipped(Decoupled(new VectorWrite(dLen)))) }) val vrf = Seq.fill(nBanks) { Module(new RegisterFileBank(reads.size, maskReads.size, egsTotal/nBanks, if (egsPerVReg < nBanks) 1 else egsPerVReg / nBanks)) } reads.zipWithIndex.foreach { case (rc, i) => val xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.read(i) <> xbar.io.out(j) } xbar.io.in <> io.read(i) } maskReads.zipWithIndex.foreach { case (rc, i) => val mask_xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.mask_read(i) <> mask_xbar.io.out(j) } mask_xbar.io.in <> io.mask_read(i) } io.ll_writes.foreach(_.ready := false.B) vrf.zipWithIndex.foreach { case (rf, i) => val bank_match = io.pipe_writes.map { w => (w.bits.bankId === i.U) && w.valid } val bank_write_data = Mux1H(bank_match, io.pipe_writes.map(_.bits.data)) val bank_write_mask = Mux1H(bank_match, io.pipe_writes.map(_.bits.mask)) val bank_write_eg = Mux1H(bank_match, io.pipe_writes.map(_.bits.eg)) val bank_write_valid = bank_match.orR rf.io.write.valid := bank_write_valid rf.io.write.bits.data := bank_write_data rf.io.write.bits.mask := bank_write_mask rf.io.write.bits.eg := bank_write_eg >> vrfBankBits when (bank_write_valid) { PopCount(bank_match) === 1.U } val ll_arb = Module(new Arbiter(new VectorWrite(dLen), llWrites)) rf.io.ll_write <> ll_arb.io.out io.ll_writes.zipWithIndex.foreach { case (w, j) => ll_arb.io.in(j).valid := w.valid && w.bits.bankId === i.U ll_arb.io.in(j).bits.eg := w.bits.eg >> vrfBankBits ll_arb.io.in(j).bits.data := w.bits.data ll_arb.io.in(j).bits.mask := w.bits.mask when (ll_arb.io.in(j).ready && w.bits.bankId === i.U) { w.ready := true.B } } } }	module OldestRRArbiter( // @[RegisterFile.scala:10:7] input clock, // @[RegisterFile.scala:10:7] output io_in_0_ready, // @[RegisterFile.scala:11:14] input io_in_0_valid, // @[RegisterFile.scala:11:14] input [4:0] io_in_0_bits_eg, // @[RegisterFile.scala:11:14] input io_in_0_bits_oldest, // @[RegisterFile.scala:11:14] output io_in_1_ready, // @[RegisterFile.scala:11:14] input io_in_1_valid, // @[RegisterFile.scala:11:14] input [4:0] io_in_1_bits_eg, // @[RegisterFile.scala:11:14] input io_in_1_bits_oldest, // @[RegisterFile.scala:11:14] output io_in_2_ready, // @[RegisterFile.scala:11:14] input io_in_2_valid, // @[RegisterFile.scala:11:14] input [4:0] io_in_2_bits_eg, // @[RegisterFile.scala:11:14] input io_out_ready, // @[RegisterFile.scala:11:14] output io_out_valid, // @[RegisterFile.scala:11:14] output [4:0] io_out_bits_eg // @[RegisterFile.scala:11:14] ); wire _arb_io_in_0_ready; // @[RegisterFile.scala:13:19] wire _arb_io_in_1_ready; // @[RegisterFile.scala:13:19] wire _arb_io_in_2_ready; // @[RegisterFile.scala:13:19] wire _arb_io_out_valid; // @[RegisterFile.scala:13:19] wire [4:0] _arb_io_out_bits_eg; // @[RegisterFile.scala:13:19] wire oldest_oh_0 = io_in_0_valid & io_in_0_bits_oldest; // @[RegisterFile.scala:15:42] wire oldest_oh_1 = io_in_1_valid & io_in_1_bits_oldest; // @[RegisterFile.scala:15:42] wire _GEN = oldest_oh_0 \| oldest_oh_1; // @[RegisterFile.scala:15:42] RRArbiter arb ( // @[RegisterFile.scala:13:19] .clock (clock), .io_in_0_ready (_arb_io_in_0_ready), .io_in_0_valid (io_in_0_valid), .io_in_0_bits_eg (io_in_0_bits_eg), .io_in_1_ready (_arb_io_in_1_ready), .io_in_1_valid (io_in_1_valid), .io_in_1_bits_eg (io_in_1_bits_eg), .io_in_2_ready (_arb_io_in_2_ready), .io_in_2_valid (io_in_2_valid), .io_in_2_bits_eg (io_in_2_bits_eg), .io_out_ready (io_out_ready), .io_out_valid (_arb_io_out_valid), .io_out_bits_eg (_arb_io_out_bits_eg) ); // @[RegisterFile.scala:13:19] assign io_in_0_ready = _GEN ? oldest_oh_0 & io_out_ready : _arb_io_in_0_ready; // @[RegisterFile.scala:10:7, :13:19, :14:6, :15:42, :17:24, :22:{22,38}] assign io_in_1_ready = _GEN ? oldest_oh_1 & io_out_ready : _arb_io_in_1_ready; // @[RegisterFile.scala:10:7, :13:19, :14:6, :15:42, :17:24, :22:{22,38}] assign io_in_2_ready = ~_GEN & _arb_io_in_2_ready; // @[RegisterFile.scala:10:7, :13:19, :14:6, :17:24, :22:22] assign io_out_valid = _GEN \| _arb_io_out_valid; // @[RegisterFile.scala:10:7, :13:19, :14:6, :17:24, :19:18] assign io_out_bits_eg = _GEN ? (oldest_oh_0 ? io_in_0_bits_eg : 5'h0) \| (oldest_oh_1 ? io_in_1_bits_eg : 5'h0) : _arb_io_out_bits_eg; // @[Mux.scala:30:73] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_189( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first \| last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first \| last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid \|\| ((!w_releaseack \|\| !w_rprobeacklast \|\| !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst \|\| !w_pprobeackfirst \|\| !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB \|\| !io.status.bits.blockB) assert (!io.status.bits.nestC \|\| !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe \|\| !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) \|\| (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) \|\| (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid \|\| io.schedule.bits.b.valid \|\| io.schedule.bits.c.valid \|\| io.schedule.bits.d.valid \|\| io.schedule.bits.e.valid \|\| io.schedule.bits.x.valid \|\| io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock \|\| request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty \|\| request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) \|\| !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) \| Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid \|\| meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U \|\| !(request.opcode === PutFullData \|\| request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r \|\| p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c \|\| m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read \|\| clean release can lead to this state eviction(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_D, true) // MMIO write \|\| dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read \|\| clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write \|\| clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read \|\| clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done \| probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done \| probe_bit probes_toN := probes_toN \| Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT \|\| io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst \|\| last_probe w_rprobeacklast := w_rprobeacklast \|\| (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst \|\| last_probe w_pprobeacklast := w_pprobeacklast \|\| (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last \|\| request.offset === 0.U) w_pprobeack := w_pprobeack \|\| set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant \|\| io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U \|\| io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f \|\| p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read \|\| clean release can lead to this state bypass(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_D, true) // MMIO write \|\| dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid \|\| (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid \|\| (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit \|\| (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT \|\| new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock \|\| new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module MSHR_2( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h20; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h20; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body \|\| !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body \|\| !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) \|\| protocol.ready protocol.valid := (!is_const \|\| io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_\|\|_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink \| sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLCToNoC_7( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0; // @[package.scala:243:{46,71,76}] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 9'h1 \| tail_beats1 == 9'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_16( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_272 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_19( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire io_in_d_bits_denied = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1110 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1110; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1110; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] wire _T_1183 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1183; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1183; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1183; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1036 = _T_1110 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1036 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1036 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1036 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1036 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1036 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1082 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1082 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1051 = _T_1183 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1051 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1051 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1051 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1154 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1154 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1136 = _T_1183 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1136 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1136 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1136 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File util.scala: //*************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File execution-unit.scala: //****************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Execution Units //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // The issue window schedules micro-ops onto a specific execution pipeline // A given execution pipeline may contain multiple functional units; one or more // read ports, and one or more writeports. package boom.v4.exu import scala.collection.mutable.{ArrayBuffer} import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.{BP, SFenceReq, CSR} import freechips.rocketchip.rocket.constants.{MemoryOpConstants} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile import freechips.rocketchip.util._ import boom.v4.common._ import boom.v4.ifu.FTQInfo import boom.v4.util._ class Wakeup(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val bypassable = Bool() val speculative_mask = UInt(aluWidth.W) val rebusy = Bool() } class ExeUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val data = Bits(dataWidth.W) val predicated = Bool() // Was this predicated off? val fflags = Valid(UInt(tile.FPConstants.FLAGS_SZ.W)) } class MemGen(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val data = UInt(xLen.W) } class CSRResp(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val data = UInt(xLen.W) val addr = UInt(CSR.ADDRSZ.W) } abstract class ExecutionUnit(name: String)(implicit p: Parameters) extends BoomMultiIOModule { val fu_types = ArrayBuffer[(Int, Bool, String)]() def get_all_fu_types(): Vec[Bool] = { val r = WireInit(VecInit(Seq.fill(FC_SZ) { false.B })) fu_types.map { case (code, _, _) => { r(code) := true.B } } r } def get_ready_fu_types(): Vec[Bool] = { val r = WireInit(VecInit(Seq.fill(FC_SZ) { false.B })) fu_types.map { case (code, ready, _) => { when (ready) { r(code) := true.B } } } r } val io_kill = IO(Input(Bool())) val io_brupdate = IO(Input(new BrUpdateInfo)) val io_status = IO(Input(new freechips.rocketchip.rocket.MStatus)) val io_ready_fu_types = IO(Output(Vec(FC_SZ, Bool()))) val io_fcsr_rm = IO(Input(UInt(tile.FPConstants.RM_SZ.W))) override def toString = { BoomCoreStringPrefix(s"===${name}ExeUnit") + fu_types.map { case (_, _, s) => BoomCoreStringPrefix(s" - ${s}") }.reduce(_+_) } val io_iss_uop = IO(Input(Valid(new MicroOp))) val arb_uop = Reg(Valid(new MicroOp)) arb_uop.valid := io_iss_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, io_iss_uop.bits) arb_uop.bits := UpdateBrMask(io_brupdate, io_iss_uop.bits) val rrd_uop = Reg(Valid(new MicroOp)) rrd_uop.valid := arb_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, arb_uop.bits) rrd_uop.bits := UpdateBrMask(io_brupdate, arb_uop.bits) val exe_uop = Reg(Valid(new MicroOp)) exe_uop.valid := rrd_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, rrd_uop.bits) exe_uop.bits := UpdateBrMask(io_brupdate, rrd_uop.bits) } trait HasIrfReadPorts { this: ExecutionUnit => def nReaders: Int val io_arb_irf_reqs = IO(Vec(nReaders, Decoupled(UInt(maxPregSz.W)))) val io_arb_rebusys = IO(Input (Vec(lsuWidth, Valid(new Wakeup)))) val io_rrd_irf_resps = IO(Input (Vec(nReaders , UInt(xLen.W)))) val io_rrd_irf_bypasses = IO(Input (Vec(coreWidth + lsuWidth, Valid(new ExeUnitResp(xLen))))) def rrd_bypass_hit(prs: UInt, rdata: UInt): (Bool, UInt) = { val hits = io_rrd_irf_bypasses map { b => b.valid && prs === b.bits.uop.pdst } (hits.reduce(_\|\|_), Mux(hits.reduce(_\|\|_), Mux1H(hits, io_rrd_irf_bypasses.map(_.bits.data)), rdata)) } def rebusied(prs: UInt): Bool = { io_arb_rebusys.map { r => r.valid && r.bits.rebusy && r.bits.uop.pdst === prs }.reduce(_\|\|_) } io_arb_irf_reqs(0).valid := arb_uop.valid && arb_uop.bits.lrs1_rtype === RT_FIX && !arb_uop.bits.iw_p1_bypass_hint io_arb_irf_reqs(0).bits := arb_uop.bits.prs1 if (nReaders == 2) { io_arb_irf_reqs(1).valid := arb_uop.valid && arb_uop.bits.lrs2_rtype === RT_FIX && !arb_uop.bits.iw_p2_bypass_hint io_arb_irf_reqs(1).bits := arb_uop.bits.prs2 } val arb_rebusied_prs1 = arb_uop.bits.lrs1_rtype === RT_FIX && rebusied(arb_uop.bits.prs1) val arb_rebusied_prs2 = arb_uop.bits.lrs2_rtype === RT_FIX && rebusied(arb_uop.bits.prs2) && (nReaders == 2).B val arb_rebusied = arb_rebusied_prs1 \|\| arb_rebusied_prs2 val exe_rs1_data = Reg(UInt(xLen.W)) val exe_rs2_data = Reg(UInt(xLen.W)) val (rs1_hit, rs1_data) = rrd_bypass_hit(rrd_uop.bits.prs1, io_rrd_irf_resps(0)) assert(!(rrd_uop.valid && rrd_uop.bits.lrs1_rtype === RT_FIX && rrd_uop.bits.iw_p1_bypass_hint && !rs1_hit)) exe_rs1_data := Mux(rrd_uop.bits.lrs1_rtype === RT_ZERO, 0.U, rs1_data) if (nReaders == 2) { val (rs2_hit, rs2_data) = rrd_bypass_hit(rrd_uop.bits.prs2, io_rrd_irf_resps(1)) assert(!(rrd_uop.valid && rrd_uop.bits.lrs2_rtype === RT_FIX && rrd_uop.bits.iw_p2_bypass_hint && !rs2_hit)) exe_rs2_data := Mux(rrd_uop.bits.lrs2_rtype === RT_ZERO, 0.U, rs2_data) } else { exe_rs2_data := DontCare } } trait HasImmrfReadPort { this: ExecutionUnit => val io_arb_immrf_req = IO(Decoupled(UInt(immPregSz.W))) assert(io_arb_immrf_req.ready) val io_rrd_immrf_resp = IO(Input(UInt(xLen.W))) val io_rrd_immrf_wakeup = IO(Output(Valid(new Wakeup))) io_arb_immrf_req.valid := (arb_uop.valid && !arb_uop.bits.imm_sel.isOneOf(IS_N, IS_SH) ) io_arb_immrf_req.bits := arb_uop.bits.pimm io_rrd_immrf_wakeup.valid := (rrd_uop.valid && !rrd_uop.bits.imm_sel.isOneOf(IS_N, IS_SH) ) io_rrd_immrf_wakeup.bits.speculative_mask := false.B io_rrd_immrf_wakeup.bits.rebusy := false.B io_rrd_immrf_wakeup.bits.bypassable := false.B io_rrd_immrf_wakeup.bits.uop := rrd_uop.bits val exe_imm_data = RegNext(Mux(rrd_uop.bits.imm_sel === IS_SH, Sext(rrd_uop.bits.pimm, xLen), Sext(ImmGen(io_rrd_immrf_resp, rrd_uop.bits.imm_sel), xLen) )) } trait HasPrfReadPort { this: ExecutionUnit => val io_arb_prf_req = IO(Decoupled(UInt(log2Ceil(ftqSz).W))) assert(io_arb_prf_req.ready) val io_rrd_prf_resp = IO(Input(Bool())) io_arb_prf_req.valid := arb_uop.valid io_arb_prf_req.bits := arb_uop.bits.ppred val exe_pred_data = Reg(Bool()) exe_pred_data := io_rrd_prf_resp } trait HasBrfReadPort { this: ExecutionUnit => val io_arb_brf_req = IO(Decoupled(UInt(brTagSz.W))) assert(io_arb_brf_req.ready) val io_rrd_brf_resp = IO(Input(new BrInfoBundle)) io_arb_brf_req.valid := (arb_uop.valid && arb_uop.bits.is_br) io_arb_brf_req.bits := arb_uop.bits.br_tag exe_uop.bits.ldq_idx := io_rrd_brf_resp.ldq_idx exe_uop.bits.stq_idx := io_rrd_brf_resp.stq_idx exe_uop.bits.rxq_idx := io_rrd_brf_resp.rxq_idx } trait HasFrfReadPorts { this: ExecutionUnit => val io_arb_frf_reqs = IO(Vec(3, Decoupled(UInt(maxPregSz.W)))) val io_rrd_frf_resps = IO(Input (Vec(3, UInt((xLen+1).W)))) val io_rrd_frf_bypasses = IO(Input(Vec(fpWidth, Valid(new ExeUnitResp(fLen+1))))) def rrd_bypass_hit(prs: UInt, rdata: UInt): (Bool, UInt) = { val hits = io_rrd_frf_bypasses map { b => b.valid && prs === b.bits.uop.pdst } (hits.reduce(_\|\|_), Mux(hits.reduce(_\|\|_), Mux1H(hits, io_rrd_frf_bypasses.map(_.bits.data)), rdata)) } io_arb_frf_reqs(0).valid := arb_uop.valid && arb_uop.bits.lrs1_rtype === RT_FLT && !arb_uop.bits.iw_p1_bypass_hint io_arb_frf_reqs(0).bits := arb_uop.bits.prs1 io_arb_frf_reqs(1).valid := arb_uop.valid && arb_uop.bits.lrs2_rtype === RT_FLT && !arb_uop.bits.iw_p2_bypass_hint io_arb_frf_reqs(1).bits := arb_uop.bits.prs2 io_arb_frf_reqs(2).valid := arb_uop.valid && arb_uop.bits.frs3_en && !arb_uop.bits.iw_p3_bypass_hint io_arb_frf_reqs(2).bits := arb_uop.bits.prs3 val exe_rs1_data = Reg(UInt((fLen+1).W)) val exe_rs2_data = Reg(UInt((fLen+1).W)) val exe_rs3_data = Reg(UInt((fLen+1).W)) val (rs1_hit, rs1_data) = rrd_bypass_hit(rrd_uop.bits.prs1, io_rrd_frf_resps(0)) assert(!(rrd_uop.valid && rrd_uop.bits.lrs1_rtype === RT_FLT && rrd_uop.bits.iw_p1_bypass_hint && !rs1_hit)) exe_rs1_data := rs1_data val (rs2_hit, rs2_data) = rrd_bypass_hit(rrd_uop.bits.prs2, io_rrd_frf_resps(1)) assert(!(rrd_uop.valid && rrd_uop.bits.lrs2_rtype === RT_FLT && rrd_uop.bits.iw_p2_bypass_hint && !rs2_hit)) exe_rs2_data := rs2_data val (rs3_hit, rs3_data) = rrd_bypass_hit(rrd_uop.bits.prs3, io_rrd_frf_resps(2)) assert(!(rrd_uop.valid && rrd_uop.bits.iw_p3_bypass_hint && !rs3_hit)) exe_rs3_data := rs3_data } trait HasFtqReadPort { this: ExecutionUnit => val io_arb_ftq_reqs = IO(Vec(2, Decoupled(UInt(log2Ceil(ftqSz).W)))) val io_rrd_ftq_resps = IO(Vec(2, Input(new FTQInfo))) // Only allow one SFB branch through multiple pipes, to avoid unnecessary predicate wakeup logic io_arb_ftq_reqs(0).valid := arb_uop.valid && (arb_uop.bits.op1_sel === OP1_PC \|\| arb_uop.bits.is_sfb_br) io_arb_ftq_reqs(0).bits := arb_uop.bits.ftq_idx // Only JALR checks the next-pc io_arb_ftq_reqs(1).valid := arb_uop.valid && (arb_uop.bits.br_type === B_JR \|\| arb_uop.bits.is_sfb_br) io_arb_ftq_reqs(1).bits := WrapInc(arb_uop.bits.ftq_idx, ftqSz) val exe_ftq_data = Reg(Vec(2, new FTQInfo)) exe_ftq_data := io_rrd_ftq_resps } class MemExeUnit( val hasAGen : Boolean = false, val hasDGen : Boolean = false )(implicit p: Parameters) extends ExecutionUnit("Mem") with HasIrfReadPorts with HasImmrfReadPort { def nReaders = 1 val io_squash_iss = IO(Output(Bool())) io_squash_iss := (io_arb_irf_reqs(0).valid && !io_arb_irf_reqs(0).ready) when (io_squash_iss \|\| arb_rebusied) { val will_replay = arb_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, arb_uop.bits) && !arb_rebusied arb_uop.valid := will_replay arb_uop.bits := UpdateBrMask(io_brupdate, arb_uop.bits) arb_uop.bits.iw_p1_bypass_hint := false.B arb_uop.bits.iw_p2_bypass_hint := false.B rrd_uop.valid := false.B } val io_agen = if (hasAGen) { val loads_saturating = exe_uop.valid && exe_uop.bits.uses_ldq && exe_uop.bits.fu_code(FC_AGEN) val saturating_loads_counter = RegInit(0.U(5.W)) when (loads_saturating) { saturating_loads_counter := saturating_loads_counter + 1.U } .otherwise { saturating_loads_counter := 0.U } val pause_mem = RegNext(loads_saturating) && saturating_loads_counter === ~(0.U(5.W)) val load_ready = !pause_mem fu_types += ((FC_AGEN, load_ready, "AGen")) val sum = (exe_rs1_data.asSInt + exe_imm_data.asSInt).asUInt val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U, sum(63,vaddrBits) =/= 0.U) val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt val agen = IO(Output(Valid(new MemGen))) if (enableAgenStage) { val agen_reg = Reg(Valid(new MemGen)) agen_reg.valid := ( exe_uop.valid && exe_uop.bits.fu_code(FC_AGEN) && !IsKilledByBranch(io_brupdate, io_kill, exe_uop.bits) ) agen_reg.bits.uop := UpdateBrMask(io_brupdate, exe_uop.bits) agen_reg.bits.data := Sext(effective_address, xLen) agen := agen_reg } else { agen.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_AGEN) agen.bits.uop := exe_uop.bits agen.bits.data := Sext(effective_address, xLen) } Some(agen) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_AGEN))) None } val io_dgen = if (hasDGen) { fu_types += ((FC_DGEN, true.B, "DGen")) val dgen = IO(Output(Valid(new MemGen))) dgen.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_DGEN) dgen.bits.data := exe_rs1_data dgen.bits.uop := exe_uop.bits Some(dgen) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_DGEN))) None } io_ready_fu_types := get_ready_fu_types() } class UniqueExeUnit( val hasCSR : Boolean = false, val hasMul : Boolean = false, val hasDiv : Boolean = false, val hasIfpu : Boolean = false, val hasRocc : Boolean = false )(implicit p: Parameters) extends ExecutionUnit("Unq") with HasIrfReadPorts with HasImmrfReadPort with MemoryOpConstants { def nReaders = 2 val io_squash_iss = IO(Output(Bool())) io_squash_iss := ((io_arb_irf_reqs(0).valid && !io_arb_irf_reqs(0).ready) \|\| (io_arb_irf_reqs(1).valid && !io_arb_irf_reqs(1).ready)) when (io_squash_iss \|\| arb_rebusied) { val will_replay = arb_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, arb_uop.bits) && !arb_rebusied arb_uop.valid := will_replay arb_uop.bits := UpdateBrMask(io_brupdate, arb_uop.bits) arb_uop.bits.iw_p1_bypass_hint := false.B arb_uop.bits.iw_p2_bypass_hint := false.B rrd_uop.valid := false.B } val exe_int_req = Wire(new FuncUnitReq(xLen)) exe_int_req.uop := exe_uop.bits exe_int_req.rs1_data := exe_rs1_data exe_int_req.rs2_data := exe_rs2_data exe_int_req.rs3_data := DontCare exe_int_req.imm_data := exe_imm_data exe_int_req.pred_data := DontCare exe_int_req.ftq_info := DontCare val io_mul_resp = if (hasMul) { fu_types += ((FC_MUL, true.B, "IMul")) val imul = Module(new PipelinedMulUnit(imulLatency, xLen)) imul.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_MUL) imul.io.req.bits := exe_int_req imul.io.brupdate := io_brupdate imul.io.kill := io_kill imul.io.resp.ready := true.B val resp = IO(Output(Valid(new ExeUnitResp(xLen)))) resp := imul.io.resp Some(resp) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_MUL))) None } val (io_csr_resp, io_sfence) = if (hasCSR) { fu_types += ((FC_CSR, true.B, "CSR")) val alu = Module(new ALUUnit(dataWidth = xLen)) alu.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_CSR) alu.io.req.bits := exe_int_req alu.io.resp.ready := true.B alu.io.brupdate := io_brupdate alu.io.kill := io_kill val c = IO(Output(Valid(new CSRResp))) c.valid := RegNext(alu.io.resp.valid && exe_uop.bits.csr_cmd =/= CSR.N) c.bits.uop := RegNext(alu.io.resp.bits.uop) c.bits.data := RegNext(alu.io.resp.bits.data) c.bits.addr := RegNext(exe_imm_data) val s = IO(Valid(new SFenceReq)) s.valid := RegNext(exe_uop.valid && exe_uop.bits.is_sfence) s.bits.rs1 := RegNext(exe_uop.bits.pimm(0)) s.bits.rs2 := RegNext(exe_uop.bits.pimm(1)) s.bits.addr := RegNext(exe_rs1_data) s.bits.asid := RegNext(exe_rs2_data) s.bits.hv := RegNext(exe_uop.bits.mem_cmd === M_HFENCEV) s.bits.hg := RegNext(exe_uop.bits.mem_cmd === M_HFENCEG) (Some(c), Some(s)) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_CSR))) assert(!(exe_uop.valid && exe_uop.bits.mem_cmd === M_SFENCE)) (None, None) } val (io_rocc_resp, io_rocc_core) = if (hasRocc) { require(hasCSR) val rocc_core = IO(new RoCCShimCoreIO) val rocc_resp = IO(Decoupled(new ExeUnitResp(xLen))) val rocc = Module(new RoCCShim) rocc.io.req.valid := exe_uop.valid && exe_uop.bits.is_rocc rocc.io.req.bits := exe_int_req rocc.io.brupdate := io_brupdate // We should assert on this somewhere rocc.io.status := io_status rocc.io.exception := io_kill rocc_core <> rocc.io.core rocc_resp <> rocc.io.resp (Some(rocc_resp), Some(rocc_core)) } else { assert(!(exe_uop.valid && exe_uop.bits.is_rocc)) (None, None) } val (io_ifpu_resp) = if (hasIfpu) { val ifpu_ready = Wire(Bool()) fu_types += ((FC_I2F, ifpu_ready, "IFPU")) val ifpu = Module(new IntToFPUnit(latency=intToFpLatency)) ifpu.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_I2F) ifpu.io.req.bits := exe_int_req ifpu.io.req.bits.uop.fp_rm := exe_uop.bits.prs2(4,2) ifpu.io.req.bits.uop.fp_typ := exe_uop.bits.prs2(1,0) ifpu.io.fcsr_rm := io_fcsr_rm ifpu.io.brupdate := io_brupdate ifpu.io.kill := io_kill // buffer up results since we share write-port on integer regfile. val queue = Module(new BranchKillableQueue(new ExeUnitResp(xLen+1), entries = intToFpLatency + 6)) // TODO being overly conservative queue.io.enq <> ifpu.io.resp queue.io.brupdate := io_brupdate queue.io.flush := io_kill assert (!(queue.io.enq.valid && !queue.io.enq.ready)) ifpu_ready := RegNext(queue.io.count < 2.U) val ifpu_resp = IO(Decoupled(new ExeUnitResp(xLen+1))) ifpu_resp <> queue.io.deq (Some(ifpu_resp)) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_I2F))) (None) } val (io_div_resp) = if (hasDiv) { val div_ready = Wire(Bool()) fu_types += ((FC_DIV, div_ready, "IDiv")) val div = Module(new DivUnit(xLen)) assert(!(div.io.req.valid && !div.io.req.ready)) div.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_DIV) div.io.req.bits := exe_int_req div.io.brupdate := io_brupdate div.io.kill := io_kill div_ready := (div.io.req.ready && !(exe_uop.valid && exe_uop.bits.fu_code(FC_DIV)) && !(rrd_uop.valid && rrd_uop.bits.fu_code(FC_DIV)) && !(arb_uop.valid && arb_uop.bits.fu_code(FC_DIV)) ) val div_resp = IO(Decoupled(new ExeUnitResp(xLen))) div_resp <> div.io.resp Some(div_resp) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_DIV))) (None) } io_ready_fu_types := get_ready_fu_types() } class ALUExeUnit( val id: Int )(implicit p: Parameters) extends ExecutionUnit("Alu") with HasIrfReadPorts with HasPrfReadPort with HasImmrfReadPort with HasBrfReadPort with HasFtqReadPort { def nReaders = 2 val io_fast_wakeup = IO(Output(Valid(new Wakeup))) io_fast_wakeup.valid := ( io_iss_uop.valid && (io_iss_uop.bits.dst_rtype === RT_FIX) ) io_fast_wakeup.bits.uop := io_iss_uop.bits io_fast_wakeup.bits.speculative_mask := (1 << id).U io_fast_wakeup.bits.rebusy := false.B io_fast_wakeup.bits.bypassable := true.B val io_fast_pred_wakeup = IO(Output(Valid(new Wakeup))) io_fast_pred_wakeup.valid := rrd_uop.valid && rrd_uop.bits.is_sfb_br io_fast_pred_wakeup.bits.uop := rrd_uop.bits io_fast_pred_wakeup.bits.speculative_mask := 0.U io_fast_pred_wakeup.bits.rebusy := false.B io_fast_pred_wakeup.bits.bypassable := false.B val io_squash_iss = IO(Output(Bool())) io_squash_iss := ((io_arb_irf_reqs(0).valid && !io_arb_irf_reqs(0).ready) \|\| (io_arb_irf_reqs(1).valid && !io_arb_irf_reqs(1).ready) \|\| (io_arb_ftq_reqs(0).valid && !io_arb_ftq_reqs(0).ready) \|\| (io_arb_ftq_reqs(1).valid && !io_arb_ftq_reqs(1).ready)) val io_child_rebusy = IO(Output(UInt(aluWidth.W))) io_child_rebusy := 0.U when (arb_rebusied && arb_uop.valid) { io_child_rebusy := (1 << id).U } // The arbiter didn't grant us a slot. Thus, we should replay the instruction in this slot, // But next time we read, it reads from the regfile, not the bypass paths, so disable the bypass hints when (io_squash_iss \|\| arb_rebusied) { val will_replay = arb_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, arb_uop.bits) && !arb_rebusied arb_uop.valid := will_replay arb_uop.bits := UpdateBrMask(io_brupdate, arb_uop.bits) arb_uop.bits.iw_p1_bypass_hint := false.B arb_uop.bits.iw_p2_bypass_hint := false.B rrd_uop.valid := false.B } val exe_int_req = Wire(new FuncUnitReq(xLen)) exe_int_req.uop := exe_uop.bits exe_int_req.rs1_data := exe_rs1_data exe_int_req.rs2_data := exe_rs2_data exe_int_req.rs3_data := DontCare exe_int_req.imm_data := exe_imm_data exe_int_req.pred_data := exe_pred_data exe_int_req.ftq_info := exe_ftq_data fu_types += ((FC_ALU, true.B, "ALU")) val alu = Module(new ALUUnit(dataWidth = xLen)) alu.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_ALU) alu.io.req.bits := exe_int_req alu.io.resp.ready := true.B alu.io.brupdate := io_brupdate alu.io.kill := io_kill val io_alu_resp = IO(Output(Valid(new ExeUnitResp(xLen)))) io_alu_resp.valid := alu.io.resp.valid io_alu_resp.bits := alu.io.resp.bits val io_brinfo = IO(Output(Valid(new BrResolutionInfo))) io_brinfo := alu.io.brinfo io_ready_fu_types := get_ready_fu_types() } class FPExeUnit(val hasFDiv: Boolean = false, val hasFpiu: Boolean = false)(implicit p: Parameters) extends ExecutionUnit("FP") with tile.HasFPUParameters with HasFrfReadPorts { val io_squash_iss = IO(Output(Bool())) io_squash_iss := ( (io_arb_frf_reqs(0).valid && !io_arb_frf_reqs(0).ready) \|\| (io_arb_frf_reqs(1).valid && !io_arb_frf_reqs(1).ready) \|\| (io_arb_frf_reqs(2).valid && !io_arb_frf_reqs(2).ready) ) when (io_squash_iss) { val will_replay = arb_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, arb_uop.bits) arb_uop.valid := will_replay arb_uop.bits := UpdateBrMask(io_brupdate, arb_uop.bits) arb_uop.bits.iw_p1_bypass_hint := false.B arb_uop.bits.iw_p2_bypass_hint := false.B arb_uop.bits.iw_p3_bypass_hint := false.B rrd_uop.valid := false.B } val exe_fp_req = Wire(new FuncUnitReq(xLen+1)) exe_fp_req.uop := exe_uop.bits exe_fp_req.rs1_data := exe_rs1_data exe_fp_req.rs2_data := exe_rs2_data exe_fp_req.rs3_data := exe_rs3_data exe_fp_req.pred_data := DontCare exe_fp_req.imm_data := DontCare exe_fp_req.ftq_info := DontCare val fpu = Module(new FPUUnit) fu_types += ((FC_FPU, true.B, "FPU")) fpu.io.req.valid := exe_uop.valid && ( exe_uop.bits.fu_code(FC_FPU) \|\| (if (hasFpiu) exe_uop.bits.fu_code(FC_F2I) else false.B) ) fpu.io.req.bits := exe_fp_req fpu.io.fcsr_rm := io_fcsr_rm fpu.io.brupdate := io_brupdate fpu.io.kill := io_kill fpu.io.resp.ready := true.B val io_wakeup = IO(Output(Valid(new Wakeup))) val fastWakeupLatency = dfmaLatency - 3 // Three stages WAKE-ISS-ARB require (fastWakeupLatency >= 0) val fast_wakeups = Wire(Vec(fastWakeupLatency + 1, Valid(new Wakeup))) fast_wakeups(0).valid := exe_uop.valid && exe_uop.bits.fu_code(FC_FPU) fast_wakeups(0).bits.uop := exe_uop.bits fast_wakeups(0).bits.speculative_mask := 0.U fast_wakeups(0).bits.rebusy := false.B fast_wakeups(0).bits.bypassable := true.B for (i <- 0 until fastWakeupLatency) { fast_wakeups(i+1) := RegNext(UpdateBrMask(io_brupdate, io_kill, fast_wakeups(i))) } io_wakeup := fast_wakeups(fastWakeupLatency) val io_fpu_resp = IO(Output(Valid(new ExeUnitResp(xLen+1)))) io_fpu_resp.valid := fpu.io.resp.valid && !fpu.io.resp.bits.uop.fu_code(FC_F2I) io_fpu_resp.bits := fpu.io.resp.bits val io_fdiv_resp = if (hasFDiv) { val fdivsqrt_ready = Wire(Bool()) fu_types += ((FC_FDV, fdivsqrt_ready, "FDiv")) val fdivsqrt = Module(new FDivSqrtUnit2) assert(!(fdivsqrt.io.req.valid && !fdivsqrt.io.req.ready)) fdivsqrt.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_FDV) fdivsqrt.io.req.bits := exe_fp_req fdivsqrt.io.brupdate := io_brupdate fdivsqrt.io.kill := io_kill fdivsqrt.io.fcsr_rm := io_fcsr_rm fdivsqrt_ready := (fdivsqrt.io.req.ready && !(exe_uop.valid && exe_uop.bits.fu_code(FC_FDV)) && !(rrd_uop.valid && rrd_uop.bits.fu_code(FC_FDV)) && !(arb_uop.valid && arb_uop.bits.fu_code(FC_FDV)) ) val fdiv_resp = IO(Decoupled(new ExeUnitResp(xLen+1))) fdiv_resp <> fdivsqrt.io.resp Some(fdiv_resp) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_FDV))) None } val (io_fpiu_resp, io_dgen) = if (hasFpiu) { val fpiu_ready = Wire(Bool()) fu_types += ((FC_F2I, fpiu_ready, "Fpiu")) val queue = Module(new BranchKillableQueue(new ExeUnitResp(xLen+1), entries = dfmaLatency + 6)) // TODO being overly conservative fpiu_ready := RegNext(queue.io.count < 2.U) queue.io.enq.valid := ( fpu.io.resp.valid && fpu.io.resp.bits.uop.fu_code(FC_F2I) && !fpu.io.resp.bits.uop.uses_stq) // STA means store data gen for floating point queue.io.enq.bits := fpu.io.resp.bits queue.io.brupdate := io_brupdate queue.io.flush := io_kill assert(!(queue.io.enq.valid && !queue.io.enq.ready)) val fpiu_resp = IO(Decoupled(new ExeUnitResp(xLen))) fpiu_resp <> queue.io.deq val dgen = IO(Valid(new MemGen)) dgen.valid := RegNext(exe_uop.valid && exe_uop.bits.uses_stq && !IsKilledByBranch(io_brupdate, io_kill, exe_uop.bits)) dgen.bits.uop := RegNext(exe_uop.bits) dgen.bits.data := RegNext(ieee(exe_rs2_data)) (Some(fpiu_resp), Some(dgen)) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_F2I))) (None, None) } io_ready_fu_types := get_ready_fu_types }	module ALUExeUnit_1( // @[execution-unit.scala:492:7] input clock, // @[execution-unit.scala:492:7] input reset, // @[execution-unit.scala:492:7] input io_kill, // @[execution-unit.scala:79:19] input [11:0] io_brupdate_b1_resolve_mask, // @[execution-unit.scala:80:23] input [11:0] io_brupdate_b1_mispredict_mask, // @[execution-unit.scala:80:23] input [31:0] io_brupdate_b2_uop_inst, // @[execution-unit.scala:80:23] input [31:0] io_brupdate_b2_uop_debug_inst, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_rvc, // @[execution-unit.scala:80:23] input [39:0] io_brupdate_b2_uop_debug_pc, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iq_type_0, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iq_type_1, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iq_type_2, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iq_type_3, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_0, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_1, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_2, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_3, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_4, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_5, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_6, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_7, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_8, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_9, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_issued, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[execution-unit.scala:80:23] input [11:0] io_brupdate_b2_uop_br_mask, // @[execution-unit.scala:80:23] input [3:0] io_brupdate_b2_uop_br_tag, // @[execution-unit.scala:80:23] input [3:0] io_brupdate_b2_uop_br_type, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_sfb, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_fence, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_fencei, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_sfence, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_amo, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_eret, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_sys_pc2epc, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_rocc, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_mov, // @[execution-unit.scala:80:23] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_edge_inst, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_pc_lob, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_taken, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_imm_rename, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_imm_sel, // @[execution-unit.scala:80:23] input [4:0] io_brupdate_b2_uop_pimm, // @[execution-unit.scala:80:23] input [19:0] io_brupdate_b2_uop_imm_packed, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_op1_sel, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_op2_sel, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_wen, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_toint, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_fma, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_div, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_vec, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_rob_idx, // @[execution-unit.scala:80:23] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[execution-unit.scala:80:23] input [3:0] io_brupdate_b2_uop_stq_idx, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[execution-unit.scala:80:23] input [6:0] io_brupdate_b2_uop_pdst, // @[execution-unit.scala:80:23] input [6:0] io_brupdate_b2_uop_prs1, // @[execution-unit.scala:80:23] input [6:0] io_brupdate_b2_uop_prs2, // @[execution-unit.scala:80:23] input [6:0] io_brupdate_b2_uop_prs3, // @[execution-unit.scala:80:23] input [4:0] io_brupdate_b2_uop_ppred, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_prs1_busy, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_prs2_busy, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_prs3_busy, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_ppred_busy, // @[execution-unit.scala:80:23] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_exception, // @[execution-unit.scala:80:23] input [63:0] io_brupdate_b2_uop_exc_cause, // @[execution-unit.scala:80:23] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_mem_size, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_mem_signed, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_uses_ldq, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_uses_stq, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_unique, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_flush_on_commit, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_ldst_is_rs1, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_ldst, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_lrs1, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_lrs2, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_lrs3, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_frs3_en, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fcn_dw, // @[execution-unit.scala:80:23] input [4:0] io_brupdate_b2_uop_fcn_op, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_val, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_fp_rm, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_fp_typ, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_xcpt_pf_if, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_xcpt_ae_if, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_xcpt_ma_if, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_bp_debug_if, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_bp_xcpt_if, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[execution-unit.scala:80:23] input io_brupdate_b2_mispredict, // @[execution-unit.scala:80:23] input io_brupdate_b2_taken, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_cfi_type, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_pc_sel, // @[execution-unit.scala:80:23] input [39:0] io_brupdate_b2_jalr_target, // @[execution-unit.scala:80:23] input [20:0] io_brupdate_b2_target_offset, // @[execution-unit.scala:80:23] input io_status_debug, // @[execution-unit.scala:81:21] input io_status_cease, // @[execution-unit.scala:81:21] input io_status_wfi, // @[execution-unit.scala:81:21] input [1:0] io_status_dprv, // @[execution-unit.scala:81:21] input io_status_dv, // @[execution-unit.scala:81:21] input [1:0] io_status_prv, // @[execution-unit.scala:81:21] input io_status_v, // @[execution-unit.scala:81:21] input io_status_sd, // @[execution-unit.scala:81:21] input io_status_mpv, // @[execution-unit.scala:81:21] input io_status_gva, // @[execution-unit.scala:81:21] input io_status_tsr, // @[execution-unit.scala:81:21] input io_status_tw, // @[execution-unit.scala:81:21] input io_status_tvm, // @[execution-unit.scala:81:21] input io_status_mxr, // @[execution-unit.scala:81:21] input io_status_sum, // @[execution-unit.scala:81:21] input io_status_mprv, // @[execution-unit.scala:81:21] input [1:0] io_status_fs, // @[execution-unit.scala:81:21] input [1:0] io_status_mpp, // @[execution-unit.scala:81:21] input io_status_spp, // @[execution-unit.scala:81:21] input io_status_mpie, // @[execution-unit.scala:81:21] input io_status_spie, // @[execution-unit.scala:81:21] input io_status_mie, // @[execution-unit.scala:81:21] input io_status_sie, // @[execution-unit.scala:81:21] input [2:0] io_fcsr_rm, // @[execution-unit.scala:84:22] input io_iss_uop_valid, // @[execution-unit.scala:90:22] input [31:0] io_iss_uop_bits_inst, // @[execution-unit.scala:90:22] input [31:0] io_iss_uop_bits_debug_inst, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_rvc, // @[execution-unit.scala:90:22] input [39:0] io_iss_uop_bits_debug_pc, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iq_type_0, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iq_type_1, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iq_type_2, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iq_type_3, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_0, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_1, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_2, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_3, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_4, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_5, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_6, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_7, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_8, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_9, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iw_issued, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_iw_p1_speculative_child, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_iw_p2_speculative_child, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iw_p1_bypass_hint, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iw_p2_bypass_hint, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iw_p3_bypass_hint, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_dis_col_sel, // @[execution-unit.scala:90:22] input [11:0] io_iss_uop_bits_br_mask, // @[execution-unit.scala:90:22] input [3:0] io_iss_uop_bits_br_tag, // @[execution-unit.scala:90:22] input [3:0] io_iss_uop_bits_br_type, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_sfb, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_fence, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_fencei, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_sfence, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_amo, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_eret, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_sys_pc2epc, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_rocc, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_mov, // @[execution-unit.scala:90:22] input [4:0] io_iss_uop_bits_ftq_idx, // @[execution-unit.scala:90:22] input io_iss_uop_bits_edge_inst, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_pc_lob, // @[execution-unit.scala:90:22] input io_iss_uop_bits_taken, // @[execution-unit.scala:90:22] input io_iss_uop_bits_imm_rename, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_imm_sel, // @[execution-unit.scala:90:22] input [4:0] io_iss_uop_bits_pimm, // @[execution-unit.scala:90:22] input [19:0] io_iss_uop_bits_imm_packed, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_op1_sel, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_op2_sel, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_ldst, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_wen, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_ren1, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_ren2, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_ren3, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_swap12, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_swap23, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_fp_ctrl_typeTagIn, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_fp_ctrl_typeTagOut, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_fromint, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_toint, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_fastpipe, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_fma, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_div, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_sqrt, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_wflags, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_vec, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_rob_idx, // @[execution-unit.scala:90:22] input [3:0] io_iss_uop_bits_ldq_idx, // @[execution-unit.scala:90:22] input [3:0] io_iss_uop_bits_stq_idx, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_rxq_idx, // @[execution-unit.scala:90:22] input [6:0] io_iss_uop_bits_pdst, // @[execution-unit.scala:90:22] input [6:0] io_iss_uop_bits_prs1, // @[execution-unit.scala:90:22] input [6:0] io_iss_uop_bits_prs2, // @[execution-unit.scala:90:22] input [6:0] io_iss_uop_bits_prs3, // @[execution-unit.scala:90:22] input [4:0] io_iss_uop_bits_ppred, // @[execution-unit.scala:90:22] input io_iss_uop_bits_prs1_busy, // @[execution-unit.scala:90:22] input io_iss_uop_bits_prs2_busy, // @[execution-unit.scala:90:22] input io_iss_uop_bits_prs3_busy, // @[execution-unit.scala:90:22] input io_iss_uop_bits_ppred_busy, // @[execution-unit.scala:90:22] input [6:0] io_iss_uop_bits_stale_pdst, // @[execution-unit.scala:90:22] input io_iss_uop_bits_exception, // @[execution-unit.scala:90:22] input [63:0] io_iss_uop_bits_exc_cause, // @[execution-unit.scala:90:22] input [4:0] io_iss_uop_bits_mem_cmd, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_mem_size, // @[execution-unit.scala:90:22] input io_iss_uop_bits_mem_signed, // @[execution-unit.scala:90:22] input io_iss_uop_bits_uses_ldq, // @[execution-unit.scala:90:22] input io_iss_uop_bits_uses_stq, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_unique, // @[execution-unit.scala:90:22] input io_iss_uop_bits_flush_on_commit, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_csr_cmd, // @[execution-unit.scala:90:22] input io_iss_uop_bits_ldst_is_rs1, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_ldst, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_lrs1, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_lrs2, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_lrs3, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_dst_rtype, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_lrs1_rtype, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_lrs2_rtype, // @[execution-unit.scala:90:22] input io_iss_uop_bits_frs3_en, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fcn_dw, // @[execution-unit.scala:90:22] input [4:0] io_iss_uop_bits_fcn_op, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_val, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_fp_rm, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_fp_typ, // @[execution-unit.scala:90:22] input io_iss_uop_bits_xcpt_pf_if, // @[execution-unit.scala:90:22] input io_iss_uop_bits_xcpt_ae_if, // @[execution-unit.scala:90:22] input io_iss_uop_bits_xcpt_ma_if, // @[execution-unit.scala:90:22] input io_iss_uop_bits_bp_debug_if, // @[execution-unit.scala:90:22] input io_iss_uop_bits_bp_xcpt_if, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_debug_fsrc, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_debug_tsrc, // @[execution-unit.scala:90:22] input io_arb_irf_reqs_0_ready, // @[execution-unit.scala:106:27] output io_arb_irf_reqs_0_valid, // @[execution-unit.scala:106:27] output [6:0] io_arb_irf_reqs_0_bits, // @[execution-unit.scala:106:27] input io_arb_irf_reqs_1_ready, // @[execution-unit.scala:106:27] output io_arb_irf_reqs_1_valid, // @[execution-unit.scala:106:27] output [6:0] io_arb_irf_reqs_1_bits, // @[execution-unit.scala:106:27] input io_arb_rebusys_0_valid, // @[execution-unit.scala:107:27] input [31:0] io_arb_rebusys_0_bits_uop_inst, // @[execution-unit.scala:107:27] input [31:0] io_arb_rebusys_0_bits_uop_debug_inst, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_rvc, // @[execution-unit.scala:107:27] input [39:0] io_arb_rebusys_0_bits_uop_debug_pc, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iq_type_0, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iq_type_1, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iq_type_2, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iq_type_3, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_0, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_1, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_2, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_3, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_4, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_5, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_6, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_7, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_8, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_9, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_issued, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_dis_col_sel, // @[execution-unit.scala:107:27] input [11:0] io_arb_rebusys_0_bits_uop_br_mask, // @[execution-unit.scala:107:27] input [3:0] io_arb_rebusys_0_bits_uop_br_tag, // @[execution-unit.scala:107:27] input [3:0] io_arb_rebusys_0_bits_uop_br_type, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_sfb, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_fence, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_fencei, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_sfence, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_amo, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_eret, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_rocc, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_mov, // @[execution-unit.scala:107:27] input [4:0] io_arb_rebusys_0_bits_uop_ftq_idx, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_edge_inst, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_pc_lob, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_taken, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_imm_rename, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_imm_sel, // @[execution-unit.scala:107:27] input [4:0] io_arb_rebusys_0_bits_uop_pimm, // @[execution-unit.scala:107:27] input [19:0] io_arb_rebusys_0_bits_uop_imm_packed, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_op1_sel, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_op2_sel, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_div, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_rob_idx, // @[execution-unit.scala:107:27] input [3:0] io_arb_rebusys_0_bits_uop_ldq_idx, // @[execution-unit.scala:107:27] input [3:0] io_arb_rebusys_0_bits_uop_stq_idx, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_rxq_idx, // @[execution-unit.scala:107:27] input [6:0] io_arb_rebusys_0_bits_uop_pdst, // @[execution-unit.scala:107:27] input [6:0] io_arb_rebusys_0_bits_uop_prs1, // @[execution-unit.scala:107:27] input [6:0] io_arb_rebusys_0_bits_uop_prs2, // @[execution-unit.scala:107:27] input [6:0] io_arb_rebusys_0_bits_uop_prs3, // @[execution-unit.scala:107:27] input [4:0] io_arb_rebusys_0_bits_uop_ppred, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_prs1_busy, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_prs2_busy, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_prs3_busy, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_ppred_busy, // @[execution-unit.scala:107:27] input [6:0] io_arb_rebusys_0_bits_uop_stale_pdst, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_exception, // @[execution-unit.scala:107:27] input [63:0] io_arb_rebusys_0_bits_uop_exc_cause, // @[execution-unit.scala:107:27] input [4:0] io_arb_rebusys_0_bits_uop_mem_cmd, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_mem_size, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_mem_signed, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_uses_ldq, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_uses_stq, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_unique, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_flush_on_commit, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_csr_cmd, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_ldst, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_lrs1, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_lrs2, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_lrs3, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_dst_rtype, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_frs3_en, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fcn_dw, // @[execution-unit.scala:107:27] input [4:0] io_arb_rebusys_0_bits_uop_fcn_op, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_val, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_fp_rm, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_fp_typ, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_bp_debug_if, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_debug_fsrc, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_debug_tsrc, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_bypassable, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_speculative_mask, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_rebusy, // @[execution-unit.scala:107:27] input [63:0] io_rrd_irf_resps_0, // @[execution-unit.scala:108:31] input [63:0] io_rrd_irf_resps_1, // @[execution-unit.scala:108:31] input io_rrd_irf_bypasses_0_valid, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_0_bits_uop_inst, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_0_bits_uop_debug_inst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_rvc, // @[execution-unit.scala:109:31] input [39:0] io_rrd_irf_bypasses_0_bits_uop_debug_pc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iq_type_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iq_type_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iq_type_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iq_type_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_4, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_5, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_6, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_7, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_8, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_9, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_issued, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31] input [11:0] io_rrd_irf_bypasses_0_bits_uop_br_mask, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_0_bits_uop_br_tag, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_0_bits_uop_br_type, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_sfb, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_fence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_fencei, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_sfence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_amo, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_eret, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_rocc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_mov, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_uop_ftq_idx, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_edge_inst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_pc_lob, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_taken, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_imm_rename, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_imm_sel, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_uop_pimm, // @[execution-unit.scala:109:31] input [19:0] io_rrd_irf_bypasses_0_bits_uop_imm_packed, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_op1_sel, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_op2_sel, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_rob_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_0_bits_uop_ldq_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_0_bits_uop_stq_idx, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_rxq_idx, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_0_bits_uop_pdst, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_0_bits_uop_prs1, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_0_bits_uop_prs2, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_0_bits_uop_prs3, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_uop_ppred, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_prs1_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_prs2_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_prs3_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_ppred_busy, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_0_bits_uop_stale_pdst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_exception, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_0_bits_uop_exc_cause, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_uop_mem_cmd, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_mem_size, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_mem_signed, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_uses_ldq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_uses_stq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_unique, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_csr_cmd, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_ldst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_lrs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_lrs2, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_lrs3, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_dst_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_frs3_en, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fcn_dw, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_uop_fcn_op, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_val, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_fp_rm, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_fp_typ, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_0_bits_data, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_predicated, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_fflags_valid, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_fflags_bits, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_valid, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_1_bits_uop_inst, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_1_bits_uop_debug_inst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_rvc, // @[execution-unit.scala:109:31] input [39:0] io_rrd_irf_bypasses_1_bits_uop_debug_pc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iq_type_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iq_type_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iq_type_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iq_type_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_4, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_5, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_6, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_7, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_8, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_9, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_issued, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31] input [11:0] io_rrd_irf_bypasses_1_bits_uop_br_mask, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_1_bits_uop_br_tag, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_1_bits_uop_br_type, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_sfb, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_fence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_fencei, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_sfence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_amo, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_eret, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_rocc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_mov, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_1_bits_uop_ftq_idx, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_edge_inst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_pc_lob, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_taken, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_imm_rename, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_imm_sel, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_1_bits_uop_pimm, // @[execution-unit.scala:109:31] input [19:0] io_rrd_irf_bypasses_1_bits_uop_imm_packed, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_op1_sel, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_op2_sel, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_rob_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_1_bits_uop_ldq_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_1_bits_uop_stq_idx, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_rxq_idx, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_1_bits_uop_pdst, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_1_bits_uop_prs1, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_1_bits_uop_prs2, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_1_bits_uop_prs3, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_1_bits_uop_ppred, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_prs1_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_prs2_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_prs3_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_ppred_busy, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_1_bits_uop_stale_pdst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_exception, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_1_bits_uop_exc_cause, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_1_bits_uop_mem_cmd, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_mem_size, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_mem_signed, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_uses_ldq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_uses_stq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_unique, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_csr_cmd, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_ldst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_lrs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_lrs2, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_lrs3, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_dst_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_frs3_en, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fcn_dw, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_1_bits_uop_fcn_op, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_val, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_fp_rm, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_fp_typ, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_1_bits_data, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_predicated, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_valid, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_2_bits_uop_inst, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_2_bits_uop_debug_inst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_rvc, // @[execution-unit.scala:109:31] input [39:0] io_rrd_irf_bypasses_2_bits_uop_debug_pc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iq_type_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iq_type_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iq_type_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iq_type_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_4, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_5, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_6, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_7, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_8, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_9, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_issued, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31] input [11:0] io_rrd_irf_bypasses_2_bits_uop_br_mask, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_2_bits_uop_br_tag, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_2_bits_uop_br_type, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_sfb, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_fence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_fencei, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_sfence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_amo, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_eret, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_rocc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_mov, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_2_bits_uop_ftq_idx, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_edge_inst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_pc_lob, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_taken, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_imm_rename, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_imm_sel, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_2_bits_uop_pimm, // @[execution-unit.scala:109:31] input [19:0] io_rrd_irf_bypasses_2_bits_uop_imm_packed, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_op1_sel, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_op2_sel, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_rob_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_2_bits_uop_ldq_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_2_bits_uop_stq_idx, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_rxq_idx, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_2_bits_uop_pdst, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_2_bits_uop_prs1, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_2_bits_uop_prs2, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_2_bits_uop_prs3, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_2_bits_uop_ppred, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_prs1_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_prs2_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_prs3_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_ppred_busy, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_2_bits_uop_stale_pdst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_exception, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_2_bits_uop_exc_cause, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_2_bits_uop_mem_cmd, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_mem_size, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_mem_signed, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_uses_ldq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_uses_stq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_unique, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_csr_cmd, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_ldst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_lrs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_lrs2, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_lrs3, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_dst_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_frs3_en, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fcn_dw, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_2_bits_uop_fcn_op, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_val, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_fp_rm, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_fp_typ, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_2_bits_data, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_predicated, // @[execution-unit.scala:109:31] output io_arb_prf_req_valid, // @[execution-unit.scala:179:29] output [4:0] io_arb_prf_req_bits, // @[execution-unit.scala:179:29] input io_rrd_prf_resp, // @[execution-unit.scala:181:29] output io_arb_immrf_req_valid, // @[execution-unit.scala:151:31] output [4:0] io_arb_immrf_req_bits, // @[execution-unit.scala:151:31] input [63:0] io_rrd_immrf_resp, // @[execution-unit.scala:153:31] output io_rrd_immrf_wakeup_valid, // @[execution-unit.scala:154:31] output [31:0] io_rrd_immrf_wakeup_bits_uop_inst, // @[execution-unit.scala:154:31] output [31:0] io_rrd_immrf_wakeup_bits_uop_debug_inst, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_rvc, // @[execution-unit.scala:154:31] output [39:0] io_rrd_immrf_wakeup_bits_uop_debug_pc, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iq_type_0, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iq_type_1, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iq_type_2, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iq_type_3, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_0, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_1, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_2, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_3, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_4, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_5, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_6, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_7, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_8, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_9, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_issued, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_dis_col_sel, // @[execution-unit.scala:154:31] output [11:0] io_rrd_immrf_wakeup_bits_uop_br_mask, // @[execution-unit.scala:154:31] output [3:0] io_rrd_immrf_wakeup_bits_uop_br_tag, // @[execution-unit.scala:154:31] output [3:0] io_rrd_immrf_wakeup_bits_uop_br_type, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_sfb, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_fence, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_fencei, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_sfence, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_amo, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_eret, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_rocc, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_mov, // @[execution-unit.scala:154:31] output [4:0] io_rrd_immrf_wakeup_bits_uop_ftq_idx, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_edge_inst, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_pc_lob, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_taken, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_imm_rename, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_imm_sel, // @[execution-unit.scala:154:31] output [4:0] io_rrd_immrf_wakeup_bits_uop_pimm, // @[execution-unit.scala:154:31] output [19:0] io_rrd_immrf_wakeup_bits_uop_imm_packed, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_op1_sel, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_op2_sel, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_div, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_rob_idx, // @[execution-unit.scala:154:31] output [3:0] io_rrd_immrf_wakeup_bits_uop_ldq_idx, // @[execution-unit.scala:154:31] output [3:0] io_rrd_immrf_wakeup_bits_uop_stq_idx, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_rxq_idx, // @[execution-unit.scala:154:31] output [6:0] io_rrd_immrf_wakeup_bits_uop_pdst, // @[execution-unit.scala:154:31] output [6:0] io_rrd_immrf_wakeup_bits_uop_prs1, // @[execution-unit.scala:154:31] output [6:0] io_rrd_immrf_wakeup_bits_uop_prs2, // @[execution-unit.scala:154:31] output [6:0] io_rrd_immrf_wakeup_bits_uop_prs3, // @[execution-unit.scala:154:31] output [4:0] io_rrd_immrf_wakeup_bits_uop_ppred, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_prs1_busy, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_prs2_busy, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_prs3_busy, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_ppred_busy, // @[execution-unit.scala:154:31] output [6:0] io_rrd_immrf_wakeup_bits_uop_stale_pdst, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_exception, // @[execution-unit.scala:154:31] output [63:0] io_rrd_immrf_wakeup_bits_uop_exc_cause, // @[execution-unit.scala:154:31] output [4:0] io_rrd_immrf_wakeup_bits_uop_mem_cmd, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_mem_size, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_mem_signed, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_uses_ldq, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_uses_stq, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_unique, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_flush_on_commit, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_csr_cmd, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_ldst_is_rs1, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_ldst, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_lrs1, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_lrs2, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_lrs3, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_dst_rtype, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_lrs1_rtype, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_lrs2_rtype, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_frs3_en, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fcn_dw, // @[execution-unit.scala:154:31] output [4:0] io_rrd_immrf_wakeup_bits_uop_fcn_op, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_val, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_fp_rm, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_fp_typ, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_xcpt_pf_if, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_xcpt_ae_if, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_xcpt_ma_if, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_bp_debug_if, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_bp_xcpt_if, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_debug_fsrc, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_debug_tsrc, // @[execution-unit.scala:154:31] output io_arb_brf_req_valid, // @[execution-unit.scala:192:29] output [3:0] io_arb_brf_req_bits, // @[execution-unit.scala:192:29] input [3:0] io_rrd_brf_resp_ldq_idx, // @[execution-unit.scala:194:29] input [3:0] io_rrd_brf_resp_stq_idx, // @[execution-unit.scala:194:29] input [1:0] io_rrd_brf_resp_rxq_idx, // @[execution-unit.scala:194:29] input io_arb_ftq_reqs_0_ready, // @[execution-unit.scala:240:28] output io_arb_ftq_reqs_0_valid, // @[execution-unit.scala:240:28] output [4:0] io_arb_ftq_reqs_0_bits, // @[execution-unit.scala:240:28] input io_arb_ftq_reqs_1_ready, // @[execution-unit.scala:240:28] output io_arb_ftq_reqs_1_valid, // @[execution-unit.scala:240:28] output [4:0] io_arb_ftq_reqs_1_bits, // @[execution-unit.scala:240:28] input io_rrd_ftq_resps_0_valid, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_0_entry_cfi_idx_valid, // @[execution-unit.scala:241:28] input [1:0] io_rrd_ftq_resps_0_entry_cfi_idx_bits, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_0_entry_cfi_taken, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_0_entry_cfi_mispredicted, // @[execution-unit.scala:241:28] input [2:0] io_rrd_ftq_resps_0_entry_cfi_type, // @[execution-unit.scala:241:28] input [3:0] io_rrd_ftq_resps_0_entry_br_mask, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_0_entry_cfi_is_call, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_0_entry_cfi_is_ret, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_0_entry_cfi_npc_plus4, // @[execution-unit.scala:241:28] input [39:0] io_rrd_ftq_resps_0_entry_ras_top, // @[execution-unit.scala:241:28] input [4:0] io_rrd_ftq_resps_0_entry_ras_idx, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_0_entry_start_bank, // @[execution-unit.scala:241:28] input [39:0] io_rrd_ftq_resps_0_pc, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_valid, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_entry_cfi_idx_valid, // @[execution-unit.scala:241:28] input [1:0] io_rrd_ftq_resps_1_entry_cfi_idx_bits, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_entry_cfi_taken, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_entry_cfi_mispredicted, // @[execution-unit.scala:241:28] input [2:0] io_rrd_ftq_resps_1_entry_cfi_type, // @[execution-unit.scala:241:28] input [3:0] io_rrd_ftq_resps_1_entry_br_mask, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_entry_cfi_is_call, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_entry_cfi_is_ret, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_entry_cfi_npc_plus4, // @[execution-unit.scala:241:28] input [39:0] io_rrd_ftq_resps_1_entry_ras_top, // @[execution-unit.scala:241:28] input [4:0] io_rrd_ftq_resps_1_entry_ras_idx, // @[execution-unit.scala:241:28] input io_rrd_ftq_resps_1_entry_start_bank, // @[execution-unit.scala:241:28] input [39:0] io_rrd_ftq_resps_1_pc, // @[execution-unit.scala:241:28] output io_fast_wakeup_valid, // @[execution-unit.scala:503:26] output [31:0] io_fast_wakeup_bits_uop_inst, // @[execution-unit.scala:503:26] output [31:0] io_fast_wakeup_bits_uop_debug_inst, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_rvc, // @[execution-unit.scala:503:26] output [39:0] io_fast_wakeup_bits_uop_debug_pc, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iq_type_0, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iq_type_1, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iq_type_2, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iq_type_3, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_0, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_1, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_2, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_3, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_4, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_5, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_6, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_7, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_8, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fu_code_9, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iw_issued, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_dis_col_sel, // @[execution-unit.scala:503:26] output [11:0] io_fast_wakeup_bits_uop_br_mask, // @[execution-unit.scala:503:26] output [3:0] io_fast_wakeup_bits_uop_br_tag, // @[execution-unit.scala:503:26] output [3:0] io_fast_wakeup_bits_uop_br_type, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_sfb, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_fence, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_fencei, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_sfence, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_amo, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_eret, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_rocc, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_mov, // @[execution-unit.scala:503:26] output [4:0] io_fast_wakeup_bits_uop_ftq_idx, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_edge_inst, // @[execution-unit.scala:503:26] output [5:0] io_fast_wakeup_bits_uop_pc_lob, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_taken, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_imm_rename, // @[execution-unit.scala:503:26] output [2:0] io_fast_wakeup_bits_uop_imm_sel, // @[execution-unit.scala:503:26] output [4:0] io_fast_wakeup_bits_uop_pimm, // @[execution-unit.scala:503:26] output [19:0] io_fast_wakeup_bits_uop_imm_packed, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_op1_sel, // @[execution-unit.scala:503:26] output [2:0] io_fast_wakeup_bits_uop_op2_sel, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_div, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:503:26] output [5:0] io_fast_wakeup_bits_uop_rob_idx, // @[execution-unit.scala:503:26] output [3:0] io_fast_wakeup_bits_uop_ldq_idx, // @[execution-unit.scala:503:26] output [3:0] io_fast_wakeup_bits_uop_stq_idx, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_rxq_idx, // @[execution-unit.scala:503:26] output [6:0] io_fast_wakeup_bits_uop_pdst, // @[execution-unit.scala:503:26] output [6:0] io_fast_wakeup_bits_uop_prs1, // @[execution-unit.scala:503:26] output [6:0] io_fast_wakeup_bits_uop_prs2, // @[execution-unit.scala:503:26] output [6:0] io_fast_wakeup_bits_uop_prs3, // @[execution-unit.scala:503:26] output [4:0] io_fast_wakeup_bits_uop_ppred, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_prs1_busy, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_prs2_busy, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_prs3_busy, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_ppred_busy, // @[execution-unit.scala:503:26] output [6:0] io_fast_wakeup_bits_uop_stale_pdst, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_exception, // @[execution-unit.scala:503:26] output [63:0] io_fast_wakeup_bits_uop_exc_cause, // @[execution-unit.scala:503:26] output [4:0] io_fast_wakeup_bits_uop_mem_cmd, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_mem_size, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_mem_signed, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_uses_ldq, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_uses_stq, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_is_unique, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_flush_on_commit, // @[execution-unit.scala:503:26] output [2:0] io_fast_wakeup_bits_uop_csr_cmd, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_ldst_is_rs1, // @[execution-unit.scala:503:26] output [5:0] io_fast_wakeup_bits_uop_ldst, // @[execution-unit.scala:503:26] output [5:0] io_fast_wakeup_bits_uop_lrs1, // @[execution-unit.scala:503:26] output [5:0] io_fast_wakeup_bits_uop_lrs2, // @[execution-unit.scala:503:26] output [5:0] io_fast_wakeup_bits_uop_lrs3, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_dst_rtype, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_lrs1_rtype, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_lrs2_rtype, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_frs3_en, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fcn_dw, // @[execution-unit.scala:503:26] output [4:0] io_fast_wakeup_bits_uop_fcn_op, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_fp_val, // @[execution-unit.scala:503:26] output [2:0] io_fast_wakeup_bits_uop_fp_rm, // @[execution-unit.scala:503:26] output [1:0] io_fast_wakeup_bits_uop_fp_typ, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_xcpt_pf_if, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_xcpt_ae_if, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_xcpt_ma_if, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_bp_debug_if, // @[execution-unit.scala:503:26] output io_fast_wakeup_bits_uop_bp_xcpt_if, // @[execution-unit.scala:503:26] output [2:0] io_fast_wakeup_bits_uop_debug_fsrc, // @[execution-unit.scala:503:26] output [2:0] io_fast_wakeup_bits_uop_debug_tsrc, // @[execution-unit.scala:503:26] output io_fast_pred_wakeup_valid, // @[execution-unit.scala:513:31] output [31:0] io_fast_pred_wakeup_bits_uop_inst, // @[execution-unit.scala:513:31] output [31:0] io_fast_pred_wakeup_bits_uop_debug_inst, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_rvc, // @[execution-unit.scala:513:31] output [39:0] io_fast_pred_wakeup_bits_uop_debug_pc, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iq_type_0, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iq_type_1, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iq_type_2, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iq_type_3, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_0, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_1, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_2, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_3, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_4, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_5, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_6, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_7, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_8, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fu_code_9, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iw_issued, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_dis_col_sel, // @[execution-unit.scala:513:31] output [11:0] io_fast_pred_wakeup_bits_uop_br_mask, // @[execution-unit.scala:513:31] output [3:0] io_fast_pred_wakeup_bits_uop_br_tag, // @[execution-unit.scala:513:31] output [3:0] io_fast_pred_wakeup_bits_uop_br_type, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_sfb, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_fence, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_fencei, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_sfence, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_amo, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_eret, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_rocc, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_mov, // @[execution-unit.scala:513:31] output [4:0] io_fast_pred_wakeup_bits_uop_ftq_idx, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_edge_inst, // @[execution-unit.scala:513:31] output [5:0] io_fast_pred_wakeup_bits_uop_pc_lob, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_taken, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_imm_rename, // @[execution-unit.scala:513:31] output [2:0] io_fast_pred_wakeup_bits_uop_imm_sel, // @[execution-unit.scala:513:31] output [4:0] io_fast_pred_wakeup_bits_uop_pimm, // @[execution-unit.scala:513:31] output [19:0] io_fast_pred_wakeup_bits_uop_imm_packed, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_op1_sel, // @[execution-unit.scala:513:31] output [2:0] io_fast_pred_wakeup_bits_uop_op2_sel, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_div, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:513:31] output [5:0] io_fast_pred_wakeup_bits_uop_rob_idx, // @[execution-unit.scala:513:31] output [3:0] io_fast_pred_wakeup_bits_uop_ldq_idx, // @[execution-unit.scala:513:31] output [3:0] io_fast_pred_wakeup_bits_uop_stq_idx, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_rxq_idx, // @[execution-unit.scala:513:31] output [6:0] io_fast_pred_wakeup_bits_uop_pdst, // @[execution-unit.scala:513:31] output [6:0] io_fast_pred_wakeup_bits_uop_prs1, // @[execution-unit.scala:513:31] output [6:0] io_fast_pred_wakeup_bits_uop_prs2, // @[execution-unit.scala:513:31] output [6:0] io_fast_pred_wakeup_bits_uop_prs3, // @[execution-unit.scala:513:31] output [4:0] io_fast_pred_wakeup_bits_uop_ppred, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_prs1_busy, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_prs2_busy, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_prs3_busy, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_ppred_busy, // @[execution-unit.scala:513:31] output [6:0] io_fast_pred_wakeup_bits_uop_stale_pdst, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_exception, // @[execution-unit.scala:513:31] output [63:0] io_fast_pred_wakeup_bits_uop_exc_cause, // @[execution-unit.scala:513:31] output [4:0] io_fast_pred_wakeup_bits_uop_mem_cmd, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_mem_size, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_mem_signed, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_uses_ldq, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_uses_stq, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_is_unique, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_flush_on_commit, // @[execution-unit.scala:513:31] output [2:0] io_fast_pred_wakeup_bits_uop_csr_cmd, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_ldst_is_rs1, // @[execution-unit.scala:513:31] output [5:0] io_fast_pred_wakeup_bits_uop_ldst, // @[execution-unit.scala:513:31] output [5:0] io_fast_pred_wakeup_bits_uop_lrs1, // @[execution-unit.scala:513:31] output [5:0] io_fast_pred_wakeup_bits_uop_lrs2, // @[execution-unit.scala:513:31] output [5:0] io_fast_pred_wakeup_bits_uop_lrs3, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_dst_rtype, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_lrs1_rtype, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_lrs2_rtype, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_frs3_en, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fcn_dw, // @[execution-unit.scala:513:31] output [4:0] io_fast_pred_wakeup_bits_uop_fcn_op, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_fp_val, // @[execution-unit.scala:513:31] output [2:0] io_fast_pred_wakeup_bits_uop_fp_rm, // @[execution-unit.scala:513:31] output [1:0] io_fast_pred_wakeup_bits_uop_fp_typ, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_xcpt_pf_if, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_xcpt_ae_if, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_xcpt_ma_if, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_bp_debug_if, // @[execution-unit.scala:513:31] output io_fast_pred_wakeup_bits_uop_bp_xcpt_if, // @[execution-unit.scala:513:31] output [2:0] io_fast_pred_wakeup_bits_uop_debug_fsrc, // @[execution-unit.scala:513:31] output [2:0] io_fast_pred_wakeup_bits_uop_debug_tsrc, // @[execution-unit.scala:513:31] output io_squash_iss, // @[execution-unit.scala:521:25] output [1:0] io_child_rebusy, // @[execution-unit.scala:528:27] output io_alu_resp_valid, // @[execution-unit.scala:565:23] output [31:0] io_alu_resp_bits_uop_inst, // @[execution-unit.scala:565:23] output [31:0] io_alu_resp_bits_uop_debug_inst, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_rvc, // @[execution-unit.scala:565:23] output [39:0] io_alu_resp_bits_uop_debug_pc, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iq_type_0, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iq_type_1, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iq_type_2, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iq_type_3, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_0, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_1, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_2, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_3, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_4, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_5, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_6, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_7, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_8, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fu_code_9, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iw_issued, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_dis_col_sel, // @[execution-unit.scala:565:23] output [11:0] io_alu_resp_bits_uop_br_mask, // @[execution-unit.scala:565:23] output [3:0] io_alu_resp_bits_uop_br_tag, // @[execution-unit.scala:565:23] output [3:0] io_alu_resp_bits_uop_br_type, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_sfb, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_fence, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_fencei, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_sfence, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_amo, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_eret, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_rocc, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_mov, // @[execution-unit.scala:565:23] output [4:0] io_alu_resp_bits_uop_ftq_idx, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_edge_inst, // @[execution-unit.scala:565:23] output [5:0] io_alu_resp_bits_uop_pc_lob, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_taken, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_imm_rename, // @[execution-unit.scala:565:23] output [2:0] io_alu_resp_bits_uop_imm_sel, // @[execution-unit.scala:565:23] output [4:0] io_alu_resp_bits_uop_pimm, // @[execution-unit.scala:565:23] output [19:0] io_alu_resp_bits_uop_imm_packed, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_op1_sel, // @[execution-unit.scala:565:23] output [2:0] io_alu_resp_bits_uop_op2_sel, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_div, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:565:23] output [5:0] io_alu_resp_bits_uop_rob_idx, // @[execution-unit.scala:565:23] output [3:0] io_alu_resp_bits_uop_ldq_idx, // @[execution-unit.scala:565:23] output [3:0] io_alu_resp_bits_uop_stq_idx, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_rxq_idx, // @[execution-unit.scala:565:23] output [6:0] io_alu_resp_bits_uop_pdst, // @[execution-unit.scala:565:23] output [6:0] io_alu_resp_bits_uop_prs1, // @[execution-unit.scala:565:23] output [6:0] io_alu_resp_bits_uop_prs2, // @[execution-unit.scala:565:23] output [6:0] io_alu_resp_bits_uop_prs3, // @[execution-unit.scala:565:23] output [4:0] io_alu_resp_bits_uop_ppred, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_prs1_busy, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_prs2_busy, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_prs3_busy, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_ppred_busy, // @[execution-unit.scala:565:23] output [6:0] io_alu_resp_bits_uop_stale_pdst, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_exception, // @[execution-unit.scala:565:23] output [63:0] io_alu_resp_bits_uop_exc_cause, // @[execution-unit.scala:565:23] output [4:0] io_alu_resp_bits_uop_mem_cmd, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_mem_size, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_mem_signed, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_uses_ldq, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_uses_stq, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_is_unique, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_flush_on_commit, // @[execution-unit.scala:565:23] output [2:0] io_alu_resp_bits_uop_csr_cmd, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:565:23] output [5:0] io_alu_resp_bits_uop_ldst, // @[execution-unit.scala:565:23] output [5:0] io_alu_resp_bits_uop_lrs1, // @[execution-unit.scala:565:23] output [5:0] io_alu_resp_bits_uop_lrs2, // @[execution-unit.scala:565:23] output [5:0] io_alu_resp_bits_uop_lrs3, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_dst_rtype, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_lrs1_rtype, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_lrs2_rtype, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_frs3_en, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fcn_dw, // @[execution-unit.scala:565:23] output [4:0] io_alu_resp_bits_uop_fcn_op, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_fp_val, // @[execution-unit.scala:565:23] output [2:0] io_alu_resp_bits_uop_fp_rm, // @[execution-unit.scala:565:23] output [1:0] io_alu_resp_bits_uop_fp_typ, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_bp_debug_if, // @[execution-unit.scala:565:23] output io_alu_resp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:565:23] output [2:0] io_alu_resp_bits_uop_debug_fsrc, // @[execution-unit.scala:565:23] output [2:0] io_alu_resp_bits_uop_debug_tsrc, // @[execution-unit.scala:565:23] output [63:0] io_alu_resp_bits_data, // @[execution-unit.scala:565:23] output io_alu_resp_bits_predicated, // @[execution-unit.scala:565:23] output io_brinfo_valid, // @[execution-unit.scala:569:21] output [31:0] io_brinfo_bits_uop_inst, // @[execution-unit.scala:569:21] output [31:0] io_brinfo_bits_uop_debug_inst, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_rvc, // @[execution-unit.scala:569:21] output [39:0] io_brinfo_bits_uop_debug_pc, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iq_type_0, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iq_type_1, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iq_type_2, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iq_type_3, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_0, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_1, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_2, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_3, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_4, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_5, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_6, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_7, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_8, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fu_code_9, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iw_issued, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_dis_col_sel, // @[execution-unit.scala:569:21] output [11:0] io_brinfo_bits_uop_br_mask, // @[execution-unit.scala:569:21] output [3:0] io_brinfo_bits_uop_br_tag, // @[execution-unit.scala:569:21] output [3:0] io_brinfo_bits_uop_br_type, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_sfb, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_fence, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_fencei, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_sfence, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_amo, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_eret, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_rocc, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_mov, // @[execution-unit.scala:569:21] output [4:0] io_brinfo_bits_uop_ftq_idx, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_edge_inst, // @[execution-unit.scala:569:21] output [5:0] io_brinfo_bits_uop_pc_lob, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_taken, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_imm_rename, // @[execution-unit.scala:569:21] output [2:0] io_brinfo_bits_uop_imm_sel, // @[execution-unit.scala:569:21] output [4:0] io_brinfo_bits_uop_pimm, // @[execution-unit.scala:569:21] output [19:0] io_brinfo_bits_uop_imm_packed, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_op1_sel, // @[execution-unit.scala:569:21] output [2:0] io_brinfo_bits_uop_op2_sel, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_div, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:569:21] output [5:0] io_brinfo_bits_uop_rob_idx, // @[execution-unit.scala:569:21] output [3:0] io_brinfo_bits_uop_ldq_idx, // @[execution-unit.scala:569:21] output [3:0] io_brinfo_bits_uop_stq_idx, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_rxq_idx, // @[execution-unit.scala:569:21] output [6:0] io_brinfo_bits_uop_pdst, // @[execution-unit.scala:569:21] output [6:0] io_brinfo_bits_uop_prs1, // @[execution-unit.scala:569:21] output [6:0] io_brinfo_bits_uop_prs2, // @[execution-unit.scala:569:21] output [6:0] io_brinfo_bits_uop_prs3, // @[execution-unit.scala:569:21] output [4:0] io_brinfo_bits_uop_ppred, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_prs1_busy, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_prs2_busy, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_prs3_busy, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_ppred_busy, // @[execution-unit.scala:569:21] output [6:0] io_brinfo_bits_uop_stale_pdst, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_exception, // @[execution-unit.scala:569:21] output [63:0] io_brinfo_bits_uop_exc_cause, // @[execution-unit.scala:569:21] output [4:0] io_brinfo_bits_uop_mem_cmd, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_mem_size, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_mem_signed, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_uses_ldq, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_uses_stq, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_is_unique, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_flush_on_commit, // @[execution-unit.scala:569:21] output [2:0] io_brinfo_bits_uop_csr_cmd, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_ldst_is_rs1, // @[execution-unit.scala:569:21] output [5:0] io_brinfo_bits_uop_ldst, // @[execution-unit.scala:569:21] output [5:0] io_brinfo_bits_uop_lrs1, // @[execution-unit.scala:569:21] output [5:0] io_brinfo_bits_uop_lrs2, // @[execution-unit.scala:569:21] output [5:0] io_brinfo_bits_uop_lrs3, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_dst_rtype, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_lrs1_rtype, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_lrs2_rtype, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_frs3_en, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fcn_dw, // @[execution-unit.scala:569:21] output [4:0] io_brinfo_bits_uop_fcn_op, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_fp_val, // @[execution-unit.scala:569:21] output [2:0] io_brinfo_bits_uop_fp_rm, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_uop_fp_typ, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_xcpt_pf_if, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_xcpt_ae_if, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_xcpt_ma_if, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_bp_debug_if, // @[execution-unit.scala:569:21] output io_brinfo_bits_uop_bp_xcpt_if, // @[execution-unit.scala:569:21] output [2:0] io_brinfo_bits_uop_debug_fsrc, // @[execution-unit.scala:569:21] output [2:0] io_brinfo_bits_uop_debug_tsrc, // @[execution-unit.scala:569:21] output io_brinfo_bits_mispredict, // @[execution-unit.scala:569:21] output io_brinfo_bits_taken, // @[execution-unit.scala:569:21] output [2:0] io_brinfo_bits_cfi_type, // @[execution-unit.scala:569:21] output [1:0] io_brinfo_bits_pc_sel, // @[execution-unit.scala:569:21] output [39:0] io_brinfo_bits_jalr_target, // @[execution-unit.scala:569:21] output [20:0] io_brinfo_bits_target_offset // @[execution-unit.scala:569:21] ); wire [1:0] _io_child_rebusy_output; // @[execution-unit.scala:529:19, :530:40, :531:21] reg [2:0] rrd_uop_bits_debug_tsrc; // @[execution-unit.scala:95:20] reg [2:0] rrd_uop_bits_debug_fsrc; // @[execution-unit.scala:95:20] reg rrd_uop_bits_bp_xcpt_if; // @[execution-unit.scala:95:20] reg rrd_uop_bits_bp_debug_if; // @[execution-unit.scala:95:20] reg rrd_uop_bits_xcpt_ma_if; // @[execution-unit.scala:95:20] reg rrd_uop_bits_xcpt_ae_if; // @[execution-unit.scala:95:20] reg rrd_uop_bits_xcpt_pf_if; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_fp_typ; // @[execution-unit.scala:95:20] reg [2:0] rrd_uop_bits_fp_rm; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_val; // @[execution-unit.scala:95:20] reg [4:0] rrd_uop_bits_fcn_op; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fcn_dw; // @[execution-unit.scala:95:20] reg rrd_uop_bits_frs3_en; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_lrs2_rtype; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_lrs1_rtype; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_dst_rtype; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_lrs3; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_lrs2; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_lrs1; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_ldst; // @[execution-unit.scala:95:20] reg rrd_uop_bits_ldst_is_rs1; // @[execution-unit.scala:95:20] reg [2:0] rrd_uop_bits_csr_cmd; // @[execution-unit.scala:95:20] reg rrd_uop_bits_flush_on_commit; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_unique; // @[execution-unit.scala:95:20] reg rrd_uop_bits_uses_stq; // @[execution-unit.scala:95:20] reg rrd_uop_bits_uses_ldq; // @[execution-unit.scala:95:20] reg rrd_uop_bits_mem_signed; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_mem_size; // @[execution-unit.scala:95:20] reg [4:0] rrd_uop_bits_mem_cmd; // @[execution-unit.scala:95:20] reg [63:0] rrd_uop_bits_exc_cause; // @[execution-unit.scala:95:20] reg rrd_uop_bits_exception; // @[execution-unit.scala:95:20] reg [6:0] rrd_uop_bits_stale_pdst; // @[execution-unit.scala:95:20] reg rrd_uop_bits_ppred_busy; // @[execution-unit.scala:95:20] reg rrd_uop_bits_prs3_busy; // @[execution-unit.scala:95:20] reg rrd_uop_bits_prs2_busy; // @[execution-unit.scala:95:20] reg rrd_uop_bits_prs1_busy; // @[execution-unit.scala:95:20] reg [4:0] rrd_uop_bits_ppred; // @[execution-unit.scala:95:20] reg [6:0] rrd_uop_bits_prs3; // @[execution-unit.scala:95:20] reg [6:0] rrd_uop_bits_prs2; // @[execution-unit.scala:95:20] reg [6:0] rrd_uop_bits_prs1; // @[execution-unit.scala:95:20] reg [6:0] rrd_uop_bits_pdst; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_rxq_idx; // @[execution-unit.scala:95:20] reg [3:0] rrd_uop_bits_stq_idx; // @[execution-unit.scala:95:20] reg [3:0] rrd_uop_bits_ldq_idx; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_rob_idx; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_div; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:95:20] reg [2:0] rrd_uop_bits_op2_sel; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_op1_sel; // @[execution-unit.scala:95:20] reg [19:0] rrd_uop_bits_imm_packed; // @[execution-unit.scala:95:20] reg [4:0] rrd_uop_bits_pimm; // @[execution-unit.scala:95:20] reg [2:0] rrd_uop_bits_imm_sel; // @[execution-unit.scala:95:20] reg rrd_uop_bits_imm_rename; // @[execution-unit.scala:95:20] reg rrd_uop_bits_taken; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_pc_lob; // @[execution-unit.scala:95:20] reg rrd_uop_bits_edge_inst; // @[execution-unit.scala:95:20] reg [4:0] rrd_uop_bits_ftq_idx; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_mov; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_rocc; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_eret; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_amo; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_sfence; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_fencei; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_fence; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_sfb; // @[execution-unit.scala:95:20] reg [3:0] rrd_uop_bits_br_type; // @[execution-unit.scala:95:20] reg [3:0] rrd_uop_bits_br_tag; // @[execution-unit.scala:95:20] reg [11:0] rrd_uop_bits_br_mask; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_dis_col_sel; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_issued; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_9; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_8; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_7; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_6; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_5; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_4; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_3; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_2; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_1; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_0; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iq_type_3; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iq_type_2; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iq_type_1; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iq_type_0; // @[execution-unit.scala:95:20] reg [39:0] rrd_uop_bits_debug_pc; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_rvc; // @[execution-unit.scala:95:20] reg [31:0] rrd_uop_bits_debug_inst; // @[execution-unit.scala:95:20] reg [31:0] rrd_uop_bits_inst; // @[execution-unit.scala:95:20] wire _alu_io_resp_valid; // @[execution-unit.scala:558:19] wire [31:0] _alu_io_resp_bits_uop_inst; // @[execution-unit.scala:558:19] wire [31:0] _alu_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:558:19] wire [39:0] _alu_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iq_type_0; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iq_type_1; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iq_type_2; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iq_type_3; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_0; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_1; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_2; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_3; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_4; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_5; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_6; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_7; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_8; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fu_code_9; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iw_issued; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iw_issued_partial_agen; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iw_issued_partial_dgen; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_iw_p1_speculative_child; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_iw_p2_speculative_child; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iw_p1_bypass_hint; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iw_p2_bypass_hint; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_iw_p3_bypass_hint; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_dis_col_sel; // @[execution-unit.scala:558:19] wire [11:0] _alu_io_resp_bits_uop_br_mask; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_resp_bits_uop_br_tag; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_resp_bits_uop_br_type; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_fence; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_sfence; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_amo; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_eret; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_rocc; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_mov; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_taken; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_imm_rename; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_resp_bits_uop_imm_sel; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_resp_bits_uop_pimm; // @[execution-unit.scala:558:19] wire [19:0] _alu_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_op1_sel; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_resp_bits_uop_op2_sel; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_ldst; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_wen; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_ren1; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_ren2; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_ren3; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_swap12; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_swap23; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_fromint; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_toint; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_fastpipe; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_fma; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_div; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_sqrt; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_wflags; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_ctrl_vec; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_resp_bits_uop_pdst; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_resp_bits_uop_prs1; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_resp_bits_uop_prs2; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_resp_bits_uop_prs3; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_resp_bits_uop_ppred; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_exception; // @[execution-unit.scala:558:19] wire [63:0] _alu_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_mem_size; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_is_unique; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_resp_bits_uop_csr_cmd; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_resp_bits_uop_ldst; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_resp_bits_uop_lrs1; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_resp_bits_uop_lrs2; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_resp_bits_uop_lrs3; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fcn_dw; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_resp_bits_uop_fcn_op; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_fp_val; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_resp_bits_uop_fp_rm; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_resp_bits_uop_fp_typ; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:558:19] wire [63:0] _alu_io_resp_bits_data; // @[execution-unit.scala:558:19] wire _alu_io_resp_bits_predicated; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_valid; // @[execution-unit.scala:558:19] wire [31:0] _alu_io_brinfo_bits_uop_inst; // @[execution-unit.scala:558:19] wire [31:0] _alu_io_brinfo_bits_uop_debug_inst; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_rvc; // @[execution-unit.scala:558:19] wire [39:0] _alu_io_brinfo_bits_uop_debug_pc; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iq_type_0; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iq_type_1; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iq_type_2; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iq_type_3; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_0; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_1; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_2; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_3; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_4; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_5; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_6; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_7; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_8; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fu_code_9; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iw_issued; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iw_issued_partial_agen; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iw_issued_partial_dgen; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_iw_p1_speculative_child; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_iw_p2_speculative_child; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iw_p1_bypass_hint; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iw_p2_bypass_hint; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_iw_p3_bypass_hint; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_dis_col_sel; // @[execution-unit.scala:558:19] wire [11:0] _alu_io_brinfo_bits_uop_br_mask; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_brinfo_bits_uop_br_tag; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_brinfo_bits_uop_br_type; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_sfb; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_fence; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_fencei; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_sfence; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_amo; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_eret; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_rocc; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_mov; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_brinfo_bits_uop_ftq_idx; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_edge_inst; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_brinfo_bits_uop_pc_lob; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_taken; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_imm_rename; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_brinfo_bits_uop_imm_sel; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_brinfo_bits_uop_pimm; // @[execution-unit.scala:558:19] wire [19:0] _alu_io_brinfo_bits_uop_imm_packed; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_op1_sel; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_brinfo_bits_uop_op2_sel; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_ldst; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_wen; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_ren1; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_ren2; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_ren3; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_swap12; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_swap23; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_fp_ctrl_typeTagIn; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_fp_ctrl_typeTagOut; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_fromint; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_toint; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_fastpipe; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_fma; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_div; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_sqrt; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_wflags; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_ctrl_vec; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_brinfo_bits_uop_rob_idx; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_brinfo_bits_uop_ldq_idx; // @[execution-unit.scala:558:19] wire [3:0] _alu_io_brinfo_bits_uop_stq_idx; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_rxq_idx; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_brinfo_bits_uop_pdst; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_brinfo_bits_uop_prs1; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_brinfo_bits_uop_prs2; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_brinfo_bits_uop_prs3; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_brinfo_bits_uop_ppred; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_prs1_busy; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_prs2_busy; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_prs3_busy; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_ppred_busy; // @[execution-unit.scala:558:19] wire [6:0] _alu_io_brinfo_bits_uop_stale_pdst; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_exception; // @[execution-unit.scala:558:19] wire [63:0] _alu_io_brinfo_bits_uop_exc_cause; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_brinfo_bits_uop_mem_cmd; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_mem_size; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_mem_signed; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_uses_ldq; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_uses_stq; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_is_unique; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_flush_on_commit; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_brinfo_bits_uop_csr_cmd; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_ldst_is_rs1; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_brinfo_bits_uop_ldst; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_brinfo_bits_uop_lrs1; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_brinfo_bits_uop_lrs2; // @[execution-unit.scala:558:19] wire [5:0] _alu_io_brinfo_bits_uop_lrs3; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_dst_rtype; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_lrs1_rtype; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_lrs2_rtype; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_frs3_en; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fcn_dw; // @[execution-unit.scala:558:19] wire [4:0] _alu_io_brinfo_bits_uop_fcn_op; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_fp_val; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_brinfo_bits_uop_fp_rm; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_uop_fp_typ; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_xcpt_pf_if; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_xcpt_ae_if; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_xcpt_ma_if; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_bp_debug_if; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_uop_bp_xcpt_if; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_brinfo_bits_uop_debug_fsrc; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_brinfo_bits_uop_debug_tsrc; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_mispredict; // @[execution-unit.scala:558:19] wire _alu_io_brinfo_bits_taken; // @[execution-unit.scala:558:19] wire [2:0] _alu_io_brinfo_bits_cfi_type; // @[execution-unit.scala:558:19] wire [1:0] _alu_io_brinfo_bits_pc_sel; // @[execution-unit.scala:558:19] wire [39:0] _alu_io_brinfo_bits_jalr_target; // @[execution-unit.scala:558:19] wire [20:0] _alu_io_brinfo_bits_target_offset; // @[execution-unit.scala:558:19] wire io_arb_irf_reqs_0_ready_0 = io_arb_irf_reqs_0_ready; // @[execution-unit.scala:492:7] wire io_arb_irf_reqs_1_ready_0 = io_arb_irf_reqs_1_ready; // @[execution-unit.scala:492:7] wire io_arb_ftq_reqs_0_ready_0 = io_arb_ftq_reqs_0_ready; // @[execution-unit.scala:492:7] wire io_arb_ftq_reqs_1_ready_0 = io_arb_ftq_reqs_1_ready; // @[execution-unit.scala:492:7] wire [31:0] arb_uop_bits_out_inst = io_iss_uop_bits_inst; // @[util.scala:104:23] wire [31:0] arb_uop_bits_out_debug_inst = io_iss_uop_bits_debug_inst; // @[util.scala:104:23] wire arb_uop_bits_out_is_rvc = io_iss_uop_bits_is_rvc; // @[util.scala:104:23] wire [39:0] arb_uop_bits_out_debug_pc = io_iss_uop_bits_debug_pc; // @[util.scala:104:23] wire arb_uop_bits_out_iq_type_0 = io_iss_uop_bits_iq_type_0; // @[util.scala:104:23] wire arb_uop_bits_out_iq_type_1 = io_iss_uop_bits_iq_type_1; // @[util.scala:104:23] wire arb_uop_bits_out_iq_type_2 = io_iss_uop_bits_iq_type_2; // @[util.scala:104:23] wire arb_uop_bits_out_iq_type_3 = io_iss_uop_bits_iq_type_3; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_0 = io_iss_uop_bits_fu_code_0; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_1 = io_iss_uop_bits_fu_code_1; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_2 = io_iss_uop_bits_fu_code_2; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_3 = io_iss_uop_bits_fu_code_3; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_4 = io_iss_uop_bits_fu_code_4; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_5 = io_iss_uop_bits_fu_code_5; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_6 = io_iss_uop_bits_fu_code_6; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_7 = io_iss_uop_bits_fu_code_7; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_8 = io_iss_uop_bits_fu_code_8; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_9 = io_iss_uop_bits_fu_code_9; // @[util.scala:104:23] wire arb_uop_bits_out_iw_issued = io_iss_uop_bits_iw_issued; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_iw_p1_speculative_child = io_iss_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_iw_p2_speculative_child = io_iss_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire arb_uop_bits_out_iw_p1_bypass_hint = io_iss_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire arb_uop_bits_out_iw_p2_bypass_hint = io_iss_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire arb_uop_bits_out_iw_p3_bypass_hint = io_iss_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_dis_col_sel = io_iss_uop_bits_dis_col_sel; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_br_tag = io_iss_uop_bits_br_tag; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_br_type = io_iss_uop_bits_br_type; // @[util.scala:104:23] wire arb_uop_bits_out_is_sfb = io_iss_uop_bits_is_sfb; // @[util.scala:104:23] wire arb_uop_bits_out_is_fence = io_iss_uop_bits_is_fence; // @[util.scala:104:23] wire arb_uop_bits_out_is_fencei = io_iss_uop_bits_is_fencei; // @[util.scala:104:23] wire arb_uop_bits_out_is_sfence = io_iss_uop_bits_is_sfence; // @[util.scala:104:23] wire arb_uop_bits_out_is_amo = io_iss_uop_bits_is_amo; // @[util.scala:104:23] wire arb_uop_bits_out_is_eret = io_iss_uop_bits_is_eret; // @[util.scala:104:23] wire arb_uop_bits_out_is_sys_pc2epc = io_iss_uop_bits_is_sys_pc2epc; // @[util.scala:104:23] wire arb_uop_bits_out_is_rocc = io_iss_uop_bits_is_rocc; // @[util.scala:104:23] wire arb_uop_bits_out_is_mov = io_iss_uop_bits_is_mov; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_ftq_idx = io_iss_uop_bits_ftq_idx; // @[util.scala:104:23] wire arb_uop_bits_out_edge_inst = io_iss_uop_bits_edge_inst; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_pc_lob = io_iss_uop_bits_pc_lob; // @[util.scala:104:23] wire arb_uop_bits_out_taken = io_iss_uop_bits_taken; // @[util.scala:104:23] wire arb_uop_bits_out_imm_rename = io_iss_uop_bits_imm_rename; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_imm_sel = io_iss_uop_bits_imm_sel; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_pimm = io_iss_uop_bits_pimm; // @[util.scala:104:23] wire [19:0] arb_uop_bits_out_imm_packed = io_iss_uop_bits_imm_packed; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_op1_sel = io_iss_uop_bits_op1_sel; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_op2_sel = io_iss_uop_bits_op2_sel; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_ldst = io_iss_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_wen = io_iss_uop_bits_fp_ctrl_wen; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_ren1 = io_iss_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_ren2 = io_iss_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_ren3 = io_iss_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_swap12 = io_iss_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_swap23 = io_iss_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_fp_ctrl_typeTagIn = io_iss_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_fp_ctrl_typeTagOut = io_iss_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_fromint = io_iss_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_toint = io_iss_uop_bits_fp_ctrl_toint; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_fastpipe = io_iss_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_fma = io_iss_uop_bits_fp_ctrl_fma; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_div = io_iss_uop_bits_fp_ctrl_div; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_sqrt = io_iss_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_wflags = io_iss_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_vec = io_iss_uop_bits_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_rob_idx = io_iss_uop_bits_rob_idx; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_ldq_idx = io_iss_uop_bits_ldq_idx; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_stq_idx = io_iss_uop_bits_stq_idx; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_rxq_idx = io_iss_uop_bits_rxq_idx; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_pdst = io_iss_uop_bits_pdst; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_prs1 = io_iss_uop_bits_prs1; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_prs2 = io_iss_uop_bits_prs2; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_prs3 = io_iss_uop_bits_prs3; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_ppred = io_iss_uop_bits_ppred; // @[util.scala:104:23] wire arb_uop_bits_out_prs1_busy = io_iss_uop_bits_prs1_busy; // @[util.scala:104:23] wire arb_uop_bits_out_prs2_busy = io_iss_uop_bits_prs2_busy; // @[util.scala:104:23] wire arb_uop_bits_out_prs3_busy = io_iss_uop_bits_prs3_busy; // @[util.scala:104:23] wire arb_uop_bits_out_ppred_busy = io_iss_uop_bits_ppred_busy; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_stale_pdst = io_iss_uop_bits_stale_pdst; // @[util.scala:104:23] wire arb_uop_bits_out_exception = io_iss_uop_bits_exception; // @[util.scala:104:23] wire [63:0] arb_uop_bits_out_exc_cause = io_iss_uop_bits_exc_cause; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_mem_cmd = io_iss_uop_bits_mem_cmd; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_mem_size = io_iss_uop_bits_mem_size; // @[util.scala:104:23] wire arb_uop_bits_out_mem_signed = io_iss_uop_bits_mem_signed; // @[util.scala:104:23] wire arb_uop_bits_out_uses_ldq = io_iss_uop_bits_uses_ldq; // @[util.scala:104:23] wire arb_uop_bits_out_uses_stq = io_iss_uop_bits_uses_stq; // @[util.scala:104:23] wire arb_uop_bits_out_is_unique = io_iss_uop_bits_is_unique; // @[util.scala:104:23] wire arb_uop_bits_out_flush_on_commit = io_iss_uop_bits_flush_on_commit; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_csr_cmd = io_iss_uop_bits_csr_cmd; // @[util.scala:104:23] wire arb_uop_bits_out_ldst_is_rs1 = io_iss_uop_bits_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_ldst = io_iss_uop_bits_ldst; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_lrs1 = io_iss_uop_bits_lrs1; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_lrs2 = io_iss_uop_bits_lrs2; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_lrs3 = io_iss_uop_bits_lrs3; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_dst_rtype = io_iss_uop_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_lrs1_rtype = io_iss_uop_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_lrs2_rtype = io_iss_uop_bits_lrs2_rtype; // @[util.scala:104:23] wire arb_uop_bits_out_frs3_en = io_iss_uop_bits_frs3_en; // @[util.scala:104:23] wire arb_uop_bits_out_fcn_dw = io_iss_uop_bits_fcn_dw; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_fcn_op = io_iss_uop_bits_fcn_op; // @[util.scala:104:23] wire arb_uop_bits_out_fp_val = io_iss_uop_bits_fp_val; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_fp_rm = io_iss_uop_bits_fp_rm; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_fp_typ = io_iss_uop_bits_fp_typ; // @[util.scala:104:23] wire arb_uop_bits_out_xcpt_pf_if = io_iss_uop_bits_xcpt_pf_if; // @[util.scala:104:23] wire arb_uop_bits_out_xcpt_ae_if = io_iss_uop_bits_xcpt_ae_if; // @[util.scala:104:23] wire arb_uop_bits_out_xcpt_ma_if = io_iss_uop_bits_xcpt_ma_if; // @[util.scala:104:23] wire arb_uop_bits_out_bp_debug_if = io_iss_uop_bits_bp_debug_if; // @[util.scala:104:23] wire arb_uop_bits_out_bp_xcpt_if = io_iss_uop_bits_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_debug_fsrc = io_iss_uop_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_debug_tsrc = io_iss_uop_bits_debug_tsrc; // @[util.scala:104:23] wire arb_uop_bits_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire arb_uop_bits_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire exe_int_req_ftq_info_0_ghist_current_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:547:25] wire exe_int_req_ftq_info_0_ghist_new_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:547:25] wire exe_int_req_ftq_info_0_ghist_new_saw_branch_taken = 1'h0; // @[execution-unit.scala:547:25] wire exe_int_req_ftq_info_1_ghist_current_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:547:25] wire exe_int_req_ftq_info_1_ghist_new_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:547:25] wire exe_int_req_ftq_info_1_ghist_new_saw_branch_taken = 1'h0; // @[execution-unit.scala:547:25] wire _r_WIRE_0 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_1 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_2 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_3 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_4 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_5 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_6 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_7 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_8 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_9 = 1'h0; // @[execution-unit.scala:74:29] wire r_1 = 1'h0; // @[execution-unit.scala:74:21] wire r_2 = 1'h0; // @[execution-unit.scala:74:21] wire r_3 = 1'h0; // @[execution-unit.scala:74:21] wire r_4 = 1'h0; // @[execution-unit.scala:74:21] wire r_5 = 1'h0; // @[execution-unit.scala:74:21] wire r_6 = 1'h0; // @[execution-unit.scala:74:21] wire r_7 = 1'h0; // @[execution-unit.scala:74:21] wire r_8 = 1'h0; // @[execution-unit.scala:74:21] wire r_9 = 1'h0; // @[execution-unit.scala:74:21] wire [4:0] exe_int_req_ftq_info_0_ghist_ras_idx = 5'h0; // @[execution-unit.scala:547:25] wire [4:0] exe_int_req_ftq_info_1_ghist_ras_idx = 5'h0; // @[execution-unit.scala:547:25] wire [63:0] exe_int_req_rs3_data = 64'h0; // @[execution-unit.scala:547:25] wire [63:0] exe_int_req_ftq_info_0_ghist_old_history = 64'h0; // @[execution-unit.scala:547:25] wire [63:0] exe_int_req_ftq_info_1_ghist_old_history = 64'h0; // @[execution-unit.scala:547:25] wire io_arb_prf_req_ready = 1'h1; // @[execution-unit.scala:492:7] wire io_arb_immrf_req_ready = 1'h1; // @[execution-unit.scala:492:7] wire io_arb_brf_req_ready = 1'h1; // @[execution-unit.scala:492:7] wire r_0 = 1'h1; // @[execution-unit.scala:74:21] wire _io_arb_irf_reqs_0_valid_T_3; // @[execution-unit.scala:121:83] wire _io_arb_irf_reqs_1_valid_T_3; // @[execution-unit.scala:125:85] wire _io_arb_immrf_req_valid_T_4; // @[execution-unit.scala:157:44] wire _io_arb_brf_req_valid_T_11; // @[execution-unit.scala:196:42] wire _io_arb_ftq_reqs_0_valid_T_5; // @[execution-unit.scala:244:45] wire _io_arb_ftq_reqs_1_valid_T_5; // @[execution-unit.scala:248:45] wire [4:0] _io_arb_ftq_reqs_1_bits_T_2; // @[util.scala:211:20] wire io_arb_irf_reqs_0_valid_0; // @[execution-unit.scala:492:7] wire [6:0] io_arb_irf_reqs_0_bits_0; // @[execution-unit.scala:492:7] wire io_arb_irf_reqs_1_valid_0; // @[execution-unit.scala:492:7] wire [6:0] io_arb_irf_reqs_1_bits_0; // @[execution-unit.scala:492:7] wire io_arb_prf_req_valid_0; // @[execution-unit.scala:492:7] wire [4:0] io_arb_prf_req_bits_0; // @[execution-unit.scala:492:7] wire io_arb_immrf_req_valid_0; // @[execution-unit.scala:492:7] wire [4:0] io_arb_immrf_req_bits_0; // @[execution-unit.scala:492:7] wire _io_rrd_immrf_wakeup_valid_T_4; // @[execution-unit.scala:162:47] wire io_arb_brf_req_valid_0; // @[execution-unit.scala:492:7] wire [3:0] io_arb_brf_req_bits_0; // @[execution-unit.scala:492:7] wire io_arb_ftq_reqs_0_valid_0; // @[execution-unit.scala:492:7] wire [4:0] io_arb_ftq_reqs_0_bits_0; // @[execution-unit.scala:492:7] wire io_arb_ftq_reqs_1_valid_0; // @[execution-unit.scala:492:7] wire [4:0] io_arb_ftq_reqs_1_bits_0; // @[execution-unit.scala:492:7] wire _io_fast_wakeup_valid_T_1; // @[execution-unit.scala:505:22] wire _io_fast_pred_wakeup_valid_T_3; // @[execution-unit.scala:514:49] wire _io_squash_iss_T_10; // @[execution-unit.scala:525:77] reg arb_uop_valid; // @[execution-unit.scala:92:20] assign io_arb_prf_req_valid_0 = arb_uop_valid; // @[execution-unit.scala:92:20, :492:7] reg [31:0] arb_uop_bits_inst; // @[execution-unit.scala:92:20] wire [31:0] rrd_uop_bits_out_inst = arb_uop_bits_inst; // @[util.scala:104:23] wire [31:0] arb_uop_bits_out_1_inst = arb_uop_bits_inst; // @[util.scala:104:23] reg [31:0] arb_uop_bits_debug_inst; // @[execution-unit.scala:92:20] wire [31:0] rrd_uop_bits_out_debug_inst = arb_uop_bits_debug_inst; // @[util.scala:104:23] wire [31:0] arb_uop_bits_out_1_debug_inst = arb_uop_bits_debug_inst; // @[util.scala:104:23] reg arb_uop_bits_is_rvc; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_rvc = arb_uop_bits_is_rvc; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_rvc = arb_uop_bits_is_rvc; // @[util.scala:104:23] reg [39:0] arb_uop_bits_debug_pc; // @[execution-unit.scala:92:20] wire [39:0] rrd_uop_bits_out_debug_pc = arb_uop_bits_debug_pc; // @[util.scala:104:23] wire [39:0] arb_uop_bits_out_1_debug_pc = arb_uop_bits_debug_pc; // @[util.scala:104:23] reg arb_uop_bits_iq_type_0; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iq_type_0 = arb_uop_bits_iq_type_0; // @[util.scala:104:23] wire arb_uop_bits_out_1_iq_type_0 = arb_uop_bits_iq_type_0; // @[util.scala:104:23] reg arb_uop_bits_iq_type_1; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iq_type_1 = arb_uop_bits_iq_type_1; // @[util.scala:104:23] wire arb_uop_bits_out_1_iq_type_1 = arb_uop_bits_iq_type_1; // @[util.scala:104:23] reg arb_uop_bits_iq_type_2; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iq_type_2 = arb_uop_bits_iq_type_2; // @[util.scala:104:23] wire arb_uop_bits_out_1_iq_type_2 = arb_uop_bits_iq_type_2; // @[util.scala:104:23] reg arb_uop_bits_iq_type_3; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iq_type_3 = arb_uop_bits_iq_type_3; // @[util.scala:104:23] wire arb_uop_bits_out_1_iq_type_3 = arb_uop_bits_iq_type_3; // @[util.scala:104:23] reg arb_uop_bits_fu_code_0; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_0 = arb_uop_bits_fu_code_0; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_0 = arb_uop_bits_fu_code_0; // @[util.scala:104:23] reg arb_uop_bits_fu_code_1; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_1 = arb_uop_bits_fu_code_1; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_1 = arb_uop_bits_fu_code_1; // @[util.scala:104:23] reg arb_uop_bits_fu_code_2; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_2 = arb_uop_bits_fu_code_2; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_2 = arb_uop_bits_fu_code_2; // @[util.scala:104:23] reg arb_uop_bits_fu_code_3; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_3 = arb_uop_bits_fu_code_3; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_3 = arb_uop_bits_fu_code_3; // @[util.scala:104:23] reg arb_uop_bits_fu_code_4; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_4 = arb_uop_bits_fu_code_4; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_4 = arb_uop_bits_fu_code_4; // @[util.scala:104:23] reg arb_uop_bits_fu_code_5; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_5 = arb_uop_bits_fu_code_5; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_5 = arb_uop_bits_fu_code_5; // @[util.scala:104:23] reg arb_uop_bits_fu_code_6; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_6 = arb_uop_bits_fu_code_6; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_6 = arb_uop_bits_fu_code_6; // @[util.scala:104:23] reg arb_uop_bits_fu_code_7; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_7 = arb_uop_bits_fu_code_7; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_7 = arb_uop_bits_fu_code_7; // @[util.scala:104:23] reg arb_uop_bits_fu_code_8; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_8 = arb_uop_bits_fu_code_8; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_8 = arb_uop_bits_fu_code_8; // @[util.scala:104:23] reg arb_uop_bits_fu_code_9; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_9 = arb_uop_bits_fu_code_9; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_9 = arb_uop_bits_fu_code_9; // @[util.scala:104:23] reg arb_uop_bits_iw_issued; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_issued = arb_uop_bits_iw_issued; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_issued = arb_uop_bits_iw_issued; // @[util.scala:104:23] reg arb_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_issued_partial_agen = arb_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_issued_partial_agen = arb_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23] reg arb_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_issued_partial_dgen = arb_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_issued_partial_dgen = arb_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23] reg [1:0] arb_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_iw_p1_speculative_child = arb_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_iw_p1_speculative_child = arb_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] arb_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_iw_p2_speculative_child = arb_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_iw_p2_speculative_child = arb_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23] reg arb_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_p1_bypass_hint = arb_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_p1_bypass_hint = arb_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23] reg arb_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_p2_bypass_hint = arb_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_p2_bypass_hint = arb_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23] reg arb_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_p3_bypass_hint = arb_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_p3_bypass_hint = arb_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] arb_uop_bits_dis_col_sel; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_dis_col_sel = arb_uop_bits_dis_col_sel; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_dis_col_sel = arb_uop_bits_dis_col_sel; // @[util.scala:104:23] reg [11:0] arb_uop_bits_br_mask; // @[execution-unit.scala:92:20] reg [3:0] arb_uop_bits_br_tag; // @[execution-unit.scala:92:20] assign io_arb_brf_req_bits_0 = arb_uop_bits_br_tag; // @[execution-unit.scala:92:20, :492:7] wire [3:0] rrd_uop_bits_out_br_tag = arb_uop_bits_br_tag; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_1_br_tag = arb_uop_bits_br_tag; // @[util.scala:104:23] reg [3:0] arb_uop_bits_br_type; // @[execution-unit.scala:92:20] wire [3:0] rrd_uop_bits_out_br_type = arb_uop_bits_br_type; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_1_br_type = arb_uop_bits_br_type; // @[util.scala:104:23] reg arb_uop_bits_is_sfb; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_sfb = arb_uop_bits_is_sfb; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_sfb = arb_uop_bits_is_sfb; // @[util.scala:104:23] reg arb_uop_bits_is_fence; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_fence = arb_uop_bits_is_fence; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_fence = arb_uop_bits_is_fence; // @[util.scala:104:23] reg arb_uop_bits_is_fencei; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_fencei = arb_uop_bits_is_fencei; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_fencei = arb_uop_bits_is_fencei; // @[util.scala:104:23] reg arb_uop_bits_is_sfence; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_sfence = arb_uop_bits_is_sfence; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_sfence = arb_uop_bits_is_sfence; // @[util.scala:104:23] reg arb_uop_bits_is_amo; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_amo = arb_uop_bits_is_amo; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_amo = arb_uop_bits_is_amo; // @[util.scala:104:23] reg arb_uop_bits_is_eret; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_eret = arb_uop_bits_is_eret; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_eret = arb_uop_bits_is_eret; // @[util.scala:104:23] reg arb_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_sys_pc2epc = arb_uop_bits_is_sys_pc2epc; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_sys_pc2epc = arb_uop_bits_is_sys_pc2epc; // @[util.scala:104:23] reg arb_uop_bits_is_rocc; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_rocc = arb_uop_bits_is_rocc; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_rocc = arb_uop_bits_is_rocc; // @[util.scala:104:23] reg arb_uop_bits_is_mov; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_mov = arb_uop_bits_is_mov; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_mov = arb_uop_bits_is_mov; // @[util.scala:104:23] reg [4:0] arb_uop_bits_ftq_idx; // @[execution-unit.scala:92:20] assign io_arb_ftq_reqs_0_bits_0 = arb_uop_bits_ftq_idx; // @[execution-unit.scala:92:20, :492:7] wire [4:0] rrd_uop_bits_out_ftq_idx = arb_uop_bits_ftq_idx; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_1_ftq_idx = arb_uop_bits_ftq_idx; // @[util.scala:104:23] reg arb_uop_bits_edge_inst; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_edge_inst = arb_uop_bits_edge_inst; // @[util.scala:104:23] wire arb_uop_bits_out_1_edge_inst = arb_uop_bits_edge_inst; // @[util.scala:104:23] reg [5:0] arb_uop_bits_pc_lob; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_pc_lob = arb_uop_bits_pc_lob; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_pc_lob = arb_uop_bits_pc_lob; // @[util.scala:104:23] reg arb_uop_bits_taken; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_taken = arb_uop_bits_taken; // @[util.scala:104:23] wire arb_uop_bits_out_1_taken = arb_uop_bits_taken; // @[util.scala:104:23] reg arb_uop_bits_imm_rename; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_imm_rename = arb_uop_bits_imm_rename; // @[util.scala:104:23] wire arb_uop_bits_out_1_imm_rename = arb_uop_bits_imm_rename; // @[util.scala:104:23] reg [2:0] arb_uop_bits_imm_sel; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_imm_sel = arb_uop_bits_imm_sel; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_imm_sel = arb_uop_bits_imm_sel; // @[util.scala:104:23] reg [4:0] arb_uop_bits_pimm; // @[execution-unit.scala:92:20] assign io_arb_immrf_req_bits_0 = arb_uop_bits_pimm; // @[execution-unit.scala:92:20, :492:7] wire [4:0] rrd_uop_bits_out_pimm = arb_uop_bits_pimm; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_1_pimm = arb_uop_bits_pimm; // @[util.scala:104:23] reg [19:0] arb_uop_bits_imm_packed; // @[execution-unit.scala:92:20] wire [19:0] rrd_uop_bits_out_imm_packed = arb_uop_bits_imm_packed; // @[util.scala:104:23] wire [19:0] arb_uop_bits_out_1_imm_packed = arb_uop_bits_imm_packed; // @[util.scala:104:23] reg [1:0] arb_uop_bits_op1_sel; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_op1_sel = arb_uop_bits_op1_sel; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_op1_sel = arb_uop_bits_op1_sel; // @[util.scala:104:23] reg [2:0] arb_uop_bits_op2_sel; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_op2_sel = arb_uop_bits_op2_sel; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_op2_sel = arb_uop_bits_op2_sel; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_ldst = arb_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_ldst = arb_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_wen = arb_uop_bits_fp_ctrl_wen; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_wen = arb_uop_bits_fp_ctrl_wen; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_ren1 = arb_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_ren1 = arb_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_ren2 = arb_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_ren2 = arb_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_ren3 = arb_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_ren3 = arb_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_swap12 = arb_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_swap12 = arb_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_swap23 = arb_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_swap23 = arb_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] arb_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_fp_ctrl_typeTagIn = arb_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_fp_ctrl_typeTagIn = arb_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] arb_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_fp_ctrl_typeTagOut = arb_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_fp_ctrl_typeTagOut = arb_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_fromint = arb_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_fromint = arb_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_toint = arb_uop_bits_fp_ctrl_toint; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_toint = arb_uop_bits_fp_ctrl_toint; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_fastpipe = arb_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_fastpipe = arb_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_fma = arb_uop_bits_fp_ctrl_fma; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_fma = arb_uop_bits_fp_ctrl_fma; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_div; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_div = arb_uop_bits_fp_ctrl_div; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_div = arb_uop_bits_fp_ctrl_div; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_sqrt = arb_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_sqrt = arb_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_wflags = arb_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_wflags = arb_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_vec = arb_uop_bits_fp_ctrl_vec; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_vec = arb_uop_bits_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] arb_uop_bits_rob_idx; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_rob_idx = arb_uop_bits_rob_idx; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_rob_idx = arb_uop_bits_rob_idx; // @[util.scala:104:23] reg [3:0] arb_uop_bits_ldq_idx; // @[execution-unit.scala:92:20] wire [3:0] rrd_uop_bits_out_ldq_idx = arb_uop_bits_ldq_idx; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_1_ldq_idx = arb_uop_bits_ldq_idx; // @[util.scala:104:23] reg [3:0] arb_uop_bits_stq_idx; // @[execution-unit.scala:92:20] wire [3:0] rrd_uop_bits_out_stq_idx = arb_uop_bits_stq_idx; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_1_stq_idx = arb_uop_bits_stq_idx; // @[util.scala:104:23] reg [1:0] arb_uop_bits_rxq_idx; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_rxq_idx = arb_uop_bits_rxq_idx; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_rxq_idx = arb_uop_bits_rxq_idx; // @[util.scala:104:23] reg [6:0] arb_uop_bits_pdst; // @[execution-unit.scala:92:20] wire [6:0] rrd_uop_bits_out_pdst = arb_uop_bits_pdst; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_1_pdst = arb_uop_bits_pdst; // @[util.scala:104:23] reg [6:0] arb_uop_bits_prs1; // @[execution-unit.scala:92:20] assign io_arb_irf_reqs_0_bits_0 = arb_uop_bits_prs1; // @[execution-unit.scala:92:20, :492:7] wire [6:0] rrd_uop_bits_out_prs1 = arb_uop_bits_prs1; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_1_prs1 = arb_uop_bits_prs1; // @[util.scala:104:23] reg [6:0] arb_uop_bits_prs2; // @[execution-unit.scala:92:20] assign io_arb_irf_reqs_1_bits_0 = arb_uop_bits_prs2; // @[execution-unit.scala:92:20, :492:7] wire [6:0] rrd_uop_bits_out_prs2 = arb_uop_bits_prs2; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_1_prs2 = arb_uop_bits_prs2; // @[util.scala:104:23] reg [6:0] arb_uop_bits_prs3; // @[execution-unit.scala:92:20] wire [6:0] rrd_uop_bits_out_prs3 = arb_uop_bits_prs3; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_1_prs3 = arb_uop_bits_prs3; // @[util.scala:104:23] reg [4:0] arb_uop_bits_ppred; // @[execution-unit.scala:92:20] assign io_arb_prf_req_bits_0 = arb_uop_bits_ppred; // @[execution-unit.scala:92:20, :492:7] wire [4:0] rrd_uop_bits_out_ppred = arb_uop_bits_ppred; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_1_ppred = arb_uop_bits_ppred; // @[util.scala:104:23] reg arb_uop_bits_prs1_busy; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_prs1_busy = arb_uop_bits_prs1_busy; // @[util.scala:104:23] wire arb_uop_bits_out_1_prs1_busy = arb_uop_bits_prs1_busy; // @[util.scala:104:23] reg arb_uop_bits_prs2_busy; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_prs2_busy = arb_uop_bits_prs2_busy; // @[util.scala:104:23] wire arb_uop_bits_out_1_prs2_busy = arb_uop_bits_prs2_busy; // @[util.scala:104:23] reg arb_uop_bits_prs3_busy; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_prs3_busy = arb_uop_bits_prs3_busy; // @[util.scala:104:23] wire arb_uop_bits_out_1_prs3_busy = arb_uop_bits_prs3_busy; // @[util.scala:104:23] reg arb_uop_bits_ppred_busy; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_ppred_busy = arb_uop_bits_ppred_busy; // @[util.scala:104:23] wire arb_uop_bits_out_1_ppred_busy = arb_uop_bits_ppred_busy; // @[util.scala:104:23] reg [6:0] arb_uop_bits_stale_pdst; // @[execution-unit.scala:92:20] wire [6:0] rrd_uop_bits_out_stale_pdst = arb_uop_bits_stale_pdst; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_1_stale_pdst = arb_uop_bits_stale_pdst; // @[util.scala:104:23] reg arb_uop_bits_exception; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_exception = arb_uop_bits_exception; // @[util.scala:104:23] wire arb_uop_bits_out_1_exception = arb_uop_bits_exception; // @[util.scala:104:23] reg [63:0] arb_uop_bits_exc_cause; // @[execution-unit.scala:92:20] wire [63:0] rrd_uop_bits_out_exc_cause = arb_uop_bits_exc_cause; // @[util.scala:104:23] wire [63:0] arb_uop_bits_out_1_exc_cause = arb_uop_bits_exc_cause; // @[util.scala:104:23] reg [4:0] arb_uop_bits_mem_cmd; // @[execution-unit.scala:92:20] wire [4:0] rrd_uop_bits_out_mem_cmd = arb_uop_bits_mem_cmd; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_1_mem_cmd = arb_uop_bits_mem_cmd; // @[util.scala:104:23] reg [1:0] arb_uop_bits_mem_size; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_mem_size = arb_uop_bits_mem_size; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_mem_size = arb_uop_bits_mem_size; // @[util.scala:104:23] reg arb_uop_bits_mem_signed; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_mem_signed = arb_uop_bits_mem_signed; // @[util.scala:104:23] wire arb_uop_bits_out_1_mem_signed = arb_uop_bits_mem_signed; // @[util.scala:104:23] reg arb_uop_bits_uses_ldq; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_uses_ldq = arb_uop_bits_uses_ldq; // @[util.scala:104:23] wire arb_uop_bits_out_1_uses_ldq = arb_uop_bits_uses_ldq; // @[util.scala:104:23] reg arb_uop_bits_uses_stq; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_uses_stq = arb_uop_bits_uses_stq; // @[util.scala:104:23] wire arb_uop_bits_out_1_uses_stq = arb_uop_bits_uses_stq; // @[util.scala:104:23] reg arb_uop_bits_is_unique; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_unique = arb_uop_bits_is_unique; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_unique = arb_uop_bits_is_unique; // @[util.scala:104:23] reg arb_uop_bits_flush_on_commit; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_flush_on_commit = arb_uop_bits_flush_on_commit; // @[util.scala:104:23] wire arb_uop_bits_out_1_flush_on_commit = arb_uop_bits_flush_on_commit; // @[util.scala:104:23] reg [2:0] arb_uop_bits_csr_cmd; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_csr_cmd = arb_uop_bits_csr_cmd; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_csr_cmd = arb_uop_bits_csr_cmd; // @[util.scala:104:23] reg arb_uop_bits_ldst_is_rs1; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_ldst_is_rs1 = arb_uop_bits_ldst_is_rs1; // @[util.scala:104:23] wire arb_uop_bits_out_1_ldst_is_rs1 = arb_uop_bits_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] arb_uop_bits_ldst; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_ldst = arb_uop_bits_ldst; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_ldst = arb_uop_bits_ldst; // @[util.scala:104:23] reg [5:0] arb_uop_bits_lrs1; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_lrs1 = arb_uop_bits_lrs1; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_lrs1 = arb_uop_bits_lrs1; // @[util.scala:104:23] reg [5:0] arb_uop_bits_lrs2; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_lrs2 = arb_uop_bits_lrs2; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_lrs2 = arb_uop_bits_lrs2; // @[util.scala:104:23] reg [5:0] arb_uop_bits_lrs3; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_lrs3 = arb_uop_bits_lrs3; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_lrs3 = arb_uop_bits_lrs3; // @[util.scala:104:23] reg [1:0] arb_uop_bits_dst_rtype; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_dst_rtype = arb_uop_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_dst_rtype = arb_uop_bits_dst_rtype; // @[util.scala:104:23] reg [1:0] arb_uop_bits_lrs1_rtype; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_lrs1_rtype = arb_uop_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_lrs1_rtype = arb_uop_bits_lrs1_rtype; // @[util.scala:104:23] reg [1:0] arb_uop_bits_lrs2_rtype; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_lrs2_rtype = arb_uop_bits_lrs2_rtype; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_lrs2_rtype = arb_uop_bits_lrs2_rtype; // @[util.scala:104:23] reg arb_uop_bits_frs3_en; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_frs3_en = arb_uop_bits_frs3_en; // @[util.scala:104:23] wire arb_uop_bits_out_1_frs3_en = arb_uop_bits_frs3_en; // @[util.scala:104:23] reg arb_uop_bits_fcn_dw; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fcn_dw = arb_uop_bits_fcn_dw; // @[util.scala:104:23] wire arb_uop_bits_out_1_fcn_dw = arb_uop_bits_fcn_dw; // @[util.scala:104:23] reg [4:0] arb_uop_bits_fcn_op; // @[execution-unit.scala:92:20] wire [4:0] rrd_uop_bits_out_fcn_op = arb_uop_bits_fcn_op; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_1_fcn_op = arb_uop_bits_fcn_op; // @[util.scala:104:23] reg arb_uop_bits_fp_val; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_val = arb_uop_bits_fp_val; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_val = arb_uop_bits_fp_val; // @[util.scala:104:23] reg [2:0] arb_uop_bits_fp_rm; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_fp_rm = arb_uop_bits_fp_rm; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_fp_rm = arb_uop_bits_fp_rm; // @[util.scala:104:23] reg [1:0] arb_uop_bits_fp_typ; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_fp_typ = arb_uop_bits_fp_typ; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_fp_typ = arb_uop_bits_fp_typ; // @[util.scala:104:23] reg arb_uop_bits_xcpt_pf_if; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_xcpt_pf_if = arb_uop_bits_xcpt_pf_if; // @[util.scala:104:23] wire arb_uop_bits_out_1_xcpt_pf_if = arb_uop_bits_xcpt_pf_if; // @[util.scala:104:23] reg arb_uop_bits_xcpt_ae_if; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_xcpt_ae_if = arb_uop_bits_xcpt_ae_if; // @[util.scala:104:23] wire arb_uop_bits_out_1_xcpt_ae_if = arb_uop_bits_xcpt_ae_if; // @[util.scala:104:23] reg arb_uop_bits_xcpt_ma_if; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_xcpt_ma_if = arb_uop_bits_xcpt_ma_if; // @[util.scala:104:23] wire arb_uop_bits_out_1_xcpt_ma_if = arb_uop_bits_xcpt_ma_if; // @[util.scala:104:23] reg arb_uop_bits_bp_debug_if; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_bp_debug_if = arb_uop_bits_bp_debug_if; // @[util.scala:104:23] wire arb_uop_bits_out_1_bp_debug_if = arb_uop_bits_bp_debug_if; // @[util.scala:104:23] reg arb_uop_bits_bp_xcpt_if; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_bp_xcpt_if = arb_uop_bits_bp_xcpt_if; // @[util.scala:104:23] wire arb_uop_bits_out_1_bp_xcpt_if = arb_uop_bits_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] arb_uop_bits_debug_fsrc; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_debug_fsrc = arb_uop_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_debug_fsrc = arb_uop_bits_debug_fsrc; // @[util.scala:104:23] reg [2:0] arb_uop_bits_debug_tsrc; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_debug_tsrc = arb_uop_bits_debug_tsrc; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_debug_tsrc = arb_uop_bits_debug_tsrc; // @[util.scala:104:23] wire [11:0] _arb_uop_valid_T = io_brupdate_b1_mispredict_mask & io_iss_uop_bits_br_mask; // @[util.scala:126:51] wire _arb_uop_valid_T_1 = \|_arb_uop_valid_T; // @[util.scala:126:{51,59}] wire _arb_uop_valid_T_2 = _arb_uop_valid_T_1 \| io_kill; // @[util.scala:61:61, :126:59] wire _arb_uop_valid_T_3 = ~_arb_uop_valid_T_2; // @[util.scala:61:61] wire _arb_uop_valid_T_4 = io_iss_uop_valid & _arb_uop_valid_T_3; // @[execution-unit.scala:93:{37,40}] wire [11:0] _arb_uop_bits_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] arb_uop_bits_out_br_mask; // @[util.scala:104:23] wire [11:0] _arb_uop_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27] assign _arb_uop_bits_out_br_mask_T_1 = io_iss_uop_bits_br_mask & _arb_uop_bits_out_br_mask_T; // @[util.scala:93:{25,27}] assign arb_uop_bits_out_br_mask = _arb_uop_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg rrd_uop_valid; // @[execution-unit.scala:95:20] wire [31:0] exe_uop_bits_out_inst = rrd_uop_bits_inst; // @[util.scala:104:23] wire [31:0] exe_uop_bits_out_debug_inst = rrd_uop_bits_debug_inst; // @[util.scala:104:23] wire exe_uop_bits_out_is_rvc = rrd_uop_bits_is_rvc; // @[util.scala:104:23] wire [39:0] exe_uop_bits_out_debug_pc = rrd_uop_bits_debug_pc; // @[util.scala:104:23] wire exe_uop_bits_out_iq_type_0 = rrd_uop_bits_iq_type_0; // @[util.scala:104:23] wire exe_uop_bits_out_iq_type_1 = rrd_uop_bits_iq_type_1; // @[util.scala:104:23] wire exe_uop_bits_out_iq_type_2 = rrd_uop_bits_iq_type_2; // @[util.scala:104:23] wire exe_uop_bits_out_iq_type_3 = rrd_uop_bits_iq_type_3; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_0 = rrd_uop_bits_fu_code_0; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_1 = rrd_uop_bits_fu_code_1; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_2 = rrd_uop_bits_fu_code_2; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_3 = rrd_uop_bits_fu_code_3; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_4 = rrd_uop_bits_fu_code_4; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_5 = rrd_uop_bits_fu_code_5; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_6 = rrd_uop_bits_fu_code_6; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_7 = rrd_uop_bits_fu_code_7; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_8 = rrd_uop_bits_fu_code_8; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_9 = rrd_uop_bits_fu_code_9; // @[util.scala:104:23] wire exe_uop_bits_out_iw_issued = rrd_uop_bits_iw_issued; // @[util.scala:104:23] wire exe_uop_bits_out_iw_issued_partial_agen = rrd_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire exe_uop_bits_out_iw_issued_partial_dgen = rrd_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_iw_p1_speculative_child = rrd_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_iw_p2_speculative_child = rrd_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire exe_uop_bits_out_iw_p1_bypass_hint = rrd_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire exe_uop_bits_out_iw_p2_bypass_hint = rrd_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire exe_uop_bits_out_iw_p3_bypass_hint = rrd_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_dis_col_sel = rrd_uop_bits_dis_col_sel; // @[util.scala:104:23] wire [3:0] exe_uop_bits_out_br_tag = rrd_uop_bits_br_tag; // @[util.scala:104:23] wire [3:0] exe_uop_bits_out_br_type = rrd_uop_bits_br_type; // @[util.scala:104:23] wire exe_uop_bits_out_is_sfb = rrd_uop_bits_is_sfb; // @[util.scala:104:23] wire exe_uop_bits_out_is_fence = rrd_uop_bits_is_fence; // @[util.scala:104:23] wire exe_uop_bits_out_is_fencei = rrd_uop_bits_is_fencei; // @[util.scala:104:23] wire exe_uop_bits_out_is_sfence = rrd_uop_bits_is_sfence; // @[util.scala:104:23] wire exe_uop_bits_out_is_amo = rrd_uop_bits_is_amo; // @[util.scala:104:23] wire exe_uop_bits_out_is_eret = rrd_uop_bits_is_eret; // @[util.scala:104:23] wire exe_uop_bits_out_is_sys_pc2epc = rrd_uop_bits_is_sys_pc2epc; // @[util.scala:104:23] wire exe_uop_bits_out_is_rocc = rrd_uop_bits_is_rocc; // @[util.scala:104:23] wire exe_uop_bits_out_is_mov = rrd_uop_bits_is_mov; // @[util.scala:104:23] wire [4:0] exe_uop_bits_out_ftq_idx = rrd_uop_bits_ftq_idx; // @[util.scala:104:23] wire exe_uop_bits_out_edge_inst = rrd_uop_bits_edge_inst; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_pc_lob = rrd_uop_bits_pc_lob; // @[util.scala:104:23] wire exe_uop_bits_out_taken = rrd_uop_bits_taken; // @[util.scala:104:23] wire exe_uop_bits_out_imm_rename = rrd_uop_bits_imm_rename; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_imm_sel = rrd_uop_bits_imm_sel; // @[util.scala:104:23] wire [4:0] exe_uop_bits_out_pimm = rrd_uop_bits_pimm; // @[util.scala:104:23] wire [19:0] exe_uop_bits_out_imm_packed = rrd_uop_bits_imm_packed; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_op1_sel = rrd_uop_bits_op1_sel; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_op2_sel = rrd_uop_bits_op2_sel; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_ldst = rrd_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_wen = rrd_uop_bits_fp_ctrl_wen; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_ren1 = rrd_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_ren2 = rrd_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_ren3 = rrd_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_swap12 = rrd_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_swap23 = rrd_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_fp_ctrl_typeTagIn = rrd_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_fp_ctrl_typeTagOut = rrd_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_fromint = rrd_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_toint = rrd_uop_bits_fp_ctrl_toint; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_fastpipe = rrd_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_fma = rrd_uop_bits_fp_ctrl_fma; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_div = rrd_uop_bits_fp_ctrl_div; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_sqrt = rrd_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_wflags = rrd_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_vec = rrd_uop_bits_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_rob_idx = rrd_uop_bits_rob_idx; // @[util.scala:104:23] wire [3:0] exe_uop_bits_out_ldq_idx = rrd_uop_bits_ldq_idx; // @[util.scala:104:23] wire [3:0] exe_uop_bits_out_stq_idx = rrd_uop_bits_stq_idx; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_rxq_idx = rrd_uop_bits_rxq_idx; // @[util.scala:104:23] wire [6:0] exe_uop_bits_out_pdst = rrd_uop_bits_pdst; // @[util.scala:104:23] wire [6:0] exe_uop_bits_out_prs1 = rrd_uop_bits_prs1; // @[util.scala:104:23] wire [6:0] exe_uop_bits_out_prs2 = rrd_uop_bits_prs2; // @[util.scala:104:23] wire [6:0] exe_uop_bits_out_prs3 = rrd_uop_bits_prs3; // @[util.scala:104:23] wire [4:0] exe_uop_bits_out_ppred = rrd_uop_bits_ppred; // @[util.scala:104:23] wire exe_uop_bits_out_prs1_busy = rrd_uop_bits_prs1_busy; // @[util.scala:104:23] wire exe_uop_bits_out_prs2_busy = rrd_uop_bits_prs2_busy; // @[util.scala:104:23] wire exe_uop_bits_out_prs3_busy = rrd_uop_bits_prs3_busy; // @[util.scala:104:23] wire exe_uop_bits_out_ppred_busy = rrd_uop_bits_ppred_busy; // @[util.scala:104:23] wire [6:0] exe_uop_bits_out_stale_pdst = rrd_uop_bits_stale_pdst; // @[util.scala:104:23] wire exe_uop_bits_out_exception = rrd_uop_bits_exception; // @[util.scala:104:23] wire [63:0] exe_uop_bits_out_exc_cause = rrd_uop_bits_exc_cause; // @[util.scala:104:23] wire [4:0] exe_uop_bits_out_mem_cmd = rrd_uop_bits_mem_cmd; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_mem_size = rrd_uop_bits_mem_size; // @[util.scala:104:23] wire exe_uop_bits_out_mem_signed = rrd_uop_bits_mem_signed; // @[util.scala:104:23] wire exe_uop_bits_out_uses_ldq = rrd_uop_bits_uses_ldq; // @[util.scala:104:23] wire exe_uop_bits_out_uses_stq = rrd_uop_bits_uses_stq; // @[util.scala:104:23] wire exe_uop_bits_out_is_unique = rrd_uop_bits_is_unique; // @[util.scala:104:23] wire exe_uop_bits_out_flush_on_commit = rrd_uop_bits_flush_on_commit; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_csr_cmd = rrd_uop_bits_csr_cmd; // @[util.scala:104:23] wire exe_uop_bits_out_ldst_is_rs1 = rrd_uop_bits_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_ldst = rrd_uop_bits_ldst; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_lrs1 = rrd_uop_bits_lrs1; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_lrs2 = rrd_uop_bits_lrs2; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_lrs3 = rrd_uop_bits_lrs3; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_dst_rtype = rrd_uop_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_lrs1_rtype = rrd_uop_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_lrs2_rtype = rrd_uop_bits_lrs2_rtype; // @[util.scala:104:23] wire exe_uop_bits_out_frs3_en = rrd_uop_bits_frs3_en; // @[util.scala:104:23] wire exe_uop_bits_out_fcn_dw = rrd_uop_bits_fcn_dw; // @[util.scala:104:23] wire [4:0] exe_uop_bits_out_fcn_op = rrd_uop_bits_fcn_op; // @[util.scala:104:23] wire exe_uop_bits_out_fp_val = rrd_uop_bits_fp_val; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_fp_rm = rrd_uop_bits_fp_rm; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_fp_typ = rrd_uop_bits_fp_typ; // @[util.scala:104:23] wire exe_uop_bits_out_xcpt_pf_if = rrd_uop_bits_xcpt_pf_if; // @[util.scala:104:23] wire exe_uop_bits_out_xcpt_ae_if = rrd_uop_bits_xcpt_ae_if; // @[util.scala:104:23] wire exe_uop_bits_out_xcpt_ma_if = rrd_uop_bits_xcpt_ma_if; // @[util.scala:104:23] wire exe_uop_bits_out_bp_debug_if = rrd_uop_bits_bp_debug_if; // @[util.scala:104:23] wire exe_uop_bits_out_bp_xcpt_if = rrd_uop_bits_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_debug_fsrc = rrd_uop_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_debug_tsrc = rrd_uop_bits_debug_tsrc; // @[util.scala:104:23] wire [11:0] _GEN = io_brupdate_b1_mispredict_mask & arb_uop_bits_br_mask; // @[util.scala:126:51] wire [11:0] _rrd_uop_valid_T; // @[util.scala:126:51] assign _rrd_uop_valid_T = _GEN; // @[util.scala:126:51] wire [11:0] _will_replay_T; // @[util.scala:126:51] assign _will_replay_T = _GEN; // @[util.scala:126:51] wire _rrd_uop_valid_T_1 = \|_rrd_uop_valid_T; // @[util.scala:126:{51,59}] wire _rrd_uop_valid_T_2 = _rrd_uop_valid_T_1 \| io_kill; // @[util.scala:61:61, :126:59] wire _rrd_uop_valid_T_3 = ~_rrd_uop_valid_T_2; // @[util.scala:61:61] wire _rrd_uop_valid_T_4 = arb_uop_valid & _rrd_uop_valid_T_3; // @[execution-unit.scala:92:20, :96:{34,37}] wire [11:0] _rrd_uop_bits_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] rrd_uop_bits_out_br_mask; // @[util.scala:104:23] wire [11:0] _rrd_uop_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27] assign _rrd_uop_bits_out_br_mask_T_1 = arb_uop_bits_br_mask & _rrd_uop_bits_out_br_mask_T; // @[util.scala:93:{25,27}] assign rrd_uop_bits_out_br_mask = _rrd_uop_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg exe_uop_valid; // @[execution-unit.scala:98:20] reg [31:0] exe_uop_bits_inst; // @[execution-unit.scala:98:20] wire [31:0] exe_int_req_uop_inst = exe_uop_bits_inst; // @[execution-unit.scala:98:20, :547:25] reg [31:0] exe_uop_bits_debug_inst; // @[execution-unit.scala:98:20] wire [31:0] exe_int_req_uop_debug_inst = exe_uop_bits_debug_inst; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_rvc; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_rvc = exe_uop_bits_is_rvc; // @[execution-unit.scala:98:20, :547:25] reg [39:0] exe_uop_bits_debug_pc; // @[execution-unit.scala:98:20] wire [39:0] exe_int_req_uop_debug_pc = exe_uop_bits_debug_pc; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iq_type_0; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iq_type_0 = exe_uop_bits_iq_type_0; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iq_type_1; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iq_type_1 = exe_uop_bits_iq_type_1; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iq_type_2; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iq_type_2 = exe_uop_bits_iq_type_2; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iq_type_3; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iq_type_3 = exe_uop_bits_iq_type_3; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_0; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_0 = exe_uop_bits_fu_code_0; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_1; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_1 = exe_uop_bits_fu_code_1; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_2; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_2 = exe_uop_bits_fu_code_2; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_3; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_3 = exe_uop_bits_fu_code_3; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_4; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_4 = exe_uop_bits_fu_code_4; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_5; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_5 = exe_uop_bits_fu_code_5; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_6; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_6 = exe_uop_bits_fu_code_6; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_7; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_7 = exe_uop_bits_fu_code_7; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_8; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_8 = exe_uop_bits_fu_code_8; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fu_code_9; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_9 = exe_uop_bits_fu_code_9; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iw_issued; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_issued = exe_uop_bits_iw_issued; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_issued_partial_agen = exe_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_issued_partial_dgen = exe_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_iw_p1_speculative_child = exe_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_iw_p2_speculative_child = exe_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_p1_bypass_hint = exe_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_p2_bypass_hint = exe_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_p3_bypass_hint = exe_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_dis_col_sel; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_dis_col_sel = exe_uop_bits_dis_col_sel; // @[execution-unit.scala:98:20, :547:25] reg [11:0] exe_uop_bits_br_mask; // @[execution-unit.scala:98:20] wire [11:0] exe_int_req_uop_br_mask = exe_uop_bits_br_mask; // @[execution-unit.scala:98:20, :547:25] reg [3:0] exe_uop_bits_br_tag; // @[execution-unit.scala:98:20] wire [3:0] exe_int_req_uop_br_tag = exe_uop_bits_br_tag; // @[execution-unit.scala:98:20, :547:25] reg [3:0] exe_uop_bits_br_type; // @[execution-unit.scala:98:20] wire [3:0] exe_int_req_uop_br_type = exe_uop_bits_br_type; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_sfb; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_sfb = exe_uop_bits_is_sfb; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_fence; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_fence = exe_uop_bits_is_fence; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_fencei; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_fencei = exe_uop_bits_is_fencei; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_sfence; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_sfence = exe_uop_bits_is_sfence; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_amo; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_amo = exe_uop_bits_is_amo; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_eret; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_eret = exe_uop_bits_is_eret; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_sys_pc2epc = exe_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_rocc; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_rocc = exe_uop_bits_is_rocc; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_mov; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_mov = exe_uop_bits_is_mov; // @[execution-unit.scala:98:20, :547:25] reg [4:0] exe_uop_bits_ftq_idx; // @[execution-unit.scala:98:20] wire [4:0] exe_int_req_uop_ftq_idx = exe_uop_bits_ftq_idx; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_edge_inst; // @[execution-unit.scala:98:20] wire exe_int_req_uop_edge_inst = exe_uop_bits_edge_inst; // @[execution-unit.scala:98:20, :547:25] reg [5:0] exe_uop_bits_pc_lob; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_pc_lob = exe_uop_bits_pc_lob; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_taken; // @[execution-unit.scala:98:20] wire exe_int_req_uop_taken = exe_uop_bits_taken; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_imm_rename; // @[execution-unit.scala:98:20] wire exe_int_req_uop_imm_rename = exe_uop_bits_imm_rename; // @[execution-unit.scala:98:20, :547:25] reg [2:0] exe_uop_bits_imm_sel; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_imm_sel = exe_uop_bits_imm_sel; // @[execution-unit.scala:98:20, :547:25] reg [4:0] exe_uop_bits_pimm; // @[execution-unit.scala:98:20] wire [4:0] exe_int_req_uop_pimm = exe_uop_bits_pimm; // @[execution-unit.scala:98:20, :547:25] reg [19:0] exe_uop_bits_imm_packed; // @[execution-unit.scala:98:20] wire [19:0] exe_int_req_uop_imm_packed = exe_uop_bits_imm_packed; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_op1_sel; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_op1_sel = exe_uop_bits_op1_sel; // @[execution-unit.scala:98:20, :547:25] reg [2:0] exe_uop_bits_op2_sel; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_op2_sel = exe_uop_bits_op2_sel; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_ldst = exe_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_wen = exe_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_ren1 = exe_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_ren2 = exe_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_ren3 = exe_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_swap12 = exe_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_swap23 = exe_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_fp_ctrl_typeTagIn = exe_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_fp_ctrl_typeTagOut = exe_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_fromint = exe_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_toint = exe_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_fastpipe = exe_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_fma = exe_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_div; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_div = exe_uop_bits_fp_ctrl_div; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_sqrt = exe_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_wflags = exe_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_vec = exe_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:98:20, :547:25] reg [5:0] exe_uop_bits_rob_idx; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_rob_idx = exe_uop_bits_rob_idx; // @[execution-unit.scala:98:20, :547:25] reg [3:0] exe_uop_bits_ldq_idx; // @[execution-unit.scala:98:20] wire [3:0] exe_int_req_uop_ldq_idx = exe_uop_bits_ldq_idx; // @[execution-unit.scala:98:20, :547:25] reg [3:0] exe_uop_bits_stq_idx; // @[execution-unit.scala:98:20] wire [3:0] exe_int_req_uop_stq_idx = exe_uop_bits_stq_idx; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_rxq_idx; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_rxq_idx = exe_uop_bits_rxq_idx; // @[execution-unit.scala:98:20, :547:25] reg [6:0] exe_uop_bits_pdst; // @[execution-unit.scala:98:20] wire [6:0] exe_int_req_uop_pdst = exe_uop_bits_pdst; // @[execution-unit.scala:98:20, :547:25] reg [6:0] exe_uop_bits_prs1; // @[execution-unit.scala:98:20] wire [6:0] exe_int_req_uop_prs1 = exe_uop_bits_prs1; // @[execution-unit.scala:98:20, :547:25] reg [6:0] exe_uop_bits_prs2; // @[execution-unit.scala:98:20] wire [6:0] exe_int_req_uop_prs2 = exe_uop_bits_prs2; // @[execution-unit.scala:98:20, :547:25] reg [6:0] exe_uop_bits_prs3; // @[execution-unit.scala:98:20] wire [6:0] exe_int_req_uop_prs3 = exe_uop_bits_prs3; // @[execution-unit.scala:98:20, :547:25] reg [4:0] exe_uop_bits_ppred; // @[execution-unit.scala:98:20] wire [4:0] exe_int_req_uop_ppred = exe_uop_bits_ppred; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_prs1_busy; // @[execution-unit.scala:98:20] wire exe_int_req_uop_prs1_busy = exe_uop_bits_prs1_busy; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_prs2_busy; // @[execution-unit.scala:98:20] wire exe_int_req_uop_prs2_busy = exe_uop_bits_prs2_busy; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_prs3_busy; // @[execution-unit.scala:98:20] wire exe_int_req_uop_prs3_busy = exe_uop_bits_prs3_busy; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_ppred_busy; // @[execution-unit.scala:98:20] wire exe_int_req_uop_ppred_busy = exe_uop_bits_ppred_busy; // @[execution-unit.scala:98:20, :547:25] reg [6:0] exe_uop_bits_stale_pdst; // @[execution-unit.scala:98:20] wire [6:0] exe_int_req_uop_stale_pdst = exe_uop_bits_stale_pdst; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_exception; // @[execution-unit.scala:98:20] wire exe_int_req_uop_exception = exe_uop_bits_exception; // @[execution-unit.scala:98:20, :547:25] reg [63:0] exe_uop_bits_exc_cause; // @[execution-unit.scala:98:20] wire [63:0] exe_int_req_uop_exc_cause = exe_uop_bits_exc_cause; // @[execution-unit.scala:98:20, :547:25] reg [4:0] exe_uop_bits_mem_cmd; // @[execution-unit.scala:98:20] wire [4:0] exe_int_req_uop_mem_cmd = exe_uop_bits_mem_cmd; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_mem_size; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_mem_size = exe_uop_bits_mem_size; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_mem_signed; // @[execution-unit.scala:98:20] wire exe_int_req_uop_mem_signed = exe_uop_bits_mem_signed; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_uses_ldq; // @[execution-unit.scala:98:20] wire exe_int_req_uop_uses_ldq = exe_uop_bits_uses_ldq; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_uses_stq; // @[execution-unit.scala:98:20] wire exe_int_req_uop_uses_stq = exe_uop_bits_uses_stq; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_is_unique; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_unique = exe_uop_bits_is_unique; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_flush_on_commit; // @[execution-unit.scala:98:20] wire exe_int_req_uop_flush_on_commit = exe_uop_bits_flush_on_commit; // @[execution-unit.scala:98:20, :547:25] reg [2:0] exe_uop_bits_csr_cmd; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_csr_cmd = exe_uop_bits_csr_cmd; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_ldst_is_rs1; // @[execution-unit.scala:98:20] wire exe_int_req_uop_ldst_is_rs1 = exe_uop_bits_ldst_is_rs1; // @[execution-unit.scala:98:20, :547:25] reg [5:0] exe_uop_bits_ldst; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_ldst = exe_uop_bits_ldst; // @[execution-unit.scala:98:20, :547:25] reg [5:0] exe_uop_bits_lrs1; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_lrs1 = exe_uop_bits_lrs1; // @[execution-unit.scala:98:20, :547:25] reg [5:0] exe_uop_bits_lrs2; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_lrs2 = exe_uop_bits_lrs2; // @[execution-unit.scala:98:20, :547:25] reg [5:0] exe_uop_bits_lrs3; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_lrs3 = exe_uop_bits_lrs3; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_dst_rtype; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_dst_rtype = exe_uop_bits_dst_rtype; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_lrs1_rtype; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_lrs1_rtype = exe_uop_bits_lrs1_rtype; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_lrs2_rtype; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_lrs2_rtype = exe_uop_bits_lrs2_rtype; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_frs3_en; // @[execution-unit.scala:98:20] wire exe_int_req_uop_frs3_en = exe_uop_bits_frs3_en; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fcn_dw; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fcn_dw = exe_uop_bits_fcn_dw; // @[execution-unit.scala:98:20, :547:25] reg [4:0] exe_uop_bits_fcn_op; // @[execution-unit.scala:98:20] wire [4:0] exe_int_req_uop_fcn_op = exe_uop_bits_fcn_op; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_fp_val; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_val = exe_uop_bits_fp_val; // @[execution-unit.scala:98:20, :547:25] reg [2:0] exe_uop_bits_fp_rm; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_fp_rm = exe_uop_bits_fp_rm; // @[execution-unit.scala:98:20, :547:25] reg [1:0] exe_uop_bits_fp_typ; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_fp_typ = exe_uop_bits_fp_typ; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_xcpt_pf_if; // @[execution-unit.scala:98:20] wire exe_int_req_uop_xcpt_pf_if = exe_uop_bits_xcpt_pf_if; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_xcpt_ae_if; // @[execution-unit.scala:98:20] wire exe_int_req_uop_xcpt_ae_if = exe_uop_bits_xcpt_ae_if; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_xcpt_ma_if; // @[execution-unit.scala:98:20] wire exe_int_req_uop_xcpt_ma_if = exe_uop_bits_xcpt_ma_if; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_bp_debug_if; // @[execution-unit.scala:98:20] wire exe_int_req_uop_bp_debug_if = exe_uop_bits_bp_debug_if; // @[execution-unit.scala:98:20, :547:25] reg exe_uop_bits_bp_xcpt_if; // @[execution-unit.scala:98:20] wire exe_int_req_uop_bp_xcpt_if = exe_uop_bits_bp_xcpt_if; // @[execution-unit.scala:98:20, :547:25] reg [2:0] exe_uop_bits_debug_fsrc; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_debug_fsrc = exe_uop_bits_debug_fsrc; // @[execution-unit.scala:98:20, :547:25] reg [2:0] exe_uop_bits_debug_tsrc; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_debug_tsrc = exe_uop_bits_debug_tsrc; // @[execution-unit.scala:98:20, :547:25] wire [11:0] _exe_uop_valid_T = io_brupdate_b1_mispredict_mask & rrd_uop_bits_br_mask; // @[util.scala:126:51] wire _exe_uop_valid_T_1 = \|_exe_uop_valid_T; // @[util.scala:126:{51,59}] wire _exe_uop_valid_T_2 = _exe_uop_valid_T_1 \| io_kill; // @[util.scala:61:61, :126:59] wire _exe_uop_valid_T_3 = ~_exe_uop_valid_T_2; // @[util.scala:61:61] wire _exe_uop_valid_T_4 = rrd_uop_valid & _exe_uop_valid_T_3; // @[execution-unit.scala:95:20, :99:{34,37}] wire [11:0] _exe_uop_bits_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] exe_uop_bits_out_br_mask; // @[util.scala:104:23] wire [11:0] _exe_uop_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27] assign _exe_uop_bits_out_br_mask_T_1 = rrd_uop_bits_br_mask & _exe_uop_bits_out_br_mask_T; // @[util.scala:93:{25,27}] assign exe_uop_bits_out_br_mask = _exe_uop_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire _GEN_0 = arb_uop_bits_lrs1_rtype == 2'h0; // @[execution-unit.scala:92:20, :121:72] wire _io_arb_irf_reqs_0_valid_T; // @[execution-unit.scala:121:72] assign _io_arb_irf_reqs_0_valid_T = _GEN_0; // @[execution-unit.scala:121:72] wire _arb_rebusied_prs1_T; // @[execution-unit.scala:128:51] assign _arb_rebusied_prs1_T = _GEN_0; // @[execution-unit.scala:121:72, :128:51] wire _io_arb_irf_reqs_0_valid_T_1 = arb_uop_valid & _io_arb_irf_reqs_0_valid_T; // @[execution-unit.scala:92:20, :121:{45,72}] wire _io_arb_irf_reqs_0_valid_T_2 = ~arb_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:92:20, :121:86] assign _io_arb_irf_reqs_0_valid_T_3 = _io_arb_irf_reqs_0_valid_T_1 & _io_arb_irf_reqs_0_valid_T_2; // @[execution-unit.scala:121:{45,83,86}] assign io_arb_irf_reqs_0_valid_0 = _io_arb_irf_reqs_0_valid_T_3; // @[execution-unit.scala:121:83, :492:7] wire _GEN_1 = arb_uop_bits_lrs2_rtype == 2'h0; // @[execution-unit.scala:92:20, :125:74] wire _io_arb_irf_reqs_1_valid_T; // @[execution-unit.scala:125:74] assign _io_arb_irf_reqs_1_valid_T = _GEN_1; // @[execution-unit.scala:125:74] wire _arb_rebusied_prs2_T; // @[execution-unit.scala:129:51] assign _arb_rebusied_prs2_T = _GEN_1; // @[execution-unit.scala:125:74, :129:51] wire _io_arb_irf_reqs_1_valid_T_1 = arb_uop_valid & _io_arb_irf_reqs_1_valid_T; // @[execution-unit.scala:92:20, :125:{47,74}] wire _io_arb_irf_reqs_1_valid_T_2 = ~arb_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:92:20, :125:88] assign _io_arb_irf_reqs_1_valid_T_3 = _io_arb_irf_reqs_1_valid_T_1 & _io_arb_irf_reqs_1_valid_T_2; // @[execution-unit.scala:125:{47,85,88}] assign io_arb_irf_reqs_1_valid_0 = _io_arb_irf_reqs_1_valid_T_3; // @[execution-unit.scala:125:85, :492:7] wire _GEN_2 = io_arb_rebusys_0_valid & io_arb_rebusys_0_bits_rebusy; // @[execution-unit.scala:118:39] wire _arb_rebusied_prs1_T_1; // @[execution-unit.scala:118:39] assign _arb_rebusied_prs1_T_1 = _GEN_2; // @[execution-unit.scala:118:39] wire _arb_rebusied_prs2_T_1; // @[execution-unit.scala:118:39] assign _arb_rebusied_prs2_T_1 = _GEN_2; // @[execution-unit.scala:118:39] wire _arb_rebusied_prs1_T_2 = io_arb_rebusys_0_bits_uop_pdst == arb_uop_bits_prs1; // @[execution-unit.scala:92:20, :118:75] wire _arb_rebusied_prs1_T_3 = _arb_rebusied_prs1_T_1 & _arb_rebusied_prs1_T_2; // @[execution-unit.scala:118:{39,56,75}] wire arb_rebusied_prs1 = _arb_rebusied_prs1_T & _arb_rebusied_prs1_T_3; // @[execution-unit.scala:118:56, :128:{51,62}] wire _arb_rebusied_prs2_T_2 = io_arb_rebusys_0_bits_uop_pdst == arb_uop_bits_prs2; // @[execution-unit.scala:92:20, :118:75] wire _arb_rebusied_prs2_T_3 = _arb_rebusied_prs2_T_1 & _arb_rebusied_prs2_T_2; // @[execution-unit.scala:118:{39,56,75}] wire _arb_rebusied_prs2_T_4 = _arb_rebusied_prs2_T & _arb_rebusied_prs2_T_3; // @[execution-unit.scala:118:56, :129:{51,62}] wire arb_rebusied_prs2 = _arb_rebusied_prs2_T_4; // @[execution-unit.scala:129:{62,93}] wire arb_rebusied = arb_rebusied_prs1 \| arb_rebusied_prs2; // @[execution-unit.scala:128:62, :129:93, :130:45] reg [63:0] exe_rs1_data; // @[execution-unit.scala:133:25] wire [63:0] exe_int_req_rs1_data = exe_rs1_data; // @[execution-unit.scala:133:25, :547:25] reg [63:0] exe_rs2_data; // @[execution-unit.scala:134:25] wire [63:0] exe_int_req_rs2_data = exe_rs2_data; // @[execution-unit.scala:134:25, :547:25] wire _hits_T = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_0_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_0 = io_rrd_irf_bypasses_0_valid & _hits_T; // @[execution-unit.scala:113:{55,62}] wire _hits_T_1 = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_1_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_1 = io_rrd_irf_bypasses_1_valid & _hits_T_1; // @[execution-unit.scala:113:{55,62}] wire _hits_T_2 = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_2_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_2 = io_rrd_irf_bypasses_2_valid & _hits_T_2; // @[execution-unit.scala:113:{55,62}] wire _T_1 = hits_0 \| hits_1; // @[execution-unit.scala:113:55, :114:19] wire rs1_hit = _T_1 \| hits_2; // @[execution-unit.scala:113:55, :114:19] wire [63:0] rs1_data = _T_1 \| hits_2 ? (hits_0 ? io_rrd_irf_bypasses_0_bits_data : 64'h0) \| (hits_1 ? io_rrd_irf_bypasses_1_bits_data : 64'h0) \| (hits_2 ? io_rrd_irf_bypasses_2_bits_data : 64'h0) : io_rrd_irf_resps_0; // @[Mux.scala:30:73] wire _exe_rs1_data_T = &rrd_uop_bits_lrs1_rtype; // @[execution-unit.scala:95:20, :137:47] wire [63:0] _exe_rs1_data_T_1 = _exe_rs1_data_T ? 64'h0 : rs1_data; // @[execution-unit.scala:114:28, :137:{22,47}] wire _hits_T_3 = rrd_uop_bits_prs2 == io_rrd_irf_bypasses_0_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_0_1 = io_rrd_irf_bypasses_0_valid & _hits_T_3; // @[execution-unit.scala:113:{55,62}] wire _hits_T_4 = rrd_uop_bits_prs2 == io_rrd_irf_bypasses_1_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_1_1 = io_rrd_irf_bypasses_1_valid & _hits_T_4; // @[execution-unit.scala:113:{55,62}] wire _hits_T_5 = rrd_uop_bits_prs2 == io_rrd_irf_bypasses_2_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_2_1 = io_rrd_irf_bypasses_2_valid & _hits_T_5; // @[execution-unit.scala:113:{55,62}] wire _T_18 = hits_0_1 \| hits_1_1; // @[execution-unit.scala:113:55, :114:19] wire rs2_hit = _T_18 \| hits_2_1; // @[execution-unit.scala:113:55, :114:19] wire [63:0] rs2_data = _T_18 \| hits_2_1 ? (hits_0_1 ? io_rrd_irf_bypasses_0_bits_data : 64'h0) \| (hits_1_1 ? io_rrd_irf_bypasses_1_bits_data : 64'h0) \| (hits_2_1 ? io_rrd_irf_bypasses_2_bits_data : 64'h0) : io_rrd_irf_resps_1; // @[Mux.scala:30:73]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w4_d3_i0_31( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_286 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_287 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_288 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_289 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid \|\| io.clear \|\| io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 \|\| rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_\|\|_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_\|\|_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready \|\| agen_ready \|\| dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }	module IssueSlot_22( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire rebusied_prs1 = 1'h0; // @[issue-slot.scala:92:31] wire rebusied_prs2 = 1'h0; // @[issue-slot.scala:93:31] wire rebusied = 1'h0; // @[issue-slot.scala:94:32] wire prs1_rebusys_0 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_0 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] next_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] _next_uop_iw_p1_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] wire _iss_ready_T_6 = slot_uop_prs3_busy; // @[issue-slot.scala:56:21, :136:131] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File TileClockGater.scala: package chipyard.clocking import chisel3._ import chisel3.util._ import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ /* This node adds clock gating control registers. * If deploying on a platform which does not support clock gating, deasserting the enable * flag will generate the registers, preserving the same memory map and behavior, but will not * generate any gaters / class TileClockGater(address: BigInt, beatBytes: Int)(implicit p: Parameters, valName: ValName) extends LazyModule { val device = new SimpleDevice(s"clock-gater", Nil) val clockNode = ClockGroupIdentityNode() val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes) lazy val module = new LazyModuleImp(this) { val sources = clockNode.in.head._1.member.data.toSeq val sinks = clockNode.out.head._1.member.elements.toSeq val nSinks = sinks.size val regs = (0 until nSinks).map({i => val sinkName = sinks(i)._1 val reg = withReset(sources(i).reset) { Module(new AsyncResetRegVec(w=1, init=1)) } if (sinkName.contains("tile")) { println(s"${(address+i4).toString(16)}: Tile $sinkName clock gate") sinks(i)._2.clock := ClockGate(sources(i).clock, reg.io.q.asBool) sinks(i)._2.reset := sources(i).reset } else { sinks(i)._2 := sources(i) } reg }) tlNode.regmap((0 until nSinks).map({i => i4 -> Seq(RegField.rwReg(1, regs(i).io)) }): _) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. / object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct / cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) / Filter out any cases identical to the default / val simple = cases.filter { case (k, v) => !default.isLit \|\| !v.isLit \|\| v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2simple.size) { /* The dense encoding case uses a Vec / val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { / The sparse encoding case uses switch / val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TileClockGater( // @[TileClockGater.scala:27:25] input clock, // @[TileClockGater.scala:27:25] input reset, // @[TileClockGater.scala:27:25] output auto_clock_gater_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_clock_gater_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_clock_gater_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_clock_gater_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_clock_gater_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_clock_gater_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_clock_gater_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_clock_gater_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_clock_gater_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_clock_gater_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_reset // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_clock_gater_in_1_a_valid_0 = auto_clock_gater_in_1_a_valid; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_a_bits_opcode_0 = auto_clock_gater_in_1_a_bits_opcode; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_a_bits_param_0 = auto_clock_gater_in_1_a_bits_param; // @[TileClockGater.scala:27:25] wire [1:0] auto_clock_gater_in_1_a_bits_size_0 = auto_clock_gater_in_1_a_bits_size; // @[TileClockGater.scala:27:25] wire [10:0] auto_clock_gater_in_1_a_bits_source_0 = auto_clock_gater_in_1_a_bits_source; // @[TileClockGater.scala:27:25] wire [20:0] auto_clock_gater_in_1_a_bits_address_0 = auto_clock_gater_in_1_a_bits_address; // @[TileClockGater.scala:27:25] wire [7:0] auto_clock_gater_in_1_a_bits_mask_0 = auto_clock_gater_in_1_a_bits_mask; // @[TileClockGater.scala:27:25] wire [63:0] auto_clock_gater_in_1_a_bits_data_0 = auto_clock_gater_in_1_a_bits_data; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_a_bits_corrupt_0 = auto_clock_gater_in_1_a_bits_corrupt; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_ready_0 = auto_clock_gater_in_1_d_ready; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_0_member_allClocks_uncore_clock_0 = auto_clock_gater_in_0_member_allClocks_uncore_clock; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_0_member_allClocks_uncore_reset_0 = auto_clock_gater_in_0_member_allClocks_uncore_reset; // @[TileClockGater.scala:27:25] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] clock_gaterIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] clock_gaterIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_clock_gater_in_1_d_bits_sink = 1'h0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_bits_denied = 1'h0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_bits_corrupt = 1'h0; // @[TileClockGater.scala:27:25] wire clock_gaterIn_1_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire clock_gaterIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire clock_gaterIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire clock_gaterIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_clock_gater_in_1_d_bits_param = 2'h0; // @[TileClockGater.scala:27:25] wire clock_gaterIn_1_a_ready; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire clock_gaterIn_1_a_valid = auto_clock_gater_in_1_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_a_bits_opcode = auto_clock_gater_in_1_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_a_bits_param = auto_clock_gater_in_1_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_a_bits_size = auto_clock_gater_in_1_a_bits_size_0; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_1_a_bits_source = auto_clock_gater_in_1_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] clock_gaterIn_1_a_bits_address = auto_clock_gater_in_1_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] clock_gaterIn_1_a_bits_mask = auto_clock_gater_in_1_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] clock_gaterIn_1_a_bits_data = auto_clock_gater_in_1_a_bits_data_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_a_bits_corrupt = auto_clock_gater_in_1_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_ready = auto_clock_gater_in_1_d_ready_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] clock_gaterIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire clock_gaterIn_member_allClocks_uncore_clock = auto_clock_gater_in_0_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clock_gaterOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clock_gaterIn_member_allClocks_uncore_reset = auto_clock_gater_in_0_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clock_gaterOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire auto_clock_gater_in_1_a_ready_0; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_d_bits_opcode_0; // @[TileClockGater.scala:27:25] wire [1:0] auto_clock_gater_in_1_d_bits_size_0; // @[TileClockGater.scala:27:25] wire [10:0] auto_clock_gater_in_1_d_bits_source_0; // @[TileClockGater.scala:27:25] wire [63:0] auto_clock_gater_in_1_d_bits_data_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_valid_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_out_member_allClocks_uncore_clock_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_out_member_allClocks_uncore_reset_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_clock_0 = clock_gaterOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_gater_out_member_allClocks_uncore_reset_0 = clock_gaterOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clock_gaterOut_member_allClocks_uncore_clock = clock_gaterIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clock_gaterOut_member_allClocks_uncore_reset = clock_gaterIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_clock_gater_in_1_a_ready_0 = clock_gaterIn_1_a_ready; // @[MixedNode.scala:551:17] wire in_valid = clock_gaterIn_1_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = clock_gaterIn_1_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = clock_gaterIn_1_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = clock_gaterIn_1_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = clock_gaterIn_1_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = clock_gaterIn_1_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_clock_gater_in_1_d_valid_0 = clock_gaterIn_1_d_valid; // @[MixedNode.scala:551:17] assign auto_clock_gater_in_1_d_bits_opcode_0 = clock_gaterIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_clock_gater_in_1_d_bits_size_0 = clock_gaterIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_clock_gater_in_1_d_bits_source_0 = clock_gaterIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_clock_gater_in_1_d_bits_data_0 = clock_gaterIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = clock_gaterIn_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [17:0] _in_bits_index_T = clock_gaterIn_1_a_bits_address[20:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _clock_gaterIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign clock_gaterIn_1_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] wire _out_T_8 = _out_T_7; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1_0 = _out_T_8; // @[MuxLiteral.scala:49:48] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_3 = _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_4 = _out_out_bits_data_T_1 & _out_out_bits_data_T_3; // @[MuxLiteral.scala:49:10] assign out_bits_data = {63'h0, _out_out_bits_data_T_4}; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_d_bits_size = clock_gaterIn_d_bits_d_size; // @[Edges.scala:792:17] assign clock_gaterIn_1_d_bits_source = clock_gaterIn_d_bits_d_source; // @[Edges.scala:792:17] assign clock_gaterIn_1_d_bits_opcode = {2'h0, _clock_gaterIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_61 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (clock_gaterIn_1_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (clock_gaterIn_1_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (clock_gaterIn_1_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (clock_gaterIn_1_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (clock_gaterIn_1_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (clock_gaterIn_1_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (clock_gaterIn_1_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (clock_gaterIn_1_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (clock_gaterIn_1_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (clock_gaterIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (clock_gaterIn_1_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (clock_gaterIn_1_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (clock_gaterIn_1_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (clock_gaterIn_1_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (clock_gaterIn_1_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (clock_gaterIn_1_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i1 regs_0 ( // @[TileClockGater.scala:33:53] .clock (clock), .reset (clock_gaterIn_member_allClocks_uncore_reset), // @[MixedNode.scala:551:17] .io_d (_out_T_2), // @[RegisterRouter.scala:87:24] .io_q (_out_T_7), .io_en (out_f_woready) // @[RegisterRouter.scala:87:24] ); // @[TileClockGater.scala:33:53] assign auto_clock_gater_in_1_a_ready = auto_clock_gater_in_1_a_ready_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_valid = auto_clock_gater_in_1_d_valid_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_opcode = auto_clock_gater_in_1_d_bits_opcode_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_size = auto_clock_gater_in_1_d_bits_size_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_source = auto_clock_gater_in_1_d_bits_source_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_data = auto_clock_gater_in_1_d_bits_data_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_clock = auto_clock_gater_out_member_allClocks_uncore_clock_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_reset = auto_clock_gater_out_member_allClocks_uncore_reset_0; // @[TileClockGater.scala:27:25] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) \| wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /* @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File TLB.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps case object ASIdBits extends Field[Int](0) case object VMIdBits extends Field[Int](0) /* =SFENCE= * rs1 rs2 * {{{ * 0 0 -> flush All * 0 1 -> flush by ASID * 1 1 -> flush by ADDR * 1 0 -> flush by ADDR and ASID * }}} * {{{ * If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. * If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered. * If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces. * If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. * }}} / class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { val rs1 = Bool() val rs2 = Bool() val addr = UInt(vaddrBits.W) val asid = UInt((asIdBits max 1).W) // TODO zero-width val hv = Bool() val hg = Bool() } class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) { /* request address from CPU. / val vaddr = UInt(vaddrBitsExtended.W) /* don't lookup TLB, bypass vaddr as paddr / val passthrough = Bool() /* granularity / val size = UInt(log2Ceil(lgMaxSize + 1).W) /* memory command. / val cmd = Bits(M_SZ.W) val prv = UInt(PRV.SZ.W) /* virtualization mode / val v = Bool() } class TLBExceptions extends Bundle { val ld = Bool() val st = Bool() val inst = Bool() } class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) { // lookup responses val miss = Bool() /* physical address / val paddr = UInt(paddrBits.W) val gpa = UInt(vaddrBitsExtended.W) val gpa_is_pte = Bool() /* page fault exception / val pf = new TLBExceptions /* guest page fault exception / val gf = new TLBExceptions /* access exception / val ae = new TLBExceptions /* misaligned access exception / val ma = new TLBExceptions /* if this address is cacheable / val cacheable = Bool() /* if caches must allocate this address / val must_alloc = Bool() /* if this address is prefetchable for caches/ val prefetchable = Bool() /* size/cmd of request that generated this response/ val size = UInt(log2Ceil(lgMaxSize + 1).W) val cmd = UInt(M_SZ.W) } class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) { val ppn = UInt(ppnBits.W) /* pte.u user / val u = Bool() /* pte.g global / val g = Bool() /* access exception. * D$ -> PTW -> TLB AE * Alignment failed. / val ae_ptw = Bool() val ae_final = Bool() val ae_stage2 = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* supervisor write / val sw = Bool() /* supervisor execute / val sx = Bool() /* supervisor read / val sr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor excute / val hx = Bool() /* hypervisor read / val hr = Bool() /* prot_w / val pw = Bool() /* prot_x / val px = Bool() /* prot_r / val pr = Bool() /* PutPartial / val ppp = Bool() /* AMO logical / val pal = Bool() /* AMO arithmetic / val paa = Bool() /* get/put effects / val eff = Bool() /* cacheable / val c = Bool() /* fragmented_superpage support / val fragmented_superpage = Bool() } /* basic cell for TLB data / class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) { require(nSectors == 1 \|\| !superpage) require(!superpageOnly \|\| superpage) val level = UInt(log2Ceil(pgLevels).W) /* use vpn as tag / val tag_vpn = UInt(vpnBits.W) /* tag in vitualization mode / val tag_v = Bool() /* entry data / val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W)) /* valid bit / val valid = Vec(nSectors, Bool()) /* returns all entry data in this entry / def entry_data = data.map(_.asTypeOf(new TLBEntryData)) /* returns the index of sector / private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0) /* returns the entry data matched with this vpn/ def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData)) /* returns whether a sector hits / def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual) /* returns whether tag matches vpn / def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual) /* returns hit signal / def hit(vpn: UInt, virtual: Bool): Bool = { if (superpage && usingVM) { var tagMatch = valid.head && (tag_v === virtual) for (j <- 0 until pgLevels) { val base = (pgLevels - 1 - j) pgLevelBits val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0) val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B tagMatch = tagMatch && (ignore \|\| (tag_vpn ^ vpn)(base + n - 1, base) === 0.U) } tagMatch } else { val idx = sectorIdx(vpn) valid(idx) && sectorTagMatch(vpn, virtual) } } /** returns the ppn of the input TLBEntryData / def ppn(vpn: UInt, data: TLBEntryData) = { val supervisorVPNBits = pgLevels pgLevelBits if (superpage && usingVM) { var res = data.ppn >> pgLevelBits(pgLevels - 1) for (j <- 1 until pgLevels) { val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B res = Cat(res, (Mux(ignore, vpn, 0.U) \| data.ppn)(supervisorVPNBits - jpgLevelBits - 1, supervisorVPNBits - (j + 1)pgLevelBits)) } res } else { data.ppn } } /* does the refill * * find the target entry with vpn tag * and replace the target entry with the input entry data / def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = { this.tag_vpn := vpn this.tag_v := virtual this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0) val idx = sectorIdx(vpn) valid(idx) := true.B data(idx) := entry.asUInt } def invalidate(): Unit = { valid.foreach(_ := false.B) } def invalidate(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual) { v := false.B } } def invalidateVPN(vpn: UInt, virtual: Bool): Unit = { if (superpage) { when (hit(vpn, virtual)) { invalidate() } } else { when (sectorTagMatch(vpn, virtual)) { for (((v, e), i) <- (valid zip entry_data).zipWithIndex) when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B } } } // For fragmented superpage mappings, we assume the worst (largest) // case, and zap entries whose most-significant VPNs match when (((tag_vpn ^ vpn) >> (pgLevelBits (pgLevels - 1))) === 0.U) { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && e.fragmented_superpage) { v := false.B } } } def invalidateNonGlobal(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && !e.g) { v := false.B } } } /** TLB config * * @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]] * @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]] * @param nSectors the number of ways in a single PTE TLBEntry * @param nSuperpageEntries the number of SuperpageEntries / case class TLBConfig( nSets: Int, nWays: Int, nSectors: Int = 4, nSuperpageEntries: Int = 4) /* =Overview= * [[TLB]] is a TLB template which contains PMA logic and PMP checker. * * TLB caches PTE and accelerates the address translation process. * When tlb miss happens, ask PTW(L2TLB) for Page Table Walk. * Perform PMP and PMA check during the translation and throw exception if there were any. * * ==Cache Structure== * - Sectored Entry (PTE) * - set-associative or direct-mapped * - nsets = [[TLBConfig.nSets]] * - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]] * - PTEEntry( sectors = [[TLBConfig.nSectors]] ) * - LRU(if set-associative) * * - Superpage Entry(superpage PTE) * - fully associative * - nsets = [[TLBConfig.nSuperpageEntries]] * - PTEEntry(sectors = 1) * - PseudoLRU * * - Special Entry(PTE across PMP) * - nsets = 1 * - PTEEntry(sectors = 1) * * ==Address structure== * {{{ * \|vaddr \| * \|ppn/vpn \| pgIndex \| * \| \| \| * \| \|nSets \|nSector \| \|}}} * * ==State Machine== * {{{ * s_ready: ready to accept request from CPU. * s_request: when L1TLB(this) miss, send request to PTW(L2TLB), . * s_wait: wait for PTW to refill L1TLB. * s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}} * * ==PMP== * pmp check * - special_entry: always check * - other entry: check on refill * * ==Note== * PMA consume diplomacy parameter generate physical memory address checking logic * * Boom use Rocket ITLB, and its own DTLB. * * Accelerators:{{{ * sha3: DTLB * gemmini: DTLB * hwacha: DTLB2+ITLB}}} @param instruction true for ITLB, false for DTLB * @param lgMaxSize @todo seems granularity * @param cfg [[TLBConfig]] * @param edge collect SoC metadata. / class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { override def desiredName = if (instruction) "ITLB" else "DTLB" val io = IO(new Bundle { /* request from Core / val req = Flipped(Decoupled(new TLBReq(lgMaxSize))) /* response to Core / val resp = Output(new TLBResp(lgMaxSize)) /* SFence Input / val sfence = Flipped(Valid(new SFenceReq)) /* IO to PTW / val ptw = new TLBPTWIO /* suppress a TLB refill, one cycle after a miss / val kill = Input(Bool()) }) io.ptw.customCSRs := DontCare val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits) /* index for sectored_Entry / val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) /* TLB Entry / val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) /* Superpage Entry / val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true))) /* Special Entry * * If PMP granularity is less than page size, thus need additional "special" entry manage PMP. / val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false))) def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries def all_entries = ordinary_entries ++ special_entry def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) val state = RegInit(s_ready) // use vpn as refill_tag val r_refill_tag = Reg(UInt(vpnBits.W)) val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W)) val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W)) val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W))) val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W))) val r_vstage1_en = Reg(Bool()) val r_stage2_en = Reg(Bool()) val r_need_gpa = Reg(Bool()) val r_gpa_valid = Reg(Bool()) val r_gpa = Reg(UInt(vaddrBits.W)) val r_gpa_vpn = Reg(UInt(vpnBits.W)) val r_gpa_is_pte = Reg(Bool()) /* privilege mode / val priv = io.req.bits.prv val priv_v = usingHypervisor.B && io.req.bits.v val priv_s = priv(0) // user mode and supervisor mode val priv_uses_vm = priv <= PRV.S.U val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1) /* VS-stage translation enable / val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1) /* G-stage translation enable / val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1) /* Enable Virtual Memory when: * 1. statically configured * 1. satp highest bits enabled * i. RV32: * - 0 -> Bare * - 1 -> SV32 * i. RV64: * - 0000 -> Bare * - 1000 -> SV39 * - 1001 -> SV48 * - 1010 -> SV57 * - 1011 -> SV64 * 1. In virtualization mode, vsatp highest bits enabled * 1. priv mode in U and S. * 1. in H & M mode, disable VM. * 1. no passthrough(micro-arch defined.) * * @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register * @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp) / val vm_enabled = (stage1_en \|\| stage2_en) && priv_uses_vm && !io.req.bits.passthrough // flush guest entries on vsatp.MODE Bare <-> SvXX transitions val v_entries_use_stage1 = RegInit(false.B) val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough // share a single physical memory attribute checker (unshare if critical path) val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) /* refill signal / val do_refill = usingVM.B && io.ptw.resp.valid /* sfence invalidate refill / val invalidate_refill = state.isOneOf(s_request / don't care /, s_wait_invalidate) \|\| io.sfence.valid // PMP val mpu_ppn = Mux(do_refill, refill_ppn, Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val mpu_priv = Mux[UInt](usingVM.B && (do_refill \|\| io.req.bits.passthrough / PTW /), PRV.S.U, Cat(io.ptw.status.debug, priv)) val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size pmp.io.pmp := (io.ptw.pmp: Seq[PMP]) pmp.io.prv := mpu_priv val pma = Module(new PMAChecker(edge.manager)(p)) pma.io.paddr := mpu_physaddr // todo: using DataScratchpad doesn't support cacheable. val cacheable = pma.io.resp.cacheable && (instruction \|\| !usingDataScratchpad).B val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous // In M mode, if access DM address(debug module program buffer) val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B) val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w val prot_pp = pma.io.resp.pp val prot_al = pma.io.resp.al val prot_aa = pma.io.resp.aa val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x val prot_eff = pma.io.resp.eff // hit check val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v)) val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v)) val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v)) val real_hits = hitsVec.asUInt val hits = Cat(!vm_enabled, real_hits) // use ptw response to refill // permission bit arrays when (do_refill) { val pte = io.ptw.resp.bits.pte val refill_v = r_vstage1_en \|\| r_stage2_en val newEntry = Wire(new TLBEntryData) newEntry.ppn := pte.ppn newEntry.c := cacheable newEntry.u := pte.u newEntry.g := pte.g && pte.v newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw newEntry.ae_final := io.ptw.resp.bits.ae_final newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en newEntry.pf := io.ptw.resp.bits.pf newEntry.gf := io.ptw.resp.bits.gf newEntry.hr := io.ptw.resp.bits.hr newEntry.hw := io.ptw.resp.bits.hw newEntry.hx := io.ptw.resp.bits.hx newEntry.sr := pte.sr() newEntry.sw := pte.sw() newEntry.sx := pte.sx() newEntry.pr := prot_r newEntry.pw := prot_w newEntry.px := prot_x newEntry.ppp := prot_pp newEntry.pal := prot_al newEntry.paa := prot_aa newEntry.eff := prot_eff newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage // refill special_entry when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) { special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)) }.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) { val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr) for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) { e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry) when (invalidate_refill) { e.invalidate() } } // refill sectored_hit }.otherwise { val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) { when (!r_sectored_hit.valid) { e.invalidate() } e.insert(r_refill_tag, refill_v, 0.U, newEntry) when (invalidate_refill) { e.invalidate() } } } r_gpa_valid := io.ptw.resp.bits.gpa.valid r_gpa := io.ptw.resp.bits.gpa.bits r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte } // get all entries data. val entries = all_entries.map(_.getData(vpn)) val normal_entries = entries.take(ordinary_entries.size) // parallel query PPN from [[all_entries]], if VM not enabled return VPN instead val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0)) val nPhysicalEntries = 1 + special_entry.size // generally PTW misaligned load exception. val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt) val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt) val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt) val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt) val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) // if in hypervisor/machine mode, cannot read/write user entries. // if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)" val priv_rw_ok = Mux(!priv_s \|\| sum, entries.map(_.u).asUInt, 0.U) \| Mux(priv_s, ~entries.map(_.u).asUInt, 0.U) // if in hypervisor/machine mode, other than user pages, all pages are executable. // if in superviosr/user mode, only user page can execute. val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt) val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) \| entries.map(_.ae_stage2).asUInt) val mxr = io.ptw.status.mxr \| Mux(priv_v, io.ptw.gstatus.mxr, false.B) // "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)" val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt \| Mux(mxr, entries.map(_.sx).asUInt, 0.U))) \| stage1_bypass) val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) \| stage1_bypass) val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) \| stage1_bypass) val stage2_bypass = Fill(entries.size, !stage2_en) val hr_array = Cat(true.B, entries.map(_.hr).asUInt \| Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) \| stage2_bypass) val hw_array = Cat(true.B, entries.map(_.hw).asUInt \| stage2_bypass) val hx_array = Cat(true.B, entries.map(_.hx).asUInt \| stage2_bypass) // These array is for each TLB entries. // user mode can read: PMA OK, TLB OK, AE OK val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array \| final_ae_array) // put effect val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt) // cacheable val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt) // put partial val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt) // atomic arithmetic val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt) // atomic logic val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt) val ppp_array_if_cached = ppp_array \| c_array val paa_array_if_cached = paa_array \| (if(usingAtomicsInCache) c_array else 0.U) val pal_array_if_cached = pal_array \| (if(usingAtomicsInCache) c_array else 0.U) val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt) // vaddr misaligned: vaddr[1:0]=b00 val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR def badVA(guestPA: Boolean): Bool = { val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels val extraBits = if (guestPA) hypervisorExtraAddrBits else 0 val signed = !guestPA val nPgLevelChoices = pgLevels - minPgLevels + 1 val minVAddrBits = pgIdxBits + minPgLevels pgLevelBits + extraBits (for (i <- 0 until nPgLevelChoices) yield { val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U val maskedVAddr = io.req.bits.vaddr & mask additionalPgLevels === i.U && !(maskedVAddr === 0.U \|\| signed.B && maskedVAddr === mask) }).orR } val bad_gpa = if (!usingHypervisor) false.B else vm_enabled && !stage1_en && badVA(true) val bad_va = if (!usingVM \|\| (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B else vm_enabled && stage1_en && badVA(false) val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC) val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd) val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd) val cmd_put_partial = io.req.bits.cmd === M_PWR val cmd_read = isRead(io.req.bits.cmd) val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX val cmd_write = isWrite(io.req.bits.cmd) val cmd_write_perms = cmd_write \|\| io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions val lrscAllowed = Mux((usingDataScratchpad \|\| usingAtomicsOnlyForIO).B, 0.U, c_array) val ae_array = Mux(misaligned, eff_array, 0.U) \| Mux(cmd_lrsc, ~lrscAllowed, 0.U) // access exception needs SoC information from PMA val ae_ld_array = Mux(cmd_read, ae_array \| ~pr_array, 0.U) val ae_st_array = Mux(cmd_write_perms, ae_array \| ~pw_array, 0.U) \| Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) \| Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U) val must_alloc_array = Mux(cmd_put_partial, ~ppp_array, 0.U) \| Mux(cmd_amo_logical, ~pal_array, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array, 0.U) \| Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U) val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_inst_array = ((~x_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_inst_array = Mux(priv_v, (~hx_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gpa_hits = { val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array \| gf_st_array val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) \| Fill(all_entries.size, !vstage1_en) hit_mask \| ~need_gpa_mask(all_entries.size-1, 0) } val tlb_hit_if_not_gpa_miss = real_hits.orR val tlb_hit = (real_hits & gpa_hits).orR // leads to s_request val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru") val superpage_plru = new PseudoLRU(superpage_entries.size) when (io.req.valid && vm_enabled) { // replace when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) } when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) } } // Superpages create the possibility that two entries in the TLB may match. // This corresponds to a software bug, but we can't return complete garbage; // we must return either the old translation or the new translation. This // isn't compatible with the Mux1H approach. So, flush the TLB and report // a miss on duplicate entries. val multipleHits = PopCountAtLeast(real_hits, 2) // only pull up req.ready when this is s_ready state. io.req.ready := state === s_ready // page fault io.resp.pf.ld := (bad_va && cmd_read) \|\| (pf_ld_array & hits).orR io.resp.pf.st := (bad_va && cmd_write_perms) \|\| (pf_st_array & hits).orR io.resp.pf.inst := bad_va \|\| (pf_inst_array & hits).orR // guest page fault io.resp.gf.ld := (bad_gpa && cmd_read) \|\| (gf_ld_array & hits).orR io.resp.gf.st := (bad_gpa && cmd_write_perms) \|\| (gf_st_array & hits).orR io.resp.gf.inst := bad_gpa \|\| (gf_inst_array & hits).orR // access exception io.resp.ae.ld := (ae_ld_array & hits).orR io.resp.ae.st := (ae_st_array & hits).orR io.resp.ae.inst := (~px_array & hits).orR // misaligned io.resp.ma.ld := misaligned && cmd_read io.resp.ma.st := misaligned && cmd_write io.resp.ma.inst := false.B // this is up to the pipeline to figure out io.resp.cacheable := (c_array & hits).orR io.resp.must_alloc := (must_alloc_array & hits).orR io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB \|\| m.supportsHint).B io.resp.miss := do_refill \|\| vsatp_mode_mismatch \|\| tlb_miss \|\| multipleHits io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) io.resp.size := io.req.bits.size io.resp.cmd := io.req.bits.cmd io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte io.resp.gpa := { val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits) val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0)) Cat(page, offset) } io.ptw.req.valid := state === s_request io.ptw.req.bits.valid := !io.kill io.ptw.req.bits.bits.addr := r_refill_tag io.ptw.req.bits.bits.vstage1 := r_vstage1_en io.ptw.req.bits.bits.stage2 := r_stage2_en io.ptw.req.bits.bits.need_gpa := r_need_gpa if (usingVM) { when(io.ptw.req.fire && io.ptw.req.bits.valid) { r_gpa_valid := false.B r_gpa_vpn := r_refill_tag } val sfence = io.sfence.valid // this is [[s_ready]] // handle miss/hit at the first cycle. // if miss, request PTW(L2TLB). when (io.req.fire && tlb_miss) { state := s_request r_refill_tag := vpn r_need_gpa := tlb_hit_if_not_gpa_miss r_vstage1_en := vstage1_en r_stage2_en := stage2_en r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way) r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx)) r_sectored_hit.valid := sector_hits.orR r_sectored_hit.bits := OHToUInt(sector_hits) r_superpage_hit.valid := superpage_hits.orR r_superpage_hit.bits := OHToUInt(superpage_hits) } // Handle SFENCE.VMA when send request to PTW. // SFENCE.VMA io.ptw.req.ready kill // ? ? 1 // 0 0 0 // 0 1 0 -> s_wait // 1 0 0 -> s_wait_invalidate // 1 0 0 -> s_ready when (state === s_request) { // SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle. when (sfence) { state := s_ready } // here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B) // fire -> s_wait when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) } // If CPU kills request(frontend.s2_redirect) when (io.kill) { state := s_ready } } // sfence in refill will results in invalidate when (state === s_wait && sfence) { state := s_wait_invalidate } // after CPU acquire response, go back to s_ready. when (io.ptw.resp.valid) { state := s_ready } // SFENCE processing logic. when (sfence) { assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn) for (e <- all_real_entries) { val hv = usingHypervisor.B && io.sfence.bits.hv val hg = usingHypervisor.B && io.sfence.bits.hg when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) } .elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) } .otherwise { e.invalidate(hv \|\| hg) } } } when(io.req.fire && vsatp_mode_mismatch) { all_real_entries.foreach(_.invalidate(true.B)) v_entries_use_stage1 := vstage1_en } when (multipleHits \|\| reset.asBool) { all_real_entries.foreach(_.invalidate()) } ccover(io.ptw.req.fire, "MISS", "TLB miss") ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy") ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill") ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB") ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID") ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line") ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID") ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc) /** Decides which entry to be replaced * * If there is a invalid entry, replace it with priorityencoder; * if not, replace the alt entry * * @return mask for TLBEntry replacement / def replacementEntry(set: Seq[TLBEntry], alt: UInt) = { val valids = set.map(_.valid.orR).asUInt Mux(valids.andR, alt, PriorityEncoder(~valids)) } } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r \|\| w \|\| x \|\| c \|\| a \|\| l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet \|\| m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull \|\| m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet \|\| m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull \|\| m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial \|\| m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB \|\| m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT \|\| m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical \|\| m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic \|\| m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ \|\| _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /* PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss / class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /* PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info / class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /* ptw access exception / val ae_ptw = Bool() /* final access exception / val ae_final = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* hypervisor read / val hr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor execute / val hx = Bool() /* PTE to refill L1TLB * * source: L2TLB / val pte = new PTE /* pte pglevel / val level = UInt(log2Ceil(pgLevels).W) /* fragmented_superpage support / val fragmented_superpage = Bool() /* homogeneous for both pma and pmp / val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /* IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) / class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /* PTW performance statistics / class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /* Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core / class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /* enable clock generated by ptw / val clock_enabled = Output(Bool()) } /* PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format / class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* global mapping / val g = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() /* valid bit / val v = Bool() /* return true if find a pointer to next level page table / def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /* return true if find a leaf PTE / def leaf(dummy: Int = 0) = v && (r \|\| (x && !w)) && a /* user read / def ur(dummy: Int = 0) = sr() && u /* user write/ def uw(dummy: Int = 0) = sw() && u /* user execute / def ux(dummy: Int = 0) = sx() && u /* supervisor read / def sr(dummy: Int = 0) = leaf() && r /* supervisor write / def sw(dummy: Int = 0) = leaf() && w && d /* supervisor execute / def sx(dummy: Int = 0) = leaf() && x /* full permission: writable and executable in user mode / def isFullPerm(dummy: Int = 0) = uw() && ux() } /* L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format / class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() } /* PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation / class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /* to n TLB / val requestor = Flipped(Vec(n, new TLBPTWIO)) /* to HellaCache / val mem = new HellaCacheIO /* to Core * * contains CSRs info and performance statistics / val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /* Arbiter to arbite request from n TLB / val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready \|\| l2_refill_wire \|\| arb.io.out.valid \|\| io.dpath.sfence.valid \|\| io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM \|\| !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /* current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} / val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /* tlb request / val r_req = Reg(new PTWReq) /* current selected way in arbitor / val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /* pte for 2-stage translation / val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /* 2-stage translation both enable / val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r \|\| tmp.w \|\| tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)pgLevelBits-1, (pgLevels-2-i)pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /* address send to mem for enquerry / val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) \| vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr / val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBitsi), r_req.addr(((pgLevelBitsi) min vpnBits)-1, 0).padTo(pgLevelBitsi))) } /* PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation / def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid \| UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 \|\| usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss \|\| io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /* the valid vec for the selected set(including n ways) / val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) \| mask g(way) := Mux(r_pte.g, g(way) \| mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) \|\| s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid \|\| (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req \|\| state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit \|\| (state =/= s_wait1) \|\| resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor \|\| pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous \|\| pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final \|\| !r_req.vstage1 \|\| aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa \|\| arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), aux_pte.ppn((pgLevels-i-1)pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req \|\| state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) \|\| (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 \|\| do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages \|\| aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf \|\| (pf && stage2) resp_hr := !stage2 \|\| (!pf && !gf && pte.ur()) resp_hw := !stage2 \|\| (!pf && !gf && pte.uw()) resp_hx := !stage2 \|\| (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), r_req.addr(((pgLevels-i-1)pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn / private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /* use hgatp and vpn to construct a new ppn / private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range / private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW */ trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } }	module DTLB_8( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input [1:0] io_req_bits_size, // @[TLB.scala:320:14] input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_status_zero2, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_mbe, // @[TLB.scala:320:14] input io_ptw_status_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_status_sxl, // @[TLB.scala:320:14] input [1:0] io_ptw_status_uxl, // @[TLB.scala:320:14] input io_ptw_status_sd_rv32, // @[TLB.scala:320:14] input [7:0] io_ptw_status_zero1, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_xs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_status_vs, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_ube, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_upie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_hie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_status_uie, // @[TLB.scala:320:14] input io_ptw_hstatus_spvp, // @[TLB.scala:320:14] input io_ptw_hstatus_spv, // @[TLB.scala:320:14] input io_ptw_hstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_debug, // @[TLB.scala:320:14] input io_ptw_gstatus_cease, // @[TLB.scala:320:14] input io_ptw_gstatus_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14] input io_ptw_gstatus_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14] input io_ptw_gstatus_v, // @[TLB.scala:320:14] input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14] input io_ptw_gstatus_mpv, // @[TLB.scala:320:14] input io_ptw_gstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_mbe, // @[TLB.scala:320:14] input io_ptw_gstatus_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14] input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14] input io_ptw_gstatus_tsr, // @[TLB.scala:320:14] input io_ptw_gstatus_tw, // @[TLB.scala:320:14] input io_ptw_gstatus_tvm, // @[TLB.scala:320:14] input io_ptw_gstatus_mxr, // @[TLB.scala:320:14] input io_ptw_gstatus_sum, // @[TLB.scala:320:14] input io_ptw_gstatus_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14] input io_ptw_gstatus_spp, // @[TLB.scala:320:14] input io_ptw_gstatus_mpie, // @[TLB.scala:320:14] input io_ptw_gstatus_ube, // @[TLB.scala:320:14] input io_ptw_gstatus_spie, // @[TLB.scala:320:14] input io_ptw_gstatus_upie, // @[TLB.scala:320:14] input io_ptw_gstatus_mie, // @[TLB.scala:320:14] input io_ptw_gstatus_hie, // @[TLB.scala:320:14] input io_ptw_gstatus_sie, // @[TLB.scala:320:14] input io_ptw_gstatus_uie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[TLB.scala:318:7] wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7] wire [6:0] hr_array = 7'h7F; // @[TLB.scala:524:21] wire [6:0] hw_array = 7'h7F; // @[TLB.scala:525:21] wire [6:0] hx_array = 7'h7F; // @[TLB.scala:526:21] wire [6:0] _must_alloc_array_T_8 = 7'h7F; // @[TLB.scala:596:19] wire [6:0] _gf_ld_array_T_1 = 7'h7F; // @[TLB.scala:600:50] wire [5:0] stage2_bypass = 6'h3F; // @[TLB.scala:523:27] wire [5:0] _hr_array_T_4 = 6'h3F; // @[TLB.scala:524:111] wire [5:0] _hw_array_T_1 = 6'h3F; // @[TLB.scala:525:55] wire [5:0] _hx_array_T_1 = 6'h3F; // @[TLB.scala:526:55] wire [5:0] _gpa_hits_hit_mask_T_4 = 6'h3F; // @[TLB.scala:606:88] wire [5:0] gpa_hits_hit_mask = 6'h3F; // @[TLB.scala:606:82] wire [5:0] _gpa_hits_T_1 = 6'h3F; // @[TLB.scala:607:16] wire [5:0] gpa_hits = 6'h3F; // @[TLB.scala:607:14] wire [2:0] _state_vec_WIRE_0 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_1 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_2 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_3 = 3'h0; // @[Replacement.scala:305:25] wire [6:0] _gf_ld_array_T_2 = 7'h0; // @[TLB.scala:600:46] wire [6:0] gf_ld_array = 7'h0; // @[TLB.scala:600:24] wire [6:0] _gf_st_array_T_1 = 7'h0; // @[TLB.scala:601:53] wire [6:0] gf_st_array = 7'h0; // @[TLB.scala:601:24] wire [6:0] _gf_inst_array_T = 7'h0; // @[TLB.scala:602:36] wire [6:0] gf_inst_array = 7'h0; // @[TLB.scala:602:26] wire [6:0] gpa_hits_need_gpa_mask = 7'h0; // @[TLB.scala:605:73] wire [6:0] _io_resp_gf_ld_T_1 = 7'h0; // @[TLB.scala:637:58] wire [6:0] _io_resp_gf_st_T_1 = 7'h0; // @[TLB.scala:638:65] wire [6:0] _io_resp_gf_inst_T = 7'h0; // @[TLB.scala:639:48] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr = 39'h0; // @[TLB.scala:318:7, :320:14] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h1; // @[TLB.scala:318:7] wire priv_uses_vm = 1'h1; // @[TLB.scala:372:27] wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64] wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_37 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire _priv_rw_ok_T = 1'h1; // @[TLB.scala:513:24] wire _priv_rw_ok_T_1 = 1'h1; // @[TLB.scala:513:32] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [5:0] _priv_rw_ok_T_6 = 6'h0; // @[TLB.scala:513:75] wire [5:0] _stage1_bypass_T = 6'h0; // @[TLB.scala:517:27] wire [5:0] stage1_bypass = 6'h0; // @[TLB.scala:517:61] wire [5:0] _gpa_hits_T = 6'h0; // @[TLB.scala:607:30] wire [1:0] io_req_bits_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7, :320:14] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7] wire io_req_bits_v = 1'h0; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs1 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs2 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_asid = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hv = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hg = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire priv_s = 1'h0; // @[TLB.scala:370:20] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:183:37] wire _io_req_ready_T; // @[TLB.scala:631:25] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire _r_superpage_repl_addr_T_3 = 1'h0; // @[TLB.scala:757:8] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire hv_13 = 1'h0; // @[TLB.scala:721:36] wire hg_13 = 1'h0; // @[TLB.scala:722:36] wire hv_14 = 1'h0; // @[TLB.scala:721:36] wire hg_14 = 1'h0; // @[TLB.scala:722:36] wire hv_15 = 1'h0; // @[TLB.scala:721:36] wire hg_15 = 1'h0; // @[TLB.scala:722:36] wire hv_16 = 1'h0; // @[TLB.scala:721:36] wire hg_16 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_17 = 1'h0; // @[TLB.scala:721:36] wire hg_17 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire [1:0] io_resp_size = io_req_bits_size_0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd = io_req_bits_cmd_0; // @[TLB.scala:318:7] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_ma_st_T; // @[TLB.scala:646:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld; // @[TLB.scala:318:7] wire io_resp_pf_st; // @[TLB.scala:318:7] wire io_resp_pf_inst; // @[TLB.scala:318:7] wire io_resp_ae_ld; // @[TLB.scala:318:7] wire io_resp_ae_st; // @[TLB.scala:318:7] wire io_resp_ae_inst; // @[TLB.scala:318:7] wire io_resp_ma_ld; // @[TLB.scala:318:7] wire io_resp_ma_st; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa; // @[TLB.scala:318:7] wire io_resp_cacheable; // @[TLB.scala:318:7] wire io_resp_must_alloc; // @[TLB.scala:318:7] wire io_resp_prefetchable; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [1:0] memIdx = vpn[1:0]; // @[package.scala:163:13] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_3_valid_0; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_9 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] wire _r_superpage_repl_addr_T = superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:16] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_11 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [1:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T; // @[TLB.scala:399:{31,45}] wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_25 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_25; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_25; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T \| _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 \| io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, 2'h0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 \| _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 \| _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 \| _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 \| _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 \| _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 \| _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 \| _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 \| _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 \| _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 \| _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 \| _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 \| _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 \| _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 \| _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire [3:0][26:0] _GEN_4 = {{sectored_entries_3_0_tag_vpn}, {sectored_entries_2_0_tag_vpn}, {sectored_entries_1_0_tag_vpn}, {sectored_entries_0_0_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_5 = {{sectored_entries_3_0_tag_v}, {sectored_entries_2_0_tag_v}, {sectored_entries_1_0_tag_v}, {sectored_entries_0_0_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_6 = {{sectored_entries_3_0_data_0}, {sectored_entries_2_0_data_0}, {sectored_entries_1_0_data_0}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_6[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_7 = {{sectored_entries_3_0_valid_0}, {sectored_entries_2_0_valid_0}, {sectored_entries_1_0_valid_0}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_8 = {{sectored_entries_3_1_tag_vpn}, {sectored_entries_2_1_tag_vpn}, {sectored_entries_1_1_tag_vpn}, {sectored_entries_0_1_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_9 = {{sectored_entries_3_1_tag_v}, {sectored_entries_2_1_tag_v}, {sectored_entries_1_1_tag_v}, {sectored_entries_0_1_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_10 = {{sectored_entries_3_1_data_0}, {sectored_entries_2_1_data_0}, {sectored_entries_1_1_data_0}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_10[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_11 = {{sectored_entries_3_1_valid_0}, {sectored_entries_2_1_valid_0}, {sectored_entries_1_1_valid_0}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_12 = {{sectored_entries_3_2_tag_vpn}, {sectored_entries_2_2_tag_vpn}, {sectored_entries_1_2_tag_vpn}, {sectored_entries_0_2_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_13 = {{sectored_entries_3_2_tag_v}, {sectored_entries_2_2_tag_v}, {sectored_entries_1_2_tag_v}, {sectored_entries_0_2_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_14 = {{sectored_entries_3_2_data_0}, {sectored_entries_2_2_data_0}, {sectored_entries_1_2_data_0}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_14[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_15 = {{sectored_entries_3_2_valid_0}, {sectored_entries_2_2_valid_0}, {sectored_entries_1_2_valid_0}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_16 = {{sectored_entries_3_3_tag_vpn}, {sectored_entries_2_3_tag_vpn}, {sectored_entries_1_3_tag_vpn}, {sectored_entries_0_3_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_17 = {{sectored_entries_3_3_tag_v}, {sectored_entries_2_3_tag_v}, {sectored_entries_1_3_tag_v}, {sectored_entries_0_3_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_18 = {{sectored_entries_3_3_data_0}, {sectored_entries_2_3_data_0}, {sectored_entries_1_3_data_0}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_18[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_19 = {{sectored_entries_3_3_valid_0}, {sectored_entries_2_3_valid_0}, {sectored_entries_1_3_valid_0}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [26:0] _GEN_20 = _GEN_4[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T; // @[TLB.scala:174:61] assign _sector_hits_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_1 = _sector_hits_T; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_2 = _sector_hits_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_4 = _sector_hits_T_2 & _sector_hits_T_3; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _GEN_7[memIdx] & _sector_hits_T_4; // @[package.scala:163:13] wire [26:0] _GEN_21 = _GEN_8[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_5; // @[TLB.scala:174:61] assign _sector_hits_T_5 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_6 = _sector_hits_T_5; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_7 = _sector_hits_T_6 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_8 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_9 = _sector_hits_T_7 & _sector_hits_T_8; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _GEN_11[memIdx] & _sector_hits_T_9; // @[package.scala:163:13] wire [26:0] _GEN_22 = _GEN_12[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_10; // @[TLB.scala:174:61] assign _sector_hits_T_10 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_11 = _sector_hits_T_10; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_12 = _sector_hits_T_11 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_13 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_14 = _sector_hits_T_12 & _sector_hits_T_13; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _GEN_15[memIdx] & _sector_hits_T_14; // @[package.scala:163:13] wire [26:0] _GEN_23 = _GEN_16[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_15; // @[TLB.scala:174:61] assign _sector_hits_T_15 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_16 = _sector_hits_T_15; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_17 = _sector_hits_T_16 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_18 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_19 = _sector_hits_T_17 & _sector_hits_T_18; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _GEN_19[memIdx] & _sector_hits_T_19; // @[package.scala:163:13] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_1876 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_24; // @[TLB.scala:183:52] assign _hitsVec_T_24 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_29; // @[TLB.scala:183:52] assign _hitsVec_T_29 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_34; // @[TLB.scala:183:52] assign _hitsVec_T_34 = _T_1876; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_24 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_24; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_8 = superpage_hits_ignore_1 \| _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire [26:0] _hitsVec_T_1 = _hitsVec_T; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_5 = _GEN_7[memIdx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_7 = _hitsVec_T_6; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_11 = _GEN_11[memIdx] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_13 = _hitsVec_T_12; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_17 = _GEN_15[memIdx] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_19 = _hitsVec_T_18; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_23 = _GEN_19[memIdx] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_25 = _hitsVec_T_24[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_26 = _hitsVec_T_25 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_27 = _hitsVec_T_26; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_28 = hitsVec_tagMatch & _hitsVec_T_27; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_30 = _hitsVec_T_29[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_31 = _hitsVec_T_30 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_32 = hitsVec_ignore_1 \| _hitsVec_T_31; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_33 = _hitsVec_T_28 & _hitsVec_T_32; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_38 = _hitsVec_T_33; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_35 = _hitsVec_T_34[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_36 = _hitsVec_T_35 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire hitsVec_4 = vm_enabled & _hitsVec_T_38; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_1 = special_entry_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_1974 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_39; // @[TLB.scala:183:52] assign _hitsVec_T_39 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_44; // @[TLB.scala:183:52] assign _hitsVec_T_44 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_49; // @[TLB.scala:183:52] assign _hitsVec_T_49 = _T_1974; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_40 = _hitsVec_T_39[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_41 = _hitsVec_T_40 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_42 = _hitsVec_T_41; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_43 = hitsVec_tagMatch_1 & _hitsVec_T_42; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_45 = _hitsVec_T_44[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_46 = _hitsVec_T_45 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_47 = hitsVec_ignore_4 \| _hitsVec_T_46; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_48 = _hitsVec_T_43 & _hitsVec_T_47; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_5 = _hitsVec_ignore_T_5; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_50 = _hitsVec_T_49[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_51 = _hitsVec_T_50 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_52 = hitsVec_ignore_5 \| _hitsVec_T_51; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_53 = _hitsVec_T_48 & _hitsVec_T_52; // @[TLB.scala:183:{29,40}] wire hitsVec_5 = vm_enabled & _hitsVec_T_53; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo = {real_hits_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_hi = {real_hits_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [5:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [6:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_25 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_27 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_28 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_29 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_30 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_31 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_32 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [1:0] r_memIdx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [2:0] sectored_entries_0_data_0_lo_lo_hi = {sectored_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_data_0_lo_lo = {sectored_entries_0_data_0_lo_lo_hi, sectored_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_lo_hi_lo = {sectored_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_lo_hi_hi = {sectored_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_lo_hi = {sectored_entries_0_data_0_lo_hi_hi, sectored_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_data_0_lo = {sectored_entries_0_data_0_lo_hi, sectored_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_lo_lo = {sectored_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_hi_lo_hi = {sectored_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_hi_lo = {sectored_entries_0_data_0_hi_lo_hi, sectored_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_hi_lo = {sectored_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_data_0_hi_hi_hi = {sectored_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_data_0_hi_hi = {sectored_entries_0_data_0_hi_hi_hi, sectored_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_data_0_hi = {sectored_entries_0_data_0_hi_hi, sectored_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_data_0_T = {sectored_entries_0_data_0_hi, sectored_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_lo_hi = {sectored_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_1_data_0_lo_lo = {sectored_entries_1_data_0_lo_lo_hi, sectored_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_hi_lo = {sectored_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_lo_hi_hi = {sectored_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_lo_hi = {sectored_entries_1_data_0_lo_hi_hi, sectored_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_1_data_0_lo = {sectored_entries_1_data_0_lo_hi, sectored_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_lo_lo = {sectored_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_hi_lo_hi = {sectored_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_hi_lo = {sectored_entries_1_data_0_hi_lo_hi, sectored_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_hi_lo = {sectored_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_1_data_0_hi_hi_hi = {sectored_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_1_data_0_hi_hi = {sectored_entries_1_data_0_hi_hi_hi, sectored_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_1_data_0_hi = {sectored_entries_1_data_0_hi_hi, sectored_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_1_data_0_T = {sectored_entries_1_data_0_hi, sectored_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_lo_hi = {sectored_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_2_data_0_lo_lo = {sectored_entries_2_data_0_lo_lo_hi, sectored_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_hi_lo = {sectored_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_lo_hi_hi = {sectored_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_lo_hi = {sectored_entries_2_data_0_lo_hi_hi, sectored_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_2_data_0_lo = {sectored_entries_2_data_0_lo_hi, sectored_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_lo_lo = {sectored_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_hi_lo_hi = {sectored_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_hi_lo = {sectored_entries_2_data_0_hi_lo_hi, sectored_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_hi_lo = {sectored_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_2_data_0_hi_hi_hi = {sectored_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_2_data_0_hi_hi = {sectored_entries_2_data_0_hi_hi_hi, sectored_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_2_data_0_hi = {sectored_entries_2_data_0_hi_hi, sectored_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_2_data_0_T = {sectored_entries_2_data_0_hi, sectored_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_lo_hi = {sectored_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_3_data_0_lo_lo = {sectored_entries_3_data_0_lo_lo_hi, sectored_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_hi_lo = {sectored_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_lo_hi_hi = {sectored_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_lo_hi = {sectored_entries_3_data_0_lo_hi_hi, sectored_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_3_data_0_lo = {sectored_entries_3_data_0_lo_hi, sectored_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_lo_lo = {sectored_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_hi_lo_hi = {sectored_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_hi_lo = {sectored_entries_3_data_0_hi_lo_hi, sectored_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_hi_lo = {sectored_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_3_data_0_hi_hi_hi = {sectored_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_3_data_0_hi_hi = {sectored_entries_3_data_0_hi_hi_hi, sectored_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_3_data_0_hi = {sectored_entries_3_data_0_hi_hi, sectored_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_3_data_0_T = {sectored_entries_3_data_0_hi, sectored_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire _entries_T; // @[TLB.scala:170:77] assign _entries_T = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T; // @[TLB.scala:170:77] assign _entries_T_1 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_22; // @[TLB.scala:170:77] wire [19:0] _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire _entries_T_24; // @[TLB.scala:170:77] wire _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_24 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_24; // @[TLB.scala:170:77] assign _entries_T_25 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_45; // @[TLB.scala:170:77] wire [19:0] _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire _entries_T_48; // @[TLB.scala:170:77] wire _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_47; // @[TLB.scala:170:77] assign _entries_T_48 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_48; // @[TLB.scala:170:77] assign _entries_T_49 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_68; // @[TLB.scala:170:77] wire [19:0] _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire _entries_T_72; // @[TLB.scala:170:77] wire _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_71; // @[TLB.scala:170:77] assign _entries_T_72 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_72; // @[TLB.scala:170:77] assign _entries_T_73 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_91; // @[TLB.scala:170:77] wire [19:0] _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire _entries_T_96; // @[TLB.scala:170:77] wire _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_95; // @[TLB.scala:170:77] assign _entries_T_96 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_96; // @[TLB.scala:170:77] assign _entries_T_97 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_114; // @[TLB.scala:170:77] wire [19:0] _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire _entries_T_120; // @[TLB.scala:170:77] wire _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_119; // @[TLB.scala:170:77] assign _entries_T_120 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_120; // @[TLB.scala:170:77] assign _entries_T_121 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_137; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_4_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] \| _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] \| _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_5_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] \| _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_3 = _ppn_ignore_T_3; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_13 = ppn_ignore_3 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] \| _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_17 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_18 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_19 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_20 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_21 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_22 = hitsVec_4 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_23 = hitsVec_5 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_24 = _ppn_T ? _ppn_T_17 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_25 = _ppn_T_18 \| _ppn_T_19; // @[Mux.scala:30:73] wire [19:0] _ppn_T_26 = _ppn_T_25 \| _ppn_T_20; // @[Mux.scala:30:73] wire [19:0] _ppn_T_27 = _ppn_T_26 \| _ppn_T_21; // @[Mux.scala:30:73] wire [19:0] _ppn_T_28 = _ppn_T_27 \| _ppn_T_22; // @[Mux.scala:30:73] wire [19:0] _ppn_T_29 = _ppn_T_28 \| _ppn_T_23; // @[Mux.scala:30:73] wire [19:0] _ppn_T_30 = _ppn_T_29 \| _ppn_T_24; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_30; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo = {final_ae_array_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi = {final_ae_array_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [6:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [6:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [6:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire [1:0] _GEN_33 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_34 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_2; // @[package.scala:45:27] wire [5:0] priv_rw_ok = _priv_rw_ok_T_3; // @[TLB.scala:513:{23,70}] wire [2:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo = {priv_x_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi = {priv_x_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [5:0] priv_x_ok = _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [5:0] _stage1_bypass_T_2 = {6{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo = {stage1_bypass_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi = {stage1_bypass_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [5:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 \| _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo = {r_array_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi = {r_array_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_35 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_1 = _GEN_35; // @[package.scala:45:27] wire [1:0] x_array_lo_hi; // @[package.scala:45:27] assign x_array_lo_hi = _GEN_35; // @[package.scala:45:27] wire [2:0] r_array_lo_1 = {r_array_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_36 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_1 = _GEN_36; // @[package.scala:45:27] wire [1:0] x_array_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi = _GEN_36; // @[package.scala:45:27] wire [2:0] r_array_hi_1 = {r_array_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [5:0] _r_array_T_2 = mxr ? _r_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _r_array_T_3 = _r_array_T \| _r_array_T_2; // @[package.scala:45:27] wire [5:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [5:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [6:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [6:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo = {w_array_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi = {w_array_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [5:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [5:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [6:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo = {x_array_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_hi = {x_array_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [5:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [5:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [6:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo = {hr_array_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi = {hr_array_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_37 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_1 = _GEN_37; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi; // @[package.scala:45:27] assign hx_array_lo_hi = _GEN_37; // @[package.scala:45:27] wire [2:0] hr_array_lo_1 = {hr_array_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_38 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_1 = _GEN_38; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi = _GEN_38; // @[package.scala:45:27] wire [2:0] hr_array_hi_1 = {hr_array_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [5:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _hr_array_T_3 = _hr_array_T \| _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo = {hw_array_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi = {hw_array_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo = {hx_array_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_hi = {hx_array_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo = {_entries_barrier_1_io_y_pr, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi = {_entries_barrier_4_io_y_pr, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi = {pr_array_hi_hi, _entries_barrier_2_io_y_pr}; // @[package.scala:45:27, :267:25] wire [4:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [6:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [6:0] _GEN_39 = ptw_ae_array \| final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [6:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_39; // @[TLB.scala:529:104] wire [6:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :531:104] wire [6:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :533:104] wire [6:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [6:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo = {_entries_barrier_1_io_y_pw, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi = {_entries_barrier_4_io_y_pw, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi = {pw_array_hi_hi, _entries_barrier_2_io_y_pw}; // @[package.scala:45:27, :267:25] wire [4:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [6:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [6:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [6:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo = {_entries_barrier_1_io_y_px, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi = {_entries_barrier_4_io_y_px, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi = {px_array_hi_hi, _entries_barrier_2_io_y_px}; // @[package.scala:45:27, :267:25] wire [4:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [6:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [6:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [6:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo = {_entries_barrier_1_io_y_eff, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi = {_entries_barrier_4_io_y_eff, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi = {eff_array_hi_hi, _entries_barrier_2_io_y_eff}; // @[package.scala:45:27, :267:25] wire [4:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [6:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_40 = {_entries_barrier_1_io_y_c, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo; // @[package.scala:45:27] assign c_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo; // @[package.scala:45:27] assign prefetchable_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] _GEN_41 = {_entries_barrier_4_io_y_c, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [2:0] c_array_hi = {c_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [6:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [6:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo = {_entries_barrier_1_io_y_ppp, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi = {_entries_barrier_4_io_y_ppp, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi = {ppp_array_hi_hi, _entries_barrier_2_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [4:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [6:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo = {_entries_barrier_1_io_y_paa, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi = {_entries_barrier_4_io_y_paa, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi = {paa_array_hi_hi, _entries_barrier_2_io_y_paa}; // @[package.scala:45:27, :267:25] wire [4:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [6:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo = {_entries_barrier_1_io_y_pal, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi = {_entries_barrier_4_io_y_pal, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi = {pal_array_hi_hi, _entries_barrier_2_io_y_pal}; // @[package.scala:45:27, :267:25] wire [4:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [6:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [6:0] ppp_array_if_cached = ppp_array \| c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [6:0] paa_array_if_cached = paa_array \| c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [6:0] pal_array_if_cached = pal_array \| c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_hi = {prefetchable_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [6:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}] wire misaligned = \|_misaligned_T_3; // @[TLB.scala:550:{39,77}] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:550:77, :559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 \| _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _GEN_42 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_42; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_42; // @[package.scala:16:47] wire _GEN_43 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_43; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_43; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_43; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T \| _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire cmd_lrsc = _cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_44 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_44; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_44; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_45; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_45; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_46; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_46; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_46; // @[package.scala:16:47] wire _GEN_47 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_47; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_47; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_47; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T \| _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 \| _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 \| _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire cmd_amo_logical = _cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_48 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_48; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_48; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_49; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_49; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_50; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_50; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_51; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_51; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_51; // @[package.scala:16:47] wire _GEN_52 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_52; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_52; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_52; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T \| _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 \| _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 \| _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 \| _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire cmd_amo_arithmetic = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_53 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41] wire cmd_put_partial; // @[TLB.scala:573:41] assign cmd_put_partial = _GEN_53; // @[TLB.scala:573:41] wire _cmd_write_T_1; // @[Consts.scala:90:49] assign _cmd_write_T_1 = _GEN_53; // @[TLB.scala:573:41] wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _GEN_54 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_1; // @[package.scala:16:47] assign _cmd_read_T_1 = _GEN_54; // @[package.scala:16:47] wire _cmd_readx_T; // @[TLB.scala:575:56] assign _cmd_readx_T = _GEN_54; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T \| _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 \| _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 \| _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 \| _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 \| _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 \| _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 \| _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 \| _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 \| _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 \| _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 \| _cmd_read_T_22; // @[package.scala:81:59] wire cmd_read = _cmd_read_T_6 \| _cmd_read_T_23; // @[package.scala:81:59] wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7] wire _cmd_write_T_2 = _cmd_write_T \| _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 \| _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 \| _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 \| _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 \| _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 \| _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 \| _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 \| _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 \| _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 \| _cmd_write_T_20; // @[package.scala:81:59] wire cmd_write = _cmd_write_T_4 \| _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = _cmd_write_perms_T \| _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire cmd_write_perms = cmd_write \| _cmd_write_perms_T_2; // @[package.scala:81:59] wire [6:0] _ae_array_T = misaligned ? eff_array : 7'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [6:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [6:0] _ae_array_T_2 = cmd_lrsc ? _ae_array_T_1 : 7'h0; // @[TLB.scala:570:33, :583:{8,19}] wire [6:0] ae_array = _ae_array_T \| _ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [6:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [6:0] _ae_ld_array_T_1 = ae_array \| _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [6:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 7'h0; // @[TLB.scala:586:{24,44}] wire [6:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [6:0] _ae_st_array_T_1 = ae_array \| _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [6:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 7'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [6:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [6:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 7'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [6:0] _ae_st_array_T_5 = _ae_st_array_T_2 \| _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [6:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [6:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_6 : 7'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [6:0] _ae_st_array_T_8 = _ae_st_array_T_5 \| _ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [6:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [6:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_9 : 7'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [6:0] ae_st_array = _ae_st_array_T_8 \| _ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [6:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [6:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 7'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [6:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [6:0] _must_alloc_array_T_3 = cmd_amo_logical ? _must_alloc_array_T_2 : 7'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [6:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 \| _must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [6:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [6:0] _must_alloc_array_T_6 = cmd_amo_arithmetic ? _must_alloc_array_T_5 : 7'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [6:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 \| _must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [6:0] _must_alloc_array_T_9 = {7{cmd_lrsc}}; // @[TLB.scala:570:33, :596:8] wire [6:0] must_alloc_array = _must_alloc_array_T_7 \| _must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [6:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [6:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [6:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [6:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 \| ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [6:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [6:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [6:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 7'h0; // @[TLB.scala:597:{24,104}] wire [6:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [6:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [6:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [6:0] _pf_st_array_T_3 = _pf_st_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [6:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [6:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [6:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 7'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [6:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [6:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [6:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [6:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [6:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [6:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [6:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [6:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [6:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [6:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [6:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [6:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [4:0] _gpa_hits_hit_mask_T_2 = {5{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = \|real_hits; // @[package.scala:45:27] wire tlb_hit = \|_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [2:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_vec_1; // @[Replacement.scala:305:17] reg [2:0] state_vec_2; // @[Replacement.scala:305:17] reg [2:0] state_vec_3; // @[Replacement.scala:305:17] wire [1:0] _GEN_55 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo; // @[OneHot.scala:21:45] assign lo = _GEN_55; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo = _GEN_55; // @[OneHot.scala:21:45] wire [1:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_56 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi; // @[OneHot.scala:21:45] assign hi = _GEN_56; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi = _GEN_56; // @[OneHot.scala:21:45] wire [1:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_vec_touch_way_sized = {\|hi_1, hi_1[1] \| lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_set_left_older_T = state_vec_touch_way_sized[1]; // @[package.scala:163:13] wire state_vec_set_left_older = ~_state_vec_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [3:0][2:0] _GEN_57 = {{state_vec_3}, {state_vec_2}, {state_vec_1}, {state_vec_0}}; // @[package.scala:163:13] wire state_vec_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13] wire state_vec_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13] wire _state_vec_T = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_4 = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_1 = _state_vec_T; // @[package.scala:163:13] wire _state_vec_T_2 = ~_state_vec_T_1; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_3 = state_vec_set_left_older ? state_vec_left_subtree_state : _state_vec_T_2; // @[package.scala:163:13] wire _state_vec_T_5 = _state_vec_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_vec_T_6 = ~_state_vec_T_5; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_7 = state_vec_set_left_older ? _state_vec_T_6 : state_vec_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_hi = {state_vec_set_left_older, _state_vec_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_T_8 = {state_vec_hi, _state_vec_T_7}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _multipleHits_T = real_hits[2:0]; // @[package.scala:45:27] wire _multipleHits_T_1 = _multipleHits_T[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_1; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_2 = _multipleHits_T[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_3 = _multipleHits_T_2[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_3; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_4 = _multipleHits_T_2[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_4; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 \| multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_6 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_6; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_7 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne \| multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_8 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_7 \| _multipleHits_T_8; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_9 = real_hits[5:3]; // @[package.scala:45:27] wire _multipleHits_T_10 = _multipleHits_T_9[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_10; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_11 = _multipleHits_T_9[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_12 = _multipleHits_T_11[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_12; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_13 = _multipleHits_T_11[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_13; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 \| multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_15 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_15; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_16 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 \| multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_17 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_16 \| _multipleHits_T_17; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_18 = multipleHits_leftOne_2 \| multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo \| multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_19 \| _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28] wire [6:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = \|_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T \| _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28] wire [6:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64] wire _io_resp_pf_st_T_2 = \|_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T \| _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}] assign io_resp_pf_st = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48] wire [6:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = \|_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va \| _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [6:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = \|_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [6:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33] assign _io_resp_ae_st_T_1 = \|_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign io_resp_ae_st = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41] wire [6:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [6:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = \|_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31] assign io_resp_ma_ld = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31] assign io_resp_ma_st = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31] wire [6:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = \|_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [6:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43] assign _io_resp_must_alloc_T_1 = \|_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign io_resp_must_alloc = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51] wire [6:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = \|_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T \| tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 \| multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire _r_superpage_repl_addr_T_1 = ~superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:43] wire _r_superpage_repl_addr_T_2 = _r_superpage_repl_addr_T_1; // @[OneHot.scala:48:45] wire r_sectored_repl_addr_left_subtree_older = _GEN_57[memIdx][2]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_sectored_repl_addr_valids_lo = {_GEN_11[memIdx], _GEN_7[memIdx]}; // @[package.scala:45:27, :163:13] wire [1:0] r_sectored_repl_addr_valids_hi = {_GEN_19[memIdx], _GEN_15[memIdx]}; // @[package.scala:45:27, :163:13] wire [3:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_4 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_sectored_repl_addr_T_5 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_6 = _r_sectored_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_7 = _r_sectored_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_8 = _r_sectored_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_9 = _r_sectored_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_10 = {1'h1, ~_r_sectored_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_11 = _r_sectored_repl_addr_T_7 ? 2'h1 : _r_sectored_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_6 ? 2'h0 : _r_sectored_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_4 ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_12; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 \| sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T \| sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 \| sector_hits_3; // @[package.scala:81:59] wire [3:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = \|r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 \| r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_3 = _r_sectored_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_4 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45] wire _tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire tagMatch = superpage_entries_0_valid_0 & _tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire ignore_1 = _ignore_T_1; // @[TLB.scala:182:{28,34}] wire _ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire _tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire tagMatch_1 = special_entry_valid_0 & _tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire ignore_4 = _ignore_T_4; // @[TLB.scala:182:{28,34}] wire _ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire ignore_5 = _ignore_T_5; // @[TLB.scala:182:{28,34}] wire _T_12 = io_req_valid_0 & vm_enabled; // @[TLB.scala:318:7, :399:61, :617:22] wire _T_15 = sector_hits_0 \| sector_hits_1 \| sector_hits_2 \| sector_hits_3; // @[package.scala:81:59] wire _GEN_58 = do_refill & ~io_ptw_resp_bits_homogeneous_0; // @[TLB.scala:211:18, :318:7, :346:56, :408:29, :446:20, :474:{39,70}] wire _GEN_59 = ~do_refill \| ~io_ptw_resp_bits_homogeneous_0 \| io_ptw_resp_bits_level_0[1]; // @[TLB.scala:318:7, :341:30, :408:29, :446:20, :474:70, :476:{40,58}] wire _T_4 = waddr_1 == 2'h0; // @[TLB.scala:485:22, :486:75] wire _GEN_60 = r_memIdx == 2'h0; // @[package.scala:163:13] wire _GEN_61 = r_memIdx == 2'h1; // @[package.scala:163:13] wire _GEN_62 = r_memIdx == 2'h2; // @[package.scala:163:13] wire _GEN_63 = ~io_ptw_resp_bits_homogeneous_0 \| ~(io_ptw_resp_bits_level_0[1]); // @[TLB.scala:318:7, :339:29, :474:{39,70}, :476:{40,58}, :486:84] wire _GEN_64 = ~do_refill \| _GEN_63 \| ~(_T_4 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_65 = ~do_refill \| _GEN_63 \| ~(_T_4 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_66 = ~do_refill \| _GEN_63 \| ~(_T_4 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_67 = ~do_refill \| _GEN_63 \| ~(_T_4 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_68 = invalidate_refill & _GEN_60; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_69 = ~do_refill \| _GEN_63 \| ~_T_4; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_70 = invalidate_refill & _GEN_61; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_71 = invalidate_refill & _GEN_62; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_72 = invalidate_refill & (&r_memIdx); // @[package.scala:163:13] wire _T_6 = waddr_1 == 2'h1; // @[TLB.scala:197:28, :485:22, :486:75] wire _GEN_73 = ~do_refill \| _GEN_63 \| ~(_T_6 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_74 = ~do_refill \| _GEN_63 \| ~(_T_6 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_75 = ~do_refill \| _GEN_63 \| ~(_T_6 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_76 = ~do_refill \| _GEN_63 \| ~(_T_6 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_77 = ~do_refill \| _GEN_63 \| ~_T_6; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _T_8 = waddr_1 == 2'h2; // @[TLB.scala:485:22, :486:75] wire _GEN_78 = ~do_refill \| _GEN_63 \| ~(_T_8 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_79 = ~do_refill \| _GEN_63 \| ~(_T_8 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_80 = ~do_refill \| _GEN_63 \| ~(_T_8 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_81 = ~do_refill \| _GEN_63 \| ~(_T_8 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_82 = ~do_refill \| _GEN_63 \| ~_T_8; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_83 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_84 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_85 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_86 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_87 = ~do_refill \| _GEN_63 \| ~(&waddr_1); // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _T_2491 = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] wire _T_24 = io_req_ready_0 & io_req_valid_0 & tlb_miss; // @[Decoupled.scala:51:35] wire _T_2490 = multipleHits \| reset; // @[Misc.scala:183:49] always @(posedge clock) begin // @[TLB.scala:318:7] if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_0_tag_v <= _GEN_64 & sectored_entries_0_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_0_tag_v) & (_GEN_69 ? sectored_entries_0_0_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_1_tag_v <= _GEN_73 & sectored_entries_0_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_1_tag_v) & (_GEN_77 ? sectored_entries_0_1_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_2_tag_v <= _GEN_78 & sectored_entries_0_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_2_tag_v) & (_GEN_82 ? sectored_entries_0_2_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_3_tag_v <= _GEN_83 & sectored_entries_0_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_3_tag_v) & (_GEN_87 ? sectored_entries_0_3_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_0_tag_v <= _GEN_65 & sectored_entries_1_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_0_tag_v) & (_GEN_69 ? sectored_entries_1_0_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_1_tag_v <= _GEN_74 & sectored_entries_1_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_1_tag_v) & (_GEN_77 ? sectored_entries_1_1_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_2_tag_v <= _GEN_79 & sectored_entries_1_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_2_tag_v) & (_GEN_82 ? sectored_entries_1_2_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_3_tag_v <= _GEN_84 & sectored_entries_1_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_3_tag_v) & (_GEN_87 ? sectored_entries_1_3_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_0_tag_v <= _GEN_66 & sectored_entries_2_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_0_tag_v) & (_GEN_69 ? sectored_entries_2_0_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_1_tag_v <= _GEN_75 & sectored_entries_2_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_1_tag_v) & (_GEN_77 ? sectored_entries_2_1_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_2_tag_v <= _GEN_80 & sectored_entries_2_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_2_tag_v) & (_GEN_82 ? sectored_entries_2_2_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_3_tag_v <= _GEN_85 & sectored_entries_2_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_3_tag_v) & (_GEN_87 ? sectored_entries_2_3_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_0_tag_v <= _GEN_67 & sectored_entries_3_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_0_tag_v) & (_GEN_69 ? sectored_entries_3_0_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_0_valid_0)); // @[package.scala:163:13] if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_1_tag_v <= _GEN_76 & sectored_entries_3_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_1_tag_v) & (_GEN_77 ? sectored_entries_3_1_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_1_valid_0)); // @[package.scala:163:13] if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_2_tag_v <= _GEN_81 & sectored_entries_3_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_2_tag_v) & (_GEN_82 ? sectored_entries_3_2_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_2_valid_0)); // @[package.scala:163:13] if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_3_tag_v <= _GEN_86 & sectored_entries_3_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_3_tag_v) & (_GEN_87 ? sectored_entries_3_3_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_3_valid_0)); // @[package.scala:163:13] if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_level <= {1'h0, _superpage_entries_0_level_T}; // @[package.scala:163:13] superpage_entries_0_tag_vpn <= r_refill_tag; // @[TLB.scala:341:30, :354:25] end superpage_entries_0_tag_v <= _GEN_59 & superpage_entries_0_tag_v; // @[TLB.scala:341:30, :446:20, :474:70, :476:58] if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_data_0 <= _superpage_entries_0_data_0_T; // @[TLB.scala:217:24, :341:30] superpage_entries_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~superpage_entries_0_tag_v) & (_GEN_59 ? superpage_entries_0_valid_0 : ~invalidate_refill); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :341:30, :410:88, :446:20, :474:70, :476:58, :480:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_58) begin // @[TLB.scala:211:18, :346:56, :446:20, :474:70] special_entry_level <= _special_entry_level_T; // @[package.scala:163:13] special_entry_tag_vpn <= r_refill_tag; // @[TLB.scala:346:56, :354:25] special_entry_data_0 <= _special_entry_data_0_T; // @[TLB.scala:217:24, :346:56] end special_entry_tag_v <= ~_GEN_58 & special_entry_tag_v; // @[TLB.scala:211:18, :212:16, :346:56, :446:20, :474:70] special_entry_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~special_entry_tag_v) & (_GEN_58 \| special_entry_valid_0); // @[TLB.scala:211:18, :216:16, :220:46, :223:{19,32,36}, :318:7, :346:56, :446:20, :474:70, :718:19, :723:42, :728:46, :732:{24,41}] if (_T_24) begin // @[Decoupled.scala:51:35] r_refill_tag <= vpn; // @[TLB.scala:335:30, :354:25] r_sectored_repl_addr <= _r_sectored_repl_addr_T_13; // @[TLB.scala:356:33, :757:8] r_sectored_hit_valid <= _r_sectored_hit_valid_T_2; // @[package.scala:81:59] r_sectored_hit_bits <= _r_sectored_hit_bits_T_4; // @[OneHot.scala:32:10] r_superpage_hit_valid <= superpage_hits_0; // @[TLB.scala:183:29, :358:28] r_need_gpa <= tlb_hit_if_not_gpa_miss; // @[TLB.scala:361:23, :610:43] end r_gpa_valid <= ~_T_2491 & (do_refill ? io_ptw_resp_bits_gpa_valid_0 : r_gpa_valid); // @[Decoupled.scala:51:35] if (do_refill) begin // @[TLB.scala:408:29] r_gpa <= io_ptw_resp_bits_gpa_bits_0; // @[TLB.scala:318:7, :363:18] r_gpa_is_pte <= io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :365:25] end if (_T_2491) // @[Decoupled.scala:51:35] r_gpa_vpn <= r_refill_tag; // @[TLB.scala:354:25, :364:22] if (reset) begin // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] state_vec_0 <= 3'h0; // @[Replacement.scala:305:17] state_vec_1 <= 3'h0; // @[Replacement.scala:305:17] state_vec_2 <= 3'h0; // @[Replacement.scala:305:17] state_vec_3 <= 3'h0; // @[Replacement.scala:305:17] end else begin // @[TLB.scala:318:7] if (io_ptw_resp_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (state == 2'h2 & io_sfence_valid_0) // @[TLB.scala:318:7, :352:22, :709:{17,28}] state <= 2'h3; // @[TLB.scala:352:22] else if (_T_25) begin // @[package.scala:16:47] if (io_ptw_req_ready_0) // @[TLB.scala:318:7] state <= _state_T; // @[TLB.scala:352:22, :704:45] else if (io_sfence_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] end else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] if (_T_12 & _T_15 & memIdx == 2'h0) // @[package.scala:81:59, :163:13] state_vec_0 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h1) // @[package.scala:81:59, :163:13] state_vec_1 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h2) // @[package.scala:81:59, :163:13] state_vec_2 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & (&memIdx)) // @[package.scala:81:59, :163:13] state_vec_3 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] end always @(posedge) OptimizationBarrier_TLBEntryData_70 mpu_ppn_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_mpu_ppn_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_mpu_ppn_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_mpu_ppn_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_mpu_ppn_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_mpu_ppn_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_mpu_ppn_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_mpu_ppn_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_mpu_ppn_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_mpu_ppn_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_mpu_ppn_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_mpu_ppn_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_mpu_ppn_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_mpu_ppn_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_mpu_ppn_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_mpu_ppn_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_mpu_ppn_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_mpu_ppn_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_mpu_ppn_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_mpu_ppn_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_mpu_ppn_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_mpu_ppn_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_mpu_ppn_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_mpu_ppn_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_mpu_ppn_barrier_io_y_ppn) ); // @[package.scala:267:25] PMPChecker_s3_8 pmp ( // @[TLB.scala:416:19] .clock (clock), .reset (reset), .io_prv (mpu_priv[1:0]), // @[TLB.scala:415:27, :420:14] .io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_0_addr (io_ptw_pmp_0_addr_0), // @[TLB.scala:318:7] .io_pmp_0_mask (io_ptw_pmp_0_mask_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_1_addr (io_ptw_pmp_1_addr_0), // @[TLB.scala:318:7] .io_pmp_1_mask (io_ptw_pmp_1_mask_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_2_addr (io_ptw_pmp_2_addr_0), // @[TLB.scala:318:7] .io_pmp_2_mask (io_ptw_pmp_2_mask_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_3_addr (io_ptw_pmp_3_addr_0), // @[TLB.scala:318:7] .io_pmp_3_mask (io_ptw_pmp_3_mask_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_4_addr (io_ptw_pmp_4_addr_0), // @[TLB.scala:318:7] .io_pmp_4_mask (io_ptw_pmp_4_mask_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_5_addr (io_ptw_pmp_5_addr_0), // @[TLB.scala:318:7] .io_pmp_5_mask (io_ptw_pmp_5_mask_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_6_addr (io_ptw_pmp_6_addr_0), // @[TLB.scala:318:7] .io_pmp_6_mask (io_ptw_pmp_6_mask_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_7_addr (io_ptw_pmp_7_addr_0), // @[TLB.scala:318:7] .io_pmp_7_mask (io_ptw_pmp_7_mask_0), // @[TLB.scala:318:7] .io_addr (mpu_physaddr[31:0]), // @[TLB.scala:414:25, :417:15] .io_size (io_req_bits_size_0), // @[TLB.scala:318:7] .io_r (_pmp_io_r), .io_w (_pmp_io_w), .io_x (_pmp_io_x) ); // @[TLB.scala:416:19] PMAChecker_8 pma ( // @[TLB.scala:422:19] .clock (clock), .reset (reset), .io_paddr (mpu_physaddr), // @[TLB.scala:414:25] .io_resp_cacheable (cacheable), .io_resp_r (_pma_io_resp_r), .io_resp_w (_pma_io_resp_w), .io_resp_pp (_pma_io_resp_pp), .io_resp_al (_pma_io_resp_al), .io_resp_aa (_pma_io_resp_aa), .io_resp_x (_pma_io_resp_x), .io_resp_eff (_pma_io_resp_eff) ); // @[TLB.scala:422:19] assign newEntry_ppp = _pma_io_resp_pp; // @[TLB.scala:422:19, :449:24] assign newEntry_pal = _pma_io_resp_al; // @[TLB.scala:422:19, :449:24] assign newEntry_paa = _pma_io_resp_aa; // @[TLB.scala:422:19, :449:24] assign newEntry_eff = _pma_io_resp_eff; // @[TLB.scala:422:19, :449:24] OptimizationBarrier_TLBEntryData_71 entries_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_io_y_ppn), .io_y_u (_entries_barrier_io_y_u), .io_y_ae_ptw (_entries_barrier_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_io_y_ae_stage2), .io_y_pf (_entries_barrier_io_y_pf), .io_y_gf (_entries_barrier_io_y_gf), .io_y_sw (_entries_barrier_io_y_sw), .io_y_sx (_entries_barrier_io_y_sx), .io_y_sr (_entries_barrier_io_y_sr), .io_y_hw (_entries_barrier_io_y_hw), .io_y_hx (_entries_barrier_io_y_hx), .io_y_hr (_entries_barrier_io_y_hr), .io_y_pw (_entries_barrier_io_y_pw), .io_y_px (_entries_barrier_io_y_px), .io_y_pr (_entries_barrier_io_y_pr), .io_y_ppp (_entries_barrier_io_y_ppp), .io_y_pal (_entries_barrier_io_y_pal), .io_y_paa (_entries_barrier_io_y_paa), .io_y_eff (_entries_barrier_io_y_eff), .io_y_c (_entries_barrier_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_72 entries_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_2_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_2_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_2_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_2_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_2_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_2_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_2_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_2_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_2_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_2_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_2_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_2_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_2_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_2_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_2_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_2_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_2_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_2_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_2_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_2_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_2_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_2_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_1_io_y_ppn), .io_y_u (_entries_barrier_1_io_y_u), .io_y_ae_ptw (_entries_barrier_1_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_1_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_1_io_y_ae_stage2), .io_y_pf (_entries_barrier_1_io_y_pf), .io_y_gf (_entries_barrier_1_io_y_gf), .io_y_sw (_entries_barrier_1_io_y_sw), .io_y_sx (_entries_barrier_1_io_y_sx), .io_y_sr (_entries_barrier_1_io_y_sr), .io_y_hw (_entries_barrier_1_io_y_hw), .io_y_hx (_entries_barrier_1_io_y_hx), .io_y_hr (_entries_barrier_1_io_y_hr), .io_y_pw (_entries_barrier_1_io_y_pw), .io_y_px (_entries_barrier_1_io_y_px), .io_y_pr (_entries_barrier_1_io_y_pr), .io_y_ppp (_entries_barrier_1_io_y_ppp), .io_y_pal (_entries_barrier_1_io_y_pal), .io_y_paa (_entries_barrier_1_io_y_paa), .io_y_eff (_entries_barrier_1_io_y_eff), .io_y_c (_entries_barrier_1_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_73 entries_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_4_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_4_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_4_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_4_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_4_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_4_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_4_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_4_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_4_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_4_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_4_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_4_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_4_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_4_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_4_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_4_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_4_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_4_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_4_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_4_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_4_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_4_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_2_io_y_ppn), .io_y_u (_entries_barrier_2_io_y_u), .io_y_ae_ptw (_entries_barrier_2_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_2_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_2_io_y_ae_stage2), .io_y_pf (_entries_barrier_2_io_y_pf), .io_y_gf (_entries_barrier_2_io_y_gf), .io_y_sw (_entries_barrier_2_io_y_sw), .io_y_sx (_entries_barrier_2_io_y_sx), .io_y_sr (_entries_barrier_2_io_y_sr), .io_y_hw (_entries_barrier_2_io_y_hw), .io_y_hx (_entries_barrier_2_io_y_hx), .io_y_hr (_entries_barrier_2_io_y_hr), .io_y_pw (_entries_barrier_2_io_y_pw), .io_y_px (_entries_barrier_2_io_y_px), .io_y_pr (_entries_barrier_2_io_y_pr), .io_y_ppp (_entries_barrier_2_io_y_ppp), .io_y_pal (_entries_barrier_2_io_y_pal), .io_y_paa (_entries_barrier_2_io_y_paa), .io_y_eff (_entries_barrier_2_io_y_eff), .io_y_c (_entries_barrier_2_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_74 entries_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_6_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_6_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_6_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_6_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_6_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_6_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_6_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_6_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_6_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_6_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_6_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_6_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_6_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_6_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_6_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_6_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_6_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_6_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_6_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_6_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_6_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_6_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_3_io_y_ppn), .io_y_u (_entries_barrier_3_io_y_u), .io_y_ae_ptw (_entries_barrier_3_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_3_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_3_io_y_ae_stage2), .io_y_pf (_entries_barrier_3_io_y_pf), .io_y_gf (_entries_barrier_3_io_y_gf), .io_y_sw (_entries_barrier_3_io_y_sw), .io_y_sx (_entries_barrier_3_io_y_sx), .io_y_sr (_entries_barrier_3_io_y_sr), .io_y_hw (_entries_barrier_3_io_y_hw), .io_y_hx (_entries_barrier_3_io_y_hx), .io_y_hr (_entries_barrier_3_io_y_hr), .io_y_pw (_entries_barrier_3_io_y_pw), .io_y_px (_entries_barrier_3_io_y_px), .io_y_pr (_entries_barrier_3_io_y_pr), .io_y_ppp (_entries_barrier_3_io_y_ppp), .io_y_pal (_entries_barrier_3_io_y_pal), .io_y_paa (_entries_barrier_3_io_y_paa), .io_y_eff (_entries_barrier_3_io_y_eff), .io_y_c (_entries_barrier_3_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_75 entries_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_8_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_8_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_8_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_8_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_8_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_8_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_8_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_8_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_8_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_8_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_8_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_8_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_8_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_8_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_8_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_8_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_8_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_8_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_8_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_8_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_8_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_8_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_4_io_y_ppn), .io_y_u (_entries_barrier_4_io_y_u), .io_y_ae_ptw (_entries_barrier_4_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_4_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_4_io_y_ae_stage2), .io_y_pf (_entries_barrier_4_io_y_pf), .io_y_gf (_entries_barrier_4_io_y_gf), .io_y_sw (_entries_barrier_4_io_y_sw), .io_y_sx (_entries_barrier_4_io_y_sx), .io_y_sr (_entries_barrier_4_io_y_sr), .io_y_hw (_entries_barrier_4_io_y_hw), .io_y_hx (_entries_barrier_4_io_y_hx), .io_y_hr (_entries_barrier_4_io_y_hr), .io_y_pw (_entries_barrier_4_io_y_pw), .io_y_px (_entries_barrier_4_io_y_px), .io_y_pr (_entries_barrier_4_io_y_pr), .io_y_ppp (_entries_barrier_4_io_y_ppp), .io_y_pal (_entries_barrier_4_io_y_pal), .io_y_paa (_entries_barrier_4_io_y_paa), .io_y_eff (_entries_barrier_4_io_y_eff), .io_y_c (_entries_barrier_4_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_76 entries_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_10_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_10_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_10_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_10_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_10_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_10_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_10_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_10_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_10_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_10_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_10_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_10_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_10_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_10_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_10_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_10_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_10_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_10_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_10_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_10_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_10_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_10_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_5_io_y_ppn), .io_y_u (_entries_barrier_5_io_y_u), .io_y_ae_ptw (_entries_barrier_5_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_5_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_5_io_y_ae_stage2), .io_y_pf (_entries_barrier_5_io_y_pf), .io_y_gf (_entries_barrier_5_io_y_gf), .io_y_sw (_entries_barrier_5_io_y_sw), .io_y_sx (_entries_barrier_5_io_y_sx), .io_y_sr (_entries_barrier_5_io_y_sr), .io_y_hw (_entries_barrier_5_io_y_hw), .io_y_hx (_entries_barrier_5_io_y_hx), .io_y_hr (_entries_barrier_5_io_y_hr) ); // @[package.scala:267:25] assign io_req_ready = io_req_ready_0; // @[TLB.scala:318:7] assign io_resp_miss = io_resp_miss_0; // @[TLB.scala:318:7] assign io_resp_paddr = io_resp_paddr_0; // @[TLB.scala:318:7] assign io_ptw_req_valid = io_ptw_req_valid_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_need_gpa = io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_40( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [7:0] b_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] b_first_count = 8'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1_1 = \|(io_in_b_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size_1 = mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1_1 = mask_sub_sub_sub_sub_0_1_1 \| _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1_1 = mask_sub_sub_sub_sub_0_1_1 \| _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size_1 & mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1_1 = mask_sub_sub_sub_1_1_1 \| _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size_1 & mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1_1 = mask_sub_sub_sub_1_1_1 \| _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size_1 & mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1_1 = mask_sub_sub_2_1_1 \| _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size_1 & mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1_1 = mask_sub_sub_2_1_1 \| _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size_1 & mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1_1 = mask_sub_sub_3_1_1 \| _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size_1 & mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1_1 = mask_sub_sub_3_1_1 \| _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size_1 & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_0_1_1 \| _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size_1 & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_0_1_1 \| _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size_1 & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_1_1_1 \| _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size_1 & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_1_1_1 \| _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size_1 & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_2_1_1 \| _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size_1 & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_2_1_1 \| _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size_1 & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_3_1_1 \| _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size_1 & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_3_1_1 \| _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size_1 & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_4_1_1 \| _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size_1 & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_4_1_1 \| _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size_1 & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_5_1_1 \| _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size_1 & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_5_1_1 \| _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size_1 & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_6_1_1 \| _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size_1 & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_6_1_1 \| _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size_1 & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_7_1_1 \| _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size_1 & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_7_1_1 \| _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_1 = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_1 = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_1 = {mask_lo_lo_hi_1, mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_1 = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_1 = {mask_lo_hi_hi_1, mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_1 = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_1 = {mask_hi_lo_hi_1, mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_1 = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_1 = {mask_hi_hi_hi_1, mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73] wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2399 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2399; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2399; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2473 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2473; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2473; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2473; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2473; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [7:0] b_first_counter; // @[Edges.scala:229:27] wire [8:0] _b_first_counter1_T = {1'h0, b_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] b_first_counter1 = _b_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _b_first_counter_T = b_first ? 8'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2470 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2470; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2470; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T = {1'h0, c_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1 = _c_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_21 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_22 = 2'h1 << _GEN_21; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_22; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2325 = _T_2399 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2325 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2325 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2325 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2325 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_2325 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_23 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_23; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_23; // @[Monitor.scala:673:46, :783:46] wire _T_2371 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_24 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_25 = 2'h1 << _GEN_24; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_25; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2371 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2340 = _T_2473 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2340 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2340 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2340 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1_1 = _c_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] c_set; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [15:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [1:0] _GEN_26 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_27 = 2'h1 << _GEN_26; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_27; // @[OneHot.scala:58:35] wire [1:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_27; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2412 = _T_2470 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2412 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2412 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2412 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}] assign c_opcodes_set = _T_2412 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}] assign c_sizes_set = _T_2412 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2443 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2443 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_2425 = _T_2473 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2425 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2425 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2425 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [1:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [15:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_3 = _d_first_counter1_T_3[7:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] d_set; // @[Monitor.scala:833:25] wire _T_2479 = _T_2473 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _GEN_28 = {12'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _d_set_T = 16'h1 << _GEN_28; // @[OneHot.scala:58:35] assign d_set = _T_2479 ? _d_set_T : 16'h0; // @[OneHot.scala:58:35] wire [15:0] e_clr; // @[Monitor.scala:839:25] wire _T_2488 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [15:0] _GEN_29 = {12'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _e_clr_T = 16'h1 << _GEN_29; // @[OneHot.scala:58:35] assign e_clr = _T_2488 ? _e_clr_T : 16'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first \| last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first \| last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid \|\| ((!w_releaseack \|\| !w_rprobeacklast \|\| !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst \|\| !w_pprobeackfirst \|\| !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB \|\| !io.status.bits.blockB) assert (!io.status.bits.nestC \|\| !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe \|\| !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) \|\| (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) \|\| (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid \|\| io.schedule.bits.b.valid \|\| io.schedule.bits.c.valid \|\| io.schedule.bits.d.valid \|\| io.schedule.bits.e.valid \|\| io.schedule.bits.x.valid \|\| io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock \|\| request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty \|\| request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) \|\| !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) \| Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid \|\| meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U \|\| !(request.opcode === PutFullData \|\| request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r \|\| p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c \|\| m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read \|\| clean release can lead to this state eviction(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_D, true) // MMIO write \|\| dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read \|\| clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write \|\| clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read \|\| clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done \| probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done \| probe_bit probes_toN := probes_toN \| Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT \|\| io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst \|\| last_probe w_rprobeacklast := w_rprobeacklast \|\| (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst \|\| last_probe w_pprobeacklast := w_pprobeacklast \|\| (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last \|\| request.offset === 0.U) w_pprobeack := w_pprobeack \|\| set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant \|\| io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U \|\| io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f \|\| p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read \|\| clean release can lead to this state bypass(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_D, true) // MMIO write \|\| dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid \|\| (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid \|\| (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit \|\| (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT \|\| new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock \|\| new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module MSHR_3( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [7:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [7:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [7:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [7:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [7:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [7:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [7:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [7:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 8'h40; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 8'h40; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [7:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 8'h40; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired \|\| fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module Router_9( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_3_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_3_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_3_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_3_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_4_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32] wire _vc_allocator_io_req_4_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_5_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_5_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_5_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_5_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_5_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_5_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_4_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_5_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_5_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_5_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_5_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_5_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_5_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_5_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_5_0_valid; // @[Router.scala:131:24] wire _switch_io_out_5_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_5_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_5_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_5_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_5_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_4_0_valid; // @[Router.scala:131:24] wire _switch_io_out_4_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_4_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_4_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_4_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_4_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_3_0_valid; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_3_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [144:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_5_to_20_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_5_to_20_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_5_to_20_io_out_valid; // @[Router.scala:125:13] wire _egress_unit_4_to_19_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_4_to_19_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_4_to_19_io_out_valid; // @[Router.scala:125:13] wire _output_unit_3_to_13_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_3_to_13_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_10_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_2_to_10_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_2_to_10_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_2_to_10_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_10_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_10_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_8_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_1_to_8_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_1_to_8_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_8_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_2_occupied; // @[Router.scala:122:13] wire [3:0] _ingress_unit_4_from_29_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_29_io_router_req_bits_flow_egress_node_id; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [144:0] _ingress_unit_4_from_29_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_29_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_4_from_29_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [2:0] _ingress_unit_4_from_29_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_4_from_29_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_29_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_29_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_4_from_29_io_in_ready; // @[Router.scala:116:13] wire [1:0] _input_unit_3_from_13_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_13_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_3_from_13_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_13_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_3_from_13_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_13_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_3_from_13_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_3_from_13_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_13_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_3_from_13_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_13_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_3_from_13_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_13_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_13_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_10_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_10_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_10_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_10_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_10_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_10_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_10_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_2_from_10_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_10_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_10_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_10_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_10_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_10_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_10_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_8_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_1_from_8_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [144:0] _input_unit_0_from_5_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_5_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_8_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_10_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _input_unit_3_from_13_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_4_ready & _ingress_unit_4_from_29_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_5; // @[Router.scala:203:29] reg fired_5; // @[Router.scala:204:26] wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_6; // @[Router.scala:203:29] reg fired_6; // @[Router.scala:204:26] wire _GEN_7 = _GEN_0 & fired_6; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module InputBuffer_33( // @[InputUnit.scala:49:7] input clock, // @[InputUnit.scala:49:7] input reset, // @[InputUnit.scala:49:7] input io_enq_0_valid, // @[InputUnit.scala:51:14] input io_enq_0_bits_head, // @[InputUnit.scala:51:14] input io_enq_0_bits_tail, // @[InputUnit.scala:51:14] input [72:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14] input [4:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14] output io_deq_0_bits_head, // @[InputUnit.scala:51:14] output io_deq_0_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14] output io_deq_1_bits_head, // @[InputUnit.scala:51:14] output io_deq_1_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14] input io_deq_2_ready, // @[InputUnit.scala:51:14] output io_deq_2_valid, // @[InputUnit.scala:51:14] output io_deq_2_bits_head, // @[InputUnit.scala:51:14] output io_deq_2_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14] input io_deq_3_ready, // @[InputUnit.scala:51:14] output io_deq_3_valid, // @[InputUnit.scala:51:14] output io_deq_3_bits_head, // @[InputUnit.scala:51:14] output io_deq_3_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_3_bits_payload, // @[InputUnit.scala:51:14] output io_deq_4_bits_head, // @[InputUnit.scala:51:14] output io_deq_4_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_4_bits_payload, // @[InputUnit.scala:51:14] output io_deq_5_bits_head, // @[InputUnit.scala:51:14] output io_deq_5_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_5_bits_payload, // @[InputUnit.scala:51:14] output io_deq_6_bits_head, // @[InputUnit.scala:51:14] output io_deq_6_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_6_bits_payload, // @[InputUnit.scala:51:14] output io_deq_7_bits_head, // @[InputUnit.scala:51:14] output io_deq_7_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_7_bits_payload, // @[InputUnit.scala:51:14] output io_deq_8_bits_head, // @[InputUnit.scala:51:14] output io_deq_8_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_8_bits_payload, // @[InputUnit.scala:51:14] output io_deq_9_bits_head, // @[InputUnit.scala:51:14] output io_deq_9_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_9_bits_payload, // @[InputUnit.scala:51:14] output io_deq_10_bits_head, // @[InputUnit.scala:51:14] output io_deq_10_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_10_bits_payload, // @[InputUnit.scala:51:14] output io_deq_11_bits_head, // @[InputUnit.scala:51:14] output io_deq_11_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_11_bits_payload, // @[InputUnit.scala:51:14] output io_deq_12_bits_head, // @[InputUnit.scala:51:14] output io_deq_12_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_12_bits_payload, // @[InputUnit.scala:51:14] output io_deq_13_bits_head, // @[InputUnit.scala:51:14] output io_deq_13_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_13_bits_payload, // @[InputUnit.scala:51:14] output io_deq_14_bits_head, // @[InputUnit.scala:51:14] output io_deq_14_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_14_bits_payload, // @[InputUnit.scala:51:14] output io_deq_15_bits_head, // @[InputUnit.scala:51:14] output io_deq_15_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_15_bits_payload, // @[InputUnit.scala:51:14] output io_deq_16_bits_head, // @[InputUnit.scala:51:14] output io_deq_16_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_16_bits_payload, // @[InputUnit.scala:51:14] output io_deq_17_bits_head, // @[InputUnit.scala:51:14] output io_deq_17_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_17_bits_payload, // @[InputUnit.scala:51:14] input io_deq_18_ready, // @[InputUnit.scala:51:14] output io_deq_18_valid, // @[InputUnit.scala:51:14] output io_deq_18_bits_head, // @[InputUnit.scala:51:14] output io_deq_18_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_18_bits_payload, // @[InputUnit.scala:51:14] input io_deq_19_ready, // @[InputUnit.scala:51:14] output io_deq_19_valid, // @[InputUnit.scala:51:14] output io_deq_19_bits_head, // @[InputUnit.scala:51:14] output io_deq_19_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_19_bits_payload, // @[InputUnit.scala:51:14] input io_deq_20_ready, // @[InputUnit.scala:51:14] output io_deq_20_valid, // @[InputUnit.scala:51:14] output io_deq_20_bits_head, // @[InputUnit.scala:51:14] output io_deq_20_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_20_bits_payload, // @[InputUnit.scala:51:14] input io_deq_21_ready, // @[InputUnit.scala:51:14] output io_deq_21_valid, // @[InputUnit.scala:51:14] output io_deq_21_bits_head, // @[InputUnit.scala:51:14] output io_deq_21_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_21_bits_payload // @[InputUnit.scala:51:14] ); wire _qs_21_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_20_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_19_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_18_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_17_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_16_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_15_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_14_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_13_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_12_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_11_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_10_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_9_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_8_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_7_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_6_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_5_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_4_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49] wire [74:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R4_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R5_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R6_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R7_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R8_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R9_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R10_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R11_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R12_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R13_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R14_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R15_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R16_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R17_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R18_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R19_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R20_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R21_data; // @[InputUnit.scala:85:18] reg [4:0] heads_0; // @[InputUnit.scala:86:24] reg [4:0] heads_1; // @[InputUnit.scala:86:24] reg [4:0] heads_2; // @[InputUnit.scala:86:24] reg [4:0] heads_3; // @[InputUnit.scala:86:24] reg [4:0] heads_4; // @[InputUnit.scala:86:24] reg [4:0] heads_5; // @[InputUnit.scala:86:24] reg [4:0] heads_6; // @[InputUnit.scala:86:24] reg [4:0] heads_7; // @[InputUnit.scala:86:24] reg [4:0] heads_8; // @[InputUnit.scala:86:24] reg [4:0] heads_9; // @[InputUnit.scala:86:24] reg [4:0] heads_10; // @[InputUnit.scala:86:24] reg [4:0] heads_11; // @[InputUnit.scala:86:24] reg [4:0] heads_12; // @[InputUnit.scala:86:24] reg [4:0] heads_13; // @[InputUnit.scala:86:24] reg [4:0] heads_14; // @[InputUnit.scala:86:24] reg [4:0] heads_15; // @[InputUnit.scala:86:24] reg [4:0] heads_16; // @[InputUnit.scala:86:24] reg [4:0] heads_17; // @[InputUnit.scala:86:24] reg [4:0] heads_18; // @[InputUnit.scala:86:24] reg [4:0] heads_19; // @[InputUnit.scala:86:24] reg [4:0] heads_20; // @[InputUnit.scala:86:24] reg [4:0] heads_21; // @[InputUnit.scala:86:24] reg [4:0] tails_0; // @[InputUnit.scala:87:24] reg [4:0] tails_1; // @[InputUnit.scala:87:24] reg [4:0] tails_2; // @[InputUnit.scala:87:24] reg [4:0] tails_3; // @[InputUnit.scala:87:24] reg [4:0] tails_4; // @[InputUnit.scala:87:24] reg [4:0] tails_5; // @[InputUnit.scala:87:24] reg [4:0] tails_6; // @[InputUnit.scala:87:24] reg [4:0] tails_7; // @[InputUnit.scala:87:24] reg [4:0] tails_8; // @[InputUnit.scala:87:24] reg [4:0] tails_9; // @[InputUnit.scala:87:24] reg [4:0] tails_10; // @[InputUnit.scala:87:24] reg [4:0] tails_11; // @[InputUnit.scala:87:24] reg [4:0] tails_12; // @[InputUnit.scala:87:24] reg [4:0] tails_13; // @[InputUnit.scala:87:24] reg [4:0] tails_14; // @[InputUnit.scala:87:24] reg [4:0] tails_15; // @[InputUnit.scala:87:24] reg [4:0] tails_16; // @[InputUnit.scala:87:24] reg [4:0] tails_17; // @[InputUnit.scala:87:24] reg [4:0] tails_18; // @[InputUnit.scala:87:24] reg [4:0] tails_19; // @[InputUnit.scala:87:24] reg [4:0] tails_20; // @[InputUnit.scala:87:24] reg [4:0] tails_21; // @[InputUnit.scala:87:24] wire _tails_T_66 = io_enq_0_bits_virt_channel_id == 5'h0; // @[Mux.scala:32:36] wire _tails_T_67 = io_enq_0_bits_virt_channel_id == 5'h1; // @[Mux.scala:32:36] wire _tails_T_68 = io_enq_0_bits_virt_channel_id == 5'h2; // @[Mux.scala:32:36] wire _tails_T_69 = io_enq_0_bits_virt_channel_id == 5'h3; // @[Mux.scala:32:36] wire _tails_T_70 = io_enq_0_bits_virt_channel_id == 5'h4; // @[Mux.scala:32:36] wire _tails_T_71 = io_enq_0_bits_virt_channel_id == 5'h5; // @[Mux.scala:32:36] wire _tails_T_72 = io_enq_0_bits_virt_channel_id == 5'h6; // @[Mux.scala:32:36] wire _tails_T_73 = io_enq_0_bits_virt_channel_id == 5'h7; // @[Mux.scala:32:36] wire _tails_T_74 = io_enq_0_bits_virt_channel_id == 5'h8; // @[Mux.scala:32:36] wire _tails_T_75 = io_enq_0_bits_virt_channel_id == 5'h9; // @[Mux.scala:32:36] wire _tails_T_76 = io_enq_0_bits_virt_channel_id == 5'hA; // @[Mux.scala:32:36] wire _tails_T_77 = io_enq_0_bits_virt_channel_id == 5'hB; // @[Mux.scala:32:36] wire _tails_T_78 = io_enq_0_bits_virt_channel_id == 5'hC; // @[Mux.scala:32:36] wire _tails_T_79 = io_enq_0_bits_virt_channel_id == 5'hD; // @[Mux.scala:32:36] wire _tails_T_80 = io_enq_0_bits_virt_channel_id == 5'hE; // @[Mux.scala:32:36] wire _tails_T_81 = io_enq_0_bits_virt_channel_id == 5'hF; // @[Mux.scala:32:36] wire _tails_T_82 = io_enq_0_bits_virt_channel_id == 5'h10; // @[Mux.scala:32:36] wire _tails_T_83 = io_enq_0_bits_virt_channel_id == 5'h11; // @[Mux.scala:32:36] wire _tails_T_84 = io_enq_0_bits_virt_channel_id == 5'h12; // @[Mux.scala:32:36] wire _tails_T_85 = io_enq_0_bits_virt_channel_id == 5'h13; // @[Mux.scala:32:36] wire _tails_T_86 = io_enq_0_bits_virt_channel_id == 5'h14; // @[Mux.scala:32:36] wire _tails_T_87 = io_enq_0_bits_virt_channel_id == 5'h15; // @[Mux.scala:32:36] wire direct_to_q = (_tails_T_66 & _qs_0_io_enq_ready \| _tails_T_67 & _qs_1_io_enq_ready \| _tails_T_68 & _qs_2_io_enq_ready \| _tails_T_69 & _qs_3_io_enq_ready \| _tails_T_70 & _qs_4_io_enq_ready \| _tails_T_71 & _qs_5_io_enq_ready \| _tails_T_72 & _qs_6_io_enq_ready \| _tails_T_73 & _qs_7_io_enq_ready \| _tails_T_74 & _qs_8_io_enq_ready \| _tails_T_75 & _qs_9_io_enq_ready \| _tails_T_76 & _qs_10_io_enq_ready \| _tails_T_77 & _qs_11_io_enq_ready \| _tails_T_78 & _qs_12_io_enq_ready \| _tails_T_79 & _qs_13_io_enq_ready \| _tails_T_80 & _qs_14_io_enq_ready \| _tails_T_81 & _qs_15_io_enq_ready \| _tails_T_82 & _qs_16_io_enq_ready \| _tails_T_83 & _qs_17_io_enq_ready \| _tails_T_84 & _qs_18_io_enq_ready \| _tails_T_85 & _qs_19_io_enq_ready \| _tails_T_86 & _qs_20_io_enq_ready \| _tails_T_87 & _qs_21_io_enq_ready) & (_tails_T_66 & heads_0 == tails_0 \| _tails_T_67 & heads_1 == tails_1 \| _tails_T_68 & heads_2 == tails_2 \| _tails_T_69 & heads_3 == tails_3 \| _tails_T_70 & heads_4 == tails_4 \| _tails_T_71 & heads_5 == tails_5 \| _tails_T_72 & heads_6 == tails_6 \| _tails_T_73 & heads_7 == tails_7 \| _tails_T_74 & heads_8 == tails_8 \| _tails_T_75 & heads_9 == tails_9 \| _tails_T_76 & heads_10 == tails_10 \| _tails_T_77 & heads_11 == tails_11 \| _tails_T_78 & heads_12 == tails_12 \| _tails_T_79 & heads_13 == tails_13 \| _tails_T_80 & heads_14 == tails_14 \| _tails_T_81 & heads_15 == tails_15 \| _tails_T_82 & heads_16 == tails_16 \| _tails_T_83 & heads_17 == tails_17 \| _tails_T_84 & heads_18 == tails_18 \| _tails_T_85 & heads_19 == tails_19 \| _tails_T_86 & heads_20 == tails_20 \| _tails_T_87 & heads_21 == tails_21); // @[Mux.scala:30:73, :32:36] wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}] wire [31:0][4:0] _GEN = {{tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_21}, {tails_20}, {tails_19}, {tails_18}, {tails_17}, {tails_16}, {tails_15}, {tails_14}, {tails_13}, {tails_12}, {tails_11}, {tails_10}, {tails_9}, {tails_8}, {tails_7}, {tails_6}, {tails_5}, {tails_4}, {tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16] wire _GEN_0 = io_enq_0_bits_virt_channel_id == 5'h0; // @[InputUnit.scala:103:45] wire _GEN_1 = io_enq_0_bits_virt_channel_id == 5'h1; // @[InputUnit.scala:103:45] wire _GEN_2 = io_enq_0_bits_virt_channel_id == 5'h2; // @[InputUnit.scala:103:45] wire _GEN_3 = io_enq_0_bits_virt_channel_id == 5'h3; // @[InputUnit.scala:103:45] wire _GEN_4 = io_enq_0_bits_virt_channel_id == 5'h4; // @[InputUnit.scala:103:45] wire _GEN_5 = io_enq_0_bits_virt_channel_id == 5'h5; // @[InputUnit.scala:103:45] wire _GEN_6 = io_enq_0_bits_virt_channel_id == 5'h6; // @[InputUnit.scala:103:45] wire _GEN_7 = io_enq_0_bits_virt_channel_id == 5'h7; // @[InputUnit.scala:103:45] wire _GEN_8 = io_enq_0_bits_virt_channel_id == 5'h8; // @[InputUnit.scala:103:45] wire _GEN_9 = io_enq_0_bits_virt_channel_id == 5'h9; // @[InputUnit.scala:103:45] wire _GEN_10 = io_enq_0_bits_virt_channel_id == 5'hA; // @[InputUnit.scala:103:45] wire _GEN_11 = io_enq_0_bits_virt_channel_id == 5'hB; // @[InputUnit.scala:103:45] wire _GEN_12 = io_enq_0_bits_virt_channel_id == 5'hC; // @[InputUnit.scala:103:45] wire _GEN_13 = io_enq_0_bits_virt_channel_id == 5'hD; // @[InputUnit.scala:103:45] wire _GEN_14 = io_enq_0_bits_virt_channel_id == 5'hE; // @[InputUnit.scala:103:45] wire _GEN_15 = io_enq_0_bits_virt_channel_id == 5'hF; // @[InputUnit.scala:103:45] wire _GEN_16 = io_enq_0_bits_virt_channel_id == 5'h10; // @[InputUnit.scala:103:45] wire _GEN_17 = io_enq_0_bits_virt_channel_id == 5'h11; // @[InputUnit.scala:103:45] wire _GEN_18 = io_enq_0_bits_virt_channel_id == 5'h12; // @[InputUnit.scala:103:45] wire _GEN_19 = io_enq_0_bits_virt_channel_id == 5'h13; // @[InputUnit.scala:103:45] wire _GEN_20 = io_enq_0_bits_virt_channel_id == 5'h14; // @[InputUnit.scala:103:45] wire _GEN_21 = io_enq_0_bits_virt_channel_id == 5'h15; // @[InputUnit.scala:103:45] wire _GEN_22 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34] wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_4 = heads_4 != tails_4 & _qs_4_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_5 = heads_5 != tails_5 & _qs_5_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_6 = heads_6 != tails_6 & _qs_6_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_7 = heads_7 != tails_7 & _qs_7_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_8 = heads_8 != tails_8 & _qs_8_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_9 = heads_9 != tails_9 & _qs_9_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_10 = heads_10 != tails_10 & _qs_10_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_11 = heads_11 != tails_11 & _qs_11_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_12 = heads_12 != tails_12 & _qs_12_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_13 = heads_13 != tails_13 & _qs_13_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_14 = heads_14 != tails_14 & _qs_14_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_15 = heads_15 != tails_15 & _qs_15_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_16 = heads_16 != tails_16 & _qs_16_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_17 = heads_17 != tails_17 & _qs_17_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_18 = heads_18 != tails_18 & _qs_18_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_19 = heads_19 != tails_19 & _qs_19_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_20 = heads_20 != tails_20 & _qs_20_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_21 = heads_21 != tails_21 & _qs_21_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire [21:0] to_q_oh_enc = can_to_q_0 ? 22'h1 : can_to_q_1 ? 22'h2 : can_to_q_2 ? 22'h4 : can_to_q_3 ? 22'h8 : can_to_q_4 ? 22'h10 : can_to_q_5 ? 22'h20 : can_to_q_6 ? 22'h40 : can_to_q_7 ? 22'h80 : can_to_q_8 ? 22'h100 : can_to_q_9 ? 22'h200 : can_to_q_10 ? 22'h400 : can_to_q_11 ? 22'h800 : can_to_q_12 ? 22'h1000 : can_to_q_13 ? 22'h2000 : can_to_q_14 ? 22'h4000 : can_to_q_15 ? 22'h8000 : can_to_q_16 ? 22'h10000 : can_to_q_17 ? 22'h20000 : can_to_q_18 ? 22'h40000 : can_to_q_19 ? 22'h80000 : can_to_q_20 ? 22'h100000 : {can_to_q_21, 21'h0}; // @[Mux.scala:50:70] wire _GEN_23 = can_to_q_0 \| can_to_q_1 \| can_to_q_2 \| can_to_q_3 \| can_to_q_4 \| can_to_q_5 \| can_to_q_6 \| can_to_q_7 \| can_to_q_8 \| can_to_q_9 \| can_to_q_10 \| can_to_q_11 \| can_to_q_12 \| can_to_q_13 \| can_to_q_14 \| can_to_q_15 \| can_to_q_16 \| can_to_q_17 \| can_to_q_18 \| can_to_q_19 \| can_to_q_20 \| can_to_q_21; // @[package.scala:81:59] wire [4:0] head = (to_q_oh_enc[0] ? heads_0 : 5'h0) \| (to_q_oh_enc[1] ? heads_1 : 5'h0) \| (to_q_oh_enc[2] ? heads_2 : 5'h0) \| (to_q_oh_enc[3] ? heads_3 : 5'h0) \| (to_q_oh_enc[4] ? heads_4 : 5'h0) \| (to_q_oh_enc[5] ? heads_5 : 5'h0) \| (to_q_oh_enc[6] ? heads_6 : 5'h0) \| (to_q_oh_enc[7] ? heads_7 : 5'h0) \| (to_q_oh_enc[8] ? heads_8 : 5'h0) \| (to_q_oh_enc[9] ? heads_9 : 5'h0) \| (to_q_oh_enc[10] ? heads_10 : 5'h0) \| (to_q_oh_enc[11] ? heads_11 : 5'h0) \| (to_q_oh_enc[12] ? heads_12 : 5'h0) \| (to_q_oh_enc[13] ? heads_13 : 5'h0) \| (to_q_oh_enc[14] ? heads_14 : 5'h0) \| (to_q_oh_enc[15] ? heads_15 : 5'h0) \| (to_q_oh_enc[16] ? heads_16 : 5'h0) \| (to_q_oh_enc[17] ? heads_17 : 5'h0) \| (to_q_oh_enc[18] ? heads_18 : 5'h0) \| (to_q_oh_enc[19] ? heads_19 : 5'h0) \| (to_q_oh_enc[20] ? heads_20 : 5'h0) \| (to_q_oh_enc[21] ? heads_21 : 5'h0); // @[OneHot.scala:83:30] wire _GEN_24 = _GEN_23 & to_q_oh_enc[0]; // @[OneHot.scala:83:30] wire _GEN_25 = _GEN_23 & to_q_oh_enc[1]; // @[OneHot.scala:83:30] wire _GEN_26 = _GEN_23 & to_q_oh_enc[2]; // @[OneHot.scala:83:30] wire _GEN_27 = _GEN_23 & to_q_oh_enc[3]; // @[OneHot.scala:83:30] wire _GEN_28 = _GEN_23 & to_q_oh_enc[4]; // @[OneHot.scala:83:30] wire _GEN_29 = _GEN_23 & to_q_oh_enc[5]; // @[OneHot.scala:83:30] wire _GEN_30 = _GEN_23 & to_q_oh_enc[6]; // @[OneHot.scala:83:30] wire _GEN_31 = _GEN_23 & to_q_oh_enc[7]; // @[OneHot.scala:83:30] wire _GEN_32 = _GEN_23 & to_q_oh_enc[8]; // @[OneHot.scala:83:30] wire _GEN_33 = _GEN_23 & to_q_oh_enc[9]; // @[OneHot.scala:83:30] wire _GEN_34 = _GEN_23 & to_q_oh_enc[10]; // @[OneHot.scala:83:30] wire _GEN_35 = _GEN_23 & to_q_oh_enc[11]; // @[OneHot.scala:83:30] wire _GEN_36 = _GEN_23 & to_q_oh_enc[12]; // @[OneHot.scala:83:30] wire _GEN_37 = _GEN_23 & to_q_oh_enc[13]; // @[OneHot.scala:83:30] wire _GEN_38 = _GEN_23 & to_q_oh_enc[14]; // @[OneHot.scala:83:30] wire _GEN_39 = _GEN_23 & to_q_oh_enc[15]; // @[OneHot.scala:83:30] wire _GEN_40 = _GEN_23 & to_q_oh_enc[16]; // @[OneHot.scala:83:30] wire _GEN_41 = _GEN_23 & to_q_oh_enc[17]; // @[OneHot.scala:83:30] wire _GEN_42 = _GEN_23 & to_q_oh_enc[18]; // @[OneHot.scala:83:30] wire _GEN_43 = _GEN_23 & to_q_oh_enc[19]; // @[OneHot.scala:83:30] wire _GEN_44 = _GEN_23 & to_q_oh_enc[20]; // @[OneHot.scala:83:30] wire _GEN_45 = _GEN_23 & to_q_oh_enc[21]; // @[OneHot.scala:83:30] wire [4:0] _tails_T_133 = _GEN[io_enq_0_bits_virt_channel_id] == ({1'h0, {1'h0, {1'h0, {2{_tails_T_68}}} \| {3{_tails_T_69}}} \| (_tails_T_84 ? 4'hB : 4'h0) \| {4{_tails_T_85}}} \| (_tails_T_86 ? 5'h13 : 5'h0) \| (_tails_T_87 ? 5'h17 : 5'h0)) ? {_tails_T_86, {_tails_T_84, _tails_T_69, 2'h0} \| (_tails_T_85 ? 4'hC : 4'h0)} \| (_tails_T_87 ? 5'h14 : 5'h0) : _GEN[io_enq_0_bits_virt_channel_id] + 5'h1; // @[Mux.scala:30:73, :32:36] wire [14:0] _to_q_T_2 = {10'h0, to_q_oh_enc[21:17]} \| to_q_oh_enc[15:1]; // @[OneHot.scala:31:18, :32:28] wire [6:0] _to_q_T_4 = _to_q_T_2[14:8] \| _to_q_T_2[6:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] _to_q_T_6 = _to_q_T_4[6:4] \| _to_q_T_4[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire _to_q_T_8 = _to_q_T_6[2] \| _to_q_T_6[0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [4:0] to_q = {\|(to_q_oh_enc[21:16]), \|(_to_q_T_2[14:7]), \|(_to_q_T_4[6:3]), \|(_to_q_T_6[2:1]), _to_q_T_8}; // @[OneHot.scala:30:18, :32:{10,14,28}] wire [4:0] _heads_T_89 = head == ({1'h0, {1'h0, {1'h0, {2{to_q_oh_enc[2]}}} \| {3{to_q_oh_enc[3]}}} \| (to_q_oh_enc[18] ? 4'hB : 4'h0) \| {4{to_q_oh_enc[19]}}} \| (to_q_oh_enc[20] ? 5'h13 : 5'h0) \| (to_q_oh_enc[21] ? 5'h17 : 5'h0)) ? {to_q_oh_enc[20], {to_q_oh_enc[18], to_q_oh_enc[3], 2'h0} \| (to_q_oh_enc[19] ? 4'hC : 4'h0)} \| (to_q_oh_enc[21] ? 5'h14 : 5'h0) : head + 5'h1; // @[OneHot.scala:83:30] always @(posedge clock) begin // @[InputUnit.scala:49:7] if (reset) begin // @[InputUnit.scala:49:7] heads_0 <= 5'h0; // @[InputUnit.scala:86:24] heads_1 <= 5'h0; // @[InputUnit.scala:86:24] heads_2 <= 5'h0; // @[InputUnit.scala:86:24] heads_3 <= 5'h4; // @[InputUnit.scala:86:24] heads_4 <= 5'h0; // @[InputUnit.scala:86:24] heads_5 <= 5'h0; // @[InputUnit.scala:86:24] heads_6 <= 5'h0; // @[InputUnit.scala:86:24] heads_7 <= 5'h0; // @[InputUnit.scala:86:24] heads_8 <= 5'h0; // @[InputUnit.scala:86:24] heads_9 <= 5'h0; // @[InputUnit.scala:86:24] heads_10 <= 5'h0; // @[InputUnit.scala:86:24] heads_11 <= 5'h0; // @[InputUnit.scala:86:24] heads_12 <= 5'h0; // @[InputUnit.scala:86:24] heads_13 <= 5'h0; // @[InputUnit.scala:86:24] heads_14 <= 5'h0; // @[InputUnit.scala:86:24] heads_15 <= 5'h0; // @[InputUnit.scala:86:24] heads_16 <= 5'h0; // @[InputUnit.scala:86:24] heads_17 <= 5'h0; // @[InputUnit.scala:86:24] heads_18 <= 5'h8; // @[InputUnit.scala:86:24] heads_19 <= 5'hC; // @[InputUnit.scala:86:24] heads_20 <= 5'h10; // @[InputUnit.scala:86:24] heads_21 <= 5'h14; // @[InputUnit.scala:86:24] tails_0 <= 5'h0; // @[InputUnit.scala:87:24] tails_1 <= 5'h0; // @[InputUnit.scala:87:24] tails_2 <= 5'h0; // @[InputUnit.scala:87:24] tails_3 <= 5'h4; // @[InputUnit.scala:87:24] tails_4 <= 5'h0; // @[InputUnit.scala:87:24] tails_5 <= 5'h0; // @[InputUnit.scala:87:24] tails_6 <= 5'h0; // @[InputUnit.scala:87:24] tails_7 <= 5'h0; // @[InputUnit.scala:87:24] tails_8 <= 5'h0; // @[InputUnit.scala:87:24] tails_9 <= 5'h0; // @[InputUnit.scala:87:24] tails_10 <= 5'h0; // @[InputUnit.scala:87:24] tails_11 <= 5'h0; // @[InputUnit.scala:87:24] tails_12 <= 5'h0; // @[InputUnit.scala:87:24] tails_13 <= 5'h0; // @[InputUnit.scala:87:24] tails_14 <= 5'h0; // @[InputUnit.scala:87:24] tails_15 <= 5'h0; // @[InputUnit.scala:87:24] tails_16 <= 5'h0; // @[InputUnit.scala:87:24] tails_17 <= 5'h0; // @[InputUnit.scala:87:24] tails_18 <= 5'h8; // @[InputUnit.scala:87:24] tails_19 <= 5'hC; // @[InputUnit.scala:87:24] tails_20 <= 5'h10; // @[InputUnit.scala:87:24] tails_21 <= 5'h14; // @[InputUnit.scala:87:24] end else begin // @[InputUnit.scala:49:7] if (_GEN_23 & {to_q_oh_enc[21:16], \|(_to_q_T_2[14:7]), \|(_to_q_T_4[6:3]), \|(_to_q_T_6[2:1]), _to_q_T_8} == 10'h0) // @[OneHot.scala:30:18, :32:{10,14,28}] heads_0 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h1) // @[OneHot.scala:32:10] heads_1 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h2) // @[OneHot.scala:32:10] heads_2 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h3) // @[OneHot.scala:32:10] heads_3 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h4) // @[OneHot.scala:32:10] heads_4 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h5) // @[OneHot.scala:32:10] heads_5 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h6) // @[OneHot.scala:32:10] heads_6 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h7) // @[OneHot.scala:32:10] heads_7 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h8) // @[OneHot.scala:32:10] heads_8 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h9) // @[OneHot.scala:32:10] heads_9 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hA) // @[OneHot.scala:32:10] heads_10 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hB) // @[OneHot.scala:32:10] heads_11 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hC) // @[OneHot.scala:32:10] heads_12 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hD) // @[OneHot.scala:32:10] heads_13 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hE) // @[OneHot.scala:32:10] heads_14 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hF) // @[OneHot.scala:32:10] heads_15 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h10) // @[OneHot.scala:32:10] heads_16 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h11) // @[OneHot.scala:32:10] heads_17 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h12) // @[OneHot.scala:32:10] heads_18 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h13) // @[OneHot.scala:32:10] heads_19 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h14) // @[OneHot.scala:32:10] heads_20 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h15) // @[OneHot.scala:32:10] heads_21 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_0 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_1 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_2 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_3) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_3 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_4) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_4 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_5) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_5 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_6) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_6 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_7) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_7 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_8) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_8 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_9) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_9 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_10) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_10 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_11) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_11 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_12) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_12 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_13) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_13 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_14) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_14 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_15) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_15 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_16) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_16 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_17) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_17 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_18) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_18 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_19) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_19 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_20) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_20 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_21) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_21 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Multiplier.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe} import freechips.rocketchip.util._ import ALU._ class MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle { val fn = Bits(SZ_ALU_FN.W) val dw = Bits(SZ_DW.W) val in1 = Bits(dataBits.W) val in2 = Bits(dataBits.W) val tag = UInt(tagBits.W) } class MultiplierResp(dataBits: Int, tagBits: Int) extends Bundle { val data = Bits(dataBits.W) val full_data = Bits((2dataBits).W) val tag = UInt(tagBits.W) } class MultiplierIO(val dataBits: Int, val tagBits: Int) extends Bundle { val req = Flipped(Decoupled(new MultiplierReq(dataBits, tagBits))) val kill = Input(Bool()) val resp = Decoupled(new MultiplierResp(dataBits, tagBits)) } case class MulDivParams( mulUnroll: Int = 1, divUnroll: Int = 1, mulEarlyOut: Boolean = false, divEarlyOut: Boolean = false, divEarlyOutGranularity: Int = 1 ) class MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module { private def minDivLatency = (cfg.divUnroll > 0).option(if (cfg.divEarlyOut) 3 else 1 + w/cfg.divUnroll) private def minMulLatency = (cfg.mulUnroll > 0).option(if (cfg.mulEarlyOut) 2 else w/cfg.mulUnroll) def minLatency: Int = (minDivLatency ++ minMulLatency).min val io = IO(new MultiplierIO(width, log2Up(nXpr))) val w = io.req.bits.in1.getWidth val mulw = if (cfg.mulUnroll == 0) w else (w + cfg.mulUnroll - 1) / cfg.mulUnroll cfg.mulUnroll val fastMulW = if (cfg.mulUnroll == 0) false else w/2 > cfg.mulUnroll && w % (2cfg.mulUnroll) == 0 val s_ready :: s_neg_inputs :: s_mul :: s_div :: s_dummy :: s_neg_output :: s_done_mul :: s_done_div :: Nil = Enum(8) val state = RegInit(s_ready) val req = Reg(chiselTypeOf(io.req.bits)) val count = Reg(UInt(log2Ceil( ((cfg.divUnroll != 0).option(w/cfg.divUnroll + 1).toSeq ++ (cfg.mulUnroll != 0).option(mulw/cfg.mulUnroll)).reduce(_ max _)).W)) val neg_out = Reg(Bool()) val isHi = Reg(Bool()) val resHi = Reg(Bool()) val divisor = Reg(Bits((w+1).W)) // div only needs w bits val remainder = Reg(Bits((2mulw+2).W)) // div only needs 2w+1 bits val mulDecode = List( FN_MUL -> List(Y, N, X, X), FN_MULH -> List(Y, Y, Y, Y), FN_MULHU -> List(Y, Y, N, N), FN_MULHSU -> List(Y, Y, Y, N)) val divDecode = List( FN_DIV -> List(N, N, Y, Y), FN_REM -> List(N, Y, Y, Y), FN_DIVU -> List(N, N, N, N), FN_REMU -> List(N, Y, N, N)) val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil = DecodeLogic(io.req.bits.fn, List(X, X, X, X), (if (cfg.divUnroll != 0) divDecode else Nil) ++ (if (cfg.mulUnroll != 0) mulDecode else Nil)).map(_.asBool) require(w == 32 \|\| w == 64) def halfWidth(req: MultiplierReq) = (w > 32).B && req.dw === DW_32 def sext(x: Bits, halfW: Bool, signed: Bool) = { val sign = signed && Mux(halfW, x(w/2-1), x(w-1)) val hi = Mux(halfW, Fill(w/2, sign), x(w-1,w/2)) (Cat(hi, x(w/2-1,0)), sign) } val (lhs_in, lhs_sign) = sext(io.req.bits.in1, halfWidth(io.req.bits), lhsSigned) val (rhs_in, rhs_sign) = sext(io.req.bits.in2, halfWidth(io.req.bits), rhsSigned) val subtractor = remainder(2w,w) - divisor val result = Mux(resHi, remainder(2w, w+1), remainder(w-1, 0)) val negated_remainder = -result if (cfg.divUnroll != 0) when (state === s_neg_inputs) { when (remainder(w-1)) { remainder := negated_remainder } when (divisor(w-1)) { divisor := subtractor } state := s_div } if (cfg.divUnroll != 0) when (state === s_neg_output) { remainder := negated_remainder state := s_done_div resHi := false.B } if (cfg.mulUnroll != 0) when (state === s_mul) { val mulReg = Cat(remainder(2mulw+1,w+1),remainder(w-1,0)) val mplierSign = remainder(w) val mplier = mulReg(mulw-1,0) val accum = mulReg(2mulw,mulw).asSInt val mpcand = divisor.asSInt val prod = Cat(mplierSign, mplier(cfg.mulUnroll-1, 0)).asSInt mpcand + accum val nextMulReg = Cat(prod, mplier(mulw-1, cfg.mulUnroll)) val nextMplierSign = count === (mulw/cfg.mulUnroll-2).U && neg_out val eOutMask = ((BigInt(-1) << mulw).S >> (count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))(mulw-1,0) val eOut = (cfg.mulEarlyOut).B && count =/= (mulw/cfg.mulUnroll-1).U && count =/= 0.U && !isHi && (mplier & ~eOutMask) === 0.U val eOutRes = (mulReg >> (mulw.U - count * cfg.mulUnroll.U)(log2Up(mulw)-1,0)) val nextMulReg1 = Cat(nextMulReg(2mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0)) remainder := Cat(nextMulReg1 >> w, nextMplierSign, nextMulReg1(w-1,0)) count := count + 1.U when (eOut \|\| count === (mulw/cfg.mulUnroll-1).U) { state := s_done_mul resHi := isHi } } if (cfg.divUnroll != 0) when (state === s_div) { val unrolls = ((0 until cfg.divUnroll) scanLeft remainder) { case (rem, i) => // the special case for iteration 0 is to save HW, not for correctness val difference = if (i == 0) subtractor else rem(2w,w) - divisor(w-1,0) val less = difference(w) Cat(Mux(less, rem(2w-1,w), difference(w-1,0)), rem(w-1,0), !less) }.tail remainder := unrolls.last when (count === (w/cfg.divUnroll).U) { state := Mux(neg_out, s_neg_output, s_done_div) resHi := isHi if (w % cfg.divUnroll < cfg.divUnroll - 1) remainder := unrolls(w % cfg.divUnroll) } count := count + 1.U val divby0 = count === 0.U && !subtractor(w) if (cfg.divEarlyOut) { val align = 1 << log2Floor(cfg.divUnroll max cfg.divEarlyOutGranularity) val alignMask = ~((align-1).U(log2Ceil(w).W)) val divisorMSB = Log2(divisor(w-1,0), w) & alignMask val dividendMSB = Log2(remainder(w-1,0), w) \| ~alignMask val eOutPos = ~(dividendMSB - divisorMSB) val eOut = count === 0.U && !divby0 && eOutPos >= align.U when (eOut) { remainder := remainder(w-1,0) << eOutPos count := eOutPos >> log2Floor(cfg.divUnroll) } } when (divby0 && !isHi) { neg_out := false.B } } when (io.resp.fire \|\| io.kill) { state := s_ready } when (io.req.fire) { state := Mux(cmdMul, s_mul, Mux(lhs_sign \|\| rhs_sign, s_neg_inputs, s_div)) isHi := cmdHi resHi := false.B count := (if (fastMulW) Mux[UInt](cmdMul && halfWidth(io.req.bits), (w/cfg.mulUnroll/2).U, 0.U) else 0.U) neg_out := Mux(cmdHi, lhs_sign, lhs_sign =/= rhs_sign) divisor := Cat(rhs_sign, rhs_in) remainder := lhs_in req := io.req.bits } val outMul = (state & (s_done_mul ^ s_done_div)) === (s_done_mul & ~s_done_div) val loOut = Mux(fastMulW.B && halfWidth(req) && outMul, result(w-1,w/2), result(w/2-1,0)) val hiOut = Mux(halfWidth(req), Fill(w/2, loOut(w/2-1)), result(w-1,w/2)) io.resp.bits.tag := req.tag io.resp.bits.data := Cat(hiOut, loOut) io.resp.bits.full_data := Cat(remainder(2w, w+1), remainder(w-1, 0)) io.resp.valid := (state === s_done_mul \|\| state === s_done_div) io.req.ready := state === s_ready } class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module with ShouldBeRetimed { val io = IO(new Bundle { val req = Flipped(Valid(new MultiplierReq(width, log2Ceil(nXpr)))) val resp = Valid(new MultiplierResp(width, log2Ceil(nXpr))) }) val in = Pipe(io.req) val decode = List( FN_MUL -> List(N, X, X), FN_MULH -> List(Y, Y, Y), FN_MULHU -> List(Y, N, N), FN_MULHSU -> List(Y, Y, N)) val cmdHi :: lhsSigned :: rhsSigned :: Nil = DecodeLogic(in.bits.fn, List(X, X, X), decode).map(_.asBool) val cmdHalf = (width > 32).B && in.bits.dw === DW_32 val lhs = Cat(lhsSigned && in.bits.in1(width-1), in.bits.in1).asSInt val rhs = Cat(rhsSigned && in.bits.in2(width-1), in.bits.in2).asSInt val prod = lhs * rhs val muxed = Mux(cmdHi, prod(2*width-1, width), Mux(cmdHalf, prod(width/2-1, 0).sextTo(width), prod(width-1, 0))) val resp = Pipe(in, latency-1) io.resp.valid := resp.valid io.resp.bits.tag := resp.bits.tag io.resp.bits.data := Pipe(in.valid, muxed, latency-1).bits io.resp.bits.full_data := Pipe(in.valid, prod, latency-1).bits.asUInt }	module MulDiv_2( // @[Multiplier.scala:40:7] input clock, // @[Multiplier.scala:40:7] input reset, // @[Multiplier.scala:40:7] output io_req_ready, // @[Multiplier.scala:45:14] input io_req_valid, // @[Multiplier.scala:45:14] input [4:0] io_req_bits_fn, // @[Multiplier.scala:45:14] input io_req_bits_dw, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in1, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in2, // @[Multiplier.scala:45:14] input [4:0] io_req_bits_tag, // @[Multiplier.scala:45:14] input io_kill, // @[Multiplier.scala:45:14] input io_resp_ready, // @[Multiplier.scala:45:14] output io_resp_valid, // @[Multiplier.scala:45:14] output [63:0] io_resp_bits_data, // @[Multiplier.scala:45:14] output [4:0] io_resp_bits_tag // @[Multiplier.scala:45:14] ); wire io_req_valid_0 = io_req_valid; // @[Multiplier.scala:40:7] wire [4:0] io_req_bits_fn_0 = io_req_bits_fn; // @[Multiplier.scala:40:7] wire io_req_bits_dw_0 = io_req_bits_dw; // @[Multiplier.scala:40:7] wire [63:0] io_req_bits_in1_0 = io_req_bits_in1; // @[Multiplier.scala:40:7] wire [63:0] io_req_bits_in2_0 = io_req_bits_in2; // @[Multiplier.scala:40:7] wire [4:0] io_req_bits_tag_0 = io_req_bits_tag; // @[Multiplier.scala:40:7] wire io_kill_0 = io_kill; // @[Multiplier.scala:40:7] wire io_resp_ready_0 = io_resp_ready; // @[Multiplier.scala:40:7] wire [5:0] alignMask = 6'h3F; // @[Multiplier.scala:149:23] wire [5:0] _dividendMSB_T_111 = 6'h0; // @[Multiplier.scala:151:53] wire [2:0] _outMul_T = 3'h1; // @[Multiplier.scala:175:37] wire [2:0] _outMul_T_2 = 3'h0; // @[Multiplier.scala:175:70] wire [2:0] _outMul_T_3 = 3'h0; // @[Multiplier.scala:175:68] wire _io_req_ready_T; // @[Multiplier.scala:183:25] wire _io_resp_valid_T_2; // @[Multiplier.scala:182:42] wire [63:0] _io_resp_bits_data_T; // @[Multiplier.scala:180:27] wire [127:0] _io_resp_bits_full_data_T_2; // @[Multiplier.scala:181:32] wire io_req_ready_0; // @[Multiplier.scala:40:7] wire [63:0] io_resp_bits_data_0; // @[Multiplier.scala:40:7] wire [127:0] io_resp_bits_full_data; // @[Multiplier.scala:40:7] wire [4:0] io_resp_bits_tag_0; // @[Multiplier.scala:40:7] wire io_resp_valid_0; // @[Multiplier.scala:40:7] reg [2:0] state; // @[Multiplier.scala:51:22] reg [4:0] req_fn; // @[Multiplier.scala:53:16] reg req_dw; // @[Multiplier.scala:53:16] reg [63:0] req_in1; // @[Multiplier.scala:53:16] reg [63:0] req_in2; // @[Multiplier.scala:53:16] reg [4:0] req_tag; // @[Multiplier.scala:53:16] assign io_resp_bits_tag_0 = req_tag; // @[Multiplier.scala:40:7, :53:16] reg [6:0] count; // @[Multiplier.scala:54:18] reg neg_out; // @[Multiplier.scala:57:20] reg isHi; // @[Multiplier.scala:58:17] reg resHi; // @[Multiplier.scala:59:18] reg [64:0] divisor; // @[Multiplier.scala:60:20] wire [64:0] mpcand = divisor; // @[Multiplier.scala:60:20, :111:26] reg [129:0] remainder; // @[Multiplier.scala:61:22] wire [2:0] decoded_plaInput; // @[pla.scala:77:22] wire [2:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [3:0] decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [3:0] decoded; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_3_2 = decoded_andMatrixOutputs_andMatrixInput_0; // @[pla.scala:91:29, :98:70] wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_4_2 = decoded_andMatrixOutputs_andMatrixInput_0_1; // @[pla.scala:91:29, :98:70] wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire [1:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_1_2 = decoded_andMatrixOutputs_andMatrixInput_0_4; // @[pla.scala:90:45, :98:70] wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T = {decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_1 = \|_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _decoded_orMatrixOutputs_T_2 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_3 = \|_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] _decoded_orMatrixOutputs_T_4 = {decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_5 = \|_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo = {_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoded_plaInput = io_req_bits_fn_0[2:0]; // @[pla.scala:77:22] wire cmdMul = decoded[3]; // @[pla.scala:81:23] wire cmdHi = decoded[2]; // @[pla.scala:81:23] wire lhsSigned = decoded[1]; // @[pla.scala:81:23] wire rhsSigned = decoded[0]; // @[pla.scala:81:23] wire _count_T_5 = ~io_req_bits_dw_0; // @[Multiplier.scala:40:7, :78:60] wire _sign_T = io_req_bits_in1_0[31]; // @[Multiplier.scala:40:7, :81:38] wire _sign_T_1 = io_req_bits_in1_0[63]; // @[Multiplier.scala:40:7, :81:48] wire _sign_T_2 = io_req_bits_dw_0 ? _sign_T_1 : _sign_T; // @[Multiplier.scala:40:7, :81:{29,38,48}] wire lhs_sign = lhsSigned & _sign_T_2; // @[Multiplier.scala:75:107, :81:{23,29}] wire [31:0] _hi_T = {32{lhs_sign}}; // @[Multiplier.scala:81:23, :82:29] wire [31:0] _hi_T_1 = io_req_bits_in1_0[63:32]; // @[Multiplier.scala:40:7, :82:43] wire [31:0] hi = io_req_bits_dw_0 ? _hi_T_1 : _hi_T; // @[Multiplier.scala:40:7, :82:{17,29,43}] wire [63:0] lhs_in = {hi, io_req_bits_in1_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}] wire _sign_T_3 = io_req_bits_in2_0[31]; // @[Multiplier.scala:40:7, :81:38] wire _sign_T_4 = io_req_bits_in2_0[63]; // @[Multiplier.scala:40:7, :81:48] wire _sign_T_5 = io_req_bits_dw_0 ? _sign_T_4 : _sign_T_3; // @[Multiplier.scala:40:7, :81:{29,38,48}] wire rhs_sign = rhsSigned & _sign_T_5; // @[Multiplier.scala:75:107, :81:{23,29}] wire [31:0] _hi_T_2 = {32{rhs_sign}}; // @[Multiplier.scala:81:23, :82:29] wire [31:0] _hi_T_3 = io_req_bits_in2_0[63:32]; // @[Multiplier.scala:40:7, :82:43] wire [31:0] hi_1 = io_req_bits_dw_0 ? _hi_T_3 : _hi_T_2; // @[Multiplier.scala:40:7, :82:{17,29,43}] wire [63:0] rhs_in = {hi_1, io_req_bits_in2_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}] wire [64:0] _subtractor_T = remainder[128:64]; // @[Multiplier.scala:61:22, :88:29] wire [65:0] _subtractor_T_1 = {1'h0, _subtractor_T} - {1'h0, divisor}; // @[Multiplier.scala:60:20, :88:{29,37}] wire [64:0] subtractor = _subtractor_T_1[64:0]; // @[Multiplier.scala:88:37] wire [63:0] _result_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36] wire [63:0] _io_resp_bits_full_data_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36, :181:42] wire [63:0] _result_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57] wire [63:0] _mulReg_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :107:55] wire [63:0] _unrolls_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :134:58] wire [63:0] _dividendMSB_T = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :151:39] wire [63:0] _remainder_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :155:31] wire [63:0] _io_resp_bits_full_data_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :181:63] wire [63:0] result = resHi ? _result_T : _result_T_1; // @[Multiplier.scala:59:18, :89:{19,36,57}] wire [64:0] _negated_remainder_T = 65'h0 - {1'h0, result}; // @[Multiplier.scala:89:19, :90:27] wire [63:0] negated_remainder = _negated_remainder_T[63:0]; // @[Multiplier.scala:90:27] wire [64:0] _mulReg_T = remainder[129:65]; // @[Multiplier.scala:61:22, :107:31] wire [128:0] mulReg = {_mulReg_T, _mulReg_T_1}; // @[Multiplier.scala:107:{21,31,55}] wire mplierSign = remainder[64]; // @[Multiplier.scala:61:22, :108:31] wire [63:0] mplier = mulReg[63:0]; // @[Multiplier.scala:107:21, :109:24] wire [64:0] _accum_T = mulReg[128:64]; // @[Multiplier.scala:107:21, :110:23] wire [64:0] accum = _accum_T; // @[Multiplier.scala:110:{23,37}] wire [7:0] _prod_T = mplier[7:0]; // @[Multiplier.scala:109:24, :112:38] wire [8:0] _prod_T_1 = {mplierSign, _prod_T}; // @[Multiplier.scala:108:31, :112:{19,38}] wire [8:0] _prod_T_2 = _prod_T_1; // @[Multiplier.scala:112:{19,60}] wire [73:0] _prod_T_3 = {{65{_prod_T_2[8]}}, _prod_T_2} * {{9{mpcand[64]}}, mpcand}; // @[Multiplier.scala:111:26, :112:{60,67}] wire [74:0] _prod_T_4 = {_prod_T_3[73], _prod_T_3} + {{10{accum[64]}}, accum}; // @[Multiplier.scala:110:37, :112:{67,76}] wire [73:0] _prod_T_5 = _prod_T_4[73:0]; // @[Multiplier.scala:112:76] wire [73:0] prod = _prod_T_5; // @[Multiplier.scala:112:76] wire [73:0] nextMulReg_hi = prod; // @[Multiplier.scala:112:76, :113:25] wire [55:0] _nextMulReg_T = mplier[63:8]; // @[Multiplier.scala:109:24, :113:38] wire [129:0] nextMulReg = {nextMulReg_hi, _nextMulReg_T}; // @[Multiplier.scala:113:{25,38}] wire _nextMplierSign_T = count == 7'h6; // @[Multiplier.scala:54:18, :114:32] wire nextMplierSign = _nextMplierSign_T & neg_out; // @[Multiplier.scala:57:20, :114:{32,61}] wire [10:0] _GEN = {1'h0, count, 3'h0}; // @[Multiplier.scala:54:18, :116:54] wire [10:0] _eOutMask_T; // @[Multiplier.scala:116:54] assign _eOutMask_T = _GEN; // @[Multiplier.scala:116:54] wire [10:0] _eOutRes_T; // @[Multiplier.scala:119:46] assign _eOutRes_T = _GEN; // @[Multiplier.scala:116:54, :119:46] wire [5:0] _eOutMask_T_1 = _eOutMask_T[5:0]; // @[Multiplier.scala:116:{54,72}] wire [64:0] _eOutMask_T_2 = $signed(65'sh10000000000000000 >>> _eOutMask_T_1); // @[Multiplier.scala:116:{44,72}] wire [63:0] eOutMask = _eOutMask_T_2[63:0]; // @[Multiplier.scala:116:{44,91}] wire _eOut_T = count != 7'h7; // @[Multiplier.scala:54:18, :117:45] wire _eOut_T_1 = _eOut_T; // @[Multiplier.scala:117:{36,45}] wire _eOut_T_2 = \|count; // @[Multiplier.scala:54:18, :117:83] wire _eOut_T_3 = _eOut_T_1 & _eOut_T_2; // @[Multiplier.scala:117:{36,74,83}] wire _eOut_T_4 = ~isHi; // @[Multiplier.scala:58:17, :118:7] wire _eOut_T_5 = _eOut_T_3 & _eOut_T_4; // @[Multiplier.scala:117:{74,91}, :118:7] wire [63:0] _eOut_T_6 = ~eOutMask; // @[Multiplier.scala:116:91, :118:26] wire [63:0] _eOut_T_7 = mplier & _eOut_T_6; // @[Multiplier.scala:109:24, :118:{24,26}] wire _eOut_T_8 = _eOut_T_7 == 64'h0; // @[Multiplier.scala:118:{24,37}] wire eOut = _eOut_T_5 & _eOut_T_8; // @[Multiplier.scala:117:91, :118:{13,37}] wire [11:0] _eOutRes_T_1 = 12'h40 - {1'h0, _eOutRes_T}; // @[Multiplier.scala:119:{38,46}] wire [10:0] _eOutRes_T_2 = _eOutRes_T_1[10:0]; // @[Multiplier.scala:119:38] wire [5:0] _eOutRes_T_3 = _eOutRes_T_2[5:0]; // @[Multiplier.scala:119:{38,64}] wire [128:0] eOutRes = mulReg >> _eOutRes_T_3; // @[Multiplier.scala:107:21, :119:{27,64}] wire [64:0] _nextMulReg1_T = nextMulReg[128:64]; // @[Multiplier.scala:113:25, :120:37] wire [129:0] _nextMulReg1_T_1 = eOut ? {1'h0, eOutRes} : nextMulReg; // @[Multiplier.scala:113:25, :118:13, :119:27, :120:55] wire [63:0] _nextMulReg1_T_2 = _nextMulReg1_T_1[63:0]; // @[Multiplier.scala:120:{55,82}] wire [128:0] nextMulReg1 = {_nextMulReg1_T, _nextMulReg1_T_2}; // @[Multiplier.scala:120:{26,37,82}] wire [64:0] _remainder_T = nextMulReg1[128:64]; // @[Multiplier.scala:120:26, :121:34] wire [63:0] _remainder_T_1 = nextMulReg1[63:0]; // @[Multiplier.scala:120:26, :121:67] wire [65:0] remainder_hi = {_remainder_T, nextMplierSign}; // @[Multiplier.scala:114:61, :121:{21,34}] wire [129:0] _remainder_T_2 = {remainder_hi, _remainder_T_1}; // @[Multiplier.scala:121:{21,67}] wire [7:0] _GEN_0 = {1'h0, count} + 8'h1; // @[Multiplier.scala:54:18, :123:20] wire [7:0] _count_T; // @[Multiplier.scala:123:20] assign _count_T = _GEN_0; // @[Multiplier.scala:123:20] wire [7:0] _count_T_2; // @[Multiplier.scala:144:20] assign _count_T_2 = _GEN_0; // @[Multiplier.scala:123:20, :144:20] wire [6:0] _count_T_1 = _count_T[6:0]; // @[Multiplier.scala:123:20] wire unrolls_less = subtractor[64]; // @[Multiplier.scala:88:37, :133:28] wire _divby0_T_1 = subtractor[64]; // @[Multiplier.scala:88:37, :133:28, :146:46] wire [63:0] _unrolls_T = remainder[127:64]; // @[Multiplier.scala:61:22, :134:24] wire [63:0] _unrolls_T_1 = subtractor[63:0]; // @[Multiplier.scala:88:37, :134:45] wire [63:0] _unrolls_T_2 = unrolls_less ? _unrolls_T : _unrolls_T_1; // @[Multiplier.scala:133:28, :134:{14,24,45}] wire _unrolls_T_4 = ~unrolls_less; // @[Multiplier.scala:133:28, :134:67] wire [127:0] unrolls_hi = {_unrolls_T_2, _unrolls_T_3}; // @[Multiplier.scala:134:{10,14,58}] wire [128:0] unrolls_0 = {unrolls_hi, _unrolls_T_4}; // @[Multiplier.scala:134:{10,67}] wire [2:0] _state_T = {1'h1, ~neg_out, 1'h1}; // @[Multiplier.scala:57:20, :139:19] wire [6:0] _count_T_3 = _count_T_2[6:0]; // @[Multiplier.scala:144:20] wire _divby0_T = ~(\|count); // @[Multiplier.scala:54:18, :117:83, :146:24] wire _divby0_T_2 = ~_divby0_T_1; // @[Multiplier.scala:146:{35,46}] wire divby0 = _divby0_T & _divby0_T_2; // @[Multiplier.scala:146:{24,32,35}] wire [63:0] _divisorMSB_T = divisor[63:0]; // @[Multiplier.scala:60:20, :150:36] wire [31:0] divisorMSB_hi = _divisorMSB_T[63:32]; // @[CircuitMath.scala:33:17] wire [31:0] divisorMSB_lo = _divisorMSB_T[31:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi = \|divisorMSB_hi; // @[CircuitMath.scala:33:17, :35:22] wire [15:0] divisorMSB_hi_1 = divisorMSB_hi[31:16]; // @[CircuitMath.scala:33:17] wire [15:0] divisorMSB_lo_1 = divisorMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_1 = \|divisorMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] divisorMSB_hi_2 = divisorMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] divisorMSB_lo_2 = divisorMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_2 = \|divisorMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_3 = divisorMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_3 = divisorMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_3 = \|divisorMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_1 = divisorMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_2 = divisorMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_3 = divisorMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_4 = _divisorMSB_T_2 ? 2'h2 : {1'h0, _divisorMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_5 = _divisorMSB_T_1 ? 2'h3 : _divisorMSB_T_4; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_6 = divisorMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_7 = divisorMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_8 = divisorMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_9 = _divisorMSB_T_7 ? 2'h2 : {1'h0, _divisorMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_10 = _divisorMSB_T_6 ? 2'h3 : _divisorMSB_T_9; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_11 = divisorMSB_useHi_3 ? _divisorMSB_T_5 : _divisorMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_12 = {divisorMSB_useHi_3, _divisorMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_4 = divisorMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_4 = divisorMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_4 = \|divisorMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_13 = divisorMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_14 = divisorMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_15 = divisorMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_16 = _divisorMSB_T_14 ? 2'h2 : {1'h0, _divisorMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_17 = _divisorMSB_T_13 ? 2'h3 : _divisorMSB_T_16; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_18 = divisorMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_19 = divisorMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_20 = divisorMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_21 = _divisorMSB_T_19 ? 2'h2 : {1'h0, _divisorMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_22 = _divisorMSB_T_18 ? 2'h3 : _divisorMSB_T_21; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_23 = divisorMSB_useHi_4 ? _divisorMSB_T_17 : _divisorMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_24 = {divisorMSB_useHi_4, _divisorMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_25 = divisorMSB_useHi_2 ? _divisorMSB_T_12 : _divisorMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_26 = {divisorMSB_useHi_2, _divisorMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] divisorMSB_hi_5 = divisorMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] divisorMSB_lo_5 = divisorMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_5 = \|divisorMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_6 = divisorMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_6 = divisorMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_6 = \|divisorMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_27 = divisorMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_28 = divisorMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_29 = divisorMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_30 = _divisorMSB_T_28 ? 2'h2 : {1'h0, _divisorMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_31 = _divisorMSB_T_27 ? 2'h3 : _divisorMSB_T_30; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_32 = divisorMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_33 = divisorMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_34 = divisorMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_35 = _divisorMSB_T_33 ? 2'h2 : {1'h0, _divisorMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_36 = _divisorMSB_T_32 ? 2'h3 : _divisorMSB_T_35; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_37 = divisorMSB_useHi_6 ? _divisorMSB_T_31 : _divisorMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_38 = {divisorMSB_useHi_6, _divisorMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_7 = divisorMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_7 = divisorMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_7 = \|divisorMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_39 = divisorMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_40 = divisorMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_41 = divisorMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_42 = _divisorMSB_T_40 ? 2'h2 : {1'h0, _divisorMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_43 = _divisorMSB_T_39 ? 2'h3 : _divisorMSB_T_42; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_44 = divisorMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_45 = divisorMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_46 = divisorMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_47 = _divisorMSB_T_45 ? 2'h2 : {1'h0, _divisorMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_48 = _divisorMSB_T_44 ? 2'h3 : _divisorMSB_T_47; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_49 = divisorMSB_useHi_7 ? _divisorMSB_T_43 : _divisorMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_50 = {divisorMSB_useHi_7, _divisorMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_51 = divisorMSB_useHi_5 ? _divisorMSB_T_38 : _divisorMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_52 = {divisorMSB_useHi_5, _divisorMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_53 = divisorMSB_useHi_1 ? _divisorMSB_T_26 : _divisorMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_54 = {divisorMSB_useHi_1, _divisorMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [15:0] divisorMSB_hi_8 = divisorMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17] wire [15:0] divisorMSB_lo_8 = divisorMSB_lo[15:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_8 = \|divisorMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] divisorMSB_hi_9 = divisorMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] divisorMSB_lo_9 = divisorMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_9 = \|divisorMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_10 = divisorMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_10 = divisorMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_10 = \|divisorMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_55 = divisorMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_56 = divisorMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_57 = divisorMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_58 = _divisorMSB_T_56 ? 2'h2 : {1'h0, _divisorMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_59 = _divisorMSB_T_55 ? 2'h3 : _divisorMSB_T_58; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_60 = divisorMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_61 = divisorMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_62 = divisorMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_63 = _divisorMSB_T_61 ? 2'h2 : {1'h0, _divisorMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_64 = _divisorMSB_T_60 ? 2'h3 : _divisorMSB_T_63; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_65 = divisorMSB_useHi_10 ? _divisorMSB_T_59 : _divisorMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_66 = {divisorMSB_useHi_10, _divisorMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_11 = divisorMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_11 = divisorMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_11 = \|divisorMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_67 = divisorMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_68 = divisorMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_69 = divisorMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_70 = _divisorMSB_T_68 ? 2'h2 : {1'h0, _divisorMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_71 = _divisorMSB_T_67 ? 2'h3 : _divisorMSB_T_70; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_72 = divisorMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_73 = divisorMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_74 = divisorMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_75 = _divisorMSB_T_73 ? 2'h2 : {1'h0, _divisorMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_76 = _divisorMSB_T_72 ? 2'h3 : _divisorMSB_T_75; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_77 = divisorMSB_useHi_11 ? _divisorMSB_T_71 : _divisorMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_78 = {divisorMSB_useHi_11, _divisorMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_79 = divisorMSB_useHi_9 ? _divisorMSB_T_66 : _divisorMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_80 = {divisorMSB_useHi_9, _divisorMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] divisorMSB_hi_12 = divisorMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] divisorMSB_lo_12 = divisorMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_12 = \|divisorMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_13 = divisorMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_13 = divisorMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_13 = \|divisorMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_81 = divisorMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_82 = divisorMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_83 = divisorMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_84 = _divisorMSB_T_82 ? 2'h2 : {1'h0, _divisorMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_85 = _divisorMSB_T_81 ? 2'h3 : _divisorMSB_T_84; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_86 = divisorMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_87 = divisorMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_88 = divisorMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_89 = _divisorMSB_T_87 ? 2'h2 : {1'h0, _divisorMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_90 = _divisorMSB_T_86 ? 2'h3 : _divisorMSB_T_89; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_91 = divisorMSB_useHi_13 ? _divisorMSB_T_85 : _divisorMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_92 = {divisorMSB_useHi_13, _divisorMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_14 = divisorMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_14 = divisorMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_14 = \|divisorMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_93 = divisorMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_94 = divisorMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_95 = divisorMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_96 = _divisorMSB_T_94 ? 2'h2 : {1'h0, _divisorMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_97 = _divisorMSB_T_93 ? 2'h3 : _divisorMSB_T_96; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_98 = divisorMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_99 = divisorMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_100 = divisorMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_101 = _divisorMSB_T_99 ? 2'h2 : {1'h0, _divisorMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_102 = _divisorMSB_T_98 ? 2'h3 : _divisorMSB_T_101; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_103 = divisorMSB_useHi_14 ? _divisorMSB_T_97 : _divisorMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_104 = {divisorMSB_useHi_14, _divisorMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_105 = divisorMSB_useHi_12 ? _divisorMSB_T_92 : _divisorMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_106 = {divisorMSB_useHi_12, _divisorMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_107 = divisorMSB_useHi_8 ? _divisorMSB_T_80 : _divisorMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_108 = {divisorMSB_useHi_8, _divisorMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_109 = divisorMSB_useHi ? _divisorMSB_T_54 : _divisorMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] _divisorMSB_T_110 = {divisorMSB_useHi, _divisorMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] divisorMSB = _divisorMSB_T_110; // @[CircuitMath.scala:36:10] wire [31:0] dividendMSB_hi = _dividendMSB_T[63:32]; // @[CircuitMath.scala:33:17] wire [31:0] dividendMSB_lo = _dividendMSB_T[31:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi = \|dividendMSB_hi; // @[CircuitMath.scala:33:17, :35:22] wire [15:0] dividendMSB_hi_1 = dividendMSB_hi[31:16]; // @[CircuitMath.scala:33:17] wire [15:0] dividendMSB_lo_1 = dividendMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_1 = \|dividendMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] dividendMSB_hi_2 = dividendMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] dividendMSB_lo_2 = dividendMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_2 = \|dividendMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_3 = dividendMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_3 = dividendMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_3 = \|dividendMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_1 = dividendMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_2 = dividendMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_3 = dividendMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_4 = _dividendMSB_T_2 ? 2'h2 : {1'h0, _dividendMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_5 = _dividendMSB_T_1 ? 2'h3 : _dividendMSB_T_4; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_6 = dividendMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_7 = dividendMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_8 = dividendMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_9 = _dividendMSB_T_7 ? 2'h2 : {1'h0, _dividendMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_10 = _dividendMSB_T_6 ? 2'h3 : _dividendMSB_T_9; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_11 = dividendMSB_useHi_3 ? _dividendMSB_T_5 : _dividendMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_12 = {dividendMSB_useHi_3, _dividendMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_4 = dividendMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_4 = dividendMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_4 = \|dividendMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_13 = dividendMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_14 = dividendMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_15 = dividendMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_16 = _dividendMSB_T_14 ? 2'h2 : {1'h0, _dividendMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_17 = _dividendMSB_T_13 ? 2'h3 : _dividendMSB_T_16; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_18 = dividendMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_19 = dividendMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_20 = dividendMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_21 = _dividendMSB_T_19 ? 2'h2 : {1'h0, _dividendMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_22 = _dividendMSB_T_18 ? 2'h3 : _dividendMSB_T_21; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_23 = dividendMSB_useHi_4 ? _dividendMSB_T_17 : _dividendMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_24 = {dividendMSB_useHi_4, _dividendMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_25 = dividendMSB_useHi_2 ? _dividendMSB_T_12 : _dividendMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_26 = {dividendMSB_useHi_2, _dividendMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] dividendMSB_hi_5 = dividendMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] dividendMSB_lo_5 = dividendMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_5 = \|dividendMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_6 = dividendMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_6 = dividendMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_6 = \|dividendMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_27 = dividendMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_28 = dividendMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_29 = dividendMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_30 = _dividendMSB_T_28 ? 2'h2 : {1'h0, _dividendMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_31 = _dividendMSB_T_27 ? 2'h3 : _dividendMSB_T_30; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_32 = dividendMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_33 = dividendMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_34 = dividendMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_35 = _dividendMSB_T_33 ? 2'h2 : {1'h0, _dividendMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_36 = _dividendMSB_T_32 ? 2'h3 : _dividendMSB_T_35; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_37 = dividendMSB_useHi_6 ? _dividendMSB_T_31 : _dividendMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_38 = {dividendMSB_useHi_6, _dividendMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_7 = dividendMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_7 = dividendMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_7 = \|dividendMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_39 = dividendMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_40 = dividendMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_41 = dividendMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_42 = _dividendMSB_T_40 ? 2'h2 : {1'h0, _dividendMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_43 = _dividendMSB_T_39 ? 2'h3 : _dividendMSB_T_42; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_44 = dividendMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_45 = dividendMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_46 = dividendMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_47 = _dividendMSB_T_45 ? 2'h2 : {1'h0, _dividendMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_48 = _dividendMSB_T_44 ? 2'h3 : _dividendMSB_T_47; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_49 = dividendMSB_useHi_7 ? _dividendMSB_T_43 : _dividendMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_50 = {dividendMSB_useHi_7, _dividendMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_51 = dividendMSB_useHi_5 ? _dividendMSB_T_38 : _dividendMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_52 = {dividendMSB_useHi_5, _dividendMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_53 = dividendMSB_useHi_1 ? _dividendMSB_T_26 : _dividendMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_54 = {dividendMSB_useHi_1, _dividendMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [15:0] dividendMSB_hi_8 = dividendMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17] wire [15:0] dividendMSB_lo_8 = dividendMSB_lo[15:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_8 = \|dividendMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] dividendMSB_hi_9 = dividendMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] dividendMSB_lo_9 = dividendMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_9 = \|dividendMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_10 = dividendMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_10 = dividendMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_10 = \|dividendMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_55 = dividendMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_56 = dividendMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_57 = dividendMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_58 = _dividendMSB_T_56 ? 2'h2 : {1'h0, _dividendMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_59 = _dividendMSB_T_55 ? 2'h3 : _dividendMSB_T_58; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_60 = dividendMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_61 = dividendMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_62 = dividendMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_63 = _dividendMSB_T_61 ? 2'h2 : {1'h0, _dividendMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_64 = _dividendMSB_T_60 ? 2'h3 : _dividendMSB_T_63; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_65 = dividendMSB_useHi_10 ? _dividendMSB_T_59 : _dividendMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_66 = {dividendMSB_useHi_10, _dividendMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_11 = dividendMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_11 = dividendMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_11 = \|dividendMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_67 = dividendMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_68 = dividendMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_69 = dividendMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_70 = _dividendMSB_T_68 ? 2'h2 : {1'h0, _dividendMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_71 = _dividendMSB_T_67 ? 2'h3 : _dividendMSB_T_70; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_72 = dividendMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_73 = dividendMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_74 = dividendMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_75 = _dividendMSB_T_73 ? 2'h2 : {1'h0, _dividendMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_76 = _dividendMSB_T_72 ? 2'h3 : _dividendMSB_T_75; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_77 = dividendMSB_useHi_11 ? _dividendMSB_T_71 : _dividendMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_78 = {dividendMSB_useHi_11, _dividendMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_79 = dividendMSB_useHi_9 ? _dividendMSB_T_66 : _dividendMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_80 = {dividendMSB_useHi_9, _dividendMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] dividendMSB_hi_12 = dividendMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] dividendMSB_lo_12 = dividendMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_12 = \|dividendMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_13 = dividendMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_13 = dividendMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_13 = \|dividendMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_81 = dividendMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_82 = dividendMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_83 = dividendMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_84 = _dividendMSB_T_82 ? 2'h2 : {1'h0, _dividendMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_85 = _dividendMSB_T_81 ? 2'h3 : _dividendMSB_T_84; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_86 = dividendMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_87 = dividendMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_88 = dividendMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_89 = _dividendMSB_T_87 ? 2'h2 : {1'h0, _dividendMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_90 = _dividendMSB_T_86 ? 2'h3 : _dividendMSB_T_89; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_91 = dividendMSB_useHi_13 ? _dividendMSB_T_85 : _dividendMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_92 = {dividendMSB_useHi_13, _dividendMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_14 = dividendMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_14 = dividendMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_14 = \|dividendMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_93 = dividendMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_94 = dividendMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_95 = dividendMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_96 = _dividendMSB_T_94 ? 2'h2 : {1'h0, _dividendMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_97 = _dividendMSB_T_93 ? 2'h3 : _dividendMSB_T_96; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_98 = dividendMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_99 = dividendMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_100 = dividendMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_101 = _dividendMSB_T_99 ? 2'h2 : {1'h0, _dividendMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_102 = _dividendMSB_T_98 ? 2'h3 : _dividendMSB_T_101; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_103 = dividendMSB_useHi_14 ? _dividendMSB_T_97 : _dividendMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_104 = {dividendMSB_useHi_14, _dividendMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_105 = dividendMSB_useHi_12 ? _dividendMSB_T_92 : _dividendMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_106 = {dividendMSB_useHi_12, _dividendMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_107 = dividendMSB_useHi_8 ? _dividendMSB_T_80 : _dividendMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_108 = {dividendMSB_useHi_8, _dividendMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_109 = dividendMSB_useHi ? _dividendMSB_T_54 : _dividendMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] _dividendMSB_T_110 = {dividendMSB_useHi, _dividendMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] dividendMSB = _dividendMSB_T_110; // @[CircuitMath.scala:36:10] wire [6:0] _eOutPos_T = {1'h0, dividendMSB} - {1'h0, divisorMSB}; // @[Multiplier.scala:150:48, :151:51, :152:35] wire [5:0] _eOutPos_T_1 = _eOutPos_T[5:0]; // @[Multiplier.scala:152:35] wire [5:0] eOutPos = ~_eOutPos_T_1; // @[Multiplier.scala:152:{21,35}] wire [5:0] _count_T_4 = eOutPos; // @[Multiplier.scala:152:21, :156:26] wire _eOut_T_9 = ~(\|count); // @[Multiplier.scala:54:18, :117:83, :146:24, :153:24] wire _eOut_T_10 = ~divby0; // @[Multiplier.scala:146:32, :153:35] wire _eOut_T_11 = _eOut_T_9 & _eOut_T_10; // @[Multiplier.scala:153:{24,32,35}] wire _eOut_T_12 = \|eOutPos; // @[Multiplier.scala:152:21, :153:54] wire eOut_1 = _eOut_T_11 & _eOut_T_12; // @[Multiplier.scala:153:{32,43,54}] wire [126:0] _remainder_T_4 = {63'h0, _remainder_T_3} << eOutPos; // @[Multiplier.scala:152:21, :155:{31,39}] wire _state_T_1 = lhs_sign \| rhs_sign; // @[Multiplier.scala:81:23, :165:46] wire [2:0] _state_T_2 = {1'h0, ~_state_T_1, 1'h1}; // @[Multiplier.scala:165:{36,46}] wire [2:0] _state_T_3 = cmdMul ? 3'h2 : _state_T_2; // @[Multiplier.scala:75:107, :165:{17,36}] wire _count_T_6 = _count_T_5; // @[Multiplier.scala:78:{50,60}] wire _count_T_7 = cmdMul & _count_T_6; // @[Multiplier.scala:75:107, :78:50, :168:46] wire [2:0] _count_T_8 = {_count_T_7, 2'h0}; // @[Multiplier.scala:168:{38,46}] wire _neg_out_T = lhs_sign != rhs_sign; // @[Multiplier.scala:81:23, :169:46] wire _neg_out_T_1 = cmdHi ? lhs_sign : _neg_out_T; // @[Multiplier.scala:75:107, :81:23, :169:{19,46}] wire [64:0] _divisor_T = {rhs_sign, rhs_in}; // @[Multiplier.scala:81:23, :83:9, :170:19] wire [2:0] _outMul_T_1 = state & 3'h1; // @[Multiplier.scala:51:22, :175:23] wire outMul = _outMul_T_1 == 3'h0; // @[Multiplier.scala:175:{23,52}] wire _loOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60] wire _loOut_T_1 = _loOut_T; // @[Multiplier.scala:78:{50,60}] wire _loOut_T_2 = _loOut_T_1; // @[Multiplier.scala:78:50, :176:30] wire _loOut_T_3 = _loOut_T_2 & outMul; // @[Multiplier.scala:175:52, :176:{30,48}] wire [31:0] _loOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65] wire [31:0] _hiOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65, :177:66] wire [31:0] _loOut_T_5 = result[31:0]; // @[Multiplier.scala:89:19, :176:82] wire [31:0] loOut = _loOut_T_3 ? _loOut_T_4 : _loOut_T_5; // @[Multiplier.scala:176:{18,48,65,82}] wire _hiOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60] wire _hiOut_T_1 = _hiOut_T; // @[Multiplier.scala:78:{50,60}] wire _hiOut_T_2 = loOut[31]; // @[Multiplier.scala:176:18, :177:50] wire [31:0] _hiOut_T_3 = {32{_hiOut_T_2}}; // @[Multiplier.scala:177:{39,50}] wire [31:0] hiOut = _hiOut_T_1 ? _hiOut_T_3 : _hiOut_T_4; // @[Multiplier.scala:78:50, :177:{18,39,66}] assign _io_resp_bits_data_T = {hiOut, loOut}; // @[Multiplier.scala:176:18, :177:18, :180:27] assign io_resp_bits_data_0 = _io_resp_bits_data_T; // @[Multiplier.scala:40:7, :180:27] assign _io_resp_bits_full_data_T_2 = {_io_resp_bits_full_data_T, _io_resp_bits_full_data_T_1}; // @[Multiplier.scala:181:{32,42,63}] assign io_resp_bits_full_data = _io_resp_bits_full_data_T_2; // @[Multiplier.scala:40:7, :181:32] wire _io_resp_valid_T = state == 3'h6; // @[Multiplier.scala:51:22, :182:27] wire _io_resp_valid_T_1 = &state; // @[Multiplier.scala:51:22, :182:51] assign _io_resp_valid_T_2 = _io_resp_valid_T \| _io_resp_valid_T_1; // @[Multiplier.scala:182:{27,42,51}] assign io_resp_valid_0 = _io_resp_valid_T_2; // @[Multiplier.scala:40:7, :182:42] assign _io_req_ready_T = state == 3'h0; // @[Multiplier.scala:51:22, :183:25] assign io_req_ready_0 = _io_req_ready_T; // @[Multiplier.scala:40:7, :183:25] wire _T_10 = state == 3'h1; // @[Multiplier.scala:51:22, :92:39] wire _T_13 = state == 3'h5; // @[Multiplier.scala:51:22, :101:39] wire _T_14 = state == 3'h2; // @[Multiplier.scala:51:22, :106:39] wire _GEN_1 = _T_14 & (eOut \| count == 7'h7); // @[Multiplier.scala:54:18, :101:57, :106:{39,50}, :118:13, :124:{16,25,55}, :125:13] wire _T_17 = state == 3'h3; // @[Multiplier.scala:51:22, :129:39] wire _T_18 = count == 7'h40; // @[Multiplier.scala:54:18, :138:17] wire _T_23 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Multiplier.scala:40:7] if (reset) // @[Multiplier.scala:40:7] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_T_23) // @[Decoupled.scala:51:35] state <= _state_T_3; // @[Multiplier.scala:51:22, :165:17] else if (io_resp_ready_0 & io_resp_valid_0 \| io_kill_0) // @[Decoupled.scala:51:35] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_T_17 & _T_18) // @[Multiplier.scala:106:50, :129:{39,50}, :138:{17,42}, :139:13] state <= _state_T; // @[Multiplier.scala:51:22, :139:19] else if (_GEN_1) // @[Multiplier.scala:101:57, :106:50, :124:55, :125:13] state <= 3'h6; // @[Multiplier.scala:51:22] else if (_T_13) // @[Multiplier.scala:101:39] state <= 3'h7; // @[Multiplier.scala:51:22] else if (_T_10) // @[Multiplier.scala:92:39] state <= 3'h3; // @[Multiplier.scala:51:22] if (_T_23) begin // @[Decoupled.scala:51:35] req_fn <= io_req_bits_fn_0; // @[Multiplier.scala:40:7, :53:16] req_dw <= io_req_bits_dw_0; // @[Multiplier.scala:40:7, :53:16] req_in1 <= io_req_bits_in1_0; // @[Multiplier.scala:40:7, :53:16] req_in2 <= io_req_bits_in2_0; // @[Multiplier.scala:40:7, :53:16] req_tag <= io_req_bits_tag_0; // @[Multiplier.scala:40:7, :53:16] count <= {4'h0, _count_T_8}; // @[Multiplier.scala:54:18, :114:32, :168:{11,38}] isHi <= cmdHi; // @[Multiplier.scala:58:17, :75:107] divisor <= _divisor_T; // @[Multiplier.scala:60:20, :170:19] remainder <= {66'h0, lhs_in}; // @[Multiplier.scala:61:22, :83:9, :94:17, :171:15] end else begin // @[Decoupled.scala:51:35] if (_T_17) begin // @[Multiplier.scala:129:39] count <= eOut_1 ? {1'h0, _count_T_4} : _count_T_3; // @[Multiplier.scala:54:18, :144:{11,20}, :153:43, :154:19, :156:{15,26}] remainder <= eOut_1 ? {3'h0, _remainder_T_4} : {1'h0, unrolls_0}; // @[Multiplier.scala:61:22, :134:10, :137:15, :153:43, :154:19, :155:{19,39}] end else if (_T_14) begin // @[Multiplier.scala:106:39] count <= _count_T_1; // @[Multiplier.scala:54:18, :123:20] remainder <= _remainder_T_2; // @[Multiplier.scala:61:22, :121:21] end else if (_T_13 \| _T_10 & remainder[63]) // @[Multiplier.scala:61:22, :92:{39,57}, :93:{20,27}, :94:17, :101:{39,57}, :102:15] remainder <= {66'h0, negated_remainder}; // @[Multiplier.scala:61:22, :90:27, :94:17] if (_T_10 & divisor[63]) // @[Multiplier.scala:60:20, :92:{39,57}, :96:{18,25}, :97:15] divisor <= subtractor; // @[Multiplier.scala:60:20, :88:37] end neg_out <= _T_23 ? _neg_out_T_1 : ~(_T_17 & divby0 & ~isHi) & neg_out; // @[Decoupled.scala:51:35] resHi <= ~_T_23 & (_T_17 & _T_18 \| _GEN_1 ? isHi : ~_T_13 & resHi); // @[Decoupled.scala:51:35] always @(posedge) assign io_req_ready = io_req_ready_0; // @[Multiplier.scala:40:7] assign io_resp_valid = io_resp_valid_0; // @[Multiplier.scala:40:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[Multiplier.scala:40:7] assign io_resp_bits_tag = io_resp_bits_tag_0; // @[Multiplier.scala:40:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_21(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /* This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }	module IntSyncCrossingSource_n1x1_2( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset // @[Crossing.scala:41:9] ); wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9] wire auto_out_sync_0 = 1'h0; // @[Crossing.scala:41:9] wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17] AsyncResetRegVec_w1_i0_2 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset) ); // @[AsyncResetReg.scala:86:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_36(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_69( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module RecFNToRecFN_206( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_4( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1502 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1502; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1502; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1575 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1575; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1428 = _T_1502 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1428 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1428 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1428 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1428 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1428 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1474 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1474 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1443 = _T_1575 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1443 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1443 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1443 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1546 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1546 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1528 = _T_1575 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1528 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1528 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1528 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels / // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /* Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) \| t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }	module NoCMonitor_28( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /* This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }	module IntSyncCrossingSource_n1x5_5( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] output auto_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_1, // @[LazyModuleImp.scala:107:25] output auto_out_sync_2, // @[LazyModuleImp.scala:107:25] output auto_out_sync_3, // @[LazyModuleImp.scala:107:25] output auto_out_sync_4 // @[LazyModuleImp.scala:107:25] ); wire [4:0] _reg_io_q; // @[AsyncResetReg.scala:86:21] wire [1:0] lo = 2'h0; // @[Crossing.scala:45:36] wire [1:0] hi_hi = 2'h0; // @[Crossing.scala:45:36] wire [2:0] hi = 3'h0; // @[Crossing.scala:45:36] wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_1 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_2 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_3 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_4 = 1'h0; // @[Crossing.scala:41:9] wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_1 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_2 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_3 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_4 = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire nodeOut_sync_1; // @[MixedNode.scala:542:17] wire nodeOut_sync_2; // @[MixedNode.scala:542:17] wire nodeOut_sync_3; // @[MixedNode.scala:542:17] wire nodeOut_sync_4; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] wire auto_out_sync_1_0; // @[Crossing.scala:41:9] wire auto_out_sync_2_0; // @[Crossing.scala:41:9] wire auto_out_sync_3_0; // @[Crossing.scala:41:9] wire auto_out_sync_4_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] assign auto_out_sync_1_0 = nodeOut_sync_1; // @[Crossing.scala:41:9] assign auto_out_sync_2_0 = nodeOut_sync_2; // @[Crossing.scala:41:9] assign auto_out_sync_3_0 = nodeOut_sync_3; // @[Crossing.scala:41:9] assign auto_out_sync_4_0 = nodeOut_sync_4; // @[Crossing.scala:41:9] assign nodeOut_sync_0 = _reg_io_q[0]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_1 = _reg_io_q[1]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_2 = _reg_io_q[2]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_3 = _reg_io_q[3]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_4 = _reg_io_q[4]; // @[AsyncResetReg.scala:86:21] AsyncResetRegVec_w5_i0_5 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_q (_reg_io_q) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_1 = auto_out_sync_1_0; // @[Crossing.scala:41:9] assign auto_out_sync_2 = auto_out_sync_2_0; // @[Crossing.scala:41:9] assign auto_out_sync_3 = auto_out_sync_3_0; // @[Crossing.scala:41:9] assign auto_out_sync_4 = auto_out_sync_4_0; // @[Crossing.scala:41:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_94( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_104 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module TLFragmenter_UART( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30] wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [9:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [28:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71] wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49] wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18] wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} \| ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] dFirst_size = {\|dFirst_size_hi, \|(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] \| _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (\|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}] wire anonOut_d_ready = auto_anon_in_d_ready \| drop; // @[Fragmenter.scala:234:30, :235:35] wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}] wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}] reg aToggle_r; // @[Fragmenter.scala:309:54]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_49( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_428( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_172 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_6( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1339 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1339; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1339; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1412 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1412; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1412; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1412; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1265 = _T_1339 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1265 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1265 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1265 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1265 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1265 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1311 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1311 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1280 = _T_1412 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1280 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1280 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1280 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1383 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1383 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1365 = _T_1412 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1365 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1365 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1365 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_63( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_5 = 2'h1 << _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1184 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1153 = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1153 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1153 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1153 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1238 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1238 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1238 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1238 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_34( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [2:0] b_first_counter; // @[Edges.scala:229:27] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [2:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [34:0] inflight; // @[Monitor.scala:614:27] reg [139:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [139:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [63:0] _GEN_1 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [63:0] _GEN_4 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [34:0] inflight_1; // @[Monitor.scala:726:35] reg [139:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [63:0] _GEN_6 = {58'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [6:0] inflight_2; // @[Monitor.scala:828:27] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35] wire [6:0] d_set = _GEN_8 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLBuffer_a29d64s9k1z3u_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [8:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [8:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_8 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a29d64s9k1z3u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a29d64s9k1z3u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /* This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }	module IntSyncCrossingSource_n1x1_9( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset // @[Crossing.scala:41:9] ); wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9] wire auto_out_sync_0 = 1'h0; // @[Crossing.scala:41:9] wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17] AsyncResetRegVec_w1_i0_9 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset) ); // @[AsyncResetReg.scala:86:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_34( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_732; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_732; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_805; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_805; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_805; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_658 = _T_732 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_658 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_704 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_673 = _T_805 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_673 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_776 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_758 = _T_805 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_758 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Tilelink.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} trait TLFieldHelper { def getBodyFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.mask, b.data, b.corrupt) case b: TLBundleB => Seq(b.mask, b.data, b.corrupt) case b: TLBundleC => Seq( b.data, b.corrupt) case b: TLBundleD => Seq( b.data, b.corrupt) case b: TLBundleE => Seq() } def getConstFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address ) case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied) case b: TLBundleE => Seq( b.sink ) } def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits)) } class TLMasterToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2)) a.io.protocol <> io.tilelink.a io.tilelink.b <> b.io.protocol c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol e.io.protocol <> io.tilelink.e io.flits.a <> a.io.flit b.io.flit <> io.flits.b io.flits.c <> c.io.flit d.io.flit <> io.flits.d io.flits.e <> e.io.flit } class TLMasterACDToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) a.io.protocol <> io.tilelink.a c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol io.flits.a <> a.io.flit io.flits.c <> c.io.flit d.io.flit <> io.flits.d } class TLMasterBEToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0)) io.tilelink.b <> b.io.protocol e.io.protocol <> io.tilelink.e b.io.flit <> io.flits.b io.flits.e <> e.io.flit } class TLSlaveToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val b = Decoupled(new IngressFlit(flitWidth)) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) io.tilelink.a <> a.io.protocol b.io.protocol <> io.tilelink.b io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d io.tilelink.e <> e.io.protocol a.io.flit <> io.flits.a io.flits.b <> b.io.flit c.io.flit <> io.flits.c io.flits.d <> d.io.flit e.io.flit <> io.flits.e } class TLSlaveACDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart)) io.tilelink.a <> a.io.protocol io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d a.io.flit <> io.flits.a c.io.flit <> io.flits.c io.flits.d <> d.io.flit } class TLSlaveBEToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val b = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) b.io.protocol <> io.tilelink.b io.tilelink.e <> e.io.protocol io.flits.b <> b.io.flit e.io.flit <> io.flits.e } class TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle { val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) }) val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) }) } trait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper { def edgesIn: Seq[TLEdge] def edgesOut: Seq[TLEdge] def edgeInNodes: Seq[Int] def edgeOutNodes: Seq[Int] require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size) def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle)) def genBundle = new TLBundle(wideBundle) def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut) } object TLConnect { def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = { l.valid := r.valid r.ready := l.ready l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll } } // BEGIN: TileLinkProtocolParams case class TileLinkABCDEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int] ) extends TileLinkProtocolParams { // END: TileLinkProtocolParams val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten val nVirtualNetworks = 5 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A (if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B (if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D (if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { edgesIn.zipWithIndex.map { case (e,i) => val nif_master = Module(new TLMasterToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 3 + edgesIn.size * 2 + egressOffset, minPayloadWidth )) nif_master.io.tilelink := DontCare nif_master.io.tilelink.a.valid := false.B nif_master.io.tilelink.c.valid := false.B nif_master.io.tilelink.e.valid := false.B TLConnect(nif_master.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master.io.tilelink.b) TLConnect(nif_master.io.tilelink.c, protocol.in(i).c) TLConnect(nif_master.io.tilelink.e, protocol.in(i).e) } ingresses(i * 3 + 0).flit <> nif_master.io.flits.a ingresses(i * 3 + 1).flit <> nif_master.io.flits.c ingresses(i * 3 + 2).flit <> nif_master.io.flits.e nif_master.io.flits.b <> egresses(i * 2 + 0).flit nif_master.io.flits.d <> egresses(i * 2 + 1).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave = Module(new TLSlaveToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 2 + egressOffset, minPayloadWidth )) nif_slave.io.tilelink := DontCare nif_slave.io.tilelink.b.valid := false.B nif_slave.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a) TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b) TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c) TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e) } ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit } } } } } case class TileLinkACDProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val nVirtualNetworks = 3 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A (if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_acd = Module(new TLMasterACDToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 2 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_acd.io.tilelink := DontCare nif_master_acd.io.tilelink.a.valid := false.B nif_master_acd.io.tilelink.c.valid := false.B nif_master_acd.io.tilelink.e.valid := false.B TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c) } ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_acd = Module(new TLSlaveACDToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_acd.io.tilelink := DontCare nif_slave_acd.io.tilelink.b.valid := false.B nif_slave_acd.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a) TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c) } ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit } }} } } case class TileLinkBEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val nVirtualNetworks = 2 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B (if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_be = Module(new TLMasterBEToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 1 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_be.io.tilelink := DontCare nif_master_be.io.tilelink.a.valid := false.B nif_master_be.io.tilelink.c.valid := false.B nif_master_be.io.tilelink.e.valid := false.B if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b) TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e) } ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_be = Module(new TLSlaveBEToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_be.io.tilelink := DontCare nif_slave_be.io.tilelink.b.valid := false.B nif_slave_be.io.tilelink.d.valid := false.B if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e) TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b) } ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit } }} } } abstract class TLNoCLike(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") // TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers port.managers map { manager => manager.v1copy(fifoId = None) } } ) } ) } abstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) { val edgesIn: Seq[TLEdge] val edgesOut: Seq[TLEdge] val nodeMapping: DiplomaticNetworkNodeMapping val nocName: String lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name))) lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name))) lazy val edgeInNodes = nodeMapping.getNodesIn(inNames) lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames) def printNodeMappings() { println(s"Constellation: TLNoC $nocName inwards mapping:") for ((n, i) <- inNames zip edgeInNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } println(s"Constellation: TLNoC $nocName outwards mapping:") for ((n, i) <- outNames zip edgeOutNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } } } trait TLNoCParams // Instantiates a private TLNoC. Replaces the TLXbar // BEGIN: TLNoCParams case class SimpleTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, nocParams: NoCParams = NoCParams(), ) extends TLNoCParams class TLNoC(params: SimpleTLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { // END: TLNoCParams override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val noc = Module(new ProtocolNoC(ProtocolNoCParams( params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC), Seq(protocolParams), inlineNoC = inlineNoC ))) noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } } case class SplitACDxBETLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, acdNoCParams: NoCParams = NoCParams(), beNoCParams: NoCParams = NoCParams(), beDivision: Int = 2 ) extends TLNoCParams class TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val acdProtocolParams = TileLinkACDProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val beProtocolParams = TileLinkBEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.acdNoCParams.copy(hasCtrl = false, nocName=s"${name}_acd", inlineNoC = inlineNoC), Seq(acdProtocolParams), inlineNoC = inlineNoC ))) val be_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.beNoCParams.copy(hasCtrl = false, nocName=s"${name}_be", inlineNoC = inlineNoC), Seq(beProtocolParams), widthDivision = params.beDivision, inlineNoC = inlineNoC ))) acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } }} be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.b <> r.b l.e <> r.e } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.b <> r.b l.e <> r.e } }} } } case class GlobalTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping ) extends TLNoCParams // Maps this interconnect onto a global NoC class TLGlobalNoC(params: GlobalTLNoCParams, name: String = "test")(implicit p: Parameters) extends TLNoCLike { lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) printNodeMappings() val io_global = IO(Flipped(protocolParams.genIO())) io_global match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } }	module TLMasterToNoC_2( // @[Tilelink.scala:37:7] input clock, // @[Tilelink.scala:37:7] input reset, // @[Tilelink.scala:37:7] output io_tilelink_a_ready, // @[Tilelink.scala:44:14] input io_tilelink_a_valid, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:44:14] input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:44:14] input [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:44:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:44:14] input [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:44:14] input [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:44:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:44:14] input io_tilelink_b_ready, // @[Tilelink.scala:44:14] output io_tilelink_b_valid, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_b_bits_opcode, // @[Tilelink.scala:44:14] output [1:0] io_tilelink_b_bits_param, // @[Tilelink.scala:44:14] output [3:0] io_tilelink_b_bits_size, // @[Tilelink.scala:44:14] output [5:0] io_tilelink_b_bits_source, // @[Tilelink.scala:44:14] output [31:0] io_tilelink_b_bits_address, // @[Tilelink.scala:44:14] output [7:0] io_tilelink_b_bits_mask, // @[Tilelink.scala:44:14] output [63:0] io_tilelink_b_bits_data, // @[Tilelink.scala:44:14] output io_tilelink_b_bits_corrupt, // @[Tilelink.scala:44:14] output io_tilelink_c_ready, // @[Tilelink.scala:44:14] input io_tilelink_c_valid, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:44:14] input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:44:14] input [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:44:14] input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:44:14] input [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:44:14] input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:44:14] input io_tilelink_d_ready, // @[Tilelink.scala:44:14] output io_tilelink_d_valid, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:44:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:44:14] output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:44:14] output [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:44:14] output [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:44:14] output [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:44:14] output io_tilelink_e_ready, // @[Tilelink.scala:44:14] input io_tilelink_e_valid, // @[Tilelink.scala:44:14] input [4:0] io_tilelink_e_bits_sink, // @[Tilelink.scala:44:14] input io_flits_a_ready, // @[Tilelink.scala:44:14] output io_flits_a_valid, // @[Tilelink.scala:44:14] output io_flits_a_bits_head, // @[Tilelink.scala:44:14] output io_flits_a_bits_tail, // @[Tilelink.scala:44:14] output [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:44:14] output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:44:14] output io_flits_b_ready, // @[Tilelink.scala:44:14] input io_flits_b_valid, // @[Tilelink.scala:44:14] input io_flits_b_bits_head, // @[Tilelink.scala:44:14] input io_flits_b_bits_tail, // @[Tilelink.scala:44:14] input [72:0] io_flits_b_bits_payload, // @[Tilelink.scala:44:14] input io_flits_c_ready, // @[Tilelink.scala:44:14] output io_flits_c_valid, // @[Tilelink.scala:44:14] output io_flits_c_bits_head, // @[Tilelink.scala:44:14] output io_flits_c_bits_tail, // @[Tilelink.scala:44:14] output [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:44:14] output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:44:14] output io_flits_d_ready, // @[Tilelink.scala:44:14] input io_flits_d_valid, // @[Tilelink.scala:44:14] input io_flits_d_bits_head, // @[Tilelink.scala:44:14] input io_flits_d_bits_tail, // @[Tilelink.scala:44:14] input [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:44:14] input io_flits_e_ready, // @[Tilelink.scala:44:14] output io_flits_e_valid, // @[Tilelink.scala:44:14] output io_flits_e_bits_head, // @[Tilelink.scala:44:14] output [72:0] io_flits_e_bits_payload, // @[Tilelink.scala:44:14] output [4:0] io_flits_e_bits_egress_id // @[Tilelink.scala:44:14] ); wire [4:0] _e_io_flit_bits_payload; // @[Tilelink.scala:58:17] wire [64:0] _c_io_flit_bits_payload; // @[Tilelink.scala:56:17] TLAToNoC_2 a ( // @[Tilelink.scala:54:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:54:17] TLBFromNoC_1 b ( // @[Tilelink.scala:55:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_b_ready), .io_protocol_valid (io_tilelink_b_valid), .io_protocol_bits_opcode (io_tilelink_b_bits_opcode), .io_protocol_bits_param (io_tilelink_b_bits_param), .io_protocol_bits_size (io_tilelink_b_bits_size), .io_protocol_bits_source (io_tilelink_b_bits_source), .io_protocol_bits_address (io_tilelink_b_bits_address), .io_protocol_bits_mask (io_tilelink_b_bits_mask), .io_protocol_bits_data (io_tilelink_b_bits_data), .io_protocol_bits_corrupt (io_tilelink_b_bits_corrupt), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail), .io_flit_bits_payload (io_flits_b_bits_payload) ); // @[Tilelink.scala:55:17] TLCToNoC_2 c ( // @[Tilelink.scala:56:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (_c_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_c_bits_egress_id) ); // @[Tilelink.scala:56:17] TLDFromNoC_1 d ( // @[Tilelink.scala:57:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[64:0]) // @[Tilelink.scala:68:14] ); // @[Tilelink.scala:57:17] TLEToNoC e ( // @[Tilelink.scala:58:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_e_ready), .io_protocol_valid (io_tilelink_e_valid), .io_protocol_bits_sink (io_tilelink_e_bits_sink), .io_flit_ready (io_flits_e_ready), .io_flit_valid (io_flits_e_valid), .io_flit_bits_head (io_flits_e_bits_head), .io_flit_bits_payload (_e_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_e_bits_egress_id) ); // @[Tilelink.scala:58:17] assign io_flits_c_bits_payload = {8'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :56:17, :67:14] assign io_flits_e_bits_payload = {68'h0, _e_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :58:17, :69:14] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_60( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_237( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }	module dataArrayB1Way_0_0( // @[DescribedSRAM.scala:17:26] input [7:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [63:0] RW0_wdata, output [63:0] RW0_rdata ); dataArrayB0Way_0_ext dataArrayB0Way_0_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File CustomCSRs.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import org.chipsalliance.cde.config.Parameters case class CustomCSR(id: Int, mask: BigInt, init: Option[BigInt]) object CustomCSR { def constant(id: Int, value: BigInt): CustomCSR = CustomCSR(id, BigInt(0), Some(value)) } class CustomCSRIO(implicit p: Parameters) extends CoreBundle { val ren = Output(Bool()) // set by CSRFile, indicates an instruction is reading the CSR val wen = Output(Bool()) // set by CSRFile, indicates an instruction is writing the CSR val wdata = Output(UInt(xLen.W)) // wdata provided by instruction writing CSR val value = Output(UInt(xLen.W)) // current value of CSR in CSRFile val stall = Input(Bool()) // reads and writes to this CSR should stall (must be bounded) val set = Input(Bool()) // set/sdata enables external agents to set the value of this CSR val sdata = Input(UInt(xLen.W)) } class CustomCSRs(implicit p: Parameters) extends CoreBundle { // Not all cores have these CSRs, but those that do should follow the same // numbering conventions. So we list them here but default them to None. protected def bpmCSRId = 0x7c0 protected def bpmCSR: Option[CustomCSR] = None protected def chickenCSRId = 0x7c1 protected def chickenCSR: Option[CustomCSR] = None // If you override this, you'll want to concatenate super.decls def decls: Seq[CustomCSR] = bpmCSR.toSeq ++ chickenCSR val csrs = Vec(decls.size, new CustomCSRIO) def flushBTB = getOrElse(bpmCSR, _.wen, false.B) def bpmStatic = getOrElse(bpmCSR, _.value(0), false.B) def disableDCacheClockGate = getOrElse(chickenCSR, _.value(0), false.B) def disableICacheClockGate = getOrElse(chickenCSR, _.value(1), false.B) def disableCoreClockGate = getOrElse(chickenCSR, _.value(2), false.B) def disableSpeculativeICacheRefill = getOrElse(chickenCSR, _.value(3), false.B) def suppressCorruptOnGrantData = getOrElse(chickenCSR, _.value(9), false.B) protected def getByIdOrElse[T](id: Int, f: CustomCSRIO => T, alt: T): T = { val idx = decls.indexWhere(_.id == id) if (idx < 0) alt else f(csrs(idx)) } protected def getOrElse[T](csr: Option[CustomCSR], f: CustomCSRIO => T, alt: T): T = csr.map(c => getByIdOrElse(c.id, f, alt)).getOrElse(alt) } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File Events.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.log2Ceil import freechips.rocketchip.util._ import freechips.rocketchip.util.property class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bool)]) { def size = events.size val hits = WireDefault(VecInit(Seq.fill(size)(false.B))) def check(mask: UInt) = { hits := events.map(_._2()) gate(mask, hits.asUInt) } def dump(): Unit = { for (((name, _), i) <- events.zipWithIndex) when (check(1.U << i)) { printf(s"Event $name\n") } } def withCovers: Unit = { events.zipWithIndex.foreach { case ((name, func), i) => property.cover(gate((1.U << i), (func() << i)), name) } } } class EventSets(val eventSets: Seq[EventSet]) { def maskEventSelector(eventSel: UInt): UInt = { // allow full associativity between counters and event sets (for now?) val setMask = (BigInt(1) << eventSetIdBits) - 1 val maskMask = ((BigInt(1) << eventSets.map(_.size).max) - 1) << maxEventSetIdBits eventSel & (setMask \| maskMask).U } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } def evaluate(eventSel: UInt): Bool = { val (set, mask) = decode(eventSel) val sets = for (e <- eventSets) yield { require(e.hits.getWidth <= mask.getWidth, s"too many events ${e.hits.getWidth} wider than mask ${mask.getWidth}") e check mask } sets(set) } def cover() = eventSets.foreach { _.withCovers } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSetIdBits <= maxEventSetIdBits) } class SuperscalarEventSets(val eventSets: Seq[(Seq[EventSet], (UInt, UInt) => UInt)]) { def evaluate(eventSel: UInt): UInt = { val (set, mask) = decode(eventSel) val sets = for ((sets, reducer) <- eventSets) yield { sets.map { set => require(set.hits.getWidth <= mask.getWidth, s"too many events ${set.hits.getWidth} wider than mask ${mask.getWidth}") set.check(mask) }.reduce(reducer) } val zeroPadded = sets.padTo(1 << eventSetIdBits, 0.U) zeroPadded(set) } def toScalarEventSets: EventSets = new EventSets(eventSets.map(_._1.head)) def cover(): Unit = { eventSets.foreach(_._1.foreach(_.withCovers)) } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSets.forall(s => s._1.forall(_.size == s._1.head.size))) require(eventSetIdBits <= maxEventSetIdBits) } File RocketCore.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.withClock import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ArrayBuffer case class RocketCoreParams( xLen: Int = 64, pgLevels: Int = 3, // sv39 default bootFreqHz: BigInt = 0, useVM: Boolean = true, useUser: Boolean = false, useSupervisor: Boolean = false, useHypervisor: Boolean = false, useDebug: Boolean = true, useAtomics: Boolean = true, useAtomicsOnlyForIO: Boolean = false, useCompressed: Boolean = true, useRVE: Boolean = false, useConditionalZero: Boolean = false, useZba: Boolean = false, useZbb: Boolean = false, useZbs: Boolean = false, nLocalInterrupts: Int = 0, useNMI: Boolean = false, nBreakpoints: Int = 1, useBPWatch: Boolean = false, mcontextWidth: Int = 0, scontextWidth: Int = 0, nPMPs: Int = 8, nPerfCounters: Int = 0, haveBasicCounters: Boolean = true, haveCFlush: Boolean = false, misaWritable: Boolean = true, nL2TLBEntries: Int = 0, nL2TLBWays: Int = 1, nPTECacheEntries: Int = 8, mtvecInit: Option[BigInt] = Some(BigInt(0)), mtvecWritable: Boolean = true, fastLoadWord: Boolean = true, fastLoadByte: Boolean = false, branchPredictionModeCSR: Boolean = false, clockGate: Boolean = false, mvendorid: Int = 0, // 0 means non-commercial implementation mimpid: Int = 0x20181004, // release date in BCD mulDiv: Option[MulDivParams] = Some(MulDivParams()), fpu: Option[FPUParams] = Some(FPUParams()), debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB haveCease: Boolean = true, // non-standard CEASE instruction haveSimTimeout: Boolean = true, // add plusarg for simulation timeout vector: Option[RocketCoreVectorParams] = None ) extends CoreParams { val lgPauseCycles = 5 val haveFSDirty = false val pmpGranularity: Int = if (useHypervisor) 4096 else 4 val fetchWidth: Int = if (useCompressed) 2 else 1 // fetchWidth doubled, but coreInstBytes halved, for RVC: val decodeWidth: Int = fetchWidth / (if (useCompressed) 2 else 1) val retireWidth: Int = 1 val instBits: Int = if (useCompressed) 16 else 32 val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace override val useVector = vector.isDefined override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false) override def vLen = vector.map(_.vLen).getOrElse(0) override def eLen = vector.map(_.eLen).getOrElse(0) override def vfLen = vector.map(_.vfLen).getOrElse(0) override def vfh = vector.map(_.vfh).getOrElse(false) override def vExts = vector.map(_.vExts).getOrElse(Nil) override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0) override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32) override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs } trait HasRocketCoreParameters extends HasCoreParameters { lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams] val fastLoadWord = rocketParams.fastLoadWord val fastLoadByte = rocketParams.fastLoadByte val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this require(!fastLoadByte \|\| fastLoadWord) require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty") } class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters { override def bpmCSR = { rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0)))) } private def haveDCache = tileParams.dcache.get.scratch.isEmpty override def chickenCSR = { val mask = BigInt( tileParams.dcache.get.clockGate.toInt << 0 \| rocketParams.clockGate.toInt << 1 \| rocketParams.clockGate.toInt << 2 \| 1 << 3 \| // disableSpeculativeICacheRefill haveDCache.toInt << 9 \| // suppressCorruptOnGrantData tileParams.icache.get.prefetch.toInt << 17 ) Some(CustomCSR(chickenCSRId, mask, Some(mask))) } def disableICachePrefetch = getOrElse(chickenCSR, _.value(17), true.B) def marchid = CustomCSR.constant(CSRs.marchid, BigInt(1)) def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid)) // mimpid encodes a release version in the form of a BCD-encoded datestamp. def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid)) override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid } class CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) { val buserror = Option.when(hasBeu)(Bool()) } trait HasRocketCoreIO extends HasRocketCoreParameters { implicit val p: Parameters def nTotalRoCCCSRs: Int val io = IO(new CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val reset_vector = Input(UInt(resetVectorLen.W)) val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParams].beuAddr.isDefined)) val imem = new FrontendIO val dmem = new HellaCacheIO val ptw = Flipped(new DatapathPTWIO()) val fpu = Flipped(new FPUCoreIO()) val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs)) val trace = Output(new TraceBundle) val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth))) val cease = Output(Bool()) val wfi = Output(Bool()) val traceStall = Input(Bool()) val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None }) } class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) with HasRocketCoreParameters with HasRocketCoreIO { def nTotalRoCCCSRs = tile.roccCSRs.flatten.size import ALU._ val clock_en_reg = RegInit(true.B) val long_latency_stall = Reg(Bool()) val id_reg_pause = Reg(Bool()) val imem_might_request_reg = Reg(Bool()) val clock_en = WireDefault(true.B) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "rocket_clock_gate") class RocketImpl { // entering gated-clock domain // performance counters def pipelineIDToWB[T <: Data](x: T): T = RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid) val perfEvents = new EventSets(Seq( new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq( ("exception", () => false.B), ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp), ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp), ("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) \|\| id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))), ("system", () => id_ctrl.csr =/= CSR.N), ("arith", () => id_ctrl.wxd && !(id_ctrl.jal \|\| id_ctrl.jalr \|\| id_ctrl.mem \|\| id_ctrl.fp \|\| id_ctrl.mul \|\| id_ctrl.div \|\| id_ctrl.csr =/= CSR.N)), ("branch", () => id_ctrl.branch), ("jal", () => id_ctrl.jal), ("jalr", () => id_ctrl.jalr)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV), ("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV))) ++ (if (!usingFPU) Seq() else Seq( ("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen), ("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen), ("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23), ("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3), ("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3), ("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div \|\| io.fpu.dec.sqrt)), ("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst \|\| io.fpu.dec.fma \|\| io.fpu.dec.div \|\| io.fpu.dec.sqrt))))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("load-use interlock", () => id_ex_hazard && ex_ctrl.mem \|\| id_mem_hazard && mem_ctrl.mem \|\| id_wb_hazard && wb_ctrl.mem), ("long-latency interlock", () => id_sboard_hazard), ("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N \|\| id_mem_hazard && mem_ctrl.csr =/= CSR.N \|\| id_wb_hazard && wb_ctrl.csr =/= CSR.N), ("I$ blocked", () => icache_blocked), ("D$ blocked", () => id_ctrl.mem && dcache_blocked), ("branch misprediction", () => take_pc_mem && mem_direction_misprediction), ("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked), ("flush", () => wb_reg_flush_pipe), ("replay", () => replay_wb)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul \|\| ex_ctrl.div) \|\| id_mem_hazard && (mem_ctrl.mul \|\| mem_ctrl.div) \|\| id_wb_hazard && wb_ctrl.div))) ++ (if (!usingFPU) Seq() else Seq( ("fp interlock", () => id_ex_hazard && ex_ctrl.fp \|\| id_mem_hazard && mem_ctrl.fp \|\| id_wb_hazard && wb_ctrl.fp \|\| id_ctrl.fp && id_stall_fpu)))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("I$ miss", () => io.imem.perf.acquire), ("D$ miss", () => io.dmem.perf.acquire), ("D$ release", () => io.dmem.perf.release), ("ITLB miss", () => io.imem.perf.tlbMiss), ("DTLB miss", () => io.dmem.perf.tlbMiss), ("L2 TLB miss", () => io.ptw.perf.l2miss))))) val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen val decode_table = { (if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++: (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: (if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++: (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++: (if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++: (usingRoCC.option(new RoCCDecode)) ++: (if (xLen == 32) new I32Decode else new I64Decode) +: (usingVM.option(new SVMDecode)) ++: (usingSupervisor.option(new SDecode)) ++: (usingHypervisor.option(new HypervisorDecode)) ++: ((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++: (usingDebug.option(new DebugDecode)) ++: (usingNMI.option(new NMIDecode)) ++: (usingConditionalZero.option(new ConditionalZeroDecode)) ++: Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++: coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++: rocketParams.haveCease.option(new CeaseDecode) ++: usingVector.option(new VCFGDecode) ++: (if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++: (if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++: coreParams.useZbs.option(new ZbsDecode) ++: Seq(new IDecode) } flatMap(_.table) val ex_ctrl = Reg(new IntCtrlSigs) val mem_ctrl = Reg(new IntCtrlSigs) val wb_ctrl = Reg(new IntCtrlSigs) val ex_reg_xcpt_interrupt = Reg(Bool()) val ex_reg_valid = Reg(Bool()) val ex_reg_rvc = Reg(Bool()) val ex_reg_btb_resp = Reg(new BTBResp) val ex_reg_xcpt = Reg(Bool()) val ex_reg_flush_pipe = Reg(Bool()) val ex_reg_load_use = Reg(Bool()) val ex_reg_cause = Reg(UInt()) val ex_reg_replay = Reg(Bool()) val ex_reg_pc = Reg(UInt()) val ex_reg_mem_size = Reg(UInt()) val ex_reg_hls = Reg(Bool()) val ex_reg_inst = Reg(Bits()) val ex_reg_raw_inst = Reg(UInt()) val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val ex_reg_set_vconfig = Reg(Bool()) val mem_reg_xcpt_interrupt = Reg(Bool()) val mem_reg_valid = Reg(Bool()) val mem_reg_rvc = Reg(Bool()) val mem_reg_btb_resp = Reg(new BTBResp) val mem_reg_xcpt = Reg(Bool()) val mem_reg_replay = Reg(Bool()) val mem_reg_flush_pipe = Reg(Bool()) val mem_reg_cause = Reg(UInt()) val mem_reg_slow_bypass = Reg(Bool()) val mem_reg_load = Reg(Bool()) val mem_reg_store = Reg(Bool()) val mem_reg_set_vconfig = Reg(Bool()) val mem_reg_sfence = Reg(Bool()) val mem_reg_pc = Reg(UInt()) val mem_reg_inst = Reg(Bits()) val mem_reg_mem_size = Reg(UInt()) val mem_reg_hls_or_dv = Reg(Bool()) val mem_reg_raw_inst = Reg(UInt()) val mem_reg_wdata = Reg(Bits()) val mem_reg_rs2 = Reg(Bits()) val mem_br_taken = Reg(Bool()) val take_pc_mem = Wire(Bool()) val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val wb_reg_valid = Reg(Bool()) val wb_reg_xcpt = Reg(Bool()) val wb_reg_replay = Reg(Bool()) val wb_reg_flush_pipe = Reg(Bool()) val wb_reg_cause = Reg(UInt()) val wb_reg_set_vconfig = Reg(Bool()) val wb_reg_sfence = Reg(Bool()) val wb_reg_pc = Reg(UInt()) val wb_reg_mem_size = Reg(UInt()) val wb_reg_hls_or_dv = Reg(Bool()) val wb_reg_hfence_v = Reg(Bool()) val wb_reg_hfence_g = Reg(Bool()) val wb_reg_inst = Reg(Bits()) val wb_reg_raw_inst = Reg(UInt()) val wb_reg_wdata = Reg(Bits()) val wb_reg_rs2 = Reg(Bits()) val take_pc_wb = Wire(Bool()) val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val take_pc_mem_wb = take_pc_wb \|\| take_pc_mem val take_pc = take_pc_mem_wb // decode stage val ibuf = Module(new IBuf) val id_expanded_inst = ibuf.io.inst.map(_.bits.inst) val id_raw_inst = ibuf.io.inst.map(_.bits.raw) val id_inst = id_expanded_inst.map(_.bits) ibuf.io.imem <> io.imem.resp ibuf.io.kill := take_pc require(decodeWidth == 1 / TODO / && retireWidth == decodeWidth) require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point") require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor") val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table) val lgNXRegs = if (coreParams.useRVE) 4 else 5 val regAddrMask = (1 << lgNXRegs) - 1 def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0)) val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3) val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2) val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1) val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd) val id_load_use = Wire(Bool()) val id_reg_fence = RegInit(false.B) val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2) val id_raddr = IndexedSeq(id_raddr1, id_raddr2) val rf = new RegFile(regAddrMask, xLen) val id_rs = id_raddr.map(rf.read _) val ctrl_killd = Wire(Bool()) val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined)) val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W) val id_system_insn = id_ctrl.csr === CSR.I val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr)) val id_csr_flush = id_system_insn \|\| (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush) val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B id_ctrl.vec := false.B if (usingVector) { val v_decode = rocketParams.vector.get.decoder(p) v_decode.io.inst := id_inst(0) v_decode.io.vconfig := csr.io.vector.get.vconfig when (v_decode.io.legal) { id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill id_ctrl.fp := v_decode.io.fp id_ctrl.rocc := false.B id_ctrl.branch := false.B id_ctrl.jal := false.B id_ctrl.jalr := false.B id_ctrl.rxs2 := v_decode.io.read_rs2 id_ctrl.rxs1 := v_decode.io.read_rs1 id_ctrl.mem := false.B id_ctrl.rfs1 := v_decode.io.read_frs1 id_ctrl.rfs2 := false.B id_ctrl.rfs3 := false.B id_ctrl.wfd := v_decode.io.write_frd id_ctrl.mul := false.B id_ctrl.div := false.B id_ctrl.wxd := v_decode.io.write_rd id_ctrl.csr := CSR.N id_ctrl.fence_i := false.B id_ctrl.fence := false.B id_ctrl.amo := false.B id_ctrl.dp := false.B id_ctrl.vec := true.B } } val id_illegal_insn = !id_ctrl.legal \|\| (id_ctrl.mul \|\| id_ctrl.div) && !csr.io.status.isa('m'-'a') \|\| id_ctrl.amo && !csr.io.status.isa('a'-'a') \|\| id_ctrl.fp && (csr.io.decode(0).fp_illegal \|\| (io.fpu.illegal_rm && !id_ctrl.vec)) \|\| (id_ctrl.vec) && (csr.io.decode(0).vector_illegal \|\| csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) \|\| id_ctrl.dp && !csr.io.status.isa('d'-'a') \|\| ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') \|\| id_raddr2_illegal && id_ctrl.rxs2 \|\| id_raddr1_illegal && id_ctrl.rxs1 \|\| id_waddr_illegal && id_ctrl.wxd \|\| id_ctrl.rocc && csr.io.decode(0).rocc_illegal \|\| id_csr_en && (csr.io.decode(0).read_illegal \|\| !id_csr_ren && csr.io.decode(0).write_illegal) \|\| !ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal) val id_virtual_insn = id_ctrl.legal && ((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) \|\| (!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal)) // stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE) val id_amo_aq = id_inst(0)(26) val id_amo_rl = id_inst(0)(25) val id_fence_pred = id_inst(0)(27,24) val id_fence_succ = id_inst(0)(23,20) val id_fence_next = id_ctrl.fence \|\| id_ctrl.amo && id_amo_aq val id_mem_busy = !io.dmem.ordered \|\| io.dmem.req.valid when (!id_mem_busy) { id_reg_fence := false.B } val id_rocc_busy = usingRoCC.B && (io.rocc.busy \|\| ex_reg_valid && ex_ctrl.rocc \|\| mem_reg_valid && mem_ctrl.rocc \|\| wb_reg_valid && wb_ctrl.rocc) val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren val id_vec_busy = io.vector.map(v => v.backend_busy \|\| v.trap_check_busy).getOrElse(false.B) val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence \|\| id_csr_rocc_write) \|\| id_vec_busy && id_ctrl.fence \|\| id_mem_busy && (id_ctrl.amo && id_amo_rl \|\| id_ctrl.fence_i \|\| id_reg_fence && (id_ctrl.mem \|\| id_ctrl.rocc))) val bpu = Module(new BreakpointUnit(nBreakpoints)) bpu.io.status := csr.io.status bpu.io.bp := csr.io.bp bpu.io.pc := ibuf.io.pc bpu.io.ea := mem_reg_wdata bpu.io.mcontext := csr.io.mcontext bpu.io.scontext := csr.io.scontext val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0 val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1 val (id_xcpt, id_cause) = checkExceptions(List( (csr.io.interrupt, csr.io.interrupt_cause), (bpu.io.debug_if, CSR.debugTriggerCause.U), (bpu.io.xcpt_if, Causes.breakpoint.U), (id_xcpt0.pf.inst, Causes.fetch_page_fault.U), (id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt0.ae.inst, Causes.fetch_access.U), (id_xcpt1.pf.inst, Causes.fetch_page_fault.U), (id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt1.ae.inst, Causes.fetch_access.U), (id_virtual_insn, Causes.virtual_instruction.U), (id_illegal_insn, Causes.illegal_instruction.U))) val idCoverCauses = List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.fetch_access, "FETCH_ACCESS"), (Causes.illegal_instruction, "ILLEGAL_INSTRUCTION") ) ++ (if (usingVM) List( (Causes.fetch_page_fault, "FETCH_PAGE_FAULT") ) else Nil) coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses) val dcache_bypass_data = if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0) else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0) else wb_reg_wdata // detect bypass opportunities val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U val bypass_sources = IndexedSeq( (true.B, 0.U, 0.U), // treat reading x0 as a bypass (ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata), (mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata), (mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data)) val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr)) // execute stage val bypass_mux = bypass_sources.map(_._3) val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool())) val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W))) val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt())) val ex_rs = for (i <- 0 until id_raddr.size) yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i))) val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst) val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13) val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq( A1_RS1 -> ex_rs(0).asSInt, A1_PC -> ex_reg_pc.asSInt, A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S) )) val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq( A2_RS2 -> ex_rs(1).asSInt, A2_IMM -> ex_imm, A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S), ) ++ (if (coreParams.useZbs) Seq( A2_RS2OH -> ex_op2_oh, A2_IMMOH -> ex_op2_oh, ) else Nil)) val (ex_new_vl, ex_new_vconfig) = if (usingVector) { val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq( ex_reg_inst(31,30).andR -> ex_reg_inst(29,20), !ex_reg_inst(31) -> ex_reg_inst(30,20)))) val ex_avl = Mux(ex_ctrl.rxs1, Mux(ex_reg_inst(19,15) === 0.U, Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax), ex_rs(0) ), ex_reg_inst(19,15)) val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B) val ex_new_vconfig = Wire(new VConfig) ex_new_vconfig.vtype := ex_new_vtype ex_new_vconfig.vl := ex_new_vl (Some(ex_new_vl), Some(ex_new_vconfig)) } else { (None, None) } val alu = Module(new ALU) alu.io.dw := ex_ctrl.alu_dw alu.io.fn := ex_ctrl.alu_fn alu.io.in2 := ex_op2.asUInt alu.io.in1 := ex_op1.asUInt // multiplier and divider val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen)) div.io.req.valid := ex_reg_valid && ex_ctrl.div div.io.req.bits.dw := ex_ctrl.alu_dw div.io.req.bits.fn := ex_ctrl.alu_fn div.io.req.bits.in1 := ex_rs(0) div.io.req.bits.in2 := ex_rs(1) div.io.req.bits.tag := ex_waddr val mul = pipelinedMul.option { val m = Module(new PipelinedMultiplier(xLen, 2)) m.io.req.valid := ex_reg_valid && ex_ctrl.mul m.io.req.bits := div.io.req.bits m } ex_reg_valid := !ctrl_killd ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay ex_reg_xcpt := !ctrl_killd && id_xcpt ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt when (!ctrl_killd) { ex_ctrl := id_ctrl ex_reg_rvc := ibuf.io.inst(0).bits.rvc ex_ctrl.csr := id_csr when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B } when (id_fence_next) { id_reg_fence := true.B } when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr ex_ctrl.alu_fn := FN_ADD ex_ctrl.alu_dw := DW_XPR ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction ex_ctrl.sel_alu2 := A2_ZERO when (id_xcpt1.asUInt.orR) { // badaddr := PC+2 ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_SIZE ex_reg_rvc := true.B } when (bpu.io.xcpt_if \|\| id_xcpt0.asUInt.orR) { // badaddr := PC ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_ZERO } } ex_reg_flush_pipe := id_ctrl.fence_i \|\| id_csr_flush ex_reg_load_use := id_load_use ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX) ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12)) when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) { ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U) } when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) { ex_ctrl.mem_cmd := M_HFENCEV } if (tile.dcache.flushOnFenceI) { when (id_ctrl.fence_i) { ex_reg_mem_size := 0.U } } for (i <- 0 until id_raddr.size) { val do_bypass = id_bypass_src(i).reduce(_\|\|_) val bypass_src = PriorityEncoder(id_bypass_src(i)) ex_reg_rs_bypass(i) := do_bypass ex_reg_rs_lsb(i) := bypass_src when (id_ren(i) && !do_bypass) { ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size) } } when (id_illegal_insn \|\| id_virtual_insn) { val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0)) ex_reg_rs_bypass(0) := false.B ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size) } } when (!ctrl_killd \|\| csr.io.interrupt \|\| ibuf.io.inst(0).bits.replay) { ex_reg_cause := id_cause ex_reg_inst := id_inst(0) ex_reg_raw_inst := id_raw_inst(0) ex_reg_pc := ibuf.io.pc ex_reg_btb_resp := ibuf.io.btb_resp ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) } ex_reg_set_vconfig := id_set_vconfig && !id_xcpt } // replay inst in ex stage? val ex_pc_valid = ex_reg_valid \|\| ex_reg_replay \|\| ex_reg_xcpt_interrupt val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready \|\| ex_ctrl.div && !div.io.req.ready \|\| ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B) val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use val replay_ex = ex_reg_replay \|\| (ex_reg_valid && (replay_ex_structural \|\| replay_ex_load_use)) val ctrl_killx = take_pc_mem_wb \|\| replay_ex \|\| !ex_reg_valid // detect 2-cycle load-use delay for LB/LH/SC val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC \|\| ex_reg_mem_size < 2.U val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE \|\| ex_ctrl.mem_cmd === M_HFENCEV \|\| ex_ctrl.mem_cmd === M_HFENCEG) val (ex_xcpt, ex_cause) = checkExceptions(List( (ex_reg_xcpt_interrupt \|\| ex_reg_xcpt, ex_reg_cause))) val exCoverCauses = idCoverCauses coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses) // memory stage val mem_pc_valid = mem_reg_valid \|\| mem_reg_replay \|\| mem_reg_xcpt_interrupt val mem_br_target = mem_reg_pc.asSInt + Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst), Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), Mux(mem_reg_rvc, 2.S, 4.S))) val mem_npc = (Mux(mem_ctrl.jalr \|\| mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt val mem_wrong_npc = Mux(ex_pc_valid, mem_npc =/= ex_reg_pc, Mux(ibuf.io.inst(0).valid \|\| ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B)) val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt val mem_cfi = mem_ctrl.branch \|\| mem_ctrl.jalr \|\| mem_ctrl.jal val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) \|\| mem_ctrl.jalr \|\| mem_ctrl.jal val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken) val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction \|\| mem_reg_sfence) mem_reg_valid := !ctrl_killx mem_reg_replay := !take_pc_mem_wb && replay_ex mem_reg_xcpt := !ctrl_killx && ex_xcpt mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt // on pipeline flushes, cause mem_npc to hold the sequential npc, which // will drive the W-stage npc mux when (mem_reg_valid && mem_reg_flush_pipe) { mem_reg_sfence := false.B }.elsewhen (ex_pc_valid) { mem_ctrl := ex_ctrl mem_reg_rvc := ex_reg_rvc mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd) mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd) mem_reg_sfence := ex_sfence mem_reg_btb_resp := ex_reg_btb_resp mem_reg_flush_pipe := ex_reg_flush_pipe mem_reg_slow_bypass := ex_slow_bypass mem_reg_wphit := ex_reg_wphit mem_reg_set_vconfig := ex_reg_set_vconfig mem_reg_cause := ex_cause mem_reg_inst := ex_reg_inst mem_reg_raw_inst := ex_reg_raw_inst mem_reg_mem_size := ex_reg_mem_size mem_reg_hls_or_dv := io.dmem.req.bits.dv mem_reg_pc := ex_reg_pc // IDecode ensured they are 1H mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out) mem_br_taken := alu.io.cmp_out when (ex_ctrl.rxs2 && (ex_ctrl.mem \|\| ex_ctrl.rocc \|\| ex_sfence)) { val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size) mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data } if (usingVector) { when (ex_reg_set_vconfig) { mem_reg_rs2 := ex_new_vconfig.get.asUInt } } when (ex_ctrl.jalr && csr.io.status.debug) { // flush I$ on D-mode JALR to effect uncached fetch without D$ flush mem_ctrl.fence_i := true.B mem_reg_flush_pipe := true.B } } val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) \|\| (mem_reg_store && bpu.io.xcpt_st) val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) \|\| (mem_reg_store && bpu.io.debug_st) val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List( (mem_debug_breakpoint, CSR.debugTriggerCause.U), (mem_breakpoint, Causes.breakpoint.U))) val (mem_xcpt, mem_cause) = checkExceptions(List( (mem_reg_xcpt_interrupt \|\| mem_reg_xcpt, mem_reg_cause), (mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U), (mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause))) val memCoverCauses = (exCoverCauses ++ List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.misaligned_fetch, "MISALIGNED_FETCH") )).distinct coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses) val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B) val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B) val replay_mem = dcache_kill_mem \|\| mem_reg_replay \|\| fpu_kill_mem \|\| vec_kill_mem \|\| vec_kill_all val killm_common = dcache_kill_mem \|\| take_pc_wb \|\| mem_reg_xcpt \|\| !mem_reg_valid div.io.kill := killm_common && RegNext(div.io.req.fire) val ctrl_killm = killm_common \|\| mem_xcpt \|\| fpu_kill_mem \|\| vec_kill_mem // writeback stage wb_reg_valid := !ctrl_killm wb_reg_replay := replay_mem && !take_pc_wb wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B) wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe when (mem_pc_valid) { wb_ctrl := mem_ctrl wb_reg_sfence := mem_reg_sfence wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata) when (mem_ctrl.rocc \|\| mem_reg_sfence \|\| mem_reg_set_vconfig) { wb_reg_rs2 := mem_reg_rs2 } wb_reg_cause := mem_cause wb_reg_inst := mem_reg_inst wb_reg_raw_inst := mem_reg_raw_inst wb_reg_mem_size := mem_reg_mem_size wb_reg_hls_or_dv := mem_reg_hls_or_dv wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG wb_reg_pc := mem_reg_pc wb_reg_wphit := mem_reg_wphit \| bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) \|\| (bpw.wvalid(0) && mem_reg_store) } wb_reg_set_vconfig := mem_reg_set_vconfig } val (wb_xcpt, wb_cause) = checkExceptions(List( (wb_reg_xcpt, wb_reg_cause), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U) )) val wbCoverCauses = List( (Causes.misaligned_store, "MISALIGNED_STORE"), (Causes.misaligned_load, "MISALIGNED_LOAD"), (Causes.store_access, "STORE_ACCESS"), (Causes.load_access, "LOAD_ACCESS") ) ++ (if(usingVM) List( (Causes.store_page_fault, "STORE_PAGE_FAULT"), (Causes.load_page_fault, "LOAD_PAGE_FAULT") ) else Nil) ++ (if (usingHypervisor) List( (Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"), (Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT"), ) else Nil) coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses) val wb_pc_valid = wb_reg_valid \|\| wb_reg_replay \|\| wb_reg_xcpt val wb_wxd = wb_reg_valid && wb_ctrl.wxd val wb_set_sboard = wb_ctrl.div \|\| wb_dcache_miss \|\| wb_ctrl.rocc \|\| wb_ctrl.vec val replay_wb_common = io.dmem.s2_nack \|\| wb_reg_replay val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B) val replay_wb = replay_wb_common \|\| replay_wb_rocc \|\| replay_wb_csr \|\| replay_wb_vec take_pc_wb := replay_wb \|\| wb_xcpt \|\| csr.io.eret \|\| wb_reg_flush_pipe // writeback arbitration val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1) val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay class LLWB extends Bundle { val data = UInt(xLen.W) val tag = UInt(5.W) } val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec ll_arb.io.in.foreach(_.valid := false.B) ll_arb.io.in.foreach(_.bits := DontCare) val ll_wdata = WireInit(ll_arb.io.out.bits.data) val ll_waddr = WireInit(ll_arb.io.out.bits.tag) val ll_wen = WireInit(ll_arb.io.out.fire) ll_arb.io.out.ready := !wb_wxd div.io.resp.ready := ll_arb.io.in(0).ready ll_arb.io.in(0).valid := div.io.resp.valid ll_arb.io.in(0).bits.data := div.io.resp.bits.data ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag if (usingRoCC) { io.rocc.resp.ready := ll_arb.io.in(1).ready ll_arb.io.in(1).valid := io.rocc.resp.valid ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd } else { // tie off RoCC io.rocc.resp.ready := false.B io.rocc.mem.req.ready := false.B } io.vector.map { v => v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready) ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp ll_arb.io.in(2).bits.data := v.resp.bits.data ll_arb.io.in(2).bits.tag := v.resp.bits.rd } // Dont care mem since not all RoCC need accessing memory io.rocc.mem := DontCare when (dmem_resp_replay && dmem_resp_xpu) { ll_arb.io.out.ready := false.B ll_waddr := dmem_resp_waddr ll_wen := true.B } val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt val wb_wen = wb_valid && wb_ctrl.wxd val rf_wen = wb_wen \|\| ll_wen val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr) val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0), Mux(ll_wen, ll_wdata, Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata, Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata), wb_reg_wdata)))) when (rf_wen) { rf.write(rf_waddr, rf_wdata) } // hook up control/status regfile csr.io.ungated_clock := clock csr.io.decode(0).inst := id_inst(0) csr.io.exception := wb_xcpt csr.io.cause := wb_cause csr.io.retire := wb_valid csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst) csr.io.interrupts := io.interrupts csr.io.hartid := io.hartid io.fpu.fcsr_rm := csr.io.fcsr_rm val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W)) val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B) csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid \| vector_fcsr_flags_valid csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) \| (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid)) io.fpu.time := csr.io.time(31,0) io.fpu.hartid := io.hartid csr.io.rocc_interrupt := io.rocc.interrupt csr.io.pc := wb_reg_pc val tval_dmem_addr = !wb_reg_xcpt val tval_any_addr = tval_dmem_addr \|\| wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U) val tval_inst = wb_reg_cause === Causes.illegal_instruction.U val tval_valid = wb_xcpt && (tval_any_addr \|\| tval_inst) csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v \|\| tval_dmem_addr && wb_reg_hls_or_dv) csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U) val (htval, mhtinst_read_pseudo) = { val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U) assert(!htval_valid_imem \|\| io.imem.gpa.valid) val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U) val htval = (htval_dmem \| htval_imem) >> hypervisorExtraAddrBits // read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) \|\| (io.dmem.s2_gpa_is_pte && htval_valid_dmem) (htval, mhtinst_read_pseudo) } csr.io.vector.foreach { v => v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig) v.set_vs_dirty := wb_valid && wb_ctrl.vec v.set_vstart.valid := wb_valid && wb_reg_set_vconfig v.set_vstart.bits := 0.U } io.vector.foreach { v => when (v.wb.retire \|\| v.wb.xcpt \|\| wb_ctrl.vec) { csr.io.pc := v.wb.pc csr.io.retire := v.wb.retire csr.io.inst(0) := v.wb.inst when (v.wb.xcpt && !wb_reg_xcpt) { wb_xcpt := true.B wb_cause := v.wb.cause csr.io.tval := v.wb.tval } } v.wb.store_pending := io.dmem.store_pending v.wb.vxrm := csr.io.vector.get.vxrm v.wb.frm := csr.io.fcsr_rm csr.io.vector.get.set_vxsat := v.set_vxsat when (v.set_vconfig.valid) { csr.io.vector.get.set_vconfig.valid := true.B csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits } when (v.set_vstart.valid) { csr.io.vector.get.set_vstart.valid := true.B csr.io.vector.get.set_vstart.bits := v.set_vstart.bits } } csr.io.htval := htval csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo io.ptw.ptbr := csr.io.ptbr io.ptw.hgatp := csr.io.hgatp io.ptw.vsatp := csr.io.vsatp (io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs } io.ptw.status := csr.io.status io.ptw.hstatus := csr.io.hstatus io.ptw.gstatus := csr.io.gstatus io.ptw.pmp := csr.io.pmp csr.io.rw.addr := wb_reg_inst(31,20) csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr) csr.io.rw.wdata := wb_reg_wdata io.rocc.csrs <> csr.io.roccCSRs io.trace.time := csr.io.time io.trace.insns := csr.io.trace if (rocketParams.debugROB.isDefined) { val sz = rocketParams.debugROB.get.size if (sz < 1) { // use unsynthesizable ROB val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val should_wb = WireInit((wb_ctrl.wfd \|\| (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception) val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard) val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)) io.vector.foreach { v => when (v.wb.retire) { should_wb := v.wb.rob_should_wb has_wb := false.B wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7)) }} DebugROB.pushTrace(clock, reset, io.hartid, csr_trace_with_wdata, should_wb, has_wb, wb_addr) io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid) DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata) } else { // synthesizable ROB (no FPRs) require(!usingVector, "Synthesizable ROB does not support vector implementations") val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val debug_rob = Module(new HardDebugROB(sz, 32)) debug_rob.io.i_insn := csr_trace_with_wdata debug_rob.io.should_wb := (wb_ctrl.wfd \|\| (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U) debug_rob.io.wb_val := ll_wen debug_rob.io.wb_tag := rf_waddr debug_rob.io.wb_data := rf_wdata io.trace.insns(0) := debug_rob.io.o_insn } } else { io.trace.insns := csr.io.trace } for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) { iobpw.valid(0) := wphit iobpw.action := bp.control.action // tie off bpwatch valids iobpw.rvalid.foreach(_ := false.B) iobpw.wvalid.foreach(_ := false.B) iobpw.ivalid.foreach(_ := false.B) } val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1), (id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2), (id_ctrl.wxd && id_waddr =/= 0.U, id_waddr)) val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1), (io.fpu.dec.ren2, id_raddr2), (io.fpu.dec.ren3, id_raddr3), (io.fpu.dec.wen, id_waddr)) val sboard = new Scoreboard(32, true) sboard.clear(ll_wen, ll_waddr) def id_sboard_clear_bypass(r: UInt) = { // ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r else div.io.resp.fire && div.io.resp.bits.tag === r \|\| dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r } val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd)) sboard.set(wb_set_sboard && wb_wen, wb_waddr) // stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage. val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N \|\| ex_ctrl.jalr \|\| ex_ctrl.mem \|\| ex_ctrl.mul \|\| ex_ctrl.div \|\| ex_ctrl.fp \|\| ex_ctrl.rocc \|\| ex_ctrl.vec val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr) val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr) val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass \|\| fp_data_hazard_ex) // stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage. val mem_mem_cmd_bh = if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass else true.B val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N \|\| mem_ctrl.mem && mem_mem_cmd_bh \|\| mem_ctrl.mul \|\| mem_ctrl.div \|\| mem_ctrl.fp \|\| mem_ctrl.rocc \|\| mem_ctrl.vec val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr) val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr) val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass \|\| fp_data_hazard_mem) id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem val id_vconfig_hazard = id_ctrl.vec && ( (ex_reg_valid && ex_reg_set_vconfig) \|\| (mem_reg_valid && mem_reg_set_vconfig) \|\| (wb_reg_valid && wb_reg_set_vconfig)) // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback. val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr) val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr) val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard \|\| fp_data_hazard_wb) val id_stall_fpu = if (usingFPU) { val fp_sboard = new Scoreboard(32) fp_sboard.set(((wb_dcache_miss \|\| wb_ctrl.vec) && wb_ctrl.wfd \|\| io.fpu.sboard_set) && wb_valid, wb_waddr) val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B) fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) \|\| v_ll, io.fpu.ll_resp_tag) fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) checkHazards(fp_hazard_targets, fp_sboard.read _) } else false.B val dcache_blocked = { // speculate that a blocked D$ will unblock the cycle after a Grant val blocked = Reg(Bool()) blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked \|\| io.dmem.req.valid \|\| io.dmem.s2_nack) blocked && !io.dmem.perf.grant } val rocc_blocked = Reg(Bool()) rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid \|\| rocc_blocked) val ctrl_stalld = id_ex_hazard \|\| id_mem_hazard \|\| id_wb_hazard \|\| id_sboard_hazard \|\| id_vconfig_hazard \|\| csr.io.singleStep && (ex_reg_valid \|\| mem_reg_valid \|\| wb_reg_valid) \|\| id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy \|\| id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy \|\| id_ctrl.fp && id_stall_fpu \|\| id_ctrl.mem && dcache_blocked \|\| // reduce activity during D$ misses id_ctrl.rocc && rocc_blocked \|\| // reduce activity while RoCC is busy id_ctrl.div && (!(div.io.req.ready \|\| (div.io.resp.valid && !wb_wxd)) \|\| div.io.req.valid) \|\| // reduce odds of replay !clock_en \|\| id_do_fence \|\| csr.io.csr_stall \|\| id_reg_pause \|\| io.traceStall ctrl_killd := !ibuf.io.inst(0).valid \|\| ibuf.io.inst(0).bits.replay \|\| take_pc_mem_wb \|\| ctrl_stalld \|\| csr.io.interrupt io.imem.req.valid := take_pc io.imem.req.bits.speculative := !take_pc_wb io.imem.req.bits.pc := Mux(wb_xcpt \|\| csr.io.eret, csr.io.evec, // exception or [m\|s]ret Mux(replay_wb, wb_reg_pc, // replay mem_npc)) // flush or branch misprediction io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack io.imem.might_request := { imem_might_request_reg := ex_pc_valid \|\| mem_pc_valid \|\| io.ptw.customCSRs.disableICacheClockGate \|\| io.vector.map(_.trap_check_busy).getOrElse(false.B) imem_might_request_reg } io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common) io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence io.imem.sfence.bits.rs1 := wb_reg_mem_size(0) io.imem.sfence.bits.rs2 := wb_reg_mem_size(1) io.imem.sfence.bits.addr := wb_reg_wdata io.imem.sfence.bits.asid := wb_reg_rs2 io.imem.sfence.bits.hv := wb_reg_hfence_v io.imem.sfence.bits.hg := wb_reg_hfence_g io.ptw.sfence := io.imem.sfence ibuf.io.inst(0).ready := !ctrl_stalld io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi \|\| mem_cfi_taken) io.imem.btb_update.bits.isValid := mem_cfi io.imem.btb_update.bits.cfiType := Mux((mem_ctrl.jal \|\| mem_ctrl.jalr) && mem_waddr(0), CFIType.call, Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat("b00?01"), CFIType.ret, Mux(mem_ctrl.jal \|\| mem_ctrl.jalr, CFIType.jump, CFIType.branch))) io.imem.btb_update.bits.target := io.imem.req.bits.pc io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc) io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc \| (coreInstBytesfetchWidth-1).U) io.imem.btb_update.bits.prediction := mem_reg_btb_resp io.imem.btb_update.bits.taken := DontCare io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc io.imem.bht_update.bits.taken := mem_br_taken io.imem.bht_update.bits.mispredict := mem_wrong_npc io.imem.bht_update.bits.branch := mem_ctrl.branch io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht // Connect RAS in Frontend io.imem.ras_update := DontCare io.fpu.valid := !ctrl_killd && id_ctrl.fp io.fpu.killx := ctrl_killx io.fpu.killm := killm_common io.fpu.inst := id_inst(0) io.fpu.fromint_data := ex_rs(0) io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data) io.fpu.ll_resp_type := io.dmem.resp.bits.size io.fpu.ll_resp_tag := dmem_resp_waddr io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U) io.vector.map { v => when (!(dmem_resp_valid && dmem_resp_fpu)) { io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp io.fpu.ll_resp_data := v.resp.bits.data io.fpu.ll_resp_type := v.resp.bits.size io.fpu.ll_resp_tag := v.resp.bits.rd } } io.vector.foreach { v => v.ex.valid := ex_reg_valid && (ex_ctrl.vec \|\| rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx v.ex.inst := ex_reg_inst v.ex.vconfig := csr.io.vector.get.vconfig v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec \|\| wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart) v.ex.rs1 := ex_rs(0) v.ex.rs2 := ex_rs(1) v.ex.pc := ex_reg_pc v.mem.frs1 := io.fpu.store_data v.killm := killm_common v.status := csr.io.status } io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp) require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth) io.dmem.req.bits.tag := ex_dcache_tag io.dmem.req.bits.cmd := ex_ctrl.mem_cmd io.dmem.req.bits.size := ex_reg_mem_size io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14)) io.dmem.req.bits.phys := false.B io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out) io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr) io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv) io.dmem.req.bits.dv := ex_reg_hls \|\| csr.io.status.dv io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) \|\| (!ex_ctrl.fp && ex_waddr === 0.U) io.dmem.req.bits.no_alloc := DontCare io.dmem.req.bits.no_xcpt := DontCare io.dmem.req.bits.data := DontCare io.dmem.req.bits.mask := DontCare io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2)) io.dmem.s1_data.mask := DontCare io.dmem.s1_kill := killm_common \|\| mem_ldst_xcpt \|\| fpu_kill_mem \|\| vec_kill_mem io.dmem.s2_kill := false.B // don't let D$ go to sleep if we're probably going to use it soon io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common io.rocc.exception := wb_xcpt && csr.io.status.xs.orR io.rocc.cmd.bits.status := csr.io.status io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction()) io.rocc.cmd.bits.rs1 := wb_reg_wdata io.rocc.cmd.bits.rs2 := wb_reg_rs2 // gate the clock val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U \|\| csr.io.inhibit_cycle \|\| io.dmem.perf.release \|\| take_pc when (unpause) { id_reg_pause := false.B } io.cease := csr.io.status.cease && !clock_en_reg io.wfi := csr.io.status.wfi if (rocketParams.clockGate) { long_latency_stall := csr.io.csr_stall \|\| io.dmem.perf.blocked \|\| id_reg_pause && !unpause clock_en := clock_en_reg \|\| ex_pc_valid \|\| (!long_latency_stall && io.imem.resp.valid) clock_en_reg := ex_pc_valid \|\| mem_pc_valid \|\| wb_pc_valid \|\| // instruction in flight io.ptw.customCSRs.disableCoreClockGate \|\| // chicken bit !div.io.req.ready \|\| // mul/div in flight usingFPU.B && !io.fpu.fcsr_rdy \|\| // long-latency FPU in flight io.dmem.replay_next \|\| // long-latency load replaying (!long_latency_stall && (ibuf.io.inst(0).valid \|\| io.imem.resp.valid)) // instruction pending assert(!(ex_pc_valid \|\| mem_pc_valid \|\| wb_pc_valid) \|\| clock_en) } // evaluate performance counters val icache_blocked = !(io.imem.resp.valid \|\| RegNext(io.imem.resp.valid)) csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) } val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen)) coreMonitorBundle.clock := clock coreMonitorBundle.reset := reset coreMonitorBundle.hartid := io.hartid coreMonitorBundle.timer := csr.io.time(31,0) coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen) coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard coreMonitorBundle.wrenf := false.B coreMonitorBundle.wrdst := wb_waddr coreMonitorBundle.wrdata := rf_wdata coreMonitorBundle.rd0src := wb_reg_inst(19,15) coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0))) coreMonitorBundle.rd1src := wb_reg_inst(24,20) coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1))) coreMonitorBundle.inst := csr.io.trace(0).insn coreMonitorBundle.excpt := csr.io.trace(0).exception coreMonitorBundle.priv_mode := csr.io.trace(0).priv if (enableCommitLog) { val t = csr.io.trace(0) val rd = wb_waddr val wfd = wb_ctrl.wfd val wxd = wb_ctrl.wxd val has_data = wb_wen && !wb_set_sboard when (t.valid && !t.exception) { when (wfd) { printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+32.U) } .elsewhen (wxd && rd =/= 0.U && has_data) { printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata) } .elsewhen (wxd && rd =/= 0.U && !has_data) { printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd) } .otherwise { printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn) } } when (ll_wen && rf_waddr =/= 0.U) { printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata) } } else { when (csr.io.trace(0).valid) { printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid, coreMonitorBundle.pc, Mux(wb_ctrl.wxd \|\| wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U), Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U), coreMonitorBundle.wrenx, Mux(wb_ctrl.rxs1 \|\| wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U), Mux(wb_ctrl.rxs1 \|\| wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U), Mux(wb_ctrl.rxs2 \|\| wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U), Mux(wb_ctrl.rxs2 \|\| wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U), coreMonitorBundle.inst, coreMonitorBundle.inst) } } // CoreMonitorBundle for late latency writes val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen)) xrfWriteBundle.clock := clock xrfWriteBundle.reset := reset xrfWriteBundle.hartid := io.hartid xrfWriteBundle.timer := csr.io.time(31,0) xrfWriteBundle.valid := false.B xrfWriteBundle.pc := 0.U xrfWriteBundle.wrdst := rf_waddr xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr)) xrfWriteBundle.wrenf := false.B xrfWriteBundle.wrdata := rf_wdata xrfWriteBundle.rd0src := 0.U xrfWriteBundle.rd0val := 0.U xrfWriteBundle.rd1src := 0.U xrfWriteBundle.rd1val := 0.U xrfWriteBundle.inst := 0.U xrfWriteBundle.excpt := false.B xrfWriteBundle.priv_mode := csr.io.trace(0).priv if (rocketParams.haveSimTimeout) PlusArg.timeout( name = "max_core_cycles", docstring = "Kill the emulation after INT rdtime cycles. Off if 0." )(csr.io.time) } // leaving gated-clock domain val rocketImpl = withClock (gated_clock) { new RocketImpl } def checkExceptions(x: Seq[(Bool, UInt)]) = (WireInit(x.map(_._1).reduce(_\|\|_)), WireInit(PriorityMux(x))) def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = { for ((coverCause, label) <- coverCausesLabels) { property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_${label}") } } def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) = targets.map(h => h._1 && cond(h._2)).reduce(_\|\|_) def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else { // efficient means to compress 64-bit VA into vaddrBits+1 bits // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) val b = vaddrBitsExtended-1 val a = (a0 >> b).asSInt val msb = Mux(a === 0.S \|\| a === -1.S, ea(b), !ea(b-1)) Cat(msb, ea(b-1, 0)) } class Scoreboard(n: Int, zero: Boolean = false) { def set(en: Bool, addr: UInt): Unit = update(en, _next \| mask(en, addr)) def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr)) def read(addr: UInt): Bool = r(addr) def readBypassed(addr: UInt): Bool = _next(addr) private val _r = RegInit(0.U(n.W)) private val r = if (zero) (_r >> 1 << 1) else _r private var _next = r private var ens = false.B private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U) private def update(en: Bool, update: UInt) = { _next = update ens = ens \|\| en when (ens) { _r := _next } } } } class RegFile(n: Int, w: Int, zero: Boolean = false) { val rf = Mem(n, UInt(w.W)) private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0)) private val reads = ArrayBuffer[(UInt,UInt)]() private var canRead = true def read(addr: UInt) = { require(canRead) reads += addr -> Wire(UInt()) reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr)) reads.last._2 } def write(addr: UInt, data: UInt) = { canRead = false when (addr =/= 0.U) { access(addr) := data for ((raddr, rdata) <- reads) when (addr === raddr) { rdata := data } } } } object ImmGen { def apply(sel: UInt, inst: UInt) = { val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt) val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign) val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt) val b11 = Mux(sel === IMM_U \|\| sel === IMM_Z, 0.S, Mux(sel === IMM_UJ, inst(20).asSInt, Mux(sel === IMM_SB, inst(7).asSInt, sign))) val b10_5 = Mux(sel === IMM_U \|\| sel === IMM_Z, 0.U, inst(30,25)) val b4_1 = Mux(sel === IMM_U, 0.U, Mux(sel === IMM_S \|\| sel === IMM_SB, inst(11,8), Mux(sel === IMM_Z, inst(19,16), inst(24,21)))) val b0 = Mux(sel === IMM_S, inst(7), Mux(sel === IMM_I, inst(20), Mux(sel === IMM_Z, inst(15), 0.U))) Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt } } File Configs.scala: package ara import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.tile._ import freechips.rocketchip.subsystem._ import shuttle.common.{ShuttleTileAttachParams, ShuttleCoreVectorParams} class WithAraRocketVectorUnit(vLen: Int = 4096, nLanes: Int = 2, axiIdBits: Int = 4, cores: Option[Seq[Int]] = None, enableDelay: Boolean = false) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => { val buildVector = cores.map(_.contains(tp.tileParams.tileId)).getOrElse(true) require(nLanes >= 2) if (buildVector) tp.copy(tileParams = tp.tileParams.copy( core = tp.tileParams.core.copy( vector = Some(RocketCoreVectorParams( build = ((p: Parameters) => new AraRocketUnit(nLanes, axiIdBits, enableDelay)(p)), vLen = vLen, eLen = 64, vfLen = 64, vfh = false, vMemDataBits = 0, decoder = ((p: Parameters) => { val decoder = Module(new AraEarlyVectorDecode()(p)) decoder }), useDCache = false, issueVConfig = true, vExts = Nil )), ) )) else tp } case other => other } }) class WithAraShuttleVectorUnit(vLen: Int = 4096, nLanes: Int = 2, axiIdBits: Int = 4, cores: Option[Seq[Int]] = None, enableDelay: Boolean = false) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: ShuttleTileAttachParams => { val buildVector = cores.map(_.contains(tp.tileParams.tileId)).getOrElse(true) if (buildVector) tp.copy(tileParams = tp.tileParams.copy( core = tp.tileParams.core.copy( vector = Some(ShuttleCoreVectorParams( build = ((p: Parameters) => new AraShuttleUnit(nLanes, axiIdBits, enableDelay)(p)), vLen = vLen, vfLen = 64, vfh = false, decoder = ((p: Parameters) => { val decoder = Module(new AraEarlyVectorDecode()(p)) decoder }), issueVConfig = true, vExts = Nil )), ) )) else tp } case other => other } }) File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out } File CSR.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.LinkedHashMap import Instructions._ import CustomInstructions._ class MStatus extends Bundle { // not truly part of mstatus, but convenient val debug = Bool() val cease = Bool() val wfi = Bool() val isa = UInt(32.W) val dprv = UInt(PRV.SZ.W) // effective prv for data accesses val dv = Bool() // effective v for data accesses val prv = UInt(PRV.SZ.W) val v = Bool() val sd = Bool() val zero2 = UInt(23.W) val mpv = Bool() val gva = Bool() val mbe = Bool() val sbe = Bool() val sxl = UInt(2.W) val uxl = UInt(2.W) val sd_rv32 = Bool() val zero1 = UInt(8.W) val tsr = Bool() val tw = Bool() val tvm = Bool() val mxr = Bool() val sum = Bool() val mprv = Bool() val xs = UInt(2.W) val fs = UInt(2.W) val mpp = UInt(2.W) val vs = UInt(2.W) val spp = UInt(1.W) val mpie = Bool() val ube = Bool() val spie = Bool() val upie = Bool() val mie = Bool() val hie = Bool() val sie = Bool() val uie = Bool() } class MNStatus extends Bundle { val mpp = UInt(2.W) val zero3 = UInt(3.W) val mpv = Bool() val zero2 = UInt(3.W) val mie = Bool() val zero1 = UInt(3.W) } class HStatus extends Bundle { val zero6 = UInt(30.W) val vsxl = UInt(2.W) val zero5 = UInt(9.W) val vtsr = Bool() val vtw = Bool() val vtvm = Bool() val zero3 = UInt(2.W) val vgein = UInt(6.W) val zero2 = UInt(2.W) val hu = Bool() val spvp = Bool() val spv = Bool() val gva = Bool() val vsbe = Bool() val zero1 = UInt(5.W) } class DCSR extends Bundle { val xdebugver = UInt(2.W) val zero4 = UInt(2.W) val zero3 = UInt(12.W) val ebreakm = Bool() val ebreakh = Bool() val ebreaks = Bool() val ebreaku = Bool() val zero2 = Bool() val stopcycle = Bool() val stoptime = Bool() val cause = UInt(3.W) val v = Bool() val zero1 = UInt(2.W) val step = Bool() val prv = UInt(PRV.SZ.W) } class MIP(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val lip = Vec(coreParams.nLocalInterrupts, Bool()) val zero1 = Bool() val debug = Bool() // keep in sync with CSR.debugIntCause val rocc = Bool() val sgeip = Bool() val meip = Bool() val vseip = Bool() val seip = Bool() val ueip = Bool() val mtip = Bool() val vstip = Bool() val stip = Bool() val utip = Bool() val msip = Bool() val vssip = Bool() val ssip = Bool() val usip = Bool() } class Envcfg extends Bundle { val stce = Bool() // only for menvcfg/henvcfg val pbmte = Bool() // only for menvcfg/henvcfg val zero54 = UInt(54.W) val cbze = Bool() val cbcfe = Bool() val cbie = UInt(2.W) val zero3 = UInt(3.W) val fiom = Bool() def write(wdata: UInt) { val new_envcfg = wdata.asTypeOf(new Envcfg) fiom := new_envcfg.fiom // only FIOM is writable currently } } class PTBR(implicit p: Parameters) extends CoreBundle()(p) { def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0) def pgLevelsToMode(i: Int) = (xLen, i) match { case (32, 2) => 1 case (64, x) if x >= 3 && x <= 6 => x + 5 } val (modeBits, maxASIdBits) = xLen match { case 32 => (1, 9) case 64 => (4, 16) } require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen) val mode = UInt(modeBits.W) val asid = UInt(maxASIdBits.W) val ppn = UInt((maxPAddrBits - pgIdxBits).W) } object PRV { val SZ = 2 val U = 0 val S = 1 val H = 2 val M = 3 } object CSR { // commands val SZ = 3 def X = BitPat.dontCare(SZ) def N = 0.U(SZ.W) def R = 2.U(SZ.W) def I = 4.U(SZ.W) def W = 5.U(SZ.W) def S = 6.U(SZ.W) def C = 7.U(SZ.W) // mask a CSR cmd with a valid bit def maskCmd(valid: Bool, cmd: UInt): UInt = { // all commands less than CSR.I are treated by CSRFile as NOPs cmd & ~Mux(valid, 0.U, CSR.I) } val ADDRSZ = 12 def modeLSB: Int = 8 def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ) def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB) def busErrorIntCause = 128 def debugIntCause = 14 // keep in sync with MIP.debug def debugTriggerCause = { val res = debugIntCause require(!(Causes.all contains res)) res } def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause def rnmiBEUCause = 12 val firstCtr = CSRs.cycle val firstCtrH = CSRs.cycleh val firstHPC = CSRs.hpmcounter3 val firstHPCH = CSRs.hpmcounter3h val firstHPE = CSRs.mhpmevent3 val firstMHPC = CSRs.mhpmcounter3 val firstMHPCH = CSRs.mhpmcounter3h val firstHPM = 3 val nCtr = 32 val nHPM = nCtr - firstHPM val hpmWidth = 40 val maxPMPs = 16 } class PerfCounterIO(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val eventSel = Output(UInt(xLen.W)) val inc = Input(UInt(log2Ceil(1+retireWidth).W)) } class TracedInstruction(implicit p: Parameters) extends CoreBundle { val valid = Bool() val iaddr = UInt(coreMaxAddrBits.W) val insn = UInt(iLen.W) val priv = UInt(3.W) val exception = Bool() val interrupt = Bool() val cause = UInt(xLen.W) val tval = UInt((coreMaxAddrBits max iLen).W) val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W)) } class TraceAux extends Bundle { val enable = Bool() val stall = Bool() } class CSRDecodeIO(implicit p: Parameters) extends CoreBundle { val inst = Input(UInt(iLen.W)) def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0) val fp_illegal = Output(Bool()) val vector_illegal = Output(Bool()) val fp_csr = Output(Bool()) val vector_csr = Output(Bool()) val rocc_illegal = Output(Bool()) val read_illegal = Output(Bool()) val write_illegal = Output(Bool()) val write_flush = Output(Bool()) val system_illegal = Output(Bool()) val virtual_access_illegal = Output(Bool()) val virtual_system_illegal = Output(Bool()) } class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val ungated_clock = Input(Clock()) val interrupts = Input(new CoreInterrupts(hasBeu)) val hartid = Input(UInt(hartIdLen.W)) val rw = new Bundle { val addr = Input(UInt(CSR.ADDRSZ.W)) val cmd = Input(Bits(CSR.SZ.W)) val rdata = Output(Bits(xLen.W)) val wdata = Input(Bits(xLen.W)) } val decode = Vec(decodeWidth, new CSRDecodeIO) val csr_stall = Output(Bool()) // stall retire for wfi val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall val eret = Output(Bool()) val singleStep = Output(Bool()) val status = Output(new MStatus()) val hstatus = Output(new HStatus()) val gstatus = Output(new MStatus()) val ptbr = Output(new PTBR()) val hgatp = Output(new PTBR()) val vsatp = Output(new PTBR()) val evec = Output(UInt(vaddrBitsExtended.W)) val exception = Input(Bool()) val retire = Input(UInt(log2Up(1+retireWidth).W)) val cause = Input(UInt(xLen.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val tval = Input(UInt(vaddrBitsExtended.W)) val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W)) val mhtinst_read_pseudo = Input(Bool()) val gva = Input(Bool()) val time = Output(UInt(xLen.W)) val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W))) val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool())) val rocc_interrupt = Input(Bool()) val interrupt = Output(Bool()) val interrupt_cause = Output(UInt(xLen.W)) val bp = Output(Vec(nBreakpoints, new BP)) val pmp = Output(Vec(nPMPs, new PMP)) val counters = Vec(nPerfCounters, new PerfCounterIO) val csrw_counter = Output(UInt(CSR.nCtr.W)) val inhibit_cycle = Output(Bool()) val inst = Input(Vec(retireWidth, UInt(iLen.W))) val trace = Output(Vec(retireWidth, new TracedInstruction)) val mcontext = Output(UInt(coreParams.mcontextWidth.W)) val scontext = Output(UInt(coreParams.scontextWidth.W)) val fiom = Output(Bool()) val vector = usingVector.option(new Bundle { val vconfig = Output(new VConfig()) val vstart = Output(UInt(maxVLMax.log2.W)) val vxrm = Output(UInt(2.W)) val set_vs_dirty = Input(Bool()) val set_vconfig = Flipped(Valid(new VConfig)) val set_vstart = Flipped(Valid(vstart)) val set_vxsat = Input(Bool()) }) } class VConfig(implicit p: Parameters) extends CoreBundle { val vl = UInt((maxVLMax.log2 + 1).W) val vtype = new VType } object VType { def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = { val res = 0.U.asTypeOf(new VType) val in = that.asTypeOf(res) val vill = (in.max_vsew.U < in.vsew) \|\| !in.lmul_ok \|\| in.reserved =/= 0.U \|\| in.vill when (!vill \|\| ignore_vill.B) { res := in res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0) } res.reserved := 0.U res.vill := vill res } def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt = VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero) } class VType(implicit p: Parameters) extends CoreBundle { val vill = Bool() val reserved = UInt((xLen - 9).W) val vma = Bool() val vta = Bool() val vsew = UInt(3.W) val vlmul_sign = Bool() val vlmul_mag = UInt(2.W) def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt @deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9") def vlmul: UInt = vlmul_mag def max_vsew = log2Ceil(eLen/8) def max_vlmul = (1 << vlmul_mag.getWidth) - 1 def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B) def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1 def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U) def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = { val atLeastMaxVLMax = useMax \|\| Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U) val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0) val atLeastVLMax = atLeastMaxVLMax \|\| (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR val isZero = vill \|\| useZero Mux(!isZero && atLeastVLMax, vlMax, 0.U) \| Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U) } } class CSRFile( perfEventSets: EventSets = new EventSets(Seq()), customCSRs: Seq[CustomCSR] = Nil, roccCSRs: Seq[CustomCSR] = Nil, hasBeu: Boolean = false)(implicit p: Parameters) extends CoreModule()(p) with HasCoreParameters { val io = IO(new CSRFileIO(hasBeu) { val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO) val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO) }) io.rw_stall := false.B val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := PRV.M.U reset_mstatus.prv := PRV.M.U reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U) val reg_mstatus = RegInit(reset_mstatus) val new_prv = WireDefault(reg_mstatus.prv) reg_mstatus.prv := legalizePrivilege(new_prv) val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR())) reset_dcsr.xdebugver := 1.U reset_dcsr.prv := PRV.M.U val reg_dcsr = RegInit(reset_dcsr) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) sup.usip := false.B sup.ssip := usingSupervisor.B sup.vssip := usingHypervisor.B sup.msip := true.B sup.utip := false.B sup.stip := usingSupervisor.B sup.vstip := usingHypervisor.B sup.mtip := true.B sup.ueip := false.B sup.seip := usingSupervisor.B sup.vseip := usingHypervisor.B sup.meip := true.B sup.sgeip := false.B sup.rocc := usingRoCC.B sup.debug := false.B sup.zero1 := false.B sup.lip foreach { _ := true.B } val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U val del = WireDefault(sup) del.msip := false.B del.mtip := false.B del.meip := false.B (sup.asUInt \| supported_high_interrupts, del.asUInt) } val delegable_base_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_page_fault, Causes.breakpoint, Causes.load_page_fault, Causes.store_page_fault, Causes.misaligned_load, Causes.misaligned_store, Causes.illegal_instruction, Causes.user_ecall, ) val delegable_hypervisor_exceptions = Seq( Causes.virtual_supervisor_ecall, Causes.fetch_guest_page_fault, Causes.load_guest_page_fault, Causes.virtual_instruction, Causes.store_guest_page_fault, ) val delegable_exceptions = ( delegable_base_exceptions ++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq()) ).map(1 << _).sum.U val hs_delegable_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_access, Causes.illegal_instruction, Causes.breakpoint, Causes.misaligned_load, Causes.load_access, Causes.misaligned_store, Causes.store_access, Causes.user_ecall, Causes.fetch_page_fault, Causes.load_page_fault, Causes.store_page_fault).map(1 << _).sum.U val (hs_delegable_interrupts, mideleg_always_hs) = { val always = WireDefault(0.U.asTypeOf(new MIP())) always.vssip := usingHypervisor.B always.vstip := usingHypervisor.B always.vseip := usingHypervisor.B val deleg = WireDefault(always) deleg.lip.foreach { _ := usingHypervisor.B } (deleg.asUInt, always.asUInt) } val reg_debug = RegInit(false.B) val reg_dpc = Reg(UInt(vaddrBitsExtended.W)) val reg_dscratch0 = Reg(UInt(xLen.W)) val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W))) val reg_singleStepped = Reg(Bool()) val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W))) val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W))) val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W)) val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP)) val reg_pmp = Reg(Vec(nPMPs, new PMPReg)) val reg_mie = Reg(UInt(xLen.W)) val (reg_mideleg, read_mideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_interrupts \| mideleg_always_hs, 0.U)) } val (reg_medeleg, read_medeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U)) } val reg_mip = Reg(new MIP) val reg_mepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mcause = RegInit(0.U(xLen.W)) val reg_mtval = Reg(UInt(vaddrBitsExtended.W)) val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W)) val reg_mscratch = Reg(Bits(xLen.W)) val mtvecWidth = paddrBits min xLen val reg_mtvec = mtvecInit match { case Some(addr) => RegInit(addr.U(mtvecWidth.W)) case None => Reg(UInt(mtvecWidth.W)) } val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus())) reset_mnstatus.mpp := PRV.M.U val reg_mnscratch = Reg(Bits(xLen.W)) val reg_mnepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mncause = RegInit(0.U(xLen.W)) val reg_mnstatus = RegInit(reset_mnstatus) val reg_rnmie = RegInit(true.B) val nmie = reg_rnmie val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U val (reg_mcounteren, read_mcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingUser.B, reg & delegable_counters, 0.U)) } val (reg_scounteren, read_scounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U)) } val (reg_hideleg, read_hideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U)) } val (reg_hedeleg, read_hedeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U)) } val hs_delegable_counters = delegable_counters val (reg_hcounteren, read_hcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U)) } val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus)) val reg_hgatp = Reg(new PTBR) val reg_htval = Reg(reg_mtval2.cloneType) val read_hvip = reg_mip.asUInt & hs_delegable_interrupts val read_hie = reg_mie & hs_delegable_interrupts val (reg_vstvec, read_vstvec) = { val reg = Reg(UInt(vaddrBitsExtended.W)) (reg, formTVec(reg).sextTo(xLen)) } val reg_vsstatus = Reg(new MStatus) val reg_vsscratch = Reg(Bits(xLen.W)) val reg_vsepc = Reg(UInt(vaddrBitsExtended.W)) val reg_vscause = Reg(Bits(xLen.W)) val reg_vstval = Reg(UInt(vaddrBitsExtended.W)) val reg_vsatp = Reg(new PTBR) val reg_sepc = Reg(UInt(vaddrBitsExtended.W)) val reg_scause = Reg(Bits(xLen.W)) val reg_stval = Reg(UInt(vaddrBitsExtended.W)) val reg_sscratch = Reg(Bits(xLen.W)) val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W)) val reg_satp = Reg(new PTBR) val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) } val reg_fflags = Reg(UInt(5.W)) val reg_frm = Reg(UInt(3.W)) val reg_vconfig = usingVector.option(Reg(new VConfig)) val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W))) val reg_vxsat = usingVector.option(Reg(Bool())) val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W))) val reg_mtinst_read_pseudo = Reg(Bool()) val reg_htinst_read_pseudo = Reg(Bool()) // XLEN=32: 0x00002000 // XLEN=64: 0x00003000 val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W))) val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W)) io.inhibit_cycle := reg_mcountinhibit(0) val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2)) val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0)) else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) } val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W))) (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e } val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) => WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) } val mip = WireDefault(reg_mip) mip.lip := (io.interrupts.lip: Seq[Bool]) mip.mtip := io.interrupts.mtip mip.msip := io.interrupts.msip mip.meip := io.interrupts.meip // seip is the OR of reg_mip.seip and the actual line from the PLIC io.interrupts.seip.foreach { mip.seip := reg_mip.seip \|\| _ } // Simimlar sort of thing would apply if the PLIC had a VSEIP line: //io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip \|\| _ } mip.rocc := io.rocc_interrupt val read_mip = mip.asUInt & supported_interrupts val read_hip = read_mip & hs_delegable_interrupts val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U)) val pending_interrupts = high_interrupts \| (read_mip & reg_mie) val d_interrupts = io.interrupts.debug << CSR.debugIntCause val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi => (((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) \| io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U), !io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B) val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U \|\| reg_mstatus.mie), ~(~pending_interrupts \| read_mideleg), 0.U) val s_interrupts = Mux(nmie && (reg_mstatus.v \|\| reg_mstatus.prv < PRV.S.U \|\| (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U) val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U \|\| reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U) val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts)) val interruptMSB = BigInt(1) << (xLen-1) val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt io.interrupt := (anyInterrupt && !io.singleStep \|\| reg_singleStepped) && !(reg_debug \|\| io.status.cease) io.interrupt_cause := interruptCause io.bp := reg_bp take nBreakpoints io.mcontext := reg_mcontext.getOrElse(0.U) io.scontext := reg_scontext.getOrElse(0.U) io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) \|\| (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) \|\| (reg_mstatus.v && reg_henvcfg.fiom) io.pmp := reg_pmp.map(PMP(_)) val isaMaskString = (if (usingMulDiv) "M" else "") + (if (usingAtomics) "A" else "") + (if (fLen >= 32) "F" else "") + (if (fLen >= 64) "D" else "") + (if (coreParams.hasV) "V" else "") + (if (usingCompressed) "C" else "") val isaString = (if (coreParams.useRVE) "E" else "I") + isaMaskString + (if (customIsaExt.isDefined \|\| usingRoCC) "X" else "") + (if (usingSupervisor) "S" else "") + (if (usingHypervisor) "H" else "") + (if (usingUser) "U" else "") val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) \| isaStringToMask(isaString) val reg_misa = RegInit(isaMax.U) val read_mstatus = io.status.asUInt.extract(xLen-1,0) val read_mtvec = formTVec(reg_mtvec).padTo(xLen) val read_stvec = formTVec(reg_stvec).sextTo(xLen) val read_mapping = LinkedHashMap[Int,Bits]( CSRs.tselect -> reg_tselect, CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt, CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen), CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt, CSRs.misa -> reg_misa, CSRs.mstatus -> read_mstatus, CSRs.mtvec -> read_mtvec, CSRs.mip -> read_mip, CSRs.mie -> reg_mie, CSRs.mscratch -> reg_mscratch, CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen), CSRs.mtval -> reg_mtval.sextTo(xLen), CSRs.mcause -> reg_mcause, CSRs.mhartid -> io.hartid) val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.dcsr -> reg_dcsr.asUInt, CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen), CSRs.dscratch0 -> reg_dscratch0.asUInt) ++ reg_dscratch1.map(r => CSRs.dscratch1 -> r) val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus())) read_mnstatus.mpp := reg_mnstatus.mpp read_mnstatus.mpv := reg_mnstatus.mpv read_mnstatus.mie := reg_rnmie val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits]( CustomCSRs.mnscratch -> reg_mnscratch, CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen), CustomCSRs.mncause -> reg_mncause, CustomCSRs.mnstatus -> read_mnstatus.asUInt) val context_csrs = LinkedHashMap[Int,Bits]() ++ reg_mcontext.map(r => CSRs.mcontext -> r) ++ reg_scontext.map(r => CSRs.scontext -> r) val read_fcsr = Cat(reg_frm, reg_fflags) val fp_csrs = LinkedHashMap[Int,Bits]() ++ usingFPU.option(CSRs.fflags -> reg_fflags) ++ usingFPU.option(CSRs.frm -> reg_frm) ++ (usingFPU \|\| usingVector).option(CSRs.fcsr -> read_fcsr) val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U)) val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.vxsat -> reg_vxsat.get, CSRs.vxrm -> reg_vxrm.get, CSRs.vcsr -> read_vcsr, CSRs.vstart -> reg_vstart.get, CSRs.vtype -> reg_vconfig.get.vtype.asUInt, CSRs.vl -> reg_vconfig.get.vl, CSRs.vlenb -> (vLen / 8).U) read_mapping ++= debug_csrs read_mapping ++= nmi_csrs read_mapping ++= context_csrs read_mapping ++= fp_csrs read_mapping ++= vector_csrs if (coreParams.haveBasicCounters) { read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit read_mapping += CSRs.mcycle -> reg_cycle read_mapping += CSRs.minstret -> reg_instret for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U) zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) { read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN if (xLen == 32) { read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh } } if (usingUser) { read_mapping += CSRs.mcounteren -> read_mcounteren } read_mapping += CSRs.cycle -> reg_cycle read_mapping += CSRs.instret -> reg_instret if (xLen == 32) { read_mapping += CSRs.mcycleh -> (reg_cycle >> 32) read_mapping += CSRs.minstreth -> (reg_instret >> 32) read_mapping += CSRs.cycleh -> (reg_cycle >> 32) read_mapping += CSRs.instreth -> (reg_instret >> 32) } } if (usingUser) { read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt if (xLen == 32) read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32) } val sie_mask = { val sgeip_mask = WireInit(0.U.asTypeOf(new MIP)) sgeip_mask.sgeip := true.B read_mideleg & ~(hs_delegable_interrupts \| sgeip_mask.asUInt) } if (usingSupervisor) { val read_sie = reg_mie & sie_mask val read_sip = read_mip & sie_mask val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus)) read_sstatus.sd := io.status.sd read_sstatus.uxl := io.status.uxl read_sstatus.sd_rv32 := io.status.sd_rv32 read_sstatus.mxr := io.status.mxr read_sstatus.sum := io.status.sum read_sstatus.xs := io.status.xs read_sstatus.fs := io.status.fs read_sstatus.vs := io.status.vs read_sstatus.spp := io.status.spp read_sstatus.spie := io.status.spie read_sstatus.sie := io.status.sie read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0) read_mapping += CSRs.sip -> read_sip.asUInt read_mapping += CSRs.sie -> read_sie.asUInt read_mapping += CSRs.sscratch -> reg_sscratch read_mapping += CSRs.scause -> reg_scause read_mapping += CSRs.stval -> reg_stval.sextTo(xLen) read_mapping += CSRs.satp -> reg_satp.asUInt read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen) read_mapping += CSRs.stvec -> read_stvec read_mapping += CSRs.scounteren -> read_scounteren read_mapping += CSRs.mideleg -> read_mideleg read_mapping += CSRs.medeleg -> read_medeleg read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt } val pmpCfgPerCSR = xLen / new PMPConfig().getWidth def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR) if (reg_pmp.nonEmpty) { require(reg_pmp.size <= CSR.maxPMPs) val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP)) for (i <- 0 until read_pmp.size by pmpCfgPerCSR) read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt for ((pmp, i) <- read_pmp.zipWithIndex) read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr } // implementation-defined CSRs def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = { require(csr.mask >= 0 && csr.mask.bitLength <= xLen) require(!read_mapping.contains(csr.id)) val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W))) val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U csr_io.ren := read when (read && csr_io.stall) { io.rw_stall := true.B } read_mapping += csr.id -> reg reg } val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2)) val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2)) if (usingHypervisor) { read_mapping += CSRs.mtinst -> read_mtinst read_mapping += CSRs.mtval2 -> reg_mtval2 val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.hstatus -> read_hstatus read_mapping += CSRs.hedeleg -> read_hedeleg read_mapping += CSRs.hideleg -> read_hideleg read_mapping += CSRs.hcounteren-> read_hcounteren read_mapping += CSRs.hgatp -> reg_hgatp.asUInt read_mapping += CSRs.hip -> read_hip read_mapping += CSRs.hie -> read_hie read_mapping += CSRs.hvip -> read_hvip read_mapping += CSRs.hgeie -> 0.U read_mapping += CSRs.hgeip -> 0.U read_mapping += CSRs.htval -> reg_htval read_mapping += CSRs.htinst -> read_htinst read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt if (xLen == 32) read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32) val read_vsie = (read_hie & read_hideleg) >> 1 val read_vsip = (read_hip & read_hideleg) >> 1 val read_vsepc = readEPC(reg_vsepc).sextTo(xLen) val read_vstval = reg_vstval.sextTo(xLen) val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.vsstatus -> read_vsstatus read_mapping += CSRs.vsip -> read_vsip read_mapping += CSRs.vsie -> read_vsie read_mapping += CSRs.vsscratch -> reg_vsscratch read_mapping += CSRs.vscause -> reg_vscause read_mapping += CSRs.vstval -> read_vstval read_mapping += CSRs.vsatp -> reg_vsatp.asUInt read_mapping += CSRs.vsepc -> read_vsepc read_mapping += CSRs.vstvec -> read_vstvec } // mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U)) val decoded_addr = { val addr = Cat(io.status.v, io.rw.addr) val pats = for (((k, _), i) <- read_mapping.zipWithIndex) yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B))) val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats) val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap for ((k, v) <- unvirtualized_mapping) yield k -> { val alt: Option[Bool] = CSR.mode(k) match { // hcontext was assigned an unfortunate address; it lives where a // hypothetical vscontext will live. Exclude them from the S/VS remapping. // (on separate lines so scala-lint doesnt do something stupid) case _ if k == CSRs.scontext => None case _ if k == CSRs.hcontext => None // When V=1, if a corresponding VS CSR exists, access it instead... case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB)) // ...and don't access the original S-mode version. case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B) case _ => None } alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v) } } val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata) val system_insn = io.rw.cmd === CSR.I val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU) val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N), EBREAK-> List(N,Y,N,N,N,N,N,N,N), MRET-> List(N,N,Y,N,N,N,N,N,N), CEASE-> List(N,N,N,Y,N,N,N,N,N), WFI-> List(N,N,N,N,Y,N,N,N,N)) ++ usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++ coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++ usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++ usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++ usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++ (if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq()) val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = { val insn = ECALL.value.U \| (io.rw.addr << 20) DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool) } for (io_dec <- io.decode) { val addr = io_dec.inst(31, 20) def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_\|\|_) def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U)) val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil = DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool) val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) \|\| addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U)) val allow_wfi = (!usingSupervisor).B \|\| reg_mstatus.prv > PRV.S.U \|\| !reg_mstatus.tw && (!reg_mstatus.v \|\| !reg_hstatus.vtw) val allow_sfence_vma = (!usingVM).B \|\| reg_mstatus.prv > PRV.S.U \|\| !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) val allow_hfence_vvma = (!usingHypervisor).B \|\| !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U) val allow_hlsv = (!usingHypervisor).B \|\| !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U \|\| reg_hstatus.hu) val allow_sret = (!usingSupervisor).B \|\| reg_mstatus.prv > PRV.S.U \|\| !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0) val allow_counter = (reg_mstatus.prv > PRV.S.U \|\| read_mcounteren(counter_addr)) && (!usingSupervisor.B \|\| reg_mstatus.prv >= PRV.S.U \|\| read_scounteren(counter_addr)) && (!usingHypervisor.B \|\| !reg_mstatus.v \|\| read_hcounteren(counter_addr)) io_dec.fp_illegal := io.status.fs === 0.U \|\| reg_mstatus.v && reg_vsstatus.fs === 0.U \|\| !reg_misa('f'-'a') io_dec.vector_illegal := io.status.vs === 0.U \|\| reg_mstatus.v && reg_vsstatus.vs === 0.U \|\| !reg_misa('v'-'a') io_dec.fp_csr := decodeFast(fp_csrs.keys.toList) io_dec.vector_csr := decodeFast(vector_csrs.keys.toList) io_dec.rocc_illegal := io.status.xs === 0.U \|\| reg_mstatus.v && reg_vsstatus.xs === 0.U \|\| !reg_misa('x'-'a') val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) \|\| usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U val csr_exists = decodeAny(read_mapping) io_dec.read_illegal := !csr_addr_legal \|\| !csr_exists \|\| ((addr === CSRs.satp.U \|\| addr === CSRs.hgatp.U) && !allow_sfence_vma) \|\| is_counter && !allow_counter \|\| decodeFast(debug_csrs.keys.toList) && !reg_debug \|\| decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal \|\| io_dec.fp_csr && io_dec.fp_illegal io_dec.write_illegal := addr(11,10).andR io_dec.write_flush := { val addr_m = addr \| (PRV.M.U << CSR.modeLSB) !(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U) } io_dec.system_illegal := !csr_addr_legal && !is_hlsv \|\| is_wfi && !allow_wfi \|\| is_ret && !allow_sret \|\| is_ret && addr(10) && addr(7) && !reg_debug \|\| (is_sfence \|\| is_hfence_gvma) && !allow_sfence_vma \|\| is_hfence_vvma && !allow_hfence_vvma \|\| is_hlsv && !allow_hlsv io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && ( CSR.mode(addr) === PRV.H.U \|\| is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) \|\| !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) \|\| CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) \|\| addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm) io_dec.virtual_system_illegal := reg_mstatus.v && ( is_hfence_vvma \|\| is_hfence_gvma \|\| is_hlsv \|\| is_wfi && (!reg_mstatus.prv(0) \|\| !reg_mstatus.tw && reg_hstatus.vtw) \|\| is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) \|\| reg_hstatus.vtsr) \|\| is_sfence && (!reg_mstatus.prv(0) \|\| reg_hstatus.vtvm)) } val cause = Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv), Mux[UInt](insn_break, Causes.breakpoint.U, io.cause)) val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0) val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0) val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv) val trapToDebug = usingDebug.B && (reg_singleStepped \|\| causeIsDebugInt \|\| causeIsDebugTrigger \|\| causeIsDebugBreak \|\| reg_debug) val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800)) val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808)) val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U) val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs)) val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs)) def mtvecBaseAlign = 2 def mtvecInterruptAlign = { require(reg_mip.getWidth <= xLen) log2Ceil(xLen) } val notDebugTVec = { val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec) val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset) val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign) } val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U \|\| cause_lsbs === CSR.rnmiBEUCause.U) val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U val causeIsNmi = causeIsRnmiInt val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U) val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U) val trapToNmiInt = usingNMI.B && causeIsNmi val trapToNmiXcpt = usingNMI.B && !nmie val trapToNmi = trapToNmiInt \|\| trapToNmiXcpt val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1 val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec)) io.evec := tvec io.ptbr := reg_satp io.hgatp := reg_hgatp io.vsatp := reg_vsatp io.eret := insn_call \|\| insn_break \|\| insn_ret io.singleStep := reg_dcsr.step && !reg_debug io.status := reg_mstatus io.status.sd := io.status.fs.andR \|\| io.status.xs.andR \|\| io.status.vs.andR io.status.debug := reg_debug io.status.isa := reg_misa io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv) io.status.dv := reg_mstatus.v \|\| Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B) io.status.sd_rv32 := (xLen == 32).B && io.status.sd io.status.mpv := reg_mstatus.mpv io.status.gva := reg_mstatus.gva io.hstatus := reg_hstatus io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.gstatus := reg_vsstatus io.gstatus.sd := io.gstatus.fs.andR \|\| io.gstatus.xs.andR \|\| io.gstatus.vs.andR io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd val exception = insn_call \|\| insn_break \|\| io.exception assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive") when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B } when (pending_interrupts.orR \|\| io.interrupts.debug \|\| exception) { reg_wfi := false.B } io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } ) when (io.retire(0) \|\| exception) { reg_singleStepped := true.B } when (!io.singleStep) { reg_singleStepped := false.B } assert(!io.singleStep \|\| io.retire <= 1.U) assert(!reg_singleStepped \|\| io.retire === 0.U) val epc = formEPC(io.pc) val tval = Mux(insn_break, epc, io.tval) when (exception) { when (trapToDebug) { when (!reg_debug) { reg_mstatus.v := false.B reg_debug := true.B reg_dpc := epc reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U))) reg_dcsr.prv := trimPrivilege(reg_mstatus.prv) reg_dcsr.v := reg_mstatus.v new_prv := PRV.M.U } }.elsewhen (trapToNmiInt) { when (reg_rnmie) { reg_mstatus.v := false.B reg_mnstatus.mpv := reg_mstatus.v reg_rnmie := false.B reg_mnepc := epc reg_mncause := (BigInt(1) << (xLen-1)).U \| Mux(causeIsRnmiBEU, 3.U, 2.U) reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv) new_prv := PRV.M.U } }.elsewhen (delegateVS && nmie) { reg_mstatus.v := true.B reg_vsstatus.spp := reg_mstatus.prv reg_vsepc := epc reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause) reg_vstval := tval reg_vsstatus.spie := reg_vsstatus.sie reg_vsstatus.sie := false.B new_prv := PRV.S.U }.elsewhen (delegate && nmie) { reg_mstatus.v := false.B reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp) reg_hstatus.gva := io.gva reg_hstatus.spv := reg_mstatus.v reg_sepc := epc reg_scause := cause reg_stval := tval reg_htval := io.htval reg_htinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.spie := reg_mstatus.sie reg_mstatus.spp := reg_mstatus.prv reg_mstatus.sie := false.B new_prv := PRV.S.U }.otherwise { reg_mstatus.v := false.B reg_mstatus.mpv := reg_mstatus.v reg_mstatus.gva := io.gva reg_mepc := epc reg_mcause := cause reg_mtval := tval reg_mtval2 := io.htval reg_mtinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.mpie := reg_mstatus.mie reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv) reg_mstatus.mie := false.B new_prv := PRV.M.U } } for (i <- 0 until supported_interrupts.getWidth) { val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"INTERRUPT_M_$i") property.cover(en && delegable && delegate, s"INTERRUPT_S_$i") } for (i <- 0 until xLen) { val supported_exceptions: BigInt = 0x8fe \| (if (usingCompressed && !coreParams.misaWritable) 0 else 1) \| (if (usingUser) 0x100 else 0) \| (if (usingSupervisor) 0x200 else 0) \| (if (usingVM) 0xb000 else 0) if (((supported_exceptions >> i) & 1) != 0) { val en = exception && cause === i.U val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"EXCEPTION_M_$i") property.cover(en && delegable && delegate, s"EXCEPTION_S_$i") } } when (insn_ret) { val ret_prv = WireInit(UInt(), DontCare) when (usingSupervisor.B && !io.rw.addr(9)) { when (!reg_mstatus.v) { reg_mstatus.sie := reg_mstatus.spie reg_mstatus.spie := true.B reg_mstatus.spp := PRV.U.U ret_prv := reg_mstatus.spp reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv io.evec := readEPC(reg_sepc) reg_hstatus.spv := false.B }.otherwise { reg_vsstatus.sie := reg_vsstatus.spie reg_vsstatus.spie := true.B reg_vsstatus.spp := PRV.U.U ret_prv := reg_vsstatus.spp reg_mstatus.v := usingHypervisor.B io.evec := readEPC(reg_vsepc) } }.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) { ret_prv := reg_dcsr.prv reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U reg_debug := false.B io.evec := readEPC(reg_dpc) }.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) { ret_prv := reg_mnstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U reg_rnmie := true.B io.evec := readEPC(reg_mnepc) }.otherwise { reg_mstatus.mie := reg_mstatus.mpie reg_mstatus.mpie := true.B reg_mstatus.mpp := legalizePrivilege(PRV.U.U) reg_mstatus.mpv := false.B ret_prv := reg_mstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U io.evec := readEPC(reg_mepc) } new_prv := ret_prv when (usingUser.B && ret_prv <= PRV.S.U) { reg_mstatus.mprv := false.B } } io.time := reg_cycle io.csr_stall := reg_wfi \|\| io.status.cease io.status.cease := RegEnable(true.B, false.B, insn_cease) io.status.wfi := reg_wfi for ((io, reg) <- io.customCSRs zip reg_custom) { io.wen := false.B io.wdata := wdata io.value := reg } for ((io, reg) <- io.roccCSRs zip reg_rocc) { io.wen := false.B io.wdata := wdata io.value := reg } io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) // cover access to register val coverable_counters = read_mapping.filterNot { case (k, _) => k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM } coverable_counters.foreach( {case (k, v) => { when (!k.U(11,10).andR) { // Cover points for RW CSR registers property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } .otherwise { // Cover points for RO CSR registers property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } }}) val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B)) io.vector.foreach { vio => when (set_vs_dirty) { assert(reg_mstatus.vs > 0.U) when (reg_mstatus.v) { reg_vsstatus.vs := 3.U } reg_mstatus.vs := 3.U } } val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B)) if (coreParams.haveFSDirty) { when (set_fs_dirty) { assert(reg_mstatus.fs > 0.U) when (reg_mstatus.v) { reg_vsstatus.fs := 3.U } reg_mstatus.fs := 3.U } } io.fcsr_rm := reg_frm when (io.fcsr_flags.valid) { reg_fflags := reg_fflags \| io.fcsr_flags.bits set_fs_dirty := true.B } io.vector.foreach { vio => when (vio.set_vxsat) { reg_vxsat.get := true.B set_vs_dirty := true.B } } val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) \|\| io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U) when (csr_wen) { val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB / val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_)) when (decoded_addr(CSRs.mstatus)) { val new_mstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.mie := new_mstatus.mie reg_mstatus.mpie := new_mstatus.mpie if (usingUser) { reg_mstatus.mprv := new_mstatus.mprv reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp) if (usingSupervisor) { reg_mstatus.spp := new_mstatus.spp reg_mstatus.spie := new_mstatus.spie reg_mstatus.sie := new_mstatus.sie reg_mstatus.tw := new_mstatus.tw reg_mstatus.tsr := new_mstatus.tsr } if (usingVM) { reg_mstatus.mxr := new_mstatus.mxr reg_mstatus.sum := new_mstatus.sum reg_mstatus.tvm := new_mstatus.tvm } if (usingHypervisor) { reg_mstatus.mpv := new_mstatus.mpv reg_mstatus.gva := new_mstatus.gva } } if (usingSupervisor \|\| usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs) reg_mstatus.vs := formVS(new_mstatus.vs) } when (decoded_addr(CSRs.misa)) { val mask = isaStringToMask(isaMaskString).U(xLen.W) val f = wdata('f' - 'a') // suppress write if it would cause the next fetch to be misaligned when (!usingCompressed.B \|\| !io.pc(1) \|\| wdata('c' - 'a')) { if (coreParams.misaWritable) reg_misa := ~(~wdata \| (!f << ('d' - 'a'))) & mask \| reg_misa & ~mask } } when (decoded_addr(CSRs.mip)) { // MIP should be modified based on the value in reg_mip, not the value // in read_mip, since read_mip.seip is the OR of reg_mip.seip and // io.interrupts.seip. We don't want the value on the PLIC line to // inadvertently be OR'd into read_mip.seip. val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP) if (usingSupervisor) { reg_mip.ssip := new_mip.ssip reg_mip.stip := new_mip.stip reg_mip.seip := new_mip.seip } if (usingHypervisor) { reg_mip.vssip := new_mip.vssip } } when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts } when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) } when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata } if (mtvecWritable) when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata } when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U } when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata } if (usingNMI) { val new_mnstatus = wdata.asTypeOf(new MNStatus()) when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata } when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) } when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U } when (decoded_addr(CustomCSRs.mnstatus)) { reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp) reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv reg_rnmie := reg_rnmie \| new_mnstatus.mie // mnie bit settable but not clearable from software } } for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) { writeCounter(i + CSR.firstMHPC, c, wdata) when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) } } if (coreParams.haveBasicCounters) { when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero writeCounter(CSRs.mcycle, reg_cycle, wdata) writeCounter(CSRs.minstret, reg_instret, wdata) } if (usingFPU) { when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata } when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata } when (decoded_addr(CSRs.fcsr)) { set_fs_dirty := true.B reg_fflags := wdata reg_frm := wdata >> reg_fflags.getWidth } } if (usingDebug) { when (decoded_addr(CSRs.dcsr)) { val new_dcsr = wdata.asTypeOf(new DCSR()) reg_dcsr.step := new_dcsr.step reg_dcsr.ebreakm := new_dcsr.ebreakm if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv) if (usingHypervisor) reg_dcsr.v := new_dcsr.v } when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) } when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata } reg_dscratch1.foreach { r => when (decoded_addr(CSRs.dscratch1)) { r := wdata } } } if (usingSupervisor) { when (decoded_addr(CSRs.sstatus)) { val new_sstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.sie := new_sstatus.sie reg_mstatus.spie := new_sstatus.spie reg_mstatus.spp := new_sstatus.spp reg_mstatus.fs := formFS(new_sstatus.fs) reg_mstatus.vs := formVS(new_sstatus.vs) if (usingVM) { reg_mstatus.mxr := new_sstatus.mxr reg_mstatus.sum := new_sstatus.sum } } when (decoded_addr(CSRs.sip)) { val new_sip = ((read_mip & ~read_mideleg) \| (wdata & read_mideleg)).asTypeOf(new MIP()) reg_mip.ssip := new_sip.ssip } when (decoded_addr(CSRs.satp)) { if (usingVM) { val new_satp = wdata.asTypeOf(new PTBR()) when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) { reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_\|_).U reg_satp.ppn := new_satp.ppn(ppnBits-1,0) if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0) } } } when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) \| (wdata & sie_mask) } when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata } when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) } when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata } when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask } when (decoded_addr(CSRs.stval)) { reg_stval := wdata } when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata } when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata } when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata } when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) } } if (usingHypervisor) { when (decoded_addr(CSRs.hstatus)) { val new_hstatus = wdata.asTypeOf(new HStatus()) reg_hstatus.gva := new_hstatus.gva reg_hstatus.spv := new_hstatus.spv reg_hstatus.spvp := new_hstatus.spvp reg_hstatus.hu := new_hstatus.hu reg_hstatus.vtvm := new_hstatus.vtvm reg_hstatus.vtw := new_hstatus.vtw reg_hstatus.vtsr := new_hstatus.vtsr reg_hstatus.vsxl := new_hstatus.vsxl } when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata } when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata } when (decoded_addr(CSRs.hgatp)) { val new_hgatp = wdata.asTypeOf(new PTBR()) val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_)) when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) { reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_\|_).U } reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W)) if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0) } when (decoded_addr(CSRs.hip)) { val new_hip = ((read_mip & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_hip.vssip } when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts) } when (decoded_addr(CSRs.hvip)) { val new_sip = ((read_mip & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_sip.vssip reg_mip.vstip := new_sip.vstip reg_mip.vseip := new_sip.vseip } when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata } when (decoded_addr(CSRs.htval)) { reg_htval := wdata } when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata } val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12)) when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo } when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo } when (decoded_addr(CSRs.vsstatus)) { val new_vsstatus = wdata.asTypeOf(new MStatus()) reg_vsstatus.sie := new_vsstatus.sie reg_vsstatus.spie := new_vsstatus.spie reg_vsstatus.spp := new_vsstatus.spp reg_vsstatus.mxr := new_vsstatus.mxr reg_vsstatus.sum := new_vsstatus.sum reg_vsstatus.fs := formFS(new_vsstatus.fs) reg_vsstatus.vs := formVS(new_vsstatus.vs) } when (decoded_addr(CSRs.vsip)) { val new_vsip = ((read_hip & ~read_hideleg) \| ((wdata << 1) & read_hideleg)).asTypeOf(new MIP()) reg_mip.vssip := new_vsip.vssip } when (decoded_addr(CSRs.vsatp)) { val new_vsatp = wdata.asTypeOf(new PTBR()) val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U)) when (mode_ok) { reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_\|_).U } when (mode_ok \|\| !reg_mstatus.v) { reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0) if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0) } } when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) \| ((wdata << 1) & read_hideleg) } when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata } when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) } when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata } when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask } when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata } when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) } } if (usingUser) { when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata } when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) } } if (nBreakpoints > 0) { when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata } for ((bp, i) <- reg_bp.zipWithIndex) { when (i.U === reg_tselect && (!bp.control.dmode \|\| reg_debug)) { when (decoded_addr(CSRs.tdata2)) { bp.address := wdata } when (decoded_addr(CSRs.tdata3)) { if (coreParams.mcontextWidth > 0) { bp.textra.mselect := wdata(bp.textra.mselectPos) bp.textra.mvalue := wdata >> bp.textra.mvaluePos } if (coreParams.scontextWidth > 0) { bp.textra.sselect := wdata(bp.textra.sselectPos) bp.textra.svalue := wdata >> bp.textra.svaluePos } } when (decoded_addr(CSRs.tdata1)) { bp.control := wdata.asTypeOf(bp.control) val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control) val dMode = newBPC.dmode && reg_debug && (prevDMode \|\| !prevChain) bp.control.dmode := dMode when (dMode \|\| (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U } bp.control.chain := newBPC.chain && !(prevChain \|\| nextChain) && (dMode \|\| !nextDMode) } } } } reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }} reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }} if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) { require(xLen % pmp.cfg.getWidth == 0) when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) { val newCfg = (wdata >> ((i pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig()) pmp.cfg := newCfg // disallow unreadable but writable PMPs pmp.cfg.w := newCfg.w && newCfg.r // can't select a=NA4 with coarse-grained PMPs if (pmpGranularity.log2 > PMP.lgAlign) pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR) } when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) { pmp.addr := wdata } } def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (decoded_addr(csr.id)) { reg := (wdata & mask) \| (reg & ~mask) io.wen := true.B } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { writeCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { writeCustomCSR(io, csr, reg) } if (usingVector) { when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata } when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata } when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata } when (decoded_addr(CSRs.vcsr)) { set_vs_dirty := true.B reg_vxsat.get := wdata reg_vxrm.get := wdata >> 1 } } } def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (io.set) { reg := (io.sdata & mask) \| (reg & ~mask) } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { setCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { setCustomCSR(io, csr, reg) } io.vector.map { vio => when (vio.set_vconfig.valid) { // user of CSRFile is responsible for set_vs_dirty in this case assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax) reg_vconfig.get := vio.set_vconfig.bits } when (vio.set_vstart.valid) { set_vs_dirty := true.B reg_vstart.get := vio.set_vstart.bits } vio.vstart := reg_vstart.get vio.vconfig := reg_vconfig.get vio.vxrm := reg_vxrm.get when (reset.asBool) { reg_vconfig.get.vl := 0.U reg_vconfig.get.vtype := 0.U.asTypeOf(new VType) reg_vconfig.get.vtype.vill := true.B } } when(reset.asBool) { reg_satp.mode := 0.U reg_vsatp.mode := 0.U reg_hgatp.mode := 0.U } if (!usingVM) { reg_satp.mode := 0.U reg_satp.ppn := 0.U reg_satp.asid := 0.U } if (!usingHypervisor) { reg_vsatp.mode := 0.U reg_vsatp.ppn := 0.U reg_vsatp.asid := 0.U reg_hgatp.mode := 0.U reg_hgatp.ppn := 0.U reg_hgatp.asid := 0.U } if (!(asIdBits > 0)) { reg_satp.asid := 0.U reg_vsatp.asid := 0.U } if (!(vmIdBits > 0)) { reg_hgatp.asid := 0.U } reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U) if (nBreakpoints <= 1) reg_tselect := 0.U for (bpc <- reg_bp map {_.control}) { bpc.ttype := bpc.tType.U bpc.maskmax := bpc.maskMax.U bpc.reserved := 0.U bpc.zero := 0.U bpc.h := false.B if (!usingSupervisor) bpc.s := false.B if (!usingUser) bpc.u := false.B if (!usingSupervisor && !usingUser) bpc.m := true.B when (reset.asBool) { bpc.action := 0.U bpc.dmode := false.B bpc.chain := false.B bpc.r := false.B bpc.w := false.B bpc.x := false.B } } for (bpx <- reg_bp map {_.textra}) { if (coreParams.mcontextWidth == 0) bpx.mselect := false.B if (coreParams.scontextWidth == 0) bpx.sselect := false.B } for (bp <- reg_bp drop nBreakpoints) bp := 0.U.asTypeOf(new BP()) for (pmp <- reg_pmp) { pmp.cfg.res := 0.U when (reset.asBool) { pmp.reset() } } for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) { t.exception := io.retire >= i.U && exception t.valid := io.retire > i.U \|\| t.exception t.insn := insn t.iaddr := io.pc t.priv := Cat(reg_debug, reg_mstatus.prv) t.cause := cause t.interrupt := cause(xLen-1) t.tval := io.tval t.wdata.foreach(_ := DontCare) } def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = { val nonstandard = supported_interrupts.getWidth-1 to 12 by -1 // MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4) val priority = nonstandard ++ standard val masks = masksIn.reverse val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_\|\|_) val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U)))) (any, which) } def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = { (Mux(cmd(1), rdata, 0.U) \| wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U) } def legalizePrivilege(priv: UInt): UInt = if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv) else if (usingUser) Fill(2, priv(0)) else PRV.M.U def trimPrivilege(priv: UInt): UInt = if (usingSupervisor) priv else legalizePrivilege(priv) def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { if (xLen == 32) { val hi = lo + CSRs.mcycleh - CSRs.mcycle when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } } else { when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) } } } def formEPC(x: UInt) = ~(~x \| (if (usingCompressed) 1.U else 3.U)) def readEPC(x: UInt) = ~(~x \| Mux(reg_misa('c' - 'a'), 1.U, 3.U)) def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) \| 2).U, 2.U) def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_\|_) def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR) def formVS(vs: UInt) = if (usingVector) vs else 0.U }	module Rocket( // @[RocketCore.scala:153:7] input clock, // @[RocketCore.scala:153:7] input reset, // @[RocketCore.scala:153:7] input io_hartid, // @[RocketCore.scala:134:14] input io_interrupts_debug, // @[RocketCore.scala:134:14] input io_interrupts_mtip, // @[RocketCore.scala:134:14] input io_interrupts_msip, // @[RocketCore.scala:134:14] input io_interrupts_meip, // @[RocketCore.scala:134:14] input io_interrupts_seip, // @[RocketCore.scala:134:14] output io_imem_might_request, // @[RocketCore.scala:134:14] output io_imem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_imem_req_bits_pc, // @[RocketCore.scala:134:14] output io_imem_req_bits_speculative, // @[RocketCore.scala:134:14] output io_imem_sfence_valid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_imem_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_asid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_hv, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_hg, // @[RocketCore.scala:134:14] output io_imem_resp_ready, // @[RocketCore.scala:134:14] input io_imem_resp_valid, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_btb_cfiType, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_taken, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_btb_mask, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bridx, // @[RocketCore.scala:134:14] input [38:0] io_imem_resp_bits_btb_target, // @[RocketCore.scala:134:14] input [4:0] io_imem_resp_bits_btb_entry, // @[RocketCore.scala:134:14] input [7:0] io_imem_resp_bits_btb_bht_history, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bht_value, // @[RocketCore.scala:134:14] input [39:0] io_imem_resp_bits_pc, // @[RocketCore.scala:134:14] input [31:0] io_imem_resp_bits_data, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_mask, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_pf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_gf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_ae_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_imem_gpa_valid, // @[RocketCore.scala:134:14] input [39:0] io_imem_gpa_bits, // @[RocketCore.scala:134:14] input io_imem_gpa_is_pte, // @[RocketCore.scala:134:14] output io_imem_btb_update_valid, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_prediction_cfiType, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_taken, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_prediction_mask, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_bridx, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_prediction_target, // @[RocketCore.scala:134:14] output [4:0] io_imem_btb_update_bits_prediction_entry, // @[RocketCore.scala:134:14] output [7:0] io_imem_btb_update_bits_prediction_bht_history, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_bht_value, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_pc, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_target, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_isValid, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_br_pc, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_cfiType, // @[RocketCore.scala:134:14] output io_imem_bht_update_valid, // @[RocketCore.scala:134:14] output [7:0] io_imem_bht_update_bits_prediction_history, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_prediction_value, // @[RocketCore.scala:134:14] output [38:0] io_imem_bht_update_bits_pc, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_branch, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_taken, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_mispredict, // @[RocketCore.scala:134:14] output io_imem_flush_icache, // @[RocketCore.scala:134:14] input [39:0] io_imem_npc, // @[RocketCore.scala:134:14] input io_imem_perf_acquire, // @[RocketCore.scala:134:14] input io_imem_perf_tlbMiss, // @[RocketCore.scala:134:14] output io_imem_progress, // @[RocketCore.scala:134:14] input io_dmem_req_ready, // @[RocketCore.scala:134:14] output io_dmem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_dmem_req_bits_addr, // @[RocketCore.scala:134:14] output [6:0] io_dmem_req_bits_tag, // @[RocketCore.scala:134:14] output [4:0] io_dmem_req_bits_cmd, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_size, // @[RocketCore.scala:134:14] output io_dmem_req_bits_signed, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_dprv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_dv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_no_resp, // @[RocketCore.scala:134:14] output io_dmem_s1_kill, // @[RocketCore.scala:134:14] output [63:0] io_dmem_s1_data_data, // @[RocketCore.scala:134:14] input io_dmem_s2_nack, // @[RocketCore.scala:134:14] input io_dmem_s2_nack_cause_raw, // @[RocketCore.scala:134:14] input io_dmem_s2_uncached, // @[RocketCore.scala:134:14] input [31:0] io_dmem_s2_paddr, // @[RocketCore.scala:134:14] input io_dmem_resp_valid, // @[RocketCore.scala:134:14] input [39:0] io_dmem_resp_bits_addr, // @[RocketCore.scala:134:14] input [6:0] io_dmem_resp_bits_tag, // @[RocketCore.scala:134:14] input [4:0] io_dmem_resp_bits_cmd, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_size, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_signed, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_dprv, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_dv, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data, // @[RocketCore.scala:134:14] input [7:0] io_dmem_resp_bits_mask, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_has_data, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_word_bypass, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_raw, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_store_data, // @[RocketCore.scala:134:14] input io_dmem_replay_next, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_st, // @[RocketCore.scala:134:14] input [39:0] io_dmem_s2_gpa, // @[RocketCore.scala:134:14] input io_dmem_ordered, // @[RocketCore.scala:134:14] input io_dmem_store_pending, // @[RocketCore.scala:134:14] input io_dmem_perf_acquire, // @[RocketCore.scala:134:14] input io_dmem_perf_release, // @[RocketCore.scala:134:14] input io_dmem_perf_grant, // @[RocketCore.scala:134:14] input io_dmem_perf_tlbMiss, // @[RocketCore.scala:134:14] input io_dmem_perf_blocked, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptStoreThenLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptStoreThenRMW, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptLoadThenLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_storeBufferEmptyAfterLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_storeBufferEmptyAfterStore, // @[RocketCore.scala:134:14] output io_dmem_keep_clock_enabled, // @[RocketCore.scala:134:14] output [3:0] io_ptw_ptbr_mode, // @[RocketCore.scala:134:14] output [43:0] io_ptw_ptbr_ppn, // @[RocketCore.scala:134:14] output io_ptw_sfence_valid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_ptw_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_asid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_hv, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_hg, // @[RocketCore.scala:134:14] output io_ptw_status_debug, // @[RocketCore.scala:134:14] output io_ptw_status_cease, // @[RocketCore.scala:134:14] output io_ptw_status_wfi, // @[RocketCore.scala:134:14] output [31:0] io_ptw_status_isa, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_dprv, // @[RocketCore.scala:134:14] output io_ptw_status_dv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_prv, // @[RocketCore.scala:134:14] output io_ptw_status_v, // @[RocketCore.scala:134:14] output io_ptw_status_sd, // @[RocketCore.scala:134:14] output io_ptw_status_mpv, // @[RocketCore.scala:134:14] output io_ptw_status_gva, // @[RocketCore.scala:134:14] output io_ptw_status_tsr, // @[RocketCore.scala:134:14] output io_ptw_status_tw, // @[RocketCore.scala:134:14] output io_ptw_status_tvm, // @[RocketCore.scala:134:14] output io_ptw_status_mxr, // @[RocketCore.scala:134:14] output io_ptw_status_sum, // @[RocketCore.scala:134:14] output io_ptw_status_mprv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_fs, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_mpp, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_vs, // @[RocketCore.scala:134:14] output io_ptw_status_spp, // @[RocketCore.scala:134:14] output io_ptw_status_mpie, // @[RocketCore.scala:134:14] output io_ptw_status_spie, // @[RocketCore.scala:134:14] output io_ptw_status_mie, // @[RocketCore.scala:134:14] output io_ptw_status_sie, // @[RocketCore.scala:134:14] output io_ptw_hstatus_spvp, // @[RocketCore.scala:134:14] output io_ptw_hstatus_spv, // @[RocketCore.scala:134:14] output io_ptw_hstatus_gva, // @[RocketCore.scala:134:14] output io_ptw_gstatus_debug, // @[RocketCore.scala:134:14] output io_ptw_gstatus_cease, // @[RocketCore.scala:134:14] output io_ptw_gstatus_wfi, // @[RocketCore.scala:134:14] output [31:0] io_ptw_gstatus_isa, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_dprv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_dv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_prv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_v, // @[RocketCore.scala:134:14] output [22:0] io_ptw_gstatus_zero2, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mpv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_gva, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mbe, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sbe, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_sxl, // @[RocketCore.scala:134:14] output [7:0] io_ptw_gstatus_zero1, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tsr, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tw, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tvm, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mxr, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sum, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mprv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_fs, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_mpp, // @[RocketCore.scala:134:14] output io_ptw_gstatus_spp, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mpie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_ube, // @[RocketCore.scala:134:14] output io_ptw_gstatus_spie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_upie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_hie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_uie, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_0_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_0_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_0_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_1_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_1_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_1_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_2_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_2_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_2_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_3_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_3_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_3_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_4_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_4_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_4_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_5_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_5_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_5_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_6_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_6_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_6_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_7_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_7_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_7_mask, // @[RocketCore.scala:134:14] input io_ptw_perf_pte_miss, // @[RocketCore.scala:134:14] input io_ptw_perf_pte_hit, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_0_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_0_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_1_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_1_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_1_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_2_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_2_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_2_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_3_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_3_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_3_value, // @[RocketCore.scala:134:14] input io_ptw_clock_enabled, // @[RocketCore.scala:134:14] output io_fpu_hartid, // @[RocketCore.scala:134:14] output [63:0] io_fpu_time, // @[RocketCore.scala:134:14] output [31:0] io_fpu_inst, // @[RocketCore.scala:134:14] output [63:0] io_fpu_fromint_data, // @[RocketCore.scala:134:14] output [2:0] io_fpu_fcsr_rm, // @[RocketCore.scala:134:14] input io_fpu_fcsr_flags_valid, // @[RocketCore.scala:134:14] input [4:0] io_fpu_fcsr_flags_bits, // @[RocketCore.scala:134:14] output [2:0] io_fpu_v_sew, // @[RocketCore.scala:134:14] input [63:0] io_fpu_store_data, // @[RocketCore.scala:134:14] input [63:0] io_fpu_toint_data, // @[RocketCore.scala:134:14] output io_fpu_ll_resp_val, // @[RocketCore.scala:134:14] output [2:0] io_fpu_ll_resp_type, // @[RocketCore.scala:134:14] output [4:0] io_fpu_ll_resp_tag, // @[RocketCore.scala:134:14] output [63:0] io_fpu_ll_resp_data, // @[RocketCore.scala:134:14] output io_fpu_valid, // @[RocketCore.scala:134:14] input io_fpu_fcsr_rdy, // @[RocketCore.scala:134:14] input io_fpu_nack_mem, // @[RocketCore.scala:134:14] input io_fpu_illegal_rm, // @[RocketCore.scala:134:14] output io_fpu_killx, // @[RocketCore.scala:134:14] output io_fpu_killm, // @[RocketCore.scala:134:14] input io_fpu_dec_ldst, // @[RocketCore.scala:134:14] input io_fpu_dec_wen, // @[RocketCore.scala:134:14] input io_fpu_dec_ren1, // @[RocketCore.scala:134:14] input io_fpu_dec_ren2, // @[RocketCore.scala:134:14] input io_fpu_dec_ren3, // @[RocketCore.scala:134:14] input io_fpu_dec_swap12, // @[RocketCore.scala:134:14] input io_fpu_dec_swap23, // @[RocketCore.scala:134:14] input [1:0] io_fpu_dec_typeTagIn, // @[RocketCore.scala:134:14] input [1:0] io_fpu_dec_typeTagOut, // @[RocketCore.scala:134:14] input io_fpu_dec_fromint, // @[RocketCore.scala:134:14] input io_fpu_dec_toint, // @[RocketCore.scala:134:14] input io_fpu_dec_fastpipe, // @[RocketCore.scala:134:14] input io_fpu_dec_fma, // @[RocketCore.scala:134:14] input io_fpu_dec_div, // @[RocketCore.scala:134:14] input io_fpu_dec_sqrt, // @[RocketCore.scala:134:14] input io_fpu_dec_wflags, // @[RocketCore.scala:134:14] input io_fpu_dec_vec, // @[RocketCore.scala:134:14] input io_fpu_sboard_set, // @[RocketCore.scala:134:14] input io_fpu_sboard_clr, // @[RocketCore.scala:134:14] input [4:0] io_fpu_sboard_clra, // @[RocketCore.scala:134:14] output io_fpu_keep_clock_enabled, // @[RocketCore.scala:134:14] output io_trace_insns_0_valid, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_iaddr, // @[RocketCore.scala:134:14] output [31:0] io_trace_insns_0_insn, // @[RocketCore.scala:134:14] output [2:0] io_trace_insns_0_priv, // @[RocketCore.scala:134:14] output io_trace_insns_0_exception, // @[RocketCore.scala:134:14] output io_trace_insns_0_interrupt, // @[RocketCore.scala:134:14] output [63:0] io_trace_insns_0_cause, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_tval, // @[RocketCore.scala:134:14] output [63:0] io_trace_time, // @[RocketCore.scala:134:14] output io_bpwatch_0_valid_0, // @[RocketCore.scala:134:14] output [2:0] io_bpwatch_0_action, // @[RocketCore.scala:134:14] output io_wfi, // @[RocketCore.scala:134:14] output io_vector_status_debug, // @[RocketCore.scala:134:14] output io_vector_status_cease, // @[RocketCore.scala:134:14] output io_vector_status_wfi, // @[RocketCore.scala:134:14] output [31:0] io_vector_status_isa, // @[RocketCore.scala:134:14] output [1:0] io_vector_status_dprv, // @[RocketCore.scala:134:14] output io_vector_status_dv, // @[RocketCore.scala:134:14] output [1:0] io_vector_status_prv, // @[RocketCore.scala:134:14] output io_vector_status_v, // @[RocketCore.scala:134:14] output io_vector_status_sd, // @[RocketCore.scala:134:14] output io_vector_status_mpv, // @[RocketCore.scala:134:14] output io_vector_status_gva, // @[RocketCore.scala:134:14] output io_vector_status_tsr, // @[RocketCore.scala:134:14] output io_vector_status_tw, // @[RocketCore.scala:134:14] output io_vector_status_tvm, // @[RocketCore.scala:134:14] output io_vector_status_mxr, // @[RocketCore.scala:134:14] output io_vector_status_sum, // @[RocketCore.scala:134:14] output io_vector_status_mprv, // @[RocketCore.scala:134:14] output [1:0] io_vector_status_fs, // @[RocketCore.scala:134:14] output [1:0] io_vector_status_mpp, // @[RocketCore.scala:134:14] output [1:0] io_vector_status_vs, // @[RocketCore.scala:134:14] output io_vector_status_spp, // @[RocketCore.scala:134:14] output io_vector_status_mpie, // @[RocketCore.scala:134:14] output io_vector_status_spie, // @[RocketCore.scala:134:14] output io_vector_status_mie, // @[RocketCore.scala:134:14] output io_vector_status_sie, // @[RocketCore.scala:134:14] output io_vector_ex_valid, // @[RocketCore.scala:134:14] output [31:0] io_vector_ex_inst, // @[RocketCore.scala:134:14] output [39:0] io_vector_ex_pc, // @[RocketCore.scala:134:14] output [12:0] io_vector_ex_vconfig_vl, // @[RocketCore.scala:134:14] output io_vector_ex_vconfig_vtype_vill, // @[RocketCore.scala:134:14] output [54:0] io_vector_ex_vconfig_vtype_reserved, // @[RocketCore.scala:134:14] output io_vector_ex_vconfig_vtype_vma, // @[RocketCore.scala:134:14] output io_vector_ex_vconfig_vtype_vta, // @[RocketCore.scala:134:14] output [2:0] io_vector_ex_vconfig_vtype_vsew, // @[RocketCore.scala:134:14] output io_vector_ex_vconfig_vtype_vlmul_sign, // @[RocketCore.scala:134:14] output [1:0] io_vector_ex_vconfig_vtype_vlmul_mag, // @[RocketCore.scala:134:14] output [11:0] io_vector_ex_vstart, // @[RocketCore.scala:134:14] output [63:0] io_vector_ex_rs1, // @[RocketCore.scala:134:14] output [63:0] io_vector_ex_rs2, // @[RocketCore.scala:134:14] output io_vector_killm, // @[RocketCore.scala:134:14] output [63:0] io_vector_mem_frs1, // @[RocketCore.scala:134:14] input io_vector_mem_block_mem, // @[RocketCore.scala:134:14] output io_vector_wb_store_pending, // @[RocketCore.scala:134:14] input io_vector_wb_replay, // @[RocketCore.scala:134:14] input io_vector_wb_retire, // @[RocketCore.scala:134:14] input [31:0] io_vector_wb_inst, // @[RocketCore.scala:134:14] input io_vector_wb_rob_should_wb, // @[RocketCore.scala:134:14] input io_vector_wb_rob_should_wb_fp, // @[RocketCore.scala:134:14] input [39:0] io_vector_wb_pc, // @[RocketCore.scala:134:14] output [1:0] io_vector_wb_vxrm, // @[RocketCore.scala:134:14] output [2:0] io_vector_wb_frm, // @[RocketCore.scala:134:14] output io_vector_resp_ready, // @[RocketCore.scala:134:14] input io_vector_resp_valid, // @[RocketCore.scala:134:14] input io_vector_resp_bits_fp, // @[RocketCore.scala:134:14] input [1:0] io_vector_resp_bits_size, // @[RocketCore.scala:134:14] input [4:0] io_vector_resp_bits_rd, // @[RocketCore.scala:134:14] input [63:0] io_vector_resp_bits_data, // @[RocketCore.scala:134:14] input io_vector_set_vstart_valid, // @[RocketCore.scala:134:14] input io_vector_set_fflags_valid, // @[RocketCore.scala:134:14] input [4:0] io_vector_set_fflags_bits, // @[RocketCore.scala:134:14] input io_vector_backend_busy // @[RocketCore.scala:134:14] ); wire ll_arb_io_out_ready; // @[RocketCore.scala:782:23, :809:44, :810:25] wire ex_new_vtype_vlmul_sign; // @[CSR.scala:328:27] wire [2:0] ex_new_vtype_vsew; // @[CSR.scala:328:27] wire ex_new_vtype_vta; // @[CSR.scala:328:27] wire ex_new_vtype_vma; // @[CSR.scala:328:27] wire ex_new_vtype_vill; // @[CSR.scala:328:27] wire id_ctrl_fence; // @[RocketCore.scala:321:21] wire id_ctrl_rocc; // @[RocketCore.scala:321:21] wire io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_valid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7] wire _ll_arb_io_in_0_ready; // @[RocketCore.scala:776:22] wire _ll_arb_io_in_2_ready; // @[RocketCore.scala:776:22] wire _ll_arb_io_out_valid; // @[RocketCore.scala:776:22] wire [4:0] _ll_arb_io_out_bits_tag; // @[RocketCore.scala:776:22] wire _div_io_req_ready; // @[RocketCore.scala:511:19] wire _div_io_resp_valid; // @[RocketCore.scala:511:19] wire [63:0] _div_io_resp_bits_data; // @[RocketCore.scala:511:19] wire [4:0] _div_io_resp_bits_tag; // @[RocketCore.scala:511:19] wire [63:0] _alu_io_out; // @[RocketCore.scala:504:19] wire [63:0] _alu_io_adder_out; // @[RocketCore.scala:504:19] wire _alu_io_cmp_out; // @[RocketCore.scala:504:19] wire _bpu_io_xcpt_if; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_ld; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_st; // @[RocketCore.scala:414:19] wire _bpu_io_debug_if; // @[RocketCore.scala:414:19] wire _bpu_io_debug_ld; // @[RocketCore.scala:414:19] wire _bpu_io_debug_st; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_rvalid_0; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_wvalid_0; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_ivalid_0; // @[RocketCore.scala:414:19] wire _v_decode_io_legal; // @[Configs.scala:26:35] wire _v_decode_io_fp; // @[Configs.scala:26:35] wire _v_decode_io_read_rs1; // @[Configs.scala:26:35] wire _v_decode_io_read_rs2; // @[Configs.scala:26:35] wire _v_decode_io_read_frs1; // @[Configs.scala:26:35] wire _v_decode_io_write_rd; // @[Configs.scala:26:35] wire _v_decode_io_write_frd; // @[Configs.scala:26:35] wire [63:0] _csr_io_rw_rdata; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_vector_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_csr; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_vector_csr; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_read_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_csr_stall; // @[RocketCore.scala:341:19] wire _csr_io_eret; // @[RocketCore.scala:341:19] wire _csr_io_singleStep; // @[RocketCore.scala:341:19] wire _csr_io_status_debug; // @[RocketCore.scala:341:19] wire _csr_io_status_cease; // @[RocketCore.scala:341:19] wire _csr_io_status_wfi; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_status_isa; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_dprv; // @[RocketCore.scala:341:19] wire _csr_io_status_dv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_prv; // @[RocketCore.scala:341:19] wire _csr_io_status_v; // @[RocketCore.scala:341:19] wire _csr_io_status_sd; // @[RocketCore.scala:341:19] wire _csr_io_status_mpv; // @[RocketCore.scala:341:19] wire _csr_io_status_gva; // @[RocketCore.scala:341:19] wire _csr_io_status_tsr; // @[RocketCore.scala:341:19] wire _csr_io_status_tw; // @[RocketCore.scala:341:19] wire _csr_io_status_tvm; // @[RocketCore.scala:341:19] wire _csr_io_status_mxr; // @[RocketCore.scala:341:19] wire _csr_io_status_sum; // @[RocketCore.scala:341:19] wire _csr_io_status_mprv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_fs; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_mpp; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_vs; // @[RocketCore.scala:341:19] wire _csr_io_status_spp; // @[RocketCore.scala:341:19] wire _csr_io_status_mpie; // @[RocketCore.scala:341:19] wire _csr_io_status_spie; // @[RocketCore.scala:341:19] wire _csr_io_status_mie; // @[RocketCore.scala:341:19] wire _csr_io_status_sie; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_evec; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_time; // @[RocketCore.scala:341:19] wire [2:0] _csr_io_fcsr_rm; // @[RocketCore.scala:341:19] wire _csr_io_interrupt; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_interrupt_cause; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_dmode; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_action; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_bp_0_control_tmatch; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_m; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_s; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_u; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_x; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_w; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_r; // @[RocketCore.scala:341:19] wire [38:0] _csr_io_bp_0_address; // @[RocketCore.scala:341:19] wire [47:0] _csr_io_bp_0_textra_pad2; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_textra_pad1; // @[RocketCore.scala:341:19] wire _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_valid; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_trace_0_iaddr; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_trace_0_insn; // @[RocketCore.scala:341:19] wire [2:0] _csr_io_trace_0_priv; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_exception; // @[RocketCore.scala:341:19] wire [12:0] _csr_io_vector_vconfig_vl; // @[RocketCore.scala:341:19] wire _csr_io_vector_vconfig_vtype_vill; // @[RocketCore.scala:341:19] wire [54:0] _csr_io_vector_vconfig_vtype_reserved; // @[RocketCore.scala:341:19] wire _csr_io_vector_vconfig_vtype_vma; // @[RocketCore.scala:341:19] wire _csr_io_vector_vconfig_vtype_vta; // @[RocketCore.scala:341:19] wire [2:0] _csr_io_vector_vconfig_vtype_vsew; // @[RocketCore.scala:341:19] wire _csr_io_vector_vconfig_vtype_vlmul_sign; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_vector_vconfig_vtype_vlmul_mag; // @[RocketCore.scala:341:19] wire [11:0] _csr_io_vector_vstart; // @[RocketCore.scala:341:19] wire [39:0] _ibuf_io_pc; // @[RocketCore.scala:311:20] wire [1:0] _ibuf_io_btb_resp_cfiType; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_taken; // @[RocketCore.scala:311:20] wire [1:0] _ibuf_io_btb_resp_mask; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_bridx; // @[RocketCore.scala:311:20] wire [38:0] _ibuf_io_btb_resp_target; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_btb_resp_entry; // @[RocketCore.scala:311:20] wire [7:0] _ibuf_io_btb_resp_bht_history; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_bht_value; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20] wire io_hartid_0 = io_hartid; // @[RocketCore.scala:153:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[RocketCore.scala:153:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[RocketCore.scala:153:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[RocketCore.scala:153:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[RocketCore.scala:153:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[RocketCore.scala:153:7] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_btb_cfiType_0 = io_imem_resp_bits_btb_cfiType; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_taken_0 = io_imem_resp_bits_btb_taken; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_btb_mask_0 = io_imem_resp_bits_btb_mask; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_bridx_0 = io_imem_resp_bits_btb_bridx; // @[RocketCore.scala:153:7] wire [38:0] io_imem_resp_bits_btb_target_0 = io_imem_resp_bits_btb_target; // @[RocketCore.scala:153:7] wire [4:0] io_imem_resp_bits_btb_entry_0 = io_imem_resp_bits_btb_entry; // @[RocketCore.scala:153:7] wire [7:0] io_imem_resp_bits_btb_bht_history_0 = io_imem_resp_bits_btb_bht_history; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_bht_value_0 = io_imem_resp_bits_btb_bht_value; // @[RocketCore.scala:153:7] wire [39:0] io_imem_resp_bits_pc_0 = io_imem_resp_bits_pc; // @[RocketCore.scala:153:7] wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_mask_0 = io_imem_resp_bits_mask; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_pf_inst_0 = io_imem_resp_bits_xcpt_pf_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_gf_inst_0 = io_imem_resp_bits_xcpt_gf_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_ae_inst_0 = io_imem_resp_bits_xcpt_ae_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_replay_0 = io_imem_resp_bits_replay; // @[RocketCore.scala:153:7] wire io_imem_gpa_valid_0 = io_imem_gpa_valid; // @[RocketCore.scala:153:7] wire [39:0] io_imem_gpa_bits_0 = io_imem_gpa_bits; // @[RocketCore.scala:153:7] wire io_imem_gpa_is_pte_0 = io_imem_gpa_is_pte; // @[RocketCore.scala:153:7] wire [39:0] io_imem_npc_0 = io_imem_npc; // @[RocketCore.scala:153:7] wire io_imem_perf_acquire_0 = io_imem_perf_acquire; // @[RocketCore.scala:153:7] wire io_imem_perf_tlbMiss_0 = io_imem_perf_tlbMiss; // @[RocketCore.scala:153:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[RocketCore.scala:153:7] wire io_dmem_s2_nack_0 = io_dmem_s2_nack; // @[RocketCore.scala:153:7] wire io_dmem_s2_nack_cause_raw_0 = io_dmem_s2_nack_cause_raw; // @[RocketCore.scala:153:7] wire io_dmem_s2_uncached_0 = io_dmem_s2_uncached; // @[RocketCore.scala:153:7] wire [31:0] io_dmem_s2_paddr_0 = io_dmem_s2_paddr; // @[RocketCore.scala:153:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_resp_bits_addr_0 = io_dmem_resp_bits_addr; // @[RocketCore.scala:153:7] wire [6:0] io_dmem_resp_bits_tag_0 = io_dmem_resp_bits_tag; // @[RocketCore.scala:153:7] wire [4:0] io_dmem_resp_bits_cmd_0 = io_dmem_resp_bits_cmd; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_resp_bits_size_0 = io_dmem_resp_bits_size; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_signed_0 = io_dmem_resp_bits_signed; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_resp_bits_dprv_0 = io_dmem_resp_bits_dprv; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_dv_0 = io_dmem_resp_bits_dv; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_resp_bits_mask_0 = io_dmem_resp_bits_mask; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_replay_0 = io_dmem_resp_bits_replay; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_has_data_0 = io_dmem_resp_bits_has_data; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_word_bypass_0 = io_dmem_resp_bits_data_word_bypass; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_raw_0 = io_dmem_resp_bits_data_raw; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_store_data_0 = io_dmem_resp_bits_store_data; // @[RocketCore.scala:153:7] wire io_dmem_replay_next_0 = io_dmem_replay_next; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ma_ld_0 = io_dmem_s2_xcpt_ma_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ma_st_0 = io_dmem_s2_xcpt_ma_st; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_pf_ld_0 = io_dmem_s2_xcpt_pf_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_pf_st_0 = io_dmem_s2_xcpt_pf_st; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ae_ld_0 = io_dmem_s2_xcpt_ae_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ae_st_0 = io_dmem_s2_xcpt_ae_st; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_s2_gpa_0 = io_dmem_s2_gpa; // @[RocketCore.scala:153:7] wire io_dmem_ordered_0 = io_dmem_ordered; // @[RocketCore.scala:153:7] wire io_dmem_store_pending_0 = io_dmem_store_pending; // @[RocketCore.scala:153:7] wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[RocketCore.scala:153:7] wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[RocketCore.scala:153:7] wire io_dmem_perf_grant_0 = io_dmem_perf_grant; // @[RocketCore.scala:153:7] wire io_dmem_perf_tlbMiss_0 = io_dmem_perf_tlbMiss; // @[RocketCore.scala:153:7] wire io_dmem_perf_blocked_0 = io_dmem_perf_blocked; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptStoreThenLoad_0 = io_dmem_perf_canAcceptStoreThenLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptStoreThenRMW_0 = io_dmem_perf_canAcceptStoreThenRMW; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptLoadThenLoad_0 = io_dmem_perf_canAcceptLoadThenLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_storeBufferEmptyAfterLoad_0 = io_dmem_perf_storeBufferEmptyAfterLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_storeBufferEmptyAfterStore_0 = io_dmem_perf_storeBufferEmptyAfterStore; // @[RocketCore.scala:153:7] wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[RocketCore.scala:153:7] wire io_ptw_perf_pte_hit_0 = io_ptw_perf_pte_hit; // @[RocketCore.scala:153:7] wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[RocketCore.scala:153:7] wire io_fpu_fcsr_flags_valid_0 = io_fpu_fcsr_flags_valid; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_fcsr_flags_bits_0 = io_fpu_fcsr_flags_bits; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_store_data_0 = io_fpu_store_data; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_toint_data_0 = io_fpu_toint_data; // @[RocketCore.scala:153:7] wire io_fpu_fcsr_rdy_0 = io_fpu_fcsr_rdy; // @[RocketCore.scala:153:7] wire io_fpu_nack_mem_0 = io_fpu_nack_mem; // @[RocketCore.scala:153:7] wire io_fpu_illegal_rm_0 = io_fpu_illegal_rm; // @[RocketCore.scala:153:7] wire io_fpu_dec_ldst_0 = io_fpu_dec_ldst; // @[RocketCore.scala:153:7] wire io_fpu_dec_wen_0 = io_fpu_dec_wen; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren1_0 = io_fpu_dec_ren1; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren2_0 = io_fpu_dec_ren2; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren3_0 = io_fpu_dec_ren3; // @[RocketCore.scala:153:7] wire io_fpu_dec_swap12_0 = io_fpu_dec_swap12; // @[RocketCore.scala:153:7] wire io_fpu_dec_swap23_0 = io_fpu_dec_swap23; // @[RocketCore.scala:153:7] wire [1:0] io_fpu_dec_typeTagIn_0 = io_fpu_dec_typeTagIn; // @[RocketCore.scala:153:7] wire [1:0] io_fpu_dec_typeTagOut_0 = io_fpu_dec_typeTagOut; // @[RocketCore.scala:153:7] wire io_fpu_dec_fromint_0 = io_fpu_dec_fromint; // @[RocketCore.scala:153:7] wire io_fpu_dec_toint_0 = io_fpu_dec_toint; // @[RocketCore.scala:153:7] wire io_fpu_dec_fastpipe_0 = io_fpu_dec_fastpipe; // @[RocketCore.scala:153:7] wire io_fpu_dec_fma_0 = io_fpu_dec_fma; // @[RocketCore.scala:153:7] wire io_fpu_dec_div_0 = io_fpu_dec_div; // @[RocketCore.scala:153:7] wire io_fpu_dec_sqrt_0 = io_fpu_dec_sqrt; // @[RocketCore.scala:153:7] wire io_fpu_dec_wflags_0 = io_fpu_dec_wflags; // @[RocketCore.scala:153:7] wire io_fpu_dec_vec_0 = io_fpu_dec_vec; // @[RocketCore.scala:153:7] wire io_fpu_sboard_set_0 = io_fpu_sboard_set; // @[RocketCore.scala:153:7] wire io_fpu_sboard_clr_0 = io_fpu_sboard_clr; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_sboard_clra_0 = io_fpu_sboard_clra; // @[RocketCore.scala:153:7] wire io_vector_mem_block_mem_0 = io_vector_mem_block_mem; // @[RocketCore.scala:153:7] wire io_vector_wb_replay_0 = io_vector_wb_replay; // @[RocketCore.scala:153:7] wire io_vector_wb_retire_0 = io_vector_wb_retire; // @[RocketCore.scala:153:7] wire [31:0] io_vector_wb_inst_0 = io_vector_wb_inst; // @[RocketCore.scala:153:7] wire io_vector_wb_rob_should_wb_0 = io_vector_wb_rob_should_wb; // @[RocketCore.scala:153:7] wire io_vector_wb_rob_should_wb_fp_0 = io_vector_wb_rob_should_wb_fp; // @[RocketCore.scala:153:7] wire [39:0] io_vector_wb_pc_0 = io_vector_wb_pc; // @[RocketCore.scala:153:7] wire io_vector_resp_valid_0 = io_vector_resp_valid; // @[RocketCore.scala:153:7] wire io_vector_resp_bits_fp_0 = io_vector_resp_bits_fp; // @[RocketCore.scala:153:7] wire [1:0] io_vector_resp_bits_size_0 = io_vector_resp_bits_size; // @[RocketCore.scala:153:7] wire [4:0] io_vector_resp_bits_rd_0 = io_vector_resp_bits_rd; // @[RocketCore.scala:153:7] wire [63:0] io_vector_resp_bits_data_0 = io_vector_resp_bits_data; // @[RocketCore.scala:153:7] wire io_vector_set_vstart_valid_0 = io_vector_set_vstart_valid; // @[RocketCore.scala:153:7] wire io_vector_set_fflags_valid_0 = io_vector_set_fflags_valid; // @[RocketCore.scala:153:7] wire [4:0] io_vector_set_fflags_bits_0 = io_vector_set_fflags_bits; // @[RocketCore.scala:153:7] wire io_vector_backend_busy_0 = io_vector_backend_busy; // @[RocketCore.scala:153:7] wire coreMonitorBundle_clock = clock; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_reset = reset; // @[RocketCore.scala:1186:31] wire xrfWriteBundle_clock = clock; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_reset = reset; // @[RocketCore.scala:1249:28] wire io_imem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7] wire io_dmem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sd = 1'h1; // @[RocketCore.scala:153:7] wire io_vector_ex_ready = 1'h1; // @[RocketCore.scala:153:7] wire clock_en = 1'h1; // @[RocketCore.scala:153:7, :163:29] wire _id_npc_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _id_npc_b11_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1345:23] wire _mem_br_target_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _mem_br_target_b19_12_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1343:43] wire _mem_br_target_b19_12_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1343:36] wire _mem_br_target_b11_T_6 = 1'h1; // @[RocketCore.scala:153:7, :1346:23] wire _mem_br_target_b4_1_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1349:41] wire _mem_br_target_b4_1_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1349:34] wire _mem_br_target_b19_12_T_5 = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _mem_br_target_b11_T_14 = 1'h1; // @[RocketCore.scala:153:7, :1345:23] wire _wb_reg_xcpt_T_2 = 1'h1; // @[RocketCore.scala:153:7, :707:45] wire _replay_wb_rocc_T_1 = 1'h1; // @[RocketCore.scala:153:7, :758:56] wire _rocc_blocked_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1029:31] wire io_imem_btb_update_bits_taken = 1'h0; // @[RocketCore.scala:153:7] wire io_imem_ras_update_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtw = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_hu = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_perf_l2miss = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_perf_l2hit = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_resp_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_resp_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_signed = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_dv = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_resp = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s1_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_nack = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_nack_cause_raw = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_uncached = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_signed = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_dv = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_replay = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_has_data = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_replay_next = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ma_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_pf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ae_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_ordered = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_store_pending = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_acquire = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_release = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_grant = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_tlbMiss = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_blocked = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_keep_clock_enabled = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_clock_enabled = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_busy = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_interrupt = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_exception = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_rvalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_wvalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_ivalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_cease = 1'h0; // @[RocketCore.scala:153:7] wire io_traceStall = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_mem_block_all = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_wb_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_set_vxsat = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_set_vconfig_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_set_vconfig_bits_vtype_vill = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_set_vconfig_bits_vtype_vma = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_set_vconfig_bits_vtype_vta = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_set_vconfig_bits_vtype_vlmul_sign = 1'h0; // @[RocketCore.scala:153:7] wire io_vector_trap_check_busy = 1'h0; // @[RocketCore.scala:153:7] wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_5 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_6 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_7 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_8 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_9 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_10 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_11 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_12 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_13 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_14 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_15 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_16 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_17 = 1'h0; // @[Events.scala:13:33] wire hits_0 = 1'h0; // @[Events.scala:13:25] wire hits_1 = 1'h0; // @[Events.scala:13:25] wire hits_2 = 1'h0; // @[Events.scala:13:25] wire hits_3 = 1'h0; // @[Events.scala:13:25] wire hits_4 = 1'h0; // @[Events.scala:13:25] wire hits_5 = 1'h0; // @[Events.scala:13:25] wire hits_6 = 1'h0; // @[Events.scala:13:25] wire hits_7 = 1'h0; // @[Events.scala:13:25] wire hits_8 = 1'h0; // @[Events.scala:13:25] wire hits_9 = 1'h0; // @[Events.scala:13:25] wire hits_10 = 1'h0; // @[Events.scala:13:25] wire hits_11 = 1'h0; // @[Events.scala:13:25] wire hits_12 = 1'h0; // @[Events.scala:13:25] wire hits_13 = 1'h0; // @[Events.scala:13:25] wire hits_14 = 1'h0; // @[Events.scala:13:25] wire hits_15 = 1'h0; // @[Events.scala:13:25] wire hits_16 = 1'h0; // @[Events.scala:13:25] wire hits_17 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_1_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_5 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_6 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_7 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_8 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_9 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_10 = 1'h0; // @[Events.scala:13:33] wire hits_1_0 = 1'h0; // @[Events.scala:13:25] wire hits_1_1 = 1'h0; // @[Events.scala:13:25] wire hits_1_2 = 1'h0; // @[Events.scala:13:25] wire hits_1_3 = 1'h0; // @[Events.scala:13:25] wire hits_1_4 = 1'h0; // @[Events.scala:13:25] wire hits_1_5 = 1'h0; // @[Events.scala:13:25] wire hits_1_6 = 1'h0; // @[Events.scala:13:25] wire hits_1_7 = 1'h0; // @[Events.scala:13:25] wire hits_1_8 = 1'h0; // @[Events.scala:13:25] wire hits_1_9 = 1'h0; // @[Events.scala:13:25] wire hits_1_10 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_2_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_5 = 1'h0; // @[Events.scala:13:33] wire hits_2_0 = 1'h0; // @[Events.scala:13:25] wire hits_2_1 = 1'h0; // @[Events.scala:13:25] wire hits_2_2 = 1'h0; // @[Events.scala:13:25] wire hits_2_3 = 1'h0; // @[Events.scala:13:25] wire hits_2_4 = 1'h0; // @[Events.scala:13:25] wire hits_2_5 = 1'h0; // @[Events.scala:13:25] wire _id_rs_T_1 = 1'h0; // @[RocketCore.scala:1326:33] wire _id_rs_T_6 = 1'h0; // @[RocketCore.scala:1326:33] wire _id_npc_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _id_npc_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _id_npc_b19_12_T_1 = 1'h0; // @[RocketCore.scala:1343:43] wire _id_npc_b19_12_T_2 = 1'h0; // @[RocketCore.scala:1343:36] wire _id_npc_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _id_npc_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _id_npc_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _id_npc_b11_T_6 = 1'h0; // @[RocketCore.scala:1346:23] wire _id_npc_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _id_npc_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _id_npc_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _id_npc_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _id_npc_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _id_npc_b4_1_T_2 = 1'h0; // @[RocketCore.scala:1349:41] wire _id_npc_b4_1_T_3 = 1'h0; // @[RocketCore.scala:1349:34] wire _id_npc_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _id_npc_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _id_npc_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _id_npc_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _id_npc_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _id_npc_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire id_npc_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _id_illegal_insn_T_26 = 1'h0; // @[RocketCore.scala:388:23] wire _id_illegal_insn_T_28 = 1'h0; // @[RocketCore.scala:389:23] wire _id_illegal_insn_T_30 = 1'h0; // @[RocketCore.scala:390:22] wire id_rocc_busy = 1'h0; // @[RocketCore.scala:405:34] wire _id_csr_rocc_write_T = 1'h0; // @[RocketCore.scala:408:87] wire id_csr_rocc_write = 1'h0; // @[RocketCore.scala:408:100] wire _id_do_fence_T_1 = 1'h0; // @[RocketCore.scala:410:46] wire _ex_reg_hls_T = 1'h0; // @[RocketCore.scala:553:37] wire _ex_reg_hls_T_6 = 1'h0; // @[RocketCore.scala:553:55] wire _ex_reg_mem_size_T = 1'h0; // @[RocketCore.scala:554:46] wire _replay_ex_structural_T_5 = 1'h0; // @[RocketCore.scala:599:45] wire _replay_ex_structural_T_6 = 1'h0; // @[RocketCore.scala:599:42] wire _mem_br_target_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_br_target_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_br_target_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_br_target_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_br_target_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_br_target_b11_T_3 = 1'h0; // @[RocketCore.scala:1345:23] wire _mem_br_target_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_br_target_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_br_target_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_br_target_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_br_target_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_br_target_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_br_target_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_br_target_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_br_target_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_br_target_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_br_target_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_br_target_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _mem_br_target_sign_T_3 = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_br_target_b30_20_T_3 = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_br_target_b19_12_T_6 = 1'h0; // @[RocketCore.scala:1343:43] wire _mem_br_target_b19_12_T_7 = 1'h0; // @[RocketCore.scala:1343:36] wire _mem_br_target_b11_T_11 = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_br_target_b11_T_12 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_br_target_b11_T_13 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_br_target_b11_T_17 = 1'h0; // @[RocketCore.scala:1346:23] wire _mem_br_target_b10_5_T_4 = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_br_target_b10_5_T_5 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_br_target_b10_5_T_6 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_br_target_b4_1_T_10 = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_br_target_b4_1_T_11 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_br_target_b4_1_T_12 = 1'h0; // @[RocketCore.scala:1349:41] wire _mem_br_target_b4_1_T_13 = 1'h0; // @[RocketCore.scala:1349:34] wire _mem_br_target_b4_1_T_15 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_br_target_b0_T_8 = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_br_target_b0_T_10 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_br_target_b0_T_12 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_br_target_b0_T_14 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_br_target_b0_T_15 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_br_target_b0_1 = 1'h0; // @[RocketCore.scala:1351:17] wire vec_kill_all = 1'h0; // @[RocketCore.scala:698:36] wire replay_wb_csr = 1'h0; // @[RocketCore.scala:759:42] wire _htval_valid_dmem_T_2 = 1'h0; // @[RocketCore.scala:857:83] wire _htval_valid_dmem_T_3 = 1'h0; // @[RocketCore.scala:857:54] wire htval_valid_dmem = 1'h0; // @[RocketCore.scala:857:87] wire _mhtinst_read_pseudo_T_1 = 1'h0; // @[RocketCore.scala:862:98] wire _ctrl_stalld_T_28 = 1'h0; // @[RocketCore.scala:1041:5] wire _io_rocc_exception_T = 1'h0; // @[RocketCore.scala:1157:52] wire _io_rocc_exception_T_1 = 1'h0; // @[RocketCore.scala:1157:32] wire _io_cease_T = 1'h0; // @[RocketCore.scala:1166:38] wire _io_cease_T_1 = 1'h0; // @[RocketCore.scala:1166:35] wire coreMonitorBundle_wrenf = 1'h0; // @[RocketCore.scala:1186:31] wire xrfWriteBundle_excpt = 1'h0; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_valid = 1'h0; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_wrenf = 1'h0; // @[RocketCore.scala:1249:28] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[RocketCore.scala:153:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[RocketCore.scala:153:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[RocketCore.scala:153:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [22:0] io_vector_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_vector_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_ras_update_bits_cfiType = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_req_bits_size = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_resp_bits_size = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_set_vconfig_bits_vtype_vlmul_mag = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] _htval_valid_dmem_T_1 = 2'h0; // @[RocketCore.scala:857:76] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[RocketCore.scala:153:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[RocketCore.scala:153:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[RocketCore.scala:153:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_resp_bits_rd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_vector_wb_cause = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] xrfWriteBundle_rd0src = 5'h0; // @[RocketCore.scala:1249:28] wire [4:0] xrfWriteBundle_rd1src = 5'h0; // @[RocketCore.scala:1249:28] wire [1:0] io_ptw_gstatus_vs = 2'h3; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_req_bits_addr = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_s2_gpa = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_vector_wb_tval = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] htval_dmem = 40'h0; // @[RocketCore.scala:858:25] wire [31:0] io_reset_vector = 32'h0; // @[RocketCore.scala:153:7] wire [31:0] io_rocc_mem_s2_paddr = 32'h0; // @[RocketCore.scala:153:7] wire [31:0] xrfWriteBundle_inst = 32'h0; // @[RocketCore.scala:1249:28] wire [38:0] io_imem_ras_update_bits_returnAddr = 39'h0; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_s1_data_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] xrfWriteBundle_pc = 64'h0; // @[RocketCore.scala:1249:28] wire [63:0] xrfWriteBundle_rd0val = 64'h0; // @[RocketCore.scala:1249:28] wire [63:0] xrfWriteBundle_rd1val = 64'h0; // @[RocketCore.scala:1249:28] wire [1:0] io_ptw_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_mem_req_bits_tag = 7'h0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0; // @[RocketCore.scala:153:7] wire [11:0] io_vector_set_vstart_bits = 12'h0; // @[RocketCore.scala:153:7] wire [12:0] io_vector_set_vconfig_bits_vl = 13'h0; // @[RocketCore.scala:153:7] wire [12:0] _ex_avl_T_8 = 13'h0; // @[package.scala:174:46] wire [12:0] _ex_new_vl_T_6 = 13'h0; // @[package.scala:174:46] wire [54:0] io_vector_set_vconfig_bits_vtype_reserved = 55'h0; // @[RocketCore.scala:153:7] wire [54:0] ex_new_vtype_reserved = 55'h0; // @[CSR.scala:328:27] wire [54:0] ex_new_vconfig_vtype_reserved = 55'h0; // @[RocketCore.scala:498:30] wire [2:0] io_vector_set_vconfig_bits_vtype_vsew = 3'h0; // @[RocketCore.scala:153:7] wire [12:0] _ex_avl_T_10 = 13'h1FF8; // @[package.scala:174:37] wire [12:0] _ex_new_vl_T_8 = 13'h1FF8; // @[package.scala:174:37] wire [12:0] _ex_avl_T_9 = 13'h7; // @[package.scala:174:41] wire [12:0] _ex_new_vl_T_7 = 13'h7; // @[package.scala:174:41] wire [13:0] _ex_new_vl_atLeastVLMax_T_10 = 14'h3FF8; // @[package.scala:174:37] wire [13:0] _ex_new_vl_atLeastVLMax_T_9 = 14'h7; // @[package.scala:174:41] wire [13:0] _ex_new_vl_atLeastVLMax_T_1 = 14'h3000; // @[CSR.scala:371:56] wire [13:0] _ex_new_vl_atLeastVLMax_T_2 = 14'h3000; // @[CSR.scala:371:56] wire [13:0] _ex_new_vl_atLeastVLMax_T_8 = 14'h0; // @[package.scala:174:46] wire [14:0] _ex_new_vl_atLeastVLMax_T = 15'h7000; // @[CSR.scala:371:56] wire io_fpu_hartid_0 = io_hartid_0; // @[RocketCore.scala:153:7] wire take_pc_mem_wb; // @[RocketCore.scala:307:35] wire [39:0] _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:1051:8] wire _io_imem_req_bits_speculative_T; // @[RocketCore.scala:1049:35] wire _io_imem_sfence_valid_T; // @[RocketCore.scala:1060:40] wire io_ptw_sfence_valid_0 = io_imem_sfence_valid_0; // @[RocketCore.scala:153:7] wire _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:1061:45] wire io_ptw_sfence_bits_rs1_0 = io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7] wire _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:1062:45] wire io_ptw_sfence_bits_rs2_0 = io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7] wire [38:0] io_ptw_sfence_bits_addr_0 = io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_asid_0 = io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_hv_0 = io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_hg_0 = io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7] wire _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:1071:77] wire [38:0] _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:1080:33] wire [38:0] io_imem_bht_update_bits_pc_0 = io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7] wire mem_cfi; // @[RocketCore.scala:625:50] wire [1:0] _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:1074:8] wire _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:1084:45] wire mem_wrong_npc; // @[RocketCore.scala:621:8] wire _io_imem_flush_icache_T_2; // @[RocketCore.scala:1054:59] wire _io_dmem_req_valid_T; // @[RocketCore.scala:1130:41] wire [39:0] _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:1295:8] wire _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:1136:30] wire [1:0] _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:1140:31] wire _io_dmem_req_bits_dv_T; // @[RocketCore.scala:1141:37] wire _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:1142:56] wire _io_dmem_s1_kill_T_2; // @[RocketCore.scala:1151:68] wire [63:0] _rf_wdata_T_1 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7, :819:78] wire [63:0] dcache_bypass_data = io_dmem_resp_bits_data_word_bypass_0; // @[RocketCore.scala:153:7, :449:62] wire io_vector_wb_store_pending_0 = io_dmem_store_pending_0; // @[RocketCore.scala:153:7] wire _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:1154:70] wire [63:0] ex_rs_0; // @[RocketCore.scala:469:14] wire [63:0] io_vector_mem_frs1_0 = io_fpu_store_data_0; // @[RocketCore.scala:153:7] wire _io_fpu_valid_T_1; // @[RocketCore.scala:1094:31] wire ctrl_killx; // @[RocketCore.scala:602:48] wire killm_common; // @[RocketCore.scala:700:68] wire _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59] wire _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:1156:53] wire [6:0] _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:1159:48] wire [6:0] _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:1159:48] wire _io_vector_ex_valid_T_4; // @[RocketCore.scala:1117:113] wire [11:0] _io_vector_ex_vstart_T_3; // @[RocketCore.scala:1120:23] wire [63:0] ex_rs_1; // @[RocketCore.scala:469:14] wire _io_vector_resp_ready_T_2; // @[RocketCore.scala:801:24] wire id_vec_busy = io_vector_backend_busy_0; // @[RocketCore.scala:153:7, :409:55] wire [39:0] io_imem_req_bits_pc_0; // @[RocketCore.scala:153:7] wire io_imem_req_bits_speculative_0; // @[RocketCore.scala:153:7] wire io_imem_req_valid_0; // @[RocketCore.scala:153:7] wire io_imem_resp_ready_0; // @[RocketCore.scala:153:7] wire [7:0] io_imem_btb_update_bits_prediction_bht_history_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_bht_value_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_prediction_cfiType_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_taken_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_prediction_mask_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_bridx_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_prediction_target_0; // @[RocketCore.scala:153:7] wire [4:0] io_imem_btb_update_bits_prediction_entry_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_target_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_isValid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_cfiType_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_valid_0; // @[RocketCore.scala:153:7] wire [7:0] io_imem_bht_update_bits_prediction_history_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_prediction_value_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_branch_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_taken_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_mispredict_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_valid_0; // @[RocketCore.scala:153:7] wire io_imem_might_request_0; // @[RocketCore.scala:153:7] wire io_imem_flush_icache_0; // @[RocketCore.scala:153:7] wire io_imem_progress_0; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_req_bits_addr_0; // @[RocketCore.scala:153:7] wire [6:0] io_dmem_req_bits_tag_0; // @[RocketCore.scala:153:7] wire [4:0] io_dmem_req_bits_cmd_0; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_req_bits_size_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_signed_0; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_req_bits_dprv_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_dv_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_resp_0; // @[RocketCore.scala:153:7] wire io_dmem_req_valid_0; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_s1_data_data_0; // @[RocketCore.scala:153:7] wire io_dmem_s1_kill_0; // @[RocketCore.scala:153:7] wire io_dmem_keep_clock_enabled_0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_ptbr_mode_0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_ptbr_ppn_0; // @[RocketCore.scala:153:7] wire io_ptw_status_debug_0; // @[RocketCore.scala:153:7] wire io_ptw_status_cease_0; // @[RocketCore.scala:153:7] wire io_ptw_status_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_status_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_dprv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_prv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_v_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sd_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mpv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tsr_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tw_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tvm_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mxr_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sum_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_mpp_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_vs_0; // @[RocketCore.scala:153:7] wire io_ptw_status_spp_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mpie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_spie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sie_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_spvp_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_spv_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_debug_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_cease_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_gstatus_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_dprv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_prv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_v_0; // @[RocketCore.scala:153:7] wire [22:0] io_ptw_gstatus_zero2_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mpv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mbe_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sbe_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_sxl_0; // @[RocketCore.scala:153:7] wire [7:0] io_ptw_gstatus_zero1_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tsr_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tw_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tvm_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mxr_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sum_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_mpp_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_spp_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mpie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_ube_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_spie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_upie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_hie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_uie_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_0_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_0_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_0_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_1_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_1_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_1_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_2_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_2_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_2_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_3_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_3_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_3_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_4_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_4_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_4_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_5_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_5_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_5_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_6_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_6_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_6_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_7_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_7_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_7_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_time_0; // @[RocketCore.scala:153:7] wire [31:0] io_fpu_inst_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_fromint_data_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_fcsr_rm_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_v_sew_0; // @[RocketCore.scala:153:7] wire io_fpu_ll_resp_val_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_ll_resp_type_0; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_ll_resp_data_0; // @[RocketCore.scala:153:7] wire io_fpu_valid_0; // @[RocketCore.scala:153:7] wire io_fpu_killx_0; // @[RocketCore.scala:153:7] wire io_fpu_killm_0; // @[RocketCore.scala:153:7] wire io_fpu_keep_clock_enabled_0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_cmd_bits_inst_funct; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rs2; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rs1; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xd; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xs1; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xs2; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rd; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_cmd_bits_inst_opcode; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_debug; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_cease; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_wfi; // @[RocketCore.scala:153:7] wire [31:0] io_rocc_cmd_bits_status_isa; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_dprv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_dv; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_prv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_v; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sd; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mpv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_gva; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tsr; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tw; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tvm; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mxr; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sum; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mprv; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_fs; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_mpp; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_vs; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_spp; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mpie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_spie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sie; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_cmd_bits_rs1; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_cmd_bits_rs2; // @[RocketCore.scala:153:7] wire io_rocc_cmd_valid; // @[RocketCore.scala:153:7] wire io_trace_insns_0_valid_0; // @[RocketCore.scala:153:7] wire [39:0] io_trace_insns_0_iaddr_0; // @[RocketCore.scala:153:7] wire [31:0] io_trace_insns_0_insn_0; // @[RocketCore.scala:153:7] wire [2:0] io_trace_insns_0_priv_0; // @[RocketCore.scala:153:7] wire io_trace_insns_0_exception_0; // @[RocketCore.scala:153:7] wire io_trace_insns_0_interrupt_0; // @[RocketCore.scala:153:7] wire [63:0] io_trace_insns_0_cause_0; // @[RocketCore.scala:153:7] wire [39:0] io_trace_insns_0_tval_0; // @[RocketCore.scala:153:7] wire [63:0] io_trace_time_0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_valid_0_0; // @[RocketCore.scala:153:7] wire [2:0] io_bpwatch_0_action_0; // @[RocketCore.scala:153:7] wire io_vector_status_debug_0; // @[RocketCore.scala:153:7] wire io_vector_status_cease_0; // @[RocketCore.scala:153:7] wire io_vector_status_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_vector_status_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_dprv_0; // @[RocketCore.scala:153:7] wire io_vector_status_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_prv_0; // @[RocketCore.scala:153:7] wire io_vector_status_v_0; // @[RocketCore.scala:153:7] wire io_vector_status_sd_0; // @[RocketCore.scala:153:7] wire io_vector_status_mpv_0; // @[RocketCore.scala:153:7] wire io_vector_status_gva_0; // @[RocketCore.scala:153:7] wire io_vector_status_tsr_0; // @[RocketCore.scala:153:7] wire io_vector_status_tw_0; // @[RocketCore.scala:153:7] wire io_vector_status_tvm_0; // @[RocketCore.scala:153:7] wire io_vector_status_mxr_0; // @[RocketCore.scala:153:7] wire io_vector_status_sum_0; // @[RocketCore.scala:153:7] wire io_vector_status_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_mpp_0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_status_vs_0; // @[RocketCore.scala:153:7] wire io_vector_status_spp_0; // @[RocketCore.scala:153:7] wire io_vector_status_mpie_0; // @[RocketCore.scala:153:7] wire io_vector_status_spie_0; // @[RocketCore.scala:153:7] wire io_vector_status_mie_0; // @[RocketCore.scala:153:7] wire io_vector_status_sie_0; // @[RocketCore.scala:153:7] wire io_vector_ex_vconfig_vtype_vill_0; // @[RocketCore.scala:153:7] wire [54:0] io_vector_ex_vconfig_vtype_reserved_0; // @[RocketCore.scala:153:7] wire io_vector_ex_vconfig_vtype_vma_0; // @[RocketCore.scala:153:7] wire io_vector_ex_vconfig_vtype_vta_0; // @[RocketCore.scala:153:7] wire [2:0] io_vector_ex_vconfig_vtype_vsew_0; // @[RocketCore.scala:153:7] wire io_vector_ex_vconfig_vtype_vlmul_sign_0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_ex_vconfig_vtype_vlmul_mag_0; // @[RocketCore.scala:153:7] wire [12:0] io_vector_ex_vconfig_vl_0; // @[RocketCore.scala:153:7] wire io_vector_ex_valid_0; // @[RocketCore.scala:153:7] wire [31:0] io_vector_ex_inst_0; // @[RocketCore.scala:153:7] wire [39:0] io_vector_ex_pc_0; // @[RocketCore.scala:153:7] wire [11:0] io_vector_ex_vstart_0; // @[RocketCore.scala:153:7] wire [63:0] io_vector_ex_rs1_0; // @[RocketCore.scala:153:7] wire [63:0] io_vector_ex_rs2_0; // @[RocketCore.scala:153:7] wire [1:0] io_vector_wb_vxrm_0; // @[RocketCore.scala:153:7] wire [2:0] io_vector_wb_frm_0; // @[RocketCore.scala:153:7] wire io_vector_resp_ready_0; // @[RocketCore.scala:153:7] wire io_vector_killm_0; // @[RocketCore.scala:153:7] wire io_wfi_0; // @[RocketCore.scala:153:7] reg id_reg_pause; // @[RocketCore.scala:161:25] reg imem_might_request_reg; // @[RocketCore.scala:162:35] assign io_imem_might_request_0 = imem_might_request_reg; // @[RocketCore.scala:153:7, :162:35] reg ex_ctrl_legal; // @[RocketCore.scala:243:20] reg ex_ctrl_fp; // @[RocketCore.scala:243:20] reg ex_ctrl_rocc; // @[RocketCore.scala:243:20] reg ex_ctrl_branch; // @[RocketCore.scala:243:20] reg ex_ctrl_jal; // @[RocketCore.scala:243:20] reg ex_ctrl_jalr; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_alu2; // @[RocketCore.scala:243:20] reg [1:0] ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_imm; // @[RocketCore.scala:243:20] reg ex_ctrl_alu_dw; // @[RocketCore.scala:243:20] reg [4:0] ex_ctrl_alu_fn; // @[RocketCore.scala:243:20] reg ex_ctrl_mem; // @[RocketCore.scala:243:20] wire _ex_sfence_T = ex_ctrl_mem; // @[RocketCore.scala:243:20, :605:29] reg [4:0] ex_ctrl_mem_cmd; // @[RocketCore.scala:243:20] assign io_dmem_req_bits_cmd_0 = ex_ctrl_mem_cmd; // @[RocketCore.scala:153:7, :243:20] reg ex_ctrl_rfs1; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs3; // @[RocketCore.scala:243:20] reg ex_ctrl_wfd; // @[RocketCore.scala:243:20] reg ex_ctrl_mul; // @[RocketCore.scala:243:20] reg ex_ctrl_div; // @[RocketCore.scala:243:20] reg ex_ctrl_wxd; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_csr; // @[RocketCore.scala:243:20] reg ex_ctrl_fence_i; // @[RocketCore.scala:243:20] reg ex_ctrl_fence; // @[RocketCore.scala:243:20] reg ex_ctrl_amo; // @[RocketCore.scala:243:20] reg ex_ctrl_dp; // @[RocketCore.scala:243:20] reg ex_ctrl_vec; // @[RocketCore.scala:243:20] reg mem_ctrl_legal; // @[RocketCore.scala:244:21] reg mem_ctrl_fp; // @[RocketCore.scala:244:21] reg mem_ctrl_rocc; // @[RocketCore.scala:244:21] reg mem_ctrl_branch; // @[RocketCore.scala:244:21] assign io_imem_bht_update_bits_branch_0 = mem_ctrl_branch; // @[RocketCore.scala:153:7, :244:21] reg mem_ctrl_jal; // @[RocketCore.scala:244:21] reg mem_ctrl_jalr; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs1; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_sel_alu2; // @[RocketCore.scala:244:21] reg [1:0] mem_ctrl_sel_alu1; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_sel_imm; // @[RocketCore.scala:244:21] reg mem_ctrl_alu_dw; // @[RocketCore.scala:244:21] reg [4:0] mem_ctrl_alu_fn; // @[RocketCore.scala:244:21] reg mem_ctrl_mem; // @[RocketCore.scala:244:21] reg [4:0] mem_ctrl_mem_cmd; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs1; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs3; // @[RocketCore.scala:244:21] reg mem_ctrl_wfd; // @[RocketCore.scala:244:21] reg mem_ctrl_mul; // @[RocketCore.scala:244:21] reg mem_ctrl_div; // @[RocketCore.scala:244:21] reg mem_ctrl_wxd; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_csr; // @[RocketCore.scala:244:21] reg mem_ctrl_fence_i; // @[RocketCore.scala:244:21] reg mem_ctrl_fence; // @[RocketCore.scala:244:21] reg mem_ctrl_amo; // @[RocketCore.scala:244:21] reg mem_ctrl_dp; // @[RocketCore.scala:244:21] reg mem_ctrl_vec; // @[RocketCore.scala:244:21] reg wb_ctrl_legal; // @[RocketCore.scala:245:20] reg wb_ctrl_fp; // @[RocketCore.scala:245:20] reg wb_ctrl_rocc; // @[RocketCore.scala:245:20] reg wb_ctrl_branch; // @[RocketCore.scala:245:20] reg wb_ctrl_jal; // @[RocketCore.scala:245:20] reg wb_ctrl_jalr; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs1; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_sel_alu2; // @[RocketCore.scala:245:20] reg [1:0] wb_ctrl_sel_alu1; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_sel_imm; // @[RocketCore.scala:245:20] reg wb_ctrl_alu_dw; // @[RocketCore.scala:245:20] reg [4:0] wb_ctrl_alu_fn; // @[RocketCore.scala:245:20] reg wb_ctrl_mem; // @[RocketCore.scala:245:20] reg [4:0] wb_ctrl_mem_cmd; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs1; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs3; // @[RocketCore.scala:245:20] reg wb_ctrl_wfd; // @[RocketCore.scala:245:20] reg wb_ctrl_mul; // @[RocketCore.scala:245:20] reg wb_ctrl_div; // @[RocketCore.scala:245:20] reg wb_ctrl_wxd; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_csr; // @[RocketCore.scala:245:20] reg wb_ctrl_fence_i; // @[RocketCore.scala:245:20] reg wb_ctrl_fence; // @[RocketCore.scala:245:20] reg wb_ctrl_amo; // @[RocketCore.scala:245:20] reg wb_ctrl_dp; // @[RocketCore.scala:245:20] reg wb_ctrl_vec; // @[RocketCore.scala:245:20] reg ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35] reg ex_reg_valid; // @[RocketCore.scala:248:35] reg ex_reg_rvc; // @[RocketCore.scala:249:35] reg [1:0] ex_reg_btb_resp_cfiType; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_taken; // @[RocketCore.scala:250:35] reg [1:0] ex_reg_btb_resp_mask; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_bridx; // @[RocketCore.scala:250:35] reg [38:0] ex_reg_btb_resp_target; // @[RocketCore.scala:250:35] reg [4:0] ex_reg_btb_resp_entry; // @[RocketCore.scala:250:35] reg [7:0] ex_reg_btb_resp_bht_history; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_bht_value; // @[RocketCore.scala:250:35] reg ex_reg_xcpt; // @[RocketCore.scala:251:35] reg ex_reg_flush_pipe; // @[RocketCore.scala:252:35] reg ex_reg_load_use; // @[RocketCore.scala:253:35] reg [63:0] ex_reg_cause; // @[RocketCore.scala:254:35] wire [63:0] ex_cause = ex_reg_cause; // @[RocketCore.scala:254:35, :1278:50] reg ex_reg_replay; // @[RocketCore.scala:255:26] reg [39:0] ex_reg_pc; // @[RocketCore.scala:256:22] assign io_vector_ex_pc_0 = ex_reg_pc; // @[RocketCore.scala:153:7, :256:22] wire [39:0] _ex_op1_T_1 = ex_reg_pc; // @[RocketCore.scala:256:22, :474:24] reg [1:0] ex_reg_mem_size; // @[RocketCore.scala:257:28] assign io_dmem_req_bits_size_0 = ex_reg_mem_size; // @[RocketCore.scala:153:7, :257:28] reg [31:0] ex_reg_inst; // @[RocketCore.scala:259:24] assign io_vector_ex_inst_0 = ex_reg_inst; // @[RocketCore.scala:153:7, :259:24] reg [31:0] ex_reg_raw_inst; // @[RocketCore.scala:260:28] reg ex_reg_wphit_0; // @[RocketCore.scala:261:36] reg ex_reg_set_vconfig; // @[RocketCore.scala:262:36] wire _io_vector_ex_valid_T = ex_reg_set_vconfig; // @[RocketCore.scala:262:36, :1117:90] reg mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36] reg mem_reg_valid; // @[RocketCore.scala:265:36] reg mem_reg_rvc; // @[RocketCore.scala:266:36] reg [1:0] mem_reg_btb_resp_cfiType; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_cfiType_0 = mem_reg_btb_resp_cfiType; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_taken_0 = mem_reg_btb_resp_taken; // @[RocketCore.scala:153:7, :267:36] wire _mem_direction_misprediction_T = mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36, :627:85] reg [1:0] mem_reg_btb_resp_mask; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_mask_0 = mem_reg_btb_resp_mask; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_bridx; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bridx_0 = mem_reg_btb_resp_bridx; // @[RocketCore.scala:153:7, :267:36] reg [38:0] mem_reg_btb_resp_target; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_target_0 = mem_reg_btb_resp_target; // @[RocketCore.scala:153:7, :267:36] reg [4:0] mem_reg_btb_resp_entry; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_entry_0 = mem_reg_btb_resp_entry; // @[RocketCore.scala:153:7, :267:36] reg [7:0] mem_reg_btb_resp_bht_history; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bht_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36] assign io_imem_bht_update_bits_prediction_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_bht_value; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bht_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36] assign io_imem_bht_update_bits_prediction_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_xcpt; // @[RocketCore.scala:268:36] reg mem_reg_replay; // @[RocketCore.scala:269:36] reg mem_reg_flush_pipe; // @[RocketCore.scala:270:36] reg [63:0] mem_reg_cause; // @[RocketCore.scala:271:36] reg mem_reg_slow_bypass; // @[RocketCore.scala:272:36] wire mem_mem_cmd_bh = mem_reg_slow_bypass; // @[RocketCore.scala:272:36, :995:41] reg mem_reg_load; // @[RocketCore.scala:273:36] reg mem_reg_store; // @[RocketCore.scala:274:36] reg mem_reg_set_vconfig; // @[RocketCore.scala:275:36] reg mem_reg_sfence; // @[RocketCore.scala:276:27] reg [39:0] mem_reg_pc; // @[RocketCore.scala:277:23] wire [39:0] _mem_br_target_T = mem_reg_pc; // @[RocketCore.scala:277:23, :615:34] reg [31:0] mem_reg_inst; // @[RocketCore.scala:278:25] reg [1:0] mem_reg_mem_size; // @[RocketCore.scala:279:29] reg mem_reg_hls_or_dv; // @[RocketCore.scala:280:30] reg [31:0] mem_reg_raw_inst; // @[RocketCore.scala:281:29] reg [63:0] mem_reg_wdata; // @[RocketCore.scala:282:26] wire [63:0] _mem_int_wdata_T_3 = mem_reg_wdata; // @[RocketCore.scala:282:26, :624:111] reg [76:0] mem_reg_rs2; // @[RocketCore.scala:283:24] reg mem_br_taken; // @[RocketCore.scala:284:25] assign io_imem_bht_update_bits_taken_0 = mem_br_taken; // @[RocketCore.scala:153:7, :284:25] wire _take_pc_mem_T_3; // @[RocketCore.scala:629:49] wire take_pc_mem; // @[RocketCore.scala:285:25] reg mem_reg_wphit_0; // @[RocketCore.scala:286:35] reg wb_reg_valid; // @[RocketCore.scala:288:35] reg wb_reg_xcpt; // @[RocketCore.scala:289:35] reg wb_reg_replay; // @[RocketCore.scala:290:35] reg wb_reg_flush_pipe; // @[RocketCore.scala:291:35] reg [63:0] wb_reg_cause; // @[RocketCore.scala:292:35] reg wb_reg_set_vconfig; // @[RocketCore.scala:293:35] reg wb_reg_sfence; // @[RocketCore.scala:294:26] reg [39:0] wb_reg_pc; // @[RocketCore.scala:295:22] reg [1:0] wb_reg_mem_size; // @[RocketCore.scala:296:28] reg wb_reg_hls_or_dv; // @[RocketCore.scala:297:29] reg wb_reg_hfence_v; // @[RocketCore.scala:298:28] assign io_imem_sfence_bits_hv_0 = wb_reg_hfence_v; // @[RocketCore.scala:153:7, :298:28] reg wb_reg_hfence_g; // @[RocketCore.scala:299:28] assign io_imem_sfence_bits_hg_0 = wb_reg_hfence_g; // @[RocketCore.scala:153:7, :299:28] reg [31:0] wb_reg_inst; // @[RocketCore.scala:300:24] wire [31:0] _io_rocc_cmd_bits_inst_WIRE_1 = wb_reg_inst; // @[RocketCore.scala:300:24, :1159:48] reg [31:0] wb_reg_raw_inst; // @[RocketCore.scala:301:28] reg [63:0] wb_reg_wdata; // @[RocketCore.scala:302:25] assign io_rocc_cmd_bits_rs1 = wb_reg_wdata; // @[RocketCore.scala:153:7, :302:25] wire [63:0] _rf_wdata_T_3 = wb_reg_wdata; // @[RocketCore.scala:302:25, :822:21] reg [76:0] wb_reg_rs2; // @[RocketCore.scala:303:23] wire [76:0] _csr_io_vector_set_vconfig_bits_WIRE_1 = wb_reg_rs2; // @[RocketCore.scala:303:23, :868:46] wire _take_pc_wb_T_2; // @[RocketCore.scala:762:53] wire take_pc_wb; // @[RocketCore.scala:304:24] reg wb_reg_wphit_0; // @[RocketCore.scala:305:35] assign io_bpwatch_0_valid_0_0 = wb_reg_wphit_0; // @[RocketCore.scala:153:7, :305:35] assign take_pc_mem_wb = take_pc_wb \| take_pc_mem; // @[RocketCore.scala:285:25, :304:24, :307:35] assign io_imem_req_valid_0 = take_pc_mem_wb; // @[RocketCore.scala:153:7, :307:35] wire _id_illegal_insn_T_32 = id_ctrl_rocc; // @[RocketCore.scala:321:21, :391:18] wire [2:0] id_ctrl_decoder_8; // @[Decode.scala:50:77] wire [1:0] id_ctrl_decoder_9; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_10; // @[Decode.scala:50:77] wire id_ctrl_decoder_11; // @[Decode.scala:50:77] wire [4:0] id_ctrl_decoder_12; // @[Decode.scala:50:77] wire [4:0] id_ctrl_decoder_14; // @[Decode.scala:50:77] wire _id_do_fence_T = id_ctrl_fence; // @[RocketCore.scala:321:21, :410:64] wire id_ctrl_legal; // @[RocketCore.scala:321:21] wire id_ctrl_fp; // @[RocketCore.scala:321:21] wire id_ctrl_branch; // @[RocketCore.scala:321:21] wire id_ctrl_jal; // @[RocketCore.scala:321:21] wire id_ctrl_jalr; // @[RocketCore.scala:321:21] wire id_ctrl_rxs2; // @[RocketCore.scala:321:21] wire id_ctrl_rxs1; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_sel_alu2; // @[RocketCore.scala:321:21] wire [1:0] id_ctrl_sel_alu1; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_sel_imm; // @[RocketCore.scala:321:21] wire id_ctrl_alu_dw; // @[RocketCore.scala:321:21] wire [4:0] id_ctrl_alu_fn; // @[RocketCore.scala:321:21] wire id_ctrl_mem; // @[RocketCore.scala:321:21] wire [4:0] id_ctrl_mem_cmd; // @[RocketCore.scala:321:21] wire id_ctrl_rfs1; // @[RocketCore.scala:321:21] wire id_ctrl_rfs2; // @[RocketCore.scala:321:21] wire id_ctrl_rfs3; // @[RocketCore.scala:321:21] wire id_ctrl_wfd; // @[RocketCore.scala:321:21] wire id_ctrl_mul; // @[RocketCore.scala:321:21] wire id_ctrl_div; // @[RocketCore.scala:321:21] wire id_ctrl_wxd; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_csr; // @[RocketCore.scala:321:21] wire id_ctrl_fence_i; // @[RocketCore.scala:321:21] wire id_ctrl_amo; // @[RocketCore.scala:321:21] wire id_ctrl_dp; // @[RocketCore.scala:321:21] wire id_ctrl_vec; // @[RocketCore.scala:321:21] wire [31:0] id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22] wire [31:0] id_ctrl_decoder_decoded_invInputs = ~id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [41:0] id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [41:0] id_ctrl_decoder_decoded; // @[pla.scala:81:23] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_194 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_195 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_196 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_194 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_195 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_196 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_194 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_195 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_196 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_194 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_195 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_196 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_193 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_194 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_195 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_184 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_185 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T = {id_ctrl_decoder_decoded_andMatrixOutputs_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_100_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_103_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_183 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_165 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_166 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_9_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_164 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_145 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_146 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_29_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_140_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_118_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_4 = id_ctrl_decoder_decoded_andMatrixOutputs_118_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_194 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_195 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_196 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_97_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_35_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_185_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_129_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_67_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_47 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_78_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_193_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_7_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_99_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_32_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_71_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_190 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_191 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_192 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [4:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_184_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_16 = id_ctrl_decoder_decoded_andMatrixOutputs_184_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_146_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_144_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_20_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_22_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_98_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_39_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_132_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_194_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_63 = id_ctrl_decoder_decoded_andMatrixOutputs_194_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_165_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_64 = id_ctrl_decoder_decoded_andMatrixOutputs_165_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_141 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_138 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_139 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_134 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_132 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_119 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_55_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_91_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_30_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_26_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_178_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_77_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_21_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_5 = id_ctrl_decoder_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_122_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_61_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_106_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_24_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_166_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_161_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_96_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_56_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_16_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_188_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_6 = id_ctrl_decoder_decoded_andMatrixOutputs_188_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_141_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_53_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_196_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_93_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_17_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_130_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_180_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_124_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_14_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_27 = id_ctrl_decoder_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_133_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_49_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_156_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_7 = id_ctrl_decoder_decoded_andMatrixOutputs_156_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_187_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_149_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_116_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_163_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_44_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_127_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_151_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_162_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_134_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_182_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_5_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_89_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_95_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_66_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_126_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_92_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_113_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_171_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_147_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_170_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_2_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_15_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_169_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_179_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_173_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_76_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_88_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_145_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_36_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_41_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_8_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_105_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_73_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_192_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_28_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_0_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_144 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_142 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_143 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_60_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_48_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_168_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_164_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_138_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_74_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_59_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_153_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_47_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_104_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_84_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_28 = id_ctrl_decoder_decoded_andMatrixOutputs_84_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_31_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_13_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_112_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_65_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_125_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_50_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_6_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_135_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_154_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_110_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_190_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_45_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_79_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_160_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_34_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_87_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_10_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_94_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_183_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_43_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_136_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_3_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_191_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_4_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_25_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_58_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_148_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_27_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_52_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_139_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_181_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_176_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_121_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_19_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_64_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_143_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_11_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_46_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_142_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_115_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_70_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_72_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_177_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_81_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_131_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_158_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_68_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_42_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_54_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_63_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_69_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_186_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_51_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_137_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_128_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_152_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_1_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_101_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_107_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_189_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_18_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_109_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_90_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_62_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_150_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_172_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_169}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_37_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_169; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = id_ctrl_decoder_decoded_plaInput[23]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_170}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_123_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_170; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_171}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_83_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_171; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168}; // @[pla.scala:98:53] wire [31:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_172}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_120_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_172; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_173}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_174_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_173; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_174}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_82_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_174; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_175}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_57_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_175; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_176}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_80_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_176; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_177}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_167_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_177; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_178}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_155_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_178; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_179}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_195_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_179; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_180}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_38_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_180; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_181}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_159_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_181; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_182}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_111_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_182; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_183}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_23_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_183; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_184}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_102_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_184; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_185}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_175_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_185; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_186}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_119_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_186; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_187}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_117_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_187; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_188}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_157_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_188; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_189}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_114_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_189; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_190}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_108_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_190; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_191}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_85_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_191; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_192}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_33_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_192; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_lo_193}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_86_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_193; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_194 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_183}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_141}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_164}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_194, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_194}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_193}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_194, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_194}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_194}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_194 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_194 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_194, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_190}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_194 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_194, id_ctrl_decoder_decoded_andMatrixOutputs_lo_194}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_40_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_194; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_194 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_195 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_194, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_184}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_142}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_165}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_195, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_195}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_194}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_195, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_195}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_195}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_195 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_195 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_195, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_191}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_195 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_195, id_ctrl_decoder_decoded_andMatrixOutputs_lo_195}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_12_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_195; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_78}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_134}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_132}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_195 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_132}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_196 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_195, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_185}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_143}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_166}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_196, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_196}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_195}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_196, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_196}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_196}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_196 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_134}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_196 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_196, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_192}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_196 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_196, id_ctrl_decoder_decoded_andMatrixOutputs_lo_196}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_75_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_196; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_119_2, id_ctrl_decoder_decoded_andMatrixOutputs_86_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_115_2, id_ctrl_decoder_decoded_andMatrixOutputs_177_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_128_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_87_2, id_ctrl_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_94_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_149_2, id_ctrl_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [11:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T = {id_ctrl_decoder_decoded_orMatrixOutputs_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_1 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _GEN = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_1 = _GEN; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6 = _GEN; // @[pla.scala:114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_3 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_47_2, id_ctrl_decoder_decoded_andMatrixOutputs_84_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_156_2, id_ctrl_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_55_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_9 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_175_2, id_ctrl_decoder_decoded_andMatrixOutputs_85_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_102_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_57_2, id_ctrl_decoder_decoded_andMatrixOutputs_80_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_0 = {id_ctrl_decoder_decoded_andMatrixOutputs_90_2, id_ctrl_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = _GEN_0; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_152_2, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_176_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_136_2, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = _GEN_1; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = _GEN_1; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_160_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = _GEN_2; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_183_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [23:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = _GEN_3; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = _GEN_3; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4 = _GEN_3; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_156_2, id_ctrl_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = _GEN_4; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = _GEN_4; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_169_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_165_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = _GEN_5; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = _GEN_5; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = _GEN_5; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = _GEN_5; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_194_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_193_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_6; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3 = _GEN_6; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_140_2, id_ctrl_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = _GEN_7; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [12:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [24:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [48:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_11 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_179_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_13 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_117_2, id_ctrl_decoder_decoded_andMatrixOutputs_157_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_72_2, id_ctrl_decoder_decoded_andMatrixOutputs_81_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_45_2, id_ctrl_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_154_2, id_ctrl_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3 = _GEN_10; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_77_2, id_ctrl_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_184_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = _GEN_11; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_15 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_110_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = _GEN_12; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_154_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_124_2, id_ctrl_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_22_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [12:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_18 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_85_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_13; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = _GEN_13; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_102_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_70_2, id_ctrl_decoder_decoded_andMatrixOutputs_177_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_110_2, id_ctrl_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_154_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_125_2, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_20 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_65_2, id_ctrl_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_129_2, id_ctrl_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_22 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_138_2, id_ctrl_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_24 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_23; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_26 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_25; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_74_2, id_ctrl_decoder_decoded_andMatrixOutputs_112_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_103_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [8:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_30 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_143_2, id_ctrl_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_150_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_168_2, id_ctrl_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_95_2, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_56_2, id_ctrl_decoder_decoded_andMatrixOutputs_182_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = _GEN_14; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = _GEN_14; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = _GEN_14; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19] wire [14:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_32 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_64_2, id_ctrl_decoder_decoded_andMatrixOutputs_143_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_139_2, id_ctrl_decoder_decoded_andMatrixOutputs_176_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = _GEN_15; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = _GEN_15; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_43_2, id_ctrl_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_73_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_170_2, id_ctrl_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_113_2, id_ctrl_decoder_decoded_andMatrixOutputs_171_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_39_2, id_ctrl_decoder_decoded_andMatrixOutputs_116_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19] wire [17:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_34 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_183_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_24; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_24 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_5_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_151_2, id_ctrl_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19] wire [10:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_36 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_54_2, id_ctrl_decoder_decoded_andMatrixOutputs_186_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_148_2, id_ctrl_decoder_decoded_andMatrixOutputs_181_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_48_2, id_ctrl_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19] wire [9:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_38 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_37; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_172_2, id_ctrl_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_107_2, id_ctrl_decoder_decoded_andMatrixOutputs_189_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_11_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19] wire [13:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_40 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_62_2, id_ctrl_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_152_2, id_ctrl_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = _GEN_17; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = _GEN_17; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = _GEN_17; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_34_2, id_ctrl_decoder_decoded_andMatrixOutputs_183_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_192_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_162_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = _GEN_18; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = _GEN_18; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_165_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_78_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19] wire [35:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_42 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_66_2, id_ctrl_decoder_decoded_andMatrixOutputs_147_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_44 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}] wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_46 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_101_2, id_ctrl_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] _GEN_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = _GEN_19; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN_19; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = _GEN_20; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_183_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_92_2, id_ctrl_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_24_2, id_ctrl_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_194_2, id_ctrl_decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19] wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_48 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_123_2, id_ctrl_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_157_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = _GEN_21; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] _GEN_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_176_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = _GEN_22; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = _GEN_22; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = _GEN_22; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_31_2, id_ctrl_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = _GEN_23; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = _GEN_23; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] _GEN_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = _GEN_24; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = _GEN_24; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = _GEN_24; // @[pla.scala:114:19] wire [1:0] _GEN_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_127_2, id_ctrl_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = _GEN_25; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_187_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_106_2, id_ctrl_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] _GEN_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = _GEN_26; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = _GEN_26; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_193_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = _GEN_27; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = _GEN_27; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19] wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_50 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_49; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_185_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_192_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_52 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_183_2, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19] wire [1:0] _GEN_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_141_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = _GEN_28; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = _GEN_28; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = _GEN_28; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_194_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_29_2, id_ctrl_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:114:19] wire [12:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19] wire [24:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_54 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_143_2, id_ctrl_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_147_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_127_2, id_ctrl_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_193_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19] wire [34:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_56 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_68_2, id_ctrl_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_24, id_ctrl_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_58 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_82_2, id_ctrl_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_157_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_101_2, id_ctrl_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:114:19] wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_162_2, id_ctrl_decoder_decoded_andMatrixOutputs_169_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_187_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_16_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:114:19] wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19] wire [45:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_25, id_ctrl_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_60 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_59; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_90_2, id_ctrl_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_34_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_138_2, id_ctrl_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_162_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] _GEN_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = _GEN_29; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = _GEN_29; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_129_2, id_ctrl_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_193_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19] wire [22:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_26, id_ctrl_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_62 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_61; // @[pla.scala:114:{19,36}] wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_66 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_65; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_159_2, id_ctrl_decoder_decoded_andMatrixOutputs_111_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_195_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_131_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = _GEN_30; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2 = _GEN_30; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_177_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_50_2, id_ctrl_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_178_2, id_ctrl_decoder_decoded_andMatrixOutputs_196_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19] wire [20:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_27, id_ctrl_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_68 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_67; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_114_2, id_ctrl_decoder_decoded_andMatrixOutputs_108_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_111_2, id_ctrl_decoder_decoded_andMatrixOutputs_175_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_120_2, id_ctrl_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_189_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_107_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_177_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_112_2, id_ctrl_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:114:19] wire [35:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_153_2, id_ctrl_decoder_decoded_andMatrixOutputs_104_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_169_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_91_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_132_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_146_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_118_2, id_ctrl_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:114:19] wire [35:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19] wire [71:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_28, id_ctrl_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_70 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_69; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_3, _id_ctrl_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_9, _id_ctrl_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5 = {1'h0, _id_ctrl_decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5, _id_ctrl_decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_16, _id_ctrl_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_22, _id_ctrl_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_27, _id_ctrl_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_32, _id_ctrl_decoder_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:102:36] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:102:36] wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_36, _id_ctrl_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_42, _id_ctrl_decoder_decoded_orMatrixOutputs_T_40}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_38}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_46, _id_ctrl_decoder_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_52, _id_ctrl_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_56, _id_ctrl_decoder_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_62, _id_ctrl_decoder_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_66, _id_ctrl_decoder_decoded_orMatrixOutputs_T_64}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_70, _id_ctrl_decoder_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6, 1'h0}; // @[pla.scala:102:36] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:102:36] wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:102:36] wire [41:0] id_ctrl_decoder_decoded_orMatrixOutputs = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_29, id_ctrl_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:102:36] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T = id_ctrl_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_1 = id_ctrl_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_2 = id_ctrl_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_3 = id_ctrl_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_4 = id_ctrl_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_5 = id_ctrl_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_6 = id_ctrl_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_7 = id_ctrl_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_8 = id_ctrl_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_9 = id_ctrl_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_10 = id_ctrl_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_11 = id_ctrl_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_12 = id_ctrl_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_13 = id_ctrl_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_14 = id_ctrl_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_15 = id_ctrl_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_16 = id_ctrl_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_17 = id_ctrl_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_18 = id_ctrl_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_19 = id_ctrl_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_20 = id_ctrl_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_21 = id_ctrl_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_22 = id_ctrl_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_23 = id_ctrl_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_24 = id_ctrl_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_25 = id_ctrl_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_26 = id_ctrl_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_27 = id_ctrl_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_28 = id_ctrl_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_29 = id_ctrl_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_30 = id_ctrl_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_31 = id_ctrl_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_32 = id_ctrl_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_33 = id_ctrl_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_34 = id_ctrl_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_35 = id_ctrl_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_36 = id_ctrl_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_37 = id_ctrl_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_38 = id_ctrl_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_39 = id_ctrl_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_40 = id_ctrl_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_41 = id_ctrl_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_1, _id_ctrl_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_4, _id_ctrl_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_6, _id_ctrl_decoder_decoded_invMatrixOutputs_T_5}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_9, _id_ctrl_decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_11, _id_ctrl_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_14, _id_ctrl_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_17, _id_ctrl_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_20, _id_ctrl_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_22, _id_ctrl_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_25, _id_ctrl_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_27, _id_ctrl_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_30, _id_ctrl_decoder_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_32, _id_ctrl_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_35, _id_ctrl_decoder_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_38, _id_ctrl_decoder_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_41, _id_ctrl_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign id_ctrl_decoder_decoded_invMatrixOutputs = {id_ctrl_decoder_decoded_invMatrixOutputs_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign id_ctrl_decoder_decoded = id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire id_ctrl_decoder_0 = id_ctrl_decoder_decoded[41]; // @[pla.scala:81:23] wire id_ctrl_decoder_1 = id_ctrl_decoder_decoded[40]; // @[pla.scala:81:23] wire id_ctrl_decoder_2 = id_ctrl_decoder_decoded[39]; // @[pla.scala:81:23] wire id_ctrl_decoder_3 = id_ctrl_decoder_decoded[38]; // @[pla.scala:81:23] wire id_ctrl_decoder_4 = id_ctrl_decoder_decoded[37]; // @[pla.scala:81:23] wire id_ctrl_decoder_5 = id_ctrl_decoder_decoded[36]; // @[pla.scala:81:23] wire id_ctrl_decoder_6 = id_ctrl_decoder_decoded[35]; // @[pla.scala:81:23] wire id_ctrl_decoder_7 = id_ctrl_decoder_decoded[34]; // @[pla.scala:81:23] assign id_ctrl_decoder_8 = id_ctrl_decoder_decoded[33:31]; // @[pla.scala:81:23] assign id_ctrl_sel_alu2 = id_ctrl_decoder_8; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_9 = id_ctrl_decoder_decoded[30:29]; // @[pla.scala:81:23] assign id_ctrl_sel_alu1 = id_ctrl_decoder_9; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_10 = id_ctrl_decoder_decoded[28:26]; // @[pla.scala:81:23] assign id_ctrl_sel_imm = id_ctrl_decoder_10; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_11 = id_ctrl_decoder_decoded[25]; // @[pla.scala:81:23] assign id_ctrl_alu_dw = id_ctrl_decoder_11; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_12 = id_ctrl_decoder_decoded[24:20]; // @[pla.scala:81:23] assign id_ctrl_alu_fn = id_ctrl_decoder_12; // @[RocketCore.scala:321:21] wire id_ctrl_decoder_13 = id_ctrl_decoder_decoded[19]; // @[pla.scala:81:23] assign id_ctrl_decoder_14 = id_ctrl_decoder_decoded[18:14]; // @[pla.scala:81:23] assign id_ctrl_mem_cmd = id_ctrl_decoder_14; // @[RocketCore.scala:321:21] wire id_ctrl_decoder_15 = id_ctrl_decoder_decoded[13]; // @[pla.scala:81:23] wire id_ctrl_decoder_16 = id_ctrl_decoder_decoded[12]; // @[pla.scala:81:23] wire id_ctrl_decoder_17 = id_ctrl_decoder_decoded[11]; // @[pla.scala:81:23] wire id_ctrl_decoder_18 = id_ctrl_decoder_decoded[10]; // @[pla.scala:81:23] wire id_ctrl_decoder_19 = id_ctrl_decoder_decoded[9]; // @[pla.scala:81:23] wire id_ctrl_decoder_20 = id_ctrl_decoder_decoded[8]; // @[pla.scala:81:23] wire id_ctrl_decoder_21 = id_ctrl_decoder_decoded[7]; // @[pla.scala:81:23] wire [2:0] id_ctrl_decoder_22 = id_ctrl_decoder_decoded[6:4]; // @[pla.scala:81:23] wire id_ctrl_decoder_23 = id_ctrl_decoder_decoded[3]; // @[pla.scala:81:23] wire id_ctrl_decoder_24 = id_ctrl_decoder_decoded[2]; // @[pla.scala:81:23] wire id_ctrl_decoder_25 = id_ctrl_decoder_decoded[1]; // @[pla.scala:81:23] wire id_ctrl_decoder_26 = id_ctrl_decoder_decoded[0]; // @[pla.scala:81:23] wire [4:0] id_raddr3; // @[RocketCore.scala:326:72] wire [4:0] id_raddr2; // @[RocketCore.scala:326:72] wire [4:0] _id_rs_T_7 = id_raddr2; // @[RocketCore.scala:326:72, :1320:44] wire [4:0] id_raddr1; // @[RocketCore.scala:326:72] wire [4:0] _id_rs_T_2 = id_raddr1; // @[RocketCore.scala:326:72, :1320:44] wire [4:0] id_waddr; // @[RocketCore.scala:326:72] wire _id_load_use_T_1; // @[RocketCore.scala:1001:51] wire id_load_use; // @[RocketCore.scala:332:25] reg id_reg_fence; // @[RocketCore.scala:333:29] wire [63:0] id_rs_0; // @[RocketCore.scala:1325:26] wire _id_rs_T = ~(\|id_raddr1); // @[RocketCore.scala:326:72, :1326:41] wire [4:0] _id_rs_T_3 = ~_id_rs_T_2; // @[RocketCore.scala:1320:{39,44}] wire [63:0] id_rs_1; // @[RocketCore.scala:1325:26] wire _id_rs_T_5 = ~(\|id_raddr2); // @[RocketCore.scala:326:72, :1326:41] wire [4:0] _id_rs_T_8 = ~_id_rs_T_7; // @[RocketCore.scala:1320:{39,44}] wire _ctrl_killd_T_4; // @[RocketCore.scala:1046:104] wire ctrl_killd; // @[RocketCore.scala:338:24] wire _id_npc_sign_T_1 = _ibuf_io_inst_0_bits_inst_bits[31]; // @[RocketCore.scala:311:20, :1341:44] wire _id_npc_sign_T_2 = _id_npc_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire id_npc_sign = _id_npc_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire _id_npc_b11_T_9 = id_npc_sign; // @[RocketCore.scala:1341:19, :1346:18] wire id_npc_hi_hi_hi = id_npc_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _id_npc_b30_20_T_1 = _ibuf_io_inst_0_bits_inst_bits[30:20]; // @[RocketCore.scala:311:20, :1342:41] wire [10:0] _id_npc_b30_20_T_2 = _id_npc_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] id_npc_b30_20 = {11{id_npc_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] id_npc_hi_hi_lo = id_npc_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _id_npc_b19_12_T_3 = _ibuf_io_inst_0_bits_inst_bits[19:12]; // @[RocketCore.scala:311:20, :1343:65] wire [7:0] _id_npc_b19_12_T_4 = _id_npc_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] id_npc_b19_12 = _id_npc_b19_12_T_4; // @[RocketCore.scala:1343:{21,73}] wire [7:0] id_npc_hi_lo_hi = id_npc_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _id_npc_b11_T_4 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39] wire _id_npc_b0_T_3 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39, :1352:37] wire _id_npc_b11_T_5 = _id_npc_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _id_npc_b11_T_10 = _id_npc_b11_T_5; // @[RocketCore.scala:1345:{18,44}] wire _id_npc_b11_T_7 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39] wire _id_npc_b0_T_1 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39, :1351:37] wire _id_npc_b11_T_8 = _id_npc_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire id_npc_b11 = _id_npc_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire id_npc_hi_lo_lo = id_npc_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _id_npc_b10_5_T_3 = _ibuf_io_inst_0_bits_inst_bits[30:25]; // @[RocketCore.scala:311:20, :1347:62] wire [5:0] id_npc_b10_5 = _id_npc_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _id_npc_b4_1_T_4 = _ibuf_io_inst_0_bits_inst_bits[11:8]; // @[RocketCore.scala:311:20, :1349:57] wire [3:0] _id_npc_b4_1_T_6 = _ibuf_io_inst_0_bits_inst_bits[19:16]; // @[RocketCore.scala:311:20, :1350:39] wire [3:0] _id_npc_b4_1_T_7 = _ibuf_io_inst_0_bits_inst_bits[24:21]; // @[RocketCore.scala:311:20, :1350:52] wire [3:0] _id_npc_b4_1_T_8 = _id_npc_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _id_npc_b4_1_T_9 = _id_npc_b4_1_T_8; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] id_npc_b4_1 = _id_npc_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _id_npc_b0_T_5 = _ibuf_io_inst_0_bits_inst_bits[15]; // @[RocketCore.scala:311:20, :1353:37] wire [9:0] id_npc_lo_hi = {id_npc_b10_5, id_npc_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] id_npc_lo = {id_npc_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] id_npc_hi_lo = {id_npc_hi_lo_hi, id_npc_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] id_npc_hi_hi = {id_npc_hi_hi_hi, id_npc_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] id_npc_hi = {id_npc_hi_hi, id_npc_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _id_npc_T_1 = {id_npc_hi, id_npc_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _id_npc_T_2 = _id_npc_T_1; // @[RocketCore.scala:1355:{8,53}] wire [39:0] _id_npc_T; // @[RocketCore.scala:339:28] wire [40:0] _id_npc_T_3 = {_id_npc_T[39], _id_npc_T} + {{9{_id_npc_T_2[31]}}, _id_npc_T_2}; // @[RocketCore.scala:339:{28,35}, :1355:53] wire [39:0] _id_npc_T_4 = _id_npc_T_3[39:0]; // @[RocketCore.scala:339:35] wire [39:0] _id_npc_T_5 = _id_npc_T_4; // @[RocketCore.scala:339:35] wire [39:0] id_npc = _id_npc_T_5; // @[RocketCore.scala:339:{35,65}] wire _GEN_31 = id_ctrl_csr == 3'h6; // @[package.scala:16:47] wire _id_csr_en_T; // @[package.scala:16:47] assign _id_csr_en_T = _GEN_31; // @[package.scala:16:47] wire _id_csr_ren_T; // @[package.scala:16:47] assign _id_csr_ren_T = _GEN_31; // @[package.scala:16:47] wire _id_csr_en_T_1 = &id_ctrl_csr; // @[package.scala:16:47] wire _id_csr_en_T_2 = id_ctrl_csr == 3'h5; // @[package.scala:16:47] wire _id_csr_en_T_3 = _id_csr_en_T \| _id_csr_en_T_1; // @[package.scala:16:47, :81:59] wire id_csr_en = _id_csr_en_T_3 \| _id_csr_en_T_2; // @[package.scala:16:47, :81:59] wire id_system_insn = id_ctrl_csr == 3'h4; // @[RocketCore.scala:321:21, :343:36] wire _id_csr_ren_T_1 = &id_ctrl_csr; // @[package.scala:16:47] wire _id_csr_ren_T_2 = _id_csr_ren_T \| _id_csr_ren_T_1; // @[package.scala:16:47, :81:59] wire _id_csr_ren_T_3 = _ibuf_io_inst_0_bits_inst_rs1 == 5'h0; // @[RocketCore.scala:311:20, :344:81] wire id_csr_ren = _id_csr_ren_T_2 & _id_csr_ren_T_3; // @[package.scala:81:59] wire _id_csr_T = id_system_insn & id_ctrl_mem; // @[RocketCore.scala:321:21, :343:36, :345:35] wire [2:0] _id_csr_T_1 = id_csr_ren ? 3'h2 : id_ctrl_csr; // @[RocketCore.scala:321:21, :344:54, :345:61] wire [2:0] id_csr = _id_csr_T ? 3'h0 : _id_csr_T_1; // @[RocketCore.scala:345:{19,35,61}] wire _id_csr_flush_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54] wire _id_csr_flush_T_1 = id_csr_en & _id_csr_flush_T; // @[package.scala:81:59] wire _id_csr_flush_T_2 = _id_csr_flush_T_1 & _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19, :346:{51,66}] wire id_csr_flush = id_system_insn \| _id_csr_flush_T_2; // @[RocketCore.scala:343:36, :346:{37,66}] wire [31:0] _id_set_vconfig_T = _ibuf_io_inst_0_bits_inst_bits & 32'h8000707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_1 = _id_set_vconfig_T == 32'h7057; // @[RocketCore.scala:347:100] wire [31:0] _id_set_vconfig_T_2 = _ibuf_io_inst_0_bits_inst_bits & 32'hC000707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_3 = _id_set_vconfig_T_2 == 32'hC0007057; // @[RocketCore.scala:347:100] wire [31:0] _id_set_vconfig_T_4 = _ibuf_io_inst_0_bits_inst_bits & 32'hFE00707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_5 = _id_set_vconfig_T_4 == 32'h80007057; // @[RocketCore.scala:347:100] wire _id_set_vconfig_T_6 = _id_set_vconfig_T_1 \| _id_set_vconfig_T_3; // @[package.scala:81:59] wire _id_set_vconfig_T_7 = _id_set_vconfig_T_6 \| _id_set_vconfig_T_5; // @[package.scala:81:59] wire id_set_vconfig = _id_set_vconfig_T_7; // @[package.scala:81:59] wire _id_ctrl_legal_T = ~_csr_io_vector_vconfig_vtype_vill; // @[RocketCore.scala:341:19, :355:24] assign id_ctrl_legal = _v_decode_io_legal ? _id_ctrl_legal_T : id_ctrl_decoder_0; // @[RocketCore.scala:321:21, :354:30, :355:{21,24}] assign id_ctrl_fp = _v_decode_io_legal ? _v_decode_io_fp : id_ctrl_decoder_1; // @[RocketCore.scala:321:21, :354:30, :356:18] assign id_ctrl_rocc = ~_v_decode_io_legal & id_ctrl_decoder_2; // @[RocketCore.scala:321:21, :354:30, :357:20] assign id_ctrl_branch = ~_v_decode_io_legal & id_ctrl_decoder_3; // @[RocketCore.scala:321:21, :354:30, :357:20, :358:22] assign id_ctrl_jal = ~_v_decode_io_legal & id_ctrl_decoder_4; // @[RocketCore.scala:321:21, :354:30, :357:20, :359:19] assign id_ctrl_jalr = ~_v_decode_io_legal & id_ctrl_decoder_5; // @[RocketCore.scala:321:21, :354:30, :357:20, :360:20] assign id_ctrl_rxs2 = _v_decode_io_legal ? _v_decode_io_read_rs2 : id_ctrl_decoder_6; // @[RocketCore.scala:321:21, :354:30, :361:20] assign id_ctrl_rxs1 = _v_decode_io_legal ? _v_decode_io_read_rs1 : id_ctrl_decoder_7; // @[RocketCore.scala:321:21, :354:30, :362:20] assign id_ctrl_mem = ~_v_decode_io_legal & id_ctrl_decoder_13; // @[RocketCore.scala:321:21, :354:30, :357:20, :363:19] assign id_ctrl_rfs1 = _v_decode_io_legal ? _v_decode_io_read_frs1 : id_ctrl_decoder_15; // @[RocketCore.scala:321:21, :354:30, :364:20] assign id_ctrl_rfs2 = ~_v_decode_io_legal & id_ctrl_decoder_16; // @[RocketCore.scala:321:21, :354:30, :357:20, :365:20] assign id_ctrl_rfs3 = ~_v_decode_io_legal & id_ctrl_decoder_17; // @[RocketCore.scala:321:21, :354:30, :357:20, :366:20] assign id_ctrl_wfd = _v_decode_io_legal ? _v_decode_io_write_frd : id_ctrl_decoder_18; // @[RocketCore.scala:321:21, :354:30, :367:19] assign id_ctrl_mul = ~_v_decode_io_legal & id_ctrl_decoder_19; // @[RocketCore.scala:321:21, :354:30, :357:20, :368:19] assign id_ctrl_div = ~_v_decode_io_legal & id_ctrl_decoder_20; // @[RocketCore.scala:321:21, :354:30, :357:20, :369:19] assign id_ctrl_wxd = _v_decode_io_legal ? _v_decode_io_write_rd : id_ctrl_decoder_21; // @[RocketCore.scala:321:21, :354:30, :370:19] assign id_ctrl_csr = _v_decode_io_legal ? 3'h0 : id_ctrl_decoder_22; // @[RocketCore.scala:321:21, :354:30, :371:19] assign id_ctrl_fence_i = ~_v_decode_io_legal & id_ctrl_decoder_23; // @[RocketCore.scala:321:21, :354:30, :357:20, :372:23] assign id_ctrl_fence = ~_v_decode_io_legal & id_ctrl_decoder_24; // @[RocketCore.scala:321:21, :354:30, :357:20, :373:21] assign id_ctrl_amo = ~_v_decode_io_legal & id_ctrl_decoder_25; // @[RocketCore.scala:321:21, :354:30, :357:20, :374:19] assign id_ctrl_dp = ~_v_decode_io_legal & id_ctrl_decoder_26; // @[RocketCore.scala:321:21, :354:30, :357:20, :375:18] wire _id_illegal_insn_T = ~id_ctrl_legal; // @[RocketCore.scala:321:21, :381:25] wire _id_illegal_insn_T_1 = id_ctrl_mul \| id_ctrl_div; // @[RocketCore.scala:321:21, :382:18] wire _id_illegal_insn_T_2 = _csr_io_status_isa[12]; // @[RocketCore.scala:341:19, :382:55] wire _id_illegal_insn_T_3 = ~_id_illegal_insn_T_2; // @[RocketCore.scala:382:{37,55}] wire _id_illegal_insn_T_4 = _id_illegal_insn_T_1 & _id_illegal_insn_T_3; // @[RocketCore.scala:382:{18,34,37}] wire _id_illegal_insn_T_5 = _id_illegal_insn_T \| _id_illegal_insn_T_4; // @[RocketCore.scala:381:{25,40}, :382:34] wire _id_illegal_insn_T_6 = _csr_io_status_isa[0]; // @[RocketCore.scala:341:19, :383:38] wire _id_illegal_insn_T_7 = ~_id_illegal_insn_T_6; // @[RocketCore.scala:383:{20,38}] wire _id_illegal_insn_T_8 = id_ctrl_amo & _id_illegal_insn_T_7; // @[RocketCore.scala:321:21, :383:{17,20}] wire _id_illegal_insn_T_9 = _id_illegal_insn_T_5 \| _id_illegal_insn_T_8; // @[RocketCore.scala:381:40, :382:65, :383:17] wire _id_illegal_insn_T_10 = ~id_ctrl_vec; // @[RocketCore.scala:321:21, :384:73] wire _id_illegal_insn_T_11 = io_fpu_illegal_rm_0 & _id_illegal_insn_T_10; // @[RocketCore.scala:153:7, :384:{70,73}] wire _id_illegal_insn_T_12 = _csr_io_decode_0_fp_illegal \| _id_illegal_insn_T_11; // @[RocketCore.scala:341:19, :384:{48,70}] wire _id_illegal_insn_T_13 = id_ctrl_fp & _id_illegal_insn_T_12; // @[RocketCore.scala:321:21, :384:{16,48}] wire _id_illegal_insn_T_14 = _id_illegal_insn_T_9 \| _id_illegal_insn_T_13; // @[RocketCore.scala:382:65, :383:48, :384:16] wire _id_illegal_insn_T_15 = _csr_io_decode_0_vector_illegal \| _csr_io_vector_vconfig_vtype_vill; // @[RocketCore.scala:341:19, :385:55] wire _id_illegal_insn_T_16 = id_ctrl_vec & _id_illegal_insn_T_15; // @[RocketCore.scala:321:21, :385:{19,55}] wire _id_illegal_insn_T_17 = _id_illegal_insn_T_14 \| _id_illegal_insn_T_16; // @[RocketCore.scala:383:48, :384:88, :385:19] wire _id_illegal_insn_T_18 = _csr_io_status_isa[3]; // @[RocketCore.scala:341:19, :386:37] wire _id_illegal_insn_T_19 = ~_id_illegal_insn_T_18; // @[RocketCore.scala:386:{19,37}] wire _id_illegal_insn_T_20 = id_ctrl_dp & _id_illegal_insn_T_19; // @[RocketCore.scala:321:21, :386:{16,19}] wire _id_illegal_insn_T_21 = _id_illegal_insn_T_17 \| _id_illegal_insn_T_20; // @[RocketCore.scala:384:88, :385:118, :386:16] wire _id_illegal_insn_T_22 = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51] wire _mem_npc_misaligned_T = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51, :623:46] wire _id_illegal_insn_T_23 = ~_id_illegal_insn_T_22; // @[RocketCore.scala:387:{33,51}] wire _id_illegal_insn_T_24 = _ibuf_io_inst_0_bits_rvc & _id_illegal_insn_T_23; // @[RocketCore.scala:311:20, :387:{30,33}] wire _id_illegal_insn_T_25 = _id_illegal_insn_T_21 \| _id_illegal_insn_T_24; // @[RocketCore.scala:385:118, :386:47, :387:30] wire _id_illegal_insn_T_27 = _id_illegal_insn_T_25; // @[RocketCore.scala:386:47, :387:61] wire _id_illegal_insn_T_29 = _id_illegal_insn_T_27; // @[RocketCore.scala:387:61, :388:39] wire _id_illegal_insn_T_31 = _id_illegal_insn_T_29; // @[RocketCore.scala:388:39, :389:39] wire _id_illegal_insn_T_33 = _id_illegal_insn_T_31 \| _id_illegal_insn_T_32; // @[RocketCore.scala:389:39, :390:37, :391:18] wire _id_illegal_insn_T_34 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :392:52] wire _id_illegal_insn_T_35 = _id_illegal_insn_T_34 & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :392:{52,64}] wire _id_illegal_insn_T_36 = _csr_io_decode_0_read_illegal \| _id_illegal_insn_T_35; // @[RocketCore.scala:341:19, :392:{49,64}] wire _id_illegal_insn_T_37 = id_csr_en & _id_illegal_insn_T_36; // @[package.scala:81:59] wire _id_illegal_insn_T_38 = _id_illegal_insn_T_33 \| _id_illegal_insn_T_37; // @[RocketCore.scala:390:37, :391:51, :392:15] wire _id_illegal_insn_T_39 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5] wire _id_illegal_insn_T_40 = id_system_insn & _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19, :343:36, :393:50] wire _id_illegal_insn_T_41 = _id_illegal_insn_T_39 & _id_illegal_insn_T_40; // @[RocketCore.scala:393:{5,31,50}] wire id_illegal_insn = _id_illegal_insn_T_38 \| _id_illegal_insn_T_41; // @[RocketCore.scala:391:51, :392:99, :393:31] wire _id_virtual_insn_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :395:22] wire _id_virtual_insn_T_1 = _id_virtual_insn_T & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :395:{22,34}] wire _id_virtual_insn_T_2 = ~_id_virtual_insn_T_1; // @[RocketCore.scala:395:{20,34}] wire _id_virtual_insn_T_3 = id_csr_en & _id_virtual_insn_T_2; // @[package.scala:81:59] wire _id_virtual_insn_T_4 = _id_virtual_insn_T_3 & _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19, :395:{17,69}] wire _id_virtual_insn_T_5 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5, :396:7] wire _id_virtual_insn_T_6 = _id_virtual_insn_T_5 & id_system_insn; // @[RocketCore.scala:343:36, :396:{7,33}] wire _id_virtual_insn_T_7 = _id_virtual_insn_T_6 & _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19, :396:{33,51}] wire _id_virtual_insn_T_8 = _id_virtual_insn_T_4 \| _id_virtual_insn_T_7; // @[RocketCore.scala:395:{69,113}, :396:51] wire id_virtual_insn = id_ctrl_legal & _id_virtual_insn_T_8; // @[RocketCore.scala:321:21, :394:39, :395:113] wire id_amo_aq = _ibuf_io_inst_0_bits_inst_bits[26]; // @[RocketCore.scala:311:20, :398:29] wire id_amo_rl = _ibuf_io_inst_0_bits_inst_bits[25]; // @[RocketCore.scala:311:20, :399:29] wire [3:0] id_fence_pred = _ibuf_io_inst_0_bits_inst_bits[27:24]; // @[RocketCore.scala:311:20, :400:33] wire [3:0] id_fence_succ = _ibuf_io_inst_0_bits_inst_bits[23:20]; // @[RocketCore.scala:311:20, :401:33] wire _id_fence_next_T = id_ctrl_amo & id_amo_aq; // @[RocketCore.scala:321:21, :398:29, :402:52] wire id_fence_next = id_ctrl_fence \| _id_fence_next_T; // @[RocketCore.scala:321:21, :402:{37,52}] wire _id_mem_busy_T = ~io_dmem_ordered_0; // @[RocketCore.scala:153:7, :403:21] wire id_mem_busy = _id_mem_busy_T \| io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :403:{21,38}] wire _id_rocc_busy_T = ex_reg_valid & ex_ctrl_rocc; // @[RocketCore.scala:243:20, :248:35, :406:35] wire _id_rocc_busy_T_1 = _id_rocc_busy_T; // @[RocketCore.scala:406:{19,35}] wire _id_rocc_busy_T_2 = mem_reg_valid & mem_ctrl_rocc; // @[RocketCore.scala:244:21, :265:36, :407:20] wire _id_rocc_busy_T_3 = _id_rocc_busy_T_1 \| _id_rocc_busy_T_2; // @[RocketCore.scala:406:{19,51}, :407:20] wire _GEN_32 = wb_reg_valid & wb_ctrl_rocc; // @[RocketCore.scala:245:20, :288:35, :407:53] wire _id_rocc_busy_T_4; // @[RocketCore.scala:407:53] assign _id_rocc_busy_T_4 = _GEN_32; // @[RocketCore.scala:407:53] wire _replay_wb_rocc_T; // @[RocketCore.scala:758:37] assign _replay_wb_rocc_T = _GEN_32; // @[RocketCore.scala:407:53, :758:37] wire _io_rocc_cmd_valid_T; // @[RocketCore.scala:1156:37] assign _io_rocc_cmd_valid_T = _GEN_32; // @[RocketCore.scala:407:53, :1156:37] wire _id_rocc_busy_T_5 = _id_rocc_busy_T_3 \| _id_rocc_busy_T_4; // @[RocketCore.scala:406:51, :407:{37,53}] wire _id_csr_rocc_write_T_1 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :408:103] wire _id_do_fence_T_2 = id_vec_busy & id_ctrl_fence; // @[RocketCore.scala:321:21, :409:55, :411:17] wire _id_do_fence_T_3 = _id_do_fence_T_2; // @[RocketCore.scala:410:86, :411:17] wire _id_do_fence_T_4 = id_ctrl_amo & id_amo_rl; // @[RocketCore.scala:321:21, :399:29, :412:33] wire _id_do_fence_T_5 = _id_do_fence_T_4 \| id_ctrl_fence_i; // @[RocketCore.scala:321:21, :412:{33,46}] wire _id_do_fence_T_6 = id_ctrl_mem \| id_ctrl_rocc; // @[RocketCore.scala:321:21, :412:97] wire _id_do_fence_T_7 = id_reg_fence & _id_do_fence_T_6; // @[RocketCore.scala:333:29, :412:{81,97}] wire _id_do_fence_T_8 = _id_do_fence_T_5 \| _id_do_fence_T_7; // @[RocketCore.scala:412:{46,65,81}] wire _id_do_fence_T_9 = id_mem_busy & _id_do_fence_T_8; // @[RocketCore.scala:403:38, :412:{17,65}] wire _id_do_fence_T_10 = _id_do_fence_T_3 \| _id_do_fence_T_9; // @[RocketCore.scala:410:86, :411:34, :412:17] wire id_do_fence = _id_do_fence_T_10; // @[RocketCore.scala:410:32, :411:34] wire [38:0] _mem_npc_T_1 = mem_reg_wdata[38:0]; // @[RocketCore.scala:282:26, :418:13, :1295:16] wire id_xcpt = _csr_io_interrupt \| _bpu_io_debug_if \| _bpu_io_xcpt_if \| _ibuf_io_inst_0_bits_xcpt0_pf_inst \| _ibuf_io_inst_0_bits_xcpt0_gf_inst \| _ibuf_io_inst_0_bits_xcpt0_ae_inst \| _ibuf_io_inst_0_bits_xcpt1_pf_inst \| _ibuf_io_inst_0_bits_xcpt1_gf_inst \| _ibuf_io_inst_0_bits_xcpt1_ae_inst \| id_virtual_insn \| id_illegal_insn; // @[RocketCore.scala:311:20, :341:19, :392:99, :394:39, :414:19, :1278:{14,35}] wire [63:0] id_cause = _csr_io_interrupt ? _csr_io_interrupt_cause : {59'h0, _bpu_io_debug_if ? 5'hE : _bpu_io_xcpt_if ? 5'h3 : _ibuf_io_inst_0_bits_xcpt0_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt0_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt0_ae_inst ? 5'h1 : _ibuf_io_inst_0_bits_xcpt1_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt1_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt1_ae_inst ? 5'h1 : id_virtual_insn ? 5'h16 : 5'h2}; // @[Mux.scala:50:70] wire [4:0] _ex_waddr_T = ex_reg_inst[11:7]; // @[RocketCore.scala:259:24, :453:29] wire [4:0] _ex_avl_T_2 = ex_reg_inst[11:7]; // @[RocketCore.scala:259:24, :453:29, :493:24] wire [4:0] ex_waddr = _ex_waddr_T; // @[RocketCore.scala:453:{29,36}] wire [4:0] _mem_waddr_T = mem_reg_inst[11:7]; // @[RocketCore.scala:278:25, :454:31] wire [4:0] mem_waddr = _mem_waddr_T; // @[RocketCore.scala:454:{31,38}] wire [4:0] _wb_waddr_T = wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :455:29] wire [4:0] wb_waddr = _wb_waddr_T; // @[RocketCore.scala:455:{29,36}] wire [4:0] coreMonitorBundle_wrdst = wb_waddr; // @[RocketCore.scala:455:36, :1186:31] wire bypass_sources_1_1 = ex_reg_valid & ex_ctrl_wxd; // @[RocketCore.scala:243:20, :248:35, :458:19] wire _GEN_33 = mem_reg_valid & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :265:36, :459:20] wire _bypass_sources_T; // @[RocketCore.scala:459:20] assign _bypass_sources_T = _GEN_33; // @[RocketCore.scala:459:20] wire bypass_sources_3_1; // @[RocketCore.scala:460:20] assign bypass_sources_3_1 = _GEN_33; // @[RocketCore.scala:459:20, :460:20] wire _dcache_kill_mem_T; // @[RocketCore.scala:695:39] assign _dcache_kill_mem_T = _GEN_33; // @[RocketCore.scala:459:20, :695:39] wire _bypass_sources_T_1 = ~mem_ctrl_mem; // @[RocketCore.scala:244:21, :459:39] wire bypass_sources_2_1 = _bypass_sources_T & _bypass_sources_T_1; // @[RocketCore.scala:459:{20,36,39}] wire _id_bypass_src_T = ~(\|id_raddr1); // @[RocketCore.scala:326:72, :461:82, :1326:41] wire id_bypass_src_0_0 = _id_bypass_src_T; // @[RocketCore.scala:461:{74,82}] wire _GEN_34 = ex_waddr == id_raddr1; // @[RocketCore.scala:326:72, :453:36, :461:82] wire _id_bypass_src_T_1; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_1 = _GEN_34; // @[RocketCore.scala:461:82] wire _data_hazard_ex_T; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T = _GEN_34; // @[RocketCore.scala:461:82, :989:70] wire _fp_data_hazard_ex_T_1; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_1 = _GEN_34; // @[RocketCore.scala:461:82, :990:90] wire id_bypass_src_0_1 = bypass_sources_1_1 & _id_bypass_src_T_1; // @[RocketCore.scala:458:19, :461:{74,82}] wire _GEN_35 = mem_waddr == id_raddr1; // @[RocketCore.scala:326:72, :454:38, :461:82] wire _id_bypass_src_T_2; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_2 = _GEN_35; // @[RocketCore.scala:461:82] wire _id_bypass_src_T_3; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_3 = _GEN_35; // @[RocketCore.scala:461:82] wire _data_hazard_mem_T; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T = _GEN_35; // @[RocketCore.scala:461:82, :998:72] wire _fp_data_hazard_mem_T_1; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_1 = _GEN_35; // @[RocketCore.scala:461:82, :999:92] wire id_bypass_src_0_2 = bypass_sources_2_1 & _id_bypass_src_T_2; // @[RocketCore.scala:459:36, :461:{74,82}] wire id_bypass_src_0_3 = bypass_sources_3_1 & _id_bypass_src_T_3; // @[RocketCore.scala:460:20, :461:{74,82}] wire _id_bypass_src_T_4 = ~(\|id_raddr2); // @[RocketCore.scala:326:72, :461:82, :1326:41] wire id_bypass_src_1_0 = _id_bypass_src_T_4; // @[RocketCore.scala:461:{74,82}] wire _GEN_36 = ex_waddr == id_raddr2; // @[RocketCore.scala:326:72, :453:36, :461:82] wire _id_bypass_src_T_5; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_5 = _GEN_36; // @[RocketCore.scala:461:82] wire _data_hazard_ex_T_2; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T_2 = _GEN_36; // @[RocketCore.scala:461:82, :989:70] wire _fp_data_hazard_ex_T_3; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_3 = _GEN_36; // @[RocketCore.scala:461:82, :990:90] wire id_bypass_src_1_1 = bypass_sources_1_1 & _id_bypass_src_T_5; // @[RocketCore.scala:458:19, :461:{74,82}] wire _GEN_37 = mem_waddr == id_raddr2; // @[RocketCore.scala:326:72, :454:38, :461:82] wire _id_bypass_src_T_6; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_6 = _GEN_37; // @[RocketCore.scala:461:82] wire _id_bypass_src_T_7; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_7 = _GEN_37; // @[RocketCore.scala:461:82] wire _data_hazard_mem_T_2; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T_2 = _GEN_37; // @[RocketCore.scala:461:82, :998:72] wire _fp_data_hazard_mem_T_3; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_3 = _GEN_37; // @[RocketCore.scala:461:82, :999:92] wire id_bypass_src_1_2 = bypass_sources_2_1 & _id_bypass_src_T_6; // @[RocketCore.scala:459:36, :461:{74,82}] wire id_bypass_src_1_3 = bypass_sources_3_1 & _id_bypass_src_T_7; // @[RocketCore.scala:460:20, :461:{74,82}] reg ex_reg_rs_bypass_0; // @[RocketCore.scala:465:29] reg ex_reg_rs_bypass_1; // @[RocketCore.scala:465:29] reg [1:0] ex_reg_rs_lsb_0; // @[RocketCore.scala:466:26] reg [1:0] ex_reg_rs_lsb_1; // @[RocketCore.scala:466:26] reg [61:0] ex_reg_rs_msb_0; // @[RocketCore.scala:467:26] reg [61:0] ex_reg_rs_msb_1; // @[RocketCore.scala:467:26] wire _ex_rs_T = ex_reg_rs_lsb_0 == 2'h1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_1 = _ex_rs_T ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}] wire _ex_rs_T_2 = ex_reg_rs_lsb_0 == 2'h2; // @[package.scala:39:86] wire [63:0] _ex_rs_T_3 = _ex_rs_T_2 ? wb_reg_wdata : _ex_rs_T_1; // @[package.scala:39:{76,86}] wire _ex_rs_T_4 = &ex_reg_rs_lsb_0; // @[package.scala:39:86] wire [63:0] _ex_rs_T_5 = _ex_rs_T_4 ? dcache_bypass_data : _ex_rs_T_3; // @[package.scala:39:{76,86}] wire [63:0] _ex_rs_T_6 = {ex_reg_rs_msb_0, ex_reg_rs_lsb_0}; // @[RocketCore.scala:466:26, :467:26, :469:69] assign ex_rs_0 = ex_reg_rs_bypass_0 ? _ex_rs_T_5 : _ex_rs_T_6; // @[package.scala:39:76] assign io_fpu_fromint_data_0 = ex_rs_0; // @[RocketCore.scala:153:7, :469:14] assign io_vector_ex_rs1_0 = ex_rs_0; // @[RocketCore.scala:153:7, :469:14] wire [63:0] _ex_op1_T = ex_rs_0; // @[RocketCore.scala:469:14, :473:24] wire _ex_rs_T_7 = ex_reg_rs_lsb_1 == 2'h1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_8 = _ex_rs_T_7 ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}] wire _ex_rs_T_9 = ex_reg_rs_lsb_1 == 2'h2; // @[package.scala:39:86] wire [63:0] _ex_rs_T_10 = _ex_rs_T_9 ? wb_reg_wdata : _ex_rs_T_8; // @[package.scala:39:{76,86}] wire _ex_rs_T_11 = &ex_reg_rs_lsb_1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_12 = _ex_rs_T_11 ? dcache_bypass_data : _ex_rs_T_10; // @[package.scala:39:{76,86}] wire [63:0] _ex_rs_T_13 = {ex_reg_rs_msb_1, ex_reg_rs_lsb_1}; // @[RocketCore.scala:466:26, :467:26, :469:69] assign ex_rs_1 = ex_reg_rs_bypass_1 ? _ex_rs_T_12 : _ex_rs_T_13; // @[package.scala:39:76] assign io_vector_ex_rs2_0 = ex_rs_1; // @[RocketCore.scala:153:7, :469:14] wire [63:0] _ex_op2_T = ex_rs_1; // @[RocketCore.scala:469:14, :479:24] wire [63:0] mem_reg_rs2_dat_padded = ex_rs_1; // @[RocketCore.scala:469:14] wire _GEN_38 = ex_ctrl_sel_imm == 3'h5; // @[RocketCore.scala:243:20, :1341:24] wire _ex_imm_sign_T; // @[RocketCore.scala:1341:24] assign _ex_imm_sign_T = _GEN_38; // @[RocketCore.scala:1341:24] wire _ex_imm_b11_T_1; // @[RocketCore.scala:1344:40] assign _ex_imm_b11_T_1 = _GEN_38; // @[RocketCore.scala:1341:24, :1344:40] wire _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:42] assign _ex_imm_b10_5_T_1 = _GEN_38; // @[RocketCore.scala:1341:24, :1347:42] wire _ex_imm_b4_1_T_5; // @[RocketCore.scala:1350:24] assign _ex_imm_b4_1_T_5 = _GEN_38; // @[RocketCore.scala:1341:24, :1350:24] wire _ex_imm_b0_T_4; // @[RocketCore.scala:1353:22] assign _ex_imm_b0_T_4 = _GEN_38; // @[RocketCore.scala:1341:24, :1353:22] wire _ex_imm_sign_T_1 = ex_reg_inst[31]; // @[RocketCore.scala:259:24, :1341:44] wire _ex_new_vtype_T_3 = ex_reg_inst[31]; // @[RocketCore.scala:259:24, :490:19, :1341:44] wire _ex_imm_sign_T_2 = _ex_imm_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire ex_imm_sign = ~_ex_imm_sign_T & _ex_imm_sign_T_2; // @[RocketCore.scala:1341:{19,24,49}] wire ex_imm_hi_hi_hi = ex_imm_sign; // @[RocketCore.scala:1341:19, :1355:8] wire _GEN_39 = ex_ctrl_sel_imm == 3'h2; // @[RocketCore.scala:243:20, :1342:26] wire _ex_imm_b30_20_T; // @[RocketCore.scala:1342:26] assign _ex_imm_b30_20_T = _GEN_39; // @[RocketCore.scala:1342:26] wire _ex_imm_b11_T; // @[RocketCore.scala:1344:23] assign _ex_imm_b11_T = _GEN_39; // @[RocketCore.scala:1342:26, :1344:23] wire _ex_imm_b10_5_T; // @[RocketCore.scala:1347:25] assign _ex_imm_b10_5_T = _GEN_39; // @[RocketCore.scala:1342:26, :1347:25] wire _ex_imm_b4_1_T; // @[RocketCore.scala:1348:24] assign _ex_imm_b4_1_T = _GEN_39; // @[RocketCore.scala:1342:26, :1348:24] wire [10:0] _ex_imm_b30_20_T_1 = ex_reg_inst[30:20]; // @[RocketCore.scala:259:24, :1342:41] wire [10:0] _ex_new_vtype_T_5 = ex_reg_inst[30:20]; // @[RocketCore.scala:259:24, :490:45, :1342:41] wire [10:0] _ex_imm_b30_20_T_2 = _ex_imm_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] ex_imm_b30_20 = _ex_imm_b30_20_T ? _ex_imm_b30_20_T_2 : {11{ex_imm_sign}}; // @[RocketCore.scala:1341:19, :1342:{21,26,49}] wire [10:0] ex_imm_hi_hi_lo = ex_imm_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire _ex_imm_b19_12_T = ex_ctrl_sel_imm != 3'h2; // @[RocketCore.scala:243:20, :1343:26] wire _ex_imm_b19_12_T_1 = ex_ctrl_sel_imm != 3'h3; // @[RocketCore.scala:243:20, :1343:43] wire _ex_imm_b19_12_T_2 = _ex_imm_b19_12_T & _ex_imm_b19_12_T_1; // @[RocketCore.scala:1343:{26,36,43}] wire [7:0] _ex_imm_b19_12_T_3 = ex_reg_inst[19:12]; // @[RocketCore.scala:259:24, :1343:65] wire [7:0] _ex_imm_b19_12_T_4 = _ex_imm_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] ex_imm_b19_12 = _ex_imm_b19_12_T_2 ? {8{ex_imm_sign}} : _ex_imm_b19_12_T_4; // @[RocketCore.scala:1341:19, :1343:{21,36,73}] wire [7:0] ex_imm_hi_lo_hi = ex_imm_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _ex_imm_b11_T_2 = _ex_imm_b11_T \| _ex_imm_b11_T_1; // @[RocketCore.scala:1344:{23,33,40}] wire _ex_imm_b11_T_3 = ex_ctrl_sel_imm == 3'h3; // @[RocketCore.scala:243:20, :1345:23] wire _ex_imm_b11_T_4 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39] wire _ex_imm_b0_T_3 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39, :1352:37] wire _io_dmem_req_bits_signed_T = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1136:58, :1345:39] wire _ex_imm_b11_T_5 = _ex_imm_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _GEN_40 = ex_ctrl_sel_imm == 3'h1; // @[RocketCore.scala:243:20, :1346:23] wire _ex_imm_b11_T_6; // @[RocketCore.scala:1346:23] assign _ex_imm_b11_T_6 = _GEN_40; // @[RocketCore.scala:1346:23] wire _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:41] assign _ex_imm_b4_1_T_2 = _GEN_40; // @[RocketCore.scala:1346:23, :1349:41] wire _ex_imm_b11_T_7 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39] wire _ex_imm_b0_T_1 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39, :1351:37] wire _ex_imm_b11_T_8 = _ex_imm_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _ex_imm_b11_T_9 = _ex_imm_b11_T_6 ? _ex_imm_b11_T_8 : ex_imm_sign; // @[RocketCore.scala:1341:19, :1346:{18,23,43}] wire _ex_imm_b11_T_10 = _ex_imm_b11_T_3 ? _ex_imm_b11_T_5 : _ex_imm_b11_T_9; // @[RocketCore.scala:1345:{18,23,44}, :1346:18] wire ex_imm_b11 = ~_ex_imm_b11_T_2 & _ex_imm_b11_T_10; // @[RocketCore.scala:1344:{18,33}, :1345:18] wire ex_imm_hi_lo_lo = ex_imm_b11; // @[RocketCore.scala:1344:18, :1355:8] wire _ex_imm_b10_5_T_2 = _ex_imm_b10_5_T \| _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:{25,35,42}] wire [5:0] _ex_imm_b10_5_T_3 = ex_reg_inst[30:25]; // @[RocketCore.scala:259:24, :1347:62] wire [5:0] ex_imm_b10_5 = _ex_imm_b10_5_T_2 ? 6'h0 : _ex_imm_b10_5_T_3; // @[RocketCore.scala:1347:{20,35,62}] wire _GEN_41 = ex_ctrl_sel_imm == 3'h0; // @[RocketCore.scala:243:20, :1349:24] wire _ex_imm_b4_1_T_1; // @[RocketCore.scala:1349:24] assign _ex_imm_b4_1_T_1 = _GEN_41; // @[RocketCore.scala:1349:24] wire _ex_imm_b0_T; // @[RocketCore.scala:1351:22] assign _ex_imm_b0_T = _GEN_41; // @[RocketCore.scala:1349:24, :1351:22] wire _ex_imm_b4_1_T_3 = _ex_imm_b4_1_T_1 \| _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:{24,34,41}] wire [3:0] _ex_imm_b4_1_T_4 = ex_reg_inst[11:8]; // @[RocketCore.scala:259:24, :1349:57] wire [3:0] _ex_imm_b4_1_T_6 = ex_reg_inst[19:16]; // @[RocketCore.scala:259:24, :1350:39] wire [3:0] _ex_imm_b4_1_T_7 = ex_reg_inst[24:21]; // @[RocketCore.scala:259:24, :1350:52] wire [3:0] _ex_imm_b4_1_T_8 = _ex_imm_b4_1_T_5 ? _ex_imm_b4_1_T_6 : _ex_imm_b4_1_T_7; // @[RocketCore.scala:1350:{19,24,39,52}] wire [3:0] _ex_imm_b4_1_T_9 = _ex_imm_b4_1_T_3 ? _ex_imm_b4_1_T_4 : _ex_imm_b4_1_T_8; // @[RocketCore.scala:1349:{19,34,57}, :1350:19] wire [3:0] ex_imm_b4_1 = _ex_imm_b4_1_T ? 4'h0 : _ex_imm_b4_1_T_9; // @[RocketCore.scala:1348:{19,24}, :1349:19] wire _ex_imm_b0_T_2 = ex_ctrl_sel_imm == 3'h4; // @[RocketCore.scala:243:20, :1352:22] wire _ex_imm_b0_T_5 = ex_reg_inst[15]; // @[RocketCore.scala:259:24, :1353:37] wire _ex_imm_b0_T_6 = _ex_imm_b0_T_4 & _ex_imm_b0_T_5; // @[RocketCore.scala:1353:{17,22,37}] wire _ex_imm_b0_T_7 = _ex_imm_b0_T_2 ? _ex_imm_b0_T_3 : _ex_imm_b0_T_6; // @[RocketCore.scala:1352:{17,22,37}, :1353:17] wire ex_imm_b0 = _ex_imm_b0_T ? _ex_imm_b0_T_1 : _ex_imm_b0_T_7; // @[RocketCore.scala:1351:{17,22,37}, :1352:17] wire [9:0] ex_imm_lo_hi = {ex_imm_b10_5, ex_imm_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] ex_imm_lo = {ex_imm_lo_hi, ex_imm_b0}; // @[RocketCore.scala:1351:17, :1355:8] wire [8:0] ex_imm_hi_lo = {ex_imm_hi_lo_hi, ex_imm_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] ex_imm_hi_hi = {ex_imm_hi_hi_hi, ex_imm_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] ex_imm_hi = {ex_imm_hi_hi, ex_imm_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _ex_imm_T = {ex_imm_hi, ex_imm_lo}; // @[RocketCore.scala:1355:8] wire [31:0] ex_imm = _ex_imm_T; // @[RocketCore.scala:1355:{8,53}] wire _ex_rs1shl_T = ex_reg_inst[3]; // @[RocketCore.scala:259:24, :471:34] wire [31:0] _ex_rs1shl_T_1 = ex_rs_0[31:0]; // @[RocketCore.scala:469:14, :471:47] wire [63:0] _ex_rs1shl_T_2 = _ex_rs1shl_T ? {32'h0, _ex_rs1shl_T_1} : ex_rs_0; // @[RocketCore.scala:469:14, :471:{22,34,47}] wire [1:0] _ex_rs1shl_T_3 = ex_reg_inst[14:13]; // @[RocketCore.scala:259:24, :471:79] wire [66:0] ex_rs1shl = {3'h0, _ex_rs1shl_T_2} << _ex_rs1shl_T_3; // @[RocketCore.scala:471:{22,65,79}] wire [66:0] _ex_op1_T_2 = ex_rs1shl; // @[RocketCore.scala:471:65, :475:54] wire _ex_op1_T_3 = ex_ctrl_sel_alu1 == 2'h1; // @[RocketCore.scala:243:20, :472:48] wire [63:0] _ex_op1_T_4 = _ex_op1_T_3 ? _ex_op1_T : 64'h0; // @[RocketCore.scala:472:48, :473:24] wire _ex_op1_T_5 = ex_ctrl_sel_alu1 == 2'h2; // @[RocketCore.scala:243:20, :472:48] wire [63:0] _ex_op1_T_6 = _ex_op1_T_5 ? {{24{_ex_op1_T_1[39]}}, _ex_op1_T_1} : _ex_op1_T_4; // @[RocketCore.scala:472:48, :474:24] wire _ex_op1_T_7 = &ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20, :472:48] wire [66:0] ex_op1 = _ex_op1_T_7 ? _ex_op1_T_2 : {{3{_ex_op1_T_6[63]}}, _ex_op1_T_6}; // @[RocketCore.scala:472:48, :475:54] wire [66:0] _alu_io_in1_T = ex_op1; // @[RocketCore.scala:472:48, :508:24] wire _ex_op2_oh_T = ex_ctrl_sel_alu2[0]; // @[RocketCore.scala:243:20, :477:48] wire [11:0] _ex_op2_oh_T_1 = ex_reg_inst[31:20]; // @[RocketCore.scala:259:24, :477:66] wire [63:0] _ex_op2_oh_T_2 = _ex_op2_oh_T ? {52'h0, _ex_op2_oh_T_1} : ex_rs_1; // @[RocketCore.scala:469:14, :477:{31,48,66}] wire [5:0] _ex_op2_oh_T_3 = _ex_op2_oh_T_2[5:0]; // @[RocketCore.scala:477:{31,90}] wire [63:0] _ex_op2_oh_T_4 = 64'h1 << _ex_op2_oh_T_3; // @[OneHot.scala:58:35] wire [63:0] ex_op2_oh = _ex_op2_oh_T_4; // @[OneHot.scala:58:35] wire [3:0] _ex_op2_T_1 = ex_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:249:35, :481:19] wire _ex_op2_T_2 = ex_ctrl_sel_alu2 == 3'h2; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_3 = _ex_op2_T_2 ? _ex_op2_T : 64'h0; // @[RocketCore.scala:478:48, :479:24] wire _ex_op2_T_4 = ex_ctrl_sel_alu2 == 3'h3; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_5 = _ex_op2_T_4 ? {{32{ex_imm[31]}}, ex_imm} : _ex_op2_T_3; // @[RocketCore.scala:478:48, :1355:53] wire _ex_op2_T_6 = ex_ctrl_sel_alu2 == 3'h1; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_7 = _ex_op2_T_6 ? {{60{_ex_op2_T_1[3]}}, _ex_op2_T_1} : _ex_op2_T_5; // @[RocketCore.scala:478:48, :481:19] wire _ex_op2_T_8 = ex_ctrl_sel_alu2 == 3'h4; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_9 = _ex_op2_T_8 ? ex_op2_oh : _ex_op2_T_7; // @[RocketCore.scala:477:112, :478:48] wire _ex_op2_T_10 = ex_ctrl_sel_alu2 == 3'h5; // @[RocketCore.scala:243:20, :478:48] wire [63:0] ex_op2 = _ex_op2_T_10 ? ex_op2_oh : _ex_op2_T_9; // @[RocketCore.scala:477:112, :478:48] wire [63:0] _alu_io_in2_T = ex_op2; // @[RocketCore.scala:478:48, :507:24] wire [1:0] _ex_new_vtype_T = ex_reg_inst[31:30]; // @[RocketCore.scala:259:24, :489:18] wire _ex_new_vtype_T_1 = &_ex_new_vtype_T; // @[RocketCore.scala:489:{18,26}] wire [9:0] _ex_new_vtype_T_2 = ex_reg_inst[29:20]; // @[RocketCore.scala:259:24, :489:45] wire _ex_new_vtype_T_4 = ~_ex_new_vtype_T_3; // @[RocketCore.scala:490:{7,19}] wire [63:0] _ex_new_vtype_T_6 = _ex_new_vtype_T_4 ? {53'h0, _ex_new_vtype_T_5} : ex_rs_1; // @[Mux.scala:126:16] wire [63:0] _ex_new_vtype_T_7 = _ex_new_vtype_T_1 ? {54'h0, _ex_new_vtype_T_2} : _ex_new_vtype_T_6; // @[Mux.scala:126:16] wire [63:0] _ex_new_vtype_in_WIRE = _ex_new_vtype_T_7; // @[Mux.scala:126:16] wire ex_new_vtype_vill_0; // @[CSR.scala:330:80] wire ex_new_vl_isZero = ex_new_vtype_vill; // @[CSR.scala:328:27, :372:23] wire ex_new_vconfig_vtype_vill = ex_new_vtype_vill; // @[RocketCore.scala:498:30] wire ex_new_vconfig_vtype_vma = ex_new_vtype_vma; // @[RocketCore.scala:498:30] wire ex_new_vconfig_vtype_vta = ex_new_vtype_vta; // @[RocketCore.scala:498:30] wire [2:0] ex_new_vconfig_vtype_vsew = ex_new_vtype_vsew; // @[RocketCore.scala:498:30] wire ex_new_vconfig_vtype_vlmul_sign = ex_new_vtype_vlmul_sign; // @[RocketCore.scala:498:30] wire [1:0] ex_new_vtype_vlmul_mag; // @[CSR.scala:328:27] wire [1:0] ex_new_vconfig_vtype_vlmul_mag = ex_new_vtype_vlmul_mag; // @[RocketCore.scala:498:30] wire _ex_new_vtype_in_T_6; // @[CSR.scala:329:27] wire [54:0] _ex_new_vtype_in_T_5; // @[CSR.scala:329:27] wire _ex_new_vtype_in_T_4; // @[CSR.scala:329:27] wire _ex_new_vtype_in_T_3; // @[CSR.scala:329:27] wire [2:0] _ex_new_vtype_in_T_2; // @[CSR.scala:329:27] wire _ex_new_vtype_in_T_1; // @[CSR.scala:329:27] wire [1:0] _ex_new_vtype_in_T; // @[CSR.scala:329:27] wire ex_new_vtype_in_vill; // @[CSR.scala:329:27] wire [54:0] ex_new_vtype_in_reserved; // @[CSR.scala:329:27] wire ex_new_vtype_in_vma; // @[CSR.scala:329:27] wire ex_new_vtype_in_vta; // @[CSR.scala:329:27] wire [2:0] ex_new_vtype_in_vsew; // @[CSR.scala:329:27] wire ex_new_vtype_in_vlmul_sign; // @[CSR.scala:329:27] wire [1:0] ex_new_vtype_in_vlmul_mag; // @[CSR.scala:329:27] assign _ex_new_vtype_in_T = _ex_new_vtype_in_WIRE[1:0]; // @[CSR.scala:329:27] assign ex_new_vtype_in_vlmul_mag = _ex_new_vtype_in_T; // @[CSR.scala:329:27] assign _ex_new_vtype_in_T_1 = _ex_new_vtype_in_WIRE[2]; // @[CSR.scala:329:27] assign ex_new_vtype_in_vlmul_sign = _ex_new_vtype_in_T_1; // @[CSR.scala:329:27] assign _ex_new_vtype_in_T_2 = _ex_new_vtype_in_WIRE[5:3]; // @[CSR.scala:329:27] assign ex_new_vtype_in_vsew = _ex_new_vtype_in_T_2; // @[CSR.scala:329:27] assign _ex_new_vtype_in_T_3 = _ex_new_vtype_in_WIRE[6]; // @[CSR.scala:329:27] assign ex_new_vtype_in_vta = _ex_new_vtype_in_T_3; // @[CSR.scala:329:27] assign _ex_new_vtype_in_T_4 = _ex_new_vtype_in_WIRE[7]; // @[CSR.scala:329:27] assign ex_new_vtype_in_vma = _ex_new_vtype_in_T_4; // @[CSR.scala:329:27] assign _ex_new_vtype_in_T_5 = _ex_new_vtype_in_WIRE[62:8]; // @[CSR.scala:329:27] assign ex_new_vtype_in_reserved = _ex_new_vtype_in_T_5; // @[CSR.scala:329:27] assign _ex_new_vtype_in_T_6 = _ex_new_vtype_in_WIRE[63]; // @[CSR.scala:329:27] assign ex_new_vtype_in_vill = _ex_new_vtype_in_T_6; // @[CSR.scala:329:27] wire _ex_new_vtype_vill_T = ex_new_vtype_in_vsew[2]; // @[CSR.scala:329:27, :330:31] wire _ex_new_vtype_vill_T_1 = \|ex_new_vtype_in_vlmul_mag; // @[CSR.scala:329:27, :361:59] wire [1:0] _ex_new_vtype_vill_T_2 = ~ex_new_vtype_in_vlmul_mag; // @[CSR.scala:329:27, :361:70] wire [3:0] _ex_new_vtype_vill_T_3 = 4'h3 - {1'h0, ex_new_vtype_in_vsew}; // @[CSR.scala:329:27, :361:99] wire [2:0] _ex_new_vtype_vill_T_4 = _ex_new_vtype_vill_T_3[2:0]; // @[CSR.scala:361:99] wire _ex_new_vtype_vill_T_5 = {1'h0, _ex_new_vtype_vill_T_2} < _ex_new_vtype_vill_T_4; // @[CSR.scala:361:{70,86,99}] wire _ex_new_vtype_vill_T_6 = _ex_new_vtype_vill_T_1 & _ex_new_vtype_vill_T_5; // @[CSR.scala:361:{59,67,86}] wire _ex_new_vtype_vill_T_7 = ~ex_new_vtype_in_vlmul_sign \| _ex_new_vtype_vill_T_6; // @[CSR.scala:329:27, :361:{26,67}] wire _ex_new_vtype_vill_T_8 = ~_ex_new_vtype_vill_T_7; // @[CSR.scala:330:45, :361:26] wire _ex_new_vtype_vill_T_9 = _ex_new_vtype_vill_T \| _ex_new_vtype_vill_T_8; // @[CSR.scala:330:{31,42,45}] wire _ex_new_vtype_vill_T_10 = \|ex_new_vtype_in_reserved; // @[CSR.scala:329:27, :330:72] wire _ex_new_vtype_vill_T_11 = _ex_new_vtype_vill_T_9 \| _ex_new_vtype_vill_T_10; // @[CSR.scala:330:{42,57,72}] assign ex_new_vtype_vill_0 = _ex_new_vtype_vill_T_11 \| ex_new_vtype_in_vill; // @[CSR.scala:329:27, :330:{57,80}] assign ex_new_vtype_vill = ex_new_vtype_vill_0; // @[CSR.scala:328:27, :330:80] wire _ex_new_vtype_T_8 = ~ex_new_vtype_vill_0; // @[CSR.scala:330:80, :331:11] wire _ex_new_vtype_T_9 = _ex_new_vtype_T_8; // @[CSR.scala:331:{11,17}] assign ex_new_vtype_vma = _ex_new_vtype_T_9 & ex_new_vtype_in_vma; // @[CSR.scala:328:27, :329:27, :331:{17,35}, :332:11] assign ex_new_vtype_vta = _ex_new_vtype_T_9 & ex_new_vtype_in_vta; // @[CSR.scala:328:27, :329:27, :331:{17,35}, :332:11] assign ex_new_vtype_vlmul_sign = _ex_new_vtype_T_9 & ex_new_vtype_in_vlmul_sign; // @[CSR.scala:328:27, :329:27, :331:{17,35}, :332:11] assign ex_new_vtype_vlmul_mag = _ex_new_vtype_T_9 ? ex_new_vtype_in_vlmul_mag : 2'h0; // @[CSR.scala:328:27, :329:27, :331:{17,35}, :332:11] wire [1:0] _ex_new_vtype_view__vsew_T = ex_new_vtype_in_vsew[1:0]; // @[CSR.scala:329:27, :333:26] assign ex_new_vtype_vsew = _ex_new_vtype_T_9 ? {1'h0, _ex_new_vtype_view__vsew_T} : 3'h0; // @[CSR.scala:328:27, :331:{17,35}, :333:{16,26}] wire [4:0] _ex_avl_T = ex_reg_inst[19:15]; // @[RocketCore.scala:259:24, :492:22] wire [4:0] _ex_avl_T_14 = ex_reg_inst[19:15]; // @[RocketCore.scala:259:24, :492:22, :496:18] wire _ex_avl_T_1 = _ex_avl_T == 5'h0; // @[RocketCore.scala:492:{22,30}] wire _ex_avl_T_3 = _ex_avl_T_2 == 5'h0; // @[RocketCore.scala:493:{24,31}] wire [1:0] _ex_avl_T_4 = ~ex_new_vtype_vlmul_mag; // @[CSR.scala:328:27, :365:71] wire [2:0] _ex_avl_T_5 = {ex_new_vtype_vlmul_sign, _ex_avl_T_4}; // @[CSR.scala:328:27, :365:{53,71}] wire [3:0] _GEN_42 = {1'h0, ex_new_vtype_vsew}; // @[CSR.scala:328:27, :365:47] wire [3:0] _ex_avl_T_6 = _GEN_42 + {1'h0, _ex_avl_T_5}; // @[CSR.scala:365:{47,53}] wire [12:0] _ex_avl_T_7 = 13'h1000 >> _ex_avl_T_6; // @[CSR.scala:365:{33,47}] wire [12:0] _ex_avl_T_11 = _ex_avl_T_7 & 13'h1FF8; // @[package.scala:174:35] wire [12:0] _ex_avl_T_12 = _ex_avl_T_3 ? _csr_io_vector_vconfig_vl : _ex_avl_T_11; // @[package.scala:174:35] wire [63:0] _ex_avl_T_13 = _ex_avl_T_1 ? {51'h0, _ex_avl_T_12} : ex_rs_0; // @[RocketCore.scala:469:14, :492:{10,30}, :493:12] wire [63:0] ex_avl = ex_ctrl_rxs1 ? _ex_avl_T_13 : {59'h0, _ex_avl_T_14}; // @[RocketCore.scala:243:20, :491:21, :492:10, :496:18] wire [63:0] _ex_new_vl_avl_lsbs_T = ex_avl; // @[RocketCore.scala:491:21] wire _ex_new_vl_atLeastMaxVLMax_T = _csr_io_vector_vconfig_vl[12]; // @[RocketCore.scala:341:19] wire _ex_new_vl_atLeastMaxVLMax_T_1 = \|(ex_avl[63:12]); // @[RocketCore.scala:491:21] wire _ex_new_vl_atLeastMaxVLMax_T_2 = _ex_new_vl_atLeastMaxVLMax_T_1; // @[CSR.scala:368:{40,84}] wire ex_new_vl_atLeastMaxVLMax = _ex_new_vl_atLeastMaxVLMax_T_2; // @[CSR.scala:368:{34,40}] wire [11:0] ex_new_vl_avl_lsbs = _ex_new_vl_avl_lsbs_T[11:0]; // @[CSR.scala:369:{23,53}] wire [1:0] _ex_new_vl_atLeastVLMax_T_3 = ~ex_new_vtype_vlmul_mag; // @[CSR.scala:328:27, :365:71, :371:106] wire [2:0] _ex_new_vl_atLeastVLMax_T_4 = {ex_new_vtype_vlmul_sign, _ex_new_vl_atLeastVLMax_T_3}; // @[CSR.scala:328:27, :371:{88,106}] wire [3:0] _ex_new_vl_atLeastVLMax_T_5 = _GEN_42 + {1'h0, _ex_new_vl_atLeastVLMax_T_4}; // @[CSR.scala:365:47, :371:{82,88}] wire [13:0] _ex_new_vl_atLeastVLMax_T_6 = $signed(-14'sh1000 >>> _ex_new_vl_atLeastVLMax_T_5); // @[CSR.scala:371:{68,82}] wire [13:0] _ex_new_vl_atLeastVLMax_T_7 = _ex_new_vl_atLeastVLMax_T_6; // @[CSR.scala:371:{68,125}] wire [13:0] _ex_new_vl_atLeastVLMax_T_11 = _ex_new_vl_atLeastVLMax_T_7 & 14'h3FF8; // @[package.scala:174:35] wire [13:0] _ex_new_vl_atLeastVLMax_T_12 = {2'h0, _ex_new_vl_atLeastVLMax_T_11[11:0] & ex_new_vl_avl_lsbs}; // @[package.scala:174:35] wire _ex_new_vl_atLeastVLMax_T_13 = \|_ex_new_vl_atLeastVLMax_T_12; // @[CSR.scala:371:{53,156}] wire ex_new_vl_atLeastVLMax = ex_new_vl_atLeastMaxVLMax \| _ex_new_vl_atLeastVLMax_T_13; // @[CSR.scala:368:34, :371:{40,156}] wire _ex_new_vl_T = ~ex_new_vl_isZero; // @[CSR.scala:372:23, :373:9] wire _ex_new_vl_T_1 = _ex_new_vl_T & ex_new_vl_atLeastVLMax; // @[CSR.scala:371:40, :373:{9,17}] wire [1:0] _ex_new_vl_T_2 = ~ex_new_vtype_vlmul_mag; // @[CSR.scala:328:27, :365:71] wire [2:0] _ex_new_vl_T_3 = {ex_new_vtype_vlmul_sign, _ex_new_vl_T_2}; // @[CSR.scala:328:27, :365:{53,71}] wire [3:0] _ex_new_vl_T_4 = _GEN_42 + {1'h0, _ex_new_vl_T_3}; // @[CSR.scala:365:{47,53}] wire [12:0] _ex_new_vl_T_5 = 13'h1000 >> _ex_new_vl_T_4; // @[CSR.scala:365:{33,47}] wire [12:0] _ex_new_vl_T_9 = _ex_new_vl_T_5 & 13'h1FF8; // @[package.scala:174:35] wire [12:0] _ex_new_vl_T_10 = _ex_new_vl_T_1 ? _ex_new_vl_T_9 : 13'h0; // @[package.scala:174:35] wire _ex_new_vl_T_11 = ~ex_new_vl_isZero; // @[CSR.scala:372:23, :373:{9,52}] wire _ex_new_vl_T_12 = ~ex_new_vl_atLeastVLMax; // @[CSR.scala:371:40, :373:63] wire _ex_new_vl_T_13 = _ex_new_vl_T_11 & _ex_new_vl_T_12; // @[CSR.scala:373:{52,60,63}] wire [11:0] _ex_new_vl_T_14 = _ex_new_vl_T_13 ? ex_new_vl_avl_lsbs : 12'h0; // @[CSR.scala:369:53, :373:{51,60}] wire [12:0] ex_new_vl = {_ex_new_vl_T_10[12], _ex_new_vl_T_10[11:0] \| _ex_new_vl_T_14}; // @[CSR.scala:373:{8,46,51}] wire [12:0] ex_new_vconfig_vl = ex_new_vl; // @[RocketCore.scala:498:30] wire _div_io_req_valid_T = ex_reg_valid & ex_ctrl_div; // @[RocketCore.scala:243:20, :248:35, :512:36] wire _ex_reg_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19] wire _ex_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20] wire _ex_reg_replay_T_1 = _ex_reg_replay_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :526:{20,29}] wire _ex_reg_replay_T_2 = _ex_reg_replay_T_1 & _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :526:{29,54}] wire _ex_reg_xcpt_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :527:18] wire _ex_reg_xcpt_T_1 = _ex_reg_xcpt_T & id_xcpt; // @[RocketCore.scala:527:{18,30}, :1278:14] wire _ex_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :528:28] wire _ex_reg_xcpt_interrupt_T_1 = _ex_reg_xcpt_interrupt_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :528:{28,37}] wire _ex_reg_xcpt_interrupt_T_2 = _ex_reg_xcpt_interrupt_T_1 & _csr_io_interrupt; // @[RocketCore.scala:341:19, :528:{37,62}] wire [1:0] hi = {_ibuf_io_inst_0_bits_xcpt1_pf_inst, _ibuf_io_inst_0_bits_xcpt1_gf_inst}; // @[RocketCore.scala:311:20, :541:22] wire [1:0] hi_1 = {_ibuf_io_inst_0_bits_xcpt0_pf_inst, _ibuf_io_inst_0_bits_xcpt0_gf_inst}; // @[RocketCore.scala:311:20, :546:40] wire _ex_reg_flush_pipe_T = id_ctrl_fence_i \| id_csr_flush; // @[RocketCore.scala:321:21, :346:37, :551:42] wire _ex_reg_hls_T_1 = id_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47] wire _ex_reg_hls_T_2 = id_ctrl_mem_cmd == 5'h1; // @[package.scala:16:47] wire _ex_reg_hls_T_3 = id_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47] wire _ex_reg_hls_T_4 = _ex_reg_hls_T_1 \| _ex_reg_hls_T_2; // @[package.scala:16:47, :81:59] wire _ex_reg_hls_T_5 = _ex_reg_hls_T_4 \| _ex_reg_hls_T_3; // @[package.scala:16:47, :81:59] wire [1:0] _ex_reg_mem_size_T_1 = _ibuf_io_inst_0_bits_inst_bits[27:26]; // @[RocketCore.scala:311:20, :554:75] wire [1:0] _ex_reg_mem_size_T_2 = _ibuf_io_inst_0_bits_inst_bits[13:12]; // @[RocketCore.scala:311:20, :554:95] wire [1:0] _ex_reg_mem_size_T_3 = _ex_reg_mem_size_T_2; // @[RocketCore.scala:554:{27,95}] wire _ex_reg_mem_size_T_4 = \|id_raddr2; // @[RocketCore.scala:326:72, :556:40, :1326:41] wire _ex_reg_mem_size_T_5 = \|id_raddr1; // @[RocketCore.scala:326:72, :556:59, :1326:41] wire [1:0] _ex_reg_mem_size_T_6 = {_ex_reg_mem_size_T_4, _ex_reg_mem_size_T_5}; // @[RocketCore.scala:556:{29,40,59}] wire _do_bypass_T = id_bypass_src_0_0 \| id_bypass_src_0_1; // @[RocketCore.scala:461:74, :568:48] wire _do_bypass_T_1 = _do_bypass_T \| id_bypass_src_0_2; // @[RocketCore.scala:461:74, :568:48] wire do_bypass = _do_bypass_T_1 \| id_bypass_src_0_3; // @[RocketCore.scala:461:74, :568:48] wire [1:0] _bypass_src_T = {1'h1, ~id_bypass_src_0_2}; // @[Mux.scala:50:70] wire [1:0] _bypass_src_T_1 = id_bypass_src_0_1 ? 2'h1 : _bypass_src_T; // @[Mux.scala:50:70] wire [1:0] bypass_src = id_bypass_src_0_0 ? 2'h0 : _bypass_src_T_1; // @[Mux.scala:50:70] wire [1:0] _ex_reg_rs_lsb_0_T = id_rs_0[1:0]; // @[RocketCore.scala:573:37, :1325:26] wire [61:0] _ex_reg_rs_msb_0_T = id_rs_0[63:2]; // @[RocketCore.scala:574:38, :1325:26] wire _do_bypass_T_2 = id_bypass_src_1_0 \| id_bypass_src_1_1; // @[RocketCore.scala:461:74, :568:48] wire _do_bypass_T_3 = _do_bypass_T_2 \| id_bypass_src_1_2; // @[RocketCore.scala:461:74, :568:48] wire do_bypass_1 = _do_bypass_T_3 \| id_bypass_src_1_3; // @[RocketCore.scala:461:74, :568:48] wire [1:0] _bypass_src_T_2 = {1'h1, ~id_bypass_src_1_2}; // @[Mux.scala:50:70] wire [1:0] _bypass_src_T_3 = id_bypass_src_1_1 ? 2'h1 : _bypass_src_T_2; // @[Mux.scala:50:70] wire [1:0] bypass_src_1 = id_bypass_src_1_0 ? 2'h0 : _bypass_src_T_3; // @[Mux.scala:50:70] wire [1:0] _ex_reg_rs_lsb_1_T = id_rs_1[1:0]; // @[RocketCore.scala:573:37, :1325:26] wire [61:0] _ex_reg_rs_msb_1_T = id_rs_1[63:2]; // @[RocketCore.scala:574:38, :1325:26] wire [15:0] _inst_T = _ibuf_io_inst_0_bits_raw[15:0]; // @[RocketCore.scala:311:20, :578:62] wire [31:0] inst = _ibuf_io_inst_0_bits_rvc ? {16'h0, _inst_T} : _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20, :578:{21,62}] wire [1:0] _ex_reg_rs_lsb_0_T_1 = inst[1:0]; // @[RocketCore.scala:578:21, :580:31] wire [29:0] _ex_reg_rs_msb_0_T_1 = inst[31:2]; // @[RocketCore.scala:578:21, :581:32] wire _ex_reg_set_vconfig_T = ~id_xcpt; // @[RocketCore.scala:591:45, :1278:14] wire _ex_reg_set_vconfig_T_1 = id_set_vconfig & _ex_reg_set_vconfig_T; // @[RocketCore.scala:347:120, :591:{42,45}] wire _ex_pc_valid_T = ex_reg_valid \| ex_reg_replay; // @[RocketCore.scala:248:35, :255:26, :595:34] wire ex_pc_valid = _ex_pc_valid_T \| ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :595:{34,51}] wire _wb_dcache_miss_T = ~io_dmem_resp_valid_0; // @[RocketCore.scala:153:7, :596:39] wire wb_dcache_miss = wb_ctrl_mem & _wb_dcache_miss_T; // @[RocketCore.scala:245:20, :596:{36,39}] wire _replay_ex_structural_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45] wire _replay_ex_structural_T_1 = ex_ctrl_mem & _replay_ex_structural_T; // @[RocketCore.scala:243:20, :597:{42,45}] wire _replay_ex_structural_T_2 = ~_div_io_req_ready; // @[RocketCore.scala:511:19, :598:45] wire _replay_ex_structural_T_3 = ex_ctrl_div & _replay_ex_structural_T_2; // @[RocketCore.scala:243:20, :598:{42,45}] wire _replay_ex_structural_T_4 = _replay_ex_structural_T_1 \| _replay_ex_structural_T_3; // @[RocketCore.scala:597:{42,64}, :598:42] wire replay_ex_structural = _replay_ex_structural_T_4; // @[RocketCore.scala:597:64, :598:63] wire replay_ex_load_use = wb_dcache_miss & ex_reg_load_use; // @[RocketCore.scala:253:35, :596:36, :600:43] wire _replay_ex_T = replay_ex_structural \| replay_ex_load_use; // @[RocketCore.scala:598:63, :600:43, :601:75] wire _replay_ex_T_1 = ex_reg_valid & _replay_ex_T; // @[RocketCore.scala:248:35, :601:{50,75}] wire replay_ex = ex_reg_replay \| _replay_ex_T_1; // @[RocketCore.scala:255:26, :601:{33,50}] wire _ctrl_killx_T = take_pc_mem_wb \| replay_ex; // @[RocketCore.scala:307:35, :601:33, :602:35] wire _ctrl_killx_T_1 = ~ex_reg_valid; // @[RocketCore.scala:248:35, :602:51] assign ctrl_killx = _ctrl_killx_T \| _ctrl_killx_T_1; // @[RocketCore.scala:602:{35,48,51}] assign io_fpu_killx_0 = ctrl_killx; // @[RocketCore.scala:153:7, :602:48] wire _GEN_43 = ex_ctrl_mem_cmd == 5'h7; // @[RocketCore.scala:243:20, :604:40] wire _ex_slow_bypass_T; // @[RocketCore.scala:604:40] assign _ex_slow_bypass_T = _GEN_43; // @[RocketCore.scala:604:40] wire _mem_reg_load_T_3; // @[package.scala:16:47] assign _mem_reg_load_T_3 = _GEN_43; // @[package.scala:16:47] wire _mem_reg_store_T_3; // @[Consts.scala:90:66] assign _mem_reg_store_T_3 = _GEN_43; // @[RocketCore.scala:604:40] wire _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_3 = _GEN_43; // @[package.scala:16:47] wire _ex_slow_bypass_T_1 = ~(ex_reg_mem_size[1]); // @[RocketCore.scala:257:28, :604:69] wire ex_slow_bypass = _ex_slow_bypass_T \| _ex_slow_bypass_T_1; // @[RocketCore.scala:604:{40,50,69}] wire _ex_sfence_T_1 = ex_ctrl_mem_cmd == 5'h14; // @[RocketCore.scala:243:20, :605:64] wire _ex_sfence_T_2 = ex_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:243:20, :605:96] wire _ex_sfence_T_3 = _ex_sfence_T_1 \| _ex_sfence_T_2; // @[RocketCore.scala:605:{64,77,96}] wire _ex_sfence_T_4 = ex_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:243:20, :605:129] wire _ex_sfence_T_5 = _ex_sfence_T_3 \| _ex_sfence_T_4; // @[RocketCore.scala:605:{77,110,129}] wire ex_sfence = _ex_sfence_T & _ex_sfence_T_5; // @[RocketCore.scala:605:{29,44,110}] wire ex_xcpt = ex_reg_xcpt_interrupt \| ex_reg_xcpt; // @[RocketCore.scala:247:35, :251:35, :608:28, :1278:14] wire _mem_pc_valid_T = mem_reg_valid \| mem_reg_replay; // @[RocketCore.scala:265:36, :269:36, :614:36] wire mem_pc_valid = _mem_pc_valid_T \| mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36, :614:{36,54}] wire _GEN_44 = mem_ctrl_branch & mem_br_taken; // @[RocketCore.scala:244:21, :284:25, :616:25] wire _mem_br_target_T_1; // @[RocketCore.scala:616:25] assign _mem_br_target_T_1 = _GEN_44; // @[RocketCore.scala:616:25] wire _mem_cfi_taken_T; // @[RocketCore.scala:626:40] assign _mem_cfi_taken_T = _GEN_44; // @[RocketCore.scala:616:25, :626:40] wire _mem_br_target_sign_T_1 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44] wire _mem_br_target_sign_T_4 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44] wire _mem_br_target_sign_T_2 = _mem_br_target_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire mem_br_target_sign = _mem_br_target_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire mem_br_target_hi_hi_hi = mem_br_target_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_br_target_b30_20_T_1 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41] wire [10:0] _mem_br_target_b30_20_T_4 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41] wire [10:0] _mem_br_target_b30_20_T_2 = _mem_br_target_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_br_target_b30_20 = {11{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_br_target_hi_hi_lo = mem_br_target_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_br_target_b19_12_T_3 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65] wire [7:0] _mem_br_target_b19_12_T_8 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65] wire [7:0] _mem_br_target_b19_12_T_4 = _mem_br_target_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_br_target_b19_12 = {8{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] mem_br_target_hi_lo_hi = mem_br_target_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_br_target_b11_T_4 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39] wire _mem_br_target_b0_T_3 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37] wire _mem_br_target_b11_T_15 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39] wire _mem_br_target_b0_T_11 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37] wire _mem_br_target_b11_T_5 = _mem_br_target_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _mem_br_target_b11_T_7 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39] wire _mem_br_target_b0_T_1 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37] wire _mem_br_target_b11_T_18 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39] wire _mem_br_target_b0_T_9 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37] wire _mem_br_target_b11_T_8 = _mem_br_target_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _mem_br_target_b11_T_9 = _mem_br_target_b11_T_8; // @[RocketCore.scala:1346:{18,43}] wire _mem_br_target_b11_T_10 = _mem_br_target_b11_T_9; // @[RocketCore.scala:1345:18, :1346:18] wire mem_br_target_b11 = _mem_br_target_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire mem_br_target_hi_lo_lo = mem_br_target_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _mem_br_target_b10_5_T_3 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62] wire [5:0] _mem_br_target_b10_5_T_7 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62] wire [5:0] mem_br_target_b10_5 = _mem_br_target_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_br_target_b4_1_T_4 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57] wire [3:0] _mem_br_target_b4_1_T_14 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57] wire [3:0] _mem_br_target_b4_1_T_9 = _mem_br_target_b4_1_T_4; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _mem_br_target_b4_1_T_6 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39] wire [3:0] _mem_br_target_b4_1_T_16 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39] wire [3:0] _mem_br_target_b4_1_T_7 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52] wire [3:0] _mem_br_target_b4_1_T_17 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52] wire [3:0] _mem_br_target_b4_1_T_8 = _mem_br_target_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] mem_br_target_b4_1 = _mem_br_target_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _mem_br_target_b0_T_5 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37] wire _mem_br_target_b0_T_13 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37] wire [9:0] mem_br_target_lo_hi = {mem_br_target_b10_5, mem_br_target_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_br_target_lo = {mem_br_target_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_br_target_hi_lo = {mem_br_target_hi_lo_hi, mem_br_target_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] mem_br_target_hi_hi = {mem_br_target_hi_hi_hi, mem_br_target_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] mem_br_target_hi = {mem_br_target_hi_hi, mem_br_target_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_2 = {mem_br_target_hi, mem_br_target_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_3 = _mem_br_target_T_2; // @[RocketCore.scala:1355:{8,53}] wire _mem_br_target_sign_T_5 = _mem_br_target_sign_T_4; // @[RocketCore.scala:1341:{44,49}] wire mem_br_target_sign_1 = _mem_br_target_sign_T_5; // @[RocketCore.scala:1341:{19,49}] wire _mem_br_target_b11_T_20 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1346:18] wire mem_br_target_hi_hi_hi_1 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_br_target_b30_20_T_5 = _mem_br_target_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_br_target_b30_20_1 = {11{mem_br_target_sign_1}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_br_target_hi_hi_lo_1 = mem_br_target_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_br_target_b19_12_T_9 = _mem_br_target_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_br_target_b19_12_1 = _mem_br_target_b19_12_T_9; // @[RocketCore.scala:1343:{21,73}] wire [7:0] mem_br_target_hi_lo_hi_1 = mem_br_target_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_br_target_b11_T_16 = _mem_br_target_b11_T_15; // @[RocketCore.scala:1345:{39,44}] wire _mem_br_target_b11_T_21 = _mem_br_target_b11_T_16; // @[RocketCore.scala:1345:{18,44}] wire _mem_br_target_b11_T_19 = _mem_br_target_b11_T_18; // @[RocketCore.scala:1346:{39,43}] wire mem_br_target_b11_1 = _mem_br_target_b11_T_21; // @[RocketCore.scala:1344:18, :1345:18] wire mem_br_target_hi_lo_lo_1 = mem_br_target_b11_1; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] mem_br_target_b10_5_1 = _mem_br_target_b10_5_T_7; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_br_target_b4_1_T_18 = _mem_br_target_b4_1_T_17; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _mem_br_target_b4_1_T_19 = _mem_br_target_b4_1_T_18; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] mem_br_target_b4_1_1 = _mem_br_target_b4_1_T_19; // @[RocketCore.scala:1348:19, :1349:19] wire [9:0] mem_br_target_lo_hi_1 = {mem_br_target_b10_5_1, mem_br_target_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_br_target_lo_1 = {mem_br_target_lo_hi_1, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_br_target_hi_lo_1 = {mem_br_target_hi_lo_hi_1, mem_br_target_hi_lo_lo_1}; // @[RocketCore.scala:1355:8] wire [11:0] mem_br_target_hi_hi_1 = {mem_br_target_hi_hi_hi_1, mem_br_target_hi_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [20:0] mem_br_target_hi_1 = {mem_br_target_hi_hi_1, mem_br_target_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_4 = {mem_br_target_hi_1, mem_br_target_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_5 = _mem_br_target_T_4; // @[RocketCore.scala:1355:{8,53}] wire [3:0] _mem_br_target_T_6 = mem_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:266:36, :618:8] wire [31:0] _mem_br_target_T_7 = mem_ctrl_jal ? _mem_br_target_T_5 : {{28{_mem_br_target_T_6[3]}}, _mem_br_target_T_6}; // @[RocketCore.scala:244:21, :617:8, :618:8, :1355:53] wire [31:0] _mem_br_target_T_8 = _mem_br_target_T_1 ? _mem_br_target_T_3 : _mem_br_target_T_7; // @[RocketCore.scala:616:{8,25}, :617:8, :1355:53] wire [40:0] _mem_br_target_T_9 = {_mem_br_target_T[39], _mem_br_target_T} + {{9{_mem_br_target_T_8[31]}}, _mem_br_target_T_8}; // @[RocketCore.scala:615:{34,41}, :616:8] wire [39:0] _mem_br_target_T_10 = _mem_br_target_T_9[39:0]; // @[RocketCore.scala:615:41] wire [39:0] mem_br_target = _mem_br_target_T_10; // @[RocketCore.scala:615:41] wire _mem_npc_T = mem_ctrl_jalr \| mem_reg_sfence; // @[RocketCore.scala:244:21, :276:27, :619:36] wire [24:0] _mem_npc_a_T = mem_reg_wdata[63:39]; // @[RocketCore.scala:282:26, :1293:17] wire [24:0] mem_npc_a = _mem_npc_a_T; // @[RocketCore.scala:1293:{17,23}] wire _mem_npc_msb_T = mem_npc_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _mem_npc_msb_T_1 = &mem_npc_a; // @[RocketCore.scala:1293:23, :1294:34] wire _mem_npc_msb_T_2 = _mem_npc_msb_T \| _mem_npc_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _mem_npc_msb_T_3 = mem_reg_wdata[39]; // @[RocketCore.scala:282:26, :1294:46] wire _mem_npc_msb_T_4 = mem_reg_wdata[38]; // @[RocketCore.scala:282:26, :1294:54] wire _mem_npc_msb_T_5 = ~_mem_npc_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire mem_npc_msb = _mem_npc_msb_T_2 ? _mem_npc_msb_T_3 : _mem_npc_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] wire [39:0] _mem_npc_T_2 = {mem_npc_msb, _mem_npc_T_1}; // @[RocketCore.scala:1294:18, :1295:{8,16}] wire [39:0] _mem_npc_T_3 = _mem_npc_T_2; // @[RocketCore.scala:619:106, :1295:8] wire [39:0] _mem_npc_T_4 = _mem_npc_T ? _mem_npc_T_3 : mem_br_target; // @[RocketCore.scala:615:41, :619:{21,36,106}] wire [39:0] _mem_npc_T_5 = _mem_npc_T_4 & 40'hFFFFFFFFFE; // @[RocketCore.scala:619:{21,129}] wire [39:0] _mem_npc_T_6 = _mem_npc_T_5; // @[RocketCore.scala:619:129] wire [39:0] mem_npc = _mem_npc_T_6; // @[RocketCore.scala:619:{129,139}] wire _mem_wrong_npc_T = mem_npc != ex_reg_pc; // @[RocketCore.scala:256:22, :619:139, :621:30] wire _mem_wrong_npc_T_1 = _ibuf_io_inst_0_valid \| io_imem_resp_valid_0; // @[RocketCore.scala:153:7, :311:20, :622:31] wire _mem_wrong_npc_T_2 = mem_npc != _ibuf_io_pc; // @[RocketCore.scala:311:20, :619:139, :622:62] wire _mem_wrong_npc_T_3 = ~_mem_wrong_npc_T_1 \| _mem_wrong_npc_T_2; // @[RocketCore.scala:622:{8,31,62}] assign mem_wrong_npc = ex_pc_valid ? _mem_wrong_npc_T : _mem_wrong_npc_T_3; // @[RocketCore.scala:595:51, :621:{8,30}, :622:8] assign io_imem_bht_update_bits_mispredict_0 = mem_wrong_npc; // @[RocketCore.scala:153:7, :621:8] wire _mem_npc_misaligned_T_1 = ~_mem_npc_misaligned_T; // @[RocketCore.scala:623:{28,46}] wire _mem_npc_misaligned_T_2 = mem_npc[1]; // @[RocketCore.scala:619:139, :623:66] wire _mem_npc_misaligned_T_3 = _mem_npc_misaligned_T_1 & _mem_npc_misaligned_T_2; // @[RocketCore.scala:623:{28,56,66}] wire _mem_npc_misaligned_T_4 = ~mem_reg_sfence; // @[RocketCore.scala:276:27, :623:73] wire mem_npc_misaligned = _mem_npc_misaligned_T_3 & _mem_npc_misaligned_T_4; // @[RocketCore.scala:623:{56,70,73}] wire _mem_int_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27] wire _mem_int_wdata_T_1 = mem_ctrl_jalr ^ mem_npc_misaligned; // @[RocketCore.scala:244:21, :623:70, :624:59] wire _mem_int_wdata_T_2 = _mem_int_wdata_T & _mem_int_wdata_T_1; // @[RocketCore.scala:624:{27,41,59}] wire [63:0] _mem_int_wdata_T_4 = _mem_int_wdata_T_2 ? {{24{mem_br_target[39]}}, mem_br_target} : _mem_int_wdata_T_3; // @[RocketCore.scala:615:41, :624:{26,41,111}] wire [63:0] mem_int_wdata = _mem_int_wdata_T_4; // @[RocketCore.scala:624:{26,119}] wire _mem_cfi_T = mem_ctrl_branch \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :625:33] assign mem_cfi = _mem_cfi_T \| mem_ctrl_jal; // @[RocketCore.scala:244:21, :625:{33,50}] assign io_imem_btb_update_bits_isValid_0 = mem_cfi; // @[RocketCore.scala:153:7, :625:50] wire _mem_cfi_taken_T_1 = _mem_cfi_taken_T \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :626:{40,57}] wire mem_cfi_taken = _mem_cfi_taken_T_1 \| mem_ctrl_jal; // @[RocketCore.scala:244:21, :626:{57,74}] wire _mem_direction_misprediction_T_1 = mem_br_taken != _mem_direction_misprediction_T; // @[RocketCore.scala:284:25, :627:{69,85}] wire mem_direction_misprediction = mem_ctrl_branch & _mem_direction_misprediction_T_1; // @[RocketCore.scala:244:21, :627:{53,69}] wire _take_pc_mem_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :629:35] wire _take_pc_mem_T_1 = mem_reg_valid & _take_pc_mem_T; // @[RocketCore.scala:265:36, :629:{32,35}] wire _take_pc_mem_T_2 = mem_wrong_npc \| mem_reg_sfence; // @[RocketCore.scala:276:27, :621:8, :629:71] assign _take_pc_mem_T_3 = _take_pc_mem_T_1 & _take_pc_mem_T_2; // @[RocketCore.scala:629:{32,49,71}] assign take_pc_mem = _take_pc_mem_T_3; // @[RocketCore.scala:285:25, :629:49] wire _mem_reg_valid_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20] wire _mem_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :632:21] wire _mem_reg_replay_T_1 = _mem_reg_replay_T & replay_ex; // @[RocketCore.scala:601:33, :632:{21,37}] wire _mem_reg_xcpt_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20, :633:19] wire _mem_reg_xcpt_T_1 = _mem_reg_xcpt_T & ex_xcpt; // @[RocketCore.scala:633:{19,31}, :1278:14] wire _mem_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :634:29] wire _mem_reg_xcpt_interrupt_T_1 = _mem_reg_xcpt_interrupt_T & ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :634:{29,45}] wire _GEN_45 = ex_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47] wire _mem_reg_load_T; // @[package.scala:16:47] assign _mem_reg_load_T = _GEN_45; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = ex_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47] wire _mem_reg_load_T_1; // @[package.scala:16:47] assign _mem_reg_load_T_1 = _GEN_46; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_1 = _GEN_46; // @[package.scala:16:47] wire _GEN_47 = ex_ctrl_mem_cmd == 5'h6; // @[package.scala:16:47] wire _mem_reg_load_T_2; // @[package.scala:16:47] assign _mem_reg_load_T_2 = _GEN_47; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_2 = _GEN_47; // @[package.scala:16:47] wire _mem_reg_load_T_4 = _mem_reg_load_T \| _mem_reg_load_T_1; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_5 = _mem_reg_load_T_4 \| _mem_reg_load_T_2; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_6 = _mem_reg_load_T_5 \| _mem_reg_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_48 = ex_ctrl_mem_cmd == 5'h4; // @[package.scala:16:47] wire _mem_reg_load_T_7; // @[package.scala:16:47] assign _mem_reg_load_T_7 = _GEN_48; // @[package.scala:16:47] wire _mem_reg_store_T_5; // @[package.scala:16:47] assign _mem_reg_store_T_5 = _GEN_48; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_7; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_7 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = ex_ctrl_mem_cmd == 5'h9; // @[package.scala:16:47] wire _mem_reg_load_T_8; // @[package.scala:16:47] assign _mem_reg_load_T_8 = _GEN_49; // @[package.scala:16:47] wire _mem_reg_store_T_6; // @[package.scala:16:47] assign _mem_reg_store_T_6 = _GEN_49; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_8 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = ex_ctrl_mem_cmd == 5'hA; // @[package.scala:16:47] wire _mem_reg_load_T_9; // @[package.scala:16:47] assign _mem_reg_load_T_9 = _GEN_50; // @[package.scala:16:47] wire _mem_reg_store_T_7; // @[package.scala:16:47] assign _mem_reg_store_T_7 = _GEN_50; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_9 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = ex_ctrl_mem_cmd == 5'hB; // @[package.scala:16:47] wire _mem_reg_load_T_10; // @[package.scala:16:47] assign _mem_reg_load_T_10 = _GEN_51; // @[package.scala:16:47] wire _mem_reg_store_T_8; // @[package.scala:16:47] assign _mem_reg_store_T_8 = _GEN_51; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_10 = _GEN_51; // @[package.scala:16:47] wire _mem_reg_load_T_11 = _mem_reg_load_T_7 \| _mem_reg_load_T_8; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_12 = _mem_reg_load_T_11 \| _mem_reg_load_T_9; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_13 = _mem_reg_load_T_12 \| _mem_reg_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_52 = ex_ctrl_mem_cmd == 5'h8; // @[package.scala:16:47] wire _mem_reg_load_T_14; // @[package.scala:16:47] assign _mem_reg_load_T_14 = _GEN_52; // @[package.scala:16:47] wire _mem_reg_store_T_12; // @[package.scala:16:47] assign _mem_reg_store_T_12 = _GEN_52; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_14; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_14 = _GEN_52; // @[package.scala:16:47] wire _GEN_53 = ex_ctrl_mem_cmd == 5'hC; // @[package.scala:16:47] wire _mem_reg_load_T_15; // @[package.scala:16:47] assign _mem_reg_load_T_15 = _GEN_53; // @[package.scala:16:47] wire _mem_reg_store_T_13; // @[package.scala:16:47] assign _mem_reg_store_T_13 = _GEN_53; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_15 = _GEN_53; // @[package.scala:16:47] wire _GEN_54 = ex_ctrl_mem_cmd == 5'hD; // @[package.scala:16:47] wire _mem_reg_load_T_16; // @[package.scala:16:47] assign _mem_reg_load_T_16 = _GEN_54; // @[package.scala:16:47] wire _mem_reg_store_T_14; // @[package.scala:16:47] assign _mem_reg_store_T_14 = _GEN_54; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_16 = _GEN_54; // @[package.scala:16:47] wire _GEN_55 = ex_ctrl_mem_cmd == 5'hE; // @[package.scala:16:47] wire _mem_reg_load_T_17; // @[package.scala:16:47] assign _mem_reg_load_T_17 = _GEN_55; // @[package.scala:16:47] wire _mem_reg_store_T_15; // @[package.scala:16:47] assign _mem_reg_store_T_15 = _GEN_55; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_17 = _GEN_55; // @[package.scala:16:47] wire _GEN_56 = ex_ctrl_mem_cmd == 5'hF; // @[package.scala:16:47] wire _mem_reg_load_T_18; // @[package.scala:16:47] assign _mem_reg_load_T_18 = _GEN_56; // @[package.scala:16:47] wire _mem_reg_store_T_16; // @[package.scala:16:47] assign _mem_reg_store_T_16 = _GEN_56; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_18 = _GEN_56; // @[package.scala:16:47] wire _mem_reg_load_T_19 = _mem_reg_load_T_14 \| _mem_reg_load_T_15; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_20 = _mem_reg_load_T_19 \| _mem_reg_load_T_16; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_21 = _mem_reg_load_T_20 \| _mem_reg_load_T_17; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_22 = _mem_reg_load_T_21 \| _mem_reg_load_T_18; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_23 = _mem_reg_load_T_13 \| _mem_reg_load_T_22; // @[package.scala:81:59] wire _mem_reg_load_T_24 = _mem_reg_load_T_6 \| _mem_reg_load_T_23; // @[package.scala:81:59] wire _mem_reg_load_T_25 = ex_ctrl_mem & _mem_reg_load_T_24; // @[RocketCore.scala:243:20, :643:33] wire _mem_reg_store_T = ex_ctrl_mem_cmd == 5'h1; // @[RocketCore.scala:243:20] wire _mem_reg_store_T_1 = ex_ctrl_mem_cmd == 5'h11; // @[RocketCore.scala:243:20] wire _mem_reg_store_T_2 = _mem_reg_store_T \| _mem_reg_store_T_1; // @[Consts.scala:90:{32,42,49}] wire _mem_reg_store_T_4 = _mem_reg_store_T_2 \| _mem_reg_store_T_3; // @[Consts.scala:90:{42,59,66}] wire _mem_reg_store_T_9 = _mem_reg_store_T_5 \| _mem_reg_store_T_6; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_10 = _mem_reg_store_T_9 \| _mem_reg_store_T_7; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_11 = _mem_reg_store_T_10 \| _mem_reg_store_T_8; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_17 = _mem_reg_store_T_12 \| _mem_reg_store_T_13; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_18 = _mem_reg_store_T_17 \| _mem_reg_store_T_14; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_19 = _mem_reg_store_T_18 \| _mem_reg_store_T_15; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_20 = _mem_reg_store_T_19 \| _mem_reg_store_T_16; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_21 = _mem_reg_store_T_11 \| _mem_reg_store_T_20; // @[package.scala:81:59] wire _mem_reg_store_T_22 = _mem_reg_store_T_4 \| _mem_reg_store_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _mem_reg_store_T_23 = ex_ctrl_mem & _mem_reg_store_T_22; // @[RocketCore.scala:243:20, :644:34] wire [63:0] _mem_reg_wdata_T = ex_reg_set_vconfig ? {51'h0, ex_new_vl} : _alu_io_out; // @[RocketCore.scala:262:36, :504:19, :659:25] wire [1:0] size = ex_ctrl_rocc ? 2'h3 : ex_reg_mem_size; // @[RocketCore.scala:243:20, :257:28, :664:21] wire [1:0] mem_reg_rs2_size = size; // @[RocketCore.scala:664:21] wire _mem_reg_rs2_T = mem_reg_rs2_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _mem_reg_rs2_T_1 = mem_reg_rs2_dat_padded[7:0]; // @[AMOALU.scala:13:27, :29:69] wire [15:0] _mem_reg_rs2_T_2 = {2{_mem_reg_rs2_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _mem_reg_rs2_T_3 = {2{_mem_reg_rs2_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _mem_reg_rs2_T_4 = {2{_mem_reg_rs2_T_3}}; // @[AMOALU.scala:29:32] wire _mem_reg_rs2_T_5 = mem_reg_rs2_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _mem_reg_rs2_T_6 = mem_reg_rs2_dat_padded[15:0]; // @[AMOALU.scala:13:27, :29:69] wire [31:0] _mem_reg_rs2_T_7 = {2{_mem_reg_rs2_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_reg_rs2_T_8 = {2{_mem_reg_rs2_T_7}}; // @[AMOALU.scala:29:32] wire _mem_reg_rs2_T_9 = mem_reg_rs2_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _mem_reg_rs2_T_10 = mem_reg_rs2_dat_padded[31:0]; // @[AMOALU.scala:13:27, :29:69] wire [63:0] _mem_reg_rs2_T_11 = {2{_mem_reg_rs2_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_reg_rs2_T_12 = _mem_reg_rs2_T_9 ? _mem_reg_rs2_T_11 : mem_reg_rs2_dat_padded; // @[AMOALU.scala:13:27, :29:{13,19,32}] wire [63:0] _mem_reg_rs2_T_13 = _mem_reg_rs2_T_5 ? _mem_reg_rs2_T_8 : _mem_reg_rs2_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _mem_reg_rs2_T_14 = _mem_reg_rs2_T ? _mem_reg_rs2_T_4 : _mem_reg_rs2_T_13; // @[AMOALU.scala:29:{13,19,32}] wire [3:0] mem_reg_rs2_lo_hi = {ex_new_vconfig_vtype_vsew, ex_new_vconfig_vtype_vlmul_sign}; // @[RocketCore.scala:498:30, :668:41] wire [5:0] mem_reg_rs2_lo = {mem_reg_rs2_lo_hi, ex_new_vconfig_vtype_vlmul_mag}; // @[RocketCore.scala:498:30, :668:41] wire [1:0] mem_reg_rs2_hi_lo = {ex_new_vconfig_vtype_vma, ex_new_vconfig_vtype_vta}; // @[RocketCore.scala:498:30, :668:41] wire [55:0] mem_reg_rs2_hi_hi = {ex_new_vconfig_vtype_vill, 55'h0}; // @[RocketCore.scala:498:30, :668:41] wire [57:0] mem_reg_rs2_hi = {mem_reg_rs2_hi_hi, mem_reg_rs2_hi_lo}; // @[RocketCore.scala:668:41] wire [63:0] _mem_reg_rs2_T_15 = {mem_reg_rs2_hi, mem_reg_rs2_lo}; // @[RocketCore.scala:668:41] wire [76:0] _mem_reg_rs2_T_16 = {ex_new_vconfig_vl, _mem_reg_rs2_T_15}; // @[RocketCore.scala:498:30, :668:41] wire _mem_breakpoint_T = mem_reg_load & _bpu_io_xcpt_ld; // @[RocketCore.scala:273:36, :414:19, :677:38] wire _mem_breakpoint_T_1 = mem_reg_store & _bpu_io_xcpt_st; // @[RocketCore.scala:274:36, :414:19, :677:75] wire mem_breakpoint = _mem_breakpoint_T \| _mem_breakpoint_T_1; // @[RocketCore.scala:677:{38,57,75}] wire _mem_debug_breakpoint_T = mem_reg_load & _bpu_io_debug_ld; // @[RocketCore.scala:273:36, :414:19, :678:44] wire _mem_debug_breakpoint_T_1 = mem_reg_store & _bpu_io_debug_st; // @[RocketCore.scala:274:36, :414:19, :678:82] wire mem_debug_breakpoint = _mem_debug_breakpoint_T \| _mem_debug_breakpoint_T_1; // @[RocketCore.scala:678:{44,64,82}] wire mem_ldst_xcpt = mem_debug_breakpoint \| mem_breakpoint; // @[RocketCore.scala:677:57, :678:64, :1278:{14,35}] wire [3:0] mem_ldst_cause = mem_debug_breakpoint ? 4'hE : 4'h3; // @[Mux.scala:50:70] wire _T_74 = mem_reg_xcpt_interrupt \| mem_reg_xcpt; // @[RocketCore.scala:264:36, :268:36, :684:29] wire _T_75 = mem_reg_valid & mem_npc_misaligned; // @[RocketCore.scala:265:36, :623:70, :685:20] wire mem_xcpt = _T_74 \| _T_75 \| mem_reg_valid & mem_ldst_xcpt; // @[RocketCore.scala:265:36, :684:29, :685:20, :686:20, :1278:{14,35}] wire [63:0] mem_cause = _T_74 ? mem_reg_cause : {60'h0, _T_75 ? 4'h0 : mem_ldst_cause}; // @[Mux.scala:50:70] wire dcache_kill_mem = _dcache_kill_mem_T & io_dmem_replay_next_0; // @[RocketCore.scala:153:7, :695:{39,55}] wire _fpu_kill_mem_T = mem_reg_valid & mem_ctrl_fp; // @[RocketCore.scala:244:21, :265:36, :696:36] wire fpu_kill_mem = _fpu_kill_mem_T & io_fpu_nack_mem_0; // @[RocketCore.scala:153:7, :696:{36,51}] wire _vec_kill_mem_T = mem_reg_valid & mem_ctrl_mem; // @[RocketCore.scala:244:21, :265:36, :697:36] wire vec_kill_mem = _vec_kill_mem_T & io_vector_mem_block_mem_0; // @[RocketCore.scala:153:7, :697:{36,52}] wire _replay_mem_T = dcache_kill_mem \| mem_reg_replay; // @[RocketCore.scala:269:36, :695:55, :699:37] wire _replay_mem_T_1 = _replay_mem_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :699:{37,55}] wire _replay_mem_T_2 = _replay_mem_T_1 \| vec_kill_mem; // @[RocketCore.scala:697:52, :699:{55,71}] wire replay_mem = _replay_mem_T_2; // @[RocketCore.scala:699:{71,87}] wire _killm_common_T = dcache_kill_mem \| take_pc_wb; // @[RocketCore.scala:304:24, :695:55, :700:38] wire _killm_common_T_1 = _killm_common_T \| mem_reg_xcpt; // @[RocketCore.scala:268:36, :700:{38,52}] wire _killm_common_T_2 = ~mem_reg_valid; // @[RocketCore.scala:265:36, :700:71] assign killm_common = _killm_common_T_1 \| _killm_common_T_2; // @[RocketCore.scala:700:{52,68,71}] assign io_fpu_killm_0 = killm_common; // @[RocketCore.scala:153:7, :700:68] assign io_vector_killm_0 = killm_common; // @[RocketCore.scala:153:7, :700:68] wire _div_io_kill_T = _div_io_req_ready & _div_io_req_valid_T; // @[Decoupled.scala:51:35] reg div_io_kill_REG; // @[RocketCore.scala:701:41] wire _div_io_kill_T_1 = killm_common & div_io_kill_REG; // @[RocketCore.scala:700:68, :701:{31,41}] wire _ctrl_killm_T = killm_common \| mem_xcpt; // @[RocketCore.scala:700:68, :702:33, :1278:14] wire _ctrl_killm_T_1 = _ctrl_killm_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :702:{33,45}] wire ctrl_killm = _ctrl_killm_T_1 \| vec_kill_mem; // @[RocketCore.scala:697:52, :702:{45,61}] wire _wb_reg_valid_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19] wire _wb_reg_replay_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34] wire _wb_reg_replay_T_1 = replay_mem & _wb_reg_replay_T; // @[RocketCore.scala:699:87, :706:{31,34}] wire _wb_reg_xcpt_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :707:30] wire _wb_reg_xcpt_T_1 = mem_xcpt & _wb_reg_xcpt_T; // @[RocketCore.scala:707:{27,30}, :1278:14] wire _wb_reg_xcpt_T_3 = _wb_reg_xcpt_T_1; // @[RocketCore.scala:707:{27,42}] wire _wb_reg_flush_pipe_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19, :708:24] wire _wb_reg_flush_pipe_T_1 = _wb_reg_flush_pipe_T & mem_reg_flush_pipe; // @[RocketCore.scala:270:36, :708:{24,36}] wire _wb_reg_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :712:25] wire _wb_reg_wdata_T_1 = _wb_reg_wdata_T & mem_ctrl_fp; // @[RocketCore.scala:244:21, :712:{25,39}] wire _wb_reg_wdata_T_2 = _wb_reg_wdata_T_1 & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :712:{39,54}] wire [63:0] _wb_reg_wdata_T_3 = _wb_reg_wdata_T_2 ? io_fpu_toint_data_0 : mem_int_wdata; // @[RocketCore.scala:153:7, :624:119, :712:{24,54}] wire _wb_reg_hfence_v_T = mem_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:244:21, :721:41] wire _wb_reg_hfence_g_T = mem_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:244:21, :722:41] wire _T_113 = wb_reg_valid & wb_ctrl_mem; // @[RocketCore.scala:245:20, :288:35, :730:19] wire _T_100 = _T_113 & io_dmem_s2_xcpt_pf_st_0; // @[RocketCore.scala:153:7, :730:{19,34}] wire _T_102 = _T_113 & io_dmem_s2_xcpt_pf_ld_0; // @[RocketCore.scala:153:7, :730:19, :731:34] wire _T_108 = _T_113 & io_dmem_s2_xcpt_ae_st_0; // @[RocketCore.scala:153:7, :730:19, :734:34] wire _T_110 = _T_113 & io_dmem_s2_xcpt_ae_ld_0; // @[RocketCore.scala:153:7, :730:19, :735:34] wire _T_112 = _T_113 & io_dmem_s2_xcpt_ma_st_0; // @[RocketCore.scala:153:7, :730:19, :736:34] wire wb_xcpt = wb_reg_xcpt \| _T_100 \| _T_102 \| _T_108 \| _T_110 \| _T_112 \| _T_113 & io_dmem_s2_xcpt_ma_ld_0; // @[RocketCore.scala:153:7, :289:35, :730:{19,34}, :731:34, :734:34, :735:34, :736:34, :737:34, :1278:{14,35}] wire [63:0] wb_cause = wb_reg_xcpt ? wb_reg_cause : {59'h0, _T_100 ? 5'hF : _T_102 ? 5'hD : {2'h0, _T_108 ? 3'h7 : _T_110 ? 3'h5 : {1'h1, _T_112, 1'h0}}}; // @[Mux.scala:50:70] wire _wb_pc_valid_T = wb_reg_valid \| wb_reg_replay; // @[RocketCore.scala:288:35, :290:35, :754:34] wire wb_pc_valid = _wb_pc_valid_T \| wb_reg_xcpt; // @[RocketCore.scala:289:35, :754:{34,51}] wire wb_wxd = wb_reg_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :288:35, :755:29] wire _wb_set_sboard_T = wb_ctrl_div \| wb_dcache_miss; // @[RocketCore.scala:245:20, :596:36, :756:35] wire _wb_set_sboard_T_1 = _wb_set_sboard_T \| wb_ctrl_rocc; // @[RocketCore.scala:245:20, :756:{35,53}] wire wb_set_sboard = _wb_set_sboard_T_1 \| wb_ctrl_vec; // @[RocketCore.scala:245:20, :756:{53,69}] wire replay_wb_common = io_dmem_s2_nack_0 \| wb_reg_replay; // @[RocketCore.scala:153:7, :290:35, :757:42] wire replay_wb_rocc = _replay_wb_rocc_T; // @[RocketCore.scala:758:{37,53}] wire replay_wb_vec = wb_reg_valid & io_vector_wb_replay_0; // @[RocketCore.scala:153:7, :288:35, :760:36] wire _replay_wb_T = replay_wb_common \| replay_wb_rocc; // @[RocketCore.scala:757:42, :758:53, :761:36] wire _replay_wb_T_1 = _replay_wb_T; // @[RocketCore.scala:761:{36,54}] wire replay_wb = _replay_wb_T_1 \| replay_wb_vec; // @[RocketCore.scala:760:36, :761:{54,71}] wire _take_pc_wb_T = replay_wb \| wb_xcpt; // @[RocketCore.scala:761:71, :762:27, :1278:14] wire _take_pc_wb_T_1 = _take_pc_wb_T \| _csr_io_eret; // @[RocketCore.scala:341:19, :762:{27,38}] assign _take_pc_wb_T_2 = _take_pc_wb_T_1 \| wb_reg_flush_pipe; // @[RocketCore.scala:291:35, :762:{38,53}] assign take_pc_wb = _take_pc_wb_T_2; // @[RocketCore.scala:304:24, :762:53] wire _dmem_resp_xpu_T = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45] wire dmem_resp_fpu = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45, :766:45] wire dmem_resp_xpu = ~_dmem_resp_xpu_T; // @[RocketCore.scala:765:{23,45}] wire [4:0] dmem_resp_waddr = io_dmem_resp_bits_tag_0[5:1]; // @[RocketCore.scala:153:7, :767:46] wire dmem_resp_valid = io_dmem_resp_valid_0 & io_dmem_resp_bits_has_data_0; // @[RocketCore.scala:153:7, :768:44] wire dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay_0; // @[RocketCore.scala:153:7, :768:44, :769:42] wire [63:0] ll_wdata; // @[RocketCore.scala:779:26] wire [4:0] ll_waddr; // @[RocketCore.scala:780:26] wire _ll_wen_T = ll_arb_io_out_ready & _ll_arb_io_out_valid; // @[Decoupled.scala:51:35] wire ll_wen; // @[RocketCore.scala:781:24] wire _ll_arb_io_out_ready_T = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26] wire _T_168 = dmem_resp_valid & dmem_resp_fpu; // @[RocketCore.scala:766:45, :768:44, :801:59] wire _io_vector_resp_ready_T; // @[RocketCore.scala:801:59] assign _io_vector_resp_ready_T = _T_168; // @[RocketCore.scala:801:59] wire _io_fpu_ll_resp_val_T; // @[RocketCore.scala:1099:41] assign _io_fpu_ll_resp_val_T = _T_168; // @[RocketCore.scala:801:59, :1099:41] wire _io_vector_resp_ready_T_1 = ~_io_vector_resp_ready_T; // @[RocketCore.scala:801:{41,59}] assign _io_vector_resp_ready_T_2 = io_vector_resp_bits_fp_0 ? _io_vector_resp_ready_T_1 : _ll_arb_io_in_2_ready; // @[RocketCore.scala:153:7, :776:22, :801:{24,41}] assign io_vector_resp_ready_0 = _io_vector_resp_ready_T_2; // @[RocketCore.scala:153:7, :801:24] wire _ll_arb_io_in_2_valid_T = ~io_vector_resp_bits_fp_0; // @[RocketCore.scala:153:7, :802:46] wire _ll_arb_io_in_2_valid_T_1 = io_vector_resp_valid_0 & _ll_arb_io_in_2_valid_T; // @[RocketCore.scala:153:7, :802:{43,46}] wire _T_143 = dmem_resp_replay & dmem_resp_xpu; // @[RocketCore.scala:765:23, :769:42, :809:26] assign ll_arb_io_out_ready = ~_T_143 & _ll_arb_io_out_ready_T; // @[RocketCore.scala:782:{23,26}, :809:{26,44}, :810:25] assign ll_waddr = _T_143 ? dmem_resp_waddr : _ll_arb_io_out_bits_tag; // @[RocketCore.scala:767:46, :776:22, :780:26, :809:{26,44}, :811:14] assign ll_wen = _T_143 \| _ll_wen_T; // @[Decoupled.scala:51:35] wire _wb_valid_T = ~replay_wb; // @[RocketCore.scala:761:71, :815:34] wire _wb_valid_T_1 = wb_reg_valid & _wb_valid_T; // @[RocketCore.scala:288:35, :815:{31,34}] wire _wb_valid_T_2 = ~wb_xcpt; // @[RocketCore.scala:815:48, :1278:14] wire wb_valid = _wb_valid_T_1 & _wb_valid_T_2; // @[RocketCore.scala:815:{31,45,48}] wire wb_wen = wb_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :815:45, :816:25] wire rf_wen = wb_wen \| ll_wen; // @[RocketCore.scala:781:24, :816:25, :817:23] wire [4:0] rf_waddr = ll_wen ? ll_waddr : wb_waddr; // @[RocketCore.scala:455:36, :780:26, :781:24, :818:21] wire [4:0] xrfWriteBundle_wrdst = rf_waddr; // @[RocketCore.scala:818:21, :1249:28] wire _rf_wdata_T = dmem_resp_valid & dmem_resp_xpu; // @[RocketCore.scala:765:23, :768:44, :819:38] wire _rf_wdata_T_2 = \|wb_ctrl_csr; // @[RocketCore.scala:245:20, :821:34] wire [63:0] _rf_wdata_T_4 = _rf_wdata_T_2 ? _csr_io_rw_rdata : _rf_wdata_T_3; // @[RocketCore.scala:341:19, :821:{21,34}, :822:21] wire [63:0] _rf_wdata_T_5 = ll_wen ? ll_wdata : _rf_wdata_T_4; // @[RocketCore.scala:779:26, :781:24, :820:21, :821:21] wire [63:0] rf_wdata = _rf_wdata_T ? _rf_wdata_T_1 : _rf_wdata_T_5; // @[RocketCore.scala:819:{21,38,78}, :820:21] wire [63:0] coreMonitorBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1186:31] wire [63:0] xrfWriteBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1249:28] wire [63:0] _id_rs_T_4; // @[RocketCore.scala:1326:25] assign id_rs_0 = rf_wen & (\|rf_waddr) & rf_waddr == id_raddr1 ? rf_wdata : _id_rs_T_4; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}] wire [63:0] _id_rs_T_9; // @[RocketCore.scala:1326:25] assign id_rs_1 = rf_wen & (\|rf_waddr) & rf_waddr == id_raddr2 ? rf_wdata : _id_rs_T_9; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}] wire [1:0] _csr_io_inst_0_T = wb_reg_raw_inst[1:0]; // @[RocketCore.scala:301:28, :832:66] wire _csr_io_inst_0_T_1 = &_csr_io_inst_0_T; // @[RocketCore.scala:832:{66,73}] wire [15:0] _csr_io_inst_0_T_2 = wb_reg_inst[31:16]; // @[RocketCore.scala:300:24, :832:91] wire [15:0] _csr_io_inst_0_T_3 = _csr_io_inst_0_T_1 ? _csr_io_inst_0_T_2 : 16'h0; // @[RocketCore.scala:832:{50,73,91}] wire [15:0] _csr_io_inst_0_T_4 = wb_reg_raw_inst[15:0]; // @[RocketCore.scala:301:28, :832:119] wire [31:0] _csr_io_inst_0_T_5 = {_csr_io_inst_0_T_3, _csr_io_inst_0_T_4}; // @[RocketCore.scala:832:{46,50,119}] wire _csr_io_fcsr_flags_valid_T = io_fpu_fcsr_flags_valid_0 \| io_vector_set_fflags_valid_0; // @[RocketCore.scala:153:7, :838:54] wire [4:0] _csr_io_fcsr_flags_bits_T = {5{io_fpu_fcsr_flags_valid_0}}; // @[RocketCore.scala:153:7, :839:59] wire [4:0] _csr_io_fcsr_flags_bits_T_1 = io_fpu_fcsr_flags_bits_0 & _csr_io_fcsr_flags_bits_T; // @[RocketCore.scala:153:7, :839:{53,59}] wire [4:0] _csr_io_fcsr_flags_bits_T_2 = {5{io_vector_set_fflags_valid_0}}; // @[RocketCore.scala:153:7, :839:116] wire [4:0] _csr_io_fcsr_flags_bits_T_3 = io_vector_set_fflags_bits_0 & _csr_io_fcsr_flags_bits_T_2; // @[RocketCore.scala:153:7, :839:{110,116}] wire [4:0] _csr_io_fcsr_flags_bits_T_4 = _csr_io_fcsr_flags_bits_T_1 \| _csr_io_fcsr_flags_bits_T_3; // @[RocketCore.scala:839:{53,89,110}] wire [31:0] _io_fpu_time_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29] wire [31:0] _coreMonitorBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1191:41] wire [31:0] _xrfWriteBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1254:38] assign io_fpu_time_0 = {32'h0, _io_fpu_time_T}; // @[RocketCore.scala:153:7, :840:{15,29}] wire tval_dmem_addr = ~wb_reg_xcpt; // @[RocketCore.scala:289:35, :845:24] wire _tval_any_addr_T = wb_reg_cause == 64'h3; // @[package.scala:16:47] wire _tval_any_addr_T_1 = wb_reg_cause == 64'h1; // @[package.scala:16:47] wire _tval_any_addr_T_2 = wb_reg_cause == 64'hC; // @[package.scala:16:47] wire _GEN_57 = wb_reg_cause == 64'h14; // @[package.scala:16:47] wire _tval_any_addr_T_3; // @[package.scala:16:47] assign _tval_any_addr_T_3 = _GEN_57; // @[package.scala:16:47] wire _htval_valid_imem_T; // @[RocketCore.scala:853:56] assign _htval_valid_imem_T = _GEN_57; // @[package.scala:16:47] wire _tval_any_addr_T_4 = _tval_any_addr_T \| _tval_any_addr_T_1; // @[package.scala:16:47, :81:59] wire _tval_any_addr_T_5 = _tval_any_addr_T_4 \| _tval_any_addr_T_2; // @[package.scala:16:47, :81:59] wire _tval_any_addr_T_6 = _tval_any_addr_T_5 \| _tval_any_addr_T_3; // @[package.scala:16:47, :81:59] wire tval_any_addr = tval_dmem_addr \| _tval_any_addr_T_6; // @[package.scala:81:59] wire tval_inst = wb_reg_cause == 64'h2; // @[RocketCore.scala:292:35, :848:32] wire _tval_valid_T = tval_any_addr \| tval_inst; // @[RocketCore.scala:846:38, :848:32, :849:46] wire tval_valid = wb_xcpt & _tval_valid_T; // @[RocketCore.scala:849:{28,46}, :1278:14] wire _csr_io_gva_T = tval_any_addr & _csr_io_status_v; // @[RocketCore.scala:341:19, :846:38, :850:43] wire _csr_io_gva_T_1 = tval_dmem_addr & wb_reg_hls_or_dv; // @[RocketCore.scala:297:29, :845:24, :850:80] wire _csr_io_gva_T_2 = _csr_io_gva_T \| _csr_io_gva_T_1; // @[RocketCore.scala:850:{43,62,80}] wire _csr_io_gva_T_3 = wb_xcpt & _csr_io_gva_T_2; // @[RocketCore.scala:850:{25,62}, :1278:14] wire [24:0] _csr_io_tval_a_T = wb_reg_wdata[63:39]; // @[RocketCore.scala:302:25, :1293:17] wire [24:0] csr_io_tval_a = _csr_io_tval_a_T; // @[RocketCore.scala:1293:{17,23}] wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _csr_io_tval_msb_T_1 = &csr_io_tval_a; // @[RocketCore.scala:1293:23, :1294:34] wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T \| _csr_io_tval_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _csr_io_tval_msb_T_3 = wb_reg_wdata[39]; // @[RocketCore.scala:302:25, :1294:46] wire _csr_io_tval_msb_T_4 = wb_reg_wdata[38]; // @[RocketCore.scala:302:25, :1294:54] wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] assign io_imem_sfence_bits_addr_0 = wb_reg_wdata[38:0]; // @[RocketCore.scala:153:7, :302:25, :1295:16] wire [38:0] _csr_io_tval_T = wb_reg_wdata[38:0]; // @[RocketCore.scala:302:25, :1295:16] wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}] wire [39:0] _csr_io_tval_T_2 = tval_valid ? _csr_io_tval_T_1 : 40'h0; // @[RocketCore.scala:849:28, :851:21, :1295:8] wire htval_valid_imem = wb_reg_xcpt & _htval_valid_imem_T; // @[RocketCore.scala:289:35, :853:{40,56}] wire [39:0] htval_imem = htval_valid_imem ? io_imem_gpa_bits_0 : 40'h0; // @[RocketCore.scala:153:7, :853:40, :854:25] wire [39:0] _htval_T = htval_imem; // @[RocketCore.scala:854:25, :860:29] wire _htval_valid_dmem_T = wb_xcpt & tval_dmem_addr; // @[RocketCore.scala:845:24, :857:36, :1278:14] wire [1:0] _htval_valid_dmem_T_4 = {io_dmem_s2_xcpt_pf_ld_0, io_dmem_s2_xcpt_pf_st_0}; // @[RocketCore.scala:153:7, :857:110] wire _htval_valid_dmem_T_5 = \|_htval_valid_dmem_T_4; // @[RocketCore.scala:857:{110,117}] wire _htval_valid_dmem_T_6 = ~_htval_valid_dmem_T_5; // @[RocketCore.scala:857:{90,117}] wire [39:0] htval = _htval_T; // @[RocketCore.scala:860:{29,43}] wire _mhtinst_read_pseudo_T = io_imem_gpa_is_pte_0 & htval_valid_imem; // @[RocketCore.scala:153:7, :853:40, :862:51] wire mhtinst_read_pseudo = _mhtinst_read_pseudo_T; // @[RocketCore.scala:862:{51,72}] wire _GEN_58 = wb_reg_set_vconfig & wb_reg_valid; // @[RocketCore.scala:288:35, :293:35, :867:47] wire _csr_io_vector_set_vconfig_valid_T; // @[RocketCore.scala:867:47] assign _csr_io_vector_set_vconfig_valid_T = _GEN_58; // @[RocketCore.scala:867:47] wire _id_vconfig_hazard_T_3; // @[RocketCore.scala:1005:19] assign _id_vconfig_hazard_T_3 = _GEN_58; // @[RocketCore.scala:867:47, :1005:19] wire [12:0] _csr_io_vector_set_vconfig_bits_T_7; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_T_6; // @[RocketCore.scala:868:46] wire [54:0] _csr_io_vector_set_vconfig_bits_T_5; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_T_4; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_T_3; // @[RocketCore.scala:868:46] wire [2:0] _csr_io_vector_set_vconfig_bits_T_2; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_T_1; // @[RocketCore.scala:868:46] wire [1:0] _csr_io_vector_set_vconfig_bits_T; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T = _csr_io_vector_set_vconfig_bits_WIRE_1[1:0]; // @[RocketCore.scala:868:46] wire [1:0] _csr_io_vector_set_vconfig_bits_WIRE_vtype_vlmul_mag = _csr_io_vector_set_vconfig_bits_T; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T_1 = _csr_io_vector_set_vconfig_bits_WIRE_1[2]; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_WIRE_vtype_vlmul_sign = _csr_io_vector_set_vconfig_bits_T_1; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T_2 = _csr_io_vector_set_vconfig_bits_WIRE_1[5:3]; // @[RocketCore.scala:868:46] wire [2:0] _csr_io_vector_set_vconfig_bits_WIRE_vtype_vsew = _csr_io_vector_set_vconfig_bits_T_2; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T_3 = _csr_io_vector_set_vconfig_bits_WIRE_1[6]; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_WIRE_vtype_vta = _csr_io_vector_set_vconfig_bits_T_3; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T_4 = _csr_io_vector_set_vconfig_bits_WIRE_1[7]; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_WIRE_vtype_vma = _csr_io_vector_set_vconfig_bits_T_4; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T_5 = _csr_io_vector_set_vconfig_bits_WIRE_1[62:8]; // @[RocketCore.scala:868:46] wire [54:0] _csr_io_vector_set_vconfig_bits_WIRE_vtype_reserved = _csr_io_vector_set_vconfig_bits_T_5; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T_6 = _csr_io_vector_set_vconfig_bits_WIRE_1[63]; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vconfig_bits_WIRE_vtype_vill = _csr_io_vector_set_vconfig_bits_T_6; // @[RocketCore.scala:868:46] assign _csr_io_vector_set_vconfig_bits_T_7 = _csr_io_vector_set_vconfig_bits_WIRE_1[76:64]; // @[RocketCore.scala:868:46] wire [12:0] _csr_io_vector_set_vconfig_bits_WIRE_vl = _csr_io_vector_set_vconfig_bits_T_7; // @[RocketCore.scala:868:46] wire _csr_io_vector_set_vs_dirty_T = wb_valid & wb_ctrl_vec; // @[RocketCore.scala:245:20, :815:45, :869:32] wire _csr_io_vector_set_vstart_valid_T = wb_valid & wb_reg_set_vconfig; // @[RocketCore.scala:293:35, :815:45, :870:36] wire _T_155 = io_vector_wb_retire_0 \| wb_ctrl_vec; // @[RocketCore.scala:153:7, :245:20, :875:36] wire [11:0] _csr_io_rw_addr_T = wb_reg_inst[31:20]; // @[RocketCore.scala:300:24, :909:32] wire [2:0] _csr_io_rw_cmd_T = {~wb_reg_valid, 2'h0}; // @[RocketCore.scala:288:35] wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala:183:{11,15}] wire [2:0] _csr_io_rw_cmd_T_2 = wb_ctrl_csr & _csr_io_rw_cmd_T_1; // @[RocketCore.scala:245:20] assign io_bpwatch_0_action_0 = {2'h0, _csr_io_bp_0_control_action}; // @[RocketCore.scala:153:7, :341:19, :962:18] wire _hazard_targets_T = \|id_raddr1; // @[RocketCore.scala:326:72, :969:55, :1326:41] wire hazard_targets_0_1 = id_ctrl_rxs1 & _hazard_targets_T; // @[RocketCore.scala:321:21, :969:{42,55}] wire _hazard_targets_T_1 = \|id_raddr2; // @[RocketCore.scala:326:72, :970:55, :1326:41] wire hazard_targets_1_1 = id_ctrl_rxs2 & _hazard_targets_T_1; // @[RocketCore.scala:321:21, :970:{42,55}] wire _hazard_targets_T_2 = \|id_waddr; // @[RocketCore.scala:326:72, :971:55] wire hazard_targets_2_1 = id_ctrl_wxd & _hazard_targets_T_2; // @[RocketCore.scala:321:21, :971:{42,55}] reg [31:0] _r; // @[RocketCore.scala:1305:29] wire [30:0] _r_T = _r[31:1]; // @[RocketCore.scala:1305:29, :1306:35] wire [31:0] r = {_r_T, 1'h0}; // @[RocketCore.scala:1306:{35,40}] wire [31:0] _GEN_59 = {27'h0, id_raddr1}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T = r >> _GEN_59; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_1 = _id_sboard_hazard_T[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_2 = ll_waddr == id_raddr1; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_3 = ll_wen & _id_sboard_hazard_T_2; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_4 = ~_id_sboard_hazard_T_3; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_5 = _id_sboard_hazard_T_1 & _id_sboard_hazard_T_4; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_6 = hazard_targets_0_1 & _id_sboard_hazard_T_5; // @[RocketCore.scala:969:42, :984:77, :1287:27] wire [31:0] _GEN_60 = {27'h0, id_raddr2}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_7 = r >> _GEN_60; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_8 = _id_sboard_hazard_T_7[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_9 = ll_waddr == id_raddr2; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_10 = ll_wen & _id_sboard_hazard_T_9; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_11 = ~_id_sboard_hazard_T_10; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_12 = _id_sboard_hazard_T_8 & _id_sboard_hazard_T_11; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_13 = hazard_targets_1_1 & _id_sboard_hazard_T_12; // @[RocketCore.scala:970:42, :984:77, :1287:27] wire [31:0] _GEN_61 = {27'h0, id_waddr}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_14 = r >> _GEN_61; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_15 = _id_sboard_hazard_T_14[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_16 = ll_waddr == id_waddr; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_17 = ll_wen & _id_sboard_hazard_T_16; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_18 = ~_id_sboard_hazard_T_17; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_19 = _id_sboard_hazard_T_15 & _id_sboard_hazard_T_18; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_20 = hazard_targets_2_1 & _id_sboard_hazard_T_19; // @[RocketCore.scala:971:42, :984:77, :1287:27] wire _id_sboard_hazard_T_21 = _id_sboard_hazard_T_6 \| _id_sboard_hazard_T_13; // @[RocketCore.scala:1287:{27,50}] wire id_sboard_hazard = _id_sboard_hazard_T_21 \| _id_sboard_hazard_T_20; // @[RocketCore.scala:1287:{27,50}] wire [31:0] _id_stall_fpu_T_4 = 32'h1 << wb_waddr; // @[RocketCore.scala:455:36, :1309:58] wire _ex_cannot_bypass_T = \|ex_ctrl_csr; // @[RocketCore.scala:243:20, :988:38] wire _ex_cannot_bypass_T_1 = _ex_cannot_bypass_T \| ex_ctrl_jalr; // @[RocketCore.scala:243:20, :988:{38,48}] wire _ex_cannot_bypass_T_2 = _ex_cannot_bypass_T_1 \| ex_ctrl_mem; // @[RocketCore.scala:243:20, :988:{48,64}] wire _ex_cannot_bypass_T_3 = _ex_cannot_bypass_T_2 \| ex_ctrl_mul; // @[RocketCore.scala:243:20, :988:{64,79}] wire _ex_cannot_bypass_T_4 = _ex_cannot_bypass_T_3 \| ex_ctrl_div; // @[RocketCore.scala:243:20, :988:{79,94}] wire _ex_cannot_bypass_T_5 = _ex_cannot_bypass_T_4 \| ex_ctrl_fp; // @[RocketCore.scala:243:20, :988:{94,109}] wire _ex_cannot_bypass_T_6 = _ex_cannot_bypass_T_5 \| ex_ctrl_rocc; // @[RocketCore.scala:243:20, :988:{109,123}] wire ex_cannot_bypass = _ex_cannot_bypass_T_6 \| ex_ctrl_vec; // @[RocketCore.scala:243:20, :988:{123,139}] wire _data_hazard_ex_T_1 = hazard_targets_0_1 & _data_hazard_ex_T; // @[RocketCore.scala:969:42, :989:70, :1287:27] wire _data_hazard_ex_T_3 = hazard_targets_1_1 & _data_hazard_ex_T_2; // @[RocketCore.scala:970:42, :989:70, :1287:27] wire _GEN_62 = id_waddr == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :989:70] wire _data_hazard_ex_T_4; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T_4 = _GEN_62; // @[RocketCore.scala:989:70] wire _fp_data_hazard_ex_T_7; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_7 = _GEN_62; // @[RocketCore.scala:989:70, :990:90] wire _data_hazard_ex_T_5 = hazard_targets_2_1 & _data_hazard_ex_T_4; // @[RocketCore.scala:971:42, :989:70, :1287:27] wire _data_hazard_ex_T_6 = _data_hazard_ex_T_1 \| _data_hazard_ex_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_ex_T_7 = _data_hazard_ex_T_6 \| _data_hazard_ex_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_ex = ex_ctrl_wxd & _data_hazard_ex_T_7; // @[RocketCore.scala:243:20, :989:36, :1287:50] wire _fp_data_hazard_ex_T = id_ctrl_fp & ex_ctrl_wfd; // @[RocketCore.scala:243:20, :321:21, :990:38] wire _fp_data_hazard_ex_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_ex_T_1; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_ex_T_3; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_5 = id_raddr3 == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :990:90] wire _fp_data_hazard_ex_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_ex_T_5; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_ex_T_7; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_9 = _fp_data_hazard_ex_T_2 \| _fp_data_hazard_ex_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_ex_T_10 = _fp_data_hazard_ex_T_9 \| _fp_data_hazard_ex_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_ex_T_11 = _fp_data_hazard_ex_T_10 \| _fp_data_hazard_ex_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_ex = _fp_data_hazard_ex_T & _fp_data_hazard_ex_T_11; // @[RocketCore.scala:990:{38,53}, :1287:50] wire _id_ex_hazard_T = data_hazard_ex & ex_cannot_bypass; // @[RocketCore.scala:988:139, :989:36, :991:54] wire _id_ex_hazard_T_1 = _id_ex_hazard_T \| fp_data_hazard_ex; // @[RocketCore.scala:990:53, :991:{54,74}] wire id_ex_hazard = ex_reg_valid & _id_ex_hazard_T_1; // @[RocketCore.scala:248:35, :991:{35,74}] wire _mem_cannot_bypass_T = \|mem_ctrl_csr; // @[RocketCore.scala:244:21, :997:40] wire _mem_cannot_bypass_T_1 = mem_ctrl_mem & mem_mem_cmd_bh; // @[RocketCore.scala:244:21, :995:41, :997:66] wire _mem_cannot_bypass_T_2 = _mem_cannot_bypass_T \| _mem_cannot_bypass_T_1; // @[RocketCore.scala:997:{40,50,66}] wire _mem_cannot_bypass_T_3 = _mem_cannot_bypass_T_2 \| mem_ctrl_mul; // @[RocketCore.scala:244:21, :997:{50,84}] wire _mem_cannot_bypass_T_4 = _mem_cannot_bypass_T_3 \| mem_ctrl_div; // @[RocketCore.scala:244:21, :997:{84,100}] wire _mem_cannot_bypass_T_5 = _mem_cannot_bypass_T_4 \| mem_ctrl_fp; // @[RocketCore.scala:244:21, :997:{100,116}] wire _mem_cannot_bypass_T_6 = _mem_cannot_bypass_T_5 \| mem_ctrl_rocc; // @[RocketCore.scala:244:21, :997:{116,131}] wire mem_cannot_bypass = _mem_cannot_bypass_T_6 \| mem_ctrl_vec; // @[RocketCore.scala:244:21, :997:{131,148}] wire _data_hazard_mem_T_1 = hazard_targets_0_1 & _data_hazard_mem_T; // @[RocketCore.scala:969:42, :998:72, :1287:27] wire _data_hazard_mem_T_3 = hazard_targets_1_1 & _data_hazard_mem_T_2; // @[RocketCore.scala:970:42, :998:72, :1287:27] wire _GEN_63 = id_waddr == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :998:72] wire _data_hazard_mem_T_4; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T_4 = _GEN_63; // @[RocketCore.scala:998:72] wire _fp_data_hazard_mem_T_7; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_7 = _GEN_63; // @[RocketCore.scala:998:72, :999:92] wire _data_hazard_mem_T_5 = hazard_targets_2_1 & _data_hazard_mem_T_4; // @[RocketCore.scala:971:42, :998:72, :1287:27] wire _data_hazard_mem_T_6 = _data_hazard_mem_T_1 \| _data_hazard_mem_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_mem_T_7 = _data_hazard_mem_T_6 \| _data_hazard_mem_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_mem = mem_ctrl_wxd & _data_hazard_mem_T_7; // @[RocketCore.scala:244:21, :998:38, :1287:50] wire _fp_data_hazard_mem_T = id_ctrl_fp & mem_ctrl_wfd; // @[RocketCore.scala:244:21, :321:21, :999:39] wire _fp_data_hazard_mem_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_mem_T_1; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_mem_T_3; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_5 = id_raddr3 == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :999:92] wire _fp_data_hazard_mem_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_mem_T_5; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_mem_T_7; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_9 = _fp_data_hazard_mem_T_2 \| _fp_data_hazard_mem_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_mem_T_10 = _fp_data_hazard_mem_T_9 \| _fp_data_hazard_mem_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_mem_T_11 = _fp_data_hazard_mem_T_10 \| _fp_data_hazard_mem_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_mem = _fp_data_hazard_mem_T & _fp_data_hazard_mem_T_11; // @[RocketCore.scala:999:{39,55}, :1287:50] wire _id_mem_hazard_T = data_hazard_mem & mem_cannot_bypass; // @[RocketCore.scala:997:148, :998:38, :1000:57] wire _id_mem_hazard_T_1 = _id_mem_hazard_T \| fp_data_hazard_mem; // @[RocketCore.scala:999:55, :1000:{57,78}] wire id_mem_hazard = mem_reg_valid & _id_mem_hazard_T_1; // @[RocketCore.scala:265:36, :1000:{37,78}] wire _id_load_use_T = mem_reg_valid & data_hazard_mem; // @[RocketCore.scala:265:36, :998:38, :1001:32] assign _id_load_use_T_1 = _id_load_use_T & mem_ctrl_mem; // @[RocketCore.scala:244:21, :1001:{32,51}] assign id_load_use = _id_load_use_T_1; // @[RocketCore.scala:332:25, :1001:51] wire _id_vconfig_hazard_T = ex_reg_valid & ex_reg_set_vconfig; // @[RocketCore.scala:248:35, :262:36, :1003:19] wire _id_vconfig_hazard_T_1 = mem_reg_valid & mem_reg_set_vconfig; // @[RocketCore.scala:265:36, :275:36, :1004:20] wire _id_vconfig_hazard_T_2 = _id_vconfig_hazard_T \| _id_vconfig_hazard_T_1; // @[RocketCore.scala:1003:{19,42}, :1004:20] wire _id_vconfig_hazard_T_4 = _id_vconfig_hazard_T_2 \| _id_vconfig_hazard_T_3; // @[RocketCore.scala:1003:42, :1004:44, :1005:19] wire id_vconfig_hazard = id_ctrl_vec & _id_vconfig_hazard_T_4; // @[RocketCore.scala:321:21, :1002:39, :1004:44] wire _GEN_64 = id_raddr1 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T = _GEN_64; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_1; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_1 = _GEN_64; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_1 = hazard_targets_0_1 & _data_hazard_wb_T; // @[RocketCore.scala:969:42, :1008:70, :1287:27] wire _GEN_65 = id_raddr2 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T_2; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T_2 = _GEN_65; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_3; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_3 = _GEN_65; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_3 = hazard_targets_1_1 & _data_hazard_wb_T_2; // @[RocketCore.scala:970:42, :1008:70, :1287:27] wire _GEN_66 = id_waddr == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T_4; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T_4 = _GEN_66; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_7; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_7 = _GEN_66; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_5 = hazard_targets_2_1 & _data_hazard_wb_T_4; // @[RocketCore.scala:971:42, :1008:70, :1287:27] wire _data_hazard_wb_T_6 = _data_hazard_wb_T_1 \| _data_hazard_wb_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_wb_T_7 = _data_hazard_wb_T_6 \| _data_hazard_wb_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_wb = wb_ctrl_wxd & _data_hazard_wb_T_7; // @[RocketCore.scala:245:20, :1008:36, :1287:50] wire _fp_data_hazard_wb_T = id_ctrl_fp & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :321:21, :1009:38] wire _fp_data_hazard_wb_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_wb_T_1; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_wb_T_3; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_5 = id_raddr3 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1009:90] wire _fp_data_hazard_wb_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_wb_T_5; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_wb_T_7; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_9 = _fp_data_hazard_wb_T_2 \| _fp_data_hazard_wb_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_wb_T_10 = _fp_data_hazard_wb_T_9 \| _fp_data_hazard_wb_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_wb_T_11 = _fp_data_hazard_wb_T_10 \| _fp_data_hazard_wb_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_wb = _fp_data_hazard_wb_T & _fp_data_hazard_wb_T_11; // @[RocketCore.scala:1009:{38,53}, :1287:50] wire _id_wb_hazard_T = data_hazard_wb & wb_set_sboard; // @[RocketCore.scala:756:69, :1008:36, :1010:54] wire _id_wb_hazard_T_1 = _id_wb_hazard_T \| fp_data_hazard_wb; // @[RocketCore.scala:1009:53, :1010:{54,71}] wire id_wb_hazard = wb_reg_valid & _id_wb_hazard_T_1; // @[RocketCore.scala:288:35, :1010:{35,71}] reg [31:0] _id_stall_fpu_r; // @[RocketCore.scala:1305:29] wire _id_stall_fpu_T = wb_dcache_miss \| wb_ctrl_vec; // @[RocketCore.scala:245:20, :596:36, :1014:36] wire _id_stall_fpu_T_1 = _id_stall_fpu_T & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :1014:{36,52}] wire _id_stall_fpu_T_2 = _id_stall_fpu_T_1 \| io_fpu_sboard_set_0; // @[RocketCore.scala:153:7, :1014:{52,67}] wire _id_stall_fpu_T_3 = _id_stall_fpu_T_2 & wb_valid; // @[RocketCore.scala:815:45, :1014:{67,89}] wire _id_stall_fpu_T_7 = _id_stall_fpu_T_3; // @[RocketCore.scala:1014:89, :1312:17] wire [31:0] _id_stall_fpu_T_5 = _id_stall_fpu_T_3 ? _id_stall_fpu_T_4 : 32'h0; // @[RocketCore.scala:1014:89, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_6 = _id_stall_fpu_r \| _id_stall_fpu_T_5; // @[RocketCore.scala:1300:60, :1305:29, :1309:49] wire _id_stall_fpu_v_ll_T = io_vector_resp_ready_0 & io_vector_resp_valid_0; // @[Decoupled.scala:51:35] wire id_stall_fpu_v_ll = _id_stall_fpu_v_ll_T & io_vector_resp_bits_fp_0; // @[Decoupled.scala:51:35] wire _id_stall_fpu_T_8 = dmem_resp_replay & dmem_resp_fpu; // @[RocketCore.scala:766:45, :769:42, :1016:39] wire _id_stall_fpu_T_9 = _id_stall_fpu_T_8 \| id_stall_fpu_v_ll; // @[RocketCore.scala:1015:47, :1016:{39,57}] wire [31:0] _id_stall_fpu_T_10 = 32'h1 << io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7, :1309:58] wire [31:0] _id_stall_fpu_T_11 = _id_stall_fpu_T_9 ? _id_stall_fpu_T_10 : 32'h0; // @[RocketCore.scala:1016:57, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_12 = ~_id_stall_fpu_T_11; // @[RocketCore.scala:1301:64, :1309:49] wire [31:0] _id_stall_fpu_T_13 = _id_stall_fpu_T_6 & _id_stall_fpu_T_12; // @[RocketCore.scala:1300:60, :1301:{62,64}] wire _id_stall_fpu_T_14 = _id_stall_fpu_T_7 \| _id_stall_fpu_T_9; // @[RocketCore.scala:1016:57, :1312:17] wire [31:0] _id_stall_fpu_T_15 = 32'h1 << io_fpu_sboard_clra_0; // @[RocketCore.scala:153:7, :1309:58] wire [31:0] _id_stall_fpu_T_16 = io_fpu_sboard_clr_0 ? _id_stall_fpu_T_15 : 32'h0; // @[RocketCore.scala:153:7, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_17 = ~_id_stall_fpu_T_16; // @[RocketCore.scala:1301:64, :1309:49] wire [31:0] _id_stall_fpu_T_18 = _id_stall_fpu_T_13 & _id_stall_fpu_T_17; // @[RocketCore.scala:1301:{62,64}] wire _id_stall_fpu_T_19 = _id_stall_fpu_T_14 \| io_fpu_sboard_clr_0; // @[RocketCore.scala:153:7, :1312:17] wire [31:0] _id_stall_fpu_T_20 = _id_stall_fpu_r >> _GEN_59; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_21 = _id_stall_fpu_T_20[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_22 = io_fpu_dec_ren1_0 & _id_stall_fpu_T_21; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_23 = _id_stall_fpu_r >> _GEN_60; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_24 = _id_stall_fpu_T_23[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_25 = io_fpu_dec_ren2_0 & _id_stall_fpu_T_24; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_26 = _id_stall_fpu_r >> id_raddr3; // @[RocketCore.scala:326:72, :1302:35, :1305:29] wire _id_stall_fpu_T_27 = _id_stall_fpu_T_26[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_28 = io_fpu_dec_ren3_0 & _id_stall_fpu_T_27; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_29 = _id_stall_fpu_r >> _GEN_61; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_30 = _id_stall_fpu_T_29[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_31 = io_fpu_dec_wen_0 & _id_stall_fpu_T_30; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire _id_stall_fpu_T_32 = _id_stall_fpu_T_22 \| _id_stall_fpu_T_25; // @[RocketCore.scala:1287:{27,50}] wire _id_stall_fpu_T_33 = _id_stall_fpu_T_32 \| _id_stall_fpu_T_28; // @[RocketCore.scala:1287:{27,50}] wire id_stall_fpu = _id_stall_fpu_T_33 \| _id_stall_fpu_T_31; // @[RocketCore.scala:1287:{27,50}] reg dcache_blocked_blocked; // @[RocketCore.scala:1024:22] wire _dcache_blocked_blocked_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45, :1025:16] wire _dcache_blocked_blocked_T_1 = _dcache_blocked_blocked_T; // @[RocketCore.scala:1025:{16,35}] wire _dcache_blocked_blocked_T_2 = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63] wire _dcache_blocked_blocked_T_3 = _dcache_blocked_blocked_T_1 & _dcache_blocked_blocked_T_2; // @[RocketCore.scala:1025:{35,60,63}] wire _dcache_blocked_blocked_T_4 = dcache_blocked_blocked \| io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :1024:22, :1025:95] wire _dcache_blocked_blocked_T_5 = _dcache_blocked_blocked_T_4 \| io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1025:{95,116}] wire _dcache_blocked_blocked_T_6 = _dcache_blocked_blocked_T_3 & _dcache_blocked_blocked_T_5; // @[RocketCore.scala:1025:{60,83,116}] wire _dcache_blocked_T = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63, :1026:16] wire dcache_blocked = dcache_blocked_blocked & _dcache_blocked_T; // @[RocketCore.scala:1024:22, :1026:{13,16}] reg rocc_blocked; // @[RocketCore.scala:1028:25] wire _rocc_blocked_T = ~wb_xcpt; // @[RocketCore.scala:815:48, :1029:19, :1278:14] wire _rocc_blocked_T_2 = _rocc_blocked_T; // @[RocketCore.scala:1029:{19,28}] wire _rocc_blocked_T_3 = io_rocc_cmd_valid \| rocc_blocked; // @[RocketCore.scala:153:7, :1028:25, :1029:72] wire _rocc_blocked_T_4 = _rocc_blocked_T_2 & _rocc_blocked_T_3; // @[RocketCore.scala:1029:{28,50,72}] wire _ctrl_stalld_T = id_ex_hazard \| id_mem_hazard; // @[RocketCore.scala:991:35, :1000:37, :1032:18] wire _ctrl_stalld_T_1 = _ctrl_stalld_T \| id_wb_hazard; // @[RocketCore.scala:1010:35, :1032:{18,35}] wire _ctrl_stalld_T_2 = _ctrl_stalld_T_1 \| id_sboard_hazard; // @[RocketCore.scala:1032:{35,51}, :1287:50] wire _ctrl_stalld_T_3 = _ctrl_stalld_T_2 \| id_vconfig_hazard; // @[RocketCore.scala:1002:39, :1032:{51,71}] wire _ctrl_stalld_T_4 = ex_reg_valid \| mem_reg_valid; // @[RocketCore.scala:248:35, :265:36, :1034:40] wire _ctrl_stalld_T_5 = _ctrl_stalld_T_4 \| wb_reg_valid; // @[RocketCore.scala:288:35, :1034:{40,57}] wire _ctrl_stalld_T_6 = _csr_io_singleStep & _ctrl_stalld_T_5; // @[RocketCore.scala:341:19, :1034:{23,57}] wire _ctrl_stalld_T_7 = _ctrl_stalld_T_3 \| _ctrl_stalld_T_6; // @[RocketCore.scala:1032:71, :1033:23, :1034:23] wire _ctrl_stalld_T_8 = id_csr_en & _csr_io_decode_0_fp_csr; // @[package.scala:81:59] wire _ctrl_stalld_T_9 = ~io_fpu_fcsr_rdy_0; // @[RocketCore.scala:153:7, :1035:45] wire _ctrl_stalld_T_10 = _ctrl_stalld_T_8 & _ctrl_stalld_T_9; // @[RocketCore.scala:1035:{15,42,45}] wire _ctrl_stalld_T_11 = _ctrl_stalld_T_7 \| _ctrl_stalld_T_10; // @[RocketCore.scala:1033:23, :1034:74, :1035:42] wire _ctrl_stalld_T_12 = id_csr_en & _csr_io_decode_0_vector_csr; // @[package.scala:81:59] wire _ctrl_stalld_T_13 = _ctrl_stalld_T_12 & id_vec_busy; // @[RocketCore.scala:409:55, :1036:{15,46}] wire _ctrl_stalld_T_14 = _ctrl_stalld_T_11 \| _ctrl_stalld_T_13; // @[RocketCore.scala:1034:74, :1035:62, :1036:46] wire _ctrl_stalld_T_15 = id_ctrl_fp & id_stall_fpu; // @[RocketCore.scala:321:21, :1037:16, :1287:50] wire _ctrl_stalld_T_16 = _ctrl_stalld_T_14 \| _ctrl_stalld_T_15; // @[RocketCore.scala:1035:62, :1036:61, :1037:16] wire _ctrl_stalld_T_17 = id_ctrl_mem & dcache_blocked; // @[RocketCore.scala:321:21, :1026:13, :1038:17] wire _ctrl_stalld_T_18 = _ctrl_stalld_T_16 \| _ctrl_stalld_T_17; // @[RocketCore.scala:1036:61, :1037:32, :1038:17] wire _ctrl_stalld_T_19 = id_ctrl_rocc & rocc_blocked; // @[RocketCore.scala:321:21, :1028:25, :1039:18] wire _ctrl_stalld_T_20 = _ctrl_stalld_T_18 \| _ctrl_stalld_T_19; // @[RocketCore.scala:1037:32, :1038:35, :1039:18] wire _ctrl_stalld_T_21 = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26, :1040:65] wire _ctrl_stalld_T_22 = _div_io_resp_valid & _ctrl_stalld_T_21; // @[RocketCore.scala:511:19, :1040:{62,65}] wire _ctrl_stalld_T_23 = _div_io_req_ready \| _ctrl_stalld_T_22; // @[RocketCore.scala:511:19, :1040:{40,62}] wire _ctrl_stalld_T_24 = ~_ctrl_stalld_T_23; // @[RocketCore.scala:1040:{21,40}] wire _ctrl_stalld_T_25 = _ctrl_stalld_T_24 \| _div_io_req_valid_T; // @[RocketCore.scala:512:36, :1040:{21,75}] wire _ctrl_stalld_T_26 = id_ctrl_div & _ctrl_stalld_T_25; // @[RocketCore.scala:321:21, :1040:{17,75}] wire _ctrl_stalld_T_27 = _ctrl_stalld_T_20 \| _ctrl_stalld_T_26; // @[RocketCore.scala:1038:35, :1039:34, :1040:17] wire _ctrl_stalld_T_29 = _ctrl_stalld_T_27; // @[RocketCore.scala:1039:34, :1040:96] wire _ctrl_stalld_T_30 = _ctrl_stalld_T_29 \| id_do_fence; // @[RocketCore.scala:410:32, :1040:96, :1041:15] wire _ctrl_stalld_T_31 = _ctrl_stalld_T_30 \| _csr_io_csr_stall; // @[RocketCore.scala:341:19, :1041:15, :1042:17] wire _ctrl_stalld_T_32 = _ctrl_stalld_T_31 \| id_reg_pause; // @[RocketCore.scala:161:25, :1042:17, :1043:22] wire ctrl_stalld = _ctrl_stalld_T_32; // @[RocketCore.scala:1043:22, :1044:18] wire _ctrl_killd_T = ~_ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :1046:17] wire _ctrl_killd_T_1 = _ctrl_killd_T \| _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :1046:{17,40}] wire _ctrl_killd_T_2 = _ctrl_killd_T_1 \| take_pc_mem_wb; // @[RocketCore.scala:307:35, :1046:{40,71}] wire _ctrl_killd_T_3 = _ctrl_killd_T_2 \| ctrl_stalld; // @[RocketCore.scala:1044:18, :1046:{71,89}] assign _ctrl_killd_T_4 = _ctrl_killd_T_3 \| _csr_io_interrupt; // @[RocketCore.scala:341:19, :1046:{89,104}] assign ctrl_killd = _ctrl_killd_T_4; // @[RocketCore.scala:338:24, :1046:104] assign _io_imem_req_bits_speculative_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1049:35] assign io_imem_req_bits_speculative_0 = _io_imem_req_bits_speculative_T; // @[RocketCore.scala:153:7, :1049:35] wire _io_imem_req_bits_pc_T = wb_xcpt \| _csr_io_eret; // @[RocketCore.scala:341:19, :1051:17, :1278:14] wire [39:0] _io_imem_req_bits_pc_T_1 = replay_wb ? wb_reg_pc : mem_npc; // @[RocketCore.scala:295:22, :619:139, :761:71, :1052:8] assign _io_imem_req_bits_pc_T_2 = _io_imem_req_bits_pc_T ? _csr_io_evec : _io_imem_req_bits_pc_T_1; // @[RocketCore.scala:341:19, :1051:{8,17}, :1052:8] assign io_imem_req_bits_pc_0 = _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:153:7, :1051:8] wire _io_imem_flush_icache_T = wb_reg_valid & wb_ctrl_fence_i; // @[RocketCore.scala:245:20, :288:35, :1054:40] wire _io_imem_flush_icache_T_1 = ~io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1054:62] assign _io_imem_flush_icache_T_2 = _io_imem_flush_icache_T & _io_imem_flush_icache_T_1; // @[RocketCore.scala:1054:{40,59,62}] assign io_imem_flush_icache_0 = _io_imem_flush_icache_T_2; // @[RocketCore.scala:153:7, :1054:59] wire _io_imem_might_request_imem_might_request_reg_T = ex_pc_valid \| mem_pc_valid; // @[RocketCore.scala:595:51, :614:54, :1056:43] wire _io_imem_might_request_imem_might_request_reg_T_1 = io_ptw_customCSRs_csrs_0_value_0[1]; // @[CustomCSRs.scala:44:61] wire _io_imem_might_request_imem_might_request_reg_T_2 = _io_imem_might_request_imem_might_request_reg_T \| _io_imem_might_request_imem_might_request_reg_T_1; // @[CustomCSRs.scala:44:61] wire _io_imem_might_request_imem_might_request_reg_T_3 = _io_imem_might_request_imem_might_request_reg_T_2; // @[RocketCore.scala:1056:{59,103}] wire _io_imem_progress_T = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47] wire _io_imem_progress_T_1 = wb_reg_valid & _io_imem_progress_T; // @[RocketCore.scala:288:35, :1059:{44,47}] reg io_imem_progress_REG; // @[RocketCore.scala:1059:30] assign io_imem_progress_0 = io_imem_progress_REG; // @[RocketCore.scala:153:7, :1059:30] assign _io_imem_sfence_valid_T = wb_reg_valid & wb_reg_sfence; // @[RocketCore.scala:288:35, :294:26, :1060:40] assign io_imem_sfence_valid_0 = _io_imem_sfence_valid_T; // @[RocketCore.scala:153:7, :1060:40] assign _io_imem_sfence_bits_rs1_T = wb_reg_mem_size[0]; // @[RocketCore.scala:296:28, :1061:45] assign io_imem_sfence_bits_rs1_0 = _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:153:7, :1061:45] assign _io_imem_sfence_bits_rs2_T = wb_reg_mem_size[1]; // @[RocketCore.scala:296:28, :1062:45] assign io_imem_sfence_bits_rs2_0 = _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:153:7, :1062:45] assign io_imem_sfence_bits_asid_0 = wb_reg_rs2[0]; // @[RocketCore.scala:153:7, :303:23, :1064:28] wire _ibuf_io_inst_0_ready_T = ~ctrl_stalld; // @[RocketCore.scala:1044:18, :1069:28] wire _io_imem_btb_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1071:48] wire _io_imem_btb_update_valid_T_1 = mem_reg_valid & _io_imem_btb_update_valid_T; // @[RocketCore.scala:265:36, :1071:{45,48}] wire _io_imem_btb_update_valid_T_2 = _io_imem_btb_update_valid_T_1 & mem_wrong_npc; // @[RocketCore.scala:621:8, :1071:{45,60}] wire _io_imem_btb_update_valid_T_3 = ~mem_cfi; // @[RocketCore.scala:625:50, :1071:81] wire _io_imem_btb_update_valid_T_4 = _io_imem_btb_update_valid_T_3 \| mem_cfi_taken; // @[RocketCore.scala:626:74, :1071:{81,90}] assign _io_imem_btb_update_valid_T_5 = _io_imem_btb_update_valid_T_2 & _io_imem_btb_update_valid_T_4; // @[RocketCore.scala:1071:{60,77,90}] assign io_imem_btb_update_valid_0 = _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:153:7, :1071:77] wire _GEN_67 = mem_ctrl_jal \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :1074:23] wire _io_imem_btb_update_bits_cfiType_T; // @[RocketCore.scala:1074:23] assign _io_imem_btb_update_bits_cfiType_T = _GEN_67; // @[RocketCore.scala:1074:23] wire _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:22] assign _io_imem_btb_update_bits_cfiType_T_8 = _GEN_67; // @[RocketCore.scala:1074:23, :1076:22] wire _io_imem_btb_update_bits_cfiType_T_1 = mem_waddr[0]; // @[RocketCore.scala:454:38, :1074:53] wire _io_imem_btb_update_bits_cfiType_T_2 = _io_imem_btb_update_bits_cfiType_T & _io_imem_btb_update_bits_cfiType_T_1; // @[RocketCore.scala:1074:{23,41,53}] wire [4:0] _io_imem_btb_update_bits_cfiType_T_3 = mem_reg_inst[19:15]; // @[RocketCore.scala:278:25, :1075:39] wire [4:0] _io_imem_btb_update_bits_cfiType_T_4 = _io_imem_btb_update_bits_cfiType_T_3; // @[RocketCore.scala:1075:{39,47}] wire [4:0] _io_imem_btb_update_bits_cfiType_T_5 = _io_imem_btb_update_bits_cfiType_T_4 & 5'h1B; // @[RocketCore.scala:1075:{47,64}] wire _io_imem_btb_update_bits_cfiType_T_6 = _io_imem_btb_update_bits_cfiType_T_5 == 5'h1; // @[RocketCore.scala:1075:64] wire _io_imem_btb_update_bits_cfiType_T_7 = mem_ctrl_jalr & _io_imem_btb_update_bits_cfiType_T_6; // @[RocketCore.scala:244:21, :1075:{23,64}] wire _io_imem_btb_update_bits_cfiType_T_9 = _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:{8,22}] wire [1:0] _io_imem_btb_update_bits_cfiType_T_10 = _io_imem_btb_update_bits_cfiType_T_7 ? 2'h3 : {1'h0, _io_imem_btb_update_bits_cfiType_T_9}; // @[RocketCore.scala:1075:{8,23}, :1076:8] assign _io_imem_btb_update_bits_cfiType_T_11 = _io_imem_btb_update_bits_cfiType_T_2 ? 2'h2 : _io_imem_btb_update_bits_cfiType_T_10; // @[RocketCore.scala:1074:{8,41}, :1075:8] assign io_imem_btb_update_bits_cfiType_0 = _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:153:7, :1074:8] assign io_imem_btb_update_bits_target_0 = io_imem_req_bits_pc_0[38:0]; // @[RocketCore.scala:153:7, :1078:34] wire [1:0] _io_imem_btb_update_bits_br_pc_T = {~mem_reg_rvc, 1'h0}; // @[RocketCore.scala:266:36, :1079:74] wire [40:0] _io_imem_btb_update_bits_br_pc_T_1 = {1'h0, mem_reg_pc} + {39'h0, _io_imem_btb_update_bits_br_pc_T}; // @[RocketCore.scala:277:23, :1079:{69,74}] wire [39:0] _io_imem_btb_update_bits_br_pc_T_2 = _io_imem_btb_update_bits_br_pc_T_1[39:0]; // @[RocketCore.scala:1079:69] assign io_imem_btb_update_bits_br_pc_0 = _io_imem_btb_update_bits_br_pc_T_2[38:0]; // @[RocketCore.scala:153:7, :1079:{33,69}] wire [38:0] _io_imem_btb_update_bits_pc_T = ~io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7, :1080:35] wire [38:0] _io_imem_btb_update_bits_pc_T_1 = {_io_imem_btb_update_bits_pc_T[38:2], 2'h3}; // @[RocketCore.scala:1080:{35,66}] assign _io_imem_btb_update_bits_pc_T_2 = ~_io_imem_btb_update_bits_pc_T_1; // @[RocketCore.scala:1080:{33,66}] assign io_imem_btb_update_bits_pc_0 = _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:153:7, :1080:33] wire _io_imem_bht_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1084:48] assign _io_imem_bht_update_valid_T_1 = mem_reg_valid & _io_imem_bht_update_valid_T; // @[RocketCore.scala:265:36, :1084:{45,48}] assign io_imem_bht_update_valid_0 = _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:153:7, :1084:45] wire _io_fpu_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :1094:19] assign _io_fpu_valid_T_1 = _io_fpu_valid_T & id_ctrl_fp; // @[RocketCore.scala:321:21, :1094:{19,31}] assign io_fpu_valid_0 = _io_fpu_valid_T_1; // @[RocketCore.scala:153:7, :1094:31] assign _io_fpu_keep_clock_enabled_T = io_ptw_customCSRs_csrs_0_value_0[2]; // @[CustomCSRs.scala:45:59] assign io_fpu_keep_clock_enabled_0 = _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59] wire _io_fpu_ll_resp_val_T_1 = io_vector_resp_valid_0 & io_vector_resp_bits_fp_0; // @[RocketCore.scala:153:7, :1109:42] assign io_fpu_ll_resp_val_0 = _T_168 ? _io_fpu_ll_resp_val_T : _io_fpu_ll_resp_val_T_1; // @[RocketCore.scala:153:7, :801:59, :1099:{22,41}, :1108:48, :1109:{26,42}] assign io_fpu_ll_resp_data_0 = _T_168 ? io_dmem_resp_bits_data_0 : io_vector_resp_bits_data_0; // @[RocketCore.scala:153:7, :801:59, :1100:23, :1108:48, :1110:27] assign io_fpu_ll_resp_type_0 = {1'h0, _T_168 ? io_dmem_resp_bits_size_0 : io_vector_resp_bits_size_0}; // @[RocketCore.scala:153:7, :801:59, :1101:23, :1108:48, :1111:27] assign io_fpu_ll_resp_tag_0 = _T_168 ? dmem_resp_waddr : io_vector_resp_bits_rd_0; // @[RocketCore.scala:153:7, :767:46, :801:59, :1102:22, :1108:48, :1112:26] wire _io_vector_ex_valid_T_1 = ex_ctrl_vec \| _io_vector_ex_valid_T; // @[RocketCore.scala:243:20, :1117:{48,90}] wire _io_vector_ex_valid_T_2 = ex_reg_valid & _io_vector_ex_valid_T_1; // @[RocketCore.scala:248:35, :1117:{32,48}] wire _io_vector_ex_valid_T_3 = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20, :1117:116] assign _io_vector_ex_valid_T_4 = _io_vector_ex_valid_T_2 & _io_vector_ex_valid_T_3; // @[RocketCore.scala:1117:{32,113,116}] assign io_vector_ex_valid_0 = _io_vector_ex_valid_T_4; // @[RocketCore.scala:153:7, :1117:113] wire _io_vector_ex_vstart_T = mem_reg_valid & mem_ctrl_vec; // @[RocketCore.scala:244:21, :265:36, :1120:38] wire _io_vector_ex_vstart_T_1 = wb_reg_valid & wb_ctrl_vec; // @[RocketCore.scala:245:20, :288:35, :1120:70] wire _io_vector_ex_vstart_T_2 = _io_vector_ex_vstart_T \| _io_vector_ex_vstart_T_1; // @[RocketCore.scala:1120:{38,54,70}] assign _io_vector_ex_vstart_T_3 = _io_vector_ex_vstart_T_2 ? 12'h0 : _csr_io_vector_vstart; // @[RocketCore.scala:341:19, :1120:{23,54}] assign io_vector_ex_vstart_0 = _io_vector_ex_vstart_T_3; // @[RocketCore.scala:153:7, :1120:23] assign _io_dmem_req_valid_T = ex_reg_valid & ex_ctrl_mem; // @[RocketCore.scala:243:20, :248:35, :1130:41] assign io_dmem_req_valid_0 = _io_dmem_req_valid_T; // @[RocketCore.scala:153:7, :1130:41] wire [5:0] ex_dcache_tag = {ex_waddr, ex_ctrl_fp}; // @[RocketCore.scala:243:20, :453:36, :1131:26] assign io_dmem_req_bits_tag_0 = {1'h0, ex_dcache_tag}; // @[RocketCore.scala:153:7, :1131:26, :1133:25] wire _io_dmem_req_bits_signed_T_1 = ex_reg_inst[14]; // @[RocketCore.scala:259:24, :1136:75] wire _io_dmem_req_bits_signed_T_2 = _io_dmem_req_bits_signed_T_1; // @[RocketCore.scala:1136:{34,75}] assign _io_dmem_req_bits_signed_T_3 = ~_io_dmem_req_bits_signed_T_2; // @[RocketCore.scala:1136:{30,34}] assign io_dmem_req_bits_signed_0 = _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:153:7, :1136:30] wire [24:0] _io_dmem_req_bits_addr_a_T = ex_rs_0[63:39]; // @[RocketCore.scala:469:14, :1293:17] wire [24:0] io_dmem_req_bits_addr_a = _io_dmem_req_bits_addr_a_T; // @[RocketCore.scala:1293:{17,23}] wire _io_dmem_req_bits_addr_msb_T = io_dmem_req_bits_addr_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _io_dmem_req_bits_addr_msb_T_1 = &io_dmem_req_bits_addr_a; // @[RocketCore.scala:1293:23, :1294:34] wire _io_dmem_req_bits_addr_msb_T_2 = _io_dmem_req_bits_addr_msb_T \| _io_dmem_req_bits_addr_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _io_dmem_req_bits_addr_msb_T_3 = _alu_io_adder_out[39]; // @[RocketCore.scala:504:19, :1294:46] wire _io_dmem_req_bits_addr_msb_T_4 = _alu_io_adder_out[38]; // @[RocketCore.scala:504:19, :1294:54] wire _io_dmem_req_bits_addr_msb_T_5 = ~_io_dmem_req_bits_addr_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire io_dmem_req_bits_addr_msb = _io_dmem_req_bits_addr_msb_T_2 ? _io_dmem_req_bits_addr_msb_T_3 : _io_dmem_req_bits_addr_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] wire [38:0] _io_dmem_req_bits_addr_T = _alu_io_adder_out[38:0]; // @[RocketCore.scala:504:19, :1295:16] assign _io_dmem_req_bits_addr_T_1 = {io_dmem_req_bits_addr_msb, _io_dmem_req_bits_addr_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}] assign io_dmem_req_bits_addr_0 = _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:153:7, :1295:8] assign io_dmem_req_bits_dprv_0 = _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:153:7, :1140:31] assign io_dmem_req_bits_dv_0 = _io_dmem_req_bits_dv_T; // @[RocketCore.scala:153:7, :1141:37] wire _io_dmem_req_bits_no_resp_T_4 = _io_dmem_req_bits_no_resp_T \| _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_5 = _io_dmem_req_bits_no_resp_T_4 \| _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_6 = _io_dmem_req_bits_no_resp_T_5 \| _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_11 = _io_dmem_req_bits_no_resp_T_7 \| _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_12 = _io_dmem_req_bits_no_resp_T_11 \| _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_13 = _io_dmem_req_bits_no_resp_T_12 \| _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_19 = _io_dmem_req_bits_no_resp_T_14 \| _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_20 = _io_dmem_req_bits_no_resp_T_19 \| _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_21 = _io_dmem_req_bits_no_resp_T_20 \| _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_22 = _io_dmem_req_bits_no_resp_T_21 \| _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_23 = _io_dmem_req_bits_no_resp_T_13 \| _io_dmem_req_bits_no_resp_T_22; // @[package.scala:81:59] wire _io_dmem_req_bits_no_resp_T_24 = _io_dmem_req_bits_no_resp_T_6 \| _io_dmem_req_bits_no_resp_T_23; // @[package.scala:81:59] wire _io_dmem_req_bits_no_resp_T_25 = ~_io_dmem_req_bits_no_resp_T_24; // @[RocketCore.scala:1142:31] wire _io_dmem_req_bits_no_resp_T_26 = ~ex_ctrl_fp; // @[RocketCore.scala:243:20, :1142:60] wire _io_dmem_req_bits_no_resp_T_27 = ex_waddr == 5'h0; // @[RocketCore.scala:453:36, :1142:84] wire _io_dmem_req_bits_no_resp_T_28 = _io_dmem_req_bits_no_resp_T_26 & _io_dmem_req_bits_no_resp_T_27; // @[RocketCore.scala:1142:{60,72,84}] assign _io_dmem_req_bits_no_resp_T_29 = _io_dmem_req_bits_no_resp_T_25 \| _io_dmem_req_bits_no_resp_T_28; // @[RocketCore.scala:1142:{31,56,72}] assign io_dmem_req_bits_no_resp_0 = _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:153:7, :1142:56] wire [76:0] _io_dmem_s1_data_data_T = mem_ctrl_fp ? {13'h0, io_fpu_store_data_0} : mem_reg_rs2; // @[RocketCore.scala:153:7, :244:21, :283:24, :1148:63] assign io_dmem_s1_data_data_0 = _io_dmem_s1_data_data_T[63:0]; // @[RocketCore.scala:153:7, :1148:{24,63}] wire _io_dmem_s1_kill_T = killm_common \| mem_ldst_xcpt; // @[RocketCore.scala:700:68, :1151:35, :1278:14] wire _io_dmem_s1_kill_T_1 = _io_dmem_s1_kill_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :1151:{35,52}] assign _io_dmem_s1_kill_T_2 = _io_dmem_s1_kill_T_1 \| vec_kill_mem; // @[RocketCore.scala:697:52, :1151:{52,68}] assign io_dmem_s1_kill_0 = _io_dmem_s1_kill_T_2; // @[RocketCore.scala:153:7, :1151:68] wire _io_dmem_keep_clock_enabled_T = _ibuf_io_inst_0_valid & id_ctrl_mem; // @[RocketCore.scala:311:20, :321:21, :1154:55] wire _io_dmem_keep_clock_enabled_T_1 = ~_csr_io_csr_stall; // @[RocketCore.scala:341:19, :1154:73] assign _io_dmem_keep_clock_enabled_T_2 = _io_dmem_keep_clock_enabled_T & _io_dmem_keep_clock_enabled_T_1; // @[RocketCore.scala:1154:{55,70,73}] assign io_dmem_keep_clock_enabled_0 = _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:153:7, :1154:70] wire _io_rocc_cmd_valid_T_1 = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47, :1156:56] assign _io_rocc_cmd_valid_T_2 = _io_rocc_cmd_valid_T & _io_rocc_cmd_valid_T_1; // @[RocketCore.scala:1156:{37,53,56}] assign io_rocc_cmd_valid = _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:153:7, :1156:53] wire [6:0] _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_funct = _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rs2 = _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rs1 = _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xd = _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xs1 = _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xs2 = _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rd = _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:153:7, :1159:48] wire [6:0] _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_opcode = _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:153:7, :1159:48] assign _io_rocc_cmd_bits_inst_T = _io_rocc_cmd_bits_inst_WIRE_1[6:0]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_opcode = _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_1 = _io_rocc_cmd_bits_inst_WIRE_1[11:7]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rd = _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_2 = _io_rocc_cmd_bits_inst_WIRE_1[12]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xs2 = _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_3 = _io_rocc_cmd_bits_inst_WIRE_1[13]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xs1 = _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_4 = _io_rocc_cmd_bits_inst_WIRE_1[14]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xd = _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_5 = _io_rocc_cmd_bits_inst_WIRE_1[19:15]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rs1 = _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_6 = _io_rocc_cmd_bits_inst_WIRE_1[24:20]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rs2 = _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_7 = _io_rocc_cmd_bits_inst_WIRE_1[31:25]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_funct = _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_rs2 = wb_reg_rs2[63:0]; // @[RocketCore.scala:153:7, :303:23, :1161:24] wire [4:0] _unpause_T = _csr_io_time[4:0]; // @[RocketCore.scala:341:19, :1164:28] wire _unpause_T_1 = _unpause_T == 5'h0; // @[RocketCore.scala:1164:{28,62}] wire _unpause_T_2 = _unpause_T_1 \| _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19, :1164:{62,70}] wire _unpause_T_3 = _unpause_T_2 \| io_dmem_perf_release_0; // @[RocketCore.scala:153:7, :1164:{70,94}] wire unpause = _unpause_T_3 \| take_pc_mem_wb; // @[RocketCore.scala:307:35, :1164:{94,118}] reg icache_blocked_REG; // @[RocketCore.scala:1183:55] wire _icache_blocked_T = io_imem_resp_valid_0 \| icache_blocked_REG; // @[RocketCore.scala:153:7, :1183:{45,55}] wire icache_blocked = ~_icache_blocked_T; // @[RocketCore.scala:1183:{24,45}] wire _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1192:52] wire [63:0] _coreMonitorBundle_pc_T_3; // @[package.scala:132:15] wire _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1194:37] wire [4:0] _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1198:42] wire [4:0] _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1200:42] wire coreMonitorBundle_excpt; // @[RocketCore.scala:1186:31] wire [2:0] coreMonitorBundle_priv_mode; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_hartid; // @[RocketCore.scala:1186:31] wire [31:0] coreMonitorBundle_timer; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_valid; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_pc; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_wrenx; // @[RocketCore.scala:1186:31] wire [4:0] coreMonitorBundle_rd0src; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_rd0val; // @[RocketCore.scala:1186:31] wire [4:0] coreMonitorBundle_rd1src; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_rd1val; // @[RocketCore.scala:1186:31] wire [31:0] coreMonitorBundle_inst; // @[RocketCore.scala:1186:31] wire [63:0] _GEN_68 = {63'h0, io_hartid_0}; // @[RocketCore.scala:153:7, :1190:28] assign coreMonitorBundle_hartid = _GEN_68; // @[RocketCore.scala:1186:31, :1190:28] wire [63:0] xrfWriteBundle_hartid; // @[RocketCore.scala:1249:28] assign xrfWriteBundle_hartid = _GEN_68; // @[RocketCore.scala:1190:28, :1249:28] assign coreMonitorBundle_timer = _coreMonitorBundle_timer_T; // @[RocketCore.scala:1186:31, :1191:41] wire _coreMonitorBundle_valid_T = ~_csr_io_trace_0_exception; // @[RocketCore.scala:341:19, :1192:55] assign _coreMonitorBundle_valid_T_1 = _csr_io_trace_0_valid & _coreMonitorBundle_valid_T; // @[RocketCore.scala:341:19, :1192:{52,55}] assign coreMonitorBundle_valid = _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1186:31, :1192:52] wire [39:0] _coreMonitorBundle_pc_T; // @[RocketCore.scala:1193:48] wire _coreMonitorBundle_pc_T_1 = _coreMonitorBundle_pc_T[39]; // @[package.scala:132:38] wire [23:0] _coreMonitorBundle_pc_T_2 = {24{_coreMonitorBundle_pc_T_1}}; // @[package.scala:132:{20,38}] assign _coreMonitorBundle_pc_T_3 = {_coreMonitorBundle_pc_T_2, _coreMonitorBundle_pc_T}; // @[package.scala:132:{15,20}] assign coreMonitorBundle_pc = _coreMonitorBundle_pc_T_3; // @[package.scala:132:15] wire _coreMonitorBundle_wrenx_T = ~wb_set_sboard; // @[RocketCore.scala:756:69, :1194:40] assign _coreMonitorBundle_wrenx_T_1 = wb_wen & _coreMonitorBundle_wrenx_T; // @[RocketCore.scala:816:25, :1194:{37,40}] assign coreMonitorBundle_wrenx = _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1186:31, :1194:37] assign _coreMonitorBundle_rd0src_T = wb_reg_inst[19:15]; // @[RocketCore.scala:300:24, :1198:42] assign coreMonitorBundle_rd0src = _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1186:31, :1198:42] reg [63:0] coreMonitorBundle_rd0val_REG; // @[RocketCore.scala:1199:46] reg [63:0] coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1199:38] assign coreMonitorBundle_rd0val = coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1186:31, :1199:38] assign _coreMonitorBundle_rd1src_T = wb_reg_inst[24:20]; // @[RocketCore.scala:300:24, :1200:42] assign coreMonitorBundle_rd1src = _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1186:31, :1200:42] reg [63:0] coreMonitorBundle_rd1val_REG; // @[RocketCore.scala:1201:46] reg [63:0] coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1201:38] assign coreMonitorBundle_rd1val = coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1186:31, :1201:38]
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_220( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_476 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_139( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_153 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_511( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_255 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_32( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File BaseTile.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util.{log2Ceil, log2Up} import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.bundlebridge._ import freechips.rocketchip.resources.{PropertyMap, PropertyOption, ResourceReference, DTSTimebase} import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode} import freechips.rocketchip.rocket.{ICacheParams, DCacheParams, BTBParams, ASIdBits, VMIdBits, TraceAux, BPWatch} import freechips.rocketchip.subsystem.{ HierarchicalElementParams, InstantiableHierarchicalElementParams, HierarchicalElementCrossingParamsLike, CacheBlockBytes, SystemBusKey, BaseHierarchicalElement, InsertTimingClosureRegistersOnHartIds, BaseHierarchicalElementModuleImp } import freechips.rocketchip.tilelink.{TLEphemeralNode, TLOutwardNode, TLNode, TLFragmenter, EarlyAck, TLWidthWidget, TLManagerParameters, ManagerUnification} import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters} import freechips.rocketchip.util.{TraceCoreParams, TraceCoreInterface} import freechips.rocketchip.resources.{BigIntToProperty, IntToProperty, StringToProperty} import freechips.rocketchip.util.BooleanToAugmentedBoolean case object TileVisibilityNodeKey extends Field[TLEphemeralNode] case object TileKey extends Field[TileParams] case object LookupByHartId extends Field[LookupByHartIdImpl] trait TileParams extends HierarchicalElementParams { val core: CoreParams val icache: Option[ICacheParams] val dcache: Option[DCacheParams] val btb: Option[BTBParams] val tileId: Int // may not be hartid val blockerCtrlAddr: Option[BigInt] } abstract class InstantiableTileParams[TileType <: BaseTile] extends InstantiableHierarchicalElementParams[TileType] with TileParams { def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl) (implicit p: Parameters): TileType } /** These parameters values are not computed based on diplomacy negotiation * and so are safe to use while diplomacy itself is running. / trait HasNonDiplomaticTileParameters { implicit val p: Parameters def tileParams: TileParams = p(TileKey) def usingVM: Boolean = tileParams.core.useVM def usingUser: Boolean = tileParams.core.useUser \|\| usingSupervisor def usingSupervisor: Boolean = tileParams.core.hasSupervisorMode def usingHypervisor: Boolean = usingVM && tileParams.core.useHypervisor def usingDebug: Boolean = tileParams.core.useDebug def usingRoCC: Boolean = !p(BuildRoCC).isEmpty def usingBTB: Boolean = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0 def usingPTW: Boolean = usingVM def usingDataScratchpad: Boolean = tileParams.dcache.flatMap(_.scratch).isDefined def xLen: Int = tileParams.core.xLen def xBytes: Int = xLen / 8 def iLen: Int = 32 def pgIdxBits: Int = 12 def pgLevelBits: Int = 10 - log2Ceil(xLen / 32) def pgLevels: Int = tileParams.core.pgLevels def maxSVAddrBits: Int = pgIdxBits + pgLevels pgLevelBits def maxHypervisorExtraAddrBits: Int = 2 def hypervisorExtraAddrBits: Int = { if (usingHypervisor) maxHypervisorExtraAddrBits else 0 } def maxHVAddrBits: Int = maxSVAddrBits + hypervisorExtraAddrBits def minPgLevels: Int = { val res = xLen match { case 32 => 2; case 64 => 3 } require(pgLevels >= res) res } def asIdBits: Int = p(ASIdBits) def vmIdBits: Int = p(VMIdBits) lazy val maxPAddrBits: Int = { require(xLen == 32 \|\| xLen == 64, s"Only XLENs of 32 or 64 are supported, but got $xLen") xLen match { case 32 => 34; case 64 => 56 } } def tileId: Int = tileParams.tileId def cacheBlockBytes = p(CacheBlockBytes) def lgCacheBlockBytes = log2Up(cacheBlockBytes) def masterPortBeatBytes = p(SystemBusKey).beatBytes // TODO make HellaCacheIO diplomatic and remove this brittle collection of hacks // Core PTW DTIM coprocessors def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size + (tileParams.core.useVector && tileParams.core.vectorUseDCache).toInt // TODO merge with isaString in CSR.scala def isaDTS: String = { val ie = if (tileParams.core.useRVE) "e" else "i" val m = if (tileParams.core.mulDiv.nonEmpty) "m" else "" val a = if (tileParams.core.useAtomics) "a" else "" val f = if (tileParams.core.fpu.nonEmpty) "f" else "" val d = if (tileParams.core.fpu.nonEmpty && tileParams.core.fpu.get.fLen > 32) "d" else "" val c = if (tileParams.core.useCompressed) "c" else "" val b = if (tileParams.core.useBitmanip) "b" else "" val v = if (tileParams.core.useVector && tileParams.core.vLen >= 128 && tileParams.core.eLen == 64 && tileParams.core.vfLen == 64) "v" else "" val h = if (usingHypervisor) "h" else "" val ext_strs = Seq( (tileParams.core.useVector) -> s"zvl${tileParams.core.vLen}b", (tileParams.core.useVector) -> { val c = tileParams.core.vfLen match { case 64 => "d" case 32 => "f" case 0 => "x" } s"zve${tileParams.core.eLen}$c" }, (tileParams.core.useVector && tileParams.core.vfh) -> "zvfh", (tileParams.core.fpu.map(_.fLen >= 16).getOrElse(false) && tileParams.core.minFLen <= 16) -> "zfh", (tileParams.core.useZba) -> "zba", (tileParams.core.useZbb) -> "zbb", (tileParams.core.useZbs) -> "zbs", (tileParams.core.useConditionalZero) -> "zicond" ).filter(_._1).map(_._2) val multiLetterExt = ( // rdcycle[h], rdinstret[h] is implemented // rdtime[h] is not implemented, and could be provided by software emulation // see https://github.com/chipsalliance/rocket-chip/issues/3207 //Some(Seq("zicntr")) ++ Some(Seq("zicsr", "zifencei", "zihpm")) ++ Some(ext_strs) ++ Some(tileParams.core.vExts) ++ tileParams.core.customIsaExt.map(Seq(_)) ).flatten val multiLetterString = multiLetterExt.mkString("_") s"rv$xLen$ie$m$a$f$d$c$b$v$h$multiLetterString" } def tileProperties: PropertyMap = { val dcache = tileParams.dcache.filter(!_.scratch.isDefined).map(d => Map( "d-cache-block-size" -> cacheBlockBytes.asProperty, "d-cache-sets" -> d.nSets.asProperty, "d-cache-size" -> (d.nSets * d.nWays * cacheBlockBytes).asProperty) ).getOrElse(Nil) val incoherent = if (!tileParams.core.useAtomicsOnlyForIO) Nil else Map( "sifive,d-cache-incoherent" -> Nil) val icache = tileParams.icache.map(i => Map( "i-cache-block-size" -> cacheBlockBytes.asProperty, "i-cache-sets" -> i.nSets.asProperty, "i-cache-size" -> (i.nSets * i.nWays * cacheBlockBytes).asProperty) ).getOrElse(Nil) val dtlb = tileParams.dcache.filter(_ => tileParams.core.useVM).map(d => Map( "d-tlb-size" -> (d.nTLBWays * d.nTLBSets).asProperty, "d-tlb-sets" -> d.nTLBSets.asProperty)).getOrElse(Nil) val itlb = tileParams.icache.filter(_ => tileParams.core.useVM).map(i => Map( "i-tlb-size" -> (i.nTLBWays * i.nTLBSets).asProperty, "i-tlb-sets" -> i.nTLBSets.asProperty)).getOrElse(Nil) val mmu = if (tileParams.core.useVM) { if (tileParams.core.useHypervisor) { Map("tlb-split" -> Nil, "mmu-type" -> s"riscv,sv${maxSVAddrBits},sv${maxSVAddrBits}x4".asProperty) } else { Map("tlb-split" -> Nil, "mmu-type" -> s"riscv,sv$maxSVAddrBits".asProperty) } } else { Nil } val pmp = if (tileParams.core.nPMPs > 0) Map( "riscv,pmpregions" -> tileParams.core.nPMPs.asProperty, "riscv,pmpgranularity" -> tileParams.core.pmpGranularity.asProperty) else Nil dcache ++ icache ++ dtlb ++ itlb ++ mmu ++ pmp ++ incoherent } } /** These parameters values are computed based on diplomacy negotiations * and so are NOT safe to use while diplomacy itself is running. * Only mix this trait into LazyModuleImps, Modules, Bundles, Data, etc. / trait HasTileParameters extends HasNonDiplomaticTileParameters { protected def tlBundleParams = p(TileVisibilityNodeKey).edges.out.head.bundle lazy val paddrBits: Int = { val bits = tlBundleParams.addressBits require(bits <= maxPAddrBits, s"Requested $bits paddr bits, but since xLen is $xLen only $maxPAddrBits will fit") bits } def vaddrBits: Int = if (usingVM) { val v = maxHVAddrBits require(v == xLen \|\| xLen > v && v > paddrBits) v } else { // since virtual addresses sign-extend but physical addresses // zero-extend, make room for a zero sign bit for physical addresses (paddrBits + 1) min xLen } def vpnBits: Int = vaddrBits - pgIdxBits def ppnBits: Int = paddrBits - pgIdxBits def vpnBitsExtended: Int = vpnBits + (if (vaddrBits < xLen) 1 + usingHypervisor.toInt else 0) def vaddrBitsExtended: Int = vpnBitsExtended + pgIdxBits } /* Base class for all Tiles that use TileLink / abstract class BaseTile private (crossing: ClockCrossingType, q: Parameters) extends BaseHierarchicalElement(crossing)(q) with HasNonDiplomaticTileParameters { // Public constructor alters Parameters to supply some legacy compatibility keys def this(tileParams: TileParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, p: Parameters) = { this(crossing, p.alterMap(Map( TileKey -> tileParams, TileVisibilityNodeKey -> TLEphemeralNode()(ValName("tile_master")), LookupByHartId -> lookup ))) } def intInwardNode: IntInwardNode // Interrupts to the core from external devices def intOutwardNode: Option[IntOutwardNode] // Interrupts from tile-internal devices (e.g. BEU) def haltNode: IntOutwardNode // Unrecoverable error has occurred; suggest reset def ceaseNode: IntOutwardNode // Tile has ceased to retire instructions def wfiNode: IntOutwardNode // Tile is waiting for an interrupt def module: BaseTileModuleImp[BaseTile] /* Node for broadcasting a hart id to diplomatic consumers within the tile. / val hartIdNexusNode: BundleBridgeNode[UInt] = BundleBroadcast[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) /* Node for consuming the hart id input in tile-layer Chisel logic. / val hartIdSinkNode = BundleBridgeSink[UInt]() /* Node for driving a hart id input, which is to be broadcast to units within the tile. * * Making this id value an IO and then using it to do lookups of information * that would make otherwise-homogeneous tiles heterogeneous is a useful trick * to enable deduplication of tiles for hierarchical P&R flows. / val hartIdNode: BundleBridgeInwardNode[UInt] = hartIdSinkNode := hartIdNexusNode := BundleBridgeNameNode("hartid") /* Node for broadcasting a reset vector to diplomatic consumers within the tile. / val resetVectorNexusNode: BundleBridgeNode[UInt] = BundleBroadcast[UInt]() /* Node for consuming the reset vector input in tile-layer Chisel logic. * * Its width is sized by looking at the size of the address space visible * on the tile's master ports, but this lookup is not evaluated until * diplomacy has completed and Chisel elaboration has begun. / val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(visiblePhysAddrBits.W))) /* Node for supplying a reset vector that processors in this tile might begin fetching instructions from as they come out of reset. / val resetVectorNode: BundleBridgeInwardNode[UInt] = resetVectorSinkNode := resetVectorNexusNode := BundleBridgeNameNode("reset_vector") /* Nodes for connecting NMI interrupt sources and vectors into the tile / val nmiSinkNode = Option.when(tileParams.core.useNMI) { BundleBridgeSink[NMI](Some(() => new NMI(visiblePhysAddrBits))) } val nmiNode: Option[BundleBridgeInwardNode[NMI]] = nmiSinkNode.map(_ := BundleBridgeNameNode("nmi")) /* Node for broadcasting an address prefix to diplomatic consumers within the tile. * * The prefix should be applied by consumers by or-ing ouputs of this node * with a static base address (which is looked up based on the driven hartid value). / val mmioAddressPrefixNexusNode = BundleBridgeNexus[UInt]( inputFn = BundleBridgeNexus.orReduction[UInt](registered = false) _, outputFn = BundleBridgeNexus.fillN[UInt](registered = false) _, default = Some(() => 0.U(1.W)) ) /* Node for external drivers to prefix base addresses of MMIO devices to which the core has a direct access path. / val mmioAddressPrefixNode: BundleBridgeInwardNode[UInt] = mmioAddressPrefixNexusNode := BundleBridgeNameNode("mmio_address_prefix") // TODO: Any node marked "consumed by the core" or "driven by the core" // should be moved to either be: a member of a specific BaseTile subclass, // or actually just a member of the core's LazyModule itself, // assuming the core itself is diplomatic. // Then these nodes should just become IdentityNodes of their respective type protected def traceRetireWidth = tileParams.core.retireWidth /** Node for the core to drive legacy "raw" instruction trace. / val traceSourceNode = BundleBridgeSource(() => new TraceBundle) /* Node for external consumers to source a legacy instruction trace from the core. / val traceNode = traceSourceNode def traceCoreParams = new TraceCoreParams() /* Node for core to drive instruction trace conforming to RISC-V Processor Trace spec V1.0 / val traceCoreSourceNode = BundleBridgeSource(() => new TraceCoreInterface(traceCoreParams)) /* Node for external consumers to source a V1.0 instruction trace from the core. / val traceCoreNode = traceCoreSourceNode /* Node to broadcast collected trace sideband signals into the tile. / val traceAuxNexusNode = BundleBridgeNexus[TraceAux](default = Some(() => { val aux = Wire(new TraceAux) aux.stall := false.B aux.enable := false.B aux })) /* Trace sideband signals to be consumed by the core. / val traceAuxSinkNode = BundleBridgeSink[TraceAux]() /* Trace sideband signals collected here to be driven into the tile. / val traceAuxNode: BundleBridgeInwardNode[TraceAux] = traceAuxSinkNode := traceAuxNexusNode := BundleBridgeNameNode("trace_aux") /** Node for watchpoints to control trace driven by core. / val bpwatchSourceNode = BundleBridgeSource(() => Vec(tileParams.core.nBreakpoints, new BPWatch(traceRetireWidth))) /* Node to broadcast watchpoints to control trace. / val bpwatchNexusNode = BundleBroadcast[Vec[BPWatch]]() /* Node for external consumers to source watchpoints to control trace. / val bpwatchNode: BundleBridgeOutwardNode[Vec[BPWatch]] = BundleBridgeNameNode("bpwatch") := bpwatchNexusNode := bpwatchSourceNode /** Helper function for connecting MMIO devices inside the tile to an xbar that will make them visible to external masters. / def connectTLSlave(xbarNode: TLOutwardNode, node: TLNode, bytes: Int): Unit = { DisableMonitors { implicit p => (Seq(node, TLFragmenter(bytes, cacheBlockBytes, earlyAck=EarlyAck.PutFulls)) ++ (xBytes != bytes).option(TLWidthWidget(xBytes))) .foldRight(xbarNode)(_ := _) } } def connectTLSlave(node: TLNode, bytes: Int): Unit = { connectTLSlave(tlSlaveXbar.node, node, bytes) } /** TileLink node which represents the view that the intra-tile masters have of the rest of the system. / val visibilityNode = p(TileVisibilityNodeKey) protected def visibleManagers = visibilityNode.edges.out.flatMap(_.manager.managers) protected def visiblePhysAddrBits = visibilityNode.edges.out.head.bundle.addressBits def unifyManagers: List[TLManagerParameters] = ManagerUnification(visibleManagers) /* Finds resource labels for all the outward caches. / def nextLevelCacheProperty: PropertyOption = { val outer = visibleManagers .filter(_.supportsAcquireB) .flatMap(_.resources.headOption) .map(_.owner.label) .distinct if (outer.isEmpty) None else Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList) } /* Create a DTS representation of this "cpu". / def cpuProperties: PropertyMap = Map( "device_type" -> "cpu".asProperty, "status" -> "okay".asProperty, "clock-frequency" -> tileParams.core.bootFreqHz.asProperty, "riscv,isa" -> isaDTS.asProperty, "timebase-frequency" -> p(DTSTimebase).asProperty, "hardware-exec-breakpoint-count" -> tileParams.core.nBreakpoints.asProperty ) /* Can be used to access derived params calculated by HasCoreParameters * * However, callers must ensure they do not access a diplomatically-determined parameter * before the graph in question has been fully connected. / protected lazy val lazyCoreParamsView: HasCoreParameters = { class C(implicit val p: Parameters) extends HasCoreParameters new C } this.suggestName(tileParams.baseName) } abstract class BaseTileModuleImp[+L <: BaseTile](outer: L) extends BaseHierarchicalElementModuleImp[L](outer) File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSetsblockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined \|\| nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined \|\| nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBitsrowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /* Bundle definitions for HellaCache interfaces / trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /* Base classes for Diplomatic TL2 HellaCaches / abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB \|\| !m.executable \|\| m.regionType >= RegionType.TRACKED \|\| m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM \|\| cfg.blockBytes cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush \|\| cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated / case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /* Mix-ins for constructing tiles that have a HellaCache / trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /* Metadata array used for all HellaCaches / class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst \|\| io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst } File Interrupts.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.resources.{Device, DeviceSnippet, Description, ResourceBinding, ResourceInt} import freechips.rocketchip.interrupts.{IntIdentityNode, IntSinkNode, IntSinkPortSimple, IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.util.CanHaveErrors import freechips.rocketchip.resources.{IntToProperty, StringToProperty} import freechips.rocketchip.util.BooleanToAugmentedBoolean class NMI(val w: Int) extends Bundle { val rnmi = Bool() val rnmi_interrupt_vector = UInt(w.W) val rnmi_exception_vector = UInt(w.W) } class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) { val debug = Bool() val mtip = Bool() val msip = Bool() val meip = Bool() val seip = usingSupervisor.option(Bool()) val lip = Vec(coreParams.nLocalInterrupts, Bool()) val nmi = usingNMI.option(new NMI(resetVectorLen)) } // Use diplomatic interrupts to external interrupts from the subsystem into the tile trait SinksExternalInterrupts { this: BaseTile => val intInwardNode = intXbar.intnode := IntIdentityNode()(ValName("int_local")) protected val intSinkNode = IntSinkNode(IntSinkPortSimple()) intSinkNode := intXbar.intnode def cpuDevice: Device val intcDevice = new DeviceSnippet { override def parent = Some(cpuDevice) def describe(): Description = { Description("interrupt-controller", Map( "compatible" -> "riscv,cpu-intc".asProperty, "interrupt-controller" -> Nil, "#interrupt-cells" -> 1.asProperty)) } } ResourceBinding { intSinkNode.edges.in.flatMap(_.source.sources).map { case s => for (i <- s.range.start until s.range.end) { csrIntMap.lift(i).foreach { j => s.resources.foreach { r => r.bind(intcDevice, ResourceInt(j)) } } } } } // TODO: the order of the following two functions must match, and // also match the order which things are connected to the // per-tile crossbar in subsystem.HasTiles.connectInterrupts // debug, msip, mtip, meip, seip, lip offsets in CSRs def csrIntMap: List[Int] = { val nlips = tileParams.core.nLocalInterrupts val seip = if (usingSupervisor) Seq(9) else Nil List(65535, 3, 7, 11) ++ seip ++ List.tabulate(nlips)(_ + 16) } // go from flat diplomatic Interrupts to bundled TileInterrupts def decodeCoreInterrupts(core: TileInterrupts): Unit = { val async_ips = Seq(core.debug) val periph_ips = Seq( core.msip, core.mtip, core.meip) val seip = if (core.seip.isDefined) Seq(core.seip.get) else Nil val core_ips = core.lip val (interrupts, _) = intSinkNode.in(0) (async_ips ++ periph_ips ++ seip ++ core_ips).zip(interrupts).foreach { case(c, i) => c := i } } } trait SourcesExternalNotifications { this: BaseTile => // Report unrecoverable error conditions val haltNode = IntSourceNode(IntSourcePortSimple()) def reportHalt(could_halt: Option[Bool]): Unit = { val (halt_and_catch_fire, _) = haltNode.out(0) halt_and_catch_fire(0) := could_halt.map(RegEnable(true.B, false.B, _)).getOrElse(false.B) } def reportHalt(errors: Seq[CanHaveErrors]): Unit = { reportHalt(errors.flatMap(_.uncorrectable).map(_.valid).reduceOption(_\|\|_)) } // Report when the tile has ceased to retire instructions val ceaseNode = IntSourceNode(IntSourcePortSimple()) def reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8): Unit = { def waitForQuiescence(cease: Bool): Bool = { // don't report cease until signal is stable for longer than any pipeline depth val count = RegInit(0.U(log2Ceil(quiescenceCycles + 1).W)) val saturated = count >= quiescenceCycles.U when (!cease) { count := 0.U } when (cease && !saturated) { count := count + 1.U } saturated } val (cease, _) = ceaseNode.out(0) cease(0) := could_cease.map{ c => val cease = (waitForQuiescence(c)) // Test-Only Code -- val prev_cease = RegNext(cease, false.B) assert(!(prev_cease & !cease), "CEASE line can not glitch once raised") cease }.getOrElse(false.B) } // Report when the tile is waiting for an interrupt val wfiNode = IntSourceNode(IntSourcePortSimple()) def reportWFI(could_wfi: Option[Bool]): Unit = { val (wfi, _) = wfiNode.out(0) wfi(0) := could_wfi.map(RegNext(_, init=false.B)).getOrElse(false.B) } } File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in \|\| corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ \|\| !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready \|\| !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel \| count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)outByteswidth-1, ioutByteswidth) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes8-1, edgeOut.manager.beatBytes8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File Frontend.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.tile.{CoreBundle, BaseTile} import freechips.rocketchip.tilelink.{TLWidthWidget, TLEdgeOut} import freechips.rocketchip.util.{ClockGate, ShiftQueue, property} import freechips.rocketchip.util.UIntToAugmentedUInt class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) { val pc = UInt(vaddrBitsExtended.W) val speculative = Bool() } class FrontendExceptions extends Bundle { val pf = new Bundle { val inst = Bool() } val gf = new Bundle { val inst = Bool() } val ae = new Bundle { val inst = Bool() } } class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) { val btb = new BTBResp val pc = UInt(vaddrBitsExtended.W) // ID stage PC val data = UInt((fetchWidth coreInstBits).W) val mask = Bits(fetchWidth.W) val xcpt = new FrontendExceptions val replay = Bool() } class FrontendPerfEvents extends Bundle { val acquire = Bool() val tlbMiss = Bool() } class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) { val might_request = Output(Bool()) val clock_enabled = Input(Bool()) val req = Valid(new FrontendReq) val sfence = Valid(new SFenceReq) val resp = Flipped(Decoupled(new FrontendResp)) val gpa = Flipped(Valid(UInt(vaddrBitsExtended.W))) val gpa_is_pte = Input(Bool()) val btb_update = Valid(new BTBUpdate) val bht_update = Valid(new BHTUpdate) val ras_update = Valid(new RASUpdate) val flush_icache = Output(Bool()) val npc = Input(UInt(vaddrBitsExtended.W)) val perf = Input(new FrontendPerfEvents()) val progress = Output(Bool()) } class Frontend(val icacheParams: ICacheParams, tileId: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new FrontendModule(this) val icache = LazyModule(new ICache(icacheParams, tileId)) val masterNode = icache.masterNode val slaveNode = icache.slaveNode val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(masterNode.edges.out.head.bundle.addressBits.W))) } class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p) { val cpu = Flipped(new FrontendIO()) val ptw = new TLBPTWIO() val errors = new ICacheErrors } class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) with HasRocketCoreParameters with HasL1ICacheParameters { val io = IO(new FrontendBundle(outer)) val io_reset_vector = outer.resetVectorSinkNode.bundle implicit val edge: TLEdgeOut = outer.masterNode.edges.out(0) val icache = outer.icache.module require(fetchWidthcoreInstBytes == outer.icacheParams.fetchBytes) val fq = withReset(reset.asBool \|\| io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cpu.might_request io.cpu.clock_enabled := clock_en assert(!(io.cpu.req.valid \|\| io.cpu.sfence.valid \|\| io.cpu.flush_icache \|\| io.cpu.bht_update.valid \|\| io.cpu.btb_update.valid) \|\| io.cpu.might_request) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "icache_clock_gate") icache.clock := gated_clock icache.io.clock_enabled := clock_en withClock (gated_clock) { // entering gated-clock domain val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays, outer.icacheParams.nTLBBasePageSectors, outer.icacheParams.nTLBSuperpages))) val s1_valid = Reg(Bool()) val s2_valid = RegInit(false.B) val s0_fq_has_space = !fq.io.mask(fq.io.mask.getWidth-3) \|\| (!fq.io.mask(fq.io.mask.getWidth-2) && (!s1_valid \|\| !s2_valid)) \|\| (!fq.io.mask(fq.io.mask.getWidth-1) && (!s1_valid && !s2_valid)) val s0_valid = io.cpu.req.valid \|\| s0_fq_has_space s1_valid := s0_valid val s1_pc = Reg(UInt(vaddrBitsExtended.W)) val s1_speculative = Reg(Bool()) val s2_pc = RegInit(t = UInt(vaddrBitsExtended.W), alignPC(io_reset_vector)) val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B val s2_btb_resp_bits = Reg(new BTBResp) val s2_btb_taken = s2_btb_resp_valid && s2_btb_resp_bits.taken val s2_tlb_resp = Reg(tlb.io.resp.cloneType) val s2_xcpt = s2_tlb_resp.ae.inst \|\| s2_tlb_resp.pf.inst \|\| s2_tlb_resp.gf.inst val s2_speculative = RegInit(false.B) val s2_partial_insn_valid = RegInit(false.B) val s2_partial_insn = Reg(UInt(coreInstBits.W)) val wrong_path = RegInit(false.B) val s1_base_pc = ~(~s1_pc \| (fetchBytes - 1).U) val ntpc = s1_base_pc + fetchBytes.U val predicted_npc = WireDefault(ntpc) val predicted_taken = WireDefault(false.B) val s2_replay = Wire(Bool()) s2_replay := (s2_valid && !fq.io.enq.fire) \|\| RegNext(s2_replay && !s0_valid, true.B) val npc = Mux(s2_replay, s2_pc, predicted_npc) s1_pc := io.cpu.npc // consider RVC fetches across blocks to be non-speculative if the first // part was non-speculative val s0_speculative = if (usingCompressed) s1_speculative \|\| s2_valid && !s2_speculative \|\| predicted_taken else true.B s1_speculative := Mux(io.cpu.req.valid, io.cpu.req.bits.speculative, Mux(s2_replay, s2_speculative, s0_speculative)) val s2_redirect = WireDefault(io.cpu.req.valid) s2_valid := false.B when (!s2_replay) { s2_valid := !s2_redirect s2_pc := s1_pc s2_speculative := s1_speculative s2_tlb_resp := tlb.io.resp } val recent_progress_counter_init = 3.U val recent_progress_counter = RegInit(recent_progress_counter_init) val recent_progress = recent_progress_counter > 0.U when(io.ptw.req.fire && recent_progress) { recent_progress_counter := recent_progress_counter - 1.U } when(io.cpu.progress) { recent_progress_counter := recent_progress_counter_init } val s2_kill_speculative_tlb_refill = s2_speculative && !recent_progress io.ptw <> tlb.io.ptw tlb.io.req.valid := s1_valid && !s2_replay tlb.io.req.bits.cmd := M_XRD // Frontend only reads tlb.io.req.bits.vaddr := s1_pc tlb.io.req.bits.passthrough := false.B tlb.io.req.bits.size := log2Ceil(coreInstBytesfetchWidth).U tlb.io.req.bits.prv := io.ptw.status.prv tlb.io.req.bits.v := io.ptw.status.v tlb.io.sfence := io.cpu.sfence tlb.io.kill := !s2_valid \|\| s2_kill_speculative_tlb_refill icache.io.req.valid := s0_valid icache.io.req.bits.addr := io.cpu.npc icache.io.invalidate := io.cpu.flush_icache icache.io.s1_paddr := tlb.io.resp.paddr icache.io.s2_vaddr := s2_pc icache.io.s1_kill := s2_redirect \|\| tlb.io.resp.miss \|\| s2_replay val s2_can_speculatively_refill = s2_tlb_resp.cacheable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill icache.io.s2_kill := s2_speculative && !s2_can_speculatively_refill \|\| s2_xcpt icache.io.s2_cacheable := s2_tlb_resp.cacheable icache.io.s2_prefetch := s2_tlb_resp.prefetchable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableICachePrefetch fq.io.enq.valid := RegNext(s1_valid) && s2_valid && (icache.io.resp.valid \|\| (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) \|\| (!s2_tlb_resp.miss && icache.io.s2_kill)) fq.io.enq.bits.pc := s2_pc io.cpu.npc := alignPC(Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)) fq.io.enq.bits.data := icache.io.resp.bits.data fq.io.enq.bits.mask := ((1 << fetchWidth)-1).U << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes)) fq.io.enq.bits.replay := (icache.io.resp.bits.replay \|\| icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt) \|\| (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) fq.io.enq.bits.btb := s2_btb_resp_bits fq.io.enq.bits.btb.taken := s2_btb_taken fq.io.enq.bits.xcpt := s2_tlb_resp assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill)) when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true.B } if (usingBTB) { val btb = Module(new BTB) btb.io.flush := false.B btb.io.req.valid := false.B btb.io.req.bits.addr := s1_pc btb.io.btb_update := io.cpu.btb_update btb.io.bht_update := io.cpu.bht_update btb.io.ras_update.valid := false.B btb.io.ras_update.bits := DontCare btb.io.bht_advance.valid := false.B btb.io.bht_advance.bits := DontCare when (!s2_replay) { btb.io.req.valid := !s2_redirect s2_btb_resp_valid := btb.io.resp.valid s2_btb_resp_bits := btb.io.resp.bits } when (btb.io.resp.valid && btb.io.resp.bits.taken) { predicted_npc := btb.io.resp.bits.target.sextTo(vaddrBitsExtended) predicted_taken := true.B } val force_taken = io.ptw.customCSRs.bpmStatic when (io.ptw.customCSRs.flushBTB) { btb.io.flush := true.B } when (force_taken) { btb.io.bht_update.valid := false.B } val s2_base_pc = ~(~s2_pc \| (fetchBytes-1).U) val taken_idx = Wire(UInt()) val after_idx = Wire(UInt()) val useRAS = WireDefault(false.B) val updateBTB = WireDefault(false.B) // If !prevTaken, ras_update / bht_update is always invalid. taken_idx := DontCare after_idx := DontCare def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = { def insnIsRVC(bits: UInt) = bits(1,0) =/= 3.U val prevRVI = prevValid && !insnIsRVC(prevBits) val valid = fq.io.enq.bits.mask(idx) && !prevRVI val bits = fq.io.enq.bits.data(coreInstBits(idx+1)-1, coreInstBitsidx) val rvc = insnIsRVC(bits) val rviBits = Cat(bits, prevBits) val rviBranch = rviBits(6,0) === Instructions.BEQ.value.U.extract(6,0) val rviJump = rviBits(6,0) === Instructions.JAL.value.U.extract(6,0) val rviJALR = rviBits(6,0) === Instructions.JALR.value.U.extract(6,0) val rviReturn = rviJALR && !rviBits(7) && BitPat("b00?01") === rviBits(19,15) val rviCall = (rviJALR \|\| rviJump) && rviBits(7) val rvcBranch = bits === Instructions.C_BEQZ \|\| bits === Instructions.C_BNEZ val rvcJAL = (xLen == 32).B && bits === Instructions32.C_JAL val rvcJump = bits === Instructions.C_J \|\| rvcJAL val rvcImm = Mux(bits(14), new RVCDecoder(bits, xLen, fLen).bImm.asSInt, new RVCDecoder(bits, xLen, fLen).jImm.asSInt) val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0.U val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7) val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0.U val rvcCall = rvcJAL \|\| rvcJALR val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), ImmGen(IMM_SB, rviBits)) val predict_taken = s2_btb_resp_bits.bht.taken \|\| force_taken val taken = prevRVI && (rviJump \|\| rviJALR \|\| rviBranch && predict_taken) \|\| valid && (rvcJump \|\| rvcJALR \|\| rvcJR \|\| rvcBranch && predict_taken) val predictReturn = btb.io.ras_head.valid && (prevRVI && rviReturn \|\| valid && rvcReturn) val predictJump = prevRVI && rviJump \|\| valid && rvcJump val predictBranch = predict_taken && (prevRVI && rviBranch \|\| valid && rvcBranch) when (s2_valid && s2_btb_resp_valid && s2_btb_resp_bits.bridx === idx.U && valid && !rvc) { // The BTB has predicted that the middle of an RVI instruction is // a branch! Flush the BTB and the pipeline. btb.io.flush := true.B fq.io.enq.bits.replay := true.B wrong_path := true.B ccover(wrong_path, "BTB_NON_CFI_ON_WRONG_PATH", "BTB predicted a non-branch was taken while on the wrong path") } when (!prevTaken) { taken_idx := idx.U after_idx := (idx + 1).U btb.io.ras_update.valid := fq.io.enq.fire && !wrong_path && (prevRVI && (rviCall \|\| rviReturn) \|\| valid && (rvcCall \|\| rvcReturn)) btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret, Mux(Mux(prevRVI, rviCall, rvcCall), CFIType.call, Mux(Mux(prevRVI, rviBranch, rvcBranch) && !force_taken, CFIType.branch, CFIType.jump))) when (!s2_btb_taken) { when (fq.io.enq.fire && taken && !predictBranch && !predictJump && !predictReturn) { wrong_path := true.B } when (s2_valid && predictReturn) { useRAS := true.B } when (s2_valid && (predictBranch \|\| predictJump)) { val pc = s2_base_pc \| (idxcoreInstBytes).U val npc = if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm) else Mux(prevRVI, pc - coreInstBytes.U, pc).asSInt + Mux(prevRVI, rviImm, rvcImm) predicted_npc := npc.asUInt } } when (prevRVI && rviBranch \|\| valid && rvcBranch) { btb.io.bht_advance.valid := fq.io.enq.fire && !wrong_path btb.io.bht_advance.bits := s2_btb_resp_bits } when (!s2_btb_resp_valid && (predictBranch && s2_btb_resp_bits.bht.strongly_taken \|\| predictJump \|\| predictReturn)) { updateBTB := true.B } } if (idx == fetchWidth-1) { when (fq.io.enq.fire) { s2_partial_insn_valid := false.B when (valid && !prevTaken && !rvc) { s2_partial_insn_valid := true.B s2_partial_insn := bits \| 0x3.U } } prevTaken \|\| taken } else { scanInsns(idx + 1, valid, bits, prevTaken \|\| taken) } } when (!io.cpu.btb_update.valid) { val fetch_bubble_likely = !fq.io.mask(1) btb.io.btb_update.valid := fq.io.enq.fire && !wrong_path && fetch_bubble_likely && updateBTB btb.io.btb_update.bits.prediction.entry := tileParams.btb.get.nEntries.U btb.io.btb_update.bits.isValid := true.B btb.io.btb_update.bits.cfiType := btb.io.ras_update.bits.cfiType btb.io.btb_update.bits.br_pc := s2_base_pc \| (taken_idx << log2Ceil(coreInstBytes)) btb.io.btb_update.bits.pc := s2_base_pc } btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes)) val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B) when (useRAS) { predicted_npc := btb.io.ras_head.bits } when (fq.io.enq.fire && (s2_btb_taken \|\| taken)) { s2_partial_insn_valid := false.B } when (!s2_btb_taken) { when (taken) { fq.io.enq.bits.btb.bridx := taken_idx fq.io.enq.bits.btb.taken := true.B fq.io.enq.bits.btb.entry := tileParams.btb.get.nEntries.U when (fq.io.enq.fire) { s2_redirect := true.B } } } assert(!s2_partial_insn_valid \|\| fq.io.enq.bits.mask(0)) when (s2_redirect) { s2_partial_insn_valid := false.B } when (io.cpu.req.valid) { wrong_path := false.B } } io.cpu.resp <> fq.io.deq // supply guest physical address to commit stage val gpa_valid = Reg(Bool()) val gpa = Reg(UInt(vaddrBitsExtended.W)) val gpa_is_pte = Reg(Bool()) when (fq.io.enq.fire && s2_tlb_resp.gf.inst) { when (!gpa_valid) { gpa := s2_tlb_resp.gpa gpa_is_pte := s2_tlb_resp.gpa_is_pte } gpa_valid := true.B } when (io.cpu.req.valid) { gpa_valid := false.B } io.cpu.gpa.valid := gpa_valid io.cpu.gpa.bits := gpa io.cpu.gpa_is_pte := gpa_is_pte // performance events io.cpu.perf.acquire := icache.io.perf.acquire io.cpu.perf.tlbMiss := io.ptw.req.fire io.errors := icache.io.errors // gate the clock clock_en_reg := !rocketParams.clockGate.B \|\| io.cpu.might_request \|\| // chicken bit icache.io.keep_clock_enabled \|\| // I$ miss or ITIM access s1_valid \|\| s2_valid \|\| // some fetch in flight !tlb.io.req.ready \|\| // handling TLB miss !fq.io.mask(fq.io.mask.getWidth-1) // queue not full } // leaving gated-clock domain def alignPC(pc: UInt) = ~(~pc \| (coreInstBytes - 1).U) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FRONTEND_$label", "Rocket;;" + desc) } /* Mix-ins for constructing tiles that have an ICache-based pipeline frontend / trait HasICacheFrontend extends CanHavePTW { this: BaseTile => val module: HasICacheFrontendModule val frontend = LazyModule(new Frontend(tileParams.icache.get, tileId)) tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.masterNode connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes) frontend.icache.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode } frontend.icache.mmioAddressPrefixSinkNodeOpt.foreach { _ := mmioAddressPrefixNexusNode } frontend.resetVectorSinkNode := resetVectorNexusNode nPTWPorts += 1 // This should be a None in the case of not having an ITIM address, when we // don't actually use the device that is instantiated in the frontend. private val deviceOpt = if (tileParams.icache.get.itimAddr.isDefined) Some(frontend.icache.device) else None } trait HasICacheFrontendModule extends CanHavePTWModule { val outer: HasICacheFrontend ptwPorts += outer.frontend.module.io.ptw } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /* PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss / class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /* PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info / class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /* ptw access exception / val ae_ptw = Bool() /* final access exception / val ae_final = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* hypervisor read / val hr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor execute / val hx = Bool() /* PTE to refill L1TLB * * source: L2TLB / val pte = new PTE /* pte pglevel / val level = UInt(log2Ceil(pgLevels).W) /* fragmented_superpage support / val fragmented_superpage = Bool() /* homogeneous for both pma and pmp / val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /* IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) / class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /* PTW performance statistics / class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /* Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core / class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /* enable clock generated by ptw / val clock_enabled = Output(Bool()) } /* PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format / class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* global mapping / val g = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() /* valid bit / val v = Bool() /* return true if find a pointer to next level page table / def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /* return true if find a leaf PTE / def leaf(dummy: Int = 0) = v && (r \|\| (x && !w)) && a /* user read / def ur(dummy: Int = 0) = sr() && u /* user write/ def uw(dummy: Int = 0) = sw() && u /* user execute / def ux(dummy: Int = 0) = sx() && u /* supervisor read / def sr(dummy: Int = 0) = leaf() && r /* supervisor write / def sw(dummy: Int = 0) = leaf() && w && d /* supervisor execute / def sx(dummy: Int = 0) = leaf() && x /* full permission: writable and executable in user mode / def isFullPerm(dummy: Int = 0) = uw() && ux() } /* L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format / class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() } /* PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation / class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /* to n TLB / val requestor = Flipped(Vec(n, new TLBPTWIO)) /* to HellaCache / val mem = new HellaCacheIO /* to Core * * contains CSRs info and performance statistics / val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /* Arbiter to arbite request from n TLB / val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready \|\| l2_refill_wire \|\| arb.io.out.valid \|\| io.dpath.sfence.valid \|\| io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM \|\| !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /* current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} / val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /* tlb request / val r_req = Reg(new PTWReq) /* current selected way in arbitor / val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /* pte for 2-stage translation / val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /* 2-stage translation both enable / val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r \|\| tmp.w \|\| tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)pgLevelBits-1, (pgLevels-2-i)pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /* address send to mem for enquerry / val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) \| vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr / val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBitsi), r_req.addr(((pgLevelBitsi) min vpnBits)-1, 0).padTo(pgLevelBitsi))) } /* PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation / def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid \| UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 \|\| usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss \|\| io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /* the valid vec for the selected set(including n ways) / val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) \| mask g(way) := Mux(r_pte.g, g(way) \| mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) \|\| s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid \|\| (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req \|\| state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit \|\| (state =/= s_wait1) \|\| resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor \|\| pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous \|\| pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final \|\| !r_req.vstage1 \|\| aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa \|\| arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), aux_pte.ppn((pgLevels-i-1)pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req \|\| state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) \|\| (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 \|\| do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages \|\| aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf \|\| (pf && stage2) resp_hr := !stage2 \|\| (!pf && !gf && pte.ur()) resp_hw := !stage2 \|\| (!pf && !gf && pte.uw()) resp_hx := !stage2 \|\| (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), r_req.addr(((pgLevels-i-1)pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn / private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /* use hgatp and vpn to construct a new ppn / private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range / private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW / trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File HierarchicalElement.scala: package freechips.rocketchip.subsystem import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.debug.TLDebugModule import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.interrupts.IntXbar import freechips.rocketchip.prci.{ClockSinkParameters, ResetCrossingType, ClockCrossingType} import freechips.rocketchip.tile.{LookupByHartIdImpl, TraceBundle} import freechips.rocketchip.tilelink.{TLNode, TLIdentityNode, TLXbar, TLBuffer, TLInwardNode, TLOutwardNode} trait HierarchicalElementParams { val baseName: String // duplicated instances shouuld share a base name val uniqueName: String val clockSinkParams: ClockSinkParameters } abstract class InstantiableHierarchicalElementParams[ElementType <: BaseHierarchicalElement] extends HierarchicalElementParams /* An interface for describing the parameteization of how HierarchicalElements are connected to interconnects / trait HierarchicalElementCrossingParamsLike { /* The type of clock crossing that should be inserted at the element boundary. / def crossingType: ClockCrossingType /* Parameters describing the contents and behavior of the point where the element is attached as an interconnect master. / def master: HierarchicalElementPortParamsLike /* Parameters describing the contents and behavior of the point where the element is attached as an interconnect slave. / def slave: HierarchicalElementPortParamsLike /* The subnetwork location of the device selecting the apparent base address of MMIO devices inside the element / def mmioBaseAddressPrefixWhere: TLBusWrapperLocation /* Inject a reset management subgraph that effects the element child reset only / def resetCrossingType: ResetCrossingType /* Keep the element clock separate from the interconnect clock (e.g. even if they are synchronous to one another) / def forceSeparateClockReset: Boolean } /* An interface for describing the parameterization of how a particular element port is connected to an interconnect / trait HierarchicalElementPortParamsLike { /* The subnetwork location of the interconnect to which this element port should be connected. / def where: TLBusWrapperLocation /* Allows port-specific adapters to be injected into the interconnect side of the attachment point. / def injectNode(context: Attachable)(implicit p: Parameters): TLNode } abstract class BaseHierarchicalElement (val crossing: ClockCrossingType)(implicit p: Parameters) extends LazyModule()(p) with CrossesToOnlyOneClockDomain { def module: BaseHierarchicalElementModuleImp[BaseHierarchicalElement] protected val tlOtherMastersNode = TLIdentityNode() protected val tlMasterXbar = LazyModule(new TLXbar(nameSuffix = Some(s"MasterXbar_$desiredName"))) protected val tlSlaveXbar = LazyModule(new TLXbar(nameSuffix = Some(s"SlaveXbar_$desiredName"))) protected val intXbar = LazyModule(new IntXbar) def masterNode: TLOutwardNode def slaveNode: TLInwardNode /* Helper function to insert additional buffers on master ports at the boundary of the tile. * * The boundary buffering needed to cut feed-through paths is * microarchitecture specific, so this may need to be overridden * in subclasses of this class. / def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) /* Helper function to insert additional buffers on slave ports at the boundary of the tile. * * The boundary buffering needed to cut feed-through paths is * microarchitecture specific, so this may need to be overridden * in subclasses of this class. / def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) } abstract class BaseHierarchicalElementModuleImp[+L <: BaseHierarchicalElement](val outer: L) extends LazyModuleImp(outer) File RocketTile.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tile import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BasicBusBlockerParams, BasicBusBlocker} import freechips.rocketchip.diplomacy.{ AddressSet, DisableMonitors, BufferParams } import freechips.rocketchip.resources.{ SimpleDevice, Description, ResourceAnchors, ResourceBindings, ResourceBinding, Resource, ResourceAddress, } import freechips.rocketchip.interrupts.IntIdentityNode import freechips.rocketchip.tilelink.{TLIdentityNode, TLBuffer} import freechips.rocketchip.rocket.{ RocketCoreParams, ICacheParams, DCacheParams, BTBParams, HasHellaCache, HasICacheFrontend, ScratchpadSlavePort, HasICacheFrontendModule, Rocket } import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike import freechips.rocketchip.prci.{ClockSinkParameters, RationalCrossing, ClockCrossingType} import freechips.rocketchip.util.{Annotated, InOrderArbiter} import freechips.rocketchip.util.BooleanToAugmentedBoolean case class RocketTileBoundaryBufferParams(force: Boolean = false) case class RocketTileParams( core: RocketCoreParams = RocketCoreParams(), icache: Option[ICacheParams] = Some(ICacheParams()), dcache: Option[DCacheParams] = Some(DCacheParams()), btb: Option[BTBParams] = Some(BTBParams()), dataScratchpadBytes: Int = 0, tileId: Int = 0, beuAddr: Option[BigInt] = None, blockerCtrlAddr: Option[BigInt] = None, clockSinkParams: ClockSinkParameters = ClockSinkParameters(), boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None ) extends InstantiableTileParams[RocketTile] { require(icache.isDefined) require(dcache.isDefined) val baseName = "rockettile" val uniqueName = s"${baseName}_$tileId" def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): RocketTile = { new RocketTile(this, crossing, lookup) } } class RocketTile private( val rocketParams: RocketTileParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, q: Parameters) extends BaseTile(rocketParams, crossing, lookup, q) with SinksExternalInterrupts with SourcesExternalNotifications with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache with HasHellaCache with HasICacheFrontend { // Private constructor ensures altered LazyModule.p is used implicitly def this(params: RocketTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) val intOutwardNode = rocketParams.beuAddr map { _ => IntIdentityNode() } val slaveNode = TLIdentityNode() val masterNode = visibilityNode val dtim_adapter = tileParams.dcache.flatMap { d => d.scratch.map { s => LazyModule(new ScratchpadSlavePort(AddressSet.misaligned(s, d.dataScratchpadBytes), lazyCoreParamsView.coreDataBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO)) }} dtim_adapter.foreach(lm => connectTLSlave(lm.node, lm.node.portParams.head.beatBytes)) val bus_error_unit = rocketParams.beuAddr map { a => val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a), xLen/8)) intOutwardNode.get := beu.intNode connectTLSlave(beu.node, xBytes) beu } val tile_master_blocker = tileParams.blockerCtrlAddr .map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true)) .map(bp => LazyModule(new BasicBusBlocker(bp))) tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes)) // TODO: this doesn't block other masters, e.g. RoCCs tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node } masterNode := tlOtherMastersNode DisableMonitors { implicit p => tlSlaveXbar.node := slaveNode } nDCachePorts += 1 /core / + (dtim_adapter.isDefined).toInt + rocketParams.core.vector.map(_.useDCache.toInt).getOrElse(0) val dtimProperty = dtim_adapter.map(d => Map( "sifive,dtim" -> d.device.asProperty)).getOrElse(Nil) val itimProperty = frontend.icache.itimProperty.toSeq.flatMap(p => Map("sifive,itim" -> p)) val beuProperty = bus_error_unit.map(d => Map( "sifive,buserror" -> d.device.asProperty)).getOrElse(Nil) val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("sifive,rocket0", "riscv")) { override def parent = Some(ResourceAnchors.cpus) override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty ++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty) } } val vector_unit = rocketParams.core.vector.map(v => LazyModule(v.build(p))) vector_unit.foreach(vu => tlMasterXbar.node := vu.atlNode) vector_unit.foreach(vu => tlOtherMastersNode :=* vu.tlNode) ResourceBinding { Resource(cpuDevice, "reg").bind(ResourceAddress(tileId)) } override lazy val module = new RocketTileModuleImp(this) override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer() case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)) case _ => TLBuffer(BufferParams.none) } override def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer() case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none) case _ => TLBuffer(BufferParams.none) } } class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer) with HasFpuOpt with HasLazyRoCCModule with HasICacheFrontendModule { Annotated.params(this, outer.rocketParams) val core = Module(new Rocket(outer)(outer.p)) outer.vector_unit.foreach { v => core.io.vector.get <> v.module.io.core v.module.io.tlb <> outer.dcache.module.io.tlb_port } // reset vector is connected in the Frontend to s2_pc core.io.reset_vector := DontCare // Report unrecoverable error conditions; for now the only cause is cache ECC errors outer.reportHalt(List(outer.dcache.module.io.errors)) // Report when the tile has ceased to retire instructions; for now the only cause is clock gating outer.reportCease(outer.rocketParams.core.clockGate.option( !outer.dcache.module.io.cpu.clock_enabled && !outer.frontend.module.io.cpu.clock_enabled && !ptw.io.dpath.clock_enabled && core.io.cease)) outer.reportWFI(Some(core.io.wfi)) outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector outer.bus_error_unit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt beu.module.io.errors.dcache := outer.dcache.module.io.errors beu.module.io.errors.icache := outer.frontend.module.io.errors } core.io.interrupts.nmi.foreach { nmi => nmi := outer.nmiSinkNode.get.bundle } // Pass through various external constants and reports that were bundle-bridged into the tile outer.traceSourceNode.bundle <> core.io.trace core.io.traceStall := outer.traceAuxSinkNode.bundle.stall outer.bpwatchSourceNode.bundle <> core.io.bpwatch core.io.hartid := outer.hartIdSinkNode.bundle require(core.io.hartid.getWidth >= outer.hartIdSinkNode.bundle.getWidth, s"core hartid wire (${core.io.hartid.getWidth}b) truncates external hartid wire (${outer.hartIdSinkNode.bundle.getWidth}b)") // Connect the core pipeline to other intra-tile modules outer.frontend.module.io.cpu <> core.io.imem dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ?? fpuOpt foreach { fpu => core.io.fpu :<>= fpu.io.waiveAs[FPUCoreIO](_.cp_req, _.cp_resp) } if (fpuOpt.isEmpty) { core.io.fpu := DontCare } outer.vector_unit foreach { v => if (outer.rocketParams.core.vector.get.useDCache) { dcachePorts += v.module.io.dmem } else { v.module.io.dmem := DontCare } } core.io.ptw <> ptw.io.dpath // Connect the coprocessor interfaces if (outer.roccs.size > 0) { cmdRouter.get.io.in <> core.io.rocc.cmd outer.roccs.foreach{ lm => lm.module.io.exception := core.io.rocc.exception lm.module.io.fpu_req.ready := DontCare lm.module.io.fpu_resp.valid := DontCare lm.module.io.fpu_resp.bits.data := DontCare lm.module.io.fpu_resp.bits.exc := DontCare } core.io.rocc.resp <> respArb.get.io.out core.io.rocc.busy <> (cmdRouter.get.io.busy \|\| outer.roccs.map(_.module.io.busy).reduce(_ \|\| _)) core.io.rocc.interrupt := outer.roccs.map(_.module.io.interrupt).reduce(_ \|\| _) (core.io.rocc.csrs zip roccCSRIOs.flatten).foreach { t => t._2 <> t._1 } } else { // tie off core.io.rocc.cmd.ready := false.B core.io.rocc.resp.valid := false.B core.io.rocc.resp.bits := DontCare core.io.rocc.busy := DontCare core.io.rocc.interrupt := DontCare } // Dont care mem since not all RoCC need accessing memory core.io.rocc.mem := DontCare // Rocket has higher priority to DTIM than other TileLink clients outer.dtim_adapter.foreach { lm => dcachePorts += lm.module.io.dmem } // TODO eliminate this redundancy val h = dcachePorts.size val c = core.dcacheArbPorts val o = outer.nDCachePorts require(h == c, s"port list size was $h, core expected $c") require(h == o, s"port list size was $h, outer counted $o") // TODO figure out how to move the below into their respective mix-ins dcacheArb.io.requestor <> dcachePorts.toSeq ptw.io.requestor <> ptwPorts.toSeq } trait HasFpuOpt { this: RocketTileModuleImp => val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p))) fpuOpt.foreach { fpu => val nRoCCFPUPorts = outer.roccs.count(_.usesFPU) val nFPUPorts = nRoCCFPUPorts + outer.rocketParams.core.useVector.toInt if (nFPUPorts > 0) { val fpArb = Module(new InOrderArbiter(new FPInput()(outer.p), new FPResult()(outer.p), nFPUPorts)) fpu.io.cp_req <> fpArb.io.out_req fpArb.io.out_resp <> fpu.io.cp_resp val fp_rocc_ios = outer.roccs.filter(_.usesFPU).map(_.module.io) for (i <- 0 until nRoCCFPUPorts) { fpArb.io.in_req(i) <> fp_rocc_ios(i).fpu_req fp_rocc_ios(i).fpu_resp <> fpArb.io.in_resp(i) } outer.vector_unit.foreach(vu => { fpArb.io.in_req(nRoCCFPUPorts) <> vu.module.io.fp_req vu.module.io.fp_resp <> fpArb.io.in_resp(nRoCCFPUPorts) }) } else { fpu.io.cp_req.valid := false.B fpu.io.cp_req.bits := DontCare fpu.io.cp_resp.ready := false.B } } } File BundleBridgeNexus.scala: package org.chipsalliance.diplomacy.bundlebridge import chisel3.{chiselTypeOf, ActualDirection, Data, Reg} import chisel3.reflect.DataMirror import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyRawModuleImp} class BundleBridgeNexus[T <: Data]( inputFn: Seq[T] => T, outputFn: (T, Int) => Seq[T], default: Option[() => T] = None, inputRequiresOutput: Boolean = false, override val shouldBeInlined: Boolean = true )( implicit p: Parameters) extends LazyModule { val node = BundleBridgeNexusNode[T](default, inputRequiresOutput) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val defaultWireOpt = default.map(_()) val inputs: Seq[T] = node.in.map(_._1) inputs.foreach { i => require( DataMirror.checkTypeEquivalence(i, inputs.head), s"${node.context} requires all inputs have equivalent Chisel Data types, but got\n$i\nvs\n${inputs.head}" ) } inputs.flatMap(getElements).foreach { elt => DataMirror.directionOf(elt) match { case ActualDirection.Output => () case ActualDirection.Unspecified => () case _ => require(false, s"${node.context} can only be used with Output-directed Bundles") } } val outputs: Seq[T] = if (node.out.size > 0) { val broadcast: T = if (inputs.size >= 1) inputFn(inputs) else defaultWireOpt.get outputFn(broadcast, node.out.size) } else { Nil } val typeName = outputs.headOption.map(_.typeName).getOrElse("NoOutput") override def desiredName = s"BundleBridgeNexus_$typeName" node.out.map(_._1).foreach { o => require( DataMirror.checkTypeEquivalence(o, outputs.head), s"${node.context} requires all outputs have equivalent Chisel Data types, but got\n$o\nvs\n${outputs.head}" ) } require( outputs.size == node.out.size, s"${node.context} outputFn must generate one output wire per edgeOut, but got ${outputs.size} vs ${node.out.size}" ) node.out.zip(outputs).foreach { case ((out, _), bcast) => out := bcast } } } object BundleBridgeNexus { def safeRegNext[T <: Data](x: T): T = { val reg = Reg(chiselTypeOf(x)) reg := x reg } def requireOne[T <: Data](registered: Boolean)(seq: Seq[T]): T = { require(seq.size == 1, "BundleBroadcast default requires one input") if (registered) safeRegNext(seq.head) else seq.head } def orReduction[T <: Data](registered: Boolean)(seq: Seq[T]): T = { val x = seq.reduce((a, b) => (a.asUInt \| b.asUInt).asTypeOf(seq.head)) if (registered) safeRegNext(x) else x } def fillN[T <: Data](registered: Boolean)(x: T, n: Int): Seq[T] = Seq.fill(n) { if (registered) safeRegNext(x) else x } def apply[T <: Data]( inputFn: Seq[T] => T = orReduction[T](false) _, outputFn: (T, Int) => Seq[T] = fillN[T](false) _, default: Option[() => T] = None, inputRequiresOutput: Boolean = false, shouldBeInlined: Boolean = true )( implicit p: Parameters ): BundleBridgeNexusNode[T] = { val nexus = LazyModule(new BundleBridgeNexus[T](inputFn, outputFn, default, inputRequiresOutput, shouldBeInlined)) nexus.node } }	module RocketTile_1( // @[RocketTile.scala:141:7] input clock, // @[RocketTile.scala:141:7] input reset, // @[RocketTile.scala:141:7] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_wfi_out_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25] output [39:0] auto_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25] output [31:0] auto_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25] output [2:0] auto_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25] output [39:0] auto_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_time, // @[LazyModuleImp.scala:107:25] input [1:0] auto_hartid_in // @[LazyModuleImp.scala:107:25] ); wire buffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_e_ready; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_b_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire [15:0] buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [15:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [127:0] widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire [15:0] widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire [15:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] broadcast_2_auto_in_0_action; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_valid_0; // @[BundleBridgeNexus.scala:20:9] wire [1:0] broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9] wire _core_io_imem_might_request; // @[RocketTile.scala:147:20] wire _core_io_imem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_imem_req_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_req_bits_speculative; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_asid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_hv; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_hg; // @[RocketTile.scala:147:20] wire _core_io_imem_resp_ready; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_valid; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_prediction_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_taken; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_prediction_mask; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_bridx; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_prediction_target; // @[RocketTile.scala:147:20] wire [4:0] _core_io_imem_btb_update_bits_prediction_entry; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_btb_update_bits_prediction_bht_history; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_bht_value; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_pc; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_target; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_isValid; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_br_pc; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_valid; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_bht_update_bits_prediction_history; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_prediction_value; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_bht_update_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_branch; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_taken; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_mispredict; // @[RocketTile.scala:147:20] wire _core_io_imem_flush_icache; // @[RocketTile.scala:147:20] wire _core_io_imem_progress; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_dmem_req_bits_addr; // @[RocketTile.scala:147:20] wire [6:0] _core_io_dmem_req_bits_tag; // @[RocketTile.scala:147:20] wire [4:0] _core_io_dmem_req_bits_cmd; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_size; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_signed; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_dprv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_dv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_no_resp; // @[RocketTile.scala:147:20] wire _core_io_dmem_s1_kill; // @[RocketTile.scala:147:20] wire [63:0] _core_io_dmem_s1_data_data; // @[RocketTile.scala:147:20] wire _core_io_dmem_keep_clock_enabled; // @[RocketTile.scala:147:20] wire [3:0] _core_io_ptw_ptbr_mode; // @[RocketTile.scala:147:20] wire [43:0] _core_io_ptw_ptbr_ppn; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_ptw_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_asid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_hv; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_hg; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_debug; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_cease; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_status_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_dprv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_v; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sd; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mpv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tsr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tw; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tvm; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_mpp; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_spp; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mpie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_spie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sie; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_spvp; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_spv; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_debug; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_cease; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_gstatus_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_dprv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_v; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sd; // @[RocketTile.scala:147:20] wire [22:0] _core_io_ptw_gstatus_zero2; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mpv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mbe; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sbe; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_sxl; // @[RocketTile.scala:147:20] wire [7:0] _core_io_ptw_gstatus_zero1; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tsr; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tw; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tvm; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_mpp; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_vs; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_spp; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mpie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_ube; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_spie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_upie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_hie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_uie; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_0_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_0_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_1_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_1_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_2_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_2_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_3_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_3_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_4_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_4_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_5_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_5_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_6_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_6_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_7_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_7_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_0_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_0_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_1_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_1_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_1_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_1_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_2_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_2_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_2_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_2_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_3_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_3_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_3_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_3_value; // @[RocketTile.scala:147:20] wire [1:0] _core_io_fpu_hartid; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_time; // @[RocketTile.scala:147:20] wire [31:0] _core_io_fpu_inst; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_fromint_data; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_fcsr_rm; // @[RocketTile.scala:147:20] wire _core_io_fpu_ll_resp_val; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_ll_resp_type; // @[RocketTile.scala:147:20] wire [4:0] _core_io_fpu_ll_resp_tag; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_ll_resp_data; // @[RocketTile.scala:147:20] wire _core_io_fpu_valid; // @[RocketTile.scala:147:20] wire _core_io_fpu_killx; // @[RocketTile.scala:147:20] wire _core_io_fpu_killm; // @[RocketTile.scala:147:20] wire _core_io_fpu_keep_clock_enabled; // @[RocketTile.scala:147:20] wire _core_io_wfi; // @[RocketTile.scala:147:20] wire _ptw_io_requestor_0_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sd; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sd; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_0_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_0_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_1_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sd; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sd; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_1_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_1_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_mem_req_valid; // @[PTW.scala:802:19] wire [39:0] _ptw_io_mem_req_bits_addr; // @[PTW.scala:802:19] wire _ptw_io_mem_req_bits_dv; // @[PTW.scala:802:19] wire _ptw_io_mem_s1_kill; // @[PTW.scala:802:19] wire _ptw_io_dpath_perf_pte_miss; // @[PTW.scala:802:19] wire _ptw_io_dpath_perf_pte_hit; // @[PTW.scala:802:19] wire _ptw_io_dpath_clock_enabled; // @[PTW.scala:802:19] wire _dcacheArb_io_requestor_0_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_nack_cause_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_uncached; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_0_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_0_resp_bits_addr; // @[HellaCache.scala:292:25] wire [6:0] _dcacheArb_io_requestor_0_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_0_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_0_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_0_s2_gpa; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_blocked; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_nack_cause_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_uncached; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_1_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_1_resp_bits_addr; // @[HellaCache.scala:292:25] wire [6:0] _dcacheArb_io_requestor_1_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_1_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_1_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_1_s2_gpa; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_blocked; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala:292:25] wire [6:0] _dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_dv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_phys; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_no_resp; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_s1_kill; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_keep_clock_enabled; // @[HellaCache.scala:292:25] wire _fpuOpt_io_fcsr_flags_valid; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_fcsr_flags_bits; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_store_data; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_toint_data; // @[RocketTile.scala:242:62] wire _fpuOpt_io_fcsr_rdy; // @[RocketTile.scala:242:62] wire _fpuOpt_io_nack_mem; // @[RocketTile.scala:242:62] wire _fpuOpt_io_illegal_rm; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ldst; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wen; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren1; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren2; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren3; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_swap12; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_swap23; // @[RocketTile.scala:242:62] wire [1:0] _fpuOpt_io_dec_typeTagIn; // @[RocketTile.scala:242:62] wire [1:0] _fpuOpt_io_dec_typeTagOut; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fromint; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_toint; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fastpipe; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fma; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_div; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_sqrt; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wflags; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_vec; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_set; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_clr; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_sboard_clra; // @[RocketTile.scala:242:62] wire _frontend_io_cpu_resp_valid; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_btb_cfiType; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_taken; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_btb_mask; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bridx; // @[Frontend.scala:393:28] wire [38:0] _frontend_io_cpu_resp_bits_btb_target; // @[Frontend.scala:393:28] wire [4:0] _frontend_io_cpu_resp_bits_btb_entry; // @[Frontend.scala:393:28] wire [7:0] _frontend_io_cpu_resp_bits_btb_bht_history; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bht_value; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_resp_bits_pc; // @[Frontend.scala:393:28] wire [31:0] _frontend_io_cpu_resp_bits_data; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_mask; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_pf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_gf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_replay; // @[Frontend.scala:393:28] wire _frontend_io_cpu_gpa_valid; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_gpa_bits; // @[Frontend.scala:393:28] wire _frontend_io_cpu_gpa_is_pte; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_npc; // @[Frontend.scala:393:28] wire _frontend_io_cpu_perf_acquire; // @[Frontend.scala:393:28] wire _frontend_io_cpu_perf_tlbMiss; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_valid; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_valid; // @[Frontend.scala:393:28] wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[Frontend.scala:393:28] wire _dcache_io_cpu_req_ready; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_nack; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_nack_cause_raw; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_uncached; // @[HellaCache.scala:278:43] wire [31:0] _dcache_io_cpu_s2_paddr; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_valid; // @[HellaCache.scala:278:43] wire [39:0] _dcache_io_cpu_resp_bits_addr; // @[HellaCache.scala:278:43] wire [6:0] _dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala:278:43] wire [4:0] _dcache_io_cpu_resp_bits_cmd; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_size; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_signed; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_dprv; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_dv; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data; // @[HellaCache.scala:278:43] wire [7:0] _dcache_io_cpu_resp_bits_mask; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_store_data; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_replay_next; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala:278:43] wire [39:0] _dcache_io_cpu_s2_gpa; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_ordered; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_store_pending; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_acquire; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_release; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_grant; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_tlbMiss; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_blocked; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_valid; // @[HellaCache.scala:278:43] wire [26:0] _dcache_io_ptw_req_bits_bits_addr; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_bits_bits_need_gpa; // @[HellaCache.scala:278:43] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[RocketTile.scala:141:7] wire [15:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[RocketTile.scala:141:7] wire [127:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[RocketTile.scala:141:7] wire [127:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[RocketTile.scala:141:7] wire auto_int_local_in_3_0_0 = auto_int_local_in_3_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_2_0_0 = auto_int_local_in_2_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_1_0_0 = auto_int_local_in_1_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_1_1_0 = auto_int_local_in_1_1; // @[RocketTile.scala:141:7] wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[RocketTile.scala:141:7] wire [1:0] auto_hartid_in_0 = auto_hartid_in; // @[RocketTile.scala:141:7] wire auto_buffer_out_a_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7] wire auto_buffer_out_c_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7] wire auto_cease_out_0 = 1'h0; // @[RocketTile.scala:141:7] wire auto_halt_out_0 = 1'h0; // @[RocketTile.scala:141:7] wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[RocketTile.scala:141:7] wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[RocketTile.scala:141:7] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire broadcast_2_auto_in_0_rvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_wvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_ivalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_2_nodeIn_0_rvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_wvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_ivalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire buffer_auto_in_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17] wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17] wire bpwatchSourceNodeOut_0_rvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_wvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_ivalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire haltNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire ceaseNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire [2:0] widget_1_auto_anon_in_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonIn_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [15:0] widget_1_auto_anon_in_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] widget_1_auto_anon_out_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] widget_1_anonOut_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] widget_1_anonIn_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [127:0] widget_1_auto_anon_in_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] widget_1_auto_anon_out_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] widget_1_anonOut_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] widget_1_anonIn_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [31:0] auto_reset_vector_in = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_in = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_out_1 = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_out_0 = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_nodeIn = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_x1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] reset_vectorOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] reset_vectorIn = 32'h10000; // @[RocketTile.scala:141:7] wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[RocketTile.scala:141:7] wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[RocketTile.scala:141:7] wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire widget_1_auto_anon_in_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire buffer_auto_out_a_ready = auto_buffer_out_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_b_valid = auto_buffer_out_b_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_b_bits_opcode = auto_buffer_out_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_b_bits_param = auto_buffer_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_b_bits_size = auto_buffer_out_b_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_b_bits_source = auto_buffer_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_b_bits_address = auto_buffer_out_b_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] buffer_auto_out_b_bits_mask = auto_buffer_out_b_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_out_b_bits_data = auto_buffer_out_b_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_b_bits_corrupt = auto_buffer_out_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_ready = auto_buffer_out_c_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_d_valid = auto_buffer_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_param = auto_buffer_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_e_ready = auto_buffer_out_e_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_e_valid; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] wire wfiNodeOut_0; // @[MixedNode.scala:542:17] wire x1_int_localIn_2_0 = auto_int_local_in_3_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_1_0 = auto_int_local_in_2_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_0 = auto_int_local_in_1_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_1 = auto_int_local_in_1_1_0; // @[RocketTile.scala:141:7] wire int_localIn_0 = auto_int_local_in_0_0_0; // @[RocketTile.scala:141:7] wire traceSourceNodeOut_insns_0_valid; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_0_insn; // @[MixedNode.scala:542:17] wire [2:0] traceSourceNodeOut_insns_0_priv; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_exception; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_insns_0_cause; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_tval; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_time; // @[MixedNode.scala:542:17] wire [1:0] hartidIn = auto_hartid_in_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_a_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_a_bits_address_0; // @[RocketTile.scala:141:7] wire [15:0] auto_buffer_out_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [127:0] auto_buffer_out_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_b_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_c_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_c_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_c_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_c_bits_address_0; // @[RocketTile.scala:141:7] wire [127:0] auto_buffer_out_c_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_c_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_ready_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_e_bits_sink_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_e_valid_0; // @[RocketTile.scala:141:7] wire auto_wfi_out_0_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7] wire [39:0] auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7] wire [2:0] auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7] wire [63:0] auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7] wire [39:0] auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7] wire [63:0] auto_trace_source_out_time_0; // @[RocketTile.scala:141:7] wire [1:0] hartidOut; // @[MixedNode.scala:542:17] wire [1:0] broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17] wire [1:0] broadcast_nodeOut; // @[MixedNode.scala:542:17] wire [1:0] broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9] wire [1:0] hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17] assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17] wire broadcast_2_nodeIn_0_valid_0 = broadcast_2_auto_in_0_valid_0; // @[MixedNode.scala:551:17] wire [2:0] bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17] wire [2:0] broadcast_2_nodeIn_0_action = broadcast_2_auto_in_0_action; // @[MixedNode.scala:551:17] wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [15:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [127:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9] assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire widget_1_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_valid = widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_anonIn_a_bits_address = widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_1_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_1_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] widget_1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] widget_1_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_1_anonOut_a_ready = widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] widget_1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_valid = widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_opcode = widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_anonOut_d_bits_param = widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_d_bits_size = widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_d_bits_sink = widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_denied = widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] widget_1_anonOut_d_bits_data = widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_corrupt = widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_a_ready = widget_1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_out_a_valid = widget_1_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_out_a_bits_address = widget_1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_d_valid = widget_1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_opcode = widget_1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_param = widget_1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_size = widget_1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_sink = widget_1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_denied = widget_1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_data = widget_1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_corrupt = widget_1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_a_ready = widget_1_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_1_anonOut_a_valid = widget_1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonOut_a_bits_address = widget_1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_d_valid = widget_1_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_opcode = widget_1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_param = widget_1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_size = widget_1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_sink = widget_1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_denied = widget_1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_data = widget_1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_corrupt = widget_1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [15:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [127:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_b_ready = buffer_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_b_valid = buffer_auto_in_b_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_b_bits_opcode = buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_b_bits_param = buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeOut_b_bits_size = buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_b_bits_source = buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [15:0] buffer_nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] tlOtherMastersNodeOut_b_bits_address = buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [127:0] buffer_nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire [15:0] tlOtherMastersNodeOut_b_bits_mask = buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire buffer_nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [127:0] tlOtherMastersNodeOut_b_bits_data = buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_c_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_b_bits_corrupt = buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_c_ready = buffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_c_valid = buffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_c_bits_opcode = buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_c_bits_param = buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_c_bits_size = buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_c_bits_source = buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_c_bits_address = buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire [127:0] buffer_nodeIn_c_bits_data = buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_d_bits_param = buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeOut_d_bits_sink = buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [127:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_bits_denied = buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [127:0] tlOtherMastersNodeOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_e_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_e_ready = buffer_auto_in_e_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_e_valid = buffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_e_bits_sink = buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_valid_0 = buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_opcode_0 = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_param_0 = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_size_0 = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_source_0 = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_address_0 = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_mask_0 = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_data_0 = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_b_ready_0 = buffer_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_valid = buffer_auto_out_b_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_b_bits_opcode = buffer_auto_out_b_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_b_bits_param = buffer_auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_b_bits_size = buffer_auto_out_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_b_bits_source = buffer_auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_b_bits_address = buffer_auto_out_b_bits_address; // @[Buffer.scala:40:9] wire [15:0] buffer_nodeOut_b_bits_mask = buffer_auto_out_b_bits_mask; // @[Buffer.scala:40:9] wire [127:0] buffer_nodeOut_b_bits_data = buffer_auto_out_b_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_bits_corrupt = buffer_auto_out_b_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_c_ready = buffer_auto_out_c_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_c_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_valid_0 = buffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_opcode_0 = buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_param_0 = buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_size_0 = buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_source_0 = buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_address_0 = buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] buffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_data_0 = buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_d_ready_0 = buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_d_bits_sink = buffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_denied = buffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [127:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_e_ready = buffer_auto_out_e_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_e_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_valid_0 = buffer_auto_out_e_valid; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_bits_sink_0 = buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_b_ready = buffer_nodeOut_b_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_b_valid = buffer_nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_opcode = buffer_nodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_param = buffer_nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_size = buffer_nodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_source = buffer_nodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_address = buffer_nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_mask = buffer_nodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_data = buffer_nodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_corrupt = buffer_nodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_c_ready = buffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_c_valid = buffer_nodeOut_c_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_opcode = buffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_param = buffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_size = buffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_source = buffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_address = buffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_data = buffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_e_ready = buffer_nodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_e_valid = buffer_nodeOut_e_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_e_bits_sink = buffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_b_ready = buffer_nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_b_valid = buffer_nodeIn_b_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_opcode = buffer_nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_param = buffer_nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_size = buffer_nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_source = buffer_nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_address = buffer_nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_mask = buffer_nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_data = buffer_nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_corrupt = buffer_nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_c_ready = buffer_nodeIn_c_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_c_valid = buffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_opcode = buffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_param = buffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_size = buffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_source = buffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_address = buffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_data = buffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_e_ready = buffer_nodeIn_e_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_e_valid = buffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_e_bits_sink = buffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_ready = tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_valid = tlOtherMastersNodeOut_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_opcode = tlOtherMastersNodeOut_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_param = tlOtherMastersNodeOut_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_size = tlOtherMastersNodeOut_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_source = tlOtherMastersNodeOut_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_address = tlOtherMastersNodeOut_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_mask = tlOtherMastersNodeOut_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_data = tlOtherMastersNodeOut_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_b_ready = tlOtherMastersNodeOut_b_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_b_valid = tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_b_bits_opcode = tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_b_bits_param = tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_b_bits_size = tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_b_bits_source = tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] tlOtherMastersNodeIn_b_bits_address = tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [15:0] tlOtherMastersNodeIn_b_bits_mask = tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [127:0] tlOtherMastersNodeIn_b_bits_data = tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_b_bits_corrupt = tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_c_ready = tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_valid = tlOtherMastersNodeOut_c_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_opcode = tlOtherMastersNodeOut_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_param = tlOtherMastersNodeOut_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_size = tlOtherMastersNodeOut_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_source = tlOtherMastersNodeOut_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_address = tlOtherMastersNodeOut_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_data = tlOtherMastersNodeOut_c_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_d_ready = tlOtherMastersNodeOut_d_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_valid = tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_opcode = tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_param = tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_d_bits_size = tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_source = tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_d_bits_sink = tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_denied = tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [127:0] tlOtherMastersNodeIn_d_bits_data = tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_corrupt = tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_e_ready = tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_e_valid = tlOtherMastersNodeOut_e_valid; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:551:17] assign buffer_auto_in_e_bits_sink = tlOtherMastersNodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign tlOtherMastersNodeOut_a_valid = tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_opcode = tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_param = tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_size = tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_source = tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_address = tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_mask = tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_data = tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_ready = tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_valid = tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_opcode = tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_param = tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_size = tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_source = tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_address = tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_data = tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_ready = tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_valid = tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_bits_sink = tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17] assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17] assign auto_trace_source_out_insns_0_valid_0 = traceSourceNodeOut_insns_0_valid; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_iaddr_0 = traceSourceNodeOut_insns_0_iaddr; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_insn_0 = traceSourceNodeOut_insns_0_insn; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_priv_0 = traceSourceNodeOut_insns_0_priv; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_exception_0 = traceSourceNodeOut_insns_0_exception; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_interrupt_0 = traceSourceNodeOut_insns_0_interrupt; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_cause_0 = traceSourceNodeOut_insns_0_cause; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_tval_0 = traceSourceNodeOut_insns_0_tval; // @[RocketTile.scala:141:7] assign auto_trace_source_out_time_0 = traceSourceNodeOut_time; // @[RocketTile.scala:141:7] assign broadcast_2_auto_in_0_valid_0 = bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17] assign broadcast_2_auto_in_0_action = bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17] wire int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_1; // @[MixedNode.scala:542:17] wire x1_int_localOut_1_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_2_0; // @[MixedNode.scala:542:17] assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_0 = x1_int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1 = x1_int_localIn_1; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1_0 = x1_int_localIn_1_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_2_0 = x1_int_localIn_2_0; // @[MixedNode.scala:542:17, :551:17] wire intSinkNodeIn_0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_1; // @[MixedNode.scala:551:17] wire intSinkNodeIn_2; // @[MixedNode.scala:551:17] wire intSinkNodeIn_3; // @[MixedNode.scala:551:17] wire intSinkNodeIn_4; // @[MixedNode.scala:551:17] assign auto_wfi_out_0_0 = wfiNodeOut_0; // @[RocketTile.scala:141:7] reg wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] assign wfiNodeOut_0 = wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] always @(posedge clock) begin // @[RocketTile.scala:141:7] if (reset) // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= 1'h0; // @[Interrupts.scala:131:36] else // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= _core_io_wfi; // @[RocketTile.scala:147:20] always @(posedge) TLXbar_MasterXbar_RocketTile_i2_o1_a32d128s2k4z4c_1 tlMasterXbar ( // @[HierarchicalElement.scala:55:42] .clock (clock), .reset (reset), .auto_anon_in_1_a_ready (widget_1_auto_anon_out_a_ready), .auto_anon_in_1_a_valid (widget_1_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_1_a_bits_address (widget_1_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_1_d_valid (widget_1_auto_anon_out_d_valid), .auto_anon_in_1_d_bits_opcode (widget_1_auto_anon_out_d_bits_opcode), .auto_anon_in_1_d_bits_param (widget_1_auto_anon_out_d_bits_param), .auto_anon_in_1_d_bits_size (widget_1_auto_anon_out_d_bits_size), .auto_anon_in_1_d_bits_sink (widget_1_auto_anon_out_d_bits_sink), .auto_anon_in_1_d_bits_denied (widget_1_auto_anon_out_d_bits_denied), .auto_anon_in_1_d_bits_data (widget_1_auto_anon_out_d_bits_data), .auto_anon_in_1_d_bits_corrupt (widget_1_auto_anon_out_d_bits_corrupt), .auto_anon_in_0_a_ready (widget_auto_anon_out_a_ready), .auto_anon_in_0_a_valid (widget_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_opcode (widget_auto_anon_out_a_bits_opcode), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_param (widget_auto_anon_out_a_bits_param), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_size (widget_auto_anon_out_a_bits_size), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_source (widget_auto_anon_out_a_bits_source), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_address (widget_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_mask (widget_auto_anon_out_a_bits_mask), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_data (widget_auto_anon_out_a_bits_data), // @[WidthWidget.scala:27:9] .auto_anon_in_0_b_ready (widget_auto_anon_out_b_ready), // @[WidthWidget.scala:27:9] .auto_anon_in_0_b_valid (widget_auto_anon_out_b_valid), .auto_anon_in_0_b_bits_opcode (widget_auto_anon_out_b_bits_opcode), .auto_anon_in_0_b_bits_param (widget_auto_anon_out_b_bits_param), .auto_anon_in_0_b_bits_size (widget_auto_anon_out_b_bits_size), .auto_anon_in_0_b_bits_source (widget_auto_anon_out_b_bits_source), .auto_anon_in_0_b_bits_address (widget_auto_anon_out_b_bits_address), .auto_anon_in_0_b_bits_mask (widget_auto_anon_out_b_bits_mask), .auto_anon_in_0_b_bits_data (widget_auto_anon_out_b_bits_data), .auto_anon_in_0_b_bits_corrupt (widget_auto_anon_out_b_bits_corrupt), .auto_anon_in_0_c_ready (widget_auto_anon_out_c_ready), .auto_anon_in_0_c_valid (widget_auto_anon_out_c_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_opcode (widget_auto_anon_out_c_bits_opcode), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_param (widget_auto_anon_out_c_bits_param), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_size (widget_auto_anon_out_c_bits_size), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_source (widget_auto_anon_out_c_bits_source), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_address (widget_auto_anon_out_c_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_data (widget_auto_anon_out_c_bits_data), // @[WidthWidget.scala:27:9] .auto_anon_in_0_d_ready (widget_auto_anon_out_d_ready), // @[WidthWidget.scala:27:9] .auto_anon_in_0_d_valid (widget_auto_anon_out_d_valid), .auto_anon_in_0_d_bits_opcode (widget_auto_anon_out_d_bits_opcode), .auto_anon_in_0_d_bits_param (widget_auto_anon_out_d_bits_param), .auto_anon_in_0_d_bits_size (widget_auto_anon_out_d_bits_size), .auto_anon_in_0_d_bits_source (widget_auto_anon_out_d_bits_source), .auto_anon_in_0_d_bits_sink (widget_auto_anon_out_d_bits_sink), .auto_anon_in_0_d_bits_denied (widget_auto_anon_out_d_bits_denied), .auto_anon_in_0_d_bits_data (widget_auto_anon_out_d_bits_data), .auto_anon_in_0_d_bits_corrupt (widget_auto_anon_out_d_bits_corrupt), .auto_anon_in_0_e_ready (widget_auto_anon_out_e_ready), .auto_anon_in_0_e_valid (widget_auto_anon_out_e_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_e_bits_sink (widget_auto_anon_out_e_bits_sink), // @[WidthWidget.scala:27:9] .auto_anon_out_a_ready (tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_anon_out_a_valid (tlOtherMastersNodeIn_a_valid), .auto_anon_out_a_bits_opcode (tlOtherMastersNodeIn_a_bits_opcode), .auto_anon_out_a_bits_param (tlOtherMastersNodeIn_a_bits_param), .auto_anon_out_a_bits_size (tlOtherMastersNodeIn_a_bits_size), .auto_anon_out_a_bits_source (tlOtherMastersNodeIn_a_bits_source), .auto_anon_out_a_bits_address (tlOtherMastersNodeIn_a_bits_address), .auto_anon_out_a_bits_mask (tlOtherMastersNodeIn_a_bits_mask), .auto_anon_out_a_bits_data (tlOtherMastersNodeIn_a_bits_data), .auto_anon_out_b_ready (tlOtherMastersNodeIn_b_ready), .auto_anon_out_b_valid (tlOtherMastersNodeIn_b_valid), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_opcode (tlOtherMastersNodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_param (tlOtherMastersNodeIn_b_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_size (tlOtherMastersNodeIn_b_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_source (tlOtherMastersNodeIn_b_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_address (tlOtherMastersNodeIn_b_bits_address), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_mask (tlOtherMastersNodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_data (tlOtherMastersNodeIn_b_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_corrupt (tlOtherMastersNodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .auto_anon_out_c_ready (tlOtherMastersNodeIn_c_ready), // @[MixedNode.scala:551:17] .auto_anon_out_c_valid (tlOtherMastersNodeIn_c_valid), .auto_anon_out_c_bits_opcode (tlOtherMastersNodeIn_c_bits_opcode), .auto_anon_out_c_bits_param (tlOtherMastersNodeIn_c_bits_param), .auto_anon_out_c_bits_size (tlOtherMastersNodeIn_c_bits_size), .auto_anon_out_c_bits_source (tlOtherMastersNodeIn_c_bits_source), .auto_anon_out_c_bits_address (tlOtherMastersNodeIn_c_bits_address), .auto_anon_out_c_bits_data (tlOtherMastersNodeIn_c_bits_data), .auto_anon_out_d_ready (tlOtherMastersNodeIn_d_ready), .auto_anon_out_d_valid (tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_opcode (tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_param (tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_size (tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_source (tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_sink (tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_denied (tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_data (tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_corrupt (tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_anon_out_e_ready (tlOtherMastersNodeIn_e_ready), // @[MixedNode.scala:551:17] .auto_anon_out_e_valid (tlOtherMastersNodeIn_e_valid), .auto_anon_out_e_bits_sink (tlOtherMastersNodeIn_e_bits_sink) ); // @[HierarchicalElement.scala:55:42] TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u_1 tlSlaveXbar ( // @[HierarchicalElement.scala:56:41] .clock (clock), .reset (reset) ); // @[HierarchicalElement.scala:56:41] IntXbar_i4_o1_1 intXbar ( // @[HierarchicalElement.scala:57:37] .auto_anon_in_3_0 (x1_int_localOut_2_0), // @[MixedNode.scala:542:17] .auto_anon_in_2_0 (x1_int_localOut_1_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_0 (x1_int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_1 (x1_int_localOut_1), // @[MixedNode.scala:542:17] .auto_anon_in_0_0 (int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_out_0 (intSinkNodeIn_0), .auto_anon_out_1 (intSinkNodeIn_1), .auto_anon_out_2 (intSinkNodeIn_2), .auto_anon_out_3 (intSinkNodeIn_3), .auto_anon_out_4 (intSinkNodeIn_4) ); // @[HierarchicalElement.scala:57:37] DCache_1 dcache ( // @[HellaCache.scala:278:43] .clock (clock), .reset (reset), .auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_out_a_valid (widget_auto_anon_in_a_valid), .auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (widget_auto_anon_in_a_bits_param), .auto_out_a_bits_size (widget_auto_anon_in_a_bits_size), .auto_out_a_bits_source (widget_auto_anon_in_a_bits_source), .auto_out_a_bits_address (widget_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (widget_auto_anon_in_a_bits_data), .auto_out_b_ready (widget_auto_anon_in_b_ready), .auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9] .auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9] .auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9] .auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9] .auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9] .auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9] .auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9] .auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9] .auto_out_c_valid (widget_auto_anon_in_c_valid), .auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode), .auto_out_c_bits_param (widget_auto_anon_in_c_bits_param), .auto_out_c_bits_size (widget_auto_anon_in_c_bits_size), .auto_out_c_bits_source (widget_auto_anon_in_c_bits_source), .auto_out_c_bits_address (widget_auto_anon_in_c_bits_address), .auto_out_c_bits_data (widget_auto_anon_in_c_bits_data), .auto_out_d_ready (widget_auto_anon_in_d_ready), .auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9] .auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9] .auto_out_e_valid (widget_auto_anon_in_e_valid), .auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink), .io_cpu_req_ready (_dcache_io_cpu_req_ready), .io_cpu_req_valid (_dcacheArb_io_mem_req_valid), // @[HellaCache.scala:292:25] .io_cpu_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), // @[HellaCache.scala:292:25] .io_cpu_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), // @[HellaCache.scala:292:25] .io_cpu_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), // @[HellaCache.scala:292:25] .io_cpu_req_bits_size (_dcacheArb_io_mem_req_bits_size), // @[HellaCache.scala:292:25] .io_cpu_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), // @[HellaCache.scala:292:25] .io_cpu_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), // @[HellaCache.scala:292:25] .io_cpu_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), // @[HellaCache.scala:292:25] .io_cpu_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), // @[HellaCache.scala:292:25] .io_cpu_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), // @[HellaCache.scala:292:25] .io_cpu_s1_kill (_dcacheArb_io_mem_s1_kill), // @[HellaCache.scala:292:25] .io_cpu_s1_data_data (_dcacheArb_io_mem_s1_data_data), // @[HellaCache.scala:292:25] .io_cpu_s1_data_mask (8'h0), // @[RocketTile.scala:147:20] .io_cpu_s2_nack (_dcache_io_cpu_s2_nack), .io_cpu_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), .io_cpu_s2_uncached (_dcache_io_cpu_s2_uncached), .io_cpu_s2_paddr (_dcache_io_cpu_s2_paddr), .io_cpu_resp_valid (_dcache_io_cpu_resp_valid), .io_cpu_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), .io_cpu_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), .io_cpu_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), .io_cpu_resp_bits_size (_dcache_io_cpu_resp_bits_size), .io_cpu_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), .io_cpu_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), .io_cpu_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), .io_cpu_resp_bits_data (_dcache_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), .io_cpu_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), .io_cpu_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), .io_cpu_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), .io_cpu_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), .io_cpu_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), .io_cpu_replay_next (_dcache_io_cpu_replay_next), .io_cpu_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), .io_cpu_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), .io_cpu_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), .io_cpu_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), .io_cpu_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), .io_cpu_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), .io_cpu_s2_gpa (_dcache_io_cpu_s2_gpa), .io_cpu_ordered (_dcache_io_cpu_ordered), .io_cpu_store_pending (_dcache_io_cpu_store_pending), .io_cpu_perf_acquire (_dcache_io_cpu_perf_acquire), .io_cpu_perf_release (_dcache_io_cpu_perf_release), .io_cpu_perf_grant (_dcache_io_cpu_perf_grant), .io_cpu_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), .io_cpu_perf_blocked (_dcache_io_cpu_perf_blocked), .io_cpu_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), .io_cpu_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), .io_cpu_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), .io_cpu_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), .io_cpu_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), .io_cpu_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled), // @[HellaCache.scala:292:25] .io_ptw_req_ready (_ptw_io_requestor_0_req_ready), // @[PTW.scala:802:19] .io_ptw_req_valid (_dcache_io_ptw_req_valid), .io_ptw_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_0_resp_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_status_debug (_ptw_io_requestor_0_status_debug), // @[PTW.scala:802:19] .io_ptw_status_cease (_ptw_io_requestor_0_status_cease), // @[PTW.scala:802:19] .io_ptw_status_wfi (_ptw_io_requestor_0_status_wfi), // @[PTW.scala:802:19] .io_ptw_status_isa (_ptw_io_requestor_0_status_isa), // @[PTW.scala:802:19] .io_ptw_status_dprv (_ptw_io_requestor_0_status_dprv), // @[PTW.scala:802:19] .io_ptw_status_dv (_ptw_io_requestor_0_status_dv), // @[PTW.scala:802:19] .io_ptw_status_prv (_ptw_io_requestor_0_status_prv), // @[PTW.scala:802:19] .io_ptw_status_v (_ptw_io_requestor_0_status_v), // @[PTW.scala:802:19] .io_ptw_status_sd (_ptw_io_requestor_0_status_sd), // @[PTW.scala:802:19] .io_ptw_status_mpv (_ptw_io_requestor_0_status_mpv), // @[PTW.scala:802:19] .io_ptw_status_gva (_ptw_io_requestor_0_status_gva), // @[PTW.scala:802:19] .io_ptw_status_tsr (_ptw_io_requestor_0_status_tsr), // @[PTW.scala:802:19] .io_ptw_status_tw (_ptw_io_requestor_0_status_tw), // @[PTW.scala:802:19] .io_ptw_status_tvm (_ptw_io_requestor_0_status_tvm), // @[PTW.scala:802:19] .io_ptw_status_mxr (_ptw_io_requestor_0_status_mxr), // @[PTW.scala:802:19] .io_ptw_status_sum (_ptw_io_requestor_0_status_sum), // @[PTW.scala:802:19] .io_ptw_status_mprv (_ptw_io_requestor_0_status_mprv), // @[PTW.scala:802:19] .io_ptw_status_fs (_ptw_io_requestor_0_status_fs), // @[PTW.scala:802:19] .io_ptw_status_mpp (_ptw_io_requestor_0_status_mpp), // @[PTW.scala:802:19] .io_ptw_status_spp (_ptw_io_requestor_0_status_spp), // @[PTW.scala:802:19] .io_ptw_status_mpie (_ptw_io_requestor_0_status_mpie), // @[PTW.scala:802:19] .io_ptw_status_spie (_ptw_io_requestor_0_status_spie), // @[PTW.scala:802:19] .io_ptw_status_mie (_ptw_io_requestor_0_status_mie), // @[PTW.scala:802:19] .io_ptw_status_sie (_ptw_io_requestor_0_status_sie), // @[PTW.scala:802:19] .io_ptw_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_gstatus_v (_ptw_io_requestor_0_gstatus_v), // @[PTW.scala:802:19] .io_ptw_gstatus_sd (_ptw_io_requestor_0_gstatus_sd), // @[PTW.scala:802:19] .io_ptw_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[HellaCache.scala:278:43] Frontend_1 frontend ( // @[Frontend.scala:393:28] .clock (clock), .reset (reset), .auto_icache_master_out_a_ready (widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_icache_master_out_a_valid (widget_1_auto_anon_in_a_valid), .auto_icache_master_out_a_bits_address (widget_1_auto_anon_in_a_bits_address), .auto_icache_master_out_d_valid (widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_opcode (widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_param (widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_size (widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_sink (widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_denied (widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_data (widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_corrupt (widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .io_cpu_might_request (_core_io_imem_might_request), // @[RocketTile.scala:147:20] .io_cpu_req_valid (_core_io_imem_req_valid), // @[RocketTile.scala:147:20] .io_cpu_req_bits_pc (_core_io_imem_req_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_req_bits_speculative (_core_io_imem_req_bits_speculative), // @[RocketTile.scala:147:20] .io_cpu_sfence_valid (_core_io_imem_sfence_valid), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_addr (_core_io_imem_sfence_bits_addr), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_asid (_core_io_imem_sfence_bits_asid), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_hv (_core_io_imem_sfence_bits_hv), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_hg (_core_io_imem_sfence_bits_hg), // @[RocketTile.scala:147:20] .io_cpu_resp_ready (_core_io_imem_resp_ready), // @[RocketTile.scala:147:20] .io_cpu_resp_valid (_frontend_io_cpu_resp_valid), .io_cpu_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), .io_cpu_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), .io_cpu_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), .io_cpu_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), .io_cpu_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), .io_cpu_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), .io_cpu_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), .io_cpu_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), .io_cpu_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), .io_cpu_resp_bits_data (_frontend_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), .io_cpu_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), .io_cpu_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), .io_cpu_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), .io_cpu_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), .io_cpu_gpa_valid (_frontend_io_cpu_gpa_valid), .io_cpu_gpa_bits (_frontend_io_cpu_gpa_bits), .io_cpu_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), .io_cpu_btb_update_valid (_core_io_imem_btb_update_valid), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_target (_core_io_imem_btb_update_bits_target), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), // @[RocketTile.scala:147:20] .io_cpu_bht_update_valid (_core_io_imem_bht_update_valid), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), // @[RocketTile.scala:147:20] .io_cpu_flush_icache (_core_io_imem_flush_icache), // @[RocketTile.scala:147:20] .io_cpu_npc (_frontend_io_cpu_npc), .io_cpu_perf_acquire (_frontend_io_cpu_perf_acquire), .io_cpu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), .io_cpu_progress (_core_io_imem_progress), // @[RocketTile.scala:147:20] .io_ptw_req_ready (_ptw_io_requestor_1_req_ready), // @[PTW.scala:802:19] .io_ptw_req_valid (_frontend_io_ptw_req_valid), .io_ptw_req_bits_valid (_frontend_io_ptw_req_bits_valid), .io_ptw_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_1_resp_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_status_debug (_ptw_io_requestor_1_status_debug), // @[PTW.scala:802:19] .io_ptw_status_cease (_ptw_io_requestor_1_status_cease), // @[PTW.scala:802:19] .io_ptw_status_wfi (_ptw_io_requestor_1_status_wfi), // @[PTW.scala:802:19] .io_ptw_status_isa (_ptw_io_requestor_1_status_isa), // @[PTW.scala:802:19] .io_ptw_status_dprv (_ptw_io_requestor_1_status_dprv), // @[PTW.scala:802:19] .io_ptw_status_dv (_ptw_io_requestor_1_status_dv), // @[PTW.scala:802:19] .io_ptw_status_prv (_ptw_io_requestor_1_status_prv), // @[PTW.scala:802:19] .io_ptw_status_v (_ptw_io_requestor_1_status_v), // @[PTW.scala:802:19] .io_ptw_status_sd (_ptw_io_requestor_1_status_sd), // @[PTW.scala:802:19] .io_ptw_status_mpv (_ptw_io_requestor_1_status_mpv), // @[PTW.scala:802:19] .io_ptw_status_gva (_ptw_io_requestor_1_status_gva), // @[PTW.scala:802:19] .io_ptw_status_tsr (_ptw_io_requestor_1_status_tsr), // @[PTW.scala:802:19] .io_ptw_status_tw (_ptw_io_requestor_1_status_tw), // @[PTW.scala:802:19] .io_ptw_status_tvm (_ptw_io_requestor_1_status_tvm), // @[PTW.scala:802:19] .io_ptw_status_mxr (_ptw_io_requestor_1_status_mxr), // @[PTW.scala:802:19] .io_ptw_status_sum (_ptw_io_requestor_1_status_sum), // @[PTW.scala:802:19] .io_ptw_status_mprv (_ptw_io_requestor_1_status_mprv), // @[PTW.scala:802:19] .io_ptw_status_fs (_ptw_io_requestor_1_status_fs), // @[PTW.scala:802:19] .io_ptw_status_mpp (_ptw_io_requestor_1_status_mpp), // @[PTW.scala:802:19] .io_ptw_status_spp (_ptw_io_requestor_1_status_spp), // @[PTW.scala:802:19] .io_ptw_status_mpie (_ptw_io_requestor_1_status_mpie), // @[PTW.scala:802:19] .io_ptw_status_spie (_ptw_io_requestor_1_status_spie), // @[PTW.scala:802:19] .io_ptw_status_mie (_ptw_io_requestor_1_status_mie), // @[PTW.scala:802:19] .io_ptw_status_sie (_ptw_io_requestor_1_status_sie), // @[PTW.scala:802:19] .io_ptw_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_gstatus_v (_ptw_io_requestor_1_gstatus_v), // @[PTW.scala:802:19] .io_ptw_gstatus_sd (_ptw_io_requestor_1_gstatus_sd), // @[PTW.scala:802:19] .io_ptw_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[Frontend.scala:393:28] TLFragmenter_1 fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset) ); // @[Fragmenter.scala:345:34] FPU_1 fpuOpt ( // @[RocketTile.scala:242:62] .clock (clock), .reset (reset), .io_hartid (_core_io_fpu_hartid), // @[RocketTile.scala:147:20] .io_time (_core_io_fpu_time), // @[RocketTile.scala:147:20] .io_inst (_core_io_fpu_inst), // @[RocketTile.scala:147:20] .io_fromint_data (_core_io_fpu_fromint_data), // @[RocketTile.scala:147:20] .io_fcsr_rm (_core_io_fpu_fcsr_rm), // @[RocketTile.scala:147:20] .io_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), .io_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), .io_store_data (_fpuOpt_io_store_data), .io_toint_data (_fpuOpt_io_toint_data), .io_ll_resp_val (_core_io_fpu_ll_resp_val), // @[RocketTile.scala:147:20] .io_ll_resp_type (_core_io_fpu_ll_resp_type), // @[RocketTile.scala:147:20] .io_ll_resp_tag (_core_io_fpu_ll_resp_tag), // @[RocketTile.scala:147:20] .io_ll_resp_data (_core_io_fpu_ll_resp_data), // @[RocketTile.scala:147:20] .io_valid (_core_io_fpu_valid), // @[RocketTile.scala:147:20] .io_fcsr_rdy (_fpuOpt_io_fcsr_rdy), .io_nack_mem (_fpuOpt_io_nack_mem), .io_illegal_rm (_fpuOpt_io_illegal_rm), .io_killx (_core_io_fpu_killx), // @[RocketTile.scala:147:20] .io_killm (_core_io_fpu_killm), // @[RocketTile.scala:147:20] .io_dec_ldst (_fpuOpt_io_dec_ldst), .io_dec_wen (_fpuOpt_io_dec_wen), .io_dec_ren1 (_fpuOpt_io_dec_ren1), .io_dec_ren2 (_fpuOpt_io_dec_ren2), .io_dec_ren3 (_fpuOpt_io_dec_ren3), .io_dec_swap12 (_fpuOpt_io_dec_swap12), .io_dec_swap23 (_fpuOpt_io_dec_swap23), .io_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), .io_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), .io_dec_fromint (_fpuOpt_io_dec_fromint), .io_dec_toint (_fpuOpt_io_dec_toint), .io_dec_fastpipe (_fpuOpt_io_dec_fastpipe), .io_dec_fma (_fpuOpt_io_dec_fma), .io_dec_div (_fpuOpt_io_dec_div), .io_dec_sqrt (_fpuOpt_io_dec_sqrt), .io_dec_wflags (_fpuOpt_io_dec_wflags), .io_dec_vec (_fpuOpt_io_dec_vec), .io_sboard_set (_fpuOpt_io_sboard_set), .io_sboard_clr (_fpuOpt_io_sboard_clr), .io_sboard_clra (_fpuOpt_io_sboard_clra), .io_keep_clock_enabled (_core_io_fpu_keep_clock_enabled) // @[RocketTile.scala:147:20] ); // @[RocketTile.scala:242:62] HellaCacheArbiter_1 dcacheArb ( // @[HellaCache.scala:292:25] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_dcacheArb_io_requestor_0_req_ready), .io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[PTW.scala:802:19] .io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[PTW.scala:802:19] .io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[PTW.scala:802:19] .io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[PTW.scala:802:19] .io_requestor_0_s2_nack (_dcacheArb_io_requestor_0_s2_nack), .io_requestor_0_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), .io_requestor_0_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), .io_requestor_0_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), .io_requestor_0_resp_valid (_dcacheArb_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), .io_requestor_0_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), .io_requestor_0_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), .io_requestor_0_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), .io_requestor_0_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), .io_requestor_0_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), .io_requestor_0_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), .io_requestor_0_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), .io_requestor_0_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), .io_requestor_0_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), .io_requestor_0_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), .io_requestor_0_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), .io_requestor_0_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), .io_requestor_0_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), .io_requestor_0_replay_next (_dcacheArb_io_requestor_0_replay_next), .io_requestor_0_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), .io_requestor_0_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), .io_requestor_0_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), .io_requestor_0_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), .io_requestor_0_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), .io_requestor_0_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), .io_requestor_0_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), .io_requestor_0_ordered (_dcacheArb_io_requestor_0_ordered), .io_requestor_0_store_pending (_dcacheArb_io_requestor_0_store_pending), .io_requestor_0_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), .io_requestor_0_perf_release (_dcacheArb_io_requestor_0_perf_release), .io_requestor_0_perf_grant (_dcacheArb_io_requestor_0_perf_grant), .io_requestor_0_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), .io_requestor_0_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), .io_requestor_0_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), .io_requestor_0_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), .io_requestor_0_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), .io_requestor_0_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), .io_requestor_0_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), .io_requestor_1_req_ready (_dcacheArb_io_requestor_1_req_ready), .io_requestor_1_req_valid (_core_io_dmem_req_valid), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_addr (_core_io_dmem_req_bits_addr), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_tag (_core_io_dmem_req_bits_tag), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_cmd (_core_io_dmem_req_bits_cmd), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_size (_core_io_dmem_req_bits_size), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_signed (_core_io_dmem_req_bits_signed), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_dprv (_core_io_dmem_req_bits_dprv), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_dv (_core_io_dmem_req_bits_dv), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), // @[RocketTile.scala:147:20] .io_requestor_1_s1_kill (_core_io_dmem_s1_kill), // @[RocketTile.scala:147:20] .io_requestor_1_s1_data_data (_core_io_dmem_s1_data_data), // @[RocketTile.scala:147:20] .io_requestor_1_s2_nack (_dcacheArb_io_requestor_1_s2_nack), .io_requestor_1_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), .io_requestor_1_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), .io_requestor_1_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), .io_requestor_1_resp_valid (_dcacheArb_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), .io_requestor_1_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), .io_requestor_1_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), .io_requestor_1_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), .io_requestor_1_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), .io_requestor_1_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), .io_requestor_1_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), .io_requestor_1_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), .io_requestor_1_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), .io_requestor_1_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), .io_requestor_1_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), .io_requestor_1_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), .io_requestor_1_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), .io_requestor_1_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), .io_requestor_1_replay_next (_dcacheArb_io_requestor_1_replay_next), .io_requestor_1_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), .io_requestor_1_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), .io_requestor_1_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), .io_requestor_1_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), .io_requestor_1_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), .io_requestor_1_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), .io_requestor_1_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), .io_requestor_1_ordered (_dcacheArb_io_requestor_1_ordered), .io_requestor_1_store_pending (_dcacheArb_io_requestor_1_store_pending), .io_requestor_1_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), .io_requestor_1_perf_release (_dcacheArb_io_requestor_1_perf_release), .io_requestor_1_perf_grant (_dcacheArb_io_requestor_1_perf_grant), .io_requestor_1_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), .io_requestor_1_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), .io_requestor_1_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), .io_requestor_1_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), .io_requestor_1_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), .io_requestor_1_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), .io_requestor_1_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore), .io_requestor_1_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), // @[RocketTile.scala:147:20] .io_mem_req_ready (_dcache_io_cpu_req_ready), // @[HellaCache.scala:278:43] .io_mem_req_valid (_dcacheArb_io_mem_req_valid), .io_mem_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), .io_mem_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), .io_mem_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), .io_mem_req_bits_size (_dcacheArb_io_mem_req_bits_size), .io_mem_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), .io_mem_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), .io_mem_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), .io_mem_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), .io_mem_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), .io_mem_s1_kill (_dcacheArb_io_mem_s1_kill), .io_mem_s1_data_data (_dcacheArb_io_mem_s1_data_data), .io_mem_s2_nack (_dcache_io_cpu_s2_nack), // @[HellaCache.scala:278:43] .io_mem_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), // @[HellaCache.scala:278:43] .io_mem_s2_uncached (_dcache_io_cpu_s2_uncached), // @[HellaCache.scala:278:43] .io_mem_s2_paddr (_dcache_io_cpu_s2_paddr), // @[HellaCache.scala:278:43] .io_mem_resp_valid (_dcache_io_cpu_resp_valid), // @[HellaCache.scala:278:43] .io_mem_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), // @[HellaCache.scala:278:43] .io_mem_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), // @[HellaCache.scala:278:43] .io_mem_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), // @[HellaCache.scala:278:43] .io_mem_resp_bits_size (_dcache_io_cpu_resp_bits_size), // @[HellaCache.scala:278:43] .io_mem_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), // @[HellaCache.scala:278:43] .io_mem_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), // @[HellaCache.scala:278:43] .io_mem_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data (_dcache_io_cpu_resp_bits_data), // @[HellaCache.scala:278:43] .io_mem_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), // @[HellaCache.scala:278:43] .io_mem_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), // @[HellaCache.scala:278:43] .io_mem_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), // @[HellaCache.scala:278:43] .io_mem_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), // @[HellaCache.scala:278:43] .io_mem_replay_next (_dcache_io_cpu_replay_next), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), // @[HellaCache.scala:278:43] .io_mem_s2_gpa (_dcache_io_cpu_s2_gpa), // @[HellaCache.scala:278:43] .io_mem_ordered (_dcache_io_cpu_ordered), // @[HellaCache.scala:278:43] .io_mem_store_pending (_dcache_io_cpu_store_pending), // @[HellaCache.scala:278:43] .io_mem_perf_acquire (_dcache_io_cpu_perf_acquire), // @[HellaCache.scala:278:43] .io_mem_perf_release (_dcache_io_cpu_perf_release), // @[HellaCache.scala:278:43] .io_mem_perf_grant (_dcache_io_cpu_perf_grant), // @[HellaCache.scala:278:43] .io_mem_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), // @[HellaCache.scala:278:43] .io_mem_perf_blocked (_dcache_io_cpu_perf_blocked), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:278:43] .io_mem_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:278:43] .io_mem_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:278:43] .io_mem_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled) ); // @[HellaCache.scala:292:25] PTW_1 ptw ( // @[PTW.scala:802:19] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready), .io_requestor_0_req_valid (_dcache_io_ptw_req_valid), // @[HellaCache.scala:278:43] .io_requestor_0_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), // @[HellaCache.scala:278:43] .io_requestor_0_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), // @[HellaCache.scala:278:43] .io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), .io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), .io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), .io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), .io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), .io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), .io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), .io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), .io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), .io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), .io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), .io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), .io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), .io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), .io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), .io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), .io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), .io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), .io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), .io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), .io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), .io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), .io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), .io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), .io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), .io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug), .io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease), .io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi), .io_requestor_0_status_isa (_ptw_io_requestor_0_status_isa), .io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv), .io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv), .io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv), .io_requestor_0_status_v (_ptw_io_requestor_0_status_v), .io_requestor_0_status_sd (_ptw_io_requestor_0_status_sd), .io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv), .io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva), .io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr), .io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw), .io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm), .io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr), .io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum), .io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv), .io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs), .io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp), .io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp), .io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie), .io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie), .io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie), .io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie), .io_requestor_0_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), .io_requestor_0_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), .io_requestor_0_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), .io_requestor_0_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), .io_requestor_0_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), .io_requestor_0_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), .io_requestor_0_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), .io_requestor_0_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), .io_requestor_0_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), .io_requestor_0_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), .io_requestor_0_gstatus_v (_ptw_io_requestor_0_gstatus_v), .io_requestor_0_gstatus_sd (_ptw_io_requestor_0_gstatus_sd), .io_requestor_0_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), .io_requestor_0_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), .io_requestor_0_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), .io_requestor_0_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), .io_requestor_0_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), .io_requestor_0_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), .io_requestor_0_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), .io_requestor_0_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), .io_requestor_0_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), .io_requestor_0_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), .io_requestor_0_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), .io_requestor_0_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), .io_requestor_0_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), .io_requestor_0_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), .io_requestor_0_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), .io_requestor_0_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), .io_requestor_0_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), .io_requestor_0_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), .io_requestor_0_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), .io_requestor_0_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), .io_requestor_0_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), .io_requestor_0_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), .io_requestor_0_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), .io_requestor_0_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), .io_requestor_0_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), .io_requestor_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), .io_requestor_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), .io_requestor_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), .io_requestor_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), .io_requestor_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), .io_requestor_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), .io_requestor_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), .io_requestor_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), .io_requestor_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), .io_requestor_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), .io_requestor_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), .io_requestor_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), .io_requestor_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), .io_requestor_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), .io_requestor_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), .io_requestor_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), .io_requestor_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), .io_requestor_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), .io_requestor_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), .io_requestor_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), .io_requestor_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), .io_requestor_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), .io_requestor_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), .io_requestor_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), .io_requestor_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), .io_requestor_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), .io_requestor_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), .io_requestor_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), .io_requestor_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), .io_requestor_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), .io_requestor_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), .io_requestor_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), .io_requestor_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), .io_requestor_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), .io_requestor_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), .io_requestor_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), .io_requestor_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), .io_requestor_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), .io_requestor_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), .io_requestor_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), .io_requestor_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), .io_requestor_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), .io_requestor_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), .io_requestor_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), .io_requestor_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), .io_requestor_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), .io_requestor_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), .io_requestor_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), .io_requestor_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), .io_requestor_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), .io_requestor_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), .io_requestor_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), .io_requestor_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), .io_requestor_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), .io_requestor_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), .io_requestor_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), .io_requestor_0_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), .io_requestor_0_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), .io_requestor_0_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), .io_requestor_0_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), .io_requestor_0_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), .io_requestor_0_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), .io_requestor_0_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), .io_requestor_0_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), .io_requestor_0_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), .io_requestor_0_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), .io_requestor_0_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), .io_requestor_0_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), .io_requestor_0_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), .io_requestor_0_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), .io_requestor_0_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), .io_requestor_0_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value), .io_requestor_1_req_ready (_ptw_io_requestor_1_req_ready), .io_requestor_1_req_valid (_frontend_io_ptw_req_valid), // @[Frontend.scala:393:28] .io_requestor_1_req_bits_valid (_frontend_io_ptw_req_bits_valid), // @[Frontend.scala:393:28] .io_requestor_1_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), // @[Frontend.scala:393:28] .io_requestor_1_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), // @[Frontend.scala:393:28] .io_requestor_1_resp_valid (_ptw_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), .io_requestor_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), .io_requestor_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), .io_requestor_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), .io_requestor_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), .io_requestor_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), .io_requestor_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), .io_requestor_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), .io_requestor_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), .io_requestor_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), .io_requestor_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), .io_requestor_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), .io_requestor_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), .io_requestor_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), .io_requestor_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), .io_requestor_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), .io_requestor_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), .io_requestor_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), .io_requestor_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), .io_requestor_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), .io_requestor_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), .io_requestor_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), .io_requestor_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), .io_requestor_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), .io_requestor_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), .io_requestor_1_status_debug (_ptw_io_requestor_1_status_debug), .io_requestor_1_status_cease (_ptw_io_requestor_1_status_cease), .io_requestor_1_status_wfi (_ptw_io_requestor_1_status_wfi), .io_requestor_1_status_isa (_ptw_io_requestor_1_status_isa), .io_requestor_1_status_dprv (_ptw_io_requestor_1_status_dprv), .io_requestor_1_status_dv (_ptw_io_requestor_1_status_dv), .io_requestor_1_status_prv (_ptw_io_requestor_1_status_prv), .io_requestor_1_status_v (_ptw_io_requestor_1_status_v), .io_requestor_1_status_sd (_ptw_io_requestor_1_status_sd), .io_requestor_1_status_mpv (_ptw_io_requestor_1_status_mpv), .io_requestor_1_status_gva (_ptw_io_requestor_1_status_gva), .io_requestor_1_status_tsr (_ptw_io_requestor_1_status_tsr), .io_requestor_1_status_tw (_ptw_io_requestor_1_status_tw), .io_requestor_1_status_tvm (_ptw_io_requestor_1_status_tvm), .io_requestor_1_status_mxr (_ptw_io_requestor_1_status_mxr), .io_requestor_1_status_sum (_ptw_io_requestor_1_status_sum), .io_requestor_1_status_mprv (_ptw_io_requestor_1_status_mprv), .io_requestor_1_status_fs (_ptw_io_requestor_1_status_fs), .io_requestor_1_status_mpp (_ptw_io_requestor_1_status_mpp), .io_requestor_1_status_spp (_ptw_io_requestor_1_status_spp), .io_requestor_1_status_mpie (_ptw_io_requestor_1_status_mpie), .io_requestor_1_status_spie (_ptw_io_requestor_1_status_spie), .io_requestor_1_status_mie (_ptw_io_requestor_1_status_mie), .io_requestor_1_status_sie (_ptw_io_requestor_1_status_sie), .io_requestor_1_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), .io_requestor_1_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), .io_requestor_1_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), .io_requestor_1_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), .io_requestor_1_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), .io_requestor_1_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), .io_requestor_1_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), .io_requestor_1_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), .io_requestor_1_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), .io_requestor_1_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), .io_requestor_1_gstatus_v (_ptw_io_requestor_1_gstatus_v), .io_requestor_1_gstatus_sd (_ptw_io_requestor_1_gstatus_sd), .io_requestor_1_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), .io_requestor_1_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), .io_requestor_1_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), .io_requestor_1_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), .io_requestor_1_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), .io_requestor_1_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), .io_requestor_1_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), .io_requestor_1_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), .io_requestor_1_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), .io_requestor_1_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), .io_requestor_1_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), .io_requestor_1_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), .io_requestor_1_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), .io_requestor_1_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), .io_requestor_1_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), .io_requestor_1_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), .io_requestor_1_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), .io_requestor_1_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), .io_requestor_1_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), .io_requestor_1_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), .io_requestor_1_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), .io_requestor_1_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), .io_requestor_1_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), .io_requestor_1_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), .io_requestor_1_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), .io_requestor_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), .io_requestor_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), .io_requestor_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), .io_requestor_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), .io_requestor_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), .io_requestor_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), .io_requestor_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), .io_requestor_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), .io_requestor_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), .io_requestor_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), .io_requestor_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), .io_requestor_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), .io_requestor_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), .io_requestor_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), .io_requestor_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), .io_requestor_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), .io_requestor_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), .io_requestor_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), .io_requestor_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), .io_requestor_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), .io_requestor_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), .io_requestor_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), .io_requestor_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), .io_requestor_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), .io_requestor_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), .io_requestor_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), .io_requestor_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), .io_requestor_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), .io_requestor_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), .io_requestor_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), .io_requestor_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), .io_requestor_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), .io_requestor_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), .io_requestor_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), .io_requestor_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), .io_requestor_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), .io_requestor_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), .io_requestor_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), .io_requestor_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), .io_requestor_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), .io_requestor_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), .io_requestor_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), .io_requestor_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), .io_requestor_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), .io_requestor_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), .io_requestor_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), .io_requestor_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), .io_requestor_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), .io_requestor_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), .io_requestor_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), .io_requestor_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), .io_requestor_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), .io_requestor_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), .io_requestor_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), .io_requestor_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), .io_requestor_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), .io_requestor_1_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), .io_requestor_1_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), .io_requestor_1_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), .io_requestor_1_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), .io_requestor_1_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), .io_requestor_1_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), .io_requestor_1_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), .io_requestor_1_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), .io_requestor_1_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), .io_requestor_1_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), .io_requestor_1_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), .io_requestor_1_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), .io_requestor_1_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), .io_requestor_1_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), .io_requestor_1_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), .io_requestor_1_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value), .io_mem_req_ready (_dcacheArb_io_requestor_0_req_ready), // @[HellaCache.scala:292:25] .io_mem_req_valid (_ptw_io_mem_req_valid), .io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr), .io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv), .io_mem_s1_kill (_ptw_io_mem_s1_kill), .io_mem_s2_nack (_dcacheArb_io_requestor_0_s2_nack), // @[HellaCache.scala:292:25] .io_mem_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), // @[HellaCache.scala:292:25] .io_mem_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), // @[HellaCache.scala:292:25] .io_mem_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), // @[HellaCache.scala:292:25] .io_mem_resp_valid (_dcacheArb_io_requestor_0_resp_valid), // @[HellaCache.scala:292:25] .io_mem_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), // @[HellaCache.scala:292:25] .io_mem_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), // @[HellaCache.scala:292:25] .io_mem_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_mem_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), // @[HellaCache.scala:292:25] .io_mem_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), // @[HellaCache.scala:292:25] .io_mem_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_mem_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), // @[HellaCache.scala:292:25] .io_mem_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), // @[HellaCache.scala:292:25] .io_mem_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), // @[HellaCache.scala:292:25] .io_mem_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_mem_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_mem_replay_next (_dcacheArb_io_requestor_0_replay_next), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_mem_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), // @[HellaCache.scala:292:25] .io_mem_ordered (_dcacheArb_io_requestor_0_ordered), // @[HellaCache.scala:292:25] .io_mem_store_pending (_dcacheArb_io_requestor_0_store_pending), // @[HellaCache.scala:292:25] .io_mem_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), // @[HellaCache.scala:292:25] .io_mem_perf_release (_dcacheArb_io_requestor_0_perf_release), // @[HellaCache.scala:292:25] .io_mem_perf_grant (_dcacheArb_io_requestor_0_perf_grant), // @[HellaCache.scala:292:25] .io_mem_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_mem_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25] .io_mem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25] .io_mem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25] .io_dpath_ptbr_mode (_core_io_ptw_ptbr_mode), // @[RocketTile.scala:147:20] .io_dpath_ptbr_ppn (_core_io_ptw_ptbr_ppn), // @[RocketTile.scala:147:20] .io_dpath_sfence_valid (_core_io_ptw_sfence_valid), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), // @[RocketTile.scala:147:20] .io_dpath_status_debug (_core_io_ptw_status_debug), // @[RocketTile.scala:147:20] .io_dpath_status_cease (_core_io_ptw_status_cease), // @[RocketTile.scala:147:20] .io_dpath_status_wfi (_core_io_ptw_status_wfi), // @[RocketTile.scala:147:20] .io_dpath_status_isa (_core_io_ptw_status_isa), // @[RocketTile.scala:147:20] .io_dpath_status_dprv (_core_io_ptw_status_dprv), // @[RocketTile.scala:147:20] .io_dpath_status_dv (_core_io_ptw_status_dv), // @[RocketTile.scala:147:20] .io_dpath_status_prv (_core_io_ptw_status_prv), // @[RocketTile.scala:147:20] .io_dpath_status_v (_core_io_ptw_status_v), // @[RocketTile.scala:147:20] .io_dpath_status_sd (_core_io_ptw_status_sd), // @[RocketTile.scala:147:20] .io_dpath_status_mpv (_core_io_ptw_status_mpv), // @[RocketTile.scala:147:20] .io_dpath_status_gva (_core_io_ptw_status_gva), // @[RocketTile.scala:147:20] .io_dpath_status_tsr (_core_io_ptw_status_tsr), // @[RocketTile.scala:147:20] .io_dpath_status_tw (_core_io_ptw_status_tw), // @[RocketTile.scala:147:20] .io_dpath_status_tvm (_core_io_ptw_status_tvm), // @[RocketTile.scala:147:20] .io_dpath_status_mxr (_core_io_ptw_status_mxr), // @[RocketTile.scala:147:20] .io_dpath_status_sum (_core_io_ptw_status_sum), // @[RocketTile.scala:147:20] .io_dpath_status_mprv (_core_io_ptw_status_mprv), // @[RocketTile.scala:147:20] .io_dpath_status_fs (_core_io_ptw_status_fs), // @[RocketTile.scala:147:20] .io_dpath_status_mpp (_core_io_ptw_status_mpp), // @[RocketTile.scala:147:20] .io_dpath_status_spp (_core_io_ptw_status_spp), // @[RocketTile.scala:147:20] .io_dpath_status_mpie (_core_io_ptw_status_mpie), // @[RocketTile.scala:147:20] .io_dpath_status_spie (_core_io_ptw_status_spie), // @[RocketTile.scala:147:20] .io_dpath_status_mie (_core_io_ptw_status_mie), // @[RocketTile.scala:147:20] .io_dpath_status_sie (_core_io_ptw_status_sie), // @[RocketTile.scala:147:20] .io_dpath_hstatus_spvp (_core_io_ptw_hstatus_spvp), // @[RocketTile.scala:147:20] .io_dpath_hstatus_spv (_core_io_ptw_hstatus_spv), // @[RocketTile.scala:147:20] .io_dpath_hstatus_gva (_core_io_ptw_hstatus_gva), // @[RocketTile.scala:147:20] .io_dpath_gstatus_debug (_core_io_ptw_gstatus_debug), // @[RocketTile.scala:147:20] .io_dpath_gstatus_cease (_core_io_ptw_gstatus_cease), // @[RocketTile.scala:147:20] .io_dpath_gstatus_wfi (_core_io_ptw_gstatus_wfi), // @[RocketTile.scala:147:20] .io_dpath_gstatus_isa (_core_io_ptw_gstatus_isa), // @[RocketTile.scala:147:20] .io_dpath_gstatus_dprv (_core_io_ptw_gstatus_dprv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_dv (_core_io_ptw_gstatus_dv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_prv (_core_io_ptw_gstatus_prv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_v (_core_io_ptw_gstatus_v), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sd (_core_io_ptw_gstatus_sd), // @[RocketTile.scala:147:20] .io_dpath_gstatus_zero2 (_core_io_ptw_gstatus_zero2), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpv (_core_io_ptw_gstatus_mpv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_gva (_core_io_ptw_gstatus_gva), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mbe (_core_io_ptw_gstatus_mbe), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sbe (_core_io_ptw_gstatus_sbe), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sxl (_core_io_ptw_gstatus_sxl), // @[RocketTile.scala:147:20] .io_dpath_gstatus_zero1 (_core_io_ptw_gstatus_zero1), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tsr (_core_io_ptw_gstatus_tsr), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tw (_core_io_ptw_gstatus_tw), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tvm (_core_io_ptw_gstatus_tvm), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mxr (_core_io_ptw_gstatus_mxr), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sum (_core_io_ptw_gstatus_sum), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mprv (_core_io_ptw_gstatus_mprv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_fs (_core_io_ptw_gstatus_fs), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpp (_core_io_ptw_gstatus_mpp), // @[RocketTile.scala:147:20] .io_dpath_gstatus_vs (_core_io_ptw_gstatus_vs), // @[RocketTile.scala:147:20] .io_dpath_gstatus_spp (_core_io_ptw_gstatus_spp), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpie (_core_io_ptw_gstatus_mpie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_ube (_core_io_ptw_gstatus_ube), // @[RocketTile.scala:147:20] .io_dpath_gstatus_spie (_core_io_ptw_gstatus_spie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_upie (_core_io_ptw_gstatus_upie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mie (_core_io_ptw_gstatus_mie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_hie (_core_io_ptw_gstatus_hie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sie (_core_io_ptw_gstatus_sie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_uie (_core_io_ptw_gstatus_uie), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_addr (_core_io_ptw_pmp_0_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_mask (_core_io_ptw_pmp_0_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_addr (_core_io_ptw_pmp_1_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_mask (_core_io_ptw_pmp_1_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_addr (_core_io_ptw_pmp_2_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_mask (_core_io_ptw_pmp_2_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_addr (_core_io_ptw_pmp_3_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_mask (_core_io_ptw_pmp_3_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_addr (_core_io_ptw_pmp_4_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_mask (_core_io_ptw_pmp_4_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_addr (_core_io_ptw_pmp_5_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_mask (_core_io_ptw_pmp_5_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_addr (_core_io_ptw_pmp_6_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_mask (_core_io_ptw_pmp_6_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_addr (_core_io_ptw_pmp_7_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_mask (_core_io_ptw_pmp_7_mask), // @[RocketTile.scala:147:20] .io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), .io_dpath_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), .io_dpath_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), // @[RocketTile.scala:147:20] .io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled) ); // @[PTW.scala:802:19] Rocket_1 core ( // @[RocketTile.scala:147:20] .clock (clock), .reset (reset), .io_hartid (hartIdSinkNodeIn), // @[MixedNode.scala:551:17] .io_interrupts_debug (intSinkNodeIn_0), // @[MixedNode.scala:551:17] .io_interrupts_mtip (intSinkNodeIn_2), // @[MixedNode.scala:551:17] .io_interrupts_msip (intSinkNodeIn_1), // @[MixedNode.scala:551:17] .io_interrupts_meip (intSinkNodeIn_3), // @[MixedNode.scala:551:17] .io_interrupts_seip (intSinkNodeIn_4), // @[MixedNode.scala:551:17] .io_imem_might_request (_core_io_imem_might_request), .io_imem_req_valid (_core_io_imem_req_valid), .io_imem_req_bits_pc (_core_io_imem_req_bits_pc), .io_imem_req_bits_speculative (_core_io_imem_req_bits_speculative), .io_imem_sfence_valid (_core_io_imem_sfence_valid), .io_imem_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), .io_imem_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), .io_imem_sfence_bits_addr (_core_io_imem_sfence_bits_addr), .io_imem_sfence_bits_asid (_core_io_imem_sfence_bits_asid), .io_imem_sfence_bits_hv (_core_io_imem_sfence_bits_hv), .io_imem_sfence_bits_hg (_core_io_imem_sfence_bits_hg), .io_imem_resp_ready (_core_io_imem_resp_ready), .io_imem_resp_valid (_frontend_io_cpu_resp_valid), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), // @[Frontend.scala:393:28] .io_imem_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), // @[Frontend.scala:393:28] .io_imem_resp_bits_data (_frontend_io_cpu_resp_bits_data), // @[Frontend.scala:393:28] .io_imem_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), // @[Frontend.scala:393:28] .io_imem_gpa_valid (_frontend_io_cpu_gpa_valid), // @[Frontend.scala:393:28] .io_imem_gpa_bits (_frontend_io_cpu_gpa_bits), // @[Frontend.scala:393:28] .io_imem_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), // @[Frontend.scala:393:28] .io_imem_btb_update_valid (_core_io_imem_btb_update_valid), .io_imem_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), .io_imem_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), .io_imem_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), .io_imem_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), .io_imem_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), .io_imem_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), .io_imem_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), .io_imem_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), .io_imem_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), .io_imem_btb_update_bits_target (_core_io_imem_btb_update_bits_target), .io_imem_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), .io_imem_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), .io_imem_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), .io_imem_bht_update_valid (_core_io_imem_bht_update_valid), .io_imem_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), .io_imem_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), .io_imem_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), .io_imem_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), .io_imem_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), .io_imem_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), .io_imem_flush_icache (_core_io_imem_flush_icache), .io_imem_npc (_frontend_io_cpu_npc), // @[Frontend.scala:393:28] .io_imem_perf_acquire (_frontend_io_cpu_perf_acquire), // @[Frontend.scala:393:28] .io_imem_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), // @[Frontend.scala:393:28] .io_imem_progress (_core_io_imem_progress), .io_dmem_req_ready (_dcacheArb_io_requestor_1_req_ready), // @[HellaCache.scala:292:25] .io_dmem_req_valid (_core_io_dmem_req_valid), .io_dmem_req_bits_addr (_core_io_dmem_req_bits_addr), .io_dmem_req_bits_tag (_core_io_dmem_req_bits_tag), .io_dmem_req_bits_cmd (_core_io_dmem_req_bits_cmd), .io_dmem_req_bits_size (_core_io_dmem_req_bits_size), .io_dmem_req_bits_signed (_core_io_dmem_req_bits_signed), .io_dmem_req_bits_dprv (_core_io_dmem_req_bits_dprv), .io_dmem_req_bits_dv (_core_io_dmem_req_bits_dv), .io_dmem_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), .io_dmem_s1_kill (_core_io_dmem_s1_kill), .io_dmem_s1_data_data (_core_io_dmem_s1_data_data), .io_dmem_s2_nack (_dcacheArb_io_requestor_1_s2_nack), // @[HellaCache.scala:292:25] .io_dmem_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), // @[HellaCache.scala:292:25] .io_dmem_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), // @[HellaCache.scala:292:25] .io_dmem_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), // @[HellaCache.scala:292:25] .io_dmem_resp_valid (_dcacheArb_io_requestor_1_resp_valid), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_dmem_replay_next (_dcacheArb_io_requestor_1_replay_next), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_dmem_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), // @[HellaCache.scala:292:25] .io_dmem_ordered (_dcacheArb_io_requestor_1_ordered), // @[HellaCache.scala:292:25] .io_dmem_store_pending (_dcacheArb_io_requestor_1_store_pending), // @[HellaCache.scala:292:25] .io_dmem_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), // @[HellaCache.scala:292:25] .io_dmem_perf_release (_dcacheArb_io_requestor_1_perf_release), // @[HellaCache.scala:292:25] .io_dmem_perf_grant (_dcacheArb_io_requestor_1_perf_grant), // @[HellaCache.scala:292:25] .io_dmem_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_dmem_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25] .io_dmem_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), .io_ptw_ptbr_mode (_core_io_ptw_ptbr_mode), .io_ptw_ptbr_ppn (_core_io_ptw_ptbr_ppn), .io_ptw_sfence_valid (_core_io_ptw_sfence_valid), .io_ptw_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), .io_ptw_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), .io_ptw_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), .io_ptw_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), .io_ptw_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), .io_ptw_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), .io_ptw_status_debug (_core_io_ptw_status_debug), .io_ptw_status_cease (_core_io_ptw_status_cease), .io_ptw_status_wfi (_core_io_ptw_status_wfi), .io_ptw_status_isa (_core_io_ptw_status_isa), .io_ptw_status_dprv (_core_io_ptw_status_dprv), .io_ptw_status_dv (_core_io_ptw_status_dv), .io_ptw_status_prv (_core_io_ptw_status_prv), .io_ptw_status_v (_core_io_ptw_status_v), .io_ptw_status_sd (_core_io_ptw_status_sd), .io_ptw_status_mpv (_core_io_ptw_status_mpv), .io_ptw_status_gva (_core_io_ptw_status_gva), .io_ptw_status_tsr (_core_io_ptw_status_tsr), .io_ptw_status_tw (_core_io_ptw_status_tw), .io_ptw_status_tvm (_core_io_ptw_status_tvm), .io_ptw_status_mxr (_core_io_ptw_status_mxr), .io_ptw_status_sum (_core_io_ptw_status_sum), .io_ptw_status_mprv (_core_io_ptw_status_mprv), .io_ptw_status_fs (_core_io_ptw_status_fs), .io_ptw_status_mpp (_core_io_ptw_status_mpp), .io_ptw_status_spp (_core_io_ptw_status_spp), .io_ptw_status_mpie (_core_io_ptw_status_mpie), .io_ptw_status_spie (_core_io_ptw_status_spie), .io_ptw_status_mie (_core_io_ptw_status_mie), .io_ptw_status_sie (_core_io_ptw_status_sie), .io_ptw_hstatus_spvp (_core_io_ptw_hstatus_spvp), .io_ptw_hstatus_spv (_core_io_ptw_hstatus_spv), .io_ptw_hstatus_gva (_core_io_ptw_hstatus_gva), .io_ptw_gstatus_debug (_core_io_ptw_gstatus_debug), .io_ptw_gstatus_cease (_core_io_ptw_gstatus_cease), .io_ptw_gstatus_wfi (_core_io_ptw_gstatus_wfi), .io_ptw_gstatus_isa (_core_io_ptw_gstatus_isa), .io_ptw_gstatus_dprv (_core_io_ptw_gstatus_dprv), .io_ptw_gstatus_dv (_core_io_ptw_gstatus_dv), .io_ptw_gstatus_prv (_core_io_ptw_gstatus_prv), .io_ptw_gstatus_v (_core_io_ptw_gstatus_v), .io_ptw_gstatus_sd (_core_io_ptw_gstatus_sd), .io_ptw_gstatus_zero2 (_core_io_ptw_gstatus_zero2), .io_ptw_gstatus_mpv (_core_io_ptw_gstatus_mpv), .io_ptw_gstatus_gva (_core_io_ptw_gstatus_gva), .io_ptw_gstatus_mbe (_core_io_ptw_gstatus_mbe), .io_ptw_gstatus_sbe (_core_io_ptw_gstatus_sbe), .io_ptw_gstatus_sxl (_core_io_ptw_gstatus_sxl), .io_ptw_gstatus_zero1 (_core_io_ptw_gstatus_zero1), .io_ptw_gstatus_tsr (_core_io_ptw_gstatus_tsr), .io_ptw_gstatus_tw (_core_io_ptw_gstatus_tw), .io_ptw_gstatus_tvm (_core_io_ptw_gstatus_tvm), .io_ptw_gstatus_mxr (_core_io_ptw_gstatus_mxr), .io_ptw_gstatus_sum (_core_io_ptw_gstatus_sum), .io_ptw_gstatus_mprv (_core_io_ptw_gstatus_mprv), .io_ptw_gstatus_fs (_core_io_ptw_gstatus_fs), .io_ptw_gstatus_mpp (_core_io_ptw_gstatus_mpp), .io_ptw_gstatus_vs (_core_io_ptw_gstatus_vs), .io_ptw_gstatus_spp (_core_io_ptw_gstatus_spp), .io_ptw_gstatus_mpie (_core_io_ptw_gstatus_mpie), .io_ptw_gstatus_ube (_core_io_ptw_gstatus_ube), .io_ptw_gstatus_spie (_core_io_ptw_gstatus_spie), .io_ptw_gstatus_upie (_core_io_ptw_gstatus_upie), .io_ptw_gstatus_mie (_core_io_ptw_gstatus_mie), .io_ptw_gstatus_hie (_core_io_ptw_gstatus_hie), .io_ptw_gstatus_sie (_core_io_ptw_gstatus_sie), .io_ptw_gstatus_uie (_core_io_ptw_gstatus_uie), .io_ptw_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), .io_ptw_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), .io_ptw_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), .io_ptw_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), .io_ptw_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), .io_ptw_pmp_0_addr (_core_io_ptw_pmp_0_addr), .io_ptw_pmp_0_mask (_core_io_ptw_pmp_0_mask), .io_ptw_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), .io_ptw_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), .io_ptw_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), .io_ptw_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), .io_ptw_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), .io_ptw_pmp_1_addr (_core_io_ptw_pmp_1_addr), .io_ptw_pmp_1_mask (_core_io_ptw_pmp_1_mask), .io_ptw_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), .io_ptw_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), .io_ptw_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), .io_ptw_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), .io_ptw_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), .io_ptw_pmp_2_addr (_core_io_ptw_pmp_2_addr), .io_ptw_pmp_2_mask (_core_io_ptw_pmp_2_mask), .io_ptw_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), .io_ptw_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), .io_ptw_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), .io_ptw_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), .io_ptw_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), .io_ptw_pmp_3_addr (_core_io_ptw_pmp_3_addr), .io_ptw_pmp_3_mask (_core_io_ptw_pmp_3_mask), .io_ptw_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), .io_ptw_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), .io_ptw_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), .io_ptw_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), .io_ptw_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), .io_ptw_pmp_4_addr (_core_io_ptw_pmp_4_addr), .io_ptw_pmp_4_mask (_core_io_ptw_pmp_4_mask), .io_ptw_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), .io_ptw_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), .io_ptw_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), .io_ptw_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), .io_ptw_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), .io_ptw_pmp_5_addr (_core_io_ptw_pmp_5_addr), .io_ptw_pmp_5_mask (_core_io_ptw_pmp_5_mask), .io_ptw_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), .io_ptw_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), .io_ptw_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), .io_ptw_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), .io_ptw_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), .io_ptw_pmp_6_addr (_core_io_ptw_pmp_6_addr), .io_ptw_pmp_6_mask (_core_io_ptw_pmp_6_mask), .io_ptw_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), .io_ptw_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), .io_ptw_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), .io_ptw_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), .io_ptw_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), .io_ptw_pmp_7_addr (_core_io_ptw_pmp_7_addr), .io_ptw_pmp_7_mask (_core_io_ptw_pmp_7_mask), .io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[PTW.scala:802:19] .io_ptw_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), .io_ptw_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), .io_ptw_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), .io_ptw_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), .io_ptw_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), .io_ptw_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), .io_ptw_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), .io_ptw_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), .io_ptw_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), .io_ptw_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), .io_ptw_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), .io_ptw_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), .io_ptw_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), .io_ptw_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), .io_ptw_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), .io_ptw_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), .io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled), // @[PTW.scala:802:19] .io_fpu_hartid (_core_io_fpu_hartid), .io_fpu_time (_core_io_fpu_time), .io_fpu_inst (_core_io_fpu_inst), .io_fpu_fromint_data (_core_io_fpu_fromint_data), .io_fpu_fcsr_rm (_core_io_fpu_fcsr_rm), .io_fpu_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), // @[RocketTile.scala:242:62] .io_fpu_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), // @[RocketTile.scala:242:62] .io_fpu_store_data (_fpuOpt_io_store_data), // @[RocketTile.scala:242:62] .io_fpu_toint_data (_fpuOpt_io_toint_data), // @[RocketTile.scala:242:62] .io_fpu_ll_resp_val (_core_io_fpu_ll_resp_val), .io_fpu_ll_resp_type (_core_io_fpu_ll_resp_type), .io_fpu_ll_resp_tag (_core_io_fpu_ll_resp_tag), .io_fpu_ll_resp_data (_core_io_fpu_ll_resp_data), .io_fpu_valid (_core_io_fpu_valid), .io_fpu_fcsr_rdy (_fpuOpt_io_fcsr_rdy), // @[RocketTile.scala:242:62] .io_fpu_nack_mem (_fpuOpt_io_nack_mem), // @[RocketTile.scala:242:62] .io_fpu_illegal_rm (_fpuOpt_io_illegal_rm), // @[RocketTile.scala:242:62] .io_fpu_killx (_core_io_fpu_killx), .io_fpu_killm (_core_io_fpu_killm), .io_fpu_dec_ldst (_fpuOpt_io_dec_ldst), // @[RocketTile.scala:242:62] .io_fpu_dec_wen (_fpuOpt_io_dec_wen), // @[RocketTile.scala:242:62] .io_fpu_dec_ren1 (_fpuOpt_io_dec_ren1), // @[RocketTile.scala:242:62] .io_fpu_dec_ren2 (_fpuOpt_io_dec_ren2), // @[RocketTile.scala:242:62] .io_fpu_dec_ren3 (_fpuOpt_io_dec_ren3), // @[RocketTile.scala:242:62] .io_fpu_dec_swap12 (_fpuOpt_io_dec_swap12), // @[RocketTile.scala:242:62] .io_fpu_dec_swap23 (_fpuOpt_io_dec_swap23), // @[RocketTile.scala:242:62] .io_fpu_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), // @[RocketTile.scala:242:62] .io_fpu_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), // @[RocketTile.scala:242:62] .io_fpu_dec_fromint (_fpuOpt_io_dec_fromint), // @[RocketTile.scala:242:62] .io_fpu_dec_toint (_fpuOpt_io_dec_toint), // @[RocketTile.scala:242:62] .io_fpu_dec_fastpipe (_fpuOpt_io_dec_fastpipe), // @[RocketTile.scala:242:62] .io_fpu_dec_fma (_fpuOpt_io_dec_fma), // @[RocketTile.scala:242:62] .io_fpu_dec_div (_fpuOpt_io_dec_div), // @[RocketTile.scala:242:62] .io_fpu_dec_sqrt (_fpuOpt_io_dec_sqrt), // @[RocketTile.scala:242:62] .io_fpu_dec_wflags (_fpuOpt_io_dec_wflags), // @[RocketTile.scala:242:62] .io_fpu_dec_vec (_fpuOpt_io_dec_vec), // @[RocketTile.scala:242:62] .io_fpu_sboard_set (_fpuOpt_io_sboard_set), // @[RocketTile.scala:242:62] .io_fpu_sboard_clr (_fpuOpt_io_sboard_clr), // @[RocketTile.scala:242:62] .io_fpu_sboard_clra (_fpuOpt_io_sboard_clra), // @[RocketTile.scala:242:62] .io_fpu_keep_clock_enabled (_core_io_fpu_keep_clock_enabled), .io_trace_insns_0_valid (traceSourceNodeOut_insns_0_valid), .io_trace_insns_0_iaddr (traceSourceNodeOut_insns_0_iaddr), .io_trace_insns_0_insn (traceSourceNodeOut_insns_0_insn), .io_trace_insns_0_priv (traceSourceNodeOut_insns_0_priv), .io_trace_insns_0_exception (traceSourceNodeOut_insns_0_exception), .io_trace_insns_0_interrupt (traceSourceNodeOut_insns_0_interrupt), .io_trace_insns_0_cause (traceSourceNodeOut_insns_0_cause), .io_trace_insns_0_tval (traceSourceNodeOut_insns_0_tval), .io_trace_time (traceSourceNodeOut_time), .io_bpwatch_0_valid_0 (bpwatchSourceNodeOut_0_valid_0), .io_bpwatch_0_action (bpwatchSourceNodeOut_0_action), .io_wfi (_core_io_wfi) ); // @[RocketTile.scala:147:20] assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_b_ready = auto_buffer_out_b_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_valid = auto_buffer_out_c_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_opcode = auto_buffer_out_c_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_param = auto_buffer_out_c_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_size = auto_buffer_out_c_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_source = auto_buffer_out_c_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_address = auto_buffer_out_c_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_data = auto_buffer_out_c_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_e_valid = auto_buffer_out_e_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_e_bits_sink = auto_buffer_out_e_bits_sink_0; // @[RocketTile.scala:141:7] assign auto_wfi_out_0 = auto_wfi_out_0_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_valid = auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_iaddr = auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_insn = auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_priv = auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_exception = auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_interrupt = auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_cause = auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_tval = auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_time = auto_trace_source_out_time_0; // @[RocketTile.scala:141:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_233( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_13( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1502 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1502; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1502; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1575 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1575; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [4:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1428 = _T_1502 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1428 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1428 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1428 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1428 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1428 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1474 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1474 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1443 = _T_1575 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1443 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1443 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1443 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1546 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1546 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1528 = _T_1575 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1528 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1528 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1528 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_274( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_18 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File IngressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class IngressUnit( ingressNodeId: Int, cParam: IngressChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean, ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits))) } val io = IO(new IngressUnitIO) val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2, flow=combineRCVA)) assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR)) route_buffer.io.enq.bits.head := io.in.bits.head route_buffer.io.enq.bits.tail := io.in.bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { route_buffer.io.enq.bits.flow := DontCare } else { route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U route_buffer.io.enq.bits.flow.egress_node := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNode.U) ) route_buffer.io.enq.bits.flow.egress_node_id := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNodeId.U) ) } route_buffer.io.enq.bits.payload := io.in.bits.payload route_buffer.io.enq.bits.virt_channel_id := DontCare io.router_req.bits.src_virt_id := 0.U io.router_req.bits.flow := route_buffer.io.enq.bits.flow val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U route_buffer.io.enq.valid := io.in.valid && ( io.router_req.ready \|\| !io.in.bits.head \|\| at_dest) io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest io.in.ready := route_buffer.io.enq.ready && ( io.router_req.ready \|\| !io.in.bits.head \|\| at_dest) route_q.io.enq.valid := io.router_req.fire route_q.io.enq.bits := io.router_resp when (io.in.fire && io.in.bits.head && at_dest) { route_q.io.enq.valid := true.B route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (egressParams(o).egressId.U === io.in.bits.egress_id) { route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B } } } assert(!(route_q.io.enq.valid && !route_q.io.enq.ready)) val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams), 1, pipe=true)) vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow io.vcalloc_req.bits.in_vc := 0.U val head = route_buffer.io.deq.bits.head val tail = route_buffer.io.deq.bits.tail vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid && (route_q.io.deq.valid \|\| !head) && (io.vcalloc_req.ready \|\| !head) ) io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid && head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready) route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready && (route_q.io.deq.valid \|\| !head) && (io.vcalloc_req.ready \|\| !head) && (vcalloc_q.io.enq.ready \|\| !head)) route_q.io.deq.ready := (route_buffer.io.deq.fire && tail) vcalloc_q.io.enq.valid := io.vcalloc_req.fire vcalloc_q.io.enq.bits := io.vcalloc_resp assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready)) io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire val out_bundle = if (combineSAST) { Wire(Valid(new SwitchBundle(outParams, egressParams))) } else { Reg(Valid(new SwitchBundle(outParams, egressParams))) } io.out(0) := out_bundle out_bundle.valid := vcalloc_buffer.io.deq.fire out_bundle.bits.flit := vcalloc_buffer.io.deq.bits out_bundle.bits.flit.virt_channel_id := 0.U val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_\|\|_)).toSeq out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh, vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq) io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready // TODO: We should not generate input/ingress/output/egress units for untraversable channels if (!cParam.traversable) { io.in.ready := false.B io.router_req.valid := false.B io.router_req.bits := DontCare io.vcalloc_req.valid := false.B io.vcalloc_req.bits := DontCare io.salloc_req.foreach(_.valid := false.B) io.salloc_req.foreach(_.bits := DontCare) io.out.foreach(_.valid := false.B) io.out.foreach(_.bits := DontCare) } }	module IngressUnit_9( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_7_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_6_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_5_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_7_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_6_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_5_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_4_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_10, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_11, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_12, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_13, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_14, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_15, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_16, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_17, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_18, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_19, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_20, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_21, // @[IngressUnit.scala:24:14] input io_out_credit_available_7_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_6_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_5_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_4_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_8, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_10, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_11, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_12, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_13, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_14, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_15, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_16, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_17, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_18, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_19, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_20, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_21, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_7_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_6_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_5_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [5:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [5:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [5:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _GEN; // @[Decoupled.scala:51:35] wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_7_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_6_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_5_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_4_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_10; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_11; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_12; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_13; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_14; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_15; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_16; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_17; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_18; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_19; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_20; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_21; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [5:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [5:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [5:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [5:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 6'h27; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 6'h2A; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 6'h2D; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 6'h30; // @[IngressUnit.scala:30:72] wire [2:0] _GEN_0 = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_1, 1'h0} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 3'h6 : 3'h0); // @[Mux.scala:30:73] wire [2:0] _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = {1'h0, {2{_route_buffer_io_enq_bits_flow_egress_node_id_T}}} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h5 : 3'h0); // @[Mux.scala:30:73] wire [2:0] _GEN_1 = {_route_buffer_io_enq_bits_flow_egress_node_id_T_2, _GEN_0[2:1]}; // @[Mux.scala:30:73] assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _GEN_1 == 3'h1; // @[Decoupled.scala:51:35] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _GEN_1 != 3'h1; // @[Decoupled.scala:51:35] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLBuffer_a32d64s3k3z4c_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire nodeOut_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire [63:0] auto_out_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_source = 3'h0; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_source = 3'h0; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_40 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s3k3z4c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s3k3z4c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d64s3k3z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d64s3k3z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d64s3k3z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DivSqrtRecFN_small.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2017 SiFive, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of SiFive nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ /* s = sigWidth c_i = newBit Division: width of a is (s+2) Normal ------ (qi + ci * 2^(-i))b <= a q0 = 0 r0 = a q(i+1) = qi + ci2^(-i) ri = a - qib r(i+1) = a - q(i+1)b = a - qib - ci2^(-i)b r(i+1) = ri - ci2^(-i)b ci = ri >= 2^(-i)b summary_i = ri != 0 i = 0 to s+1 (s+1)th bit plus summary_(i+1) gives enough information for rounding If (a < b), then we need to calculate (s+2)th bit and summary_(i+1) because we need s bits ignoring the leading zero. (This is skipCycle2 part of Hauser's code.) Hauser ------ sig_i = qi rem_i = 2^(i-2)ri cycle_i = s+3-i sig_0 = 0 rem_0 = a/4 cycle_0 = s+3 bit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits) sig(i+1) = sig(i) + cibit_i rem(i+1) = 2rem_i - cib/2 ci = 2rem_i >= b/2 bit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits) cycle(i+1) = cycle_i-1 summary_1 = a <> b summary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0 Proof: 2^ir(i+1) = 2^iri - cib. Qed ci = 2^iri >= b. Qed summary(i+1) = if ci then rem(i+1) else summary_i, i <> 0 Now, note that all of ck's cannot be 0, since that means a is 0. So when you traverse through a chain of 0 ck's, from the end, eventually, you reach a non-zero cj. That is exactly the value of ri as the reminder remains the same. When all ck's are 0 except c0 (which must be 1) then summary_1 is set correctly according to r1 = a-b != 0. So summary(i+1) is always set correctly according to r(i+1) Square root: width of a is (s+1) Normal ------ (xi + ci2^(-i))^2 <= a xi^2 + ci2^(-i)(2xi+ci2^(-i)) <= a x0 = 0 x(i+1) = xi + ci2^(-i) ri = a - xi^2 r(i+1) = a - x(i+1)^2 = a - (xi^2 + ci2^(-i)(2xi+ci2^(-i))) = ri - ci2^(-i)(2xi+ci2^(-i)) = ri - ci2^(-i)(2xi+2^(-i)) // ci is always 0 or 1 ci = ri >= 2^(-i)(2xi + 2^(-i)) summary_i = ri != 0 i = 0 to s+1 For odd expression, do 2 steps initially. (s+1)th bit plus summary_(i+1) gives enough information for rounding. Hauser ------ sig_i = xi rem_i = ri2^(i-1) cycle_i = s+2-i bit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation) sig_0 = 0 rem_0 = a/2 cycle_0 = s+2 bit_0 = 1 (= 2^s in terms of bit representation) sig(i+1) = sig_i + ci * bit_i rem(i+1) = 2rem_i - ci(2sig_i + bit_i) ci = 2sig_i + bit_i <= 2rem_i bit_i = 2^(cycle_i-2) (in terms of bit representation) cycle(i+1) = cycle_i-1 summary_1 = a - (2^s) (in terms of bit representation) summary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0 Proof: ci = 2sig_i + bit_i <= 2rem_i ci = 2xi + 2^(-i) <= ri2^i. Qed sig(i+1) = sig_i + ci * bit_i x(i+1) = xi + ci2^(-i). Qed rem(i+1) = 2rem_i - ci(2sig_i + bit_i) r(i+1)2^i = ri2^i - ci(2xi + 2^(-i)) r(i+1) = ri - ci2^(-i)(2xi + 2^(-i)). Qed Same argument as before for summary. ------------------------------ Note that all registers are updated normally until cycle == 2. At cycle == 2, rem is not updated, but all other registers are updated normally. But, cycle == 1 does not read rem to calculate anything (note that final summary is calculated using the values at cycle = 2). / package hardfloat import chisel3._ import chisel3.util._ import consts._ /---------------------------------------------------------------------------- \| Computes a division or square root for floating-point in recoded form. \| Multiple clock cycles are needed for each division or square-root operation, \| except possibly in special cases. ----------------------------------------------------------------------------/ class DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int) extends Module { override def desiredName = s"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { /-------------------------------------------------------------------- --------------------------------------------------------------------/ val inReady = Output(Bool()) val inValid = Input(Bool()) val sqrtOp = Input(Bool()) val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val roundingMode = Input(UInt(3.W)) /-------------------------------------------------------------------- --------------------------------------------------------------------/ val rawOutValid_div = Output(Bool()) val rawOutValid_sqrt = Output(Bool()) val roundingModeOut = Output(UInt(3.W)) val invalidExc = Output(Bool()) val infiniteExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W)) val inReady = RegInit(true.B) // <-> (cycleNum <= 1) val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1) val sqrtOp_Z = Reg(Bool()) val majorExc_Z = Reg(Bool()) //*** REDUCE 3 BITS TO 2-BIT CODE: val isNaN_Z = Reg(Bool()) val isInf_Z = Reg(Bool()) val isZero_Z = Reg(Bool()) val sign_Z = Reg(Bool()) val sExp_Z = Reg(SInt((expWidth + 2).W)) val fractB_Z = Reg(UInt(sigWidth.W)) val roundingMode_Z = Reg(UInt(3.W)) /------------------------------------------------------------------------ \| (The most-significant and least-significant bits of 'rem_Z' are needed \| only for square roots.) ------------------------------------------------------------------------/ val rem_Z = Reg(UInt((sigWidth + 2).W)) val notZeroRem_Z = Reg(Bool()) val sigX_Z = Reg(UInt((sigWidth + 2).W)) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val rawA_S = io.a val rawB_S = io.b //* IMPROVE THESE: val notSigNaNIn_invalidExc_S_div = (rawA_S.isZero && rawB_S.isZero) \|\| (rawA_S.isInf && rawB_S.isInf) val notSigNaNIn_invalidExc_S_sqrt = ! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign val majorExc_S = Mux(io.sqrtOp, isSigNaNRawFloat(rawA_S) \|\| notSigNaNIn_invalidExc_S_sqrt, isSigNaNRawFloat(rawA_S) \|\| isSigNaNRawFloat(rawB_S) \|\| notSigNaNIn_invalidExc_S_div \|\| (! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero) ) val isNaN_S = Mux(io.sqrtOp, rawA_S.isNaN \|\| notSigNaNIn_invalidExc_S_sqrt, rawA_S.isNaN \|\| rawB_S.isNaN \|\| notSigNaNIn_invalidExc_S_div ) val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf \|\| rawB_S.isZero) val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero \|\| rawB_S.isInf) val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign) val specialCaseA_S = rawA_S.isNaN \|\| rawA_S.isInf \|\| rawA_S.isZero val specialCaseB_S = rawB_S.isNaN \|\| rawB_S.isInf \|\| rawB_S.isZero val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) val sExpQuot_S_div = rawA_S.sExp +& Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt //* IS THIS OPTIMAL?: val sSatExpQuot_S_div = Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div), 6.U, sExpQuot_S_div(expWidth + 1, expWidth - 2) ), sExpQuot_S_div(expWidth - 3, 0) ).asSInt val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0) val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val idle = cycleNum === 0.U val entering = inReady && io.inValid val entering_normalCase = entering && normalCase_S val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B when (! idle \|\| entering) { def computeCycleNum(f: UInt => UInt): UInt = { Mux(entering & ! normalCase_S, f(1.U), 0.U) \| Mux(entering_normalCase, Mux(io.sqrtOp, Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)), f((sigWidth + 2).U) ), 0.U ) \| Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) \| Mux(skipCycle2, f(1.U), 0.U) } inReady := computeCycleNum(_ <= 1.U).asBool rawOutValid := computeCycleNum(_ === 1.U).asBool cycleNum := computeCycleNum(x => x) } io.inReady := inReady /------------------------------------------------------------------------ ------------------------------------------------------------------------/ when (entering) { sqrtOp_Z := io.sqrtOp majorExc_Z := majorExc_S isNaN_Z := isNaN_S isInf_Z := isInf_S isZero_Z := isZero_S sign_Z := sign_S sExp_Z := Mux(io.sqrtOp, (rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S, sSatExpQuot_S_div ) roundingMode_Z := io.roundingMode } when (entering \|\| ! inReady && sqrtOp_Z) { fractB_Z := Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) \| Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) \| Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) \| Mux(! inReady /* sqrtOp_Z / && processTwoBits, fractB_Z>>2, 0.U) \| Mux(! inReady / sqrtOp_Z / && ! processTwoBits, fractB_Z>>1, 0.U) } /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val rem = Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) \| Mux(inReady && oddSqrt_S, Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U, rawA_S.sig(sigWidth - 3, 0)<<3 ), 0.U ) \| Mux(! inReady, rem_Z<<1, 0.U) val bitMask = (1.U<<cycleNum)>>2 val trialTerm = Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) \| Mux(inReady && evenSqrt_S, (BigInt(1)<<sigWidth).U, 0.U) \| Mux(inReady && oddSqrt_S, (BigInt(5)<<(sigWidth - 1)).U, 0.U) \| Mux(! inReady, fractB_Z, 0.U) \| Mux(! inReady && ! sqrtOp_Z, 1.U << sigWidth, 0.U) \| Mux(! inReady && sqrtOp_Z, sigX_Z<<1, 0.U) val trialRem = rem.zext -& trialTerm.zext val newBit = (0.S <= trialRem) val nextRem_Z = Mux(newBit, trialRem.asUInt, rem)(sigWidth + 1, 0) val rem2 = nextRem_Z<<1 val trialTerm2_newBit0 = Mux(sqrtOp_Z, fractB_Z>>1 \| sigX_Z<<1, fractB_Z \| (1.U << sigWidth)) val trialTerm2_newBit1 = trialTerm2_newBit0 \| Mux(sqrtOp_Z, fractB_Z<<1, 0.U) val trialRem2 = Mux(newBit, (trialRem<<1) - trialTerm2_newBit1.zext, (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) val newBit2 = (0.S <= trialRem2) val nextNotZeroRem_Z = Mux(inReady \|\| newBit, trialRem =/= 0.S, notZeroRem_Z) val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z) processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) \|\| processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) \|\| !(processTwoBits && newBit2) && nextNotZeroRem_Z val nextRem_Z_2 = Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) \| Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) \| Mux(!processTwoBits, nextRem_Z, 0.U) when (entering \|\| ! inReady) { notZeroRem_Z := nextNotZeroRem_Z_2 rem_Z := nextRem_Z_2 sigX_Z := Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) \| Mux(inReady && io.sqrtOp, (BigInt(1)<<sigWidth).U, 0.U) \| Mux(inReady && oddSqrt_S, newBit<<(sigWidth - 1), 0.U) \| Mux(! inReady, sigX_Z, 0.U) \| Mux(! inReady && newBit, bitMask, 0.U) \| Mux(processTwoBits && newBit2, bitMask>>1, 0.U) } /------------------------------------------------------------------------ ------------------------------------------------------------------------/ io.rawOutValid_div := rawOutValid && ! sqrtOp_Z io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z io.roundingModeOut := roundingMode_Z io.invalidExc := majorExc_Z && isNaN_Z io.infiniteExc := majorExc_Z && ! isNaN_Z io.rawOut.isNaN := isNaN_Z io.rawOut.isInf := isInf_Z io.rawOut.isZero := isZero_Z io.rawOut.sign := sign_Z io.rawOut.sExp := sExp_Z io.rawOut.sig := sigX_Z<<1 \| notZeroRem_Z } /---------------------------------------------------------------------------- ----------------------------------------------------------------------------/ class DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int) extends Module { override def desiredName = s"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { /-------------------------------------------------------------------- --------------------------------------------------------------------/ val inReady = Output(Bool()) val inValid = Input(Bool()) val sqrtOp = Input(Bool()) val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) /-------------------------------------------------------------------- --------------------------------------------------------------------/ val rawOutValid_div = Output(Bool()) val rawOutValid_sqrt = Output(Bool()) val roundingModeOut = Output(UInt(3.W)) val invalidExc = Output(Bool()) val infiniteExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val divSqrtRawFN = Module(new DivSqrtRawFN_small(expWidth, sigWidth, options)) io.inReady := divSqrtRawFN.io.inReady divSqrtRawFN.io.inValid := io.inValid divSqrtRawFN.io.sqrtOp := io.sqrtOp divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) divSqrtRawFN.io.roundingMode := io.roundingMode io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt io.roundingModeOut := divSqrtRawFN.io.roundingModeOut io.invalidExc := divSqrtRawFN.io.invalidExc io.infiniteExc := divSqrtRawFN.io.infiniteExc io.rawOut := divSqrtRawFN.io.rawOut } /---------------------------------------------------------------------------- ----------------------------------------------------------------------------/ class DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int) extends Module { override def desiredName = s"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { /-------------------------------------------------------------------- --------------------------------------------------------------------/ val inReady = Output(Bool()) val inValid = Input(Bool()) val sqrtOp = Input(Bool()) val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) /-------------------------------------------------------------------- --------------------------------------------------------------------*/ val outValid_div = Output(Bool()) val outValid_sqrt = Output(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val divSqrtRecFNToRaw = Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options)) io.inReady := divSqrtRecFNToRaw.io.inReady divSqrtRecFNToRaw.io.inValid := io.inValid divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp divSqrtRecFNToRaw.io.a := io.a divSqrtRecFNToRaw.io.b := io.b divSqrtRecFNToRaw.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module DivSqrtRawFN_small_e8_s24_5( // @[DivSqrtRecFN_small.scala:199:5] input clock, // @[DivSqrtRecFN_small.scala:199:5] input reset, // @[DivSqrtRecFN_small.scala:199:5] output io_inReady, // @[DivSqrtRecFN_small.scala:203:16] input io_inValid, // @[DivSqrtRecFN_small.scala:203:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:203:16] input io_a_isNaN, // @[DivSqrtRecFN_small.scala:203:16] input io_a_isInf, // @[DivSqrtRecFN_small.scala:203:16] input io_a_isZero, // @[DivSqrtRecFN_small.scala:203:16] input io_a_sign, // @[DivSqrtRecFN_small.scala:203:16] input [9:0] io_a_sExp, // @[DivSqrtRecFN_small.scala:203:16] input [24:0] io_a_sig, // @[DivSqrtRecFN_small.scala:203:16] input io_b_isNaN, // @[DivSqrtRecFN_small.scala:203:16] input io_b_isInf, // @[DivSqrtRecFN_small.scala:203:16] input io_b_isZero, // @[DivSqrtRecFN_small.scala:203:16] input io_b_sign, // @[DivSqrtRecFN_small.scala:203:16] input [9:0] io_b_sExp, // @[DivSqrtRecFN_small.scala:203:16] input [24:0] io_b_sig, // @[DivSqrtRecFN_small.scala:203:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:203:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:203:16] output io_invalidExc, // @[DivSqrtRecFN_small.scala:203:16] output io_infiniteExc, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:203:16] output [9:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:203:16] output [26:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:203:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:199:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_isNaN_0 = io_a_isNaN; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_isInf_0 = io_a_isInf; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_isZero_0 = io_a_isZero; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_sign_0 = io_a_sign; // @[DivSqrtRecFN_small.scala:199:5] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[DivSqrtRecFN_small.scala:199:5] wire [24:0] io_a_sig_0 = io_a_sig; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_isNaN_0 = io_b_isNaN; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_isInf_0 = io_b_isInf; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_isZero_0 = io_b_isZero; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_sign_0 = io_b_sign; // @[DivSqrtRecFN_small.scala:199:5] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[DivSqrtRecFN_small.scala:199:5] wire [24:0] io_b_sig_0 = io_b_sig; // @[DivSqrtRecFN_small.scala:199:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:199:5] wire [1:0] _inReady_T_15 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61] wire [1:0] _rawOutValid_T_15 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61] wire [1:0] _cycleNum_T_11 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61] wire [21:0] _fractB_Z_T_19 = 22'h0; // @[DivSqrtRecFN_small.scala:345:16] wire [24:0] _trialTerm_T_16 = 25'h1000000; // @[DivSqrtRecFN_small.scala:366:42] wire [24:0] _trialTerm2_newBit0_T_3 = 25'h1000000; // @[DivSqrtRecFN_small.scala:373:85] wire [25:0] _nextRem_Z_2_T_3 = 26'h0; // @[DivSqrtRecFN_small.scala:386:12] wire [25:0] _nextRem_Z_2_T_7 = 26'h0; // @[DivSqrtRecFN_small.scala:387:12] wire [25:0] _nextRem_Z_2_T_8 = 26'h0; // @[DivSqrtRecFN_small.scala:386:81] wire _inReady_T_2 = 1'h1; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:317:38] wire _rawOutValid_T_2 = 1'h1; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:318:42] wire _fractB_Z_T_22 = 1'h1; // @[DivSqrtRecFN_small.scala:346:45] wire _nextNotZeroRem_Z_2_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:384:9] wire _nextRem_Z_2_T_9 = 1'h1; // @[DivSqrtRecFN_small.scala:388:13] wire processTwoBits = 1'h0; // @[DivSqrtRecFN_small.scala:300:42] wire _inReady_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_6 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:308:24] wire _inReady_T_8 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:307:20] wire _inReady_T_10 = 1'h0; // @[DivSqrtRecFN_small.scala:306:16] wire _rawOutValid_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_6 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:308:24] wire _rawOutValid_T_8 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:307:20] wire _rawOutValid_T_10 = 1'h0; // @[DivSqrtRecFN_small.scala:306:16] wire _fractB_Z_T_17 = 1'h0; // @[DivSqrtRecFN_small.scala:345:42] wire _nextNotZeroRem_Z_2_T = 1'h0; // @[DivSqrtRecFN_small.scala:382:24] wire _nextNotZeroRem_Z_2_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:382:34] wire _nextNotZeroRem_Z_2_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:383:24] wire _nextNotZeroRem_Z_2_T_18 = 1'h0; // @[DivSqrtRecFN_small.scala:383:35] wire _nextNotZeroRem_Z_2_T_19 = 1'h0; // @[DivSqrtRecFN_small.scala:382:85] wire _nextNotZeroRem_Z_2_T_20 = 1'h0; // @[DivSqrtRecFN_small.scala:384:26] wire _nextRem_Z_2_T = 1'h0; // @[DivSqrtRecFN_small.scala:386:28] wire _nextRem_Z_2_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:387:28] wire _sigX_Z_T_18 = 1'h0; // @[DivSqrtRecFN_small.scala:399:32] wire [28:0] _sigX_Z_T_20 = 29'h0; // @[DivSqrtRecFN_small.scala:399:16] wire _io_rawOutValid_div_T_1; // @[DivSqrtRecFN_small.scala:404:40] wire _io_rawOutValid_sqrt_T; // @[DivSqrtRecFN_small.scala:405:40] wire _io_invalidExc_T; // @[DivSqrtRecFN_small.scala:407:36] wire _io_infiniteExc_T_1; // @[DivSqrtRecFN_small.scala:408:36] wire [26:0] _io_rawOut_sig_T_1; // @[DivSqrtRecFN_small.scala:414:35] wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:199:5] wire [9:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:199:5] wire [26:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:199:5] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:199:5] reg [4:0] cycleNum; // @[DivSqrtRecFN_small.scala:224:33] reg inReady; // @[DivSqrtRecFN_small.scala:225:33] assign io_inReady_0 = inReady; // @[DivSqrtRecFN_small.scala:199:5, :225:33] reg rawOutValid; // @[DivSqrtRecFN_small.scala:226:33] reg sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29] reg majorExc_Z; // @[DivSqrtRecFN_small.scala:229:29] reg isNaN_Z; // @[DivSqrtRecFN_small.scala:231:29] assign io_rawOut_isNaN_0 = isNaN_Z; // @[DivSqrtRecFN_small.scala:199:5, :231:29] reg isInf_Z; // @[DivSqrtRecFN_small.scala:232:29] assign io_rawOut_isInf_0 = isInf_Z; // @[DivSqrtRecFN_small.scala:199:5, :232:29] reg isZero_Z; // @[DivSqrtRecFN_small.scala:233:29] assign io_rawOut_isZero_0 = isZero_Z; // @[DivSqrtRecFN_small.scala:199:5, :233:29] reg sign_Z; // @[DivSqrtRecFN_small.scala:234:29] assign io_rawOut_sign_0 = sign_Z; // @[DivSqrtRecFN_small.scala:199:5, :234:29] reg [9:0] sExp_Z; // @[DivSqrtRecFN_small.scala:235:29] assign io_rawOut_sExp_0 = sExp_Z; // @[DivSqrtRecFN_small.scala:199:5, :235:29] reg [23:0] fractB_Z; // @[DivSqrtRecFN_small.scala:236:29] reg [2:0] roundingMode_Z; // @[DivSqrtRecFN_small.scala:237:29] assign io_roundingModeOut_0 = roundingMode_Z; // @[DivSqrtRecFN_small.scala:199:5, :237:29] reg [25:0] rem_Z; // @[DivSqrtRecFN_small.scala:243:29] reg notZeroRem_Z; // @[DivSqrtRecFN_small.scala:244:29] reg [25:0] sigX_Z; // @[DivSqrtRecFN_small.scala:245:29] wire _notSigNaNIn_invalidExc_S_div_T = io_a_isZero_0 & io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :254:24] wire _notSigNaNIn_invalidExc_S_div_T_1 = io_a_isInf_0 & io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :254:59] wire notSigNaNIn_invalidExc_S_div = _notSigNaNIn_invalidExc_S_div_T \| _notSigNaNIn_invalidExc_S_div_T_1; // @[DivSqrtRecFN_small.scala:254:{24,42,59}] wire _notSigNaNIn_invalidExc_S_sqrt_T = ~io_a_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :256:9] wire _notSigNaNIn_invalidExc_S_sqrt_T_1 = ~io_a_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :256:27] wire _notSigNaNIn_invalidExc_S_sqrt_T_2 = _notSigNaNIn_invalidExc_S_sqrt_T & _notSigNaNIn_invalidExc_S_sqrt_T_1; // @[DivSqrtRecFN_small.scala:256:{9,24,27}] wire notSigNaNIn_invalidExc_S_sqrt = _notSigNaNIn_invalidExc_S_sqrt_T_2 & io_a_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :256:{24,43}] wire _majorExc_S_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _majorExc_S_T_4 = io_a_sig_0[22]; // @[common.scala:82:56] wire _majorExc_S_T_1 = ~_majorExc_S_T; // @[common.scala:82:{49,56}] wire _majorExc_S_T_2 = io_a_isNaN_0 & _majorExc_S_T_1; // @[common.scala:82:{46,49}] wire _majorExc_S_T_3 = _majorExc_S_T_2 \| notSigNaNIn_invalidExc_S_sqrt; // @[common.scala:82:46] wire _majorExc_S_T_5 = ~_majorExc_S_T_4; // @[common.scala:82:{49,56}] wire _majorExc_S_T_6 = io_a_isNaN_0 & _majorExc_S_T_5; // @[common.scala:82:{46,49}] wire _majorExc_S_T_7 = io_b_sig_0[22]; // @[common.scala:82:56] wire _majorExc_S_T_8 = ~_majorExc_S_T_7; // @[common.scala:82:{49,56}] wire _majorExc_S_T_9 = io_b_isNaN_0 & _majorExc_S_T_8; // @[common.scala:82:{46,49}] wire _majorExc_S_T_10 = _majorExc_S_T_6 \| _majorExc_S_T_9; // @[common.scala:82:46] wire _majorExc_S_T_11 = _majorExc_S_T_10 \| notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecFN_small.scala:254:42, :260:{38,66}] wire _majorExc_S_T_12 = ~io_a_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :256:9, :262:18] wire _majorExc_S_T_13 = ~io_a_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :262:36] wire _majorExc_S_T_14 = _majorExc_S_T_12 & _majorExc_S_T_13; // @[DivSqrtRecFN_small.scala:262:{18,33,36}] wire _majorExc_S_T_15 = _majorExc_S_T_14 & io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :262:{33,51}] wire _majorExc_S_T_16 = _majorExc_S_T_11 \| _majorExc_S_T_15; // @[DivSqrtRecFN_small.scala:260:66, :261:46, :262:51] wire majorExc_S = io_sqrtOp_0 ? _majorExc_S_T_3 : _majorExc_S_T_16; // @[DivSqrtRecFN_small.scala:199:5, :258:12, :259:38, :261:46] wire _isNaN_S_T = io_a_isNaN_0 \| notSigNaNIn_invalidExc_S_sqrt; // @[DivSqrtRecFN_small.scala:199:5, :256:43, :266:26] wire _isNaN_S_T_1 = io_a_isNaN_0 \| io_b_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :267:26] wire _isNaN_S_T_2 = _isNaN_S_T_1 \| notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecFN_small.scala:254:42, :267:{26,42}] wire isNaN_S = io_sqrtOp_0 ? _isNaN_S_T : _isNaN_S_T_2; // @[DivSqrtRecFN_small.scala:199:5, :265:12, :266:26, :267:42] wire _isInf_S_T = io_a_isInf_0 \| io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :269:63] wire isInf_S = io_sqrtOp_0 ? io_a_isInf_0 : _isInf_S_T; // @[DivSqrtRecFN_small.scala:199:5, :269:{23,63}] wire _isZero_S_T = io_a_isZero_0 \| io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :270:64] wire isZero_S = io_sqrtOp_0 ? io_a_isZero_0 : _isZero_S_T; // @[DivSqrtRecFN_small.scala:199:5, :270:{23,64}] wire _sign_S_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33] wire _sign_S_T_1 = _sign_S_T & io_b_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :271:{33,45}] wire sign_S = io_a_sign_0 ^ _sign_S_T_1; // @[DivSqrtRecFN_small.scala:199:5, :271:{30,45}] wire _specialCaseA_S_T = io_a_isNaN_0 \| io_a_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :273:39] wire specialCaseA_S = _specialCaseA_S_T \| io_a_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :273:{39,55}] wire _specialCaseB_S_T = io_b_isNaN_0 \| io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :274:39] wire specialCaseB_S = _specialCaseB_S_T \| io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :274:{39,55}] wire _normalCase_S_div_T = ~specialCaseA_S; // @[DivSqrtRecFN_small.scala:273:55, :275:28] wire _normalCase_S_div_T_1 = ~specialCaseB_S; // @[DivSqrtRecFN_small.scala:274:55, :275:48] wire normalCase_S_div = _normalCase_S_div_T & _normalCase_S_div_T_1; // @[DivSqrtRecFN_small.scala:275:{28,45,48}] wire _normalCase_S_sqrt_T = ~specialCaseA_S; // @[DivSqrtRecFN_small.scala:273:55, :275:28, :276:29] wire _normalCase_S_sqrt_T_1 = ~io_a_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :276:49] wire normalCase_S_sqrt = _normalCase_S_sqrt_T & _normalCase_S_sqrt_T_1; // @[DivSqrtRecFN_small.scala:276:{29,46,49}] wire normalCase_S = io_sqrtOp_0 ? normalCase_S_sqrt : normalCase_S_div; // @[DivSqrtRecFN_small.scala:199:5, :275:45, :276:46, :277:27] wire _sExpQuot_S_div_T = io_b_sExp_0[8]; // @[DivSqrtRecFN_small.scala:199:5, :281:28] wire [7:0] _sExpQuot_S_div_T_1 = io_b_sExp_0[7:0]; // @[DivSqrtRecFN_small.scala:199:5, :281:52] wire [7:0] _sExpQuot_S_div_T_2 = ~_sExpQuot_S_div_T_1; // @[DivSqrtRecFN_small.scala:281:{40,52}] wire [8:0] _sExpQuot_S_div_T_3 = {_sExpQuot_S_div_T, _sExpQuot_S_div_T_2}; // @[DivSqrtRecFN_small.scala:281:{16,28,40}] wire [8:0] _sExpQuot_S_div_T_4 = _sExpQuot_S_div_T_3; // @[DivSqrtRecFN_small.scala:281:{16,71}] wire [10:0] sExpQuot_S_div = {io_a_sExp_0[9], io_a_sExp_0} + {{2{_sExpQuot_S_div_T_4[8]}}, _sExpQuot_S_div_T_4}; // @[DivSqrtRecFN_small.scala:199:5, :280:21, :281:71] wire _sSatExpQuot_S_div_T = $signed(sExpQuot_S_div) > 11'sh1BF; // @[DivSqrtRecFN_small.scala:280:21, :284:48] wire [3:0] _sSatExpQuot_S_div_T_1 = sExpQuot_S_div[9:6]; // @[DivSqrtRecFN_small.scala:280:21, :286:31] wire [3:0] _sSatExpQuot_S_div_T_2 = _sSatExpQuot_S_div_T ? 4'h6 : _sSatExpQuot_S_div_T_1; // @[DivSqrtRecFN_small.scala:284:{16,48}, :286:31] wire [5:0] _sSatExpQuot_S_div_T_3 = sExpQuot_S_div[5:0]; // @[DivSqrtRecFN_small.scala:280:21, :288:27] wire [9:0] _sSatExpQuot_S_div_T_4 = {_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3}; // @[DivSqrtRecFN_small.scala:284:{12,16}, :288:27] wire [9:0] sSatExpQuot_S_div = _sSatExpQuot_S_div_T_4; // @[DivSqrtRecFN_small.scala:284:12, :289:11] wire _evenSqrt_S_T = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48] wire _oddSqrt_S_T = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :292:48] wire _inReady_T_4 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36] wire _rawOutValid_T_4 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36] wire _cycleNum_T_3 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36] wire _fractB_Z_T_6 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :343:52] wire _fractB_Z_T_11 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :344:54] wire _evenSqrt_S_T_1 = ~_evenSqrt_S_T; // @[DivSqrtRecFN_small.scala:291:{35,48}] wire evenSqrt_S = io_sqrtOp_0 & _evenSqrt_S_T_1; // @[DivSqrtRecFN_small.scala:199:5, :291:{32,35}] wire oddSqrt_S = io_sqrtOp_0 & _oddSqrt_S_T; // @[DivSqrtRecFN_small.scala:199:5, :292:{32,48}] wire idle = cycleNum == 5'h0; // @[DivSqrtRecFN_small.scala:224:33, :296:25] wire entering = inReady & io_inValid_0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :297:28] wire entering_normalCase = entering & normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :297:28, :298:40] wire _processTwoBits_T = cycleNum > 5'h2; // @[DivSqrtRecFN_small.scala:224:33, :300:35] wire _skipCycle2_T = cycleNum == 5'h3; // @[DivSqrtRecFN_small.scala:224:33, :301:31] wire _skipCycle2_T_1 = sigX_Z[25]; // @[DivSqrtRecFN_small.scala:245:29, :301:48] wire _skipCycle2_T_2 = _skipCycle2_T & _skipCycle2_T_1; // @[DivSqrtRecFN_small.scala:301:{31,39,48}] wire skipCycle2 = _skipCycle2_T_2; // @[DivSqrtRecFN_small.scala:301:{39,63}] wire _inReady_T_22 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16] wire _rawOutValid_T_22 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16] wire _cycleNum_T_16 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16] wire _inReady_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28] wire _inReady_T_1 = entering & _inReady_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}] wire _inReady_T_3 = _inReady_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}] wire _inReady_T_11 = _inReady_T_3; // @[DivSqrtRecFN_small.scala:305:{16,57}] wire _inReady_T_12 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17] wire _inReady_T_13 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31] wire _inReady_T_14 = _inReady_T_12 & _inReady_T_13; // @[DivSqrtRecFN_small.scala:313:{17,28,31}] wire [5:0] _GEN = {1'h0, cycleNum} - 6'h1; // @[DivSqrtRecFN_small.scala:224:33, :313:56] wire [5:0] _inReady_T_16; // @[DivSqrtRecFN_small.scala:313:56] assign _inReady_T_16 = _GEN; // @[DivSqrtRecFN_small.scala:313:56] wire [5:0] _rawOutValid_T_16; // @[DivSqrtRecFN_small.scala:313:56] assign _rawOutValid_T_16 = _GEN; // @[DivSqrtRecFN_small.scala:313:56] wire [5:0] _cycleNum_T_12; // @[DivSqrtRecFN_small.scala:313:56] assign _cycleNum_T_12 = _GEN; // @[DivSqrtRecFN_small.scala:313:56] wire [4:0] _inReady_T_17 = _inReady_T_16[4:0]; // @[DivSqrtRecFN_small.scala:313:56] wire _inReady_T_18 = _inReady_T_17 < 5'h2; // @[DivSqrtRecFN_small.scala:313:56, :317:38] wire _inReady_T_19 = _inReady_T_14 & _inReady_T_18; // @[DivSqrtRecFN_small.scala:313:{16,28}, :317:38] wire _inReady_T_20 = _inReady_T_11 \| _inReady_T_19; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16] wire _inReady_T_23 = _inReady_T_20 \| _inReady_T_22; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16] wire _inReady_T_24 = _inReady_T_23; // @[DivSqrtRecFN_small.scala:313:95, :317:46] wire _rawOutValid_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28] wire _rawOutValid_T_1 = entering & _rawOutValid_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}] wire _rawOutValid_T_3 = _rawOutValid_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}] wire _rawOutValid_T_11 = _rawOutValid_T_3; // @[DivSqrtRecFN_small.scala:305:{16,57}] wire _rawOutValid_T_12 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17] wire _rawOutValid_T_13 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31] wire _rawOutValid_T_14 = _rawOutValid_T_12 & _rawOutValid_T_13; // @[DivSqrtRecFN_small.scala:313:{17,28,31}] wire [4:0] _rawOutValid_T_17 = _rawOutValid_T_16[4:0]; // @[DivSqrtRecFN_small.scala:313:56] wire _rawOutValid_T_18 = _rawOutValid_T_17 == 5'h1; // @[DivSqrtRecFN_small.scala:313:56, :318:42] wire _rawOutValid_T_19 = _rawOutValid_T_14 & _rawOutValid_T_18; // @[DivSqrtRecFN_small.scala:313:{16,28}, :318:42] wire _rawOutValid_T_20 = _rawOutValid_T_11 \| _rawOutValid_T_19; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16] wire _rawOutValid_T_23 = _rawOutValid_T_20 \| _rawOutValid_T_22; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16] wire _rawOutValid_T_24 = _rawOutValid_T_23; // @[DivSqrtRecFN_small.scala:313:95, :318:51] wire _cycleNum_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28] wire _cycleNum_T_1 = entering & _cycleNum_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}] wire _cycleNum_T_2 = _cycleNum_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}] wire [4:0] _cycleNum_T_4 = {4'hC, ~_cycleNum_T_3}; // @[DivSqrtRecFN_small.scala:308:{24,36}] wire [4:0] _cycleNum_T_5 = io_sqrtOp_0 ? _cycleNum_T_4 : 5'h1A; // @[DivSqrtRecFN_small.scala:199:5, :307:20, :308:24] wire [4:0] _cycleNum_T_6 = entering_normalCase ? _cycleNum_T_5 : 5'h0; // @[DivSqrtRecFN_small.scala:298:40, :306:16, :307:20] wire [4:0] _cycleNum_T_7 = {4'h0, _cycleNum_T_2} \| _cycleNum_T_6; // @[DivSqrtRecFN_small.scala:305:{16,57}, :306:16, :313:56] wire _cycleNum_T_8 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17] wire _cycleNum_T_9 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31] wire _cycleNum_T_10 = _cycleNum_T_8 & _cycleNum_T_9; // @[DivSqrtRecFN_small.scala:313:{17,28,31}] wire [4:0] _cycleNum_T_13 = _cycleNum_T_12[4:0]; // @[DivSqrtRecFN_small.scala:313:56] wire [4:0] _cycleNum_T_14 = _cycleNum_T_10 ? _cycleNum_T_13 : 5'h0; // @[DivSqrtRecFN_small.scala:313:{16,28,56}] wire [4:0] _cycleNum_T_15 = _cycleNum_T_7 \| _cycleNum_T_14; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16] wire [4:0] _cycleNum_T_17 = {_cycleNum_T_15[4:1], _cycleNum_T_15[0] \| _cycleNum_T_16}; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16] wire [8:0] _sExp_Z_T = io_a_sExp_0[9:1]; // @[DivSqrtRecFN_small.scala:199:5, :335:29] wire [9:0] _sExp_Z_T_1 = {_sExp_Z_T[8], _sExp_Z_T} + 10'h80; // @[DivSqrtRecFN_small.scala:335:{29,34}] wire [9:0] _sExp_Z_T_2 = io_sqrtOp_0 ? _sExp_Z_T_1 : sSatExpQuot_S_div; // @[DivSqrtRecFN_small.scala:199:5, :289:11, :334:16, :335:34] wire _fractB_Z_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :342:28] wire _fractB_Z_T_1 = inReady & _fractB_Z_T; // @[DivSqrtRecFN_small.scala:225:33, :342:{25,28}] wire [22:0] _fractB_Z_T_2 = io_b_sig_0[22:0]; // @[DivSqrtRecFN_small.scala:199:5, :342:73] wire [23:0] _fractB_Z_T_3 = {_fractB_Z_T_2, 1'h0}; // @[DivSqrtRecFN_small.scala:342:{73,90}] wire [23:0] _fractB_Z_T_4 = _fractB_Z_T_1 ? _fractB_Z_T_3 : 24'h0; // @[DivSqrtRecFN_small.scala:342:{16,25,90}] wire _GEN_0 = inReady & io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :343:25] wire _fractB_Z_T_5; // @[DivSqrtRecFN_small.scala:343:25] assign _fractB_Z_T_5 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25] wire _fractB_Z_T_10; // @[DivSqrtRecFN_small.scala:344:25] assign _fractB_Z_T_10 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25, :344:25] wire _sigX_Z_T_4; // @[DivSqrtRecFN_small.scala:395:25] assign _sigX_Z_T_4 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25, :395:25] wire _fractB_Z_T_7 = _fractB_Z_T_5 & _fractB_Z_T_6; // @[DivSqrtRecFN_small.scala:343:{25,38,52}] wire [22:0] _fractB_Z_T_8 = {_fractB_Z_T_7, 22'h0}; // @[DivSqrtRecFN_small.scala:343:{16,38}] wire [23:0] _fractB_Z_T_9 = {_fractB_Z_T_4[23], _fractB_Z_T_4[22:0] \| _fractB_Z_T_8}; // @[DivSqrtRecFN_small.scala:342:{16,100}, :343:16] wire _fractB_Z_T_12 = ~_fractB_Z_T_11; // @[DivSqrtRecFN_small.scala:344:{41,54}] wire _fractB_Z_T_13 = _fractB_Z_T_10 & _fractB_Z_T_12; // @[DivSqrtRecFN_small.scala:344:{25,38,41}] wire [23:0] _fractB_Z_T_14 = {_fractB_Z_T_13, 23'h0}; // @[DivSqrtRecFN_small.scala:344:{16,38}] wire [23:0] _fractB_Z_T_15 = _fractB_Z_T_9 \| _fractB_Z_T_14; // @[DivSqrtRecFN_small.scala:342:100, :343:100, :344:16] wire [23:0] _fractB_Z_T_20 = _fractB_Z_T_15; // @[DivSqrtRecFN_small.scala:343:100, :344:100] wire _fractB_Z_T_16 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :345:17] wire [21:0] _fractB_Z_T_18 = fractB_Z[23:2]; // @[DivSqrtRecFN_small.scala:236:29, :345:71] wire _fractB_Z_T_21 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :346:17] wire _fractB_Z_T_23 = _fractB_Z_T_21; // @[DivSqrtRecFN_small.scala:346:{17,42}] wire [22:0] _fractB_Z_T_24 = fractB_Z[23:1]; // @[DivSqrtRecFN_small.scala:236:29, :346:71] wire [22:0] _trialTerm2_newBit0_T = fractB_Z[23:1]; // @[DivSqrtRecFN_small.scala:236:29, :346:71, :373:52] wire [22:0] _fractB_Z_T_25 = _fractB_Z_T_23 ? _fractB_Z_T_24 : 23'h0; // @[DivSqrtRecFN_small.scala:346:{16,42,71}] wire [23:0] _fractB_Z_T_26 = {_fractB_Z_T_20[23], _fractB_Z_T_20[22:0] \| _fractB_Z_T_25}; // @[DivSqrtRecFN_small.scala:344:100, :345:100, :346:16] wire _rem_T = ~oddSqrt_S; // @[DivSqrtRecFN_small.scala:292:32, :352:24] wire _rem_T_1 = inReady & _rem_T; // @[DivSqrtRecFN_small.scala:225:33, :352:{21,24}] wire [25:0] _rem_T_2 = {io_a_sig_0, 1'h0}; // @[DivSqrtRecFN_small.scala:199:5, :352:47] wire [25:0] _rem_T_3 = _rem_T_1 ? _rem_T_2 : 26'h0; // @[DivSqrtRecFN_small.scala:352:{12,21,47}] wire _GEN_1 = inReady & oddSqrt_S; // @[DivSqrtRecFN_small.scala:225:33, :292:32, :353:21] wire _rem_T_4; // @[DivSqrtRecFN_small.scala:353:21] assign _rem_T_4 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21] wire _trialTerm_T_7; // @[DivSqrtRecFN_small.scala:364:21] assign _trialTerm_T_7 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21, :364:21] wire _sigX_Z_T_7; // @[DivSqrtRecFN_small.scala:396:25] assign _sigX_Z_T_7 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21, :396:25] wire [1:0] _rem_T_5 = io_a_sig_0[23:22]; // @[DivSqrtRecFN_small.scala:199:5, :354:27] wire [2:0] _rem_T_6 = {1'h0, _rem_T_5} - 3'h1; // @[DivSqrtRecFN_small.scala:354:{27,56}] wire [1:0] _rem_T_7 = _rem_T_6[1:0]; // @[DivSqrtRecFN_small.scala:354:56] wire [21:0] _rem_T_8 = io_a_sig_0[21:0]; // @[DivSqrtRecFN_small.scala:199:5, :355:27] wire [24:0] _rem_T_9 = {_rem_T_8, 3'h0}; // @[DivSqrtRecFN_small.scala:300:35, :355:{27,44}] wire [26:0] _rem_T_10 = {_rem_T_7, _rem_T_9}; // @[DivSqrtRecFN_small.scala:354:{16,56}, :355:44] wire [26:0] _rem_T_11 = _rem_T_4 ? _rem_T_10 : 27'h0; // @[DivSqrtRecFN_small.scala:353:{12,21}, :354:16] wire [26:0] _rem_T_12 = {1'h0, _rem_T_3} \| _rem_T_11; // @[DivSqrtRecFN_small.scala:352:{12,57}, :353:12] wire _rem_T_13 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :359:13] wire [26:0] _rem_T_14 = {rem_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:243:29, :359:29] wire [26:0] _rem_T_15 = _rem_T_13 ? _rem_T_14 : 27'h0; // @[DivSqrtRecFN_small.scala:359:{12,13,29}] wire [26:0] rem = _rem_T_12 \| _rem_T_15; // @[DivSqrtRecFN_small.scala:352:57, :358:11, :359:12] wire [31:0] _bitMask_T = 32'h1 << cycleNum; // @[DivSqrtRecFN_small.scala:224:33, :360:23] wire [29:0] bitMask = _bitMask_T[31:2]; // @[DivSqrtRecFN_small.scala:360:{23,34}] wire _trialTerm_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :362:24] wire _trialTerm_T_1 = inReady & _trialTerm_T; // @[DivSqrtRecFN_small.scala:225:33, :362:{21,24}] wire [25:0] _trialTerm_T_2 = {io_b_sig_0, 1'h0}; // @[DivSqrtRecFN_small.scala:199:5, :362:48] wire [25:0] _trialTerm_T_3 = _trialTerm_T_1 ? _trialTerm_T_2 : 26'h0; // @[DivSqrtRecFN_small.scala:362:{12,21,48}] wire _trialTerm_T_4 = inReady & evenSqrt_S; // @[DivSqrtRecFN_small.scala:225:33, :291:32, :363:21] wire [24:0] _trialTerm_T_5 = {_trialTerm_T_4, 24'h0}; // @[DivSqrtRecFN_small.scala:363:{12,21}] wire [25:0] _trialTerm_T_6 = {_trialTerm_T_3[25], _trialTerm_T_3[24:0] \| _trialTerm_T_5}; // @[DivSqrtRecFN_small.scala:362:{12,74}, :363:12] wire [25:0] _trialTerm_T_8 = _trialTerm_T_7 ? 26'h2800000 : 26'h0; // @[DivSqrtRecFN_small.scala:364:{12,21}] wire [25:0] _trialTerm_T_9 = _trialTerm_T_6 \| _trialTerm_T_8; // @[DivSqrtRecFN_small.scala:362:74, :363:74, :364:12] wire _trialTerm_T_10 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :365:13] wire [23:0] _trialTerm_T_11 = _trialTerm_T_10 ? fractB_Z : 24'h0; // @[DivSqrtRecFN_small.scala:236:29, :365:{12,13}] wire [25:0] _trialTerm_T_12 = {_trialTerm_T_9[25:24], _trialTerm_T_9[23:0] \| _trialTerm_T_11}; // @[DivSqrtRecFN_small.scala:363:74, :364:74, :365:12] wire _trialTerm_T_13 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :366:13] wire _trialTerm_T_14 = ~sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :366:26] wire _trialTerm_T_15 = _trialTerm_T_13 & _trialTerm_T_14; // @[DivSqrtRecFN_small.scala:366:{13,23,26}] wire [24:0] _trialTerm_T_17 = {_trialTerm_T_15, 24'h0}; // @[DivSqrtRecFN_small.scala:366:{12,23}] wire [25:0] _trialTerm_T_18 = {_trialTerm_T_12[25], _trialTerm_T_12[24:0] \| _trialTerm_T_17}; // @[DivSqrtRecFN_small.scala:364:74, :365:74, :366:12] wire _trialTerm_T_19 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :367:13] wire _trialTerm_T_20 = _trialTerm_T_19 & sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :367:{13,23}] wire [26:0] _GEN_2 = {sigX_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:245:29, :367:44] wire [26:0] _trialTerm_T_21; // @[DivSqrtRecFN_small.scala:367:44] assign _trialTerm_T_21 = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44] wire [26:0] _trialTerm2_newBit0_T_1; // @[DivSqrtRecFN_small.scala:373:64] assign _trialTerm2_newBit0_T_1 = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44, :373:64] wire [26:0] _io_rawOut_sig_T; // @[DivSqrtRecFN_small.scala:414:31] assign _io_rawOut_sig_T = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44, :414:31] wire [26:0] _trialTerm_T_22 = _trialTerm_T_20 ? _trialTerm_T_21 : 27'h0; // @[DivSqrtRecFN_small.scala:367:{12,23,44}] wire [26:0] trialTerm = {1'h0, _trialTerm_T_18} \| _trialTerm_T_22; // @[DivSqrtRecFN_small.scala:365:74, :366:74, :367:12] wire [27:0] _trialRem_T = {1'h0, rem}; // @[DivSqrtRecFN_small.scala:358:11, :368:24] wire [27:0] _trialRem_T_1 = {1'h0, trialTerm}; // @[DivSqrtRecFN_small.scala:366:74, :368:42] wire [28:0] trialRem = {_trialRem_T[27], _trialRem_T} - {_trialRem_T_1[27], _trialRem_T_1}; // @[DivSqrtRecFN_small.scala:368:{24,29,42}] wire [28:0] _nextRem_Z_T = trialRem; // @[DivSqrtRecFN_small.scala:368:29, :371:42] wire newBit = $signed(trialRem) > -29'sh1; // @[DivSqrtRecFN_small.scala:368:29, :369:23] wire [28:0] _nextRem_Z_T_1 = newBit ? _nextRem_Z_T : {2'h0, rem}; // @[DivSqrtRecFN_small.scala:354:56, :358:11, :369:23, :371:{24,42}] wire [25:0] nextRem_Z = _nextRem_Z_T_1[25:0]; // @[DivSqrtRecFN_small.scala:371:{24,54}] wire [25:0] _nextRem_Z_2_T_10 = nextRem_Z; // @[DivSqrtRecFN_small.scala:371:54, :388:12] wire [26:0] rem2 = {nextRem_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:371:54, :372:25] wire [26:0] _trialTerm2_newBit0_T_2 = {4'h0, _trialTerm2_newBit0_T} \| _trialTerm2_newBit0_T_1; // @[DivSqrtRecFN_small.scala:313:56, :373:{52,56,64}] wire [24:0] _trialTerm2_newBit0_T_4 = {1'h1, fractB_Z}; // @[DivSqrtRecFN_small.scala:236:29, :373:78] wire [26:0] trialTerm2_newBit0 = sqrtOp_Z ? _trialTerm2_newBit0_T_2 : {2'h0, _trialTerm2_newBit0_T_4}; // @[DivSqrtRecFN_small.scala:228:29, :354:56, :373:{33,56,78}] wire [24:0] _trialTerm2_newBit1_T = {fractB_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:236:29, :374:73] wire [24:0] _trialTerm2_newBit1_T_1 = sqrtOp_Z ? _trialTerm2_newBit1_T : 25'h0; // @[DivSqrtRecFN_small.scala:228:29, :374:{54,73}] wire [26:0] trialTerm2_newBit1 = {trialTerm2_newBit0[26:25], trialTerm2_newBit0[24:0] \| _trialTerm2_newBit1_T_1}; // @[DivSqrtRecFN_small.scala:373:33, :374:{49,54}] wire [29:0] _GEN_3 = {trialRem, 1'h0}; // @[DivSqrtRecFN_small.scala:368:29, :377:22] wire [29:0] _trialRem2_T; // @[DivSqrtRecFN_small.scala:377:22] assign _trialRem2_T = _GEN_3; // @[DivSqrtRecFN_small.scala:377:22] wire [29:0] _nextNotZeroRem_Z_2_T_1; // @[DivSqrtRecFN_small.scala:382:53] assign _nextNotZeroRem_Z_2_T_1 = _GEN_3; // @[DivSqrtRecFN_small.scala:377:22, :382:53] wire [27:0] _GEN_4 = {1'h0, trialTerm2_newBit1}; // @[DivSqrtRecFN_small.scala:374:49, :377:48] wire [27:0] _trialRem2_T_1; // @[DivSqrtRecFN_small.scala:377:48] assign _trialRem2_T_1 = _GEN_4; // @[DivSqrtRecFN_small.scala:377:48] wire [27:0] _nextNotZeroRem_Z_2_T_2; // @[DivSqrtRecFN_small.scala:382:79] assign _nextNotZeroRem_Z_2_T_2 = _GEN_4; // @[DivSqrtRecFN_small.scala:377:48, :382:79] wire [30:0] _trialRem2_T_2 = {_trialRem2_T[29], _trialRem2_T} - {{3{_trialRem2_T_1[27]}}, _trialRem2_T_1}; // @[DivSqrtRecFN_small.scala:377:{22,27,48}] wire [29:0] _trialRem2_T_3 = _trialRem2_T_2[29:0]; // @[DivSqrtRecFN_small.scala:377:27] wire [29:0] _trialRem2_T_4 = _trialRem2_T_3; // @[DivSqrtRecFN_small.scala:377:27] wire [27:0] _GEN_5 = {rem_Z, 2'h0}; // @[DivSqrtRecFN_small.scala:243:29, :354:56, :378:19] wire [27:0] _trialRem2_T_5; // @[DivSqrtRecFN_small.scala:378:19] assign _trialRem2_T_5 = _GEN_5; // @[DivSqrtRecFN_small.scala:378:19] wire [27:0] _nextNotZeroRem_Z_2_T_10; // @[DivSqrtRecFN_small.scala:383:51] assign _nextNotZeroRem_Z_2_T_10 = _GEN_5; // @[DivSqrtRecFN_small.scala:378:19, :383:51] wire [26:0] _trialRem2_T_6 = _trialRem2_T_5[26:0]; // @[DivSqrtRecFN_small.scala:378:{19,23}] wire [27:0] _trialRem2_T_7 = {1'h0, _trialRem2_T_6}; // @[DivSqrtRecFN_small.scala:378:{23,39}] wire [27:0] _GEN_6 = {1'h0, trialTerm2_newBit0}; // @[DivSqrtRecFN_small.scala:373:33, :378:65] wire [27:0] _trialRem2_T_8; // @[DivSqrtRecFN_small.scala:378:65] assign _trialRem2_T_8 = _GEN_6; // @[DivSqrtRecFN_small.scala:378:65] wire [27:0] _nextNotZeroRem_Z_2_T_13; // @[DivSqrtRecFN_small.scala:383:97] assign _nextNotZeroRem_Z_2_T_13 = _GEN_6; // @[DivSqrtRecFN_small.scala:378:65, :383:97] wire [28:0] _trialRem2_T_9 = {_trialRem2_T_7[27], _trialRem2_T_7} - {_trialRem2_T_8[27], _trialRem2_T_8}; // @[DivSqrtRecFN_small.scala:378:{39,44,65}] wire [27:0] _trialRem2_T_10 = _trialRem2_T_9[27:0]; // @[DivSqrtRecFN_small.scala:378:44] wire [27:0] _trialRem2_T_11 = _trialRem2_T_10; // @[DivSqrtRecFN_small.scala:378:44] wire [29:0] trialRem2 = newBit ? _trialRem2_T_4 : {{2{_trialRem2_T_11[27]}}, _trialRem2_T_11}; // @[DivSqrtRecFN_small.scala:369:23, :376:12, :377:27, :378:44] wire [29:0] _nextRem_Z_2_T_1 = trialRem2; // @[DivSqrtRecFN_small.scala:376:12, :386:51] wire newBit2 = $signed(trialRem2) > -30'sh1; // @[DivSqrtRecFN_small.scala:376:12, :379:24] wire _nextNotZeroRem_Z_T = inReady \| newBit; // @[DivSqrtRecFN_small.scala:225:33, :369:23, :380:40] wire _nextNotZeroRem_Z_T_1 = \|trialRem; // @[DivSqrtRecFN_small.scala:368:29, :380:60] wire nextNotZeroRem_Z = _nextNotZeroRem_Z_T ? _nextNotZeroRem_Z_T_1 : notZeroRem_Z; // @[DivSqrtRecFN_small.scala:244:29, :380:{31,40,60}] wire _nextNotZeroRem_Z_2_T_22 = nextNotZeroRem_Z; // @[DivSqrtRecFN_small.scala:380:31, :384:38] wire [30:0] _nextNotZeroRem_Z_2_T_3 = {_nextNotZeroRem_Z_2_T_1[29], _nextNotZeroRem_Z_2_T_1} - {{3{_nextNotZeroRem_Z_2_T_2[27]}}, _nextNotZeroRem_Z_2_T_2}; // @[DivSqrtRecFN_small.scala:382:{53,58,79}] wire [29:0] _nextNotZeroRem_Z_2_T_4 = _nextNotZeroRem_Z_2_T_3[29:0]; // @[DivSqrtRecFN_small.scala:382:58] wire [29:0] _nextNotZeroRem_Z_2_T_5 = _nextNotZeroRem_Z_2_T_4; // @[DivSqrtRecFN_small.scala:382:58] wire _nextNotZeroRem_Z_2_T_6 = $signed(_nextNotZeroRem_Z_2_T_5) > 30'sh0; // @[DivSqrtRecFN_small.scala:379:24, :382:{42,58}] wire _nextNotZeroRem_Z_2_T_8 = ~newBit; // @[DivSqrtRecFN_small.scala:369:23, :383:27] wire [26:0] _nextNotZeroRem_Z_2_T_11 = _nextNotZeroRem_Z_2_T_10[26:0]; // @[DivSqrtRecFN_small.scala:383:{51,55}] wire [27:0] _nextNotZeroRem_Z_2_T_12 = {1'h0, _nextNotZeroRem_Z_2_T_11}; // @[DivSqrtRecFN_small.scala:383:{55,71}] wire [28:0] _nextNotZeroRem_Z_2_T_14 = {_nextNotZeroRem_Z_2_T_12[27], _nextNotZeroRem_Z_2_T_12} - {_nextNotZeroRem_Z_2_T_13[27], _nextNotZeroRem_Z_2_T_13}; // @[DivSqrtRecFN_small.scala:383:{71,76,97}] wire [27:0] _nextNotZeroRem_Z_2_T_15 = _nextNotZeroRem_Z_2_T_14[27:0]; // @[DivSqrtRecFN_small.scala:383:76] wire [27:0] _nextNotZeroRem_Z_2_T_16 = _nextNotZeroRem_Z_2_T_15; // @[DivSqrtRecFN_small.scala:383:76] wire _nextNotZeroRem_Z_2_T_17 = $signed(_nextNotZeroRem_Z_2_T_16) > 28'sh0; // @[DivSqrtRecFN_small.scala:383:{43,76}] wire nextNotZeroRem_Z_2 = _nextNotZeroRem_Z_2_T_22; // @[DivSqrtRecFN_small.scala:383:103, :384:38] wire [25:0] _nextRem_Z_2_T_2 = _nextRem_Z_2_T_1[25:0]; // @[DivSqrtRecFN_small.scala:386:{51,57}] wire _nextRem_Z_2_T_4 = ~newBit2; // @[DivSqrtRecFN_small.scala:379:24, :387:31] wire [25:0] _nextRem_Z_2_T_6 = rem2[25:0]; // @[DivSqrtRecFN_small.scala:372:25, :387:45] wire [25:0] nextRem_Z_2 = _nextRem_Z_2_T_10; // @[DivSqrtRecFN_small.scala:387:83, :388:12] wire _sigX_Z_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :394:28] wire _sigX_Z_T_1 = inReady & _sigX_Z_T; // @[DivSqrtRecFN_small.scala:225:33, :394:{25,28}] wire [25:0] _sigX_Z_T_2 = {newBit, 25'h0}; // @[DivSqrtRecFN_small.scala:369:23, :394:50] wire [25:0] _sigX_Z_T_3 = _sigX_Z_T_1 ? _sigX_Z_T_2 : 26'h0; // @[DivSqrtRecFN_small.scala:394:{16,25,50}] wire [24:0] _sigX_Z_T_5 = {_sigX_Z_T_4, 24'h0}; // @[DivSqrtRecFN_small.scala:395:{16,25}] wire [25:0] _sigX_Z_T_6 = {_sigX_Z_T_3[25], _sigX_Z_T_3[24:0] \| _sigX_Z_T_5}; // @[DivSqrtRecFN_small.scala:394:{16,74}, :395:16] wire [23:0] _sigX_Z_T_8 = {newBit, 23'h0}; // @[DivSqrtRecFN_small.scala:369:23, :396:50] wire [23:0] _sigX_Z_T_9 = _sigX_Z_T_7 ? _sigX_Z_T_8 : 24'h0; // @[DivSqrtRecFN_small.scala:396:{16,25,50}] wire [25:0] _sigX_Z_T_10 = {_sigX_Z_T_6[25:24], _sigX_Z_T_6[23:0] \| _sigX_Z_T_9}; // @[DivSqrtRecFN_small.scala:394:74, :395:74, :396:16] wire _sigX_Z_T_11 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :397:17] wire [25:0] _sigX_Z_T_12 = _sigX_Z_T_11 ? sigX_Z : 26'h0; // @[DivSqrtRecFN_small.scala:245:29, :397:{16,17}] wire [25:0] _sigX_Z_T_13 = _sigX_Z_T_10 \| _sigX_Z_T_12; // @[DivSqrtRecFN_small.scala:395:74, :396:74, :397:16] wire _sigX_Z_T_14 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :398:17] wire _sigX_Z_T_15 = _sigX_Z_T_14 & newBit; // @[DivSqrtRecFN_small.scala:369:23, :398:{17,27}] wire [29:0] _sigX_Z_T_16 = _sigX_Z_T_15 ? bitMask : 30'h0; // @[DivSqrtRecFN_small.scala:360:34, :379:24, :398:{16,27}] wire [29:0] _sigX_Z_T_17 = {4'h0, _sigX_Z_T_13} \| _sigX_Z_T_16; // @[DivSqrtRecFN_small.scala:313:56, :396:74, :397:74, :398:16] wire [29:0] _sigX_Z_T_21 = _sigX_Z_T_17; // @[DivSqrtRecFN_small.scala:397:74, :398:74] wire [28:0] _sigX_Z_T_19 = bitMask[29:1]; // @[DivSqrtRecFN_small.scala:360:34, :399:51] wire _io_rawOutValid_div_T = ~sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :366:26, :404:43] assign _io_rawOutValid_div_T_1 = rawOutValid & _io_rawOutValid_div_T; // @[DivSqrtRecFN_small.scala:226:33, :404:{40,43}] assign io_rawOutValid_div_0 = _io_rawOutValid_div_T_1; // @[DivSqrtRecFN_small.scala:199:5, :404:40] assign _io_rawOutValid_sqrt_T = rawOutValid & sqrtOp_Z; // @[DivSqrtRecFN_small.scala:226:33, :228:29, :405:40] assign io_rawOutValid_sqrt_0 = _io_rawOutValid_sqrt_T; // @[DivSqrtRecFN_small.scala:199:5, :405:40] assign _io_invalidExc_T = majorExc_Z & isNaN_Z; // @[DivSqrtRecFN_small.scala:229:29, :231:29, :407:36] assign io_invalidExc_0 = _io_invalidExc_T; // @[DivSqrtRecFN_small.scala:199:5, :407:36] wire _io_infiniteExc_T = ~isNaN_Z; // @[DivSqrtRecFN_small.scala:231:29, :408:39] assign _io_infiniteExc_T_1 = majorExc_Z & _io_infiniteExc_T; // @[DivSqrtRecFN_small.scala:229:29, :408:{36,39}] assign io_infiniteExc_0 = _io_infiniteExc_T_1; // @[DivSqrtRecFN_small.scala:199:5, :408:36] assign _io_rawOut_sig_T_1 = {_io_rawOut_sig_T[26:1], _io_rawOut_sig_T[0] \| notZeroRem_Z}; // @[DivSqrtRecFN_small.scala:244:29, :414:{31,35}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_1; // @[DivSqrtRecFN_small.scala:199:5, :414:35] always @(posedge clock) begin // @[DivSqrtRecFN_small.scala:199:5] if (reset) begin // @[DivSqrtRecFN_small.scala:199:5] cycleNum <= 5'h0; // @[DivSqrtRecFN_small.scala:224:33] inReady <= 1'h1; // @[DivSqrtRecFN_small.scala:225:33] rawOutValid <= 1'h0; // @[DivSqrtRecFN_small.scala:226:33] end else if (~idle \| entering) begin // @[DivSqrtRecFN_small.scala:296:25, :297:28, :303:{11,18}] cycleNum <= _cycleNum_T_17; // @[DivSqrtRecFN_small.scala:224:33, :313:95] inReady <= _inReady_T_24; // @[DivSqrtRecFN_small.scala:225:33, :317:46] rawOutValid <= _rawOutValid_T_24; // @[DivSqrtRecFN_small.scala:226:33, :318:51] end if (entering) begin // @[DivSqrtRecFN_small.scala:297:28] sqrtOp_Z <= io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :228:29] majorExc_Z <= majorExc_S; // @[DivSqrtRecFN_small.scala:229:29, :258:12] isNaN_Z <= isNaN_S; // @[DivSqrtRecFN_small.scala:231:29, :265:12] isInf_Z <= isInf_S; // @[DivSqrtRecFN_small.scala:232:29, :269:23] isZero_Z <= isZero_S; // @[DivSqrtRecFN_small.scala:233:29, :270:23] sign_Z <= sign_S; // @[DivSqrtRecFN_small.scala:234:29, :271:30] sExp_Z <= _sExp_Z_T_2; // @[DivSqrtRecFN_small.scala:235:29, :334:16] roundingMode_Z <= io_roundingMode_0; // @[DivSqrtRecFN_small.scala:199:5, :237:29] end if (entering \| ~inReady & sqrtOp_Z) // @[DivSqrtRecFN_small.scala:225:33, :228:29, :297:28, :340:{20,23,33}] fractB_Z <= _fractB_Z_T_26; // @[DivSqrtRecFN_small.scala:236:29, :345:100] if (entering \| ~inReady) begin // @[DivSqrtRecFN_small.scala:225:33, :297:28, :340:23, :390:20] rem_Z <= nextRem_Z_2; // @[DivSqrtRecFN_small.scala:243:29, :387:83] notZeroRem_Z <= nextNotZeroRem_Z_2; // @[DivSqrtRecFN_small.scala:244:29, :383:103] sigX_Z <= _sigX_Z_T_21[25:0]; // @[DivSqrtRecFN_small.scala:245:29, :393:16, :398:74] end always @(posedge) assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:199:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_15( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [11:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [11:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [4:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [11:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25] reg [11:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [11:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 12'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_44( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_57 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid \|\| io.clear \|\| io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 \|\| rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_\|\|_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_\|\|_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready \|\| agen_ready \|\| dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }	module IssueSlot_39( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire [1:0] io_iss_uop_lrs2_rtype = 2'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0 = io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_agen; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_agen_0 = slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_agen = slot_uop_iw_issued_partial_agen; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_dgen_0 = slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_dgen = slot_uop_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_agen_0 = next_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_dgen_0 = next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //* POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //* UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //* REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero \|\| rawB.isZero \|\| (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign \|\| (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //* NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR \|\| reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN \|\| rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR \|\| CDom_reduced4SigExtra \|\| CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR \|\| notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd \|\| io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA \|\| io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny \|\| (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) \|\| (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) \|\| (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB \|\| io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros \|\| (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) \|\| (io.fromPreMul.isInfC && opSignC) \|\| (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) \|\| (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd \|\| opSignC)) \|\| (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulAddRecFNToRaw_postMul_e5_s11_6( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [6:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [3:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [12:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [22:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [6:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [13:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [6:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [3:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [12:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [22:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[MulAddRecFN.scala:169:7] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [6:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [13:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [6:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [13:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[MulAddRecFN.scala:169:7, :186:45] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[22]; // @[MulAddRecFN.scala:169:7, :192:32] wire [13:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 14'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [12:0] _sigSum_T_2 = _sigSum_T_1[12:0]; // @[MulAddRecFN.scala:193:47] wire [12:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [21:0] _sigSum_T_4 = io_mulAddResult_0[21:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [34:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [35:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [7:0] _GEN = {io_fromPreMul_sExpSum_0[6], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [7:0] _CDom_sExp_T_1 = _GEN - {{6{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [6:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[6:0]; // @[MulAddRecFN.scala:203:43] wire [6:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [23:0] _CDom_absSigSum_T = sigSum[35:12]; // @[MulAddRecFN.scala:192:12, :206:20] wire [23:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[12:11]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [20:0] _CDom_absSigSum_T_4 = sigSum[33:13]; // @[MulAddRecFN.scala:192:12, :210:23] wire [23:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [23:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [10:0] _CDom_absSigSumExtra_T = sigSum[11:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [10:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = \|_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [11:0] _CDom_absSigSumExtra_T_3 = sigSum[12:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = \|_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [38:0] _CDom_mainSig_T = {15'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [15:0] CDom_mainSig = _CDom_mainSig_T[23:8]; // @[MulAddRecFN.scala:219:{24,56}] wire [10:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[10:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [10:0] _CDom_reduced4SigExtra_T_1 = _CDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = \|_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = \|_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[10:8]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = \|_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[3:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [1:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [4:0] CDom_reduced4SigExtra_shift = $signed(5'sh10 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [1:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[2:1]; // @[primitives.scala:76:56, :78:22] wire _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[0]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_5[1]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_8 = {_CDom_reduced4SigExtra_T_6, _CDom_reduced4SigExtra_T_7}; // @[primitives.scala:77:20] wire [2:0] _CDom_reduced4SigExtra_T_9 = {1'h0, _CDom_reduced4SigExtra_T_2[1:0] & _CDom_reduced4SigExtra_T_8}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = \|_CDom_reduced4SigExtra_T_9; // @[MulAddRecFN.scala:222:72, :223:73] wire [12:0] _CDom_sig_T = CDom_mainSig[15:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = \|_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 \| CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 \| CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [13:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[25]; // @[MulAddRecFN.scala:192:12, :232:36] wire [24:0] _notCDom_absSigSum_T = sigSum[24:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [24:0] _notCDom_absSigSum_T_2 = sigSum[24:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [24:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [25:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {25'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [24:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[24:0]; // @[MulAddRecFN.scala:236:41] wire [24:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[24]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire [3:0] _notCDom_normDistReduced2_T_13 = _notCDom_normDistReduced2_T_1 ? 4'hB : 4'hC; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_14 = _notCDom_normDistReduced2_T_2 ? 4'hA : _notCDom_normDistReduced2_T_13; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_15 = _notCDom_normDistReduced2_T_3 ? 4'h9 : _notCDom_normDistReduced2_T_14; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_16 = _notCDom_normDistReduced2_T_4 ? 4'h8 : _notCDom_normDistReduced2_T_15; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_17 = _notCDom_normDistReduced2_T_5 ? 4'h7 : _notCDom_normDistReduced2_T_16; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_18 = _notCDom_normDistReduced2_T_6 ? 4'h6 : _notCDom_normDistReduced2_T_17; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_19 = _notCDom_normDistReduced2_T_7 ? 4'h5 : _notCDom_normDistReduced2_T_18; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_20 = _notCDom_normDistReduced2_T_8 ? 4'h4 : _notCDom_normDistReduced2_T_19; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_21 = _notCDom_normDistReduced2_T_9 ? 4'h3 : _notCDom_normDistReduced2_T_20; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_22 = _notCDom_normDistReduced2_T_10 ? 4'h2 : _notCDom_normDistReduced2_T_21; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_23 = _notCDom_normDistReduced2_T_11 ? 4'h1 : _notCDom_normDistReduced2_T_22; // @[Mux.scala:50:70] wire [3:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_12 ? 4'h0 : _notCDom_normDistReduced2_T_23; // @[Mux.scala:50:70] wire [4:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [5:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [7:0] _notCDom_sExp_T_1 = _GEN - {{2{_notCDom_sExp_T[5]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [6:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[6:0]; // @[MulAddRecFN.scala:241:46] wire [6:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [55:0] _notCDom_mainSig_T = {31'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [15:0] notCDom_mainSig = _notCDom_mainSig_T[25:10]; // @[MulAddRecFN.scala:243:{27,50}] wire [5:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[5:0]; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_1 = {_notCDom_reduced4SigExtra_T, 1'h0}; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[6]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = _notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_reducedVec_1, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_reducedVec_3, notCDom_reduced4SigExtra_reducedVec_2}; // @[primitives.scala:101:30, :107:20] wire [3:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [2:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[3:1]; // @[Mux.scala:50:70] wire [2:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] notCDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [2:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[3:1]; // @[primitives.scala:76:56, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[1:0]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_6[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_9 = {_notCDom_reduced4SigExtra_T_7, _notCDom_reduced4SigExtra_T_8}; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_10 = _notCDom_reduced4SigExtra_T_5[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _notCDom_reduced4SigExtra_T_11 = {_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_10}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_12 = {1'h0, _notCDom_reduced4SigExtra_T_2[2:0] & _notCDom_reduced4SigExtra_T_11}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = \|_notCDom_reduced4SigExtra_T_12; // @[MulAddRecFN.scala:247:78, :249:11] wire [12:0] _notCDom_sig_T = notCDom_mainSig[15:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = \|_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 \| notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [13:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[13:12]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = notCDom_completeCancellation ? roundingMode_min : _notCDom_sign_T; // @[MulAddRecFN.scala:186:45, :255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 \| io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd \| io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 \| io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 \| _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 \| _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 \| _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 \| io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros \| _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T \| _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_3 = ~roundingMode_min; // @[MulAddRecFN.scala:186:45, :287:29] wire _io_rawOut_sign_T_4 = notNaN_addZeros & _io_rawOut_sign_T_3; // @[MulAddRecFN.scala:267:58, :287:{26,29}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 \| _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_8 = notNaN_addZeros & roundingMode_min; // @[MulAddRecFN.scala:186:45, :267:58, :289:26] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 \| opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_10 = _io_rawOut_sign_T_8 & _io_rawOut_sign_T_9; // @[MulAddRecFN.scala:289:{26,46}, :290:37] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7 \| _io_rawOut_sign_T_10; // @[MulAddRecFN.scala:286:43, :288:48, :289:46] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 \| _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Error.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.resources.SimpleDevice import freechips.rocketchip.tilelink.{TLArbiter, TLMessages, TLPermissions} /** Adds a /dev/null slave that generates TL error response messages / class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends DevNullDevice(params, minLatency = if (buffer) 1 else 0, beatBytes, new SimpleDevice("error-device", Seq("sifive,error0"))) { lazy val module = new Impl class Impl extends LazyModuleImp(this) { import TLMessages._ import TLPermissions._ val (in, edge) = node.in(0) val a = if (buffer) {Queue(in.a, 1)} else in.a val da = Wire(chiselTypeOf(in.d)) val idle = RegInit(true.B) val a_last = edge.last(a) val (da_first, da_last, _) = edge.firstlast(da) assert (idle \|\| da_first) // we only send Grant, never GrantData => simplified flow control below a.ready := (da.ready && da_last && idle) \|\| !a_last da.valid := a.valid && a_last && idle da.bits.opcode := TLMessages.adResponse(a.bits.opcode) da.bits.param := 0.U // toT, but error grants must be handled transiently (ie: you don't keep permissions) da.bits.size := a.bits.size da.bits.source := a.bits.source da.bits.sink := 0.U da.bits.denied := true.B da.bits.data := 0.U da.bits.corrupt := edge.hasData(da.bits) if (params.acquire) { val c = if (buffer) {Queue(in.c, 1)} else in.c val dc = Wire(chiselTypeOf(in.d)) val c_last = edge.last(c) val dc_last = edge.last(dc) // Only allow one Grant in-flight at a time when (da.fire && da.bits.opcode === Grant) { idle := false.B } when (in.e.fire) { idle := true.B } c.ready := (dc.ready && dc_last) \|\| !c_last dc.valid := c.valid && c_last // ReleaseAck is not allowed to report failure dc.bits.opcode := ReleaseAck dc.bits.param := VecInit(toB, toN, toN)(c.bits.param(1,0)) dc.bits.size := c.bits.size dc.bits.source := c.bits.source dc.bits.sink := 0.U dc.bits.denied := false.B dc.bits.data := 0.U dc.bits.corrupt := false.B // Combine response channels TLArbiter.lowest(edge, in.d, dc, da) } else { in.d <> da } // We never probe or issue B requests in.b.valid := false.B // Sink GrantAcks in.e.ready := true.B } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLError( // @[Error.scala:21:9] input clock, // @[Error.scala:21:9] input reset, // @[Error.scala:21:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _a_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _a_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [3:0] _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire auto_in_a_valid_0 = auto_in_a_valid; // @[Error.scala:21:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Error.scala:21:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Error.scala:21:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Error.scala:21:9] wire [8:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Error.scala:21:9] wire [13:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Error.scala:21:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Error.scala:21:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Error.scala:21:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Error.scala:21:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Error.scala:21:9] wire [7:0][2:0] _GEN = '{3'h4, 3'h4, 3'h2, 3'h1, 3'h1, 3'h1, 3'h0, 3'h0}; wire auto_in_d_bits_denied = 1'h1; // @[Error.scala:21:9] wire nodeIn_d_bits_denied = 1'h1; // @[MixedNode.scala:551:17] wire da_bits_denied = 1'h1; // @[Error.scala:28:18] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Error.scala:21:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] da_bits_param = 2'h0; // @[Error.scala:28:18] wire auto_in_d_bits_sink = 1'h0; // @[Error.scala:21:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire da_bits_sink = 1'h0; // @[Error.scala:28:18] wire [63:0] auto_in_d_bits_data = 64'h0; // @[Error.scala:21:9] wire [63:0] nodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] da_bits_data = 64'h0; // @[Error.scala:28:18] wire [2:0] _da_bits_opcode_WIRE_6 = 3'h4; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_7 = 3'h4; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_5 = 3'h2; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_2 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_3 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_4 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_0 = 3'h0; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_1 = 3'h0; // @[Bundles.scala:47:27] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Error.scala:21:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Error.scala:21:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Error.scala:21:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Error.scala:21:9] wire [8:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Error.scala:21:9] wire [13:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Error.scala:21:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Error.scala:21:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Error.scala:21:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Error.scala:21:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Error.scala:21:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire auto_in_a_ready_0; // @[Error.scala:21:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Error.scala:21:9] wire [3:0] auto_in_d_bits_size_0; // @[Error.scala:21:9] wire [8:0] auto_in_d_bits_source_0; // @[Error.scala:21:9] wire auto_in_d_bits_corrupt_0; // @[Error.scala:21:9] wire auto_in_d_valid_0; // @[Error.scala:21:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Error.scala:21:9] wire da_ready = nodeIn_d_ready; // @[Error.scala:28:18] wire da_valid; // @[Error.scala:28:18] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Error.scala:21:9] wire [2:0] da_bits_opcode; // @[Error.scala:28:18] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Error.scala:21:9] wire [3:0] da_bits_size; // @[Error.scala:28:18] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Error.scala:21:9] wire [8:0] da_bits_source; // @[Error.scala:28:18] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Error.scala:21:9] wire da_bits_corrupt; // @[Error.scala:28:18] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Error.scala:21:9] wire _da_valid_T_1; // @[Error.scala:36:35] assign nodeIn_d_valid = da_valid; // @[Error.scala:28:18] assign nodeIn_d_bits_opcode = da_bits_opcode; // @[Error.scala:28:18] assign nodeIn_d_bits_size = da_bits_size; // @[Error.scala:28:18] assign nodeIn_d_bits_source = da_bits_source; // @[Error.scala:28:18] wire da_bits_corrupt_opdata; // @[Edges.scala:106:36] assign nodeIn_d_bits_corrupt = da_bits_corrupt; // @[Error.scala:28:18] wire _q_io_deq_ready_T_3; // @[Error.scala:35:46] wire _a_last_T = _q_io_deq_ready_T_3 & _a_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21] wire [26:0] _a_last_beats1_decode_T = 27'hFFF << _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [11:0] _a_last_beats1_decode_T_1 = _a_last_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_last_beats1_decode_T_2 = ~_a_last_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_last_beats1_decode = _a_last_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_last_beats1_opdata_T = _a_q_io_deq_bits_opcode[2]; // @[Decoupled.scala:362:21] wire a_last_beats1_opdata = ~_a_last_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_last_beats1 = a_last_beats1_opdata ? a_last_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_last_counter; // @[Edges.scala:229:27] wire [9:0] _a_last_counter1_T = {1'h0, a_last_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_last_counter1 = _a_last_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_last_first = a_last_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_last_last_T = a_last_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_last_last_T_1 = a_last_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_last = _a_last_last_T \| _a_last_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_last_done = a_last & _a_last_T; // @[Decoupled.scala:51:35] wire [8:0] _a_last_count_T = ~a_last_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_last_count = a_last_beats1 & _a_last_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_last_counter_T = a_last_first ? a_last_beats1 : a_last_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _T = da_ready & da_valid; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << da_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36] assign da_bits_corrupt_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire da_first = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire da_last = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire r_3 = da_last & _T; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = da_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _q_io_deq_ready_T = da_ready & da_last; // @[Edges.scala:232:33] wire _q_io_deq_ready_T_1 = _q_io_deq_ready_T; // @[Error.scala:35:{26,37}] wire _q_io_deq_ready_T_2 = ~a_last; // @[Edges.scala:232:33] assign _q_io_deq_ready_T_3 = _q_io_deq_ready_T_1 \| _q_io_deq_ready_T_2; // @[Error.scala:35:{37,46,49}] wire _da_valid_T = _a_q_io_deq_valid & a_last; // @[Decoupled.scala:362:21] assign _da_valid_T_1 = _da_valid_T; // @[Error.scala:36:{25,35}] assign da_valid = _da_valid_T_1; // @[Error.scala:28:18, :36:35] assign da_bits_opcode = _GEN[_a_q_io_deq_bits_opcode]; // @[Decoupled.scala:362:21] assign da_bits_corrupt = da_bits_corrupt_opdata; // @[Edges.scala:106:36] always @(posedge clock) begin // @[Error.scala:21:9] if (reset) begin // @[Error.scala:21:9] a_last_counter <= 9'h0; // @[Edges.scala:229:27] r_counter <= 9'h0; // @[Edges.scala:229:27] end else begin // @[Error.scala:21:9] if (_a_last_T) // @[Decoupled.scala:51:35] a_last_counter <= _a_last_counter_T; // @[Edges.scala:229:27, :236:21] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] end always @(posedge) TLMonitor_19 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a14d64s9k1z4u a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (_q_io_deq_ready_T_3), // @[Error.scala:35:46] .io_deq_valid (_a_q_io_deq_valid), .io_deq_bits_opcode (_a_q_io_deq_bits_opcode), .io_deq_bits_size (_a_q_io_deq_bits_size), .io_deq_bits_source (da_bits_source) ); // @[Decoupled.scala:362:21] assign da_bits_size = _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Error.scala:21:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Error.scala:21:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Error.scala:21:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Error.scala:21:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Error.scala:21:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Error.scala:21:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_16( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1502 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1502; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1502; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1575 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1575; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1428 = _T_1502 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1428 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1428 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1428 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1428 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1428 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1474 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1474 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1443 = _T_1575 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1443 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1443 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1443 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1546 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1546 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1528 = _T_1575 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1528 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1528 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1528 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File CustomCSRs.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import org.chipsalliance.cde.config.Parameters case class CustomCSR(id: Int, mask: BigInt, init: Option[BigInt]) object CustomCSR { def constant(id: Int, value: BigInt): CustomCSR = CustomCSR(id, BigInt(0), Some(value)) } class CustomCSRIO(implicit p: Parameters) extends CoreBundle { val ren = Output(Bool()) // set by CSRFile, indicates an instruction is reading the CSR val wen = Output(Bool()) // set by CSRFile, indicates an instruction is writing the CSR val wdata = Output(UInt(xLen.W)) // wdata provided by instruction writing CSR val value = Output(UInt(xLen.W)) // current value of CSR in CSRFile val stall = Input(Bool()) // reads and writes to this CSR should stall (must be bounded) val set = Input(Bool()) // set/sdata enables external agents to set the value of this CSR val sdata = Input(UInt(xLen.W)) } class CustomCSRs(implicit p: Parameters) extends CoreBundle { // Not all cores have these CSRs, but those that do should follow the same // numbering conventions. So we list them here but default them to None. protected def bpmCSRId = 0x7c0 protected def bpmCSR: Option[CustomCSR] = None protected def chickenCSRId = 0x7c1 protected def chickenCSR: Option[CustomCSR] = None // If you override this, you'll want to concatenate super.decls def decls: Seq[CustomCSR] = bpmCSR.toSeq ++ chickenCSR val csrs = Vec(decls.size, new CustomCSRIO) def flushBTB = getOrElse(bpmCSR, _.wen, false.B) def bpmStatic = getOrElse(bpmCSR, _.value(0), false.B) def disableDCacheClockGate = getOrElse(chickenCSR, _.value(0), false.B) def disableICacheClockGate = getOrElse(chickenCSR, _.value(1), false.B) def disableCoreClockGate = getOrElse(chickenCSR, _.value(2), false.B) def disableSpeculativeICacheRefill = getOrElse(chickenCSR, _.value(3), false.B) def suppressCorruptOnGrantData = getOrElse(chickenCSR, _.value(9), false.B) protected def getByIdOrElse[T](id: Int, f: CustomCSRIO => T, alt: T): T = { val idx = decls.indexWhere(_.id == id) if (idx < 0) alt else f(csrs(idx)) } protected def getOrElse[T](csr: Option[CustomCSR], f: CustomCSRIO => T, alt: T): T = csr.map(c => getByIdOrElse(c.id, f, alt)).getOrElse(alt) } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File Events.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.log2Ceil import freechips.rocketchip.util._ import freechips.rocketchip.util.property class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bool)]) { def size = events.size val hits = WireDefault(VecInit(Seq.fill(size)(false.B))) def check(mask: UInt) = { hits := events.map(_._2()) gate(mask, hits.asUInt) } def dump(): Unit = { for (((name, _), i) <- events.zipWithIndex) when (check(1.U << i)) { printf(s"Event $name\n") } } def withCovers: Unit = { events.zipWithIndex.foreach { case ((name, func), i) => property.cover(gate((1.U << i), (func() << i)), name) } } } class EventSets(val eventSets: Seq[EventSet]) { def maskEventSelector(eventSel: UInt): UInt = { // allow full associativity between counters and event sets (for now?) val setMask = (BigInt(1) << eventSetIdBits) - 1 val maskMask = ((BigInt(1) << eventSets.map(_.size).max) - 1) << maxEventSetIdBits eventSel & (setMask \| maskMask).U } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } def evaluate(eventSel: UInt): Bool = { val (set, mask) = decode(eventSel) val sets = for (e <- eventSets) yield { require(e.hits.getWidth <= mask.getWidth, s"too many events ${e.hits.getWidth} wider than mask ${mask.getWidth}") e check mask } sets(set) } def cover() = eventSets.foreach { _.withCovers } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSetIdBits <= maxEventSetIdBits) } class SuperscalarEventSets(val eventSets: Seq[(Seq[EventSet], (UInt, UInt) => UInt)]) { def evaluate(eventSel: UInt): UInt = { val (set, mask) = decode(eventSel) val sets = for ((sets, reducer) <- eventSets) yield { sets.map { set => require(set.hits.getWidth <= mask.getWidth, s"too many events ${set.hits.getWidth} wider than mask ${mask.getWidth}") set.check(mask) }.reduce(reducer) } val zeroPadded = sets.padTo(1 << eventSetIdBits, 0.U) zeroPadded(set) } def toScalarEventSets: EventSets = new EventSets(eventSets.map(_._1.head)) def cover(): Unit = { eventSets.foreach(_._1.foreach(_.withCovers)) } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSets.forall(s => s._1.forall(_.size == s._1.head.size))) require(eventSetIdBits <= maxEventSetIdBits) } File RocketCore.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.withClock import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ArrayBuffer case class RocketCoreParams( xLen: Int = 64, pgLevels: Int = 3, // sv39 default bootFreqHz: BigInt = 0, useVM: Boolean = true, useUser: Boolean = false, useSupervisor: Boolean = false, useHypervisor: Boolean = false, useDebug: Boolean = true, useAtomics: Boolean = true, useAtomicsOnlyForIO: Boolean = false, useCompressed: Boolean = true, useRVE: Boolean = false, useConditionalZero: Boolean = false, useZba: Boolean = false, useZbb: Boolean = false, useZbs: Boolean = false, nLocalInterrupts: Int = 0, useNMI: Boolean = false, nBreakpoints: Int = 1, useBPWatch: Boolean = false, mcontextWidth: Int = 0, scontextWidth: Int = 0, nPMPs: Int = 8, nPerfCounters: Int = 0, haveBasicCounters: Boolean = true, haveCFlush: Boolean = false, misaWritable: Boolean = true, nL2TLBEntries: Int = 0, nL2TLBWays: Int = 1, nPTECacheEntries: Int = 8, mtvecInit: Option[BigInt] = Some(BigInt(0)), mtvecWritable: Boolean = true, fastLoadWord: Boolean = true, fastLoadByte: Boolean = false, branchPredictionModeCSR: Boolean = false, clockGate: Boolean = false, mvendorid: Int = 0, // 0 means non-commercial implementation mimpid: Int = 0x20181004, // release date in BCD mulDiv: Option[MulDivParams] = Some(MulDivParams()), fpu: Option[FPUParams] = Some(FPUParams()), debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB haveCease: Boolean = true, // non-standard CEASE instruction haveSimTimeout: Boolean = true, // add plusarg for simulation timeout vector: Option[RocketCoreVectorParams] = None ) extends CoreParams { val lgPauseCycles = 5 val haveFSDirty = false val pmpGranularity: Int = if (useHypervisor) 4096 else 4 val fetchWidth: Int = if (useCompressed) 2 else 1 // fetchWidth doubled, but coreInstBytes halved, for RVC: val decodeWidth: Int = fetchWidth / (if (useCompressed) 2 else 1) val retireWidth: Int = 1 val instBits: Int = if (useCompressed) 16 else 32 val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace override val useVector = vector.isDefined override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false) override def vLen = vector.map(_.vLen).getOrElse(0) override def eLen = vector.map(_.eLen).getOrElse(0) override def vfLen = vector.map(_.vfLen).getOrElse(0) override def vfh = vector.map(_.vfh).getOrElse(false) override def vExts = vector.map(_.vExts).getOrElse(Nil) override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0) override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32) override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs } trait HasRocketCoreParameters extends HasCoreParameters { lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams] val fastLoadWord = rocketParams.fastLoadWord val fastLoadByte = rocketParams.fastLoadByte val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this require(!fastLoadByte \|\| fastLoadWord) require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty") } class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters { override def bpmCSR = { rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0)))) } private def haveDCache = tileParams.dcache.get.scratch.isEmpty override def chickenCSR = { val mask = BigInt( tileParams.dcache.get.clockGate.toInt << 0 \| rocketParams.clockGate.toInt << 1 \| rocketParams.clockGate.toInt << 2 \| 1 << 3 \| // disableSpeculativeICacheRefill haveDCache.toInt << 9 \| // suppressCorruptOnGrantData tileParams.icache.get.prefetch.toInt << 17 ) Some(CustomCSR(chickenCSRId, mask, Some(mask))) } def disableICachePrefetch = getOrElse(chickenCSR, _.value(17), true.B) def marchid = CustomCSR.constant(CSRs.marchid, BigInt(1)) def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid)) // mimpid encodes a release version in the form of a BCD-encoded datestamp. def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid)) override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid } class CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) { val buserror = Option.when(hasBeu)(Bool()) } trait HasRocketCoreIO extends HasRocketCoreParameters { implicit val p: Parameters def nTotalRoCCCSRs: Int val io = IO(new CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val reset_vector = Input(UInt(resetVectorLen.W)) val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParams].beuAddr.isDefined)) val imem = new FrontendIO val dmem = new HellaCacheIO val ptw = Flipped(new DatapathPTWIO()) val fpu = Flipped(new FPUCoreIO()) val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs)) val trace = Output(new TraceBundle) val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth))) val cease = Output(Bool()) val wfi = Output(Bool()) val traceStall = Input(Bool()) val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None }) } class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) with HasRocketCoreParameters with HasRocketCoreIO { def nTotalRoCCCSRs = tile.roccCSRs.flatten.size import ALU._ val clock_en_reg = RegInit(true.B) val long_latency_stall = Reg(Bool()) val id_reg_pause = Reg(Bool()) val imem_might_request_reg = Reg(Bool()) val clock_en = WireDefault(true.B) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "rocket_clock_gate") class RocketImpl { // entering gated-clock domain // performance counters def pipelineIDToWB[T <: Data](x: T): T = RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid) val perfEvents = new EventSets(Seq( new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq( ("exception", () => false.B), ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp), ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp), ("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) \|\| id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))), ("system", () => id_ctrl.csr =/= CSR.N), ("arith", () => id_ctrl.wxd && !(id_ctrl.jal \|\| id_ctrl.jalr \|\| id_ctrl.mem \|\| id_ctrl.fp \|\| id_ctrl.mul \|\| id_ctrl.div \|\| id_ctrl.csr =/= CSR.N)), ("branch", () => id_ctrl.branch), ("jal", () => id_ctrl.jal), ("jalr", () => id_ctrl.jalr)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV), ("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV))) ++ (if (!usingFPU) Seq() else Seq( ("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen), ("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen), ("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23), ("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3), ("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3), ("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div \|\| io.fpu.dec.sqrt)), ("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst \|\| io.fpu.dec.fma \|\| io.fpu.dec.div \|\| io.fpu.dec.sqrt))))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("load-use interlock", () => id_ex_hazard && ex_ctrl.mem \|\| id_mem_hazard && mem_ctrl.mem \|\| id_wb_hazard && wb_ctrl.mem), ("long-latency interlock", () => id_sboard_hazard), ("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N \|\| id_mem_hazard && mem_ctrl.csr =/= CSR.N \|\| id_wb_hazard && wb_ctrl.csr =/= CSR.N), ("I$ blocked", () => icache_blocked), ("D$ blocked", () => id_ctrl.mem && dcache_blocked), ("branch misprediction", () => take_pc_mem && mem_direction_misprediction), ("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked), ("flush", () => wb_reg_flush_pipe), ("replay", () => replay_wb)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul \|\| ex_ctrl.div) \|\| id_mem_hazard && (mem_ctrl.mul \|\| mem_ctrl.div) \|\| id_wb_hazard && wb_ctrl.div))) ++ (if (!usingFPU) Seq() else Seq( ("fp interlock", () => id_ex_hazard && ex_ctrl.fp \|\| id_mem_hazard && mem_ctrl.fp \|\| id_wb_hazard && wb_ctrl.fp \|\| id_ctrl.fp && id_stall_fpu)))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("I$ miss", () => io.imem.perf.acquire), ("D$ miss", () => io.dmem.perf.acquire), ("D$ release", () => io.dmem.perf.release), ("ITLB miss", () => io.imem.perf.tlbMiss), ("DTLB miss", () => io.dmem.perf.tlbMiss), ("L2 TLB miss", () => io.ptw.perf.l2miss))))) val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen val decode_table = { (if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++: (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: (if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++: (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++: (if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++: (usingRoCC.option(new RoCCDecode)) ++: (if (xLen == 32) new I32Decode else new I64Decode) +: (usingVM.option(new SVMDecode)) ++: (usingSupervisor.option(new SDecode)) ++: (usingHypervisor.option(new HypervisorDecode)) ++: ((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++: (usingDebug.option(new DebugDecode)) ++: (usingNMI.option(new NMIDecode)) ++: (usingConditionalZero.option(new ConditionalZeroDecode)) ++: Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++: coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++: rocketParams.haveCease.option(new CeaseDecode) ++: usingVector.option(new VCFGDecode) ++: (if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++: (if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++: coreParams.useZbs.option(new ZbsDecode) ++: Seq(new IDecode) } flatMap(_.table) val ex_ctrl = Reg(new IntCtrlSigs) val mem_ctrl = Reg(new IntCtrlSigs) val wb_ctrl = Reg(new IntCtrlSigs) val ex_reg_xcpt_interrupt = Reg(Bool()) val ex_reg_valid = Reg(Bool()) val ex_reg_rvc = Reg(Bool()) val ex_reg_btb_resp = Reg(new BTBResp) val ex_reg_xcpt = Reg(Bool()) val ex_reg_flush_pipe = Reg(Bool()) val ex_reg_load_use = Reg(Bool()) val ex_reg_cause = Reg(UInt()) val ex_reg_replay = Reg(Bool()) val ex_reg_pc = Reg(UInt()) val ex_reg_mem_size = Reg(UInt()) val ex_reg_hls = Reg(Bool()) val ex_reg_inst = Reg(Bits()) val ex_reg_raw_inst = Reg(UInt()) val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val ex_reg_set_vconfig = Reg(Bool()) val mem_reg_xcpt_interrupt = Reg(Bool()) val mem_reg_valid = Reg(Bool()) val mem_reg_rvc = Reg(Bool()) val mem_reg_btb_resp = Reg(new BTBResp) val mem_reg_xcpt = Reg(Bool()) val mem_reg_replay = Reg(Bool()) val mem_reg_flush_pipe = Reg(Bool()) val mem_reg_cause = Reg(UInt()) val mem_reg_slow_bypass = Reg(Bool()) val mem_reg_load = Reg(Bool()) val mem_reg_store = Reg(Bool()) val mem_reg_set_vconfig = Reg(Bool()) val mem_reg_sfence = Reg(Bool()) val mem_reg_pc = Reg(UInt()) val mem_reg_inst = Reg(Bits()) val mem_reg_mem_size = Reg(UInt()) val mem_reg_hls_or_dv = Reg(Bool()) val mem_reg_raw_inst = Reg(UInt()) val mem_reg_wdata = Reg(Bits()) val mem_reg_rs2 = Reg(Bits()) val mem_br_taken = Reg(Bool()) val take_pc_mem = Wire(Bool()) val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val wb_reg_valid = Reg(Bool()) val wb_reg_xcpt = Reg(Bool()) val wb_reg_replay = Reg(Bool()) val wb_reg_flush_pipe = Reg(Bool()) val wb_reg_cause = Reg(UInt()) val wb_reg_set_vconfig = Reg(Bool()) val wb_reg_sfence = Reg(Bool()) val wb_reg_pc = Reg(UInt()) val wb_reg_mem_size = Reg(UInt()) val wb_reg_hls_or_dv = Reg(Bool()) val wb_reg_hfence_v = Reg(Bool()) val wb_reg_hfence_g = Reg(Bool()) val wb_reg_inst = Reg(Bits()) val wb_reg_raw_inst = Reg(UInt()) val wb_reg_wdata = Reg(Bits()) val wb_reg_rs2 = Reg(Bits()) val take_pc_wb = Wire(Bool()) val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val take_pc_mem_wb = take_pc_wb \|\| take_pc_mem val take_pc = take_pc_mem_wb // decode stage val ibuf = Module(new IBuf) val id_expanded_inst = ibuf.io.inst.map(_.bits.inst) val id_raw_inst = ibuf.io.inst.map(_.bits.raw) val id_inst = id_expanded_inst.map(_.bits) ibuf.io.imem <> io.imem.resp ibuf.io.kill := take_pc require(decodeWidth == 1 / TODO / && retireWidth == decodeWidth) require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point") require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor") val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table) val lgNXRegs = if (coreParams.useRVE) 4 else 5 val regAddrMask = (1 << lgNXRegs) - 1 def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0)) val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3) val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2) val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1) val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd) val id_load_use = Wire(Bool()) val id_reg_fence = RegInit(false.B) val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2) val id_raddr = IndexedSeq(id_raddr1, id_raddr2) val rf = new RegFile(regAddrMask, xLen) val id_rs = id_raddr.map(rf.read _) val ctrl_killd = Wire(Bool()) val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined)) val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W) val id_system_insn = id_ctrl.csr === CSR.I val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr)) val id_csr_flush = id_system_insn \|\| (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush) val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B id_ctrl.vec := false.B if (usingVector) { val v_decode = rocketParams.vector.get.decoder(p) v_decode.io.inst := id_inst(0) v_decode.io.vconfig := csr.io.vector.get.vconfig when (v_decode.io.legal) { id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill id_ctrl.fp := v_decode.io.fp id_ctrl.rocc := false.B id_ctrl.branch := false.B id_ctrl.jal := false.B id_ctrl.jalr := false.B id_ctrl.rxs2 := v_decode.io.read_rs2 id_ctrl.rxs1 := v_decode.io.read_rs1 id_ctrl.mem := false.B id_ctrl.rfs1 := v_decode.io.read_frs1 id_ctrl.rfs2 := false.B id_ctrl.rfs3 := false.B id_ctrl.wfd := v_decode.io.write_frd id_ctrl.mul := false.B id_ctrl.div := false.B id_ctrl.wxd := v_decode.io.write_rd id_ctrl.csr := CSR.N id_ctrl.fence_i := false.B id_ctrl.fence := false.B id_ctrl.amo := false.B id_ctrl.dp := false.B id_ctrl.vec := true.B } } val id_illegal_insn = !id_ctrl.legal \|\| (id_ctrl.mul \|\| id_ctrl.div) && !csr.io.status.isa('m'-'a') \|\| id_ctrl.amo && !csr.io.status.isa('a'-'a') \|\| id_ctrl.fp && (csr.io.decode(0).fp_illegal \|\| (io.fpu.illegal_rm && !id_ctrl.vec)) \|\| (id_ctrl.vec) && (csr.io.decode(0).vector_illegal \|\| csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) \|\| id_ctrl.dp && !csr.io.status.isa('d'-'a') \|\| ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') \|\| id_raddr2_illegal && id_ctrl.rxs2 \|\| id_raddr1_illegal && id_ctrl.rxs1 \|\| id_waddr_illegal && id_ctrl.wxd \|\| id_ctrl.rocc && csr.io.decode(0).rocc_illegal \|\| id_csr_en && (csr.io.decode(0).read_illegal \|\| !id_csr_ren && csr.io.decode(0).write_illegal) \|\| !ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal) val id_virtual_insn = id_ctrl.legal && ((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) \|\| (!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal)) // stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE) val id_amo_aq = id_inst(0)(26) val id_amo_rl = id_inst(0)(25) val id_fence_pred = id_inst(0)(27,24) val id_fence_succ = id_inst(0)(23,20) val id_fence_next = id_ctrl.fence \|\| id_ctrl.amo && id_amo_aq val id_mem_busy = !io.dmem.ordered \|\| io.dmem.req.valid when (!id_mem_busy) { id_reg_fence := false.B } val id_rocc_busy = usingRoCC.B && (io.rocc.busy \|\| ex_reg_valid && ex_ctrl.rocc \|\| mem_reg_valid && mem_ctrl.rocc \|\| wb_reg_valid && wb_ctrl.rocc) val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren val id_vec_busy = io.vector.map(v => v.backend_busy \|\| v.trap_check_busy).getOrElse(false.B) val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence \|\| id_csr_rocc_write) \|\| id_vec_busy && id_ctrl.fence \|\| id_mem_busy && (id_ctrl.amo && id_amo_rl \|\| id_ctrl.fence_i \|\| id_reg_fence && (id_ctrl.mem \|\| id_ctrl.rocc))) val bpu = Module(new BreakpointUnit(nBreakpoints)) bpu.io.status := csr.io.status bpu.io.bp := csr.io.bp bpu.io.pc := ibuf.io.pc bpu.io.ea := mem_reg_wdata bpu.io.mcontext := csr.io.mcontext bpu.io.scontext := csr.io.scontext val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0 val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1 val (id_xcpt, id_cause) = checkExceptions(List( (csr.io.interrupt, csr.io.interrupt_cause), (bpu.io.debug_if, CSR.debugTriggerCause.U), (bpu.io.xcpt_if, Causes.breakpoint.U), (id_xcpt0.pf.inst, Causes.fetch_page_fault.U), (id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt0.ae.inst, Causes.fetch_access.U), (id_xcpt1.pf.inst, Causes.fetch_page_fault.U), (id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt1.ae.inst, Causes.fetch_access.U), (id_virtual_insn, Causes.virtual_instruction.U), (id_illegal_insn, Causes.illegal_instruction.U))) val idCoverCauses = List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.fetch_access, "FETCH_ACCESS"), (Causes.illegal_instruction, "ILLEGAL_INSTRUCTION") ) ++ (if (usingVM) List( (Causes.fetch_page_fault, "FETCH_PAGE_FAULT") ) else Nil) coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses) val dcache_bypass_data = if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0) else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0) else wb_reg_wdata // detect bypass opportunities val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U val bypass_sources = IndexedSeq( (true.B, 0.U, 0.U), // treat reading x0 as a bypass (ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata), (mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata), (mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data)) val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr)) // execute stage val bypass_mux = bypass_sources.map(_._3) val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool())) val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W))) val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt())) val ex_rs = for (i <- 0 until id_raddr.size) yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i))) val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst) val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13) val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq( A1_RS1 -> ex_rs(0).asSInt, A1_PC -> ex_reg_pc.asSInt, A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S) )) val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq( A2_RS2 -> ex_rs(1).asSInt, A2_IMM -> ex_imm, A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S), ) ++ (if (coreParams.useZbs) Seq( A2_RS2OH -> ex_op2_oh, A2_IMMOH -> ex_op2_oh, ) else Nil)) val (ex_new_vl, ex_new_vconfig) = if (usingVector) { val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq( ex_reg_inst(31,30).andR -> ex_reg_inst(29,20), !ex_reg_inst(31) -> ex_reg_inst(30,20)))) val ex_avl = Mux(ex_ctrl.rxs1, Mux(ex_reg_inst(19,15) === 0.U, Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax), ex_rs(0) ), ex_reg_inst(19,15)) val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B) val ex_new_vconfig = Wire(new VConfig) ex_new_vconfig.vtype := ex_new_vtype ex_new_vconfig.vl := ex_new_vl (Some(ex_new_vl), Some(ex_new_vconfig)) } else { (None, None) } val alu = Module(new ALU) alu.io.dw := ex_ctrl.alu_dw alu.io.fn := ex_ctrl.alu_fn alu.io.in2 := ex_op2.asUInt alu.io.in1 := ex_op1.asUInt // multiplier and divider val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen)) div.io.req.valid := ex_reg_valid && ex_ctrl.div div.io.req.bits.dw := ex_ctrl.alu_dw div.io.req.bits.fn := ex_ctrl.alu_fn div.io.req.bits.in1 := ex_rs(0) div.io.req.bits.in2 := ex_rs(1) div.io.req.bits.tag := ex_waddr val mul = pipelinedMul.option { val m = Module(new PipelinedMultiplier(xLen, 2)) m.io.req.valid := ex_reg_valid && ex_ctrl.mul m.io.req.bits := div.io.req.bits m } ex_reg_valid := !ctrl_killd ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay ex_reg_xcpt := !ctrl_killd && id_xcpt ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt when (!ctrl_killd) { ex_ctrl := id_ctrl ex_reg_rvc := ibuf.io.inst(0).bits.rvc ex_ctrl.csr := id_csr when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B } when (id_fence_next) { id_reg_fence := true.B } when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr ex_ctrl.alu_fn := FN_ADD ex_ctrl.alu_dw := DW_XPR ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction ex_ctrl.sel_alu2 := A2_ZERO when (id_xcpt1.asUInt.orR) { // badaddr := PC+2 ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_SIZE ex_reg_rvc := true.B } when (bpu.io.xcpt_if \|\| id_xcpt0.asUInt.orR) { // badaddr := PC ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_ZERO } } ex_reg_flush_pipe := id_ctrl.fence_i \|\| id_csr_flush ex_reg_load_use := id_load_use ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX) ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12)) when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) { ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U) } when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) { ex_ctrl.mem_cmd := M_HFENCEV } if (tile.dcache.flushOnFenceI) { when (id_ctrl.fence_i) { ex_reg_mem_size := 0.U } } for (i <- 0 until id_raddr.size) { val do_bypass = id_bypass_src(i).reduce(_\|\|_) val bypass_src = PriorityEncoder(id_bypass_src(i)) ex_reg_rs_bypass(i) := do_bypass ex_reg_rs_lsb(i) := bypass_src when (id_ren(i) && !do_bypass) { ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size) } } when (id_illegal_insn \|\| id_virtual_insn) { val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0)) ex_reg_rs_bypass(0) := false.B ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size) } } when (!ctrl_killd \|\| csr.io.interrupt \|\| ibuf.io.inst(0).bits.replay) { ex_reg_cause := id_cause ex_reg_inst := id_inst(0) ex_reg_raw_inst := id_raw_inst(0) ex_reg_pc := ibuf.io.pc ex_reg_btb_resp := ibuf.io.btb_resp ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) } ex_reg_set_vconfig := id_set_vconfig && !id_xcpt } // replay inst in ex stage? val ex_pc_valid = ex_reg_valid \|\| ex_reg_replay \|\| ex_reg_xcpt_interrupt val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready \|\| ex_ctrl.div && !div.io.req.ready \|\| ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B) val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use val replay_ex = ex_reg_replay \|\| (ex_reg_valid && (replay_ex_structural \|\| replay_ex_load_use)) val ctrl_killx = take_pc_mem_wb \|\| replay_ex \|\| !ex_reg_valid // detect 2-cycle load-use delay for LB/LH/SC val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC \|\| ex_reg_mem_size < 2.U val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE \|\| ex_ctrl.mem_cmd === M_HFENCEV \|\| ex_ctrl.mem_cmd === M_HFENCEG) val (ex_xcpt, ex_cause) = checkExceptions(List( (ex_reg_xcpt_interrupt \|\| ex_reg_xcpt, ex_reg_cause))) val exCoverCauses = idCoverCauses coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses) // memory stage val mem_pc_valid = mem_reg_valid \|\| mem_reg_replay \|\| mem_reg_xcpt_interrupt val mem_br_target = mem_reg_pc.asSInt + Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst), Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), Mux(mem_reg_rvc, 2.S, 4.S))) val mem_npc = (Mux(mem_ctrl.jalr \|\| mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt val mem_wrong_npc = Mux(ex_pc_valid, mem_npc =/= ex_reg_pc, Mux(ibuf.io.inst(0).valid \|\| ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B)) val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt val mem_cfi = mem_ctrl.branch \|\| mem_ctrl.jalr \|\| mem_ctrl.jal val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) \|\| mem_ctrl.jalr \|\| mem_ctrl.jal val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken) val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction \|\| mem_reg_sfence) mem_reg_valid := !ctrl_killx mem_reg_replay := !take_pc_mem_wb && replay_ex mem_reg_xcpt := !ctrl_killx && ex_xcpt mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt // on pipeline flushes, cause mem_npc to hold the sequential npc, which // will drive the W-stage npc mux when (mem_reg_valid && mem_reg_flush_pipe) { mem_reg_sfence := false.B }.elsewhen (ex_pc_valid) { mem_ctrl := ex_ctrl mem_reg_rvc := ex_reg_rvc mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd) mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd) mem_reg_sfence := ex_sfence mem_reg_btb_resp := ex_reg_btb_resp mem_reg_flush_pipe := ex_reg_flush_pipe mem_reg_slow_bypass := ex_slow_bypass mem_reg_wphit := ex_reg_wphit mem_reg_set_vconfig := ex_reg_set_vconfig mem_reg_cause := ex_cause mem_reg_inst := ex_reg_inst mem_reg_raw_inst := ex_reg_raw_inst mem_reg_mem_size := ex_reg_mem_size mem_reg_hls_or_dv := io.dmem.req.bits.dv mem_reg_pc := ex_reg_pc // IDecode ensured they are 1H mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out) mem_br_taken := alu.io.cmp_out when (ex_ctrl.rxs2 && (ex_ctrl.mem \|\| ex_ctrl.rocc \|\| ex_sfence)) { val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size) mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data } if (usingVector) { when (ex_reg_set_vconfig) { mem_reg_rs2 := ex_new_vconfig.get.asUInt } } when (ex_ctrl.jalr && csr.io.status.debug) { // flush I$ on D-mode JALR to effect uncached fetch without D$ flush mem_ctrl.fence_i := true.B mem_reg_flush_pipe := true.B } } val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) \|\| (mem_reg_store && bpu.io.xcpt_st) val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) \|\| (mem_reg_store && bpu.io.debug_st) val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List( (mem_debug_breakpoint, CSR.debugTriggerCause.U), (mem_breakpoint, Causes.breakpoint.U))) val (mem_xcpt, mem_cause) = checkExceptions(List( (mem_reg_xcpt_interrupt \|\| mem_reg_xcpt, mem_reg_cause), (mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U), (mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause))) val memCoverCauses = (exCoverCauses ++ List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.misaligned_fetch, "MISALIGNED_FETCH") )).distinct coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses) val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B) val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B) val replay_mem = dcache_kill_mem \|\| mem_reg_replay \|\| fpu_kill_mem \|\| vec_kill_mem \|\| vec_kill_all val killm_common = dcache_kill_mem \|\| take_pc_wb \|\| mem_reg_xcpt \|\| !mem_reg_valid div.io.kill := killm_common && RegNext(div.io.req.fire) val ctrl_killm = killm_common \|\| mem_xcpt \|\| fpu_kill_mem \|\| vec_kill_mem // writeback stage wb_reg_valid := !ctrl_killm wb_reg_replay := replay_mem && !take_pc_wb wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B) wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe when (mem_pc_valid) { wb_ctrl := mem_ctrl wb_reg_sfence := mem_reg_sfence wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata) when (mem_ctrl.rocc \|\| mem_reg_sfence \|\| mem_reg_set_vconfig) { wb_reg_rs2 := mem_reg_rs2 } wb_reg_cause := mem_cause wb_reg_inst := mem_reg_inst wb_reg_raw_inst := mem_reg_raw_inst wb_reg_mem_size := mem_reg_mem_size wb_reg_hls_or_dv := mem_reg_hls_or_dv wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG wb_reg_pc := mem_reg_pc wb_reg_wphit := mem_reg_wphit \| bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) \|\| (bpw.wvalid(0) && mem_reg_store) } wb_reg_set_vconfig := mem_reg_set_vconfig } val (wb_xcpt, wb_cause) = checkExceptions(List( (wb_reg_xcpt, wb_reg_cause), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U) )) val wbCoverCauses = List( (Causes.misaligned_store, "MISALIGNED_STORE"), (Causes.misaligned_load, "MISALIGNED_LOAD"), (Causes.store_access, "STORE_ACCESS"), (Causes.load_access, "LOAD_ACCESS") ) ++ (if(usingVM) List( (Causes.store_page_fault, "STORE_PAGE_FAULT"), (Causes.load_page_fault, "LOAD_PAGE_FAULT") ) else Nil) ++ (if (usingHypervisor) List( (Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"), (Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT"), ) else Nil) coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses) val wb_pc_valid = wb_reg_valid \|\| wb_reg_replay \|\| wb_reg_xcpt val wb_wxd = wb_reg_valid && wb_ctrl.wxd val wb_set_sboard = wb_ctrl.div \|\| wb_dcache_miss \|\| wb_ctrl.rocc \|\| wb_ctrl.vec val replay_wb_common = io.dmem.s2_nack \|\| wb_reg_replay val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B) val replay_wb = replay_wb_common \|\| replay_wb_rocc \|\| replay_wb_csr \|\| replay_wb_vec take_pc_wb := replay_wb \|\| wb_xcpt \|\| csr.io.eret \|\| wb_reg_flush_pipe // writeback arbitration val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1) val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay class LLWB extends Bundle { val data = UInt(xLen.W) val tag = UInt(5.W) } val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec ll_arb.io.in.foreach(_.valid := false.B) ll_arb.io.in.foreach(_.bits := DontCare) val ll_wdata = WireInit(ll_arb.io.out.bits.data) val ll_waddr = WireInit(ll_arb.io.out.bits.tag) val ll_wen = WireInit(ll_arb.io.out.fire) ll_arb.io.out.ready := !wb_wxd div.io.resp.ready := ll_arb.io.in(0).ready ll_arb.io.in(0).valid := div.io.resp.valid ll_arb.io.in(0).bits.data := div.io.resp.bits.data ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag if (usingRoCC) { io.rocc.resp.ready := ll_arb.io.in(1).ready ll_arb.io.in(1).valid := io.rocc.resp.valid ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd } else { // tie off RoCC io.rocc.resp.ready := false.B io.rocc.mem.req.ready := false.B } io.vector.map { v => v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready) ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp ll_arb.io.in(2).bits.data := v.resp.bits.data ll_arb.io.in(2).bits.tag := v.resp.bits.rd } // Dont care mem since not all RoCC need accessing memory io.rocc.mem := DontCare when (dmem_resp_replay && dmem_resp_xpu) { ll_arb.io.out.ready := false.B ll_waddr := dmem_resp_waddr ll_wen := true.B } val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt val wb_wen = wb_valid && wb_ctrl.wxd val rf_wen = wb_wen \|\| ll_wen val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr) val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0), Mux(ll_wen, ll_wdata, Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata, Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata), wb_reg_wdata)))) when (rf_wen) { rf.write(rf_waddr, rf_wdata) } // hook up control/status regfile csr.io.ungated_clock := clock csr.io.decode(0).inst := id_inst(0) csr.io.exception := wb_xcpt csr.io.cause := wb_cause csr.io.retire := wb_valid csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst) csr.io.interrupts := io.interrupts csr.io.hartid := io.hartid io.fpu.fcsr_rm := csr.io.fcsr_rm val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W)) val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B) csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid \| vector_fcsr_flags_valid csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) \| (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid)) io.fpu.time := csr.io.time(31,0) io.fpu.hartid := io.hartid csr.io.rocc_interrupt := io.rocc.interrupt csr.io.pc := wb_reg_pc val tval_dmem_addr = !wb_reg_xcpt val tval_any_addr = tval_dmem_addr \|\| wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U) val tval_inst = wb_reg_cause === Causes.illegal_instruction.U val tval_valid = wb_xcpt && (tval_any_addr \|\| tval_inst) csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v \|\| tval_dmem_addr && wb_reg_hls_or_dv) csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U) val (htval, mhtinst_read_pseudo) = { val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U) assert(!htval_valid_imem \|\| io.imem.gpa.valid) val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U) val htval = (htval_dmem \| htval_imem) >> hypervisorExtraAddrBits // read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) \|\| (io.dmem.s2_gpa_is_pte && htval_valid_dmem) (htval, mhtinst_read_pseudo) } csr.io.vector.foreach { v => v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig) v.set_vs_dirty := wb_valid && wb_ctrl.vec v.set_vstart.valid := wb_valid && wb_reg_set_vconfig v.set_vstart.bits := 0.U } io.vector.foreach { v => when (v.wb.retire \|\| v.wb.xcpt \|\| wb_ctrl.vec) { csr.io.pc := v.wb.pc csr.io.retire := v.wb.retire csr.io.inst(0) := v.wb.inst when (v.wb.xcpt && !wb_reg_xcpt) { wb_xcpt := true.B wb_cause := v.wb.cause csr.io.tval := v.wb.tval } } v.wb.store_pending := io.dmem.store_pending v.wb.vxrm := csr.io.vector.get.vxrm v.wb.frm := csr.io.fcsr_rm csr.io.vector.get.set_vxsat := v.set_vxsat when (v.set_vconfig.valid) { csr.io.vector.get.set_vconfig.valid := true.B csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits } when (v.set_vstart.valid) { csr.io.vector.get.set_vstart.valid := true.B csr.io.vector.get.set_vstart.bits := v.set_vstart.bits } } csr.io.htval := htval csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo io.ptw.ptbr := csr.io.ptbr io.ptw.hgatp := csr.io.hgatp io.ptw.vsatp := csr.io.vsatp (io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs } io.ptw.status := csr.io.status io.ptw.hstatus := csr.io.hstatus io.ptw.gstatus := csr.io.gstatus io.ptw.pmp := csr.io.pmp csr.io.rw.addr := wb_reg_inst(31,20) csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr) csr.io.rw.wdata := wb_reg_wdata io.rocc.csrs <> csr.io.roccCSRs io.trace.time := csr.io.time io.trace.insns := csr.io.trace if (rocketParams.debugROB.isDefined) { val sz = rocketParams.debugROB.get.size if (sz < 1) { // use unsynthesizable ROB val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val should_wb = WireInit((wb_ctrl.wfd \|\| (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception) val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard) val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)) io.vector.foreach { v => when (v.wb.retire) { should_wb := v.wb.rob_should_wb has_wb := false.B wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7)) }} DebugROB.pushTrace(clock, reset, io.hartid, csr_trace_with_wdata, should_wb, has_wb, wb_addr) io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid) DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata) } else { // synthesizable ROB (no FPRs) require(!usingVector, "Synthesizable ROB does not support vector implementations") val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val debug_rob = Module(new HardDebugROB(sz, 32)) debug_rob.io.i_insn := csr_trace_with_wdata debug_rob.io.should_wb := (wb_ctrl.wfd \|\| (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U) debug_rob.io.wb_val := ll_wen debug_rob.io.wb_tag := rf_waddr debug_rob.io.wb_data := rf_wdata io.trace.insns(0) := debug_rob.io.o_insn } } else { io.trace.insns := csr.io.trace } for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) { iobpw.valid(0) := wphit iobpw.action := bp.control.action // tie off bpwatch valids iobpw.rvalid.foreach(_ := false.B) iobpw.wvalid.foreach(_ := false.B) iobpw.ivalid.foreach(_ := false.B) } val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1), (id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2), (id_ctrl.wxd && id_waddr =/= 0.U, id_waddr)) val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1), (io.fpu.dec.ren2, id_raddr2), (io.fpu.dec.ren3, id_raddr3), (io.fpu.dec.wen, id_waddr)) val sboard = new Scoreboard(32, true) sboard.clear(ll_wen, ll_waddr) def id_sboard_clear_bypass(r: UInt) = { // ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r else div.io.resp.fire && div.io.resp.bits.tag === r \|\| dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r } val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd)) sboard.set(wb_set_sboard && wb_wen, wb_waddr) // stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage. val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N \|\| ex_ctrl.jalr \|\| ex_ctrl.mem \|\| ex_ctrl.mul \|\| ex_ctrl.div \|\| ex_ctrl.fp \|\| ex_ctrl.rocc \|\| ex_ctrl.vec val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr) val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr) val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass \|\| fp_data_hazard_ex) // stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage. val mem_mem_cmd_bh = if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass else true.B val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N \|\| mem_ctrl.mem && mem_mem_cmd_bh \|\| mem_ctrl.mul \|\| mem_ctrl.div \|\| mem_ctrl.fp \|\| mem_ctrl.rocc \|\| mem_ctrl.vec val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr) val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr) val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass \|\| fp_data_hazard_mem) id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem val id_vconfig_hazard = id_ctrl.vec && ( (ex_reg_valid && ex_reg_set_vconfig) \|\| (mem_reg_valid && mem_reg_set_vconfig) \|\| (wb_reg_valid && wb_reg_set_vconfig)) // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback. val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr) val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr) val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard \|\| fp_data_hazard_wb) val id_stall_fpu = if (usingFPU) { val fp_sboard = new Scoreboard(32) fp_sboard.set(((wb_dcache_miss \|\| wb_ctrl.vec) && wb_ctrl.wfd \|\| io.fpu.sboard_set) && wb_valid, wb_waddr) val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B) fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) \|\| v_ll, io.fpu.ll_resp_tag) fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) checkHazards(fp_hazard_targets, fp_sboard.read _) } else false.B val dcache_blocked = { // speculate that a blocked D$ will unblock the cycle after a Grant val blocked = Reg(Bool()) blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked \|\| io.dmem.req.valid \|\| io.dmem.s2_nack) blocked && !io.dmem.perf.grant } val rocc_blocked = Reg(Bool()) rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid \|\| rocc_blocked) val ctrl_stalld = id_ex_hazard \|\| id_mem_hazard \|\| id_wb_hazard \|\| id_sboard_hazard \|\| id_vconfig_hazard \|\| csr.io.singleStep && (ex_reg_valid \|\| mem_reg_valid \|\| wb_reg_valid) \|\| id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy \|\| id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy \|\| id_ctrl.fp && id_stall_fpu \|\| id_ctrl.mem && dcache_blocked \|\| // reduce activity during D$ misses id_ctrl.rocc && rocc_blocked \|\| // reduce activity while RoCC is busy id_ctrl.div && (!(div.io.req.ready \|\| (div.io.resp.valid && !wb_wxd)) \|\| div.io.req.valid) \|\| // reduce odds of replay !clock_en \|\| id_do_fence \|\| csr.io.csr_stall \|\| id_reg_pause \|\| io.traceStall ctrl_killd := !ibuf.io.inst(0).valid \|\| ibuf.io.inst(0).bits.replay \|\| take_pc_mem_wb \|\| ctrl_stalld \|\| csr.io.interrupt io.imem.req.valid := take_pc io.imem.req.bits.speculative := !take_pc_wb io.imem.req.bits.pc := Mux(wb_xcpt \|\| csr.io.eret, csr.io.evec, // exception or [m\|s]ret Mux(replay_wb, wb_reg_pc, // replay mem_npc)) // flush or branch misprediction io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack io.imem.might_request := { imem_might_request_reg := ex_pc_valid \|\| mem_pc_valid \|\| io.ptw.customCSRs.disableICacheClockGate \|\| io.vector.map(_.trap_check_busy).getOrElse(false.B) imem_might_request_reg } io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common) io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence io.imem.sfence.bits.rs1 := wb_reg_mem_size(0) io.imem.sfence.bits.rs2 := wb_reg_mem_size(1) io.imem.sfence.bits.addr := wb_reg_wdata io.imem.sfence.bits.asid := wb_reg_rs2 io.imem.sfence.bits.hv := wb_reg_hfence_v io.imem.sfence.bits.hg := wb_reg_hfence_g io.ptw.sfence := io.imem.sfence ibuf.io.inst(0).ready := !ctrl_stalld io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi \|\| mem_cfi_taken) io.imem.btb_update.bits.isValid := mem_cfi io.imem.btb_update.bits.cfiType := Mux((mem_ctrl.jal \|\| mem_ctrl.jalr) && mem_waddr(0), CFIType.call, Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat("b00?01"), CFIType.ret, Mux(mem_ctrl.jal \|\| mem_ctrl.jalr, CFIType.jump, CFIType.branch))) io.imem.btb_update.bits.target := io.imem.req.bits.pc io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc) io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc \| (coreInstBytesfetchWidth-1).U) io.imem.btb_update.bits.prediction := mem_reg_btb_resp io.imem.btb_update.bits.taken := DontCare io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc io.imem.bht_update.bits.taken := mem_br_taken io.imem.bht_update.bits.mispredict := mem_wrong_npc io.imem.bht_update.bits.branch := mem_ctrl.branch io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht // Connect RAS in Frontend io.imem.ras_update := DontCare io.fpu.valid := !ctrl_killd && id_ctrl.fp io.fpu.killx := ctrl_killx io.fpu.killm := killm_common io.fpu.inst := id_inst(0) io.fpu.fromint_data := ex_rs(0) io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data) io.fpu.ll_resp_type := io.dmem.resp.bits.size io.fpu.ll_resp_tag := dmem_resp_waddr io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U) io.vector.map { v => when (!(dmem_resp_valid && dmem_resp_fpu)) { io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp io.fpu.ll_resp_data := v.resp.bits.data io.fpu.ll_resp_type := v.resp.bits.size io.fpu.ll_resp_tag := v.resp.bits.rd } } io.vector.foreach { v => v.ex.valid := ex_reg_valid && (ex_ctrl.vec \|\| rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx v.ex.inst := ex_reg_inst v.ex.vconfig := csr.io.vector.get.vconfig v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec \|\| wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart) v.ex.rs1 := ex_rs(0) v.ex.rs2 := ex_rs(1) v.ex.pc := ex_reg_pc v.mem.frs1 := io.fpu.store_data v.killm := killm_common v.status := csr.io.status } io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp) require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth) io.dmem.req.bits.tag := ex_dcache_tag io.dmem.req.bits.cmd := ex_ctrl.mem_cmd io.dmem.req.bits.size := ex_reg_mem_size io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14)) io.dmem.req.bits.phys := false.B io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out) io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr) io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv) io.dmem.req.bits.dv := ex_reg_hls \|\| csr.io.status.dv io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) \|\| (!ex_ctrl.fp && ex_waddr === 0.U) io.dmem.req.bits.no_alloc := DontCare io.dmem.req.bits.no_xcpt := DontCare io.dmem.req.bits.data := DontCare io.dmem.req.bits.mask := DontCare io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2)) io.dmem.s1_data.mask := DontCare io.dmem.s1_kill := killm_common \|\| mem_ldst_xcpt \|\| fpu_kill_mem \|\| vec_kill_mem io.dmem.s2_kill := false.B // don't let D$ go to sleep if we're probably going to use it soon io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common io.rocc.exception := wb_xcpt && csr.io.status.xs.orR io.rocc.cmd.bits.status := csr.io.status io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction()) io.rocc.cmd.bits.rs1 := wb_reg_wdata io.rocc.cmd.bits.rs2 := wb_reg_rs2 // gate the clock val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U \|\| csr.io.inhibit_cycle \|\| io.dmem.perf.release \|\| take_pc when (unpause) { id_reg_pause := false.B } io.cease := csr.io.status.cease && !clock_en_reg io.wfi := csr.io.status.wfi if (rocketParams.clockGate) { long_latency_stall := csr.io.csr_stall \|\| io.dmem.perf.blocked \|\| id_reg_pause && !unpause clock_en := clock_en_reg \|\| ex_pc_valid \|\| (!long_latency_stall && io.imem.resp.valid) clock_en_reg := ex_pc_valid \|\| mem_pc_valid \|\| wb_pc_valid \|\| // instruction in flight io.ptw.customCSRs.disableCoreClockGate \|\| // chicken bit !div.io.req.ready \|\| // mul/div in flight usingFPU.B && !io.fpu.fcsr_rdy \|\| // long-latency FPU in flight io.dmem.replay_next \|\| // long-latency load replaying (!long_latency_stall && (ibuf.io.inst(0).valid \|\| io.imem.resp.valid)) // instruction pending assert(!(ex_pc_valid \|\| mem_pc_valid \|\| wb_pc_valid) \|\| clock_en) } // evaluate performance counters val icache_blocked = !(io.imem.resp.valid \|\| RegNext(io.imem.resp.valid)) csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) } val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen)) coreMonitorBundle.clock := clock coreMonitorBundle.reset := reset coreMonitorBundle.hartid := io.hartid coreMonitorBundle.timer := csr.io.time(31,0) coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen) coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard coreMonitorBundle.wrenf := false.B coreMonitorBundle.wrdst := wb_waddr coreMonitorBundle.wrdata := rf_wdata coreMonitorBundle.rd0src := wb_reg_inst(19,15) coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0))) coreMonitorBundle.rd1src := wb_reg_inst(24,20) coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1))) coreMonitorBundle.inst := csr.io.trace(0).insn coreMonitorBundle.excpt := csr.io.trace(0).exception coreMonitorBundle.priv_mode := csr.io.trace(0).priv if (enableCommitLog) { val t = csr.io.trace(0) val rd = wb_waddr val wfd = wb_ctrl.wfd val wxd = wb_ctrl.wxd val has_data = wb_wen && !wb_set_sboard when (t.valid && !t.exception) { when (wfd) { printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+32.U) } .elsewhen (wxd && rd =/= 0.U && has_data) { printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata) } .elsewhen (wxd && rd =/= 0.U && !has_data) { printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd) } .otherwise { printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn) } } when (ll_wen && rf_waddr =/= 0.U) { printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata) } } else { when (csr.io.trace(0).valid) { printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid, coreMonitorBundle.pc, Mux(wb_ctrl.wxd \|\| wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U), Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U), coreMonitorBundle.wrenx, Mux(wb_ctrl.rxs1 \|\| wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U), Mux(wb_ctrl.rxs1 \|\| wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U), Mux(wb_ctrl.rxs2 \|\| wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U), Mux(wb_ctrl.rxs2 \|\| wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U), coreMonitorBundle.inst, coreMonitorBundle.inst) } } // CoreMonitorBundle for late latency writes val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen)) xrfWriteBundle.clock := clock xrfWriteBundle.reset := reset xrfWriteBundle.hartid := io.hartid xrfWriteBundle.timer := csr.io.time(31,0) xrfWriteBundle.valid := false.B xrfWriteBundle.pc := 0.U xrfWriteBundle.wrdst := rf_waddr xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr)) xrfWriteBundle.wrenf := false.B xrfWriteBundle.wrdata := rf_wdata xrfWriteBundle.rd0src := 0.U xrfWriteBundle.rd0val := 0.U xrfWriteBundle.rd1src := 0.U xrfWriteBundle.rd1val := 0.U xrfWriteBundle.inst := 0.U xrfWriteBundle.excpt := false.B xrfWriteBundle.priv_mode := csr.io.trace(0).priv if (rocketParams.haveSimTimeout) PlusArg.timeout( name = "max_core_cycles", docstring = "Kill the emulation after INT rdtime cycles. Off if 0." )(csr.io.time) } // leaving gated-clock domain val rocketImpl = withClock (gated_clock) { new RocketImpl } def checkExceptions(x: Seq[(Bool, UInt)]) = (WireInit(x.map(_._1).reduce(_\|\|_)), WireInit(PriorityMux(x))) def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = { for ((coverCause, label) <- coverCausesLabels) { property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_${label}") } } def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) = targets.map(h => h._1 && cond(h._2)).reduce(_\|\|_) def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else { // efficient means to compress 64-bit VA into vaddrBits+1 bits // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) val b = vaddrBitsExtended-1 val a = (a0 >> b).asSInt val msb = Mux(a === 0.S \|\| a === -1.S, ea(b), !ea(b-1)) Cat(msb, ea(b-1, 0)) } class Scoreboard(n: Int, zero: Boolean = false) { def set(en: Bool, addr: UInt): Unit = update(en, _next \| mask(en, addr)) def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr)) def read(addr: UInt): Bool = r(addr) def readBypassed(addr: UInt): Bool = _next(addr) private val _r = RegInit(0.U(n.W)) private val r = if (zero) (_r >> 1 << 1) else _r private var _next = r private var ens = false.B private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U) private def update(en: Bool, update: UInt) = { _next = update ens = ens \|\| en when (ens) { _r := _next } } } } class RegFile(n: Int, w: Int, zero: Boolean = false) { val rf = Mem(n, UInt(w.W)) private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0)) private val reads = ArrayBuffer[(UInt,UInt)]() private var canRead = true def read(addr: UInt) = { require(canRead) reads += addr -> Wire(UInt()) reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr)) reads.last._2 } def write(addr: UInt, data: UInt) = { canRead = false when (addr =/= 0.U) { access(addr) := data for ((raddr, rdata) <- reads) when (addr === raddr) { rdata := data } } } } object ImmGen { def apply(sel: UInt, inst: UInt) = { val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt) val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign) val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt) val b11 = Mux(sel === IMM_U \|\| sel === IMM_Z, 0.S, Mux(sel === IMM_UJ, inst(20).asSInt, Mux(sel === IMM_SB, inst(7).asSInt, sign))) val b10_5 = Mux(sel === IMM_U \|\| sel === IMM_Z, 0.U, inst(30,25)) val b4_1 = Mux(sel === IMM_U, 0.U, Mux(sel === IMM_S \|\| sel === IMM_SB, inst(11,8), Mux(sel === IMM_Z, inst(19,16), inst(24,21)))) val b0 = Mux(sel === IMM_S, inst(7), Mux(sel === IMM_I, inst(20), Mux(sel === IMM_Z, inst(15), 0.U))) Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out } File CSR.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.LinkedHashMap import Instructions._ import CustomInstructions._ class MStatus extends Bundle { // not truly part of mstatus, but convenient val debug = Bool() val cease = Bool() val wfi = Bool() val isa = UInt(32.W) val dprv = UInt(PRV.SZ.W) // effective prv for data accesses val dv = Bool() // effective v for data accesses val prv = UInt(PRV.SZ.W) val v = Bool() val sd = Bool() val zero2 = UInt(23.W) val mpv = Bool() val gva = Bool() val mbe = Bool() val sbe = Bool() val sxl = UInt(2.W) val uxl = UInt(2.W) val sd_rv32 = Bool() val zero1 = UInt(8.W) val tsr = Bool() val tw = Bool() val tvm = Bool() val mxr = Bool() val sum = Bool() val mprv = Bool() val xs = UInt(2.W) val fs = UInt(2.W) val mpp = UInt(2.W) val vs = UInt(2.W) val spp = UInt(1.W) val mpie = Bool() val ube = Bool() val spie = Bool() val upie = Bool() val mie = Bool() val hie = Bool() val sie = Bool() val uie = Bool() } class MNStatus extends Bundle { val mpp = UInt(2.W) val zero3 = UInt(3.W) val mpv = Bool() val zero2 = UInt(3.W) val mie = Bool() val zero1 = UInt(3.W) } class HStatus extends Bundle { val zero6 = UInt(30.W) val vsxl = UInt(2.W) val zero5 = UInt(9.W) val vtsr = Bool() val vtw = Bool() val vtvm = Bool() val zero3 = UInt(2.W) val vgein = UInt(6.W) val zero2 = UInt(2.W) val hu = Bool() val spvp = Bool() val spv = Bool() val gva = Bool() val vsbe = Bool() val zero1 = UInt(5.W) } class DCSR extends Bundle { val xdebugver = UInt(2.W) val zero4 = UInt(2.W) val zero3 = UInt(12.W) val ebreakm = Bool() val ebreakh = Bool() val ebreaks = Bool() val ebreaku = Bool() val zero2 = Bool() val stopcycle = Bool() val stoptime = Bool() val cause = UInt(3.W) val v = Bool() val zero1 = UInt(2.W) val step = Bool() val prv = UInt(PRV.SZ.W) } class MIP(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val lip = Vec(coreParams.nLocalInterrupts, Bool()) val zero1 = Bool() val debug = Bool() // keep in sync with CSR.debugIntCause val rocc = Bool() val sgeip = Bool() val meip = Bool() val vseip = Bool() val seip = Bool() val ueip = Bool() val mtip = Bool() val vstip = Bool() val stip = Bool() val utip = Bool() val msip = Bool() val vssip = Bool() val ssip = Bool() val usip = Bool() } class Envcfg extends Bundle { val stce = Bool() // only for menvcfg/henvcfg val pbmte = Bool() // only for menvcfg/henvcfg val zero54 = UInt(54.W) val cbze = Bool() val cbcfe = Bool() val cbie = UInt(2.W) val zero3 = UInt(3.W) val fiom = Bool() def write(wdata: UInt) { val new_envcfg = wdata.asTypeOf(new Envcfg) fiom := new_envcfg.fiom // only FIOM is writable currently } } class PTBR(implicit p: Parameters) extends CoreBundle()(p) { def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0) def pgLevelsToMode(i: Int) = (xLen, i) match { case (32, 2) => 1 case (64, x) if x >= 3 && x <= 6 => x + 5 } val (modeBits, maxASIdBits) = xLen match { case 32 => (1, 9) case 64 => (4, 16) } require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen) val mode = UInt(modeBits.W) val asid = UInt(maxASIdBits.W) val ppn = UInt((maxPAddrBits - pgIdxBits).W) } object PRV { val SZ = 2 val U = 0 val S = 1 val H = 2 val M = 3 } object CSR { // commands val SZ = 3 def X = BitPat.dontCare(SZ) def N = 0.U(SZ.W) def R = 2.U(SZ.W) def I = 4.U(SZ.W) def W = 5.U(SZ.W) def S = 6.U(SZ.W) def C = 7.U(SZ.W) // mask a CSR cmd with a valid bit def maskCmd(valid: Bool, cmd: UInt): UInt = { // all commands less than CSR.I are treated by CSRFile as NOPs cmd & ~Mux(valid, 0.U, CSR.I) } val ADDRSZ = 12 def modeLSB: Int = 8 def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ) def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB) def busErrorIntCause = 128 def debugIntCause = 14 // keep in sync with MIP.debug def debugTriggerCause = { val res = debugIntCause require(!(Causes.all contains res)) res } def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause def rnmiBEUCause = 12 val firstCtr = CSRs.cycle val firstCtrH = CSRs.cycleh val firstHPC = CSRs.hpmcounter3 val firstHPCH = CSRs.hpmcounter3h val firstHPE = CSRs.mhpmevent3 val firstMHPC = CSRs.mhpmcounter3 val firstMHPCH = CSRs.mhpmcounter3h val firstHPM = 3 val nCtr = 32 val nHPM = nCtr - firstHPM val hpmWidth = 40 val maxPMPs = 16 } class PerfCounterIO(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val eventSel = Output(UInt(xLen.W)) val inc = Input(UInt(log2Ceil(1+retireWidth).W)) } class TracedInstruction(implicit p: Parameters) extends CoreBundle { val valid = Bool() val iaddr = UInt(coreMaxAddrBits.W) val insn = UInt(iLen.W) val priv = UInt(3.W) val exception = Bool() val interrupt = Bool() val cause = UInt(xLen.W) val tval = UInt((coreMaxAddrBits max iLen).W) val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W)) } class TraceAux extends Bundle { val enable = Bool() val stall = Bool() } class CSRDecodeIO(implicit p: Parameters) extends CoreBundle { val inst = Input(UInt(iLen.W)) def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0) val fp_illegal = Output(Bool()) val vector_illegal = Output(Bool()) val fp_csr = Output(Bool()) val vector_csr = Output(Bool()) val rocc_illegal = Output(Bool()) val read_illegal = Output(Bool()) val write_illegal = Output(Bool()) val write_flush = Output(Bool()) val system_illegal = Output(Bool()) val virtual_access_illegal = Output(Bool()) val virtual_system_illegal = Output(Bool()) } class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val ungated_clock = Input(Clock()) val interrupts = Input(new CoreInterrupts(hasBeu)) val hartid = Input(UInt(hartIdLen.W)) val rw = new Bundle { val addr = Input(UInt(CSR.ADDRSZ.W)) val cmd = Input(Bits(CSR.SZ.W)) val rdata = Output(Bits(xLen.W)) val wdata = Input(Bits(xLen.W)) } val decode = Vec(decodeWidth, new CSRDecodeIO) val csr_stall = Output(Bool()) // stall retire for wfi val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall val eret = Output(Bool()) val singleStep = Output(Bool()) val status = Output(new MStatus()) val hstatus = Output(new HStatus()) val gstatus = Output(new MStatus()) val ptbr = Output(new PTBR()) val hgatp = Output(new PTBR()) val vsatp = Output(new PTBR()) val evec = Output(UInt(vaddrBitsExtended.W)) val exception = Input(Bool()) val retire = Input(UInt(log2Up(1+retireWidth).W)) val cause = Input(UInt(xLen.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val tval = Input(UInt(vaddrBitsExtended.W)) val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W)) val mhtinst_read_pseudo = Input(Bool()) val gva = Input(Bool()) val time = Output(UInt(xLen.W)) val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W))) val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool())) val rocc_interrupt = Input(Bool()) val interrupt = Output(Bool()) val interrupt_cause = Output(UInt(xLen.W)) val bp = Output(Vec(nBreakpoints, new BP)) val pmp = Output(Vec(nPMPs, new PMP)) val counters = Vec(nPerfCounters, new PerfCounterIO) val csrw_counter = Output(UInt(CSR.nCtr.W)) val inhibit_cycle = Output(Bool()) val inst = Input(Vec(retireWidth, UInt(iLen.W))) val trace = Output(Vec(retireWidth, new TracedInstruction)) val mcontext = Output(UInt(coreParams.mcontextWidth.W)) val scontext = Output(UInt(coreParams.scontextWidth.W)) val fiom = Output(Bool()) val vector = usingVector.option(new Bundle { val vconfig = Output(new VConfig()) val vstart = Output(UInt(maxVLMax.log2.W)) val vxrm = Output(UInt(2.W)) val set_vs_dirty = Input(Bool()) val set_vconfig = Flipped(Valid(new VConfig)) val set_vstart = Flipped(Valid(vstart)) val set_vxsat = Input(Bool()) }) } class VConfig(implicit p: Parameters) extends CoreBundle { val vl = UInt((maxVLMax.log2 + 1).W) val vtype = new VType } object VType { def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = { val res = 0.U.asTypeOf(new VType) val in = that.asTypeOf(res) val vill = (in.max_vsew.U < in.vsew) \|\| !in.lmul_ok \|\| in.reserved =/= 0.U \|\| in.vill when (!vill \|\| ignore_vill.B) { res := in res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0) } res.reserved := 0.U res.vill := vill res } def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt = VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero) } class VType(implicit p: Parameters) extends CoreBundle { val vill = Bool() val reserved = UInt((xLen - 9).W) val vma = Bool() val vta = Bool() val vsew = UInt(3.W) val vlmul_sign = Bool() val vlmul_mag = UInt(2.W) def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt @deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9") def vlmul: UInt = vlmul_mag def max_vsew = log2Ceil(eLen/8) def max_vlmul = (1 << vlmul_mag.getWidth) - 1 def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B) def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1 def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U) def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = { val atLeastMaxVLMax = useMax \|\| Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U) val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0) val atLeastVLMax = atLeastMaxVLMax \|\| (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR val isZero = vill \|\| useZero Mux(!isZero && atLeastVLMax, vlMax, 0.U) \| Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U) } } class CSRFile( perfEventSets: EventSets = new EventSets(Seq()), customCSRs: Seq[CustomCSR] = Nil, roccCSRs: Seq[CustomCSR] = Nil, hasBeu: Boolean = false)(implicit p: Parameters) extends CoreModule()(p) with HasCoreParameters { val io = IO(new CSRFileIO(hasBeu) { val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO) val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO) }) io.rw_stall := false.B val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := PRV.M.U reset_mstatus.prv := PRV.M.U reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U) val reg_mstatus = RegInit(reset_mstatus) val new_prv = WireDefault(reg_mstatus.prv) reg_mstatus.prv := legalizePrivilege(new_prv) val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR())) reset_dcsr.xdebugver := 1.U reset_dcsr.prv := PRV.M.U val reg_dcsr = RegInit(reset_dcsr) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) sup.usip := false.B sup.ssip := usingSupervisor.B sup.vssip := usingHypervisor.B sup.msip := true.B sup.utip := false.B sup.stip := usingSupervisor.B sup.vstip := usingHypervisor.B sup.mtip := true.B sup.ueip := false.B sup.seip := usingSupervisor.B sup.vseip := usingHypervisor.B sup.meip := true.B sup.sgeip := false.B sup.rocc := usingRoCC.B sup.debug := false.B sup.zero1 := false.B sup.lip foreach { _ := true.B } val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U val del = WireDefault(sup) del.msip := false.B del.mtip := false.B del.meip := false.B (sup.asUInt \| supported_high_interrupts, del.asUInt) } val delegable_base_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_page_fault, Causes.breakpoint, Causes.load_page_fault, Causes.store_page_fault, Causes.misaligned_load, Causes.misaligned_store, Causes.illegal_instruction, Causes.user_ecall, ) val delegable_hypervisor_exceptions = Seq( Causes.virtual_supervisor_ecall, Causes.fetch_guest_page_fault, Causes.load_guest_page_fault, Causes.virtual_instruction, Causes.store_guest_page_fault, ) val delegable_exceptions = ( delegable_base_exceptions ++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq()) ).map(1 << _).sum.U val hs_delegable_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_access, Causes.illegal_instruction, Causes.breakpoint, Causes.misaligned_load, Causes.load_access, Causes.misaligned_store, Causes.store_access, Causes.user_ecall, Causes.fetch_page_fault, Causes.load_page_fault, Causes.store_page_fault).map(1 << _).sum.U val (hs_delegable_interrupts, mideleg_always_hs) = { val always = WireDefault(0.U.asTypeOf(new MIP())) always.vssip := usingHypervisor.B always.vstip := usingHypervisor.B always.vseip := usingHypervisor.B val deleg = WireDefault(always) deleg.lip.foreach { _ := usingHypervisor.B } (deleg.asUInt, always.asUInt) } val reg_debug = RegInit(false.B) val reg_dpc = Reg(UInt(vaddrBitsExtended.W)) val reg_dscratch0 = Reg(UInt(xLen.W)) val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W))) val reg_singleStepped = Reg(Bool()) val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W))) val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W))) val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W)) val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP)) val reg_pmp = Reg(Vec(nPMPs, new PMPReg)) val reg_mie = Reg(UInt(xLen.W)) val (reg_mideleg, read_mideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_interrupts \| mideleg_always_hs, 0.U)) } val (reg_medeleg, read_medeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U)) } val reg_mip = Reg(new MIP) val reg_mepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mcause = RegInit(0.U(xLen.W)) val reg_mtval = Reg(UInt(vaddrBitsExtended.W)) val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W)) val reg_mscratch = Reg(Bits(xLen.W)) val mtvecWidth = paddrBits min xLen val reg_mtvec = mtvecInit match { case Some(addr) => RegInit(addr.U(mtvecWidth.W)) case None => Reg(UInt(mtvecWidth.W)) } val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus())) reset_mnstatus.mpp := PRV.M.U val reg_mnscratch = Reg(Bits(xLen.W)) val reg_mnepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mncause = RegInit(0.U(xLen.W)) val reg_mnstatus = RegInit(reset_mnstatus) val reg_rnmie = RegInit(true.B) val nmie = reg_rnmie val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U val (reg_mcounteren, read_mcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingUser.B, reg & delegable_counters, 0.U)) } val (reg_scounteren, read_scounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U)) } val (reg_hideleg, read_hideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U)) } val (reg_hedeleg, read_hedeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U)) } val hs_delegable_counters = delegable_counters val (reg_hcounteren, read_hcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U)) } val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus)) val reg_hgatp = Reg(new PTBR) val reg_htval = Reg(reg_mtval2.cloneType) val read_hvip = reg_mip.asUInt & hs_delegable_interrupts val read_hie = reg_mie & hs_delegable_interrupts val (reg_vstvec, read_vstvec) = { val reg = Reg(UInt(vaddrBitsExtended.W)) (reg, formTVec(reg).sextTo(xLen)) } val reg_vsstatus = Reg(new MStatus) val reg_vsscratch = Reg(Bits(xLen.W)) val reg_vsepc = Reg(UInt(vaddrBitsExtended.W)) val reg_vscause = Reg(Bits(xLen.W)) val reg_vstval = Reg(UInt(vaddrBitsExtended.W)) val reg_vsatp = Reg(new PTBR) val reg_sepc = Reg(UInt(vaddrBitsExtended.W)) val reg_scause = Reg(Bits(xLen.W)) val reg_stval = Reg(UInt(vaddrBitsExtended.W)) val reg_sscratch = Reg(Bits(xLen.W)) val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W)) val reg_satp = Reg(new PTBR) val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) } val reg_fflags = Reg(UInt(5.W)) val reg_frm = Reg(UInt(3.W)) val reg_vconfig = usingVector.option(Reg(new VConfig)) val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W))) val reg_vxsat = usingVector.option(Reg(Bool())) val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W))) val reg_mtinst_read_pseudo = Reg(Bool()) val reg_htinst_read_pseudo = Reg(Bool()) // XLEN=32: 0x00002000 // XLEN=64: 0x00003000 val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W))) val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W)) io.inhibit_cycle := reg_mcountinhibit(0) val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2)) val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0)) else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) } val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W))) (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e } val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) => WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) } val mip = WireDefault(reg_mip) mip.lip := (io.interrupts.lip: Seq[Bool]) mip.mtip := io.interrupts.mtip mip.msip := io.interrupts.msip mip.meip := io.interrupts.meip // seip is the OR of reg_mip.seip and the actual line from the PLIC io.interrupts.seip.foreach { mip.seip := reg_mip.seip \|\| _ } // Simimlar sort of thing would apply if the PLIC had a VSEIP line: //io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip \|\| _ } mip.rocc := io.rocc_interrupt val read_mip = mip.asUInt & supported_interrupts val read_hip = read_mip & hs_delegable_interrupts val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U)) val pending_interrupts = high_interrupts \| (read_mip & reg_mie) val d_interrupts = io.interrupts.debug << CSR.debugIntCause val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi => (((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) \| io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U), !io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B) val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U \|\| reg_mstatus.mie), ~(~pending_interrupts \| read_mideleg), 0.U) val s_interrupts = Mux(nmie && (reg_mstatus.v \|\| reg_mstatus.prv < PRV.S.U \|\| (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U) val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U \|\| reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U) val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts)) val interruptMSB = BigInt(1) << (xLen-1) val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt io.interrupt := (anyInterrupt && !io.singleStep \|\| reg_singleStepped) && !(reg_debug \|\| io.status.cease) io.interrupt_cause := interruptCause io.bp := reg_bp take nBreakpoints io.mcontext := reg_mcontext.getOrElse(0.U) io.scontext := reg_scontext.getOrElse(0.U) io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) \|\| (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) \|\| (reg_mstatus.v && reg_henvcfg.fiom) io.pmp := reg_pmp.map(PMP(_)) val isaMaskString = (if (usingMulDiv) "M" else "") + (if (usingAtomics) "A" else "") + (if (fLen >= 32) "F" else "") + (if (fLen >= 64) "D" else "") + (if (coreParams.hasV) "V" else "") + (if (usingCompressed) "C" else "") val isaString = (if (coreParams.useRVE) "E" else "I") + isaMaskString + (if (customIsaExt.isDefined \|\| usingRoCC) "X" else "") + (if (usingSupervisor) "S" else "") + (if (usingHypervisor) "H" else "") + (if (usingUser) "U" else "") val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) \| isaStringToMask(isaString) val reg_misa = RegInit(isaMax.U) val read_mstatus = io.status.asUInt.extract(xLen-1,0) val read_mtvec = formTVec(reg_mtvec).padTo(xLen) val read_stvec = formTVec(reg_stvec).sextTo(xLen) val read_mapping = LinkedHashMap[Int,Bits]( CSRs.tselect -> reg_tselect, CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt, CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen), CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt, CSRs.misa -> reg_misa, CSRs.mstatus -> read_mstatus, CSRs.mtvec -> read_mtvec, CSRs.mip -> read_mip, CSRs.mie -> reg_mie, CSRs.mscratch -> reg_mscratch, CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen), CSRs.mtval -> reg_mtval.sextTo(xLen), CSRs.mcause -> reg_mcause, CSRs.mhartid -> io.hartid) val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.dcsr -> reg_dcsr.asUInt, CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen), CSRs.dscratch0 -> reg_dscratch0.asUInt) ++ reg_dscratch1.map(r => CSRs.dscratch1 -> r) val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus())) read_mnstatus.mpp := reg_mnstatus.mpp read_mnstatus.mpv := reg_mnstatus.mpv read_mnstatus.mie := reg_rnmie val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits]( CustomCSRs.mnscratch -> reg_mnscratch, CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen), CustomCSRs.mncause -> reg_mncause, CustomCSRs.mnstatus -> read_mnstatus.asUInt) val context_csrs = LinkedHashMap[Int,Bits]() ++ reg_mcontext.map(r => CSRs.mcontext -> r) ++ reg_scontext.map(r => CSRs.scontext -> r) val read_fcsr = Cat(reg_frm, reg_fflags) val fp_csrs = LinkedHashMap[Int,Bits]() ++ usingFPU.option(CSRs.fflags -> reg_fflags) ++ usingFPU.option(CSRs.frm -> reg_frm) ++ (usingFPU \|\| usingVector).option(CSRs.fcsr -> read_fcsr) val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U)) val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.vxsat -> reg_vxsat.get, CSRs.vxrm -> reg_vxrm.get, CSRs.vcsr -> read_vcsr, CSRs.vstart -> reg_vstart.get, CSRs.vtype -> reg_vconfig.get.vtype.asUInt, CSRs.vl -> reg_vconfig.get.vl, CSRs.vlenb -> (vLen / 8).U) read_mapping ++= debug_csrs read_mapping ++= nmi_csrs read_mapping ++= context_csrs read_mapping ++= fp_csrs read_mapping ++= vector_csrs if (coreParams.haveBasicCounters) { read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit read_mapping += CSRs.mcycle -> reg_cycle read_mapping += CSRs.minstret -> reg_instret for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U) zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) { read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN if (xLen == 32) { read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh } } if (usingUser) { read_mapping += CSRs.mcounteren -> read_mcounteren } read_mapping += CSRs.cycle -> reg_cycle read_mapping += CSRs.instret -> reg_instret if (xLen == 32) { read_mapping += CSRs.mcycleh -> (reg_cycle >> 32) read_mapping += CSRs.minstreth -> (reg_instret >> 32) read_mapping += CSRs.cycleh -> (reg_cycle >> 32) read_mapping += CSRs.instreth -> (reg_instret >> 32) } } if (usingUser) { read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt if (xLen == 32) read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32) } val sie_mask = { val sgeip_mask = WireInit(0.U.asTypeOf(new MIP)) sgeip_mask.sgeip := true.B read_mideleg & ~(hs_delegable_interrupts \| sgeip_mask.asUInt) } if (usingSupervisor) { val read_sie = reg_mie & sie_mask val read_sip = read_mip & sie_mask val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus)) read_sstatus.sd := io.status.sd read_sstatus.uxl := io.status.uxl read_sstatus.sd_rv32 := io.status.sd_rv32 read_sstatus.mxr := io.status.mxr read_sstatus.sum := io.status.sum read_sstatus.xs := io.status.xs read_sstatus.fs := io.status.fs read_sstatus.vs := io.status.vs read_sstatus.spp := io.status.spp read_sstatus.spie := io.status.spie read_sstatus.sie := io.status.sie read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0) read_mapping += CSRs.sip -> read_sip.asUInt read_mapping += CSRs.sie -> read_sie.asUInt read_mapping += CSRs.sscratch -> reg_sscratch read_mapping += CSRs.scause -> reg_scause read_mapping += CSRs.stval -> reg_stval.sextTo(xLen) read_mapping += CSRs.satp -> reg_satp.asUInt read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen) read_mapping += CSRs.stvec -> read_stvec read_mapping += CSRs.scounteren -> read_scounteren read_mapping += CSRs.mideleg -> read_mideleg read_mapping += CSRs.medeleg -> read_medeleg read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt } val pmpCfgPerCSR = xLen / new PMPConfig().getWidth def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR) if (reg_pmp.nonEmpty) { require(reg_pmp.size <= CSR.maxPMPs) val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP)) for (i <- 0 until read_pmp.size by pmpCfgPerCSR) read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt for ((pmp, i) <- read_pmp.zipWithIndex) read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr } // implementation-defined CSRs def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = { require(csr.mask >= 0 && csr.mask.bitLength <= xLen) require(!read_mapping.contains(csr.id)) val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W))) val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U csr_io.ren := read when (read && csr_io.stall) { io.rw_stall := true.B } read_mapping += csr.id -> reg reg } val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2)) val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2)) if (usingHypervisor) { read_mapping += CSRs.mtinst -> read_mtinst read_mapping += CSRs.mtval2 -> reg_mtval2 val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.hstatus -> read_hstatus read_mapping += CSRs.hedeleg -> read_hedeleg read_mapping += CSRs.hideleg -> read_hideleg read_mapping += CSRs.hcounteren-> read_hcounteren read_mapping += CSRs.hgatp -> reg_hgatp.asUInt read_mapping += CSRs.hip -> read_hip read_mapping += CSRs.hie -> read_hie read_mapping += CSRs.hvip -> read_hvip read_mapping += CSRs.hgeie -> 0.U read_mapping += CSRs.hgeip -> 0.U read_mapping += CSRs.htval -> reg_htval read_mapping += CSRs.htinst -> read_htinst read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt if (xLen == 32) read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32) val read_vsie = (read_hie & read_hideleg) >> 1 val read_vsip = (read_hip & read_hideleg) >> 1 val read_vsepc = readEPC(reg_vsepc).sextTo(xLen) val read_vstval = reg_vstval.sextTo(xLen) val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.vsstatus -> read_vsstatus read_mapping += CSRs.vsip -> read_vsip read_mapping += CSRs.vsie -> read_vsie read_mapping += CSRs.vsscratch -> reg_vsscratch read_mapping += CSRs.vscause -> reg_vscause read_mapping += CSRs.vstval -> read_vstval read_mapping += CSRs.vsatp -> reg_vsatp.asUInt read_mapping += CSRs.vsepc -> read_vsepc read_mapping += CSRs.vstvec -> read_vstvec } // mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U)) val decoded_addr = { val addr = Cat(io.status.v, io.rw.addr) val pats = for (((k, _), i) <- read_mapping.zipWithIndex) yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B))) val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats) val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap for ((k, v) <- unvirtualized_mapping) yield k -> { val alt: Option[Bool] = CSR.mode(k) match { // hcontext was assigned an unfortunate address; it lives where a // hypothetical vscontext will live. Exclude them from the S/VS remapping. // (on separate lines so scala-lint doesnt do something stupid) case _ if k == CSRs.scontext => None case _ if k == CSRs.hcontext => None // When V=1, if a corresponding VS CSR exists, access it instead... case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB)) // ...and don't access the original S-mode version. case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B) case _ => None } alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v) } } val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata) val system_insn = io.rw.cmd === CSR.I val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU) val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N), EBREAK-> List(N,Y,N,N,N,N,N,N,N), MRET-> List(N,N,Y,N,N,N,N,N,N), CEASE-> List(N,N,N,Y,N,N,N,N,N), WFI-> List(N,N,N,N,Y,N,N,N,N)) ++ usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++ coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++ usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++ usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++ usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++ (if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq()) val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = { val insn = ECALL.value.U \| (io.rw.addr << 20) DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool) } for (io_dec <- io.decode) { val addr = io_dec.inst(31, 20) def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_\|\|_) def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U)) val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil = DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool) val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) \|\| addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U)) val allow_wfi = (!usingSupervisor).B \|\| reg_mstatus.prv > PRV.S.U \|\| !reg_mstatus.tw && (!reg_mstatus.v \|\| !reg_hstatus.vtw) val allow_sfence_vma = (!usingVM).B \|\| reg_mstatus.prv > PRV.S.U \|\| !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) val allow_hfence_vvma = (!usingHypervisor).B \|\| !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U) val allow_hlsv = (!usingHypervisor).B \|\| !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U \|\| reg_hstatus.hu) val allow_sret = (!usingSupervisor).B \|\| reg_mstatus.prv > PRV.S.U \|\| !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0) val allow_counter = (reg_mstatus.prv > PRV.S.U \|\| read_mcounteren(counter_addr)) && (!usingSupervisor.B \|\| reg_mstatus.prv >= PRV.S.U \|\| read_scounteren(counter_addr)) && (!usingHypervisor.B \|\| !reg_mstatus.v \|\| read_hcounteren(counter_addr)) io_dec.fp_illegal := io.status.fs === 0.U \|\| reg_mstatus.v && reg_vsstatus.fs === 0.U \|\| !reg_misa('f'-'a') io_dec.vector_illegal := io.status.vs === 0.U \|\| reg_mstatus.v && reg_vsstatus.vs === 0.U \|\| !reg_misa('v'-'a') io_dec.fp_csr := decodeFast(fp_csrs.keys.toList) io_dec.vector_csr := decodeFast(vector_csrs.keys.toList) io_dec.rocc_illegal := io.status.xs === 0.U \|\| reg_mstatus.v && reg_vsstatus.xs === 0.U \|\| !reg_misa('x'-'a') val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) \|\| usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U val csr_exists = decodeAny(read_mapping) io_dec.read_illegal := !csr_addr_legal \|\| !csr_exists \|\| ((addr === CSRs.satp.U \|\| addr === CSRs.hgatp.U) && !allow_sfence_vma) \|\| is_counter && !allow_counter \|\| decodeFast(debug_csrs.keys.toList) && !reg_debug \|\| decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal \|\| io_dec.fp_csr && io_dec.fp_illegal io_dec.write_illegal := addr(11,10).andR io_dec.write_flush := { val addr_m = addr \| (PRV.M.U << CSR.modeLSB) !(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U) } io_dec.system_illegal := !csr_addr_legal && !is_hlsv \|\| is_wfi && !allow_wfi \|\| is_ret && !allow_sret \|\| is_ret && addr(10) && addr(7) && !reg_debug \|\| (is_sfence \|\| is_hfence_gvma) && !allow_sfence_vma \|\| is_hfence_vvma && !allow_hfence_vvma \|\| is_hlsv && !allow_hlsv io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && ( CSR.mode(addr) === PRV.H.U \|\| is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) \|\| !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) \|\| CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) \|\| addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm) io_dec.virtual_system_illegal := reg_mstatus.v && ( is_hfence_vvma \|\| is_hfence_gvma \|\| is_hlsv \|\| is_wfi && (!reg_mstatus.prv(0) \|\| !reg_mstatus.tw && reg_hstatus.vtw) \|\| is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) \|\| reg_hstatus.vtsr) \|\| is_sfence && (!reg_mstatus.prv(0) \|\| reg_hstatus.vtvm)) } val cause = Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv), Mux[UInt](insn_break, Causes.breakpoint.U, io.cause)) val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0) val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0) val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv) val trapToDebug = usingDebug.B && (reg_singleStepped \|\| causeIsDebugInt \|\| causeIsDebugTrigger \|\| causeIsDebugBreak \|\| reg_debug) val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800)) val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808)) val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U) val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs)) val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs)) def mtvecBaseAlign = 2 def mtvecInterruptAlign = { require(reg_mip.getWidth <= xLen) log2Ceil(xLen) } val notDebugTVec = { val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec) val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset) val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign) } val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U \|\| cause_lsbs === CSR.rnmiBEUCause.U) val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U val causeIsNmi = causeIsRnmiInt val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U) val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U) val trapToNmiInt = usingNMI.B && causeIsNmi val trapToNmiXcpt = usingNMI.B && !nmie val trapToNmi = trapToNmiInt \|\| trapToNmiXcpt val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1 val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec)) io.evec := tvec io.ptbr := reg_satp io.hgatp := reg_hgatp io.vsatp := reg_vsatp io.eret := insn_call \|\| insn_break \|\| insn_ret io.singleStep := reg_dcsr.step && !reg_debug io.status := reg_mstatus io.status.sd := io.status.fs.andR \|\| io.status.xs.andR \|\| io.status.vs.andR io.status.debug := reg_debug io.status.isa := reg_misa io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv) io.status.dv := reg_mstatus.v \|\| Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B) io.status.sd_rv32 := (xLen == 32).B && io.status.sd io.status.mpv := reg_mstatus.mpv io.status.gva := reg_mstatus.gva io.hstatus := reg_hstatus io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.gstatus := reg_vsstatus io.gstatus.sd := io.gstatus.fs.andR \|\| io.gstatus.xs.andR \|\| io.gstatus.vs.andR io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd val exception = insn_call \|\| insn_break \|\| io.exception assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive") when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B } when (pending_interrupts.orR \|\| io.interrupts.debug \|\| exception) { reg_wfi := false.B } io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } ) when (io.retire(0) \|\| exception) { reg_singleStepped := true.B } when (!io.singleStep) { reg_singleStepped := false.B } assert(!io.singleStep \|\| io.retire <= 1.U) assert(!reg_singleStepped \|\| io.retire === 0.U) val epc = formEPC(io.pc) val tval = Mux(insn_break, epc, io.tval) when (exception) { when (trapToDebug) { when (!reg_debug) { reg_mstatus.v := false.B reg_debug := true.B reg_dpc := epc reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U))) reg_dcsr.prv := trimPrivilege(reg_mstatus.prv) reg_dcsr.v := reg_mstatus.v new_prv := PRV.M.U } }.elsewhen (trapToNmiInt) { when (reg_rnmie) { reg_mstatus.v := false.B reg_mnstatus.mpv := reg_mstatus.v reg_rnmie := false.B reg_mnepc := epc reg_mncause := (BigInt(1) << (xLen-1)).U \| Mux(causeIsRnmiBEU, 3.U, 2.U) reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv) new_prv := PRV.M.U } }.elsewhen (delegateVS && nmie) { reg_mstatus.v := true.B reg_vsstatus.spp := reg_mstatus.prv reg_vsepc := epc reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause) reg_vstval := tval reg_vsstatus.spie := reg_vsstatus.sie reg_vsstatus.sie := false.B new_prv := PRV.S.U }.elsewhen (delegate && nmie) { reg_mstatus.v := false.B reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp) reg_hstatus.gva := io.gva reg_hstatus.spv := reg_mstatus.v reg_sepc := epc reg_scause := cause reg_stval := tval reg_htval := io.htval reg_htinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.spie := reg_mstatus.sie reg_mstatus.spp := reg_mstatus.prv reg_mstatus.sie := false.B new_prv := PRV.S.U }.otherwise { reg_mstatus.v := false.B reg_mstatus.mpv := reg_mstatus.v reg_mstatus.gva := io.gva reg_mepc := epc reg_mcause := cause reg_mtval := tval reg_mtval2 := io.htval reg_mtinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.mpie := reg_mstatus.mie reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv) reg_mstatus.mie := false.B new_prv := PRV.M.U } } for (i <- 0 until supported_interrupts.getWidth) { val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"INTERRUPT_M_$i") property.cover(en && delegable && delegate, s"INTERRUPT_S_$i") } for (i <- 0 until xLen) { val supported_exceptions: BigInt = 0x8fe \| (if (usingCompressed && !coreParams.misaWritable) 0 else 1) \| (if (usingUser) 0x100 else 0) \| (if (usingSupervisor) 0x200 else 0) \| (if (usingVM) 0xb000 else 0) if (((supported_exceptions >> i) & 1) != 0) { val en = exception && cause === i.U val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"EXCEPTION_M_$i") property.cover(en && delegable && delegate, s"EXCEPTION_S_$i") } } when (insn_ret) { val ret_prv = WireInit(UInt(), DontCare) when (usingSupervisor.B && !io.rw.addr(9)) { when (!reg_mstatus.v) { reg_mstatus.sie := reg_mstatus.spie reg_mstatus.spie := true.B reg_mstatus.spp := PRV.U.U ret_prv := reg_mstatus.spp reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv io.evec := readEPC(reg_sepc) reg_hstatus.spv := false.B }.otherwise { reg_vsstatus.sie := reg_vsstatus.spie reg_vsstatus.spie := true.B reg_vsstatus.spp := PRV.U.U ret_prv := reg_vsstatus.spp reg_mstatus.v := usingHypervisor.B io.evec := readEPC(reg_vsepc) } }.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) { ret_prv := reg_dcsr.prv reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U reg_debug := false.B io.evec := readEPC(reg_dpc) }.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) { ret_prv := reg_mnstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U reg_rnmie := true.B io.evec := readEPC(reg_mnepc) }.otherwise { reg_mstatus.mie := reg_mstatus.mpie reg_mstatus.mpie := true.B reg_mstatus.mpp := legalizePrivilege(PRV.U.U) reg_mstatus.mpv := false.B ret_prv := reg_mstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U io.evec := readEPC(reg_mepc) } new_prv := ret_prv when (usingUser.B && ret_prv <= PRV.S.U) { reg_mstatus.mprv := false.B } } io.time := reg_cycle io.csr_stall := reg_wfi \|\| io.status.cease io.status.cease := RegEnable(true.B, false.B, insn_cease) io.status.wfi := reg_wfi for ((io, reg) <- io.customCSRs zip reg_custom) { io.wen := false.B io.wdata := wdata io.value := reg } for ((io, reg) <- io.roccCSRs zip reg_rocc) { io.wen := false.B io.wdata := wdata io.value := reg } io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) // cover access to register val coverable_counters = read_mapping.filterNot { case (k, _) => k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM } coverable_counters.foreach( {case (k, v) => { when (!k.U(11,10).andR) { // Cover points for RW CSR registers property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } .otherwise { // Cover points for RO CSR registers property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } }}) val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B)) io.vector.foreach { vio => when (set_vs_dirty) { assert(reg_mstatus.vs > 0.U) when (reg_mstatus.v) { reg_vsstatus.vs := 3.U } reg_mstatus.vs := 3.U } } val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B)) if (coreParams.haveFSDirty) { when (set_fs_dirty) { assert(reg_mstatus.fs > 0.U) when (reg_mstatus.v) { reg_vsstatus.fs := 3.U } reg_mstatus.fs := 3.U } } io.fcsr_rm := reg_frm when (io.fcsr_flags.valid) { reg_fflags := reg_fflags \| io.fcsr_flags.bits set_fs_dirty := true.B } io.vector.foreach { vio => when (vio.set_vxsat) { reg_vxsat.get := true.B set_vs_dirty := true.B } } val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) \|\| io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U) when (csr_wen) { val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB / val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_)) when (decoded_addr(CSRs.mstatus)) { val new_mstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.mie := new_mstatus.mie reg_mstatus.mpie := new_mstatus.mpie if (usingUser) { reg_mstatus.mprv := new_mstatus.mprv reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp) if (usingSupervisor) { reg_mstatus.spp := new_mstatus.spp reg_mstatus.spie := new_mstatus.spie reg_mstatus.sie := new_mstatus.sie reg_mstatus.tw := new_mstatus.tw reg_mstatus.tsr := new_mstatus.tsr } if (usingVM) { reg_mstatus.mxr := new_mstatus.mxr reg_mstatus.sum := new_mstatus.sum reg_mstatus.tvm := new_mstatus.tvm } if (usingHypervisor) { reg_mstatus.mpv := new_mstatus.mpv reg_mstatus.gva := new_mstatus.gva } } if (usingSupervisor \|\| usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs) reg_mstatus.vs := formVS(new_mstatus.vs) } when (decoded_addr(CSRs.misa)) { val mask = isaStringToMask(isaMaskString).U(xLen.W) val f = wdata('f' - 'a') // suppress write if it would cause the next fetch to be misaligned when (!usingCompressed.B \|\| !io.pc(1) \|\| wdata('c' - 'a')) { if (coreParams.misaWritable) reg_misa := ~(~wdata \| (!f << ('d' - 'a'))) & mask \| reg_misa & ~mask } } when (decoded_addr(CSRs.mip)) { // MIP should be modified based on the value in reg_mip, not the value // in read_mip, since read_mip.seip is the OR of reg_mip.seip and // io.interrupts.seip. We don't want the value on the PLIC line to // inadvertently be OR'd into read_mip.seip. val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP) if (usingSupervisor) { reg_mip.ssip := new_mip.ssip reg_mip.stip := new_mip.stip reg_mip.seip := new_mip.seip } if (usingHypervisor) { reg_mip.vssip := new_mip.vssip } } when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts } when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) } when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata } if (mtvecWritable) when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata } when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U } when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata } if (usingNMI) { val new_mnstatus = wdata.asTypeOf(new MNStatus()) when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata } when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) } when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U } when (decoded_addr(CustomCSRs.mnstatus)) { reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp) reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv reg_rnmie := reg_rnmie \| new_mnstatus.mie // mnie bit settable but not clearable from software } } for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) { writeCounter(i + CSR.firstMHPC, c, wdata) when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) } } if (coreParams.haveBasicCounters) { when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero writeCounter(CSRs.mcycle, reg_cycle, wdata) writeCounter(CSRs.minstret, reg_instret, wdata) } if (usingFPU) { when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata } when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata } when (decoded_addr(CSRs.fcsr)) { set_fs_dirty := true.B reg_fflags := wdata reg_frm := wdata >> reg_fflags.getWidth } } if (usingDebug) { when (decoded_addr(CSRs.dcsr)) { val new_dcsr = wdata.asTypeOf(new DCSR()) reg_dcsr.step := new_dcsr.step reg_dcsr.ebreakm := new_dcsr.ebreakm if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv) if (usingHypervisor) reg_dcsr.v := new_dcsr.v } when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) } when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata } reg_dscratch1.foreach { r => when (decoded_addr(CSRs.dscratch1)) { r := wdata } } } if (usingSupervisor) { when (decoded_addr(CSRs.sstatus)) { val new_sstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.sie := new_sstatus.sie reg_mstatus.spie := new_sstatus.spie reg_mstatus.spp := new_sstatus.spp reg_mstatus.fs := formFS(new_sstatus.fs) reg_mstatus.vs := formVS(new_sstatus.vs) if (usingVM) { reg_mstatus.mxr := new_sstatus.mxr reg_mstatus.sum := new_sstatus.sum } } when (decoded_addr(CSRs.sip)) { val new_sip = ((read_mip & ~read_mideleg) \| (wdata & read_mideleg)).asTypeOf(new MIP()) reg_mip.ssip := new_sip.ssip } when (decoded_addr(CSRs.satp)) { if (usingVM) { val new_satp = wdata.asTypeOf(new PTBR()) when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) { reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_\|_).U reg_satp.ppn := new_satp.ppn(ppnBits-1,0) if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0) } } } when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) \| (wdata & sie_mask) } when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata } when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) } when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata } when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask } when (decoded_addr(CSRs.stval)) { reg_stval := wdata } when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata } when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata } when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata } when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) } } if (usingHypervisor) { when (decoded_addr(CSRs.hstatus)) { val new_hstatus = wdata.asTypeOf(new HStatus()) reg_hstatus.gva := new_hstatus.gva reg_hstatus.spv := new_hstatus.spv reg_hstatus.spvp := new_hstatus.spvp reg_hstatus.hu := new_hstatus.hu reg_hstatus.vtvm := new_hstatus.vtvm reg_hstatus.vtw := new_hstatus.vtw reg_hstatus.vtsr := new_hstatus.vtsr reg_hstatus.vsxl := new_hstatus.vsxl } when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata } when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata } when (decoded_addr(CSRs.hgatp)) { val new_hgatp = wdata.asTypeOf(new PTBR()) val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_)) when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) { reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_\|_).U } reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W)) if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0) } when (decoded_addr(CSRs.hip)) { val new_hip = ((read_mip & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_hip.vssip } when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts) } when (decoded_addr(CSRs.hvip)) { val new_sip = ((read_mip & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_sip.vssip reg_mip.vstip := new_sip.vstip reg_mip.vseip := new_sip.vseip } when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata } when (decoded_addr(CSRs.htval)) { reg_htval := wdata } when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata } val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12)) when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo } when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo } when (decoded_addr(CSRs.vsstatus)) { val new_vsstatus = wdata.asTypeOf(new MStatus()) reg_vsstatus.sie := new_vsstatus.sie reg_vsstatus.spie := new_vsstatus.spie reg_vsstatus.spp := new_vsstatus.spp reg_vsstatus.mxr := new_vsstatus.mxr reg_vsstatus.sum := new_vsstatus.sum reg_vsstatus.fs := formFS(new_vsstatus.fs) reg_vsstatus.vs := formVS(new_vsstatus.vs) } when (decoded_addr(CSRs.vsip)) { val new_vsip = ((read_hip & ~read_hideleg) \| ((wdata << 1) & read_hideleg)).asTypeOf(new MIP()) reg_mip.vssip := new_vsip.vssip } when (decoded_addr(CSRs.vsatp)) { val new_vsatp = wdata.asTypeOf(new PTBR()) val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U)) when (mode_ok) { reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_\|_).U } when (mode_ok \|\| !reg_mstatus.v) { reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0) if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0) } } when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) \| ((wdata << 1) & read_hideleg) } when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata } when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) } when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata } when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask } when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata } when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) } } if (usingUser) { when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata } when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) } } if (nBreakpoints > 0) { when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata } for ((bp, i) <- reg_bp.zipWithIndex) { when (i.U === reg_tselect && (!bp.control.dmode \|\| reg_debug)) { when (decoded_addr(CSRs.tdata2)) { bp.address := wdata } when (decoded_addr(CSRs.tdata3)) { if (coreParams.mcontextWidth > 0) { bp.textra.mselect := wdata(bp.textra.mselectPos) bp.textra.mvalue := wdata >> bp.textra.mvaluePos } if (coreParams.scontextWidth > 0) { bp.textra.sselect := wdata(bp.textra.sselectPos) bp.textra.svalue := wdata >> bp.textra.svaluePos } } when (decoded_addr(CSRs.tdata1)) { bp.control := wdata.asTypeOf(bp.control) val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control) val dMode = newBPC.dmode && reg_debug && (prevDMode \|\| !prevChain) bp.control.dmode := dMode when (dMode \|\| (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U } bp.control.chain := newBPC.chain && !(prevChain \|\| nextChain) && (dMode \|\| !nextDMode) } } } } reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }} reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }} if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) { require(xLen % pmp.cfg.getWidth == 0) when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) { val newCfg = (wdata >> ((i pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig()) pmp.cfg := newCfg // disallow unreadable but writable PMPs pmp.cfg.w := newCfg.w && newCfg.r // can't select a=NA4 with coarse-grained PMPs if (pmpGranularity.log2 > PMP.lgAlign) pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR) } when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) { pmp.addr := wdata } } def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (decoded_addr(csr.id)) { reg := (wdata & mask) \| (reg & ~mask) io.wen := true.B } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { writeCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { writeCustomCSR(io, csr, reg) } if (usingVector) { when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata } when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata } when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata } when (decoded_addr(CSRs.vcsr)) { set_vs_dirty := true.B reg_vxsat.get := wdata reg_vxrm.get := wdata >> 1 } } } def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (io.set) { reg := (io.sdata & mask) \| (reg & ~mask) } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { setCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { setCustomCSR(io, csr, reg) } io.vector.map { vio => when (vio.set_vconfig.valid) { // user of CSRFile is responsible for set_vs_dirty in this case assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax) reg_vconfig.get := vio.set_vconfig.bits } when (vio.set_vstart.valid) { set_vs_dirty := true.B reg_vstart.get := vio.set_vstart.bits } vio.vstart := reg_vstart.get vio.vconfig := reg_vconfig.get vio.vxrm := reg_vxrm.get when (reset.asBool) { reg_vconfig.get.vl := 0.U reg_vconfig.get.vtype := 0.U.asTypeOf(new VType) reg_vconfig.get.vtype.vill := true.B } } when(reset.asBool) { reg_satp.mode := 0.U reg_vsatp.mode := 0.U reg_hgatp.mode := 0.U } if (!usingVM) { reg_satp.mode := 0.U reg_satp.ppn := 0.U reg_satp.asid := 0.U } if (!usingHypervisor) { reg_vsatp.mode := 0.U reg_vsatp.ppn := 0.U reg_vsatp.asid := 0.U reg_hgatp.mode := 0.U reg_hgatp.ppn := 0.U reg_hgatp.asid := 0.U } if (!(asIdBits > 0)) { reg_satp.asid := 0.U reg_vsatp.asid := 0.U } if (!(vmIdBits > 0)) { reg_hgatp.asid := 0.U } reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U) if (nBreakpoints <= 1) reg_tselect := 0.U for (bpc <- reg_bp map {_.control}) { bpc.ttype := bpc.tType.U bpc.maskmax := bpc.maskMax.U bpc.reserved := 0.U bpc.zero := 0.U bpc.h := false.B if (!usingSupervisor) bpc.s := false.B if (!usingUser) bpc.u := false.B if (!usingSupervisor && !usingUser) bpc.m := true.B when (reset.asBool) { bpc.action := 0.U bpc.dmode := false.B bpc.chain := false.B bpc.r := false.B bpc.w := false.B bpc.x := false.B } } for (bpx <- reg_bp map {_.textra}) { if (coreParams.mcontextWidth == 0) bpx.mselect := false.B if (coreParams.scontextWidth == 0) bpx.sselect := false.B } for (bp <- reg_bp drop nBreakpoints) bp := 0.U.asTypeOf(new BP()) for (pmp <- reg_pmp) { pmp.cfg.res := 0.U when (reset.asBool) { pmp.reset() } } for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) { t.exception := io.retire >= i.U && exception t.valid := io.retire > i.U \|\| t.exception t.insn := insn t.iaddr := io.pc t.priv := Cat(reg_debug, reg_mstatus.prv) t.cause := cause t.interrupt := cause(xLen-1) t.tval := io.tval t.wdata.foreach(_ := DontCare) } def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = { val nonstandard = supported_interrupts.getWidth-1 to 12 by -1 // MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4) val priority = nonstandard ++ standard val masks = masksIn.reverse val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_\|\|_) val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U)))) (any, which) } def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = { (Mux(cmd(1), rdata, 0.U) \| wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U) } def legalizePrivilege(priv: UInt): UInt = if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv) else if (usingUser) Fill(2, priv(0)) else PRV.M.U def trimPrivilege(priv: UInt): UInt = if (usingSupervisor) priv else legalizePrivilege(priv) def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { if (xLen == 32) { val hi = lo + CSRs.mcycleh - CSRs.mcycle when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } } else { when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) } } } def formEPC(x: UInt) = ~(~x \| (if (usingCompressed) 1.U else 3.U)) def readEPC(x: UInt) = ~(~x \| Mux(reg_misa('c' - 'a'), 1.U, 3.U)) def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) \| 2).U, 2.U) def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_\|_) def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR) def formVS(vs: UInt) = if (usingVector) vs else 0.U }	module Rocket_1( // @[RocketCore.scala:153:7] input clock, // @[RocketCore.scala:153:7] input reset, // @[RocketCore.scala:153:7] input io_hartid, // @[RocketCore.scala:134:14] input io_interrupts_debug, // @[RocketCore.scala:134:14] input io_interrupts_mtip, // @[RocketCore.scala:134:14] input io_interrupts_msip, // @[RocketCore.scala:134:14] input io_interrupts_meip, // @[RocketCore.scala:134:14] input io_interrupts_seip, // @[RocketCore.scala:134:14] output io_imem_might_request, // @[RocketCore.scala:134:14] output io_imem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_imem_req_bits_pc, // @[RocketCore.scala:134:14] output io_imem_req_bits_speculative, // @[RocketCore.scala:134:14] output io_imem_sfence_valid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_imem_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_asid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_hv, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_hg, // @[RocketCore.scala:134:14] output io_imem_resp_ready, // @[RocketCore.scala:134:14] input io_imem_resp_valid, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_btb_cfiType, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_taken, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_btb_mask, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bridx, // @[RocketCore.scala:134:14] input [38:0] io_imem_resp_bits_btb_target, // @[RocketCore.scala:134:14] input [4:0] io_imem_resp_bits_btb_entry, // @[RocketCore.scala:134:14] input [7:0] io_imem_resp_bits_btb_bht_history, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bht_value, // @[RocketCore.scala:134:14] input [39:0] io_imem_resp_bits_pc, // @[RocketCore.scala:134:14] input [31:0] io_imem_resp_bits_data, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_mask, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_pf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_gf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_ae_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_imem_gpa_valid, // @[RocketCore.scala:134:14] input [39:0] io_imem_gpa_bits, // @[RocketCore.scala:134:14] input io_imem_gpa_is_pte, // @[RocketCore.scala:134:14] output io_imem_btb_update_valid, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_prediction_cfiType, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_taken, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_prediction_mask, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_bridx, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_prediction_target, // @[RocketCore.scala:134:14] output [4:0] io_imem_btb_update_bits_prediction_entry, // @[RocketCore.scala:134:14] output [7:0] io_imem_btb_update_bits_prediction_bht_history, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_bht_value, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_pc, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_target, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_isValid, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_br_pc, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_cfiType, // @[RocketCore.scala:134:14] output io_imem_bht_update_valid, // @[RocketCore.scala:134:14] output [7:0] io_imem_bht_update_bits_prediction_history, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_prediction_value, // @[RocketCore.scala:134:14] output [38:0] io_imem_bht_update_bits_pc, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_branch, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_taken, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_mispredict, // @[RocketCore.scala:134:14] output io_imem_flush_icache, // @[RocketCore.scala:134:14] input [39:0] io_imem_npc, // @[RocketCore.scala:134:14] input io_imem_perf_acquire, // @[RocketCore.scala:134:14] input io_imem_perf_tlbMiss, // @[RocketCore.scala:134:14] output io_imem_progress, // @[RocketCore.scala:134:14] input io_dmem_req_ready, // @[RocketCore.scala:134:14] output io_dmem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_dmem_req_bits_addr, // @[RocketCore.scala:134:14] output [6:0] io_dmem_req_bits_tag, // @[RocketCore.scala:134:14] output [4:0] io_dmem_req_bits_cmd, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_size, // @[RocketCore.scala:134:14] output io_dmem_req_bits_signed, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_dprv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_dv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_no_resp, // @[RocketCore.scala:134:14] output io_dmem_s1_kill, // @[RocketCore.scala:134:14] output [63:0] io_dmem_s1_data_data, // @[RocketCore.scala:134:14] input io_dmem_s2_nack, // @[RocketCore.scala:134:14] input io_dmem_s2_nack_cause_raw, // @[RocketCore.scala:134:14] input io_dmem_s2_uncached, // @[RocketCore.scala:134:14] input [31:0] io_dmem_s2_paddr, // @[RocketCore.scala:134:14] input io_dmem_resp_valid, // @[RocketCore.scala:134:14] input [39:0] io_dmem_resp_bits_addr, // @[RocketCore.scala:134:14] input [6:0] io_dmem_resp_bits_tag, // @[RocketCore.scala:134:14] input [4:0] io_dmem_resp_bits_cmd, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_size, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_signed, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_dprv, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_dv, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data, // @[RocketCore.scala:134:14] input [7:0] io_dmem_resp_bits_mask, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_has_data, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_word_bypass, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_raw, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_store_data, // @[RocketCore.scala:134:14] input io_dmem_replay_next, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_st, // @[RocketCore.scala:134:14] input [39:0] io_dmem_s2_gpa, // @[RocketCore.scala:134:14] input io_dmem_ordered, // @[RocketCore.scala:134:14] input io_dmem_store_pending, // @[RocketCore.scala:134:14] input io_dmem_perf_acquire, // @[RocketCore.scala:134:14] input io_dmem_perf_release, // @[RocketCore.scala:134:14] input io_dmem_perf_grant, // @[RocketCore.scala:134:14] input io_dmem_perf_tlbMiss, // @[RocketCore.scala:134:14] input io_dmem_perf_blocked, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptStoreThenLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptStoreThenRMW, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptLoadThenLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_storeBufferEmptyAfterLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_storeBufferEmptyAfterStore, // @[RocketCore.scala:134:14] output io_dmem_keep_clock_enabled, // @[RocketCore.scala:134:14] output [3:0] io_ptw_ptbr_mode, // @[RocketCore.scala:134:14] output [43:0] io_ptw_ptbr_ppn, // @[RocketCore.scala:134:14] output io_ptw_sfence_valid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_ptw_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_asid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_hv, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_hg, // @[RocketCore.scala:134:14] output io_ptw_status_debug, // @[RocketCore.scala:134:14] output io_ptw_status_cease, // @[RocketCore.scala:134:14] output io_ptw_status_wfi, // @[RocketCore.scala:134:14] output [31:0] io_ptw_status_isa, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_dprv, // @[RocketCore.scala:134:14] output io_ptw_status_dv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_prv, // @[RocketCore.scala:134:14] output io_ptw_status_v, // @[RocketCore.scala:134:14] output io_ptw_status_sd, // @[RocketCore.scala:134:14] output io_ptw_status_mpv, // @[RocketCore.scala:134:14] output io_ptw_status_gva, // @[RocketCore.scala:134:14] output io_ptw_status_tsr, // @[RocketCore.scala:134:14] output io_ptw_status_tw, // @[RocketCore.scala:134:14] output io_ptw_status_tvm, // @[RocketCore.scala:134:14] output io_ptw_status_mxr, // @[RocketCore.scala:134:14] output io_ptw_status_sum, // @[RocketCore.scala:134:14] output io_ptw_status_mprv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_fs, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_mpp, // @[RocketCore.scala:134:14] output io_ptw_status_spp, // @[RocketCore.scala:134:14] output io_ptw_status_mpie, // @[RocketCore.scala:134:14] output io_ptw_status_spie, // @[RocketCore.scala:134:14] output io_ptw_status_mie, // @[RocketCore.scala:134:14] output io_ptw_status_sie, // @[RocketCore.scala:134:14] output io_ptw_hstatus_spvp, // @[RocketCore.scala:134:14] output io_ptw_hstatus_spv, // @[RocketCore.scala:134:14] output io_ptw_hstatus_gva, // @[RocketCore.scala:134:14] output io_ptw_gstatus_debug, // @[RocketCore.scala:134:14] output io_ptw_gstatus_cease, // @[RocketCore.scala:134:14] output io_ptw_gstatus_wfi, // @[RocketCore.scala:134:14] output [31:0] io_ptw_gstatus_isa, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_dprv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_dv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_prv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_v, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sd, // @[RocketCore.scala:134:14] output [22:0] io_ptw_gstatus_zero2, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mpv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_gva, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mbe, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sbe, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_sxl, // @[RocketCore.scala:134:14] output [7:0] io_ptw_gstatus_zero1, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tsr, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tw, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tvm, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mxr, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sum, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mprv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_fs, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_mpp, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_vs, // @[RocketCore.scala:134:14] output io_ptw_gstatus_spp, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mpie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_ube, // @[RocketCore.scala:134:14] output io_ptw_gstatus_spie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_upie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_hie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_uie, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_0_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_0_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_0_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_1_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_1_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_1_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_2_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_2_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_2_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_3_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_3_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_3_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_4_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_4_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_4_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_5_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_5_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_5_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_6_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_6_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_6_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_7_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_7_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_7_mask, // @[RocketCore.scala:134:14] input io_ptw_perf_pte_miss, // @[RocketCore.scala:134:14] input io_ptw_perf_pte_hit, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_0_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_0_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_1_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_1_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_1_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_2_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_2_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_2_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_3_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_3_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_3_value, // @[RocketCore.scala:134:14] input io_ptw_clock_enabled, // @[RocketCore.scala:134:14] output io_fpu_hartid, // @[RocketCore.scala:134:14] output [63:0] io_fpu_time, // @[RocketCore.scala:134:14] output [31:0] io_fpu_inst, // @[RocketCore.scala:134:14] output [63:0] io_fpu_fromint_data, // @[RocketCore.scala:134:14] output [2:0] io_fpu_fcsr_rm, // @[RocketCore.scala:134:14] input io_fpu_fcsr_flags_valid, // @[RocketCore.scala:134:14] input [4:0] io_fpu_fcsr_flags_bits, // @[RocketCore.scala:134:14] input [63:0] io_fpu_store_data, // @[RocketCore.scala:134:14] input [63:0] io_fpu_toint_data, // @[RocketCore.scala:134:14] output io_fpu_ll_resp_val, // @[RocketCore.scala:134:14] output [2:0] io_fpu_ll_resp_type, // @[RocketCore.scala:134:14] output [4:0] io_fpu_ll_resp_tag, // @[RocketCore.scala:134:14] output [63:0] io_fpu_ll_resp_data, // @[RocketCore.scala:134:14] output io_fpu_valid, // @[RocketCore.scala:134:14] input io_fpu_fcsr_rdy, // @[RocketCore.scala:134:14] input io_fpu_nack_mem, // @[RocketCore.scala:134:14] input io_fpu_illegal_rm, // @[RocketCore.scala:134:14] output io_fpu_killx, // @[RocketCore.scala:134:14] output io_fpu_killm, // @[RocketCore.scala:134:14] input io_fpu_dec_ldst, // @[RocketCore.scala:134:14] input io_fpu_dec_wen, // @[RocketCore.scala:134:14] input io_fpu_dec_ren1, // @[RocketCore.scala:134:14] input io_fpu_dec_ren2, // @[RocketCore.scala:134:14] input io_fpu_dec_ren3, // @[RocketCore.scala:134:14] input io_fpu_dec_swap12, // @[RocketCore.scala:134:14] input io_fpu_dec_swap23, // @[RocketCore.scala:134:14] input [1:0] io_fpu_dec_typeTagIn, // @[RocketCore.scala:134:14] input [1:0] io_fpu_dec_typeTagOut, // @[RocketCore.scala:134:14] input io_fpu_dec_fromint, // @[RocketCore.scala:134:14] input io_fpu_dec_toint, // @[RocketCore.scala:134:14] input io_fpu_dec_fastpipe, // @[RocketCore.scala:134:14] input io_fpu_dec_fma, // @[RocketCore.scala:134:14] input io_fpu_dec_div, // @[RocketCore.scala:134:14] input io_fpu_dec_sqrt, // @[RocketCore.scala:134:14] input io_fpu_dec_wflags, // @[RocketCore.scala:134:14] input io_fpu_dec_vec, // @[RocketCore.scala:134:14] input io_fpu_sboard_set, // @[RocketCore.scala:134:14] input io_fpu_sboard_clr, // @[RocketCore.scala:134:14] input [4:0] io_fpu_sboard_clra, // @[RocketCore.scala:134:14] output io_fpu_keep_clock_enabled, // @[RocketCore.scala:134:14] output io_trace_insns_0_valid, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_iaddr, // @[RocketCore.scala:134:14] output [31:0] io_trace_insns_0_insn, // @[RocketCore.scala:134:14] output [2:0] io_trace_insns_0_priv, // @[RocketCore.scala:134:14] output io_trace_insns_0_exception, // @[RocketCore.scala:134:14] output io_trace_insns_0_interrupt, // @[RocketCore.scala:134:14] output [63:0] io_trace_insns_0_cause, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_tval, // @[RocketCore.scala:134:14] output [63:0] io_trace_time, // @[RocketCore.scala:134:14] output io_bpwatch_0_valid_0, // @[RocketCore.scala:134:14] output [2:0] io_bpwatch_0_action, // @[RocketCore.scala:134:14] output io_wfi // @[RocketCore.scala:134:14] ); wire ll_arb_io_out_ready; // @[RocketCore.scala:782:23, :809:44, :810:25] wire id_ctrl_fence; // @[RocketCore.scala:321:21] wire id_ctrl_rocc; // @[RocketCore.scala:321:21] wire io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_valid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7] wire _ll_arb_io_in_0_ready; // @[RocketCore.scala:776:22] wire _ll_arb_io_out_valid; // @[RocketCore.scala:776:22] wire [4:0] _ll_arb_io_out_bits_tag; // @[RocketCore.scala:776:22] wire _div_io_req_ready; // @[RocketCore.scala:511:19] wire _div_io_resp_valid; // @[RocketCore.scala:511:19] wire [63:0] _div_io_resp_bits_data; // @[RocketCore.scala:511:19] wire [4:0] _div_io_resp_bits_tag; // @[RocketCore.scala:511:19] wire [63:0] _alu_io_adder_out; // @[RocketCore.scala:504:19] wire _alu_io_cmp_out; // @[RocketCore.scala:504:19] wire _bpu_io_xcpt_if; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_ld; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_st; // @[RocketCore.scala:414:19] wire _bpu_io_debug_if; // @[RocketCore.scala:414:19] wire _bpu_io_debug_ld; // @[RocketCore.scala:414:19] wire _bpu_io_debug_st; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_rvalid_0; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_wvalid_0; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_ivalid_0; // @[RocketCore.scala:414:19] wire [63:0] _csr_io_rw_rdata; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_csr; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_read_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_csr_stall; // @[RocketCore.scala:341:19] wire _csr_io_eret; // @[RocketCore.scala:341:19] wire _csr_io_singleStep; // @[RocketCore.scala:341:19] wire _csr_io_status_debug; // @[RocketCore.scala:341:19] wire _csr_io_status_cease; // @[RocketCore.scala:341:19] wire _csr_io_status_wfi; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_status_isa; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_dprv; // @[RocketCore.scala:341:19] wire _csr_io_status_dv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_prv; // @[RocketCore.scala:341:19] wire _csr_io_status_v; // @[RocketCore.scala:341:19] wire _csr_io_status_sd; // @[RocketCore.scala:341:19] wire _csr_io_status_mpv; // @[RocketCore.scala:341:19] wire _csr_io_status_gva; // @[RocketCore.scala:341:19] wire _csr_io_status_tsr; // @[RocketCore.scala:341:19] wire _csr_io_status_tw; // @[RocketCore.scala:341:19] wire _csr_io_status_tvm; // @[RocketCore.scala:341:19] wire _csr_io_status_mxr; // @[RocketCore.scala:341:19] wire _csr_io_status_sum; // @[RocketCore.scala:341:19] wire _csr_io_status_mprv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_fs; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_mpp; // @[RocketCore.scala:341:19] wire _csr_io_status_spp; // @[RocketCore.scala:341:19] wire _csr_io_status_mpie; // @[RocketCore.scala:341:19] wire _csr_io_status_spie; // @[RocketCore.scala:341:19] wire _csr_io_status_mie; // @[RocketCore.scala:341:19] wire _csr_io_status_sie; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_evec; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_time; // @[RocketCore.scala:341:19] wire _csr_io_interrupt; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_interrupt_cause; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_dmode; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_action; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_bp_0_control_tmatch; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_m; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_s; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_u; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_x; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_w; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_r; // @[RocketCore.scala:341:19] wire [38:0] _csr_io_bp_0_address; // @[RocketCore.scala:341:19] wire [47:0] _csr_io_bp_0_textra_pad2; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_textra_pad1; // @[RocketCore.scala:341:19] wire _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_valid; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_trace_0_iaddr; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_trace_0_insn; // @[RocketCore.scala:341:19] wire [2:0] _csr_io_trace_0_priv; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_exception; // @[RocketCore.scala:341:19] wire [39:0] _ibuf_io_pc; // @[RocketCore.scala:311:20] wire [1:0] _ibuf_io_btb_resp_cfiType; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_taken; // @[RocketCore.scala:311:20] wire [1:0] _ibuf_io_btb_resp_mask; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_bridx; // @[RocketCore.scala:311:20] wire [38:0] _ibuf_io_btb_resp_target; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_btb_resp_entry; // @[RocketCore.scala:311:20] wire [7:0] _ibuf_io_btb_resp_bht_history; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_bht_value; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20] wire io_hartid_0 = io_hartid; // @[RocketCore.scala:153:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[RocketCore.scala:153:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[RocketCore.scala:153:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[RocketCore.scala:153:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[RocketCore.scala:153:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[RocketCore.scala:153:7] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_btb_cfiType_0 = io_imem_resp_bits_btb_cfiType; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_taken_0 = io_imem_resp_bits_btb_taken; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_btb_mask_0 = io_imem_resp_bits_btb_mask; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_bridx_0 = io_imem_resp_bits_btb_bridx; // @[RocketCore.scala:153:7] wire [38:0] io_imem_resp_bits_btb_target_0 = io_imem_resp_bits_btb_target; // @[RocketCore.scala:153:7] wire [4:0] io_imem_resp_bits_btb_entry_0 = io_imem_resp_bits_btb_entry; // @[RocketCore.scala:153:7] wire [7:0] io_imem_resp_bits_btb_bht_history_0 = io_imem_resp_bits_btb_bht_history; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_bht_value_0 = io_imem_resp_bits_btb_bht_value; // @[RocketCore.scala:153:7] wire [39:0] io_imem_resp_bits_pc_0 = io_imem_resp_bits_pc; // @[RocketCore.scala:153:7] wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_mask_0 = io_imem_resp_bits_mask; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_pf_inst_0 = io_imem_resp_bits_xcpt_pf_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_gf_inst_0 = io_imem_resp_bits_xcpt_gf_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_ae_inst_0 = io_imem_resp_bits_xcpt_ae_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_replay_0 = io_imem_resp_bits_replay; // @[RocketCore.scala:153:7] wire io_imem_gpa_valid_0 = io_imem_gpa_valid; // @[RocketCore.scala:153:7] wire [39:0] io_imem_gpa_bits_0 = io_imem_gpa_bits; // @[RocketCore.scala:153:7] wire io_imem_gpa_is_pte_0 = io_imem_gpa_is_pte; // @[RocketCore.scala:153:7] wire [39:0] io_imem_npc_0 = io_imem_npc; // @[RocketCore.scala:153:7] wire io_imem_perf_acquire_0 = io_imem_perf_acquire; // @[RocketCore.scala:153:7] wire io_imem_perf_tlbMiss_0 = io_imem_perf_tlbMiss; // @[RocketCore.scala:153:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[RocketCore.scala:153:7] wire io_dmem_s2_nack_0 = io_dmem_s2_nack; // @[RocketCore.scala:153:7] wire io_dmem_s2_nack_cause_raw_0 = io_dmem_s2_nack_cause_raw; // @[RocketCore.scala:153:7] wire io_dmem_s2_uncached_0 = io_dmem_s2_uncached; // @[RocketCore.scala:153:7] wire [31:0] io_dmem_s2_paddr_0 = io_dmem_s2_paddr; // @[RocketCore.scala:153:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_resp_bits_addr_0 = io_dmem_resp_bits_addr; // @[RocketCore.scala:153:7] wire [6:0] io_dmem_resp_bits_tag_0 = io_dmem_resp_bits_tag; // @[RocketCore.scala:153:7] wire [4:0] io_dmem_resp_bits_cmd_0 = io_dmem_resp_bits_cmd; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_resp_bits_size_0 = io_dmem_resp_bits_size; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_signed_0 = io_dmem_resp_bits_signed; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_resp_bits_dprv_0 = io_dmem_resp_bits_dprv; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_dv_0 = io_dmem_resp_bits_dv; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_resp_bits_mask_0 = io_dmem_resp_bits_mask; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_replay_0 = io_dmem_resp_bits_replay; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_has_data_0 = io_dmem_resp_bits_has_data; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_word_bypass_0 = io_dmem_resp_bits_data_word_bypass; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_raw_0 = io_dmem_resp_bits_data_raw; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_store_data_0 = io_dmem_resp_bits_store_data; // @[RocketCore.scala:153:7] wire io_dmem_replay_next_0 = io_dmem_replay_next; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ma_ld_0 = io_dmem_s2_xcpt_ma_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ma_st_0 = io_dmem_s2_xcpt_ma_st; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_pf_ld_0 = io_dmem_s2_xcpt_pf_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_pf_st_0 = io_dmem_s2_xcpt_pf_st; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ae_ld_0 = io_dmem_s2_xcpt_ae_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ae_st_0 = io_dmem_s2_xcpt_ae_st; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_s2_gpa_0 = io_dmem_s2_gpa; // @[RocketCore.scala:153:7] wire io_dmem_ordered_0 = io_dmem_ordered; // @[RocketCore.scala:153:7] wire io_dmem_store_pending_0 = io_dmem_store_pending; // @[RocketCore.scala:153:7] wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[RocketCore.scala:153:7] wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[RocketCore.scala:153:7] wire io_dmem_perf_grant_0 = io_dmem_perf_grant; // @[RocketCore.scala:153:7] wire io_dmem_perf_tlbMiss_0 = io_dmem_perf_tlbMiss; // @[RocketCore.scala:153:7] wire io_dmem_perf_blocked_0 = io_dmem_perf_blocked; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptStoreThenLoad_0 = io_dmem_perf_canAcceptStoreThenLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptStoreThenRMW_0 = io_dmem_perf_canAcceptStoreThenRMW; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptLoadThenLoad_0 = io_dmem_perf_canAcceptLoadThenLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_storeBufferEmptyAfterLoad_0 = io_dmem_perf_storeBufferEmptyAfterLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_storeBufferEmptyAfterStore_0 = io_dmem_perf_storeBufferEmptyAfterStore; // @[RocketCore.scala:153:7] wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[RocketCore.scala:153:7] wire io_ptw_perf_pte_hit_0 = io_ptw_perf_pte_hit; // @[RocketCore.scala:153:7] wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[RocketCore.scala:153:7] wire io_fpu_fcsr_flags_valid_0 = io_fpu_fcsr_flags_valid; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_fcsr_flags_bits_0 = io_fpu_fcsr_flags_bits; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_store_data_0 = io_fpu_store_data; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_toint_data_0 = io_fpu_toint_data; // @[RocketCore.scala:153:7] wire io_fpu_fcsr_rdy_0 = io_fpu_fcsr_rdy; // @[RocketCore.scala:153:7] wire io_fpu_nack_mem_0 = io_fpu_nack_mem; // @[RocketCore.scala:153:7] wire io_fpu_illegal_rm_0 = io_fpu_illegal_rm; // @[RocketCore.scala:153:7] wire io_fpu_dec_ldst_0 = io_fpu_dec_ldst; // @[RocketCore.scala:153:7] wire io_fpu_dec_wen_0 = io_fpu_dec_wen; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren1_0 = io_fpu_dec_ren1; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren2_0 = io_fpu_dec_ren2; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren3_0 = io_fpu_dec_ren3; // @[RocketCore.scala:153:7] wire io_fpu_dec_swap12_0 = io_fpu_dec_swap12; // @[RocketCore.scala:153:7] wire io_fpu_dec_swap23_0 = io_fpu_dec_swap23; // @[RocketCore.scala:153:7] wire [1:0] io_fpu_dec_typeTagIn_0 = io_fpu_dec_typeTagIn; // @[RocketCore.scala:153:7] wire [1:0] io_fpu_dec_typeTagOut_0 = io_fpu_dec_typeTagOut; // @[RocketCore.scala:153:7] wire io_fpu_dec_fromint_0 = io_fpu_dec_fromint; // @[RocketCore.scala:153:7] wire io_fpu_dec_toint_0 = io_fpu_dec_toint; // @[RocketCore.scala:153:7] wire io_fpu_dec_fastpipe_0 = io_fpu_dec_fastpipe; // @[RocketCore.scala:153:7] wire io_fpu_dec_fma_0 = io_fpu_dec_fma; // @[RocketCore.scala:153:7] wire io_fpu_dec_div_0 = io_fpu_dec_div; // @[RocketCore.scala:153:7] wire io_fpu_dec_sqrt_0 = io_fpu_dec_sqrt; // @[RocketCore.scala:153:7] wire io_fpu_dec_wflags_0 = io_fpu_dec_wflags; // @[RocketCore.scala:153:7] wire io_fpu_dec_vec_0 = io_fpu_dec_vec; // @[RocketCore.scala:153:7] wire io_fpu_sboard_set_0 = io_fpu_sboard_set; // @[RocketCore.scala:153:7] wire io_fpu_sboard_clr_0 = io_fpu_sboard_clr; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_sboard_clra_0 = io_fpu_sboard_clra; // @[RocketCore.scala:153:7] wire coreMonitorBundle_clock = clock; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_reset = reset; // @[RocketCore.scala:1186:31] wire xrfWriteBundle_clock = clock; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_reset = reset; // @[RocketCore.scala:1249:28] wire io_imem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7] wire io_dmem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7] wire clock_en = 1'h1; // @[RocketCore.scala:153:7, :163:29] wire _id_npc_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _id_npc_b11_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1345:23] wire _id_illegal_insn_T_10 = 1'h1; // @[RocketCore.scala:153:7, :384:73] wire _id_illegal_insn_T_15 = 1'h1; // @[RocketCore.scala:153:7, :385:55] wire _mem_br_target_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _mem_br_target_b19_12_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1343:43] wire _mem_br_target_b19_12_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1343:36] wire _mem_br_target_b11_T_6 = 1'h1; // @[RocketCore.scala:153:7, :1346:23] wire _mem_br_target_b4_1_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1349:41] wire _mem_br_target_b4_1_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1349:34] wire _mem_br_target_b19_12_T_5 = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _mem_br_target_b11_T_14 = 1'h1; // @[RocketCore.scala:153:7, :1345:23] wire _wb_reg_xcpt_T_2 = 1'h1; // @[RocketCore.scala:153:7, :707:45] wire _replay_wb_rocc_T_1 = 1'h1; // @[RocketCore.scala:153:7, :758:56] wire _rocc_blocked_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1029:31] wire io_imem_btb_update_bits_taken = 1'h0; // @[RocketCore.scala:153:7] wire io_imem_ras_update_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtw = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_hu = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_perf_l2miss = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_perf_l2hit = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_resp_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_resp_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_signed = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_dv = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_resp = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s1_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_nack = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_nack_cause_raw = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_uncached = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_signed = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_dv = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_replay = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_has_data = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_replay_next = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ma_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_pf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ae_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_ordered = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_store_pending = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_acquire = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_release = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_grant = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_tlbMiss = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_blocked = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_keep_clock_enabled = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_clock_enabled = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_busy = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_interrupt = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_exception = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_rvalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_wvalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_ivalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_cease = 1'h0; // @[RocketCore.scala:153:7] wire io_traceStall = 1'h0; // @[RocketCore.scala:153:7] wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_5 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_6 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_7 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_8 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_9 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_10 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_11 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_12 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_13 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_14 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_15 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_16 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_17 = 1'h0; // @[Events.scala:13:33] wire hits_0 = 1'h0; // @[Events.scala:13:25] wire hits_1 = 1'h0; // @[Events.scala:13:25] wire hits_2 = 1'h0; // @[Events.scala:13:25] wire hits_3 = 1'h0; // @[Events.scala:13:25] wire hits_4 = 1'h0; // @[Events.scala:13:25] wire hits_5 = 1'h0; // @[Events.scala:13:25] wire hits_6 = 1'h0; // @[Events.scala:13:25] wire hits_7 = 1'h0; // @[Events.scala:13:25] wire hits_8 = 1'h0; // @[Events.scala:13:25] wire hits_9 = 1'h0; // @[Events.scala:13:25] wire hits_10 = 1'h0; // @[Events.scala:13:25] wire hits_11 = 1'h0; // @[Events.scala:13:25] wire hits_12 = 1'h0; // @[Events.scala:13:25] wire hits_13 = 1'h0; // @[Events.scala:13:25] wire hits_14 = 1'h0; // @[Events.scala:13:25] wire hits_15 = 1'h0; // @[Events.scala:13:25] wire hits_16 = 1'h0; // @[Events.scala:13:25] wire hits_17 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_1_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_5 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_6 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_7 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_8 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_9 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_10 = 1'h0; // @[Events.scala:13:33] wire hits_1_0 = 1'h0; // @[Events.scala:13:25] wire hits_1_1 = 1'h0; // @[Events.scala:13:25] wire hits_1_2 = 1'h0; // @[Events.scala:13:25] wire hits_1_3 = 1'h0; // @[Events.scala:13:25] wire hits_1_4 = 1'h0; // @[Events.scala:13:25] wire hits_1_5 = 1'h0; // @[Events.scala:13:25] wire hits_1_6 = 1'h0; // @[Events.scala:13:25] wire hits_1_7 = 1'h0; // @[Events.scala:13:25] wire hits_1_8 = 1'h0; // @[Events.scala:13:25] wire hits_1_9 = 1'h0; // @[Events.scala:13:25] wire hits_1_10 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_2_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_5 = 1'h0; // @[Events.scala:13:33] wire hits_2_0 = 1'h0; // @[Events.scala:13:25] wire hits_2_1 = 1'h0; // @[Events.scala:13:25] wire hits_2_2 = 1'h0; // @[Events.scala:13:25] wire hits_2_3 = 1'h0; // @[Events.scala:13:25] wire hits_2_4 = 1'h0; // @[Events.scala:13:25] wire hits_2_5 = 1'h0; // @[Events.scala:13:25] wire id_ctrl_vec = 1'h0; // @[RocketCore.scala:321:21] wire _id_rs_T_1 = 1'h0; // @[RocketCore.scala:1326:33] wire _id_rs_T_6 = 1'h0; // @[RocketCore.scala:1326:33] wire _id_npc_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _id_npc_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _id_npc_b19_12_T_1 = 1'h0; // @[RocketCore.scala:1343:43] wire _id_npc_b19_12_T_2 = 1'h0; // @[RocketCore.scala:1343:36] wire _id_npc_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _id_npc_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _id_npc_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _id_npc_b11_T_6 = 1'h0; // @[RocketCore.scala:1346:23] wire _id_npc_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _id_npc_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _id_npc_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _id_npc_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _id_npc_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _id_npc_b4_1_T_2 = 1'h0; // @[RocketCore.scala:1349:41] wire _id_npc_b4_1_T_3 = 1'h0; // @[RocketCore.scala:1349:34] wire _id_npc_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _id_npc_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _id_npc_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _id_npc_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _id_npc_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _id_npc_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire id_npc_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire id_set_vconfig = 1'h0; // @[RocketCore.scala:347:120] wire _id_illegal_insn_T_16 = 1'h0; // @[RocketCore.scala:385:19] wire _id_illegal_insn_T_26 = 1'h0; // @[RocketCore.scala:388:23] wire _id_illegal_insn_T_28 = 1'h0; // @[RocketCore.scala:389:23] wire _id_illegal_insn_T_30 = 1'h0; // @[RocketCore.scala:390:22] wire id_rocc_busy = 1'h0; // @[RocketCore.scala:405:34] wire _id_csr_rocc_write_T = 1'h0; // @[RocketCore.scala:408:87] wire id_csr_rocc_write = 1'h0; // @[RocketCore.scala:408:100] wire _id_do_fence_T_1 = 1'h0; // @[RocketCore.scala:410:46] wire _id_do_fence_T_2 = 1'h0; // @[RocketCore.scala:411:17] wire _id_do_fence_T_3 = 1'h0; // @[RocketCore.scala:410:86] wire _ex_reg_hls_T = 1'h0; // @[RocketCore.scala:553:37] wire _ex_reg_hls_T_6 = 1'h0; // @[RocketCore.scala:553:55] wire _ex_reg_mem_size_T = 1'h0; // @[RocketCore.scala:554:46] wire _ex_reg_set_vconfig_T_1 = 1'h0; // @[RocketCore.scala:591:42] wire _replay_ex_structural_T_5 = 1'h0; // @[RocketCore.scala:599:45] wire _replay_ex_structural_T_6 = 1'h0; // @[RocketCore.scala:599:42] wire _mem_br_target_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_br_target_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_br_target_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_br_target_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_br_target_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_br_target_b11_T_3 = 1'h0; // @[RocketCore.scala:1345:23] wire _mem_br_target_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_br_target_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_br_target_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_br_target_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_br_target_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_br_target_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_br_target_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_br_target_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_br_target_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_br_target_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_br_target_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_br_target_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _mem_br_target_sign_T_3 = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_br_target_b30_20_T_3 = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_br_target_b19_12_T_6 = 1'h0; // @[RocketCore.scala:1343:43] wire _mem_br_target_b19_12_T_7 = 1'h0; // @[RocketCore.scala:1343:36] wire _mem_br_target_b11_T_11 = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_br_target_b11_T_12 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_br_target_b11_T_13 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_br_target_b11_T_17 = 1'h0; // @[RocketCore.scala:1346:23] wire _mem_br_target_b10_5_T_4 = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_br_target_b10_5_T_5 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_br_target_b10_5_T_6 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_br_target_b4_1_T_10 = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_br_target_b4_1_T_11 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_br_target_b4_1_T_12 = 1'h0; // @[RocketCore.scala:1349:41] wire _mem_br_target_b4_1_T_13 = 1'h0; // @[RocketCore.scala:1349:34] wire _mem_br_target_b4_1_T_15 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_br_target_b0_T_8 = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_br_target_b0_T_10 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_br_target_b0_T_12 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_br_target_b0_T_14 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_br_target_b0_T_15 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_br_target_b0_1 = 1'h0; // @[RocketCore.scala:1351:17] wire vec_kill_mem = 1'h0; // @[RocketCore.scala:697:52] wire vec_kill_all = 1'h0; // @[RocketCore.scala:698:36] wire replay_wb_csr = 1'h0; // @[RocketCore.scala:759:42] wire replay_wb_vec = 1'h0; // @[RocketCore.scala:760:36] wire _htval_valid_dmem_T_2 = 1'h0; // @[RocketCore.scala:857:83] wire _htval_valid_dmem_T_3 = 1'h0; // @[RocketCore.scala:857:54] wire htval_valid_dmem = 1'h0; // @[RocketCore.scala:857:87] wire _mhtinst_read_pseudo_T_1 = 1'h0; // @[RocketCore.scala:862:98] wire _id_vconfig_hazard_T = 1'h0; // @[RocketCore.scala:1003:19] wire id_vconfig_hazard = 1'h0; // @[RocketCore.scala:1002:39] wire _ctrl_stalld_T_12 = 1'h0; // @[RocketCore.scala:1036:15] wire _ctrl_stalld_T_13 = 1'h0; // @[RocketCore.scala:1036:46] wire _ctrl_stalld_T_28 = 1'h0; // @[RocketCore.scala:1041:5] wire _io_rocc_exception_T = 1'h0; // @[RocketCore.scala:1157:52] wire _io_rocc_exception_T_1 = 1'h0; // @[RocketCore.scala:1157:32] wire _io_cease_T = 1'h0; // @[RocketCore.scala:1166:38] wire _io_cease_T_1 = 1'h0; // @[RocketCore.scala:1166:35] wire coreMonitorBundle_wrenf = 1'h0; // @[RocketCore.scala:1186:31] wire xrfWriteBundle_excpt = 1'h0; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_valid = 1'h0; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_wrenf = 1'h0; // @[RocketCore.scala:1249:28] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[RocketCore.scala:153:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[RocketCore.scala:153:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[RocketCore.scala:153:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_ras_update_bits_cfiType = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_vs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_req_bits_size = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_resp_bits_size = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] _htval_valid_dmem_T_1 = 2'h0; // @[RocketCore.scala:857:76] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[RocketCore.scala:153:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[RocketCore.scala:153:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[RocketCore.scala:153:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_resp_bits_rd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] _csr_io_fcsr_flags_bits_T_2 = 5'h0; // @[RocketCore.scala:839:116] wire [4:0] _csr_io_fcsr_flags_bits_T_3 = 5'h0; // @[RocketCore.scala:839:110] wire [4:0] xrfWriteBundle_rd0src = 5'h0; // @[RocketCore.scala:1249:28] wire [4:0] xrfWriteBundle_rd1src = 5'h0; // @[RocketCore.scala:1249:28] wire [39:0] io_rocc_mem_req_bits_addr = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_s2_gpa = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] htval_dmem = 40'h0; // @[RocketCore.scala:858:25] wire [31:0] io_reset_vector = 32'h0; // @[RocketCore.scala:153:7] wire [31:0] io_rocc_mem_s2_paddr = 32'h0; // @[RocketCore.scala:153:7] wire [31:0] xrfWriteBundle_inst = 32'h0; // @[RocketCore.scala:1249:28] wire [38:0] io_imem_ras_update_bits_returnAddr = 39'h0; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_s1_data_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] xrfWriteBundle_pc = 64'h0; // @[RocketCore.scala:1249:28] wire [63:0] xrfWriteBundle_rd0val = 64'h0; // @[RocketCore.scala:1249:28] wire [63:0] xrfWriteBundle_rd1val = 64'h0; // @[RocketCore.scala:1249:28] wire [1:0] io_ptw_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_v_sew = 3'h0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_mem_req_bits_tag = 7'h0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0; // @[RocketCore.scala:153:7] wire io_fpu_hartid_0 = io_hartid_0; // @[RocketCore.scala:153:7] wire take_pc_mem_wb; // @[RocketCore.scala:307:35] wire [39:0] _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:1051:8] wire _io_imem_req_bits_speculative_T; // @[RocketCore.scala:1049:35] wire _io_imem_sfence_valid_T; // @[RocketCore.scala:1060:40] wire io_ptw_sfence_valid_0 = io_imem_sfence_valid_0; // @[RocketCore.scala:153:7] wire _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:1061:45] wire io_ptw_sfence_bits_rs1_0 = io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7] wire _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:1062:45] wire io_ptw_sfence_bits_rs2_0 = io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7] wire [38:0] io_ptw_sfence_bits_addr_0 = io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_asid_0 = io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_hv_0 = io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_hg_0 = io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7] wire _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:1071:77] wire [38:0] _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:1080:33] wire [38:0] io_imem_bht_update_bits_pc_0 = io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7] wire mem_cfi; // @[RocketCore.scala:625:50] wire [1:0] _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:1074:8] wire _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:1084:45] wire mem_wrong_npc; // @[RocketCore.scala:621:8] wire _io_imem_flush_icache_T_2; // @[RocketCore.scala:1054:59] wire _io_dmem_req_valid_T; // @[RocketCore.scala:1130:41] wire [39:0] _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:1295:8] wire _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:1136:30] wire [1:0] _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:1140:31] wire _io_dmem_req_bits_dv_T; // @[RocketCore.scala:1141:37] wire _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:1142:56] wire _io_dmem_s1_kill_T_2; // @[RocketCore.scala:1151:68] wire [63:0] _io_dmem_s1_data_data_T; // @[RocketCore.scala:1148:63] wire [63:0] io_fpu_ll_resp_data_0 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7] wire [63:0] _rf_wdata_T_1 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7, :819:78] wire [63:0] dcache_bypass_data = io_dmem_resp_bits_data_word_bypass_0; // @[RocketCore.scala:153:7, :449:62] wire _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:1154:70] wire [63:0] ex_rs_0; // @[RocketCore.scala:469:14] wire _csr_io_fcsr_flags_valid_T = io_fpu_fcsr_flags_valid_0; // @[RocketCore.scala:153:7, :838:54] wire _io_fpu_ll_resp_val_T; // @[RocketCore.scala:1099:41] wire [4:0] dmem_resp_waddr; // @[RocketCore.scala:767:46] wire _io_fpu_valid_T_1; // @[RocketCore.scala:1094:31] wire _id_illegal_insn_T_11 = io_fpu_illegal_rm_0; // @[RocketCore.scala:153:7, :384:70] wire ctrl_killx; // @[RocketCore.scala:602:48] wire killm_common; // @[RocketCore.scala:700:68] wire _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59] wire _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:1156:53] wire [6:0] _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:1159:48] wire [6:0] _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:1159:48] wire [39:0] io_imem_req_bits_pc_0; // @[RocketCore.scala:153:7] wire io_imem_req_bits_speculative_0; // @[RocketCore.scala:153:7] wire io_imem_req_valid_0; // @[RocketCore.scala:153:7] wire io_imem_resp_ready_0; // @[RocketCore.scala:153:7] wire [7:0] io_imem_btb_update_bits_prediction_bht_history_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_bht_value_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_prediction_cfiType_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_taken_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_prediction_mask_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_bridx_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_prediction_target_0; // @[RocketCore.scala:153:7] wire [4:0] io_imem_btb_update_bits_prediction_entry_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_target_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_isValid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_cfiType_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_valid_0; // @[RocketCore.scala:153:7] wire [7:0] io_imem_bht_update_bits_prediction_history_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_prediction_value_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_branch_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_taken_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_mispredict_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_valid_0; // @[RocketCore.scala:153:7] wire io_imem_might_request_0; // @[RocketCore.scala:153:7] wire io_imem_flush_icache_0; // @[RocketCore.scala:153:7] wire io_imem_progress_0; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_req_bits_addr_0; // @[RocketCore.scala:153:7] wire [6:0] io_dmem_req_bits_tag_0; // @[RocketCore.scala:153:7] wire [4:0] io_dmem_req_bits_cmd_0; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_req_bits_size_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_signed_0; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_req_bits_dprv_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_dv_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_resp_0; // @[RocketCore.scala:153:7] wire io_dmem_req_valid_0; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_s1_data_data_0; // @[RocketCore.scala:153:7] wire io_dmem_s1_kill_0; // @[RocketCore.scala:153:7] wire io_dmem_keep_clock_enabled_0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_ptbr_mode_0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_ptbr_ppn_0; // @[RocketCore.scala:153:7] wire io_ptw_status_debug_0; // @[RocketCore.scala:153:7] wire io_ptw_status_cease_0; // @[RocketCore.scala:153:7] wire io_ptw_status_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_status_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_dprv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_prv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_v_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sd_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mpv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tsr_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tw_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tvm_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mxr_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sum_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_mpp_0; // @[RocketCore.scala:153:7] wire io_ptw_status_spp_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mpie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_spie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sie_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_spvp_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_spv_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_debug_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_cease_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_gstatus_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_dprv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_prv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_v_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sd_0; // @[RocketCore.scala:153:7] wire [22:0] io_ptw_gstatus_zero2_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mpv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mbe_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sbe_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_sxl_0; // @[RocketCore.scala:153:7] wire [7:0] io_ptw_gstatus_zero1_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tsr_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tw_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tvm_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mxr_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sum_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_mpp_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_vs_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_spp_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mpie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_ube_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_spie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_upie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_hie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_uie_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_0_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_0_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_0_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_1_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_1_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_1_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_2_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_2_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_2_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_3_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_3_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_3_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_4_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_4_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_4_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_5_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_5_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_5_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_6_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_6_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_6_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_7_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_7_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_7_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_time_0; // @[RocketCore.scala:153:7] wire [31:0] io_fpu_inst_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_fromint_data_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_fcsr_rm_0; // @[RocketCore.scala:153:7] wire io_fpu_ll_resp_val_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_ll_resp_type_0; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7] wire io_fpu_valid_0; // @[RocketCore.scala:153:7] wire io_fpu_killx_0; // @[RocketCore.scala:153:7] wire io_fpu_killm_0; // @[RocketCore.scala:153:7] wire io_fpu_keep_clock_enabled_0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_cmd_bits_inst_funct; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rs2; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rs1; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xd; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xs1; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xs2; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rd; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_cmd_bits_inst_opcode; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_debug; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_cease; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_wfi; // @[RocketCore.scala:153:7] wire [31:0] io_rocc_cmd_bits_status_isa; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_dprv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_dv; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_prv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_v; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sd; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mpv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_gva; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tsr; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tw; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tvm; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mxr; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sum; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mprv; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_fs; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_mpp; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_spp; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mpie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_spie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sie; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_cmd_bits_rs1; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_cmd_bits_rs2; // @[RocketCore.scala:153:7] wire io_rocc_cmd_valid; // @[RocketCore.scala:153:7] wire io_trace_insns_0_valid_0; // @[RocketCore.scala:153:7] wire [39:0] io_trace_insns_0_iaddr_0; // @[RocketCore.scala:153:7] wire [31:0] io_trace_insns_0_insn_0; // @[RocketCore.scala:153:7] wire [2:0] io_trace_insns_0_priv_0; // @[RocketCore.scala:153:7] wire io_trace_insns_0_exception_0; // @[RocketCore.scala:153:7] wire io_trace_insns_0_interrupt_0; // @[RocketCore.scala:153:7] wire [63:0] io_trace_insns_0_cause_0; // @[RocketCore.scala:153:7] wire [39:0] io_trace_insns_0_tval_0; // @[RocketCore.scala:153:7] wire [63:0] io_trace_time_0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_valid_0_0; // @[RocketCore.scala:153:7] wire [2:0] io_bpwatch_0_action_0; // @[RocketCore.scala:153:7] wire io_wfi_0; // @[RocketCore.scala:153:7] reg id_reg_pause; // @[RocketCore.scala:161:25] reg imem_might_request_reg; // @[RocketCore.scala:162:35] assign io_imem_might_request_0 = imem_might_request_reg; // @[RocketCore.scala:153:7, :162:35] reg ex_ctrl_legal; // @[RocketCore.scala:243:20] reg ex_ctrl_fp; // @[RocketCore.scala:243:20] reg ex_ctrl_rocc; // @[RocketCore.scala:243:20] reg ex_ctrl_branch; // @[RocketCore.scala:243:20] reg ex_ctrl_jal; // @[RocketCore.scala:243:20] reg ex_ctrl_jalr; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_alu2; // @[RocketCore.scala:243:20] reg [1:0] ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_imm; // @[RocketCore.scala:243:20] reg ex_ctrl_alu_dw; // @[RocketCore.scala:243:20] reg [4:0] ex_ctrl_alu_fn; // @[RocketCore.scala:243:20] reg ex_ctrl_mem; // @[RocketCore.scala:243:20] wire _ex_sfence_T = ex_ctrl_mem; // @[RocketCore.scala:243:20, :605:29] reg [4:0] ex_ctrl_mem_cmd; // @[RocketCore.scala:243:20] assign io_dmem_req_bits_cmd_0 = ex_ctrl_mem_cmd; // @[RocketCore.scala:153:7, :243:20] reg ex_ctrl_rfs1; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs3; // @[RocketCore.scala:243:20] reg ex_ctrl_wfd; // @[RocketCore.scala:243:20] reg ex_ctrl_mul; // @[RocketCore.scala:243:20] reg ex_ctrl_div; // @[RocketCore.scala:243:20] reg ex_ctrl_wxd; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_csr; // @[RocketCore.scala:243:20] reg ex_ctrl_fence_i; // @[RocketCore.scala:243:20] reg ex_ctrl_fence; // @[RocketCore.scala:243:20] reg ex_ctrl_amo; // @[RocketCore.scala:243:20] reg ex_ctrl_dp; // @[RocketCore.scala:243:20] reg mem_ctrl_legal; // @[RocketCore.scala:244:21] reg mem_ctrl_fp; // @[RocketCore.scala:244:21] reg mem_ctrl_rocc; // @[RocketCore.scala:244:21] reg mem_ctrl_branch; // @[RocketCore.scala:244:21] assign io_imem_bht_update_bits_branch_0 = mem_ctrl_branch; // @[RocketCore.scala:153:7, :244:21] reg mem_ctrl_jal; // @[RocketCore.scala:244:21] reg mem_ctrl_jalr; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs1; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_sel_alu2; // @[RocketCore.scala:244:21] reg [1:0] mem_ctrl_sel_alu1; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_sel_imm; // @[RocketCore.scala:244:21] reg mem_ctrl_alu_dw; // @[RocketCore.scala:244:21] reg [4:0] mem_ctrl_alu_fn; // @[RocketCore.scala:244:21] reg mem_ctrl_mem; // @[RocketCore.scala:244:21] reg [4:0] mem_ctrl_mem_cmd; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs1; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs3; // @[RocketCore.scala:244:21] reg mem_ctrl_wfd; // @[RocketCore.scala:244:21] reg mem_ctrl_mul; // @[RocketCore.scala:244:21] reg mem_ctrl_div; // @[RocketCore.scala:244:21] reg mem_ctrl_wxd; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_csr; // @[RocketCore.scala:244:21] reg mem_ctrl_fence_i; // @[RocketCore.scala:244:21] reg mem_ctrl_fence; // @[RocketCore.scala:244:21] reg mem_ctrl_amo; // @[RocketCore.scala:244:21] reg mem_ctrl_dp; // @[RocketCore.scala:244:21] reg mem_ctrl_vec; // @[RocketCore.scala:244:21] reg wb_ctrl_legal; // @[RocketCore.scala:245:20] reg wb_ctrl_fp; // @[RocketCore.scala:245:20] reg wb_ctrl_rocc; // @[RocketCore.scala:245:20] reg wb_ctrl_branch; // @[RocketCore.scala:245:20] reg wb_ctrl_jal; // @[RocketCore.scala:245:20] reg wb_ctrl_jalr; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs1; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_sel_alu2; // @[RocketCore.scala:245:20] reg [1:0] wb_ctrl_sel_alu1; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_sel_imm; // @[RocketCore.scala:245:20] reg wb_ctrl_alu_dw; // @[RocketCore.scala:245:20] reg [4:0] wb_ctrl_alu_fn; // @[RocketCore.scala:245:20] reg wb_ctrl_mem; // @[RocketCore.scala:245:20] reg [4:0] wb_ctrl_mem_cmd; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs1; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs3; // @[RocketCore.scala:245:20] reg wb_ctrl_wfd; // @[RocketCore.scala:245:20] reg wb_ctrl_mul; // @[RocketCore.scala:245:20] reg wb_ctrl_div; // @[RocketCore.scala:245:20] reg wb_ctrl_wxd; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_csr; // @[RocketCore.scala:245:20] reg wb_ctrl_fence_i; // @[RocketCore.scala:245:20] reg wb_ctrl_fence; // @[RocketCore.scala:245:20] reg wb_ctrl_amo; // @[RocketCore.scala:245:20] reg wb_ctrl_dp; // @[RocketCore.scala:245:20] reg wb_ctrl_vec; // @[RocketCore.scala:245:20] reg ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35] reg ex_reg_valid; // @[RocketCore.scala:248:35] reg ex_reg_rvc; // @[RocketCore.scala:249:35] reg [1:0] ex_reg_btb_resp_cfiType; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_taken; // @[RocketCore.scala:250:35] reg [1:0] ex_reg_btb_resp_mask; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_bridx; // @[RocketCore.scala:250:35] reg [38:0] ex_reg_btb_resp_target; // @[RocketCore.scala:250:35] reg [4:0] ex_reg_btb_resp_entry; // @[RocketCore.scala:250:35] reg [7:0] ex_reg_btb_resp_bht_history; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_bht_value; // @[RocketCore.scala:250:35] reg ex_reg_xcpt; // @[RocketCore.scala:251:35] reg ex_reg_flush_pipe; // @[RocketCore.scala:252:35] reg ex_reg_load_use; // @[RocketCore.scala:253:35] reg [63:0] ex_reg_cause; // @[RocketCore.scala:254:35] wire [63:0] ex_cause = ex_reg_cause; // @[RocketCore.scala:254:35, :1278:50] reg ex_reg_replay; // @[RocketCore.scala:255:26] reg [39:0] ex_reg_pc; // @[RocketCore.scala:256:22] wire [39:0] _ex_op1_T_1 = ex_reg_pc; // @[RocketCore.scala:256:22, :474:24] reg [1:0] ex_reg_mem_size; // @[RocketCore.scala:257:28] assign io_dmem_req_bits_size_0 = ex_reg_mem_size; // @[RocketCore.scala:153:7, :257:28] reg [31:0] ex_reg_inst; // @[RocketCore.scala:259:24] reg [31:0] ex_reg_raw_inst; // @[RocketCore.scala:260:28] reg ex_reg_wphit_0; // @[RocketCore.scala:261:36] reg mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36] reg mem_reg_valid; // @[RocketCore.scala:265:36] reg mem_reg_rvc; // @[RocketCore.scala:266:36] reg [1:0] mem_reg_btb_resp_cfiType; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_cfiType_0 = mem_reg_btb_resp_cfiType; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_taken_0 = mem_reg_btb_resp_taken; // @[RocketCore.scala:153:7, :267:36] wire _mem_direction_misprediction_T = mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36, :627:85] reg [1:0] mem_reg_btb_resp_mask; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_mask_0 = mem_reg_btb_resp_mask; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_bridx; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bridx_0 = mem_reg_btb_resp_bridx; // @[RocketCore.scala:153:7, :267:36] reg [38:0] mem_reg_btb_resp_target; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_target_0 = mem_reg_btb_resp_target; // @[RocketCore.scala:153:7, :267:36] reg [4:0] mem_reg_btb_resp_entry; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_entry_0 = mem_reg_btb_resp_entry; // @[RocketCore.scala:153:7, :267:36] reg [7:0] mem_reg_btb_resp_bht_history; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bht_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36] assign io_imem_bht_update_bits_prediction_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_bht_value; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bht_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36] assign io_imem_bht_update_bits_prediction_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_xcpt; // @[RocketCore.scala:268:36] reg mem_reg_replay; // @[RocketCore.scala:269:36] reg mem_reg_flush_pipe; // @[RocketCore.scala:270:36] reg [63:0] mem_reg_cause; // @[RocketCore.scala:271:36] reg mem_reg_slow_bypass; // @[RocketCore.scala:272:36] wire mem_mem_cmd_bh = mem_reg_slow_bypass; // @[RocketCore.scala:272:36, :995:41] reg mem_reg_load; // @[RocketCore.scala:273:36] reg mem_reg_store; // @[RocketCore.scala:274:36] reg mem_reg_set_vconfig; // @[RocketCore.scala:275:36] reg mem_reg_sfence; // @[RocketCore.scala:276:27] reg [39:0] mem_reg_pc; // @[RocketCore.scala:277:23] wire [39:0] _mem_br_target_T = mem_reg_pc; // @[RocketCore.scala:277:23, :615:34] reg [31:0] mem_reg_inst; // @[RocketCore.scala:278:25] reg [1:0] mem_reg_mem_size; // @[RocketCore.scala:279:29] reg mem_reg_hls_or_dv; // @[RocketCore.scala:280:30] reg [31:0] mem_reg_raw_inst; // @[RocketCore.scala:281:29] reg [63:0] mem_reg_wdata; // @[RocketCore.scala:282:26] wire [63:0] _mem_int_wdata_T_3 = mem_reg_wdata; // @[RocketCore.scala:282:26, :624:111] reg [63:0] mem_reg_rs2; // @[RocketCore.scala:283:24] reg mem_br_taken; // @[RocketCore.scala:284:25] assign io_imem_bht_update_bits_taken_0 = mem_br_taken; // @[RocketCore.scala:153:7, :284:25] wire _take_pc_mem_T_3; // @[RocketCore.scala:629:49] wire take_pc_mem; // @[RocketCore.scala:285:25] reg mem_reg_wphit_0; // @[RocketCore.scala:286:35] reg wb_reg_valid; // @[RocketCore.scala:288:35] reg wb_reg_xcpt; // @[RocketCore.scala:289:35] reg wb_reg_replay; // @[RocketCore.scala:290:35] reg wb_reg_flush_pipe; // @[RocketCore.scala:291:35] reg [63:0] wb_reg_cause; // @[RocketCore.scala:292:35] reg wb_reg_set_vconfig; // @[RocketCore.scala:293:35] reg wb_reg_sfence; // @[RocketCore.scala:294:26] reg [39:0] wb_reg_pc; // @[RocketCore.scala:295:22] reg [1:0] wb_reg_mem_size; // @[RocketCore.scala:296:28] reg wb_reg_hls_or_dv; // @[RocketCore.scala:297:29] reg wb_reg_hfence_v; // @[RocketCore.scala:298:28] assign io_imem_sfence_bits_hv_0 = wb_reg_hfence_v; // @[RocketCore.scala:153:7, :298:28] reg wb_reg_hfence_g; // @[RocketCore.scala:299:28] assign io_imem_sfence_bits_hg_0 = wb_reg_hfence_g; // @[RocketCore.scala:153:7, :299:28] reg [31:0] wb_reg_inst; // @[RocketCore.scala:300:24] wire [31:0] _io_rocc_cmd_bits_inst_WIRE_1 = wb_reg_inst; // @[RocketCore.scala:300:24, :1159:48] reg [31:0] wb_reg_raw_inst; // @[RocketCore.scala:301:28] reg [63:0] wb_reg_wdata; // @[RocketCore.scala:302:25] assign io_rocc_cmd_bits_rs1 = wb_reg_wdata; // @[RocketCore.scala:153:7, :302:25] wire [63:0] _rf_wdata_T_3 = wb_reg_wdata; // @[RocketCore.scala:302:25, :822:21] reg [63:0] wb_reg_rs2; // @[RocketCore.scala:303:23] assign io_rocc_cmd_bits_rs2 = wb_reg_rs2; // @[RocketCore.scala:153:7, :303:23] wire _take_pc_wb_T_2; // @[RocketCore.scala:762:53] wire take_pc_wb; // @[RocketCore.scala:304:24] reg wb_reg_wphit_0; // @[RocketCore.scala:305:35] assign io_bpwatch_0_valid_0_0 = wb_reg_wphit_0; // @[RocketCore.scala:153:7, :305:35] assign take_pc_mem_wb = take_pc_wb \| take_pc_mem; // @[RocketCore.scala:285:25, :304:24, :307:35] assign io_imem_req_valid_0 = take_pc_mem_wb; // @[RocketCore.scala:153:7, :307:35] wire id_ctrl_decoder_0; // @[Decode.scala:50:77] wire id_ctrl_decoder_1; // @[Decode.scala:50:77] wire id_ctrl_decoder_2; // @[Decode.scala:50:77] wire id_ctrl_decoder_3; // @[Decode.scala:50:77] wire _id_illegal_insn_T_32 = id_ctrl_rocc; // @[RocketCore.scala:321:21, :391:18] wire id_ctrl_decoder_4; // @[Decode.scala:50:77] wire id_ctrl_decoder_5; // @[Decode.scala:50:77] wire id_ctrl_decoder_6; // @[Decode.scala:50:77] wire id_ctrl_decoder_7; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_8; // @[Decode.scala:50:77] wire [1:0] id_ctrl_decoder_9; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_10; // @[Decode.scala:50:77] wire id_ctrl_decoder_11; // @[Decode.scala:50:77] wire [4:0] id_ctrl_decoder_12; // @[Decode.scala:50:77] wire id_ctrl_decoder_13; // @[Decode.scala:50:77] wire [4:0] id_ctrl_decoder_14; // @[Decode.scala:50:77] wire id_ctrl_decoder_15; // @[Decode.scala:50:77] wire id_ctrl_decoder_16; // @[Decode.scala:50:77] wire id_ctrl_decoder_17; // @[Decode.scala:50:77] wire id_ctrl_decoder_18; // @[Decode.scala:50:77] wire id_ctrl_decoder_19; // @[Decode.scala:50:77] wire id_ctrl_decoder_20; // @[Decode.scala:50:77] wire id_ctrl_decoder_21; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_22; // @[Decode.scala:50:77] wire id_ctrl_decoder_23; // @[Decode.scala:50:77] wire id_ctrl_decoder_24; // @[Decode.scala:50:77] wire id_ctrl_decoder_25; // @[Decode.scala:50:77] wire _id_do_fence_T = id_ctrl_fence; // @[RocketCore.scala:321:21, :410:64] wire id_ctrl_decoder_26; // @[Decode.scala:50:77] wire id_ctrl_legal; // @[RocketCore.scala:321:21] wire id_ctrl_fp; // @[RocketCore.scala:321:21] wire id_ctrl_branch; // @[RocketCore.scala:321:21] wire id_ctrl_jal; // @[RocketCore.scala:321:21] wire id_ctrl_jalr; // @[RocketCore.scala:321:21] wire id_ctrl_rxs2; // @[RocketCore.scala:321:21] wire id_ctrl_rxs1; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_sel_alu2; // @[RocketCore.scala:321:21] wire [1:0] id_ctrl_sel_alu1; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_sel_imm; // @[RocketCore.scala:321:21] wire id_ctrl_alu_dw; // @[RocketCore.scala:321:21] wire [4:0] id_ctrl_alu_fn; // @[RocketCore.scala:321:21] wire id_ctrl_mem; // @[RocketCore.scala:321:21] wire [4:0] id_ctrl_mem_cmd; // @[RocketCore.scala:321:21] wire id_ctrl_rfs1; // @[RocketCore.scala:321:21] wire id_ctrl_rfs2; // @[RocketCore.scala:321:21] wire id_ctrl_rfs3; // @[RocketCore.scala:321:21] wire id_ctrl_wfd; // @[RocketCore.scala:321:21] wire id_ctrl_mul; // @[RocketCore.scala:321:21] wire id_ctrl_div; // @[RocketCore.scala:321:21] wire id_ctrl_wxd; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_csr; // @[RocketCore.scala:321:21] wire id_ctrl_fence_i; // @[RocketCore.scala:321:21] wire id_ctrl_amo; // @[RocketCore.scala:321:21] wire id_ctrl_dp; // @[RocketCore.scala:321:21] wire [31:0] id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22] wire [31:0] id_ctrl_decoder_decoded_invInputs = ~id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [41:0] id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [41:0] id_ctrl_decoder_decoded; // @[pla.scala:81:23] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T = {id_ctrl_decoder_decoded_andMatrixOutputs_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_99_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_102_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_9_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_29_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_139_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_117_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_4 = id_ctrl_decoder_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_96_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_35_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_182_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_128_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_67_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_78_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_190_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_7_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_98_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_32_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_71_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [4:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_181_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_16 = id_ctrl_decoder_decoded_andMatrixOutputs_181_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_145_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_143_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_20_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_22_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_97_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_39_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_131_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_191_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_63 = id_ctrl_decoder_decoded_andMatrixOutputs_191_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_164_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_64 = id_ctrl_decoder_decoded_andMatrixOutputs_164_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_55_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_90_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_30_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_26_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_175_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_77_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_21_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_5 = id_ctrl_decoder_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_121_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_61_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_105_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_24_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_165_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_160_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_95_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_56_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_16_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_185_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_6 = id_ctrl_decoder_decoded_andMatrixOutputs_185_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_140_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_53_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_193_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_92_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_17_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_129_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_177_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_123_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_14_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_27 = id_ctrl_decoder_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_132_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_49_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_155_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_7 = id_ctrl_decoder_decoded_andMatrixOutputs_155_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_184_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_148_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_115_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_162_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_44_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_126_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_150_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_161_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_133_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_179_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_5_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_88_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_94_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_66_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_125_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_91_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_112_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_170_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_146_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_168_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_2_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_15_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_176_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_172_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_76_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_87_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_144_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_36_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_41_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_8_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_104_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_73_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_189_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_28_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_0_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_60_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_48_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_167_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_163_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_137_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_74_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_59_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_152_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_47_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_103_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_83_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_28 = id_ctrl_decoder_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_31_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_13_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_111_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_65_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_124_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_50_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_6_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_134_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_153_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_109_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_187_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_45_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_79_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_159_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_34_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_86_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_10_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_93_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_180_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_43_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_135_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_3_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_188_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_4_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_25_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_58_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_147_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_27_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_52_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_138_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_178_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_173_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_120_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_19_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_64_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_142_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_11_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_46_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_141_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_114_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_70_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_72_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_174_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_81_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_130_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_157_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_68_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_42_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_54_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_63_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_69_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_183_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_51_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_136_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_127_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_151_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_1_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_100_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_106_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_186_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_18_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_108_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_89_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_62_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_149_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_171_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_37_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = id_ctrl_decoder_decoded_plaInput[23]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_169}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_122_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_169; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_170}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_82_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_170; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167}; // @[pla.scala:98:53] wire [31:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_171}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_119_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_171; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_172}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_169_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_172; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_173}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_57_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_173; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_174}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_80_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_174; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_175}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_166_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_175; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_176}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_154_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_176; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_177}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_192_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_177; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_178}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_38_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_178; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_179}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_158_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_179; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_180}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_110_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_180; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_181}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_23_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_181; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_182}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_101_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_182; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_183}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_118_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_183; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_184}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_116_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_184; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_185}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_156_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_185; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_186}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_113_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_186; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_187}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_107_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_187; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_188}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_84_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_188; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_189}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_33_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_189; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_190}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_85_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_190; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_191}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_40_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_191; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_192}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_12_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_192; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_lo_193}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_75_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_193; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_118_2, id_ctrl_decoder_decoded_andMatrixOutputs_85_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_114_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_86_2, id_ctrl_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_148_2, id_ctrl_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [11:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T = {id_ctrl_decoder_decoded_orMatrixOutputs_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_1 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _GEN = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_1 = _GEN; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6 = _GEN; // @[pla.scala:114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_3 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_47_2, id_ctrl_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_55_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_9 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_0 = {id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_154_2, id_ctrl_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_57_2, id_ctrl_decoder_decoded_andMatrixOutputs_80_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_1; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = _GEN_1; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = _GEN_1; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_24; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_24 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3 = _GEN_2; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = _GEN_3; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = _GEN_3; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4 = _GEN_3; // @[pla.scala:114:19] wire [1:0] _GEN_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = _GEN_4; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = _GEN_4; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3 = _GEN_4; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = _GEN_5; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3 = _GEN_5; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_98_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = _GEN_6; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = _GEN_6; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = _GEN_6; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = _GEN_7; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [45:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_11 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_176_2, id_ctrl_decoder_decoded_andMatrixOutputs_172_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_13 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_116_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_72_2, id_ctrl_decoder_decoded_andMatrixOutputs_81_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_157_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_45_2, id_ctrl_decoder_decoded_andMatrixOutputs_114_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_153_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3 = _GEN_11; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_187_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_77_2, id_ctrl_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_181_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = _GEN_12; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_15 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = _GEN_13; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = _GEN_13; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = _GEN_13; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_123_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_22_2, id_ctrl_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [12:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_18 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_70_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = _GEN_14; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = _GEN_14; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_124_2, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_20 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_65_2, id_ctrl_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_177_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_22 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_24 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_23; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_169_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_10; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_10 = _GEN_15; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = _GEN_15; // @[pla.scala:114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_26 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_25; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_74_2, id_ctrl_decoder_decoded_andMatrixOutputs_111_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_102_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [8:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_30 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_167_2, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_104_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_94_2, id_ctrl_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_56_2, id_ctrl_decoder_decoded_andMatrixOutputs_179_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = _GEN_16; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19] wire [14:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_32 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_64_2, id_ctrl_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_138_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = _GEN_17; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = _GEN_17; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_43_2, id_ctrl_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_73_2, id_ctrl_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_168_2, id_ctrl_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_112_2, id_ctrl_decoder_decoded_andMatrixOutputs_170_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_39_2, id_ctrl_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19] wire [17:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_34 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_5_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_150_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19] wire [10:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_36 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_54_2, id_ctrl_decoder_decoded_andMatrixOutputs_183_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_147_2, id_ctrl_decoder_decoded_andMatrixOutputs_178_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_48_2, id_ctrl_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_129_2, id_ctrl_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19] wire [9:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_38 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_37; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_171_2, id_ctrl_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_108_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = _GEN_18; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = _GEN_18; // @[pla.scala:114:19] wire [1:0] _GEN_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_106_2, id_ctrl_decoder_decoded_andMatrixOutputs_186_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = _GEN_19; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3 = _GEN_19; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_11_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19] wire [13:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_40 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_62_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_151_2, id_ctrl_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_135_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_34_2, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_189_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_164_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_78_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19] wire [35:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_42 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_66_2, id_ctrl_decoder_decoded_andMatrixOutputs_146_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_44 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}] wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_46 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] _GEN_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = _GEN_22; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN_22; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = _GEN_22; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = _GEN_23; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = _GEN_23; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_91_2, id_ctrl_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_24_2, id_ctrl_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19] wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_48 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_116_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = _GEN_24; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = _GEN_24; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = _GEN_25; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_31_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = _GEN_26; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = _GEN_26; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] _GEN_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = _GEN_27; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = _GEN_27; // @[pla.scala:114:19] wire [1:0] _GEN_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = _GEN_28; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = _GEN_28; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = _GEN_28; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = _GEN_29; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4 = _GEN_29; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] _GEN_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = _GEN_30; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = _GEN_30; // @[pla.scala:114:19] wire [1:0] _GEN_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = _GEN_31; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = _GEN_31; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = _GEN_31; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = _GEN_32; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = _GEN_32; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19] wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_50 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_49; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_182_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_189_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_52 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_120_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19] wire [1:0] _GEN_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_140_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = _GEN_33; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = _GEN_33; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = _GEN_33; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_91_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_29_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:114:19] wire [12:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19] wire [24:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_54 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_89_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] _GEN_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_159_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = _GEN_34; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = _GEN_34; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = _GEN_34; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_146_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_190_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19] wire [34:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_56 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_68_2, id_ctrl_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_24, id_ctrl_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_58 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19] wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_25, id_ctrl_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_60 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_59; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19] wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_26, id_ctrl_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_62 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_61; // @[pla.scala:114:{19,36}] wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_66 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_65; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_158_2, id_ctrl_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = _GEN_35; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = _GEN_35; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_136_2, id_ctrl_decoder_decoded_andMatrixOutputs_192_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_141_2, id_ctrl_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_50_2, id_ctrl_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_175_2, id_ctrl_decoder_decoded_andMatrixOutputs_193_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19] wire [20:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_27, id_ctrl_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_68 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_67; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_113_2, id_ctrl_decoder_decoded_andMatrixOutputs_107_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_173_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_111_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:114:19] wire [33:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_152_2, id_ctrl_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_90_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_131_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_143_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_117_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:114:19] wire [34:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19] wire [68:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_28, id_ctrl_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_70 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_69; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_3, _id_ctrl_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_9, _id_ctrl_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5 = {1'h0, _id_ctrl_decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5, _id_ctrl_decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_16, _id_ctrl_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_22, _id_ctrl_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_27, _id_ctrl_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_32, _id_ctrl_decoder_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:102:36] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:102:36] wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_36, _id_ctrl_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_42, _id_ctrl_decoder_decoded_orMatrixOutputs_T_40}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_38}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_46, _id_ctrl_decoder_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_52, _id_ctrl_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_56, _id_ctrl_decoder_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_62, _id_ctrl_decoder_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_66, _id_ctrl_decoder_decoded_orMatrixOutputs_T_64}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_70, _id_ctrl_decoder_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6, 1'h0}; // @[pla.scala:102:36] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:102:36] wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:102:36] wire [41:0] id_ctrl_decoder_decoded_orMatrixOutputs = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_29, id_ctrl_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:102:36] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T = id_ctrl_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_1 = id_ctrl_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_2 = id_ctrl_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_3 = id_ctrl_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_4 = id_ctrl_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_5 = id_ctrl_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_6 = id_ctrl_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_7 = id_ctrl_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_8 = id_ctrl_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_9 = id_ctrl_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_10 = id_ctrl_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_11 = id_ctrl_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_12 = id_ctrl_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_13 = id_ctrl_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_14 = id_ctrl_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_15 = id_ctrl_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_16 = id_ctrl_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_17 = id_ctrl_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_18 = id_ctrl_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_19 = id_ctrl_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_20 = id_ctrl_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_21 = id_ctrl_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_22 = id_ctrl_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_23 = id_ctrl_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_24 = id_ctrl_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_25 = id_ctrl_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_26 = id_ctrl_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_27 = id_ctrl_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_28 = id_ctrl_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_29 = id_ctrl_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_30 = id_ctrl_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_31 = id_ctrl_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_32 = id_ctrl_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_33 = id_ctrl_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_34 = id_ctrl_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_35 = id_ctrl_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_36 = id_ctrl_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_37 = id_ctrl_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_38 = id_ctrl_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_39 = id_ctrl_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_40 = id_ctrl_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_41 = id_ctrl_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_1, _id_ctrl_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_4, _id_ctrl_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_6, _id_ctrl_decoder_decoded_invMatrixOutputs_T_5}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_9, _id_ctrl_decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_11, _id_ctrl_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_14, _id_ctrl_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_17, _id_ctrl_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_20, _id_ctrl_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_22, _id_ctrl_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_25, _id_ctrl_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_27, _id_ctrl_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_30, _id_ctrl_decoder_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_32, _id_ctrl_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_35, _id_ctrl_decoder_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_38, _id_ctrl_decoder_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_41, _id_ctrl_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign id_ctrl_decoder_decoded_invMatrixOutputs = {id_ctrl_decoder_decoded_invMatrixOutputs_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign id_ctrl_decoder_decoded = id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign id_ctrl_decoder_0 = id_ctrl_decoder_decoded[41]; // @[pla.scala:81:23] assign id_ctrl_legal = id_ctrl_decoder_0; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_1 = id_ctrl_decoder_decoded[40]; // @[pla.scala:81:23] assign id_ctrl_fp = id_ctrl_decoder_1; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_2 = id_ctrl_decoder_decoded[39]; // @[pla.scala:81:23] assign id_ctrl_rocc = id_ctrl_decoder_2; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_3 = id_ctrl_decoder_decoded[38]; // @[pla.scala:81:23] assign id_ctrl_branch = id_ctrl_decoder_3; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_4 = id_ctrl_decoder_decoded[37]; // @[pla.scala:81:23] assign id_ctrl_jal = id_ctrl_decoder_4; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_5 = id_ctrl_decoder_decoded[36]; // @[pla.scala:81:23] assign id_ctrl_jalr = id_ctrl_decoder_5; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_6 = id_ctrl_decoder_decoded[35]; // @[pla.scala:81:23] assign id_ctrl_rxs2 = id_ctrl_decoder_6; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_7 = id_ctrl_decoder_decoded[34]; // @[pla.scala:81:23] assign id_ctrl_rxs1 = id_ctrl_decoder_7; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_8 = id_ctrl_decoder_decoded[33:31]; // @[pla.scala:81:23] assign id_ctrl_sel_alu2 = id_ctrl_decoder_8; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_9 = id_ctrl_decoder_decoded[30:29]; // @[pla.scala:81:23] assign id_ctrl_sel_alu1 = id_ctrl_decoder_9; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_10 = id_ctrl_decoder_decoded[28:26]; // @[pla.scala:81:23] assign id_ctrl_sel_imm = id_ctrl_decoder_10; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_11 = id_ctrl_decoder_decoded[25]; // @[pla.scala:81:23] assign id_ctrl_alu_dw = id_ctrl_decoder_11; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_12 = id_ctrl_decoder_decoded[24:20]; // @[pla.scala:81:23] assign id_ctrl_alu_fn = id_ctrl_decoder_12; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_13 = id_ctrl_decoder_decoded[19]; // @[pla.scala:81:23] assign id_ctrl_mem = id_ctrl_decoder_13; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_14 = id_ctrl_decoder_decoded[18:14]; // @[pla.scala:81:23] assign id_ctrl_mem_cmd = id_ctrl_decoder_14; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_15 = id_ctrl_decoder_decoded[13]; // @[pla.scala:81:23] assign id_ctrl_rfs1 = id_ctrl_decoder_15; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_16 = id_ctrl_decoder_decoded[12]; // @[pla.scala:81:23] assign id_ctrl_rfs2 = id_ctrl_decoder_16; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_17 = id_ctrl_decoder_decoded[11]; // @[pla.scala:81:23] assign id_ctrl_rfs3 = id_ctrl_decoder_17; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_18 = id_ctrl_decoder_decoded[10]; // @[pla.scala:81:23] assign id_ctrl_wfd = id_ctrl_decoder_18; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_19 = id_ctrl_decoder_decoded[9]; // @[pla.scala:81:23] assign id_ctrl_mul = id_ctrl_decoder_19; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_20 = id_ctrl_decoder_decoded[8]; // @[pla.scala:81:23] assign id_ctrl_div = id_ctrl_decoder_20; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_21 = id_ctrl_decoder_decoded[7]; // @[pla.scala:81:23] assign id_ctrl_wxd = id_ctrl_decoder_21; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_22 = id_ctrl_decoder_decoded[6:4]; // @[pla.scala:81:23] assign id_ctrl_csr = id_ctrl_decoder_22; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_23 = id_ctrl_decoder_decoded[3]; // @[pla.scala:81:23] assign id_ctrl_fence_i = id_ctrl_decoder_23; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_24 = id_ctrl_decoder_decoded[2]; // @[pla.scala:81:23] assign id_ctrl_fence = id_ctrl_decoder_24; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_25 = id_ctrl_decoder_decoded[1]; // @[pla.scala:81:23] assign id_ctrl_amo = id_ctrl_decoder_25; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_26 = id_ctrl_decoder_decoded[0]; // @[pla.scala:81:23] assign id_ctrl_dp = id_ctrl_decoder_26; // @[RocketCore.scala:321:21] wire [4:0] id_raddr3; // @[RocketCore.scala:326:72] wire [4:0] id_raddr2; // @[RocketCore.scala:326:72] wire [4:0] _id_rs_T_7 = id_raddr2; // @[RocketCore.scala:326:72, :1320:44] wire [4:0] id_raddr1; // @[RocketCore.scala:326:72] wire [4:0] _id_rs_T_2 = id_raddr1; // @[RocketCore.scala:326:72, :1320:44] wire [4:0] id_waddr; // @[RocketCore.scala:326:72] wire _id_load_use_T_1; // @[RocketCore.scala:1001:51] wire id_load_use; // @[RocketCore.scala:332:25] reg id_reg_fence; // @[RocketCore.scala:333:29] wire [63:0] id_rs_0; // @[RocketCore.scala:1325:26] wire _id_rs_T = ~(\|id_raddr1); // @[RocketCore.scala:326:72, :1326:41] wire [4:0] _id_rs_T_3 = ~_id_rs_T_2; // @[RocketCore.scala:1320:{39,44}] wire [63:0] id_rs_1; // @[RocketCore.scala:1325:26] wire _id_rs_T_5 = ~(\|id_raddr2); // @[RocketCore.scala:326:72, :1326:41] wire [4:0] _id_rs_T_8 = ~_id_rs_T_7; // @[RocketCore.scala:1320:{39,44}] wire _ctrl_killd_T_4; // @[RocketCore.scala:1046:104] wire ctrl_killd; // @[RocketCore.scala:338:24] wire _id_npc_sign_T_1 = _ibuf_io_inst_0_bits_inst_bits[31]; // @[RocketCore.scala:311:20, :1341:44] wire _id_npc_sign_T_2 = _id_npc_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire id_npc_sign = _id_npc_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire _id_npc_b11_T_9 = id_npc_sign; // @[RocketCore.scala:1341:19, :1346:18] wire id_npc_hi_hi_hi = id_npc_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _id_npc_b30_20_T_1 = _ibuf_io_inst_0_bits_inst_bits[30:20]; // @[RocketCore.scala:311:20, :1342:41] wire [10:0] _id_npc_b30_20_T_2 = _id_npc_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] id_npc_b30_20 = {11{id_npc_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] id_npc_hi_hi_lo = id_npc_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _id_npc_b19_12_T_3 = _ibuf_io_inst_0_bits_inst_bits[19:12]; // @[RocketCore.scala:311:20, :1343:65] wire [7:0] _id_npc_b19_12_T_4 = _id_npc_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] id_npc_b19_12 = _id_npc_b19_12_T_4; // @[RocketCore.scala:1343:{21,73}] wire [7:0] id_npc_hi_lo_hi = id_npc_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _id_npc_b11_T_4 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39] wire _id_npc_b0_T_3 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39, :1352:37] wire _id_npc_b11_T_5 = _id_npc_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _id_npc_b11_T_10 = _id_npc_b11_T_5; // @[RocketCore.scala:1345:{18,44}] wire _id_npc_b11_T_7 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39] wire _id_npc_b0_T_1 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39, :1351:37] wire _id_npc_b11_T_8 = _id_npc_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire id_npc_b11 = _id_npc_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire id_npc_hi_lo_lo = id_npc_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _id_npc_b10_5_T_3 = _ibuf_io_inst_0_bits_inst_bits[30:25]; // @[RocketCore.scala:311:20, :1347:62] wire [5:0] id_npc_b10_5 = _id_npc_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _id_npc_b4_1_T_4 = _ibuf_io_inst_0_bits_inst_bits[11:8]; // @[RocketCore.scala:311:20, :1349:57] wire [3:0] _id_npc_b4_1_T_6 = _ibuf_io_inst_0_bits_inst_bits[19:16]; // @[RocketCore.scala:311:20, :1350:39] wire [3:0] _id_npc_b4_1_T_7 = _ibuf_io_inst_0_bits_inst_bits[24:21]; // @[RocketCore.scala:311:20, :1350:52] wire [3:0] _id_npc_b4_1_T_8 = _id_npc_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _id_npc_b4_1_T_9 = _id_npc_b4_1_T_8; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] id_npc_b4_1 = _id_npc_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _id_npc_b0_T_5 = _ibuf_io_inst_0_bits_inst_bits[15]; // @[RocketCore.scala:311:20, :1353:37] wire [9:0] id_npc_lo_hi = {id_npc_b10_5, id_npc_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] id_npc_lo = {id_npc_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] id_npc_hi_lo = {id_npc_hi_lo_hi, id_npc_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] id_npc_hi_hi = {id_npc_hi_hi_hi, id_npc_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] id_npc_hi = {id_npc_hi_hi, id_npc_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _id_npc_T_1 = {id_npc_hi, id_npc_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _id_npc_T_2 = _id_npc_T_1; // @[RocketCore.scala:1355:{8,53}] wire [39:0] _id_npc_T; // @[RocketCore.scala:339:28] wire [40:0] _id_npc_T_3 = {_id_npc_T[39], _id_npc_T} + {{9{_id_npc_T_2[31]}}, _id_npc_T_2}; // @[RocketCore.scala:339:{28,35}, :1355:53] wire [39:0] _id_npc_T_4 = _id_npc_T_3[39:0]; // @[RocketCore.scala:339:35] wire [39:0] _id_npc_T_5 = _id_npc_T_4; // @[RocketCore.scala:339:35] wire [39:0] id_npc = _id_npc_T_5; // @[RocketCore.scala:339:{35,65}] wire _GEN_36 = id_ctrl_csr == 3'h6; // @[package.scala:16:47] wire _id_csr_en_T; // @[package.scala:16:47] assign _id_csr_en_T = _GEN_36; // @[package.scala:16:47] wire _id_csr_ren_T; // @[package.scala:16:47] assign _id_csr_ren_T = _GEN_36; // @[package.scala:16:47] wire _id_csr_en_T_1 = &id_ctrl_csr; // @[package.scala:16:47] wire _id_csr_en_T_2 = id_ctrl_csr == 3'h5; // @[package.scala:16:47] wire _id_csr_en_T_3 = _id_csr_en_T \| _id_csr_en_T_1; // @[package.scala:16:47, :81:59] wire id_csr_en = _id_csr_en_T_3 \| _id_csr_en_T_2; // @[package.scala:16:47, :81:59] wire id_system_insn = id_ctrl_csr == 3'h4; // @[RocketCore.scala:321:21, :343:36] wire _id_csr_ren_T_1 = &id_ctrl_csr; // @[package.scala:16:47] wire _id_csr_ren_T_2 = _id_csr_ren_T \| _id_csr_ren_T_1; // @[package.scala:16:47, :81:59] wire _id_csr_ren_T_3 = _ibuf_io_inst_0_bits_inst_rs1 == 5'h0; // @[RocketCore.scala:311:20, :344:81] wire id_csr_ren = _id_csr_ren_T_2 & _id_csr_ren_T_3; // @[package.scala:81:59] wire _id_csr_T = id_system_insn & id_ctrl_mem; // @[RocketCore.scala:321:21, :343:36, :345:35] wire [2:0] _id_csr_T_1 = id_csr_ren ? 3'h2 : id_ctrl_csr; // @[RocketCore.scala:321:21, :344:54, :345:61] wire [2:0] id_csr = _id_csr_T ? 3'h0 : _id_csr_T_1; // @[RocketCore.scala:345:{19,35,61}] wire _id_csr_flush_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54] wire _id_csr_flush_T_1 = id_csr_en & _id_csr_flush_T; // @[package.scala:81:59] wire _id_csr_flush_T_2 = _id_csr_flush_T_1 & _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19, :346:{51,66}] wire id_csr_flush = id_system_insn \| _id_csr_flush_T_2; // @[RocketCore.scala:343:36, :346:{37,66}] wire [31:0] _id_set_vconfig_T = _ibuf_io_inst_0_bits_inst_bits & 32'h8000707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_1 = _id_set_vconfig_T == 32'h7057; // @[RocketCore.scala:347:100] wire [31:0] _id_set_vconfig_T_2 = _ibuf_io_inst_0_bits_inst_bits & 32'hC000707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_3 = _id_set_vconfig_T_2 == 32'hC0007057; // @[RocketCore.scala:347:100] wire [31:0] _id_set_vconfig_T_4 = _ibuf_io_inst_0_bits_inst_bits & 32'hFE00707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_5 = _id_set_vconfig_T_4 == 32'h80007057; // @[RocketCore.scala:347:100] wire _id_set_vconfig_T_6 = _id_set_vconfig_T_1 \| _id_set_vconfig_T_3; // @[package.scala:81:59] wire _id_set_vconfig_T_7 = _id_set_vconfig_T_6 \| _id_set_vconfig_T_5; // @[package.scala:81:59] wire _id_illegal_insn_T = ~id_ctrl_legal; // @[RocketCore.scala:321:21, :381:25] wire _id_illegal_insn_T_1 = id_ctrl_mul \| id_ctrl_div; // @[RocketCore.scala:321:21, :382:18] wire _id_illegal_insn_T_2 = _csr_io_status_isa[12]; // @[RocketCore.scala:341:19, :382:55] wire _id_illegal_insn_T_3 = ~_id_illegal_insn_T_2; // @[RocketCore.scala:382:{37,55}] wire _id_illegal_insn_T_4 = _id_illegal_insn_T_1 & _id_illegal_insn_T_3; // @[RocketCore.scala:382:{18,34,37}] wire _id_illegal_insn_T_5 = _id_illegal_insn_T \| _id_illegal_insn_T_4; // @[RocketCore.scala:381:{25,40}, :382:34] wire _id_illegal_insn_T_6 = _csr_io_status_isa[0]; // @[RocketCore.scala:341:19, :383:38] wire _id_illegal_insn_T_7 = ~_id_illegal_insn_T_6; // @[RocketCore.scala:383:{20,38}] wire _id_illegal_insn_T_8 = id_ctrl_amo & _id_illegal_insn_T_7; // @[RocketCore.scala:321:21, :383:{17,20}] wire _id_illegal_insn_T_9 = _id_illegal_insn_T_5 \| _id_illegal_insn_T_8; // @[RocketCore.scala:381:40, :382:65, :383:17] wire _id_illegal_insn_T_12 = _csr_io_decode_0_fp_illegal \| _id_illegal_insn_T_11; // @[RocketCore.scala:341:19, :384:{48,70}] wire _id_illegal_insn_T_13 = id_ctrl_fp & _id_illegal_insn_T_12; // @[RocketCore.scala:321:21, :384:{16,48}] wire _id_illegal_insn_T_14 = _id_illegal_insn_T_9 \| _id_illegal_insn_T_13; // @[RocketCore.scala:382:65, :383:48, :384:16] wire _id_illegal_insn_T_17 = _id_illegal_insn_T_14; // @[RocketCore.scala:383:48, :384:88] wire _id_illegal_insn_T_18 = _csr_io_status_isa[3]; // @[RocketCore.scala:341:19, :386:37] wire _id_illegal_insn_T_19 = ~_id_illegal_insn_T_18; // @[RocketCore.scala:386:{19,37}] wire _id_illegal_insn_T_20 = id_ctrl_dp & _id_illegal_insn_T_19; // @[RocketCore.scala:321:21, :386:{16,19}] wire _id_illegal_insn_T_21 = _id_illegal_insn_T_17 \| _id_illegal_insn_T_20; // @[RocketCore.scala:384:88, :385:118, :386:16] wire _id_illegal_insn_T_22 = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51] wire _mem_npc_misaligned_T = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51, :623:46] wire _id_illegal_insn_T_23 = ~_id_illegal_insn_T_22; // @[RocketCore.scala:387:{33,51}] wire _id_illegal_insn_T_24 = _ibuf_io_inst_0_bits_rvc & _id_illegal_insn_T_23; // @[RocketCore.scala:311:20, :387:{30,33}] wire _id_illegal_insn_T_25 = _id_illegal_insn_T_21 \| _id_illegal_insn_T_24; // @[RocketCore.scala:385:118, :386:47, :387:30] wire _id_illegal_insn_T_27 = _id_illegal_insn_T_25; // @[RocketCore.scala:386:47, :387:61] wire _id_illegal_insn_T_29 = _id_illegal_insn_T_27; // @[RocketCore.scala:387:61, :388:39] wire _id_illegal_insn_T_31 = _id_illegal_insn_T_29; // @[RocketCore.scala:388:39, :389:39] wire _id_illegal_insn_T_33 = _id_illegal_insn_T_31 \| _id_illegal_insn_T_32; // @[RocketCore.scala:389:39, :390:37, :391:18] wire _id_illegal_insn_T_34 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :392:52] wire _id_illegal_insn_T_35 = _id_illegal_insn_T_34 & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :392:{52,64}] wire _id_illegal_insn_T_36 = _csr_io_decode_0_read_illegal \| _id_illegal_insn_T_35; // @[RocketCore.scala:341:19, :392:{49,64}] wire _id_illegal_insn_T_37 = id_csr_en & _id_illegal_insn_T_36; // @[package.scala:81:59] wire _id_illegal_insn_T_38 = _id_illegal_insn_T_33 \| _id_illegal_insn_T_37; // @[RocketCore.scala:390:37, :391:51, :392:15] wire _id_illegal_insn_T_39 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5] wire _id_illegal_insn_T_40 = id_system_insn & _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19, :343:36, :393:50] wire _id_illegal_insn_T_41 = _id_illegal_insn_T_39 & _id_illegal_insn_T_40; // @[RocketCore.scala:393:{5,31,50}] wire id_illegal_insn = _id_illegal_insn_T_38 \| _id_illegal_insn_T_41; // @[RocketCore.scala:391:51, :392:99, :393:31] wire _id_virtual_insn_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :395:22] wire _id_virtual_insn_T_1 = _id_virtual_insn_T & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :395:{22,34}] wire _id_virtual_insn_T_2 = ~_id_virtual_insn_T_1; // @[RocketCore.scala:395:{20,34}] wire _id_virtual_insn_T_3 = id_csr_en & _id_virtual_insn_T_2; // @[package.scala:81:59] wire _id_virtual_insn_T_4 = _id_virtual_insn_T_3 & _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19, :395:{17,69}] wire _id_virtual_insn_T_5 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5, :396:7] wire _id_virtual_insn_T_6 = _id_virtual_insn_T_5 & id_system_insn; // @[RocketCore.scala:343:36, :396:{7,33}] wire _id_virtual_insn_T_7 = _id_virtual_insn_T_6 & _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19, :396:{33,51}] wire _id_virtual_insn_T_8 = _id_virtual_insn_T_4 \| _id_virtual_insn_T_7; // @[RocketCore.scala:395:{69,113}, :396:51] wire id_virtual_insn = id_ctrl_legal & _id_virtual_insn_T_8; // @[RocketCore.scala:321:21, :394:39, :395:113] wire id_amo_aq = _ibuf_io_inst_0_bits_inst_bits[26]; // @[RocketCore.scala:311:20, :398:29] wire id_amo_rl = _ibuf_io_inst_0_bits_inst_bits[25]; // @[RocketCore.scala:311:20, :399:29] wire [3:0] id_fence_pred = _ibuf_io_inst_0_bits_inst_bits[27:24]; // @[RocketCore.scala:311:20, :400:33] wire [3:0] id_fence_succ = _ibuf_io_inst_0_bits_inst_bits[23:20]; // @[RocketCore.scala:311:20, :401:33] wire _id_fence_next_T = id_ctrl_amo & id_amo_aq; // @[RocketCore.scala:321:21, :398:29, :402:52] wire id_fence_next = id_ctrl_fence \| _id_fence_next_T; // @[RocketCore.scala:321:21, :402:{37,52}] wire _id_mem_busy_T = ~io_dmem_ordered_0; // @[RocketCore.scala:153:7, :403:21] wire id_mem_busy = _id_mem_busy_T \| io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :403:{21,38}] wire _id_rocc_busy_T = ex_reg_valid & ex_ctrl_rocc; // @[RocketCore.scala:243:20, :248:35, :406:35] wire _id_rocc_busy_T_1 = _id_rocc_busy_T; // @[RocketCore.scala:406:{19,35}] wire _id_rocc_busy_T_2 = mem_reg_valid & mem_ctrl_rocc; // @[RocketCore.scala:244:21, :265:36, :407:20] wire _id_rocc_busy_T_3 = _id_rocc_busy_T_1 \| _id_rocc_busy_T_2; // @[RocketCore.scala:406:{19,51}, :407:20] wire _GEN_37 = wb_reg_valid & wb_ctrl_rocc; // @[RocketCore.scala:245:20, :288:35, :407:53] wire _id_rocc_busy_T_4; // @[RocketCore.scala:407:53] assign _id_rocc_busy_T_4 = _GEN_37; // @[RocketCore.scala:407:53] wire _replay_wb_rocc_T; // @[RocketCore.scala:758:37] assign _replay_wb_rocc_T = _GEN_37; // @[RocketCore.scala:407:53, :758:37] wire _io_rocc_cmd_valid_T; // @[RocketCore.scala:1156:37] assign _io_rocc_cmd_valid_T = _GEN_37; // @[RocketCore.scala:407:53, :1156:37] wire _id_rocc_busy_T_5 = _id_rocc_busy_T_3 \| _id_rocc_busy_T_4; // @[RocketCore.scala:406:51, :407:{37,53}] wire _id_csr_rocc_write_T_1 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :408:103] wire _id_do_fence_T_4 = id_ctrl_amo & id_amo_rl; // @[RocketCore.scala:321:21, :399:29, :412:33] wire _id_do_fence_T_5 = _id_do_fence_T_4 \| id_ctrl_fence_i; // @[RocketCore.scala:321:21, :412:{33,46}] wire _id_do_fence_T_6 = id_ctrl_mem \| id_ctrl_rocc; // @[RocketCore.scala:321:21, :412:97] wire _id_do_fence_T_7 = id_reg_fence & _id_do_fence_T_6; // @[RocketCore.scala:333:29, :412:{81,97}] wire _id_do_fence_T_8 = _id_do_fence_T_5 \| _id_do_fence_T_7; // @[RocketCore.scala:412:{46,65,81}] wire _id_do_fence_T_9 = id_mem_busy & _id_do_fence_T_8; // @[RocketCore.scala:403:38, :412:{17,65}] wire _id_do_fence_T_10 = _id_do_fence_T_9; // @[RocketCore.scala:411:34, :412:17] wire id_do_fence = _id_do_fence_T_10; // @[RocketCore.scala:410:32, :411:34] wire [38:0] _mem_npc_T_1 = mem_reg_wdata[38:0]; // @[RocketCore.scala:282:26, :418:13, :1295:16] wire id_xcpt = _csr_io_interrupt \| _bpu_io_debug_if \| _bpu_io_xcpt_if \| _ibuf_io_inst_0_bits_xcpt0_pf_inst \| _ibuf_io_inst_0_bits_xcpt0_gf_inst \| _ibuf_io_inst_0_bits_xcpt0_ae_inst \| _ibuf_io_inst_0_bits_xcpt1_pf_inst \| _ibuf_io_inst_0_bits_xcpt1_gf_inst \| _ibuf_io_inst_0_bits_xcpt1_ae_inst \| id_virtual_insn \| id_illegal_insn; // @[RocketCore.scala:311:20, :341:19, :392:99, :394:39, :414:19, :1278:{14,35}] wire [63:0] id_cause = _csr_io_interrupt ? _csr_io_interrupt_cause : {59'h0, _bpu_io_debug_if ? 5'hE : _bpu_io_xcpt_if ? 5'h3 : _ibuf_io_inst_0_bits_xcpt0_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt0_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt0_ae_inst ? 5'h1 : _ibuf_io_inst_0_bits_xcpt1_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt1_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt1_ae_inst ? 5'h1 : id_virtual_insn ? 5'h16 : 5'h2}; // @[Mux.scala:50:70] wire [4:0] _ex_waddr_T = ex_reg_inst[11:7]; // @[RocketCore.scala:259:24, :453:29] wire [4:0] ex_waddr = _ex_waddr_T; // @[RocketCore.scala:453:{29,36}] wire [4:0] _mem_waddr_T = mem_reg_inst[11:7]; // @[RocketCore.scala:278:25, :454:31] wire [4:0] mem_waddr = _mem_waddr_T; // @[RocketCore.scala:454:{31,38}] wire [4:0] _wb_waddr_T = wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :455:29] wire [4:0] wb_waddr = _wb_waddr_T; // @[RocketCore.scala:455:{29,36}] wire [4:0] coreMonitorBundle_wrdst = wb_waddr; // @[RocketCore.scala:455:36, :1186:31] wire bypass_sources_1_1 = ex_reg_valid & ex_ctrl_wxd; // @[RocketCore.scala:243:20, :248:35, :458:19] wire _GEN_38 = mem_reg_valid & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :265:36, :459:20] wire _bypass_sources_T; // @[RocketCore.scala:459:20] assign _bypass_sources_T = _GEN_38; // @[RocketCore.scala:459:20] wire bypass_sources_3_1; // @[RocketCore.scala:460:20] assign bypass_sources_3_1 = _GEN_38; // @[RocketCore.scala:459:20, :460:20] wire _dcache_kill_mem_T; // @[RocketCore.scala:695:39] assign _dcache_kill_mem_T = _GEN_38; // @[RocketCore.scala:459:20, :695:39] wire _bypass_sources_T_1 = ~mem_ctrl_mem; // @[RocketCore.scala:244:21, :459:39] wire bypass_sources_2_1 = _bypass_sources_T & _bypass_sources_T_1; // @[RocketCore.scala:459:{20,36,39}] wire _id_bypass_src_T = ~(\|id_raddr1); // @[RocketCore.scala:326:72, :461:82, :1326:41] wire id_bypass_src_0_0 = _id_bypass_src_T; // @[RocketCore.scala:461:{74,82}] wire _GEN_39 = ex_waddr == id_raddr1; // @[RocketCore.scala:326:72, :453:36, :461:82] wire _id_bypass_src_T_1; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_1 = _GEN_39; // @[RocketCore.scala:461:82] wire _data_hazard_ex_T; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T = _GEN_39; // @[RocketCore.scala:461:82, :989:70] wire _fp_data_hazard_ex_T_1; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_1 = _GEN_39; // @[RocketCore.scala:461:82, :990:90] wire id_bypass_src_0_1 = bypass_sources_1_1 & _id_bypass_src_T_1; // @[RocketCore.scala:458:19, :461:{74,82}] wire _GEN_40 = mem_waddr == id_raddr1; // @[RocketCore.scala:326:72, :454:38, :461:82] wire _id_bypass_src_T_2; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_2 = _GEN_40; // @[RocketCore.scala:461:82] wire _id_bypass_src_T_3; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_3 = _GEN_40; // @[RocketCore.scala:461:82] wire _data_hazard_mem_T; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T = _GEN_40; // @[RocketCore.scala:461:82, :998:72] wire _fp_data_hazard_mem_T_1; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_1 = _GEN_40; // @[RocketCore.scala:461:82, :999:92] wire id_bypass_src_0_2 = bypass_sources_2_1 & _id_bypass_src_T_2; // @[RocketCore.scala:459:36, :461:{74,82}] wire id_bypass_src_0_3 = bypass_sources_3_1 & _id_bypass_src_T_3; // @[RocketCore.scala:460:20, :461:{74,82}] wire _id_bypass_src_T_4 = ~(\|id_raddr2); // @[RocketCore.scala:326:72, :461:82, :1326:41] wire id_bypass_src_1_0 = _id_bypass_src_T_4; // @[RocketCore.scala:461:{74,82}] wire _GEN_41 = ex_waddr == id_raddr2; // @[RocketCore.scala:326:72, :453:36, :461:82] wire _id_bypass_src_T_5; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_5 = _GEN_41; // @[RocketCore.scala:461:82] wire _data_hazard_ex_T_2; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T_2 = _GEN_41; // @[RocketCore.scala:461:82, :989:70] wire _fp_data_hazard_ex_T_3; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_3 = _GEN_41; // @[RocketCore.scala:461:82, :990:90] wire id_bypass_src_1_1 = bypass_sources_1_1 & _id_bypass_src_T_5; // @[RocketCore.scala:458:19, :461:{74,82}] wire _GEN_42 = mem_waddr == id_raddr2; // @[RocketCore.scala:326:72, :454:38, :461:82] wire _id_bypass_src_T_6; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_6 = _GEN_42; // @[RocketCore.scala:461:82] wire _id_bypass_src_T_7; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_7 = _GEN_42; // @[RocketCore.scala:461:82] wire _data_hazard_mem_T_2; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T_2 = _GEN_42; // @[RocketCore.scala:461:82, :998:72] wire _fp_data_hazard_mem_T_3; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_3 = _GEN_42; // @[RocketCore.scala:461:82, :999:92] wire id_bypass_src_1_2 = bypass_sources_2_1 & _id_bypass_src_T_6; // @[RocketCore.scala:459:36, :461:{74,82}] wire id_bypass_src_1_3 = bypass_sources_3_1 & _id_bypass_src_T_7; // @[RocketCore.scala:460:20, :461:{74,82}] reg ex_reg_rs_bypass_0; // @[RocketCore.scala:465:29] reg ex_reg_rs_bypass_1; // @[RocketCore.scala:465:29] reg [1:0] ex_reg_rs_lsb_0; // @[RocketCore.scala:466:26] reg [1:0] ex_reg_rs_lsb_1; // @[RocketCore.scala:466:26] reg [61:0] ex_reg_rs_msb_0; // @[RocketCore.scala:467:26] reg [61:0] ex_reg_rs_msb_1; // @[RocketCore.scala:467:26] wire _ex_rs_T = ex_reg_rs_lsb_0 == 2'h1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_1 = _ex_rs_T ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}] wire _ex_rs_T_2 = ex_reg_rs_lsb_0 == 2'h2; // @[package.scala:39:86] wire [63:0] _ex_rs_T_3 = _ex_rs_T_2 ? wb_reg_wdata : _ex_rs_T_1; // @[package.scala:39:{76,86}] wire _ex_rs_T_4 = &ex_reg_rs_lsb_0; // @[package.scala:39:86] wire [63:0] _ex_rs_T_5 = _ex_rs_T_4 ? dcache_bypass_data : _ex_rs_T_3; // @[package.scala:39:{76,86}] wire [63:0] _ex_rs_T_6 = {ex_reg_rs_msb_0, ex_reg_rs_lsb_0}; // @[RocketCore.scala:466:26, :467:26, :469:69] assign ex_rs_0 = ex_reg_rs_bypass_0 ? _ex_rs_T_5 : _ex_rs_T_6; // @[package.scala:39:76] assign io_fpu_fromint_data_0 = ex_rs_0; // @[RocketCore.scala:153:7, :469:14] wire [63:0] _ex_op1_T = ex_rs_0; // @[RocketCore.scala:469:14, :473:24] wire _ex_rs_T_7 = ex_reg_rs_lsb_1 == 2'h1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_8 = _ex_rs_T_7 ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}] wire _ex_rs_T_9 = ex_reg_rs_lsb_1 == 2'h2; // @[package.scala:39:86] wire [63:0] _ex_rs_T_10 = _ex_rs_T_9 ? wb_reg_wdata : _ex_rs_T_8; // @[package.scala:39:{76,86}] wire _ex_rs_T_11 = &ex_reg_rs_lsb_1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_12 = _ex_rs_T_11 ? dcache_bypass_data : _ex_rs_T_10; // @[package.scala:39:{76,86}] wire [63:0] _ex_rs_T_13 = {ex_reg_rs_msb_1, ex_reg_rs_lsb_1}; // @[RocketCore.scala:466:26, :467:26, :469:69] wire [63:0] ex_rs_1 = ex_reg_rs_bypass_1 ? _ex_rs_T_12 : _ex_rs_T_13; // @[package.scala:39:76] wire [63:0] _ex_op2_T = ex_rs_1; // @[RocketCore.scala:469:14, :479:24] wire [63:0] mem_reg_rs2_dat_padded = ex_rs_1; // @[RocketCore.scala:469:14] wire _GEN_43 = ex_ctrl_sel_imm == 3'h5; // @[RocketCore.scala:243:20, :1341:24] wire _ex_imm_sign_T; // @[RocketCore.scala:1341:24] assign _ex_imm_sign_T = _GEN_43; // @[RocketCore.scala:1341:24] wire _ex_imm_b11_T_1; // @[RocketCore.scala:1344:40] assign _ex_imm_b11_T_1 = _GEN_43; // @[RocketCore.scala:1341:24, :1344:40] wire _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:42] assign _ex_imm_b10_5_T_1 = _GEN_43; // @[RocketCore.scala:1341:24, :1347:42] wire _ex_imm_b4_1_T_5; // @[RocketCore.scala:1350:24] assign _ex_imm_b4_1_T_5 = _GEN_43; // @[RocketCore.scala:1341:24, :1350:24] wire _ex_imm_b0_T_4; // @[RocketCore.scala:1353:22] assign _ex_imm_b0_T_4 = _GEN_43; // @[RocketCore.scala:1341:24, :1353:22] wire _ex_imm_sign_T_1 = ex_reg_inst[31]; // @[RocketCore.scala:259:24, :1341:44] wire _ex_imm_sign_T_2 = _ex_imm_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire ex_imm_sign = ~_ex_imm_sign_T & _ex_imm_sign_T_2; // @[RocketCore.scala:1341:{19,24,49}] wire ex_imm_hi_hi_hi = ex_imm_sign; // @[RocketCore.scala:1341:19, :1355:8] wire _GEN_44 = ex_ctrl_sel_imm == 3'h2; // @[RocketCore.scala:243:20, :1342:26] wire _ex_imm_b30_20_T; // @[RocketCore.scala:1342:26] assign _ex_imm_b30_20_T = _GEN_44; // @[RocketCore.scala:1342:26] wire _ex_imm_b11_T; // @[RocketCore.scala:1344:23] assign _ex_imm_b11_T = _GEN_44; // @[RocketCore.scala:1342:26, :1344:23] wire _ex_imm_b10_5_T; // @[RocketCore.scala:1347:25] assign _ex_imm_b10_5_T = _GEN_44; // @[RocketCore.scala:1342:26, :1347:25] wire _ex_imm_b4_1_T; // @[RocketCore.scala:1348:24] assign _ex_imm_b4_1_T = _GEN_44; // @[RocketCore.scala:1342:26, :1348:24] wire [10:0] _ex_imm_b30_20_T_1 = ex_reg_inst[30:20]; // @[RocketCore.scala:259:24, :1342:41] wire [10:0] _ex_imm_b30_20_T_2 = _ex_imm_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] ex_imm_b30_20 = _ex_imm_b30_20_T ? _ex_imm_b30_20_T_2 : {11{ex_imm_sign}}; // @[RocketCore.scala:1341:19, :1342:{21,26,49}] wire [10:0] ex_imm_hi_hi_lo = ex_imm_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire _ex_imm_b19_12_T = ex_ctrl_sel_imm != 3'h2; // @[RocketCore.scala:243:20, :1343:26] wire _ex_imm_b19_12_T_1 = ex_ctrl_sel_imm != 3'h3; // @[RocketCore.scala:243:20, :1343:43] wire _ex_imm_b19_12_T_2 = _ex_imm_b19_12_T & _ex_imm_b19_12_T_1; // @[RocketCore.scala:1343:{26,36,43}] wire [7:0] _ex_imm_b19_12_T_3 = ex_reg_inst[19:12]; // @[RocketCore.scala:259:24, :1343:65] wire [7:0] _ex_imm_b19_12_T_4 = _ex_imm_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] ex_imm_b19_12 = _ex_imm_b19_12_T_2 ? {8{ex_imm_sign}} : _ex_imm_b19_12_T_4; // @[RocketCore.scala:1341:19, :1343:{21,36,73}] wire [7:0] ex_imm_hi_lo_hi = ex_imm_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _ex_imm_b11_T_2 = _ex_imm_b11_T \| _ex_imm_b11_T_1; // @[RocketCore.scala:1344:{23,33,40}] wire _ex_imm_b11_T_3 = ex_ctrl_sel_imm == 3'h3; // @[RocketCore.scala:243:20, :1345:23] wire _ex_imm_b11_T_4 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39] wire _ex_imm_b0_T_3 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39, :1352:37] wire _io_dmem_req_bits_signed_T = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1136:58, :1345:39] wire _ex_imm_b11_T_5 = _ex_imm_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _GEN_45 = ex_ctrl_sel_imm == 3'h1; // @[RocketCore.scala:243:20, :1346:23] wire _ex_imm_b11_T_6; // @[RocketCore.scala:1346:23] assign _ex_imm_b11_T_6 = _GEN_45; // @[RocketCore.scala:1346:23] wire _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:41] assign _ex_imm_b4_1_T_2 = _GEN_45; // @[RocketCore.scala:1346:23, :1349:41] wire _ex_imm_b11_T_7 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39] wire _ex_imm_b0_T_1 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39, :1351:37] wire _ex_imm_b11_T_8 = _ex_imm_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _ex_imm_b11_T_9 = _ex_imm_b11_T_6 ? _ex_imm_b11_T_8 : ex_imm_sign; // @[RocketCore.scala:1341:19, :1346:{18,23,43}] wire _ex_imm_b11_T_10 = _ex_imm_b11_T_3 ? _ex_imm_b11_T_5 : _ex_imm_b11_T_9; // @[RocketCore.scala:1345:{18,23,44}, :1346:18] wire ex_imm_b11 = ~_ex_imm_b11_T_2 & _ex_imm_b11_T_10; // @[RocketCore.scala:1344:{18,33}, :1345:18] wire ex_imm_hi_lo_lo = ex_imm_b11; // @[RocketCore.scala:1344:18, :1355:8] wire _ex_imm_b10_5_T_2 = _ex_imm_b10_5_T \| _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:{25,35,42}] wire [5:0] _ex_imm_b10_5_T_3 = ex_reg_inst[30:25]; // @[RocketCore.scala:259:24, :1347:62] wire [5:0] ex_imm_b10_5 = _ex_imm_b10_5_T_2 ? 6'h0 : _ex_imm_b10_5_T_3; // @[RocketCore.scala:1347:{20,35,62}] wire _GEN_46 = ex_ctrl_sel_imm == 3'h0; // @[RocketCore.scala:243:20, :1349:24] wire _ex_imm_b4_1_T_1; // @[RocketCore.scala:1349:24] assign _ex_imm_b4_1_T_1 = _GEN_46; // @[RocketCore.scala:1349:24] wire _ex_imm_b0_T; // @[RocketCore.scala:1351:22] assign _ex_imm_b0_T = _GEN_46; // @[RocketCore.scala:1349:24, :1351:22] wire _ex_imm_b4_1_T_3 = _ex_imm_b4_1_T_1 \| _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:{24,34,41}] wire [3:0] _ex_imm_b4_1_T_4 = ex_reg_inst[11:8]; // @[RocketCore.scala:259:24, :1349:57] wire [3:0] _ex_imm_b4_1_T_6 = ex_reg_inst[19:16]; // @[RocketCore.scala:259:24, :1350:39] wire [3:0] _ex_imm_b4_1_T_7 = ex_reg_inst[24:21]; // @[RocketCore.scala:259:24, :1350:52] wire [3:0] _ex_imm_b4_1_T_8 = _ex_imm_b4_1_T_5 ? _ex_imm_b4_1_T_6 : _ex_imm_b4_1_T_7; // @[RocketCore.scala:1350:{19,24,39,52}] wire [3:0] _ex_imm_b4_1_T_9 = _ex_imm_b4_1_T_3 ? _ex_imm_b4_1_T_4 : _ex_imm_b4_1_T_8; // @[RocketCore.scala:1349:{19,34,57}, :1350:19] wire [3:0] ex_imm_b4_1 = _ex_imm_b4_1_T ? 4'h0 : _ex_imm_b4_1_T_9; // @[RocketCore.scala:1348:{19,24}, :1349:19] wire _ex_imm_b0_T_2 = ex_ctrl_sel_imm == 3'h4; // @[RocketCore.scala:243:20, :1352:22] wire _ex_imm_b0_T_5 = ex_reg_inst[15]; // @[RocketCore.scala:259:24, :1353:37] wire _ex_imm_b0_T_6 = _ex_imm_b0_T_4 & _ex_imm_b0_T_5; // @[RocketCore.scala:1353:{17,22,37}] wire _ex_imm_b0_T_7 = _ex_imm_b0_T_2 ? _ex_imm_b0_T_3 : _ex_imm_b0_T_6; // @[RocketCore.scala:1352:{17,22,37}, :1353:17] wire ex_imm_b0 = _ex_imm_b0_T ? _ex_imm_b0_T_1 : _ex_imm_b0_T_7; // @[RocketCore.scala:1351:{17,22,37}, :1352:17] wire [9:0] ex_imm_lo_hi = {ex_imm_b10_5, ex_imm_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] ex_imm_lo = {ex_imm_lo_hi, ex_imm_b0}; // @[RocketCore.scala:1351:17, :1355:8] wire [8:0] ex_imm_hi_lo = {ex_imm_hi_lo_hi, ex_imm_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] ex_imm_hi_hi = {ex_imm_hi_hi_hi, ex_imm_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] ex_imm_hi = {ex_imm_hi_hi, ex_imm_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _ex_imm_T = {ex_imm_hi, ex_imm_lo}; // @[RocketCore.scala:1355:8] wire [31:0] ex_imm = _ex_imm_T; // @[RocketCore.scala:1355:{8,53}] wire _ex_rs1shl_T = ex_reg_inst[3]; // @[RocketCore.scala:259:24, :471:34] wire [31:0] _ex_rs1shl_T_1 = ex_rs_0[31:0]; // @[RocketCore.scala:469:14, :471:47] wire [63:0] _ex_rs1shl_T_2 = _ex_rs1shl_T ? {32'h0, _ex_rs1shl_T_1} : ex_rs_0; // @[RocketCore.scala:469:14, :471:{22,34,47}] wire [1:0] _ex_rs1shl_T_3 = ex_reg_inst[14:13]; // @[RocketCore.scala:259:24, :471:79] wire [66:0] ex_rs1shl = {3'h0, _ex_rs1shl_T_2} << _ex_rs1shl_T_3; // @[RocketCore.scala:471:{22,65,79}] wire [66:0] _ex_op1_T_2 = ex_rs1shl; // @[RocketCore.scala:471:65, :475:54] wire _ex_op1_T_3 = ex_ctrl_sel_alu1 == 2'h1; // @[RocketCore.scala:243:20, :472:48] wire [63:0] _ex_op1_T_4 = _ex_op1_T_3 ? _ex_op1_T : 64'h0; // @[RocketCore.scala:472:48, :473:24] wire _ex_op1_T_5 = ex_ctrl_sel_alu1 == 2'h2; // @[RocketCore.scala:243:20, :472:48] wire [63:0] _ex_op1_T_6 = _ex_op1_T_5 ? {{24{_ex_op1_T_1[39]}}, _ex_op1_T_1} : _ex_op1_T_4; // @[RocketCore.scala:472:48, :474:24] wire _ex_op1_T_7 = &ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20, :472:48] wire [66:0] ex_op1 = _ex_op1_T_7 ? _ex_op1_T_2 : {{3{_ex_op1_T_6[63]}}, _ex_op1_T_6}; // @[RocketCore.scala:472:48, :475:54] wire [66:0] _alu_io_in1_T = ex_op1; // @[RocketCore.scala:472:48, :508:24] wire _ex_op2_oh_T = ex_ctrl_sel_alu2[0]; // @[RocketCore.scala:243:20, :477:48] wire [11:0] _ex_op2_oh_T_1 = ex_reg_inst[31:20]; // @[RocketCore.scala:259:24, :477:66] wire [63:0] _ex_op2_oh_T_2 = _ex_op2_oh_T ? {52'h0, _ex_op2_oh_T_1} : ex_rs_1; // @[RocketCore.scala:469:14, :477:{31,48,66}] wire [5:0] _ex_op2_oh_T_3 = _ex_op2_oh_T_2[5:0]; // @[RocketCore.scala:477:{31,90}] wire [63:0] _ex_op2_oh_T_4 = 64'h1 << _ex_op2_oh_T_3; // @[OneHot.scala:58:35] wire [63:0] ex_op2_oh = _ex_op2_oh_T_4; // @[OneHot.scala:58:35] wire [3:0] _ex_op2_T_1 = ex_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:249:35, :481:19] wire _ex_op2_T_2 = ex_ctrl_sel_alu2 == 3'h2; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_3 = _ex_op2_T_2 ? _ex_op2_T : 64'h0; // @[RocketCore.scala:478:48, :479:24] wire _ex_op2_T_4 = ex_ctrl_sel_alu2 == 3'h3; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_5 = _ex_op2_T_4 ? {{32{ex_imm[31]}}, ex_imm} : _ex_op2_T_3; // @[RocketCore.scala:478:48, :1355:53] wire _ex_op2_T_6 = ex_ctrl_sel_alu2 == 3'h1; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_7 = _ex_op2_T_6 ? {{60{_ex_op2_T_1[3]}}, _ex_op2_T_1} : _ex_op2_T_5; // @[RocketCore.scala:478:48, :481:19] wire _ex_op2_T_8 = ex_ctrl_sel_alu2 == 3'h4; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_9 = _ex_op2_T_8 ? ex_op2_oh : _ex_op2_T_7; // @[RocketCore.scala:477:112, :478:48] wire _ex_op2_T_10 = ex_ctrl_sel_alu2 == 3'h5; // @[RocketCore.scala:243:20, :478:48] wire [63:0] ex_op2 = _ex_op2_T_10 ? ex_op2_oh : _ex_op2_T_9; // @[RocketCore.scala:477:112, :478:48] wire [63:0] _alu_io_in2_T = ex_op2; // @[RocketCore.scala:478:48, :507:24] wire _div_io_req_valid_T = ex_reg_valid & ex_ctrl_div; // @[RocketCore.scala:243:20, :248:35, :512:36] wire _ex_reg_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19] wire _ex_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20] wire _ex_reg_replay_T_1 = _ex_reg_replay_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :526:{20,29}] wire _ex_reg_replay_T_2 = _ex_reg_replay_T_1 & _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :526:{29,54}] wire _ex_reg_xcpt_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :527:18] wire _ex_reg_xcpt_T_1 = _ex_reg_xcpt_T & id_xcpt; // @[RocketCore.scala:527:{18,30}, :1278:14] wire _ex_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :528:28] wire _ex_reg_xcpt_interrupt_T_1 = _ex_reg_xcpt_interrupt_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :528:{28,37}] wire _ex_reg_xcpt_interrupt_T_2 = _ex_reg_xcpt_interrupt_T_1 & _csr_io_interrupt; // @[RocketCore.scala:341:19, :528:{37,62}] wire [1:0] hi = {_ibuf_io_inst_0_bits_xcpt1_pf_inst, _ibuf_io_inst_0_bits_xcpt1_gf_inst}; // @[RocketCore.scala:311:20, :541:22] wire [1:0] hi_1 = {_ibuf_io_inst_0_bits_xcpt0_pf_inst, _ibuf_io_inst_0_bits_xcpt0_gf_inst}; // @[RocketCore.scala:311:20, :546:40] wire _ex_reg_flush_pipe_T = id_ctrl_fence_i \| id_csr_flush; // @[RocketCore.scala:321:21, :346:37, :551:42] wire _ex_reg_hls_T_1 = id_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47] wire _ex_reg_hls_T_2 = id_ctrl_mem_cmd == 5'h1; // @[package.scala:16:47] wire _ex_reg_hls_T_3 = id_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47] wire _ex_reg_hls_T_4 = _ex_reg_hls_T_1 \| _ex_reg_hls_T_2; // @[package.scala:16:47, :81:59] wire _ex_reg_hls_T_5 = _ex_reg_hls_T_4 \| _ex_reg_hls_T_3; // @[package.scala:16:47, :81:59] wire [1:0] _ex_reg_mem_size_T_1 = _ibuf_io_inst_0_bits_inst_bits[27:26]; // @[RocketCore.scala:311:20, :554:75] wire [1:0] _ex_reg_mem_size_T_2 = _ibuf_io_inst_0_bits_inst_bits[13:12]; // @[RocketCore.scala:311:20, :554:95] wire [1:0] _ex_reg_mem_size_T_3 = _ex_reg_mem_size_T_2; // @[RocketCore.scala:554:{27,95}] wire _ex_reg_mem_size_T_4 = \|id_raddr2; // @[RocketCore.scala:326:72, :556:40, :1326:41] wire _ex_reg_mem_size_T_5 = \|id_raddr1; // @[RocketCore.scala:326:72, :556:59, :1326:41] wire [1:0] _ex_reg_mem_size_T_6 = {_ex_reg_mem_size_T_4, _ex_reg_mem_size_T_5}; // @[RocketCore.scala:556:{29,40,59}] wire _do_bypass_T = id_bypass_src_0_0 \| id_bypass_src_0_1; // @[RocketCore.scala:461:74, :568:48] wire _do_bypass_T_1 = _do_bypass_T \| id_bypass_src_0_2; // @[RocketCore.scala:461:74, :568:48] wire do_bypass = _do_bypass_T_1 \| id_bypass_src_0_3; // @[RocketCore.scala:461:74, :568:48] wire [1:0] _bypass_src_T = {1'h1, ~id_bypass_src_0_2}; // @[Mux.scala:50:70] wire [1:0] _bypass_src_T_1 = id_bypass_src_0_1 ? 2'h1 : _bypass_src_T; // @[Mux.scala:50:70] wire [1:0] bypass_src = id_bypass_src_0_0 ? 2'h0 : _bypass_src_T_1; // @[Mux.scala:50:70] wire [1:0] _ex_reg_rs_lsb_0_T = id_rs_0[1:0]; // @[RocketCore.scala:573:37, :1325:26] wire [61:0] _ex_reg_rs_msb_0_T = id_rs_0[63:2]; // @[RocketCore.scala:574:38, :1325:26] wire _do_bypass_T_2 = id_bypass_src_1_0 \| id_bypass_src_1_1; // @[RocketCore.scala:461:74, :568:48] wire _do_bypass_T_3 = _do_bypass_T_2 \| id_bypass_src_1_2; // @[RocketCore.scala:461:74, :568:48] wire do_bypass_1 = _do_bypass_T_3 \| id_bypass_src_1_3; // @[RocketCore.scala:461:74, :568:48] wire [1:0] _bypass_src_T_2 = {1'h1, ~id_bypass_src_1_2}; // @[Mux.scala:50:70] wire [1:0] _bypass_src_T_3 = id_bypass_src_1_1 ? 2'h1 : _bypass_src_T_2; // @[Mux.scala:50:70] wire [1:0] bypass_src_1 = id_bypass_src_1_0 ? 2'h0 : _bypass_src_T_3; // @[Mux.scala:50:70] wire [1:0] _ex_reg_rs_lsb_1_T = id_rs_1[1:0]; // @[RocketCore.scala:573:37, :1325:26] wire [61:0] _ex_reg_rs_msb_1_T = id_rs_1[63:2]; // @[RocketCore.scala:574:38, :1325:26] wire [15:0] _inst_T = _ibuf_io_inst_0_bits_raw[15:0]; // @[RocketCore.scala:311:20, :578:62] wire [31:0] inst = _ibuf_io_inst_0_bits_rvc ? {16'h0, _inst_T} : _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20, :578:{21,62}] wire [1:0] _ex_reg_rs_lsb_0_T_1 = inst[1:0]; // @[RocketCore.scala:578:21, :580:31] wire [29:0] _ex_reg_rs_msb_0_T_1 = inst[31:2]; // @[RocketCore.scala:578:21, :581:32] wire _ex_reg_set_vconfig_T = ~id_xcpt; // @[RocketCore.scala:591:45, :1278:14] wire _ex_pc_valid_T = ex_reg_valid \| ex_reg_replay; // @[RocketCore.scala:248:35, :255:26, :595:34] wire ex_pc_valid = _ex_pc_valid_T \| ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :595:{34,51}] wire _wb_dcache_miss_T = ~io_dmem_resp_valid_0; // @[RocketCore.scala:153:7, :596:39] wire wb_dcache_miss = wb_ctrl_mem & _wb_dcache_miss_T; // @[RocketCore.scala:245:20, :596:{36,39}] wire _replay_ex_structural_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45] wire _replay_ex_structural_T_1 = ex_ctrl_mem & _replay_ex_structural_T; // @[RocketCore.scala:243:20, :597:{42,45}] wire _replay_ex_structural_T_2 = ~_div_io_req_ready; // @[RocketCore.scala:511:19, :598:45] wire _replay_ex_structural_T_3 = ex_ctrl_div & _replay_ex_structural_T_2; // @[RocketCore.scala:243:20, :598:{42,45}] wire _replay_ex_structural_T_4 = _replay_ex_structural_T_1 \| _replay_ex_structural_T_3; // @[RocketCore.scala:597:{42,64}, :598:42] wire replay_ex_structural = _replay_ex_structural_T_4; // @[RocketCore.scala:597:64, :598:63] wire replay_ex_load_use = wb_dcache_miss & ex_reg_load_use; // @[RocketCore.scala:253:35, :596:36, :600:43] wire _replay_ex_T = replay_ex_structural \| replay_ex_load_use; // @[RocketCore.scala:598:63, :600:43, :601:75] wire _replay_ex_T_1 = ex_reg_valid & _replay_ex_T; // @[RocketCore.scala:248:35, :601:{50,75}] wire replay_ex = ex_reg_replay \| _replay_ex_T_1; // @[RocketCore.scala:255:26, :601:{33,50}] wire _ctrl_killx_T = take_pc_mem_wb \| replay_ex; // @[RocketCore.scala:307:35, :601:33, :602:35] wire _ctrl_killx_T_1 = ~ex_reg_valid; // @[RocketCore.scala:248:35, :602:51] assign ctrl_killx = _ctrl_killx_T \| _ctrl_killx_T_1; // @[RocketCore.scala:602:{35,48,51}] assign io_fpu_killx_0 = ctrl_killx; // @[RocketCore.scala:153:7, :602:48] wire _GEN_47 = ex_ctrl_mem_cmd == 5'h7; // @[RocketCore.scala:243:20, :604:40] wire _ex_slow_bypass_T; // @[RocketCore.scala:604:40] assign _ex_slow_bypass_T = _GEN_47; // @[RocketCore.scala:604:40] wire _mem_reg_load_T_3; // @[package.scala:16:47] assign _mem_reg_load_T_3 = _GEN_47; // @[package.scala:16:47] wire _mem_reg_store_T_3; // @[Consts.scala:90:66] assign _mem_reg_store_T_3 = _GEN_47; // @[RocketCore.scala:604:40] wire _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_3 = _GEN_47; // @[package.scala:16:47] wire _ex_slow_bypass_T_1 = ~(ex_reg_mem_size[1]); // @[RocketCore.scala:257:28, :604:69] wire ex_slow_bypass = _ex_slow_bypass_T \| _ex_slow_bypass_T_1; // @[RocketCore.scala:604:{40,50,69}] wire _ex_sfence_T_1 = ex_ctrl_mem_cmd == 5'h14; // @[RocketCore.scala:243:20, :605:64] wire _ex_sfence_T_2 = ex_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:243:20, :605:96] wire _ex_sfence_T_3 = _ex_sfence_T_1 \| _ex_sfence_T_2; // @[RocketCore.scala:605:{64,77,96}] wire _ex_sfence_T_4 = ex_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:243:20, :605:129] wire _ex_sfence_T_5 = _ex_sfence_T_3 \| _ex_sfence_T_4; // @[RocketCore.scala:605:{77,110,129}] wire ex_sfence = _ex_sfence_T & _ex_sfence_T_5; // @[RocketCore.scala:605:{29,44,110}] wire ex_xcpt = ex_reg_xcpt_interrupt \| ex_reg_xcpt; // @[RocketCore.scala:247:35, :251:35, :608:28, :1278:14] wire _mem_pc_valid_T = mem_reg_valid \| mem_reg_replay; // @[RocketCore.scala:265:36, :269:36, :614:36] wire mem_pc_valid = _mem_pc_valid_T \| mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36, :614:{36,54}] wire _GEN_48 = mem_ctrl_branch & mem_br_taken; // @[RocketCore.scala:244:21, :284:25, :616:25] wire _mem_br_target_T_1; // @[RocketCore.scala:616:25] assign _mem_br_target_T_1 = _GEN_48; // @[RocketCore.scala:616:25] wire _mem_cfi_taken_T; // @[RocketCore.scala:626:40] assign _mem_cfi_taken_T = _GEN_48; // @[RocketCore.scala:616:25, :626:40] wire _mem_br_target_sign_T_1 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44] wire _mem_br_target_sign_T_4 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44] wire _mem_br_target_sign_T_2 = _mem_br_target_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire mem_br_target_sign = _mem_br_target_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire mem_br_target_hi_hi_hi = mem_br_target_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_br_target_b30_20_T_1 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41] wire [10:0] _mem_br_target_b30_20_T_4 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41] wire [10:0] _mem_br_target_b30_20_T_2 = _mem_br_target_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_br_target_b30_20 = {11{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_br_target_hi_hi_lo = mem_br_target_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_br_target_b19_12_T_3 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65] wire [7:0] _mem_br_target_b19_12_T_8 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65] wire [7:0] _mem_br_target_b19_12_T_4 = _mem_br_target_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_br_target_b19_12 = {8{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] mem_br_target_hi_lo_hi = mem_br_target_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_br_target_b11_T_4 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39] wire _mem_br_target_b0_T_3 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37] wire _mem_br_target_b11_T_15 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39] wire _mem_br_target_b0_T_11 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37] wire _mem_br_target_b11_T_5 = _mem_br_target_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _mem_br_target_b11_T_7 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39] wire _mem_br_target_b0_T_1 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37] wire _mem_br_target_b11_T_18 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39] wire _mem_br_target_b0_T_9 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37] wire _mem_br_target_b11_T_8 = _mem_br_target_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _mem_br_target_b11_T_9 = _mem_br_target_b11_T_8; // @[RocketCore.scala:1346:{18,43}] wire _mem_br_target_b11_T_10 = _mem_br_target_b11_T_9; // @[RocketCore.scala:1345:18, :1346:18] wire mem_br_target_b11 = _mem_br_target_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire mem_br_target_hi_lo_lo = mem_br_target_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _mem_br_target_b10_5_T_3 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62] wire [5:0] _mem_br_target_b10_5_T_7 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62] wire [5:0] mem_br_target_b10_5 = _mem_br_target_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_br_target_b4_1_T_4 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57] wire [3:0] _mem_br_target_b4_1_T_14 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57] wire [3:0] _mem_br_target_b4_1_T_9 = _mem_br_target_b4_1_T_4; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _mem_br_target_b4_1_T_6 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39] wire [3:0] _mem_br_target_b4_1_T_16 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39] wire [3:0] _mem_br_target_b4_1_T_7 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52] wire [3:0] _mem_br_target_b4_1_T_17 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52] wire [3:0] _mem_br_target_b4_1_T_8 = _mem_br_target_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] mem_br_target_b4_1 = _mem_br_target_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _mem_br_target_b0_T_5 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37] wire _mem_br_target_b0_T_13 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37] wire [9:0] mem_br_target_lo_hi = {mem_br_target_b10_5, mem_br_target_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_br_target_lo = {mem_br_target_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_br_target_hi_lo = {mem_br_target_hi_lo_hi, mem_br_target_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] mem_br_target_hi_hi = {mem_br_target_hi_hi_hi, mem_br_target_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] mem_br_target_hi = {mem_br_target_hi_hi, mem_br_target_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_2 = {mem_br_target_hi, mem_br_target_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_3 = _mem_br_target_T_2; // @[RocketCore.scala:1355:{8,53}] wire _mem_br_target_sign_T_5 = _mem_br_target_sign_T_4; // @[RocketCore.scala:1341:{44,49}] wire mem_br_target_sign_1 = _mem_br_target_sign_T_5; // @[RocketCore.scala:1341:{19,49}] wire _mem_br_target_b11_T_20 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1346:18] wire mem_br_target_hi_hi_hi_1 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_br_target_b30_20_T_5 = _mem_br_target_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_br_target_b30_20_1 = {11{mem_br_target_sign_1}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_br_target_hi_hi_lo_1 = mem_br_target_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_br_target_b19_12_T_9 = _mem_br_target_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_br_target_b19_12_1 = _mem_br_target_b19_12_T_9; // @[RocketCore.scala:1343:{21,73}] wire [7:0] mem_br_target_hi_lo_hi_1 = mem_br_target_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_br_target_b11_T_16 = _mem_br_target_b11_T_15; // @[RocketCore.scala:1345:{39,44}] wire _mem_br_target_b11_T_21 = _mem_br_target_b11_T_16; // @[RocketCore.scala:1345:{18,44}] wire _mem_br_target_b11_T_19 = _mem_br_target_b11_T_18; // @[RocketCore.scala:1346:{39,43}] wire mem_br_target_b11_1 = _mem_br_target_b11_T_21; // @[RocketCore.scala:1344:18, :1345:18] wire mem_br_target_hi_lo_lo_1 = mem_br_target_b11_1; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] mem_br_target_b10_5_1 = _mem_br_target_b10_5_T_7; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_br_target_b4_1_T_18 = _mem_br_target_b4_1_T_17; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _mem_br_target_b4_1_T_19 = _mem_br_target_b4_1_T_18; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] mem_br_target_b4_1_1 = _mem_br_target_b4_1_T_19; // @[RocketCore.scala:1348:19, :1349:19] wire [9:0] mem_br_target_lo_hi_1 = {mem_br_target_b10_5_1, mem_br_target_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_br_target_lo_1 = {mem_br_target_lo_hi_1, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_br_target_hi_lo_1 = {mem_br_target_hi_lo_hi_1, mem_br_target_hi_lo_lo_1}; // @[RocketCore.scala:1355:8] wire [11:0] mem_br_target_hi_hi_1 = {mem_br_target_hi_hi_hi_1, mem_br_target_hi_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [20:0] mem_br_target_hi_1 = {mem_br_target_hi_hi_1, mem_br_target_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_4 = {mem_br_target_hi_1, mem_br_target_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_5 = _mem_br_target_T_4; // @[RocketCore.scala:1355:{8,53}] wire [3:0] _mem_br_target_T_6 = mem_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:266:36, :618:8] wire [31:0] _mem_br_target_T_7 = mem_ctrl_jal ? _mem_br_target_T_5 : {{28{_mem_br_target_T_6[3]}}, _mem_br_target_T_6}; // @[RocketCore.scala:244:21, :617:8, :618:8, :1355:53] wire [31:0] _mem_br_target_T_8 = _mem_br_target_T_1 ? _mem_br_target_T_3 : _mem_br_target_T_7; // @[RocketCore.scala:616:{8,25}, :617:8, :1355:53] wire [40:0] _mem_br_target_T_9 = {_mem_br_target_T[39], _mem_br_target_T} + {{9{_mem_br_target_T_8[31]}}, _mem_br_target_T_8}; // @[RocketCore.scala:615:{34,41}, :616:8] wire [39:0] _mem_br_target_T_10 = _mem_br_target_T_9[39:0]; // @[RocketCore.scala:615:41] wire [39:0] mem_br_target = _mem_br_target_T_10; // @[RocketCore.scala:615:41] wire _mem_npc_T = mem_ctrl_jalr \| mem_reg_sfence; // @[RocketCore.scala:244:21, :276:27, :619:36] wire [24:0] _mem_npc_a_T = mem_reg_wdata[63:39]; // @[RocketCore.scala:282:26, :1293:17] wire [24:0] mem_npc_a = _mem_npc_a_T; // @[RocketCore.scala:1293:{17,23}] wire _mem_npc_msb_T = mem_npc_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _mem_npc_msb_T_1 = &mem_npc_a; // @[RocketCore.scala:1293:23, :1294:34] wire _mem_npc_msb_T_2 = _mem_npc_msb_T \| _mem_npc_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _mem_npc_msb_T_3 = mem_reg_wdata[39]; // @[RocketCore.scala:282:26, :1294:46] wire _mem_npc_msb_T_4 = mem_reg_wdata[38]; // @[RocketCore.scala:282:26, :1294:54] wire _mem_npc_msb_T_5 = ~_mem_npc_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire mem_npc_msb = _mem_npc_msb_T_2 ? _mem_npc_msb_T_3 : _mem_npc_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] wire [39:0] _mem_npc_T_2 = {mem_npc_msb, _mem_npc_T_1}; // @[RocketCore.scala:1294:18, :1295:{8,16}] wire [39:0] _mem_npc_T_3 = _mem_npc_T_2; // @[RocketCore.scala:619:106, :1295:8] wire [39:0] _mem_npc_T_4 = _mem_npc_T ? _mem_npc_T_3 : mem_br_target; // @[RocketCore.scala:615:41, :619:{21,36,106}] wire [39:0] _mem_npc_T_5 = _mem_npc_T_4 & 40'hFFFFFFFFFE; // @[RocketCore.scala:619:{21,129}] wire [39:0] _mem_npc_T_6 = _mem_npc_T_5; // @[RocketCore.scala:619:129] wire [39:0] mem_npc = _mem_npc_T_6; // @[RocketCore.scala:619:{129,139}] wire _mem_wrong_npc_T = mem_npc != ex_reg_pc; // @[RocketCore.scala:256:22, :619:139, :621:30] wire _mem_wrong_npc_T_1 = _ibuf_io_inst_0_valid \| io_imem_resp_valid_0; // @[RocketCore.scala:153:7, :311:20, :622:31] wire _mem_wrong_npc_T_2 = mem_npc != _ibuf_io_pc; // @[RocketCore.scala:311:20, :619:139, :622:62] wire _mem_wrong_npc_T_3 = ~_mem_wrong_npc_T_1 \| _mem_wrong_npc_T_2; // @[RocketCore.scala:622:{8,31,62}] assign mem_wrong_npc = ex_pc_valid ? _mem_wrong_npc_T : _mem_wrong_npc_T_3; // @[RocketCore.scala:595:51, :621:{8,30}, :622:8] assign io_imem_bht_update_bits_mispredict_0 = mem_wrong_npc; // @[RocketCore.scala:153:7, :621:8] wire _mem_npc_misaligned_T_1 = ~_mem_npc_misaligned_T; // @[RocketCore.scala:623:{28,46}] wire _mem_npc_misaligned_T_2 = mem_npc[1]; // @[RocketCore.scala:619:139, :623:66] wire _mem_npc_misaligned_T_3 = _mem_npc_misaligned_T_1 & _mem_npc_misaligned_T_2; // @[RocketCore.scala:623:{28,56,66}] wire _mem_npc_misaligned_T_4 = ~mem_reg_sfence; // @[RocketCore.scala:276:27, :623:73] wire mem_npc_misaligned = _mem_npc_misaligned_T_3 & _mem_npc_misaligned_T_4; // @[RocketCore.scala:623:{56,70,73}] wire _mem_int_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27] wire _mem_int_wdata_T_1 = mem_ctrl_jalr ^ mem_npc_misaligned; // @[RocketCore.scala:244:21, :623:70, :624:59] wire _mem_int_wdata_T_2 = _mem_int_wdata_T & _mem_int_wdata_T_1; // @[RocketCore.scala:624:{27,41,59}] wire [63:0] _mem_int_wdata_T_4 = _mem_int_wdata_T_2 ? {{24{mem_br_target[39]}}, mem_br_target} : _mem_int_wdata_T_3; // @[RocketCore.scala:615:41, :624:{26,41,111}] wire [63:0] mem_int_wdata = _mem_int_wdata_T_4; // @[RocketCore.scala:624:{26,119}] wire _mem_cfi_T = mem_ctrl_branch \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :625:33] assign mem_cfi = _mem_cfi_T \| mem_ctrl_jal; // @[RocketCore.scala:244:21, :625:{33,50}] assign io_imem_btb_update_bits_isValid_0 = mem_cfi; // @[RocketCore.scala:153:7, :625:50] wire _mem_cfi_taken_T_1 = _mem_cfi_taken_T \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :626:{40,57}] wire mem_cfi_taken = _mem_cfi_taken_T_1 \| mem_ctrl_jal; // @[RocketCore.scala:244:21, :626:{57,74}] wire _mem_direction_misprediction_T_1 = mem_br_taken != _mem_direction_misprediction_T; // @[RocketCore.scala:284:25, :627:{69,85}] wire mem_direction_misprediction = mem_ctrl_branch & _mem_direction_misprediction_T_1; // @[RocketCore.scala:244:21, :627:{53,69}] wire _take_pc_mem_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :629:35] wire _take_pc_mem_T_1 = mem_reg_valid & _take_pc_mem_T; // @[RocketCore.scala:265:36, :629:{32,35}] wire _take_pc_mem_T_2 = mem_wrong_npc \| mem_reg_sfence; // @[RocketCore.scala:276:27, :621:8, :629:71] assign _take_pc_mem_T_3 = _take_pc_mem_T_1 & _take_pc_mem_T_2; // @[RocketCore.scala:629:{32,49,71}] assign take_pc_mem = _take_pc_mem_T_3; // @[RocketCore.scala:285:25, :629:49] wire _mem_reg_valid_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20] wire _mem_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :632:21] wire _mem_reg_replay_T_1 = _mem_reg_replay_T & replay_ex; // @[RocketCore.scala:601:33, :632:{21,37}] wire _mem_reg_xcpt_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20, :633:19] wire _mem_reg_xcpt_T_1 = _mem_reg_xcpt_T & ex_xcpt; // @[RocketCore.scala:633:{19,31}, :1278:14] wire _mem_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :634:29] wire _mem_reg_xcpt_interrupt_T_1 = _mem_reg_xcpt_interrupt_T & ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :634:{29,45}] wire _GEN_49 = ex_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47] wire _mem_reg_load_T; // @[package.scala:16:47] assign _mem_reg_load_T = _GEN_49; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = ex_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47] wire _mem_reg_load_T_1; // @[package.scala:16:47] assign _mem_reg_load_T_1 = _GEN_50; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_1 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = ex_ctrl_mem_cmd == 5'h6; // @[package.scala:16:47] wire _mem_reg_load_T_2; // @[package.scala:16:47] assign _mem_reg_load_T_2 = _GEN_51; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_2 = _GEN_51; // @[package.scala:16:47] wire _mem_reg_load_T_4 = _mem_reg_load_T \| _mem_reg_load_T_1; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_5 = _mem_reg_load_T_4 \| _mem_reg_load_T_2; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_6 = _mem_reg_load_T_5 \| _mem_reg_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_52 = ex_ctrl_mem_cmd == 5'h4; // @[package.scala:16:47] wire _mem_reg_load_T_7; // @[package.scala:16:47] assign _mem_reg_load_T_7 = _GEN_52; // @[package.scala:16:47] wire _mem_reg_store_T_5; // @[package.scala:16:47] assign _mem_reg_store_T_5 = _GEN_52; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_7; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_7 = _GEN_52; // @[package.scala:16:47] wire _GEN_53 = ex_ctrl_mem_cmd == 5'h9; // @[package.scala:16:47] wire _mem_reg_load_T_8; // @[package.scala:16:47] assign _mem_reg_load_T_8 = _GEN_53; // @[package.scala:16:47] wire _mem_reg_store_T_6; // @[package.scala:16:47] assign _mem_reg_store_T_6 = _GEN_53; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_8 = _GEN_53; // @[package.scala:16:47] wire _GEN_54 = ex_ctrl_mem_cmd == 5'hA; // @[package.scala:16:47] wire _mem_reg_load_T_9; // @[package.scala:16:47] assign _mem_reg_load_T_9 = _GEN_54; // @[package.scala:16:47] wire _mem_reg_store_T_7; // @[package.scala:16:47] assign _mem_reg_store_T_7 = _GEN_54; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_9 = _GEN_54; // @[package.scala:16:47] wire _GEN_55 = ex_ctrl_mem_cmd == 5'hB; // @[package.scala:16:47] wire _mem_reg_load_T_10; // @[package.scala:16:47] assign _mem_reg_load_T_10 = _GEN_55; // @[package.scala:16:47] wire _mem_reg_store_T_8; // @[package.scala:16:47] assign _mem_reg_store_T_8 = _GEN_55; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_10 = _GEN_55; // @[package.scala:16:47] wire _mem_reg_load_T_11 = _mem_reg_load_T_7 \| _mem_reg_load_T_8; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_12 = _mem_reg_load_T_11 \| _mem_reg_load_T_9; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_13 = _mem_reg_load_T_12 \| _mem_reg_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_56 = ex_ctrl_mem_cmd == 5'h8; // @[package.scala:16:47] wire _mem_reg_load_T_14; // @[package.scala:16:47] assign _mem_reg_load_T_14 = _GEN_56; // @[package.scala:16:47] wire _mem_reg_store_T_12; // @[package.scala:16:47] assign _mem_reg_store_T_12 = _GEN_56; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_14; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_14 = _GEN_56; // @[package.scala:16:47] wire _GEN_57 = ex_ctrl_mem_cmd == 5'hC; // @[package.scala:16:47] wire _mem_reg_load_T_15; // @[package.scala:16:47] assign _mem_reg_load_T_15 = _GEN_57; // @[package.scala:16:47] wire _mem_reg_store_T_13; // @[package.scala:16:47] assign _mem_reg_store_T_13 = _GEN_57; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_15 = _GEN_57; // @[package.scala:16:47] wire _GEN_58 = ex_ctrl_mem_cmd == 5'hD; // @[package.scala:16:47] wire _mem_reg_load_T_16; // @[package.scala:16:47] assign _mem_reg_load_T_16 = _GEN_58; // @[package.scala:16:47] wire _mem_reg_store_T_14; // @[package.scala:16:47] assign _mem_reg_store_T_14 = _GEN_58; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_16 = _GEN_58; // @[package.scala:16:47] wire _GEN_59 = ex_ctrl_mem_cmd == 5'hE; // @[package.scala:16:47] wire _mem_reg_load_T_17; // @[package.scala:16:47] assign _mem_reg_load_T_17 = _GEN_59; // @[package.scala:16:47] wire _mem_reg_store_T_15; // @[package.scala:16:47] assign _mem_reg_store_T_15 = _GEN_59; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_17 = _GEN_59; // @[package.scala:16:47] wire _GEN_60 = ex_ctrl_mem_cmd == 5'hF; // @[package.scala:16:47] wire _mem_reg_load_T_18; // @[package.scala:16:47] assign _mem_reg_load_T_18 = _GEN_60; // @[package.scala:16:47] wire _mem_reg_store_T_16; // @[package.scala:16:47] assign _mem_reg_store_T_16 = _GEN_60; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_18 = _GEN_60; // @[package.scala:16:47] wire _mem_reg_load_T_19 = _mem_reg_load_T_14 \| _mem_reg_load_T_15; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_20 = _mem_reg_load_T_19 \| _mem_reg_load_T_16; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_21 = _mem_reg_load_T_20 \| _mem_reg_load_T_17; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_22 = _mem_reg_load_T_21 \| _mem_reg_load_T_18; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_23 = _mem_reg_load_T_13 \| _mem_reg_load_T_22; // @[package.scala:81:59] wire _mem_reg_load_T_24 = _mem_reg_load_T_6 \| _mem_reg_load_T_23; // @[package.scala:81:59] wire _mem_reg_load_T_25 = ex_ctrl_mem & _mem_reg_load_T_24; // @[RocketCore.scala:243:20, :643:33] wire _mem_reg_store_T = ex_ctrl_mem_cmd == 5'h1; // @[RocketCore.scala:243:20] wire _mem_reg_store_T_1 = ex_ctrl_mem_cmd == 5'h11; // @[RocketCore.scala:243:20] wire _mem_reg_store_T_2 = _mem_reg_store_T \| _mem_reg_store_T_1; // @[Consts.scala:90:{32,42,49}] wire _mem_reg_store_T_4 = _mem_reg_store_T_2 \| _mem_reg_store_T_3; // @[Consts.scala:90:{42,59,66}] wire _mem_reg_store_T_9 = _mem_reg_store_T_5 \| _mem_reg_store_T_6; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_10 = _mem_reg_store_T_9 \| _mem_reg_store_T_7; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_11 = _mem_reg_store_T_10 \| _mem_reg_store_T_8; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_17 = _mem_reg_store_T_12 \| _mem_reg_store_T_13; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_18 = _mem_reg_store_T_17 \| _mem_reg_store_T_14; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_19 = _mem_reg_store_T_18 \| _mem_reg_store_T_15; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_20 = _mem_reg_store_T_19 \| _mem_reg_store_T_16; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_21 = _mem_reg_store_T_11 \| _mem_reg_store_T_20; // @[package.scala:81:59] wire _mem_reg_store_T_22 = _mem_reg_store_T_4 \| _mem_reg_store_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _mem_reg_store_T_23 = ex_ctrl_mem & _mem_reg_store_T_22; // @[RocketCore.scala:243:20, :644:34] wire [1:0] size = ex_ctrl_rocc ? 2'h3 : ex_reg_mem_size; // @[RocketCore.scala:243:20, :257:28, :664:21] wire [1:0] mem_reg_rs2_size = size; // @[RocketCore.scala:664:21] wire _mem_reg_rs2_T = mem_reg_rs2_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _mem_reg_rs2_T_1 = mem_reg_rs2_dat_padded[7:0]; // @[AMOALU.scala:13:27, :29:69] wire [15:0] _mem_reg_rs2_T_2 = {2{_mem_reg_rs2_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _mem_reg_rs2_T_3 = {2{_mem_reg_rs2_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _mem_reg_rs2_T_4 = {2{_mem_reg_rs2_T_3}}; // @[AMOALU.scala:29:32] wire _mem_reg_rs2_T_5 = mem_reg_rs2_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _mem_reg_rs2_T_6 = mem_reg_rs2_dat_padded[15:0]; // @[AMOALU.scala:13:27, :29:69] wire [31:0] _mem_reg_rs2_T_7 = {2{_mem_reg_rs2_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_reg_rs2_T_8 = {2{_mem_reg_rs2_T_7}}; // @[AMOALU.scala:29:32] wire _mem_reg_rs2_T_9 = mem_reg_rs2_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _mem_reg_rs2_T_10 = mem_reg_rs2_dat_padded[31:0]; // @[AMOALU.scala:13:27, :29:69] wire [63:0] _mem_reg_rs2_T_11 = {2{_mem_reg_rs2_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_reg_rs2_T_12 = _mem_reg_rs2_T_9 ? _mem_reg_rs2_T_11 : mem_reg_rs2_dat_padded; // @[AMOALU.scala:13:27, :29:{13,19,32}] wire [63:0] _mem_reg_rs2_T_13 = _mem_reg_rs2_T_5 ? _mem_reg_rs2_T_8 : _mem_reg_rs2_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _mem_reg_rs2_T_14 = _mem_reg_rs2_T ? _mem_reg_rs2_T_4 : _mem_reg_rs2_T_13; // @[AMOALU.scala:29:{13,19,32}] wire _mem_breakpoint_T = mem_reg_load & _bpu_io_xcpt_ld; // @[RocketCore.scala:273:36, :414:19, :677:38] wire _mem_breakpoint_T_1 = mem_reg_store & _bpu_io_xcpt_st; // @[RocketCore.scala:274:36, :414:19, :677:75] wire mem_breakpoint = _mem_breakpoint_T \| _mem_breakpoint_T_1; // @[RocketCore.scala:677:{38,57,75}] wire _mem_debug_breakpoint_T = mem_reg_load & _bpu_io_debug_ld; // @[RocketCore.scala:273:36, :414:19, :678:44] wire _mem_debug_breakpoint_T_1 = mem_reg_store & _bpu_io_debug_st; // @[RocketCore.scala:274:36, :414:19, :678:82] wire mem_debug_breakpoint = _mem_debug_breakpoint_T \| _mem_debug_breakpoint_T_1; // @[RocketCore.scala:678:{44,64,82}] wire mem_ldst_xcpt = mem_debug_breakpoint \| mem_breakpoint; // @[RocketCore.scala:677:57, :678:64, :1278:{14,35}] wire [3:0] mem_ldst_cause = mem_debug_breakpoint ? 4'hE : 4'h3; // @[Mux.scala:50:70] wire _T_74 = mem_reg_xcpt_interrupt \| mem_reg_xcpt; // @[RocketCore.scala:264:36, :268:36, :684:29] wire _T_75 = mem_reg_valid & mem_npc_misaligned; // @[RocketCore.scala:265:36, :623:70, :685:20] wire mem_xcpt = _T_74 \| _T_75 \| mem_reg_valid & mem_ldst_xcpt; // @[RocketCore.scala:265:36, :684:29, :685:20, :686:20, :1278:{14,35}] wire [63:0] mem_cause = _T_74 ? mem_reg_cause : {60'h0, _T_75 ? 4'h0 : mem_ldst_cause}; // @[Mux.scala:50:70] wire dcache_kill_mem = _dcache_kill_mem_T & io_dmem_replay_next_0; // @[RocketCore.scala:153:7, :695:{39,55}] wire _fpu_kill_mem_T = mem_reg_valid & mem_ctrl_fp; // @[RocketCore.scala:244:21, :265:36, :696:36] wire fpu_kill_mem = _fpu_kill_mem_T & io_fpu_nack_mem_0; // @[RocketCore.scala:153:7, :696:{36,51}] wire _vec_kill_mem_T = mem_reg_valid & mem_ctrl_mem; // @[RocketCore.scala:244:21, :265:36, :697:36] wire _replay_mem_T = dcache_kill_mem \| mem_reg_replay; // @[RocketCore.scala:269:36, :695:55, :699:37] wire _replay_mem_T_1 = _replay_mem_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :699:{37,55}] wire _replay_mem_T_2 = _replay_mem_T_1; // @[RocketCore.scala:699:{55,71}] wire replay_mem = _replay_mem_T_2; // @[RocketCore.scala:699:{71,87}] wire _killm_common_T = dcache_kill_mem \| take_pc_wb; // @[RocketCore.scala:304:24, :695:55, :700:38] wire _killm_common_T_1 = _killm_common_T \| mem_reg_xcpt; // @[RocketCore.scala:268:36, :700:{38,52}] wire _killm_common_T_2 = ~mem_reg_valid; // @[RocketCore.scala:265:36, :700:71] assign killm_common = _killm_common_T_1 \| _killm_common_T_2; // @[RocketCore.scala:700:{52,68,71}] assign io_fpu_killm_0 = killm_common; // @[RocketCore.scala:153:7, :700:68] wire _div_io_kill_T = _div_io_req_ready & _div_io_req_valid_T; // @[Decoupled.scala:51:35] reg div_io_kill_REG; // @[RocketCore.scala:701:41] wire _div_io_kill_T_1 = killm_common & div_io_kill_REG; // @[RocketCore.scala:700:68, :701:{31,41}] wire _ctrl_killm_T = killm_common \| mem_xcpt; // @[RocketCore.scala:700:68, :702:33, :1278:14] wire _ctrl_killm_T_1 = _ctrl_killm_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :702:{33,45}] wire ctrl_killm = _ctrl_killm_T_1; // @[RocketCore.scala:702:{45,61}] wire _wb_reg_valid_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19] wire _wb_reg_replay_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34] wire _wb_reg_replay_T_1 = replay_mem & _wb_reg_replay_T; // @[RocketCore.scala:699:87, :706:{31,34}] wire _wb_reg_xcpt_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :707:30] wire _wb_reg_xcpt_T_1 = mem_xcpt & _wb_reg_xcpt_T; // @[RocketCore.scala:707:{27,30}, :1278:14] wire _wb_reg_xcpt_T_3 = _wb_reg_xcpt_T_1; // @[RocketCore.scala:707:{27,42}] wire _wb_reg_flush_pipe_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19, :708:24] wire _wb_reg_flush_pipe_T_1 = _wb_reg_flush_pipe_T & mem_reg_flush_pipe; // @[RocketCore.scala:270:36, :708:{24,36}] wire _wb_reg_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :712:25] wire _wb_reg_wdata_T_1 = _wb_reg_wdata_T & mem_ctrl_fp; // @[RocketCore.scala:244:21, :712:{25,39}] wire _wb_reg_wdata_T_2 = _wb_reg_wdata_T_1 & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :712:{39,54}] wire [63:0] _wb_reg_wdata_T_3 = _wb_reg_wdata_T_2 ? io_fpu_toint_data_0 : mem_int_wdata; // @[RocketCore.scala:153:7, :624:119, :712:{24,54}] wire _wb_reg_hfence_v_T = mem_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:244:21, :721:41] wire _wb_reg_hfence_g_T = mem_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:244:21, :722:41] wire _T_113 = wb_reg_valid & wb_ctrl_mem; // @[RocketCore.scala:245:20, :288:35, :730:19] wire _T_100 = _T_113 & io_dmem_s2_xcpt_pf_st_0; // @[RocketCore.scala:153:7, :730:{19,34}] wire _T_102 = _T_113 & io_dmem_s2_xcpt_pf_ld_0; // @[RocketCore.scala:153:7, :730:19, :731:34] wire _T_108 = _T_113 & io_dmem_s2_xcpt_ae_st_0; // @[RocketCore.scala:153:7, :730:19, :734:34] wire _T_110 = _T_113 & io_dmem_s2_xcpt_ae_ld_0; // @[RocketCore.scala:153:7, :730:19, :735:34] wire _T_112 = _T_113 & io_dmem_s2_xcpt_ma_st_0; // @[RocketCore.scala:153:7, :730:19, :736:34] wire wb_xcpt = wb_reg_xcpt \| _T_100 \| _T_102 \| _T_108 \| _T_110 \| _T_112 \| _T_113 & io_dmem_s2_xcpt_ma_ld_0; // @[RocketCore.scala:153:7, :289:35, :730:{19,34}, :731:34, :734:34, :735:34, :736:34, :737:34, :1278:{14,35}] wire [63:0] wb_cause = wb_reg_xcpt ? wb_reg_cause : {59'h0, _T_100 ? 5'hF : _T_102 ? 5'hD : {2'h0, _T_108 ? 3'h7 : _T_110 ? 3'h5 : {1'h1, _T_112, 1'h0}}}; // @[Mux.scala:50:70] wire _wb_pc_valid_T = wb_reg_valid \| wb_reg_replay; // @[RocketCore.scala:288:35, :290:35, :754:34] wire wb_pc_valid = _wb_pc_valid_T \| wb_reg_xcpt; // @[RocketCore.scala:289:35, :754:{34,51}] wire wb_wxd = wb_reg_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :288:35, :755:29] wire _wb_set_sboard_T = wb_ctrl_div \| wb_dcache_miss; // @[RocketCore.scala:245:20, :596:36, :756:35] wire _wb_set_sboard_T_1 = _wb_set_sboard_T \| wb_ctrl_rocc; // @[RocketCore.scala:245:20, :756:{35,53}] wire wb_set_sboard = _wb_set_sboard_T_1 \| wb_ctrl_vec; // @[RocketCore.scala:245:20, :756:{53,69}] wire replay_wb_common = io_dmem_s2_nack_0 \| wb_reg_replay; // @[RocketCore.scala:153:7, :290:35, :757:42] wire replay_wb_rocc = _replay_wb_rocc_T; // @[RocketCore.scala:758:{37,53}] wire _replay_wb_T = replay_wb_common \| replay_wb_rocc; // @[RocketCore.scala:757:42, :758:53, :761:36] wire _replay_wb_T_1 = _replay_wb_T; // @[RocketCore.scala:761:{36,54}] wire replay_wb = _replay_wb_T_1; // @[RocketCore.scala:761:{54,71}] wire _take_pc_wb_T = replay_wb \| wb_xcpt; // @[RocketCore.scala:761:71, :762:27, :1278:14] wire _take_pc_wb_T_1 = _take_pc_wb_T \| _csr_io_eret; // @[RocketCore.scala:341:19, :762:{27,38}] assign _take_pc_wb_T_2 = _take_pc_wb_T_1 \| wb_reg_flush_pipe; // @[RocketCore.scala:291:35, :762:{38,53}] assign take_pc_wb = _take_pc_wb_T_2; // @[RocketCore.scala:304:24, :762:53] wire _dmem_resp_xpu_T = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45] wire dmem_resp_fpu = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45, :766:45] wire dmem_resp_xpu = ~_dmem_resp_xpu_T; // @[RocketCore.scala:765:{23,45}] assign dmem_resp_waddr = io_dmem_resp_bits_tag_0[5:1]; // @[RocketCore.scala:153:7, :767:46] assign io_fpu_ll_resp_tag_0 = dmem_resp_waddr; // @[RocketCore.scala:153:7, :767:46] wire dmem_resp_valid = io_dmem_resp_valid_0 & io_dmem_resp_bits_has_data_0; // @[RocketCore.scala:153:7, :768:44] wire dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay_0; // @[RocketCore.scala:153:7, :768:44, :769:42] wire [63:0] ll_wdata; // @[RocketCore.scala:779:26] wire [4:0] ll_waddr; // @[RocketCore.scala:780:26] wire _ll_wen_T = ll_arb_io_out_ready & _ll_arb_io_out_valid; // @[Decoupled.scala:51:35] wire ll_wen; // @[RocketCore.scala:781:24] wire _ll_arb_io_out_ready_T = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26] wire _T_143 = dmem_resp_replay & dmem_resp_xpu; // @[RocketCore.scala:765:23, :769:42, :809:26] assign ll_arb_io_out_ready = ~_T_143 & _ll_arb_io_out_ready_T; // @[RocketCore.scala:782:{23,26}, :809:{26,44}, :810:25] assign ll_waddr = _T_143 ? dmem_resp_waddr : _ll_arb_io_out_bits_tag; // @[RocketCore.scala:767:46, :776:22, :780:26, :809:{26,44}, :811:14] assign ll_wen = _T_143 \| _ll_wen_T; // @[Decoupled.scala:51:35] wire _wb_valid_T = ~replay_wb; // @[RocketCore.scala:761:71, :815:34] wire _wb_valid_T_1 = wb_reg_valid & _wb_valid_T; // @[RocketCore.scala:288:35, :815:{31,34}] wire _wb_valid_T_2 = ~wb_xcpt; // @[RocketCore.scala:815:48, :1278:14] wire wb_valid = _wb_valid_T_1 & _wb_valid_T_2; // @[RocketCore.scala:815:{31,45,48}] wire wb_wen = wb_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :815:45, :816:25] wire rf_wen = wb_wen \| ll_wen; // @[RocketCore.scala:781:24, :816:25, :817:23] wire [4:0] rf_waddr = ll_wen ? ll_waddr : wb_waddr; // @[RocketCore.scala:455:36, :780:26, :781:24, :818:21] wire [4:0] xrfWriteBundle_wrdst = rf_waddr; // @[RocketCore.scala:818:21, :1249:28] wire _rf_wdata_T = dmem_resp_valid & dmem_resp_xpu; // @[RocketCore.scala:765:23, :768:44, :819:38] wire _rf_wdata_T_2 = \|wb_ctrl_csr; // @[RocketCore.scala:245:20, :821:34] wire [63:0] _rf_wdata_T_4 = _rf_wdata_T_2 ? _csr_io_rw_rdata : _rf_wdata_T_3; // @[RocketCore.scala:341:19, :821:{21,34}, :822:21] wire [63:0] _rf_wdata_T_5 = ll_wen ? ll_wdata : _rf_wdata_T_4; // @[RocketCore.scala:779:26, :781:24, :820:21, :821:21] wire [63:0] rf_wdata = _rf_wdata_T ? _rf_wdata_T_1 : _rf_wdata_T_5; // @[RocketCore.scala:819:{21,38,78}, :820:21] wire [63:0] coreMonitorBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1186:31] wire [63:0] xrfWriteBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1249:28] wire [63:0] _id_rs_T_4; // @[RocketCore.scala:1326:25] assign id_rs_0 = rf_wen & (\|rf_waddr) & rf_waddr == id_raddr1 ? rf_wdata : _id_rs_T_4; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}] wire [63:0] _id_rs_T_9; // @[RocketCore.scala:1326:25] assign id_rs_1 = rf_wen & (\|rf_waddr) & rf_waddr == id_raddr2 ? rf_wdata : _id_rs_T_9; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}] wire [1:0] _csr_io_inst_0_T = wb_reg_raw_inst[1:0]; // @[RocketCore.scala:301:28, :832:66] wire _csr_io_inst_0_T_1 = &_csr_io_inst_0_T; // @[RocketCore.scala:832:{66,73}] wire [15:0] _csr_io_inst_0_T_2 = wb_reg_inst[31:16]; // @[RocketCore.scala:300:24, :832:91] wire [15:0] _csr_io_inst_0_T_3 = _csr_io_inst_0_T_1 ? _csr_io_inst_0_T_2 : 16'h0; // @[RocketCore.scala:832:{50,73,91}] wire [15:0] _csr_io_inst_0_T_4 = wb_reg_raw_inst[15:0]; // @[RocketCore.scala:301:28, :832:119] wire [31:0] _csr_io_inst_0_T_5 = {_csr_io_inst_0_T_3, _csr_io_inst_0_T_4}; // @[RocketCore.scala:832:{46,50,119}] wire [4:0] _csr_io_fcsr_flags_bits_T = {5{io_fpu_fcsr_flags_valid_0}}; // @[RocketCore.scala:153:7, :839:59] wire [4:0] _csr_io_fcsr_flags_bits_T_1 = io_fpu_fcsr_flags_bits_0 & _csr_io_fcsr_flags_bits_T; // @[RocketCore.scala:153:7, :839:{53,59}] wire [4:0] _csr_io_fcsr_flags_bits_T_4 = _csr_io_fcsr_flags_bits_T_1; // @[RocketCore.scala:839:{53,89}] wire [31:0] _io_fpu_time_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29] wire [31:0] _coreMonitorBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1191:41] wire [31:0] _xrfWriteBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1254:38] assign io_fpu_time_0 = {32'h0, _io_fpu_time_T}; // @[RocketCore.scala:153:7, :840:{15,29}] wire tval_dmem_addr = ~wb_reg_xcpt; // @[RocketCore.scala:289:35, :845:24] wire _tval_any_addr_T = wb_reg_cause == 64'h3; // @[package.scala:16:47] wire _tval_any_addr_T_1 = wb_reg_cause == 64'h1; // @[package.scala:16:47] wire _tval_any_addr_T_2 = wb_reg_cause == 64'hC; // @[package.scala:16:47] wire _GEN_61 = wb_reg_cause == 64'h14; // @[package.scala:16:47] wire _tval_any_addr_T_3; // @[package.scala:16:47] assign _tval_any_addr_T_3 = _GEN_61; // @[package.scala:16:47] wire _htval_valid_imem_T; // @[RocketCore.scala:853:56] assign _htval_valid_imem_T = _GEN_61; // @[package.scala:16:47] wire _tval_any_addr_T_4 = _tval_any_addr_T \| _tval_any_addr_T_1; // @[package.scala:16:47, :81:59] wire _tval_any_addr_T_5 = _tval_any_addr_T_4 \| _tval_any_addr_T_2; // @[package.scala:16:47, :81:59] wire _tval_any_addr_T_6 = _tval_any_addr_T_5 \| _tval_any_addr_T_3; // @[package.scala:16:47, :81:59] wire tval_any_addr = tval_dmem_addr \| _tval_any_addr_T_6; // @[package.scala:81:59] wire tval_inst = wb_reg_cause == 64'h2; // @[RocketCore.scala:292:35, :848:32] wire _tval_valid_T = tval_any_addr \| tval_inst; // @[RocketCore.scala:846:38, :848:32, :849:46] wire tval_valid = wb_xcpt & _tval_valid_T; // @[RocketCore.scala:849:{28,46}, :1278:14] wire _csr_io_gva_T = tval_any_addr & _csr_io_status_v; // @[RocketCore.scala:341:19, :846:38, :850:43] wire _csr_io_gva_T_1 = tval_dmem_addr & wb_reg_hls_or_dv; // @[RocketCore.scala:297:29, :845:24, :850:80] wire _csr_io_gva_T_2 = _csr_io_gva_T \| _csr_io_gva_T_1; // @[RocketCore.scala:850:{43,62,80}] wire _csr_io_gva_T_3 = wb_xcpt & _csr_io_gva_T_2; // @[RocketCore.scala:850:{25,62}, :1278:14] wire [24:0] _csr_io_tval_a_T = wb_reg_wdata[63:39]; // @[RocketCore.scala:302:25, :1293:17] wire [24:0] csr_io_tval_a = _csr_io_tval_a_T; // @[RocketCore.scala:1293:{17,23}] wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _csr_io_tval_msb_T_1 = &csr_io_tval_a; // @[RocketCore.scala:1293:23, :1294:34] wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T \| _csr_io_tval_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _csr_io_tval_msb_T_3 = wb_reg_wdata[39]; // @[RocketCore.scala:302:25, :1294:46] wire _csr_io_tval_msb_T_4 = wb_reg_wdata[38]; // @[RocketCore.scala:302:25, :1294:54] wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] assign io_imem_sfence_bits_addr_0 = wb_reg_wdata[38:0]; // @[RocketCore.scala:153:7, :302:25, :1295:16] wire [38:0] _csr_io_tval_T = wb_reg_wdata[38:0]; // @[RocketCore.scala:302:25, :1295:16] wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}] wire [39:0] _csr_io_tval_T_2 = tval_valid ? _csr_io_tval_T_1 : 40'h0; // @[RocketCore.scala:849:28, :851:21, :1295:8] wire htval_valid_imem = wb_reg_xcpt & _htval_valid_imem_T; // @[RocketCore.scala:289:35, :853:{40,56}] wire [39:0] htval_imem = htval_valid_imem ? io_imem_gpa_bits_0 : 40'h0; // @[RocketCore.scala:153:7, :853:40, :854:25] wire [39:0] _htval_T = htval_imem; // @[RocketCore.scala:854:25, :860:29] wire _htval_valid_dmem_T = wb_xcpt & tval_dmem_addr; // @[RocketCore.scala:845:24, :857:36, :1278:14] wire [1:0] _htval_valid_dmem_T_4 = {io_dmem_s2_xcpt_pf_ld_0, io_dmem_s2_xcpt_pf_st_0}; // @[RocketCore.scala:153:7, :857:110] wire _htval_valid_dmem_T_5 = \|_htval_valid_dmem_T_4; // @[RocketCore.scala:857:{110,117}] wire _htval_valid_dmem_T_6 = ~_htval_valid_dmem_T_5; // @[RocketCore.scala:857:{90,117}] wire [39:0] htval = _htval_T; // @[RocketCore.scala:860:{29,43}] wire _mhtinst_read_pseudo_T = io_imem_gpa_is_pte_0 & htval_valid_imem; // @[RocketCore.scala:153:7, :853:40, :862:51] wire mhtinst_read_pseudo = _mhtinst_read_pseudo_T; // @[RocketCore.scala:862:{51,72}] wire [11:0] _csr_io_rw_addr_T = wb_reg_inst[31:20]; // @[RocketCore.scala:300:24, :909:32] wire [2:0] _csr_io_rw_cmd_T = {~wb_reg_valid, 2'h0}; // @[RocketCore.scala:288:35] wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala:183:{11,15}] wire [2:0] _csr_io_rw_cmd_T_2 = wb_ctrl_csr & _csr_io_rw_cmd_T_1; // @[RocketCore.scala:245:20] assign io_bpwatch_0_action_0 = {2'h0, _csr_io_bp_0_control_action}; // @[RocketCore.scala:153:7, :341:19, :962:18] wire _hazard_targets_T = \|id_raddr1; // @[RocketCore.scala:326:72, :969:55, :1326:41] wire hazard_targets_0_1 = id_ctrl_rxs1 & _hazard_targets_T; // @[RocketCore.scala:321:21, :969:{42,55}] wire _hazard_targets_T_1 = \|id_raddr2; // @[RocketCore.scala:326:72, :970:55, :1326:41] wire hazard_targets_1_1 = id_ctrl_rxs2 & _hazard_targets_T_1; // @[RocketCore.scala:321:21, :970:{42,55}] wire _hazard_targets_T_2 = \|id_waddr; // @[RocketCore.scala:326:72, :971:55] wire hazard_targets_2_1 = id_ctrl_wxd & _hazard_targets_T_2; // @[RocketCore.scala:321:21, :971:{42,55}] reg [31:0] _r; // @[RocketCore.scala:1305:29] wire [30:0] _r_T = _r[31:1]; // @[RocketCore.scala:1305:29, :1306:35] wire [31:0] r = {_r_T, 1'h0}; // @[RocketCore.scala:1306:{35,40}] wire [31:0] _GEN_62 = {27'h0, id_raddr1}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T = r >> _GEN_62; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_1 = _id_sboard_hazard_T[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_2 = ll_waddr == id_raddr1; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_3 = ll_wen & _id_sboard_hazard_T_2; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_4 = ~_id_sboard_hazard_T_3; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_5 = _id_sboard_hazard_T_1 & _id_sboard_hazard_T_4; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_6 = hazard_targets_0_1 & _id_sboard_hazard_T_5; // @[RocketCore.scala:969:42, :984:77, :1287:27] wire [31:0] _GEN_63 = {27'h0, id_raddr2}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_7 = r >> _GEN_63; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_8 = _id_sboard_hazard_T_7[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_9 = ll_waddr == id_raddr2; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_10 = ll_wen & _id_sboard_hazard_T_9; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_11 = ~_id_sboard_hazard_T_10; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_12 = _id_sboard_hazard_T_8 & _id_sboard_hazard_T_11; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_13 = hazard_targets_1_1 & _id_sboard_hazard_T_12; // @[RocketCore.scala:970:42, :984:77, :1287:27] wire [31:0] _GEN_64 = {27'h0, id_waddr}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_14 = r >> _GEN_64; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_15 = _id_sboard_hazard_T_14[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_16 = ll_waddr == id_waddr; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_17 = ll_wen & _id_sboard_hazard_T_16; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_18 = ~_id_sboard_hazard_T_17; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_19 = _id_sboard_hazard_T_15 & _id_sboard_hazard_T_18; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_20 = hazard_targets_2_1 & _id_sboard_hazard_T_19; // @[RocketCore.scala:971:42, :984:77, :1287:27] wire _id_sboard_hazard_T_21 = _id_sboard_hazard_T_6 \| _id_sboard_hazard_T_13; // @[RocketCore.scala:1287:{27,50}] wire id_sboard_hazard = _id_sboard_hazard_T_21 \| _id_sboard_hazard_T_20; // @[RocketCore.scala:1287:{27,50}] wire [31:0] _id_stall_fpu_T_4 = 32'h1 << wb_waddr; // @[RocketCore.scala:455:36, :1309:58] wire _ex_cannot_bypass_T = \|ex_ctrl_csr; // @[RocketCore.scala:243:20, :988:38] wire _ex_cannot_bypass_T_1 = _ex_cannot_bypass_T \| ex_ctrl_jalr; // @[RocketCore.scala:243:20, :988:{38,48}] wire _ex_cannot_bypass_T_2 = _ex_cannot_bypass_T_1 \| ex_ctrl_mem; // @[RocketCore.scala:243:20, :988:{48,64}] wire _ex_cannot_bypass_T_3 = _ex_cannot_bypass_T_2 \| ex_ctrl_mul; // @[RocketCore.scala:243:20, :988:{64,79}] wire _ex_cannot_bypass_T_4 = _ex_cannot_bypass_T_3 \| ex_ctrl_div; // @[RocketCore.scala:243:20, :988:{79,94}] wire _ex_cannot_bypass_T_5 = _ex_cannot_bypass_T_4 \| ex_ctrl_fp; // @[RocketCore.scala:243:20, :988:{94,109}] wire _ex_cannot_bypass_T_6 = _ex_cannot_bypass_T_5 \| ex_ctrl_rocc; // @[RocketCore.scala:243:20, :988:{109,123}] wire ex_cannot_bypass = _ex_cannot_bypass_T_6; // @[RocketCore.scala:988:{123,139}] wire _data_hazard_ex_T_1 = hazard_targets_0_1 & _data_hazard_ex_T; // @[RocketCore.scala:969:42, :989:70, :1287:27] wire _data_hazard_ex_T_3 = hazard_targets_1_1 & _data_hazard_ex_T_2; // @[RocketCore.scala:970:42, :989:70, :1287:27] wire _GEN_65 = id_waddr == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :989:70] wire _data_hazard_ex_T_4; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T_4 = _GEN_65; // @[RocketCore.scala:989:70] wire _fp_data_hazard_ex_T_7; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_7 = _GEN_65; // @[RocketCore.scala:989:70, :990:90] wire _data_hazard_ex_T_5 = hazard_targets_2_1 & _data_hazard_ex_T_4; // @[RocketCore.scala:971:42, :989:70, :1287:27] wire _data_hazard_ex_T_6 = _data_hazard_ex_T_1 \| _data_hazard_ex_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_ex_T_7 = _data_hazard_ex_T_6 \| _data_hazard_ex_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_ex = ex_ctrl_wxd & _data_hazard_ex_T_7; // @[RocketCore.scala:243:20, :989:36, :1287:50] wire _fp_data_hazard_ex_T = id_ctrl_fp & ex_ctrl_wfd; // @[RocketCore.scala:243:20, :321:21, :990:38] wire _fp_data_hazard_ex_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_ex_T_1; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_ex_T_3; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_5 = id_raddr3 == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :990:90] wire _fp_data_hazard_ex_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_ex_T_5; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_ex_T_7; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_9 = _fp_data_hazard_ex_T_2 \| _fp_data_hazard_ex_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_ex_T_10 = _fp_data_hazard_ex_T_9 \| _fp_data_hazard_ex_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_ex_T_11 = _fp_data_hazard_ex_T_10 \| _fp_data_hazard_ex_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_ex = _fp_data_hazard_ex_T & _fp_data_hazard_ex_T_11; // @[RocketCore.scala:990:{38,53}, :1287:50] wire _id_ex_hazard_T = data_hazard_ex & ex_cannot_bypass; // @[RocketCore.scala:988:139, :989:36, :991:54] wire _id_ex_hazard_T_1 = _id_ex_hazard_T \| fp_data_hazard_ex; // @[RocketCore.scala:990:53, :991:{54,74}] wire id_ex_hazard = ex_reg_valid & _id_ex_hazard_T_1; // @[RocketCore.scala:248:35, :991:{35,74}] wire _mem_cannot_bypass_T = \|mem_ctrl_csr; // @[RocketCore.scala:244:21, :997:40] wire _mem_cannot_bypass_T_1 = mem_ctrl_mem & mem_mem_cmd_bh; // @[RocketCore.scala:244:21, :995:41, :997:66] wire _mem_cannot_bypass_T_2 = _mem_cannot_bypass_T \| _mem_cannot_bypass_T_1; // @[RocketCore.scala:997:{40,50,66}] wire _mem_cannot_bypass_T_3 = _mem_cannot_bypass_T_2 \| mem_ctrl_mul; // @[RocketCore.scala:244:21, :997:{50,84}] wire _mem_cannot_bypass_T_4 = _mem_cannot_bypass_T_3 \| mem_ctrl_div; // @[RocketCore.scala:244:21, :997:{84,100}] wire _mem_cannot_bypass_T_5 = _mem_cannot_bypass_T_4 \| mem_ctrl_fp; // @[RocketCore.scala:244:21, :997:{100,116}] wire _mem_cannot_bypass_T_6 = _mem_cannot_bypass_T_5 \| mem_ctrl_rocc; // @[RocketCore.scala:244:21, :997:{116,131}] wire mem_cannot_bypass = _mem_cannot_bypass_T_6 \| mem_ctrl_vec; // @[RocketCore.scala:244:21, :997:{131,148}] wire _data_hazard_mem_T_1 = hazard_targets_0_1 & _data_hazard_mem_T; // @[RocketCore.scala:969:42, :998:72, :1287:27] wire _data_hazard_mem_T_3 = hazard_targets_1_1 & _data_hazard_mem_T_2; // @[RocketCore.scala:970:42, :998:72, :1287:27] wire _GEN_66 = id_waddr == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :998:72] wire _data_hazard_mem_T_4; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T_4 = _GEN_66; // @[RocketCore.scala:998:72] wire _fp_data_hazard_mem_T_7; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_7 = _GEN_66; // @[RocketCore.scala:998:72, :999:92] wire _data_hazard_mem_T_5 = hazard_targets_2_1 & _data_hazard_mem_T_4; // @[RocketCore.scala:971:42, :998:72, :1287:27] wire _data_hazard_mem_T_6 = _data_hazard_mem_T_1 \| _data_hazard_mem_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_mem_T_7 = _data_hazard_mem_T_6 \| _data_hazard_mem_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_mem = mem_ctrl_wxd & _data_hazard_mem_T_7; // @[RocketCore.scala:244:21, :998:38, :1287:50] wire _fp_data_hazard_mem_T = id_ctrl_fp & mem_ctrl_wfd; // @[RocketCore.scala:244:21, :321:21, :999:39] wire _fp_data_hazard_mem_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_mem_T_1; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_mem_T_3; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_5 = id_raddr3 == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :999:92] wire _fp_data_hazard_mem_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_mem_T_5; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_mem_T_7; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_9 = _fp_data_hazard_mem_T_2 \| _fp_data_hazard_mem_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_mem_T_10 = _fp_data_hazard_mem_T_9 \| _fp_data_hazard_mem_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_mem_T_11 = _fp_data_hazard_mem_T_10 \| _fp_data_hazard_mem_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_mem = _fp_data_hazard_mem_T & _fp_data_hazard_mem_T_11; // @[RocketCore.scala:999:{39,55}, :1287:50] wire _id_mem_hazard_T = data_hazard_mem & mem_cannot_bypass; // @[RocketCore.scala:997:148, :998:38, :1000:57] wire _id_mem_hazard_T_1 = _id_mem_hazard_T \| fp_data_hazard_mem; // @[RocketCore.scala:999:55, :1000:{57,78}] wire id_mem_hazard = mem_reg_valid & _id_mem_hazard_T_1; // @[RocketCore.scala:265:36, :1000:{37,78}] wire _id_load_use_T = mem_reg_valid & data_hazard_mem; // @[RocketCore.scala:265:36, :998:38, :1001:32] assign _id_load_use_T_1 = _id_load_use_T & mem_ctrl_mem; // @[RocketCore.scala:244:21, :1001:{32,51}] assign id_load_use = _id_load_use_T_1; // @[RocketCore.scala:332:25, :1001:51] wire _id_vconfig_hazard_T_1 = mem_reg_valid & mem_reg_set_vconfig; // @[RocketCore.scala:265:36, :275:36, :1004:20] wire _id_vconfig_hazard_T_2 = _id_vconfig_hazard_T_1; // @[RocketCore.scala:1003:42, :1004:20] wire _id_vconfig_hazard_T_3 = wb_reg_valid & wb_reg_set_vconfig; // @[RocketCore.scala:288:35, :293:35, :1005:19] wire _id_vconfig_hazard_T_4 = _id_vconfig_hazard_T_2 \| _id_vconfig_hazard_T_3; // @[RocketCore.scala:1003:42, :1004:44, :1005:19] wire _GEN_67 = id_raddr1 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T = _GEN_67; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_1; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_1 = _GEN_67; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_1 = hazard_targets_0_1 & _data_hazard_wb_T; // @[RocketCore.scala:969:42, :1008:70, :1287:27] wire _GEN_68 = id_raddr2 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T_2; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T_2 = _GEN_68; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_3; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_3 = _GEN_68; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_3 = hazard_targets_1_1 & _data_hazard_wb_T_2; // @[RocketCore.scala:970:42, :1008:70, :1287:27] wire _GEN_69 = id_waddr == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T_4; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T_4 = _GEN_69; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_7; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_7 = _GEN_69; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_5 = hazard_targets_2_1 & _data_hazard_wb_T_4; // @[RocketCore.scala:971:42, :1008:70, :1287:27] wire _data_hazard_wb_T_6 = _data_hazard_wb_T_1 \| _data_hazard_wb_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_wb_T_7 = _data_hazard_wb_T_6 \| _data_hazard_wb_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_wb = wb_ctrl_wxd & _data_hazard_wb_T_7; // @[RocketCore.scala:245:20, :1008:36, :1287:50] wire _fp_data_hazard_wb_T = id_ctrl_fp & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :321:21, :1009:38] wire _fp_data_hazard_wb_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_wb_T_1; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_wb_T_3; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_5 = id_raddr3 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1009:90] wire _fp_data_hazard_wb_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_wb_T_5; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_wb_T_7; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_9 = _fp_data_hazard_wb_T_2 \| _fp_data_hazard_wb_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_wb_T_10 = _fp_data_hazard_wb_T_9 \| _fp_data_hazard_wb_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_wb_T_11 = _fp_data_hazard_wb_T_10 \| _fp_data_hazard_wb_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_wb = _fp_data_hazard_wb_T & _fp_data_hazard_wb_T_11; // @[RocketCore.scala:1009:{38,53}, :1287:50] wire _id_wb_hazard_T = data_hazard_wb & wb_set_sboard; // @[RocketCore.scala:756:69, :1008:36, :1010:54] wire _id_wb_hazard_T_1 = _id_wb_hazard_T \| fp_data_hazard_wb; // @[RocketCore.scala:1009:53, :1010:{54,71}] wire id_wb_hazard = wb_reg_valid & _id_wb_hazard_T_1; // @[RocketCore.scala:288:35, :1010:{35,71}] reg [31:0] _id_stall_fpu_r; // @[RocketCore.scala:1305:29] wire _id_stall_fpu_T = wb_dcache_miss \| wb_ctrl_vec; // @[RocketCore.scala:245:20, :596:36, :1014:36] wire _id_stall_fpu_T_1 = _id_stall_fpu_T & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :1014:{36,52}] wire _id_stall_fpu_T_2 = _id_stall_fpu_T_1 \| io_fpu_sboard_set_0; // @[RocketCore.scala:153:7, :1014:{52,67}] wire _id_stall_fpu_T_3 = _id_stall_fpu_T_2 & wb_valid; // @[RocketCore.scala:815:45, :1014:{67,89}] wire _id_stall_fpu_T_7 = _id_stall_fpu_T_3; // @[RocketCore.scala:1014:89, :1312:17] wire [31:0] _id_stall_fpu_T_5 = _id_stall_fpu_T_3 ? _id_stall_fpu_T_4 : 32'h0; // @[RocketCore.scala:1014:89, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_6 = _id_stall_fpu_r \| _id_stall_fpu_T_5; // @[RocketCore.scala:1300:60, :1305:29, :1309:49] wire _id_stall_fpu_T_8 = dmem_resp_replay & dmem_resp_fpu; // @[RocketCore.scala:766:45, :769:42, :1016:39] wire _id_stall_fpu_T_9 = _id_stall_fpu_T_8; // @[RocketCore.scala:1016:{39,57}] wire [31:0] _id_stall_fpu_T_10 = 32'h1 << io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7, :1309:58] wire [31:0] _id_stall_fpu_T_11 = _id_stall_fpu_T_9 ? _id_stall_fpu_T_10 : 32'h0; // @[RocketCore.scala:1016:57, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_12 = ~_id_stall_fpu_T_11; // @[RocketCore.scala:1301:64, :1309:49] wire [31:0] _id_stall_fpu_T_13 = _id_stall_fpu_T_6 & _id_stall_fpu_T_12; // @[RocketCore.scala:1300:60, :1301:{62,64}] wire _id_stall_fpu_T_14 = _id_stall_fpu_T_7 \| _id_stall_fpu_T_9; // @[RocketCore.scala:1016:57, :1312:17] wire [31:0] _id_stall_fpu_T_15 = 32'h1 << io_fpu_sboard_clra_0; // @[RocketCore.scala:153:7, :1309:58] wire [31:0] _id_stall_fpu_T_16 = io_fpu_sboard_clr_0 ? _id_stall_fpu_T_15 : 32'h0; // @[RocketCore.scala:153:7, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_17 = ~_id_stall_fpu_T_16; // @[RocketCore.scala:1301:64, :1309:49] wire [31:0] _id_stall_fpu_T_18 = _id_stall_fpu_T_13 & _id_stall_fpu_T_17; // @[RocketCore.scala:1301:{62,64}] wire _id_stall_fpu_T_19 = _id_stall_fpu_T_14 \| io_fpu_sboard_clr_0; // @[RocketCore.scala:153:7, :1312:17] wire [31:0] _id_stall_fpu_T_20 = _id_stall_fpu_r >> _GEN_62; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_21 = _id_stall_fpu_T_20[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_22 = io_fpu_dec_ren1_0 & _id_stall_fpu_T_21; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_23 = _id_stall_fpu_r >> _GEN_63; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_24 = _id_stall_fpu_T_23[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_25 = io_fpu_dec_ren2_0 & _id_stall_fpu_T_24; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_26 = _id_stall_fpu_r >> id_raddr3; // @[RocketCore.scala:326:72, :1302:35, :1305:29] wire _id_stall_fpu_T_27 = _id_stall_fpu_T_26[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_28 = io_fpu_dec_ren3_0 & _id_stall_fpu_T_27; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_29 = _id_stall_fpu_r >> _GEN_64; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_30 = _id_stall_fpu_T_29[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_31 = io_fpu_dec_wen_0 & _id_stall_fpu_T_30; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire _id_stall_fpu_T_32 = _id_stall_fpu_T_22 \| _id_stall_fpu_T_25; // @[RocketCore.scala:1287:{27,50}] wire _id_stall_fpu_T_33 = _id_stall_fpu_T_32 \| _id_stall_fpu_T_28; // @[RocketCore.scala:1287:{27,50}] wire id_stall_fpu = _id_stall_fpu_T_33 \| _id_stall_fpu_T_31; // @[RocketCore.scala:1287:{27,50}] reg dcache_blocked_blocked; // @[RocketCore.scala:1024:22] wire _dcache_blocked_blocked_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45, :1025:16] wire _dcache_blocked_blocked_T_1 = _dcache_blocked_blocked_T; // @[RocketCore.scala:1025:{16,35}] wire _dcache_blocked_blocked_T_2 = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63] wire _dcache_blocked_blocked_T_3 = _dcache_blocked_blocked_T_1 & _dcache_blocked_blocked_T_2; // @[RocketCore.scala:1025:{35,60,63}] wire _dcache_blocked_blocked_T_4 = dcache_blocked_blocked \| io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :1024:22, :1025:95] wire _dcache_blocked_blocked_T_5 = _dcache_blocked_blocked_T_4 \| io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1025:{95,116}] wire _dcache_blocked_blocked_T_6 = _dcache_blocked_blocked_T_3 & _dcache_blocked_blocked_T_5; // @[RocketCore.scala:1025:{60,83,116}] wire _dcache_blocked_T = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63, :1026:16] wire dcache_blocked = dcache_blocked_blocked & _dcache_blocked_T; // @[RocketCore.scala:1024:22, :1026:{13,16}] reg rocc_blocked; // @[RocketCore.scala:1028:25] wire _rocc_blocked_T = ~wb_xcpt; // @[RocketCore.scala:815:48, :1029:19, :1278:14] wire _rocc_blocked_T_2 = _rocc_blocked_T; // @[RocketCore.scala:1029:{19,28}] wire _rocc_blocked_T_3 = io_rocc_cmd_valid \| rocc_blocked; // @[RocketCore.scala:153:7, :1028:25, :1029:72] wire _rocc_blocked_T_4 = _rocc_blocked_T_2 & _rocc_blocked_T_3; // @[RocketCore.scala:1029:{28,50,72}] wire _ctrl_stalld_T = id_ex_hazard \| id_mem_hazard; // @[RocketCore.scala:991:35, :1000:37, :1032:18] wire _ctrl_stalld_T_1 = _ctrl_stalld_T \| id_wb_hazard; // @[RocketCore.scala:1010:35, :1032:{18,35}] wire _ctrl_stalld_T_2 = _ctrl_stalld_T_1 \| id_sboard_hazard; // @[RocketCore.scala:1032:{35,51}, :1287:50] wire _ctrl_stalld_T_3 = _ctrl_stalld_T_2; // @[RocketCore.scala:1032:{51,71}] wire _ctrl_stalld_T_4 = ex_reg_valid \| mem_reg_valid; // @[RocketCore.scala:248:35, :265:36, :1034:40] wire _ctrl_stalld_T_5 = _ctrl_stalld_T_4 \| wb_reg_valid; // @[RocketCore.scala:288:35, :1034:{40,57}] wire _ctrl_stalld_T_6 = _csr_io_singleStep & _ctrl_stalld_T_5; // @[RocketCore.scala:341:19, :1034:{23,57}] wire _ctrl_stalld_T_7 = _ctrl_stalld_T_3 \| _ctrl_stalld_T_6; // @[RocketCore.scala:1032:71, :1033:23, :1034:23] wire _ctrl_stalld_T_8 = id_csr_en & _csr_io_decode_0_fp_csr; // @[package.scala:81:59] wire _ctrl_stalld_T_9 = ~io_fpu_fcsr_rdy_0; // @[RocketCore.scala:153:7, :1035:45] wire _ctrl_stalld_T_10 = _ctrl_stalld_T_8 & _ctrl_stalld_T_9; // @[RocketCore.scala:1035:{15,42,45}] wire _ctrl_stalld_T_11 = _ctrl_stalld_T_7 \| _ctrl_stalld_T_10; // @[RocketCore.scala:1033:23, :1034:74, :1035:42] wire _ctrl_stalld_T_14 = _ctrl_stalld_T_11; // @[RocketCore.scala:1034:74, :1035:62] wire _ctrl_stalld_T_15 = id_ctrl_fp & id_stall_fpu; // @[RocketCore.scala:321:21, :1037:16, :1287:50] wire _ctrl_stalld_T_16 = _ctrl_stalld_T_14 \| _ctrl_stalld_T_15; // @[RocketCore.scala:1035:62, :1036:61, :1037:16] wire _ctrl_stalld_T_17 = id_ctrl_mem & dcache_blocked; // @[RocketCore.scala:321:21, :1026:13, :1038:17] wire _ctrl_stalld_T_18 = _ctrl_stalld_T_16 \| _ctrl_stalld_T_17; // @[RocketCore.scala:1036:61, :1037:32, :1038:17] wire _ctrl_stalld_T_19 = id_ctrl_rocc & rocc_blocked; // @[RocketCore.scala:321:21, :1028:25, :1039:18] wire _ctrl_stalld_T_20 = _ctrl_stalld_T_18 \| _ctrl_stalld_T_19; // @[RocketCore.scala:1037:32, :1038:35, :1039:18] wire _ctrl_stalld_T_21 = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26, :1040:65] wire _ctrl_stalld_T_22 = _div_io_resp_valid & _ctrl_stalld_T_21; // @[RocketCore.scala:511:19, :1040:{62,65}] wire _ctrl_stalld_T_23 = _div_io_req_ready \| _ctrl_stalld_T_22; // @[RocketCore.scala:511:19, :1040:{40,62}] wire _ctrl_stalld_T_24 = ~_ctrl_stalld_T_23; // @[RocketCore.scala:1040:{21,40}] wire _ctrl_stalld_T_25 = _ctrl_stalld_T_24 \| _div_io_req_valid_T; // @[RocketCore.scala:512:36, :1040:{21,75}] wire _ctrl_stalld_T_26 = id_ctrl_div & _ctrl_stalld_T_25; // @[RocketCore.scala:321:21, :1040:{17,75}] wire _ctrl_stalld_T_27 = _ctrl_stalld_T_20 \| _ctrl_stalld_T_26; // @[RocketCore.scala:1038:35, :1039:34, :1040:17] wire _ctrl_stalld_T_29 = _ctrl_stalld_T_27; // @[RocketCore.scala:1039:34, :1040:96] wire _ctrl_stalld_T_30 = _ctrl_stalld_T_29 \| id_do_fence; // @[RocketCore.scala:410:32, :1040:96, :1041:15] wire _ctrl_stalld_T_31 = _ctrl_stalld_T_30 \| _csr_io_csr_stall; // @[RocketCore.scala:341:19, :1041:15, :1042:17] wire _ctrl_stalld_T_32 = _ctrl_stalld_T_31 \| id_reg_pause; // @[RocketCore.scala:161:25, :1042:17, :1043:22] wire ctrl_stalld = _ctrl_stalld_T_32; // @[RocketCore.scala:1043:22, :1044:18] wire _ctrl_killd_T = ~_ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :1046:17] wire _ctrl_killd_T_1 = _ctrl_killd_T \| _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :1046:{17,40}] wire _ctrl_killd_T_2 = _ctrl_killd_T_1 \| take_pc_mem_wb; // @[RocketCore.scala:307:35, :1046:{40,71}] wire _ctrl_killd_T_3 = _ctrl_killd_T_2 \| ctrl_stalld; // @[RocketCore.scala:1044:18, :1046:{71,89}] assign _ctrl_killd_T_4 = _ctrl_killd_T_3 \| _csr_io_interrupt; // @[RocketCore.scala:341:19, :1046:{89,104}] assign ctrl_killd = _ctrl_killd_T_4; // @[RocketCore.scala:338:24, :1046:104] assign _io_imem_req_bits_speculative_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1049:35] assign io_imem_req_bits_speculative_0 = _io_imem_req_bits_speculative_T; // @[RocketCore.scala:153:7, :1049:35] wire _io_imem_req_bits_pc_T = wb_xcpt \| _csr_io_eret; // @[RocketCore.scala:341:19, :1051:17, :1278:14] wire [39:0] _io_imem_req_bits_pc_T_1 = replay_wb ? wb_reg_pc : mem_npc; // @[RocketCore.scala:295:22, :619:139, :761:71, :1052:8] assign _io_imem_req_bits_pc_T_2 = _io_imem_req_bits_pc_T ? _csr_io_evec : _io_imem_req_bits_pc_T_1; // @[RocketCore.scala:341:19, :1051:{8,17}, :1052:8] assign io_imem_req_bits_pc_0 = _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:153:7, :1051:8] wire _io_imem_flush_icache_T = wb_reg_valid & wb_ctrl_fence_i; // @[RocketCore.scala:245:20, :288:35, :1054:40] wire _io_imem_flush_icache_T_1 = ~io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1054:62] assign _io_imem_flush_icache_T_2 = _io_imem_flush_icache_T & _io_imem_flush_icache_T_1; // @[RocketCore.scala:1054:{40,59,62}] assign io_imem_flush_icache_0 = _io_imem_flush_icache_T_2; // @[RocketCore.scala:153:7, :1054:59] wire _io_imem_might_request_imem_might_request_reg_T = ex_pc_valid \| mem_pc_valid; // @[RocketCore.scala:595:51, :614:54, :1056:43] wire _io_imem_might_request_imem_might_request_reg_T_1 = io_ptw_customCSRs_csrs_0_value_0[1]; // @[CustomCSRs.scala:44:61] wire _io_imem_might_request_imem_might_request_reg_T_2 = _io_imem_might_request_imem_might_request_reg_T \| _io_imem_might_request_imem_might_request_reg_T_1; // @[CustomCSRs.scala:44:61] wire _io_imem_might_request_imem_might_request_reg_T_3 = _io_imem_might_request_imem_might_request_reg_T_2; // @[RocketCore.scala:1056:{59,103}] wire _io_imem_progress_T = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47] wire _io_imem_progress_T_1 = wb_reg_valid & _io_imem_progress_T; // @[RocketCore.scala:288:35, :1059:{44,47}] reg io_imem_progress_REG; // @[RocketCore.scala:1059:30] assign io_imem_progress_0 = io_imem_progress_REG; // @[RocketCore.scala:153:7, :1059:30] assign _io_imem_sfence_valid_T = wb_reg_valid & wb_reg_sfence; // @[RocketCore.scala:288:35, :294:26, :1060:40] assign io_imem_sfence_valid_0 = _io_imem_sfence_valid_T; // @[RocketCore.scala:153:7, :1060:40] assign _io_imem_sfence_bits_rs1_T = wb_reg_mem_size[0]; // @[RocketCore.scala:296:28, :1061:45] assign io_imem_sfence_bits_rs1_0 = _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:153:7, :1061:45] assign _io_imem_sfence_bits_rs2_T = wb_reg_mem_size[1]; // @[RocketCore.scala:296:28, :1062:45] assign io_imem_sfence_bits_rs2_0 = _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:153:7, :1062:45] assign io_imem_sfence_bits_asid_0 = wb_reg_rs2[0]; // @[RocketCore.scala:153:7, :303:23, :1064:28] wire _ibuf_io_inst_0_ready_T = ~ctrl_stalld; // @[RocketCore.scala:1044:18, :1069:28] wire _io_imem_btb_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1071:48] wire _io_imem_btb_update_valid_T_1 = mem_reg_valid & _io_imem_btb_update_valid_T; // @[RocketCore.scala:265:36, :1071:{45,48}] wire _io_imem_btb_update_valid_T_2 = _io_imem_btb_update_valid_T_1 & mem_wrong_npc; // @[RocketCore.scala:621:8, :1071:{45,60}] wire _io_imem_btb_update_valid_T_3 = ~mem_cfi; // @[RocketCore.scala:625:50, :1071:81] wire _io_imem_btb_update_valid_T_4 = _io_imem_btb_update_valid_T_3 \| mem_cfi_taken; // @[RocketCore.scala:626:74, :1071:{81,90}] assign _io_imem_btb_update_valid_T_5 = _io_imem_btb_update_valid_T_2 & _io_imem_btb_update_valid_T_4; // @[RocketCore.scala:1071:{60,77,90}] assign io_imem_btb_update_valid_0 = _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:153:7, :1071:77] wire _GEN_70 = mem_ctrl_jal \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :1074:23] wire _io_imem_btb_update_bits_cfiType_T; // @[RocketCore.scala:1074:23] assign _io_imem_btb_update_bits_cfiType_T = _GEN_70; // @[RocketCore.scala:1074:23] wire _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:22] assign _io_imem_btb_update_bits_cfiType_T_8 = _GEN_70; // @[RocketCore.scala:1074:23, :1076:22] wire _io_imem_btb_update_bits_cfiType_T_1 = mem_waddr[0]; // @[RocketCore.scala:454:38, :1074:53] wire _io_imem_btb_update_bits_cfiType_T_2 = _io_imem_btb_update_bits_cfiType_T & _io_imem_btb_update_bits_cfiType_T_1; // @[RocketCore.scala:1074:{23,41,53}] wire [4:0] _io_imem_btb_update_bits_cfiType_T_3 = mem_reg_inst[19:15]; // @[RocketCore.scala:278:25, :1075:39] wire [4:0] _io_imem_btb_update_bits_cfiType_T_4 = _io_imem_btb_update_bits_cfiType_T_3; // @[RocketCore.scala:1075:{39,47}] wire [4:0] _io_imem_btb_update_bits_cfiType_T_5 = _io_imem_btb_update_bits_cfiType_T_4 & 5'h1B; // @[RocketCore.scala:1075:{47,64}] wire _io_imem_btb_update_bits_cfiType_T_6 = _io_imem_btb_update_bits_cfiType_T_5 == 5'h1; // @[RocketCore.scala:1075:64] wire _io_imem_btb_update_bits_cfiType_T_7 = mem_ctrl_jalr & _io_imem_btb_update_bits_cfiType_T_6; // @[RocketCore.scala:244:21, :1075:{23,64}] wire _io_imem_btb_update_bits_cfiType_T_9 = _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:{8,22}] wire [1:0] _io_imem_btb_update_bits_cfiType_T_10 = _io_imem_btb_update_bits_cfiType_T_7 ? 2'h3 : {1'h0, _io_imem_btb_update_bits_cfiType_T_9}; // @[RocketCore.scala:1075:{8,23}, :1076:8] assign _io_imem_btb_update_bits_cfiType_T_11 = _io_imem_btb_update_bits_cfiType_T_2 ? 2'h2 : _io_imem_btb_update_bits_cfiType_T_10; // @[RocketCore.scala:1074:{8,41}, :1075:8] assign io_imem_btb_update_bits_cfiType_0 = _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:153:7, :1074:8] assign io_imem_btb_update_bits_target_0 = io_imem_req_bits_pc_0[38:0]; // @[RocketCore.scala:153:7, :1078:34] wire [1:0] _io_imem_btb_update_bits_br_pc_T = {~mem_reg_rvc, 1'h0}; // @[RocketCore.scala:266:36, :1079:74] wire [40:0] _io_imem_btb_update_bits_br_pc_T_1 = {1'h0, mem_reg_pc} + {39'h0, _io_imem_btb_update_bits_br_pc_T}; // @[RocketCore.scala:277:23, :1079:{69,74}] wire [39:0] _io_imem_btb_update_bits_br_pc_T_2 = _io_imem_btb_update_bits_br_pc_T_1[39:0]; // @[RocketCore.scala:1079:69] assign io_imem_btb_update_bits_br_pc_0 = _io_imem_btb_update_bits_br_pc_T_2[38:0]; // @[RocketCore.scala:153:7, :1079:{33,69}] wire [38:0] _io_imem_btb_update_bits_pc_T = ~io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7, :1080:35] wire [38:0] _io_imem_btb_update_bits_pc_T_1 = {_io_imem_btb_update_bits_pc_T[38:2], 2'h3}; // @[RocketCore.scala:1080:{35,66}] assign _io_imem_btb_update_bits_pc_T_2 = ~_io_imem_btb_update_bits_pc_T_1; // @[RocketCore.scala:1080:{33,66}] assign io_imem_btb_update_bits_pc_0 = _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:153:7, :1080:33] wire _io_imem_bht_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1084:48] assign _io_imem_bht_update_valid_T_1 = mem_reg_valid & _io_imem_bht_update_valid_T; // @[RocketCore.scala:265:36, :1084:{45,48}] assign io_imem_bht_update_valid_0 = _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:153:7, :1084:45] wire _io_fpu_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :1094:19] assign _io_fpu_valid_T_1 = _io_fpu_valid_T & id_ctrl_fp; // @[RocketCore.scala:321:21, :1094:{19,31}] assign io_fpu_valid_0 = _io_fpu_valid_T_1; // @[RocketCore.scala:153:7, :1094:31] assign _io_fpu_ll_resp_val_T = dmem_resp_valid & dmem_resp_fpu; // @[RocketCore.scala:766:45, :768:44, :1099:41] assign io_fpu_ll_resp_val_0 = _io_fpu_ll_resp_val_T; // @[RocketCore.scala:153:7, :1099:41] assign io_fpu_ll_resp_type_0 = {1'h0, io_dmem_resp_bits_size_0}; // @[RocketCore.scala:153:7, :1101:23] assign _io_fpu_keep_clock_enabled_T = io_ptw_customCSRs_csrs_0_value_0[2]; // @[CustomCSRs.scala:45:59] assign io_fpu_keep_clock_enabled_0 = _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59] assign _io_dmem_req_valid_T = ex_reg_valid & ex_ctrl_mem; // @[RocketCore.scala:243:20, :248:35, :1130:41] assign io_dmem_req_valid_0 = _io_dmem_req_valid_T; // @[RocketCore.scala:153:7, :1130:41] wire [5:0] ex_dcache_tag = {ex_waddr, ex_ctrl_fp}; // @[RocketCore.scala:243:20, :453:36, :1131:26] assign io_dmem_req_bits_tag_0 = {1'h0, ex_dcache_tag}; // @[RocketCore.scala:153:7, :1131:26, :1133:25] wire _io_dmem_req_bits_signed_T_1 = ex_reg_inst[14]; // @[RocketCore.scala:259:24, :1136:75] wire _io_dmem_req_bits_signed_T_2 = _io_dmem_req_bits_signed_T_1; // @[RocketCore.scala:1136:{34,75}] assign _io_dmem_req_bits_signed_T_3 = ~_io_dmem_req_bits_signed_T_2; // @[RocketCore.scala:1136:{30,34}] assign io_dmem_req_bits_signed_0 = _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:153:7, :1136:30] wire [24:0] _io_dmem_req_bits_addr_a_T = ex_rs_0[63:39]; // @[RocketCore.scala:469:14, :1293:17] wire [24:0] io_dmem_req_bits_addr_a = _io_dmem_req_bits_addr_a_T; // @[RocketCore.scala:1293:{17,23}] wire _io_dmem_req_bits_addr_msb_T = io_dmem_req_bits_addr_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _io_dmem_req_bits_addr_msb_T_1 = &io_dmem_req_bits_addr_a; // @[RocketCore.scala:1293:23, :1294:34] wire _io_dmem_req_bits_addr_msb_T_2 = _io_dmem_req_bits_addr_msb_T \| _io_dmem_req_bits_addr_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _io_dmem_req_bits_addr_msb_T_3 = _alu_io_adder_out[39]; // @[RocketCore.scala:504:19, :1294:46] wire _io_dmem_req_bits_addr_msb_T_4 = _alu_io_adder_out[38]; // @[RocketCore.scala:504:19, :1294:54] wire _io_dmem_req_bits_addr_msb_T_5 = ~_io_dmem_req_bits_addr_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire io_dmem_req_bits_addr_msb = _io_dmem_req_bits_addr_msb_T_2 ? _io_dmem_req_bits_addr_msb_T_3 : _io_dmem_req_bits_addr_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] wire [38:0] _io_dmem_req_bits_addr_T = _alu_io_adder_out[38:0]; // @[RocketCore.scala:504:19, :1295:16] assign _io_dmem_req_bits_addr_T_1 = {io_dmem_req_bits_addr_msb, _io_dmem_req_bits_addr_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}] assign io_dmem_req_bits_addr_0 = _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:153:7, :1295:8] assign io_dmem_req_bits_dprv_0 = _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:153:7, :1140:31] assign io_dmem_req_bits_dv_0 = _io_dmem_req_bits_dv_T; // @[RocketCore.scala:153:7, :1141:37] wire _io_dmem_req_bits_no_resp_T_4 = _io_dmem_req_bits_no_resp_T \| _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_5 = _io_dmem_req_bits_no_resp_T_4 \| _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_6 = _io_dmem_req_bits_no_resp_T_5 \| _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_11 = _io_dmem_req_bits_no_resp_T_7 \| _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_12 = _io_dmem_req_bits_no_resp_T_11 \| _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_13 = _io_dmem_req_bits_no_resp_T_12 \| _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_19 = _io_dmem_req_bits_no_resp_T_14 \| _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_20 = _io_dmem_req_bits_no_resp_T_19 \| _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_21 = _io_dmem_req_bits_no_resp_T_20 \| _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_22 = _io_dmem_req_bits_no_resp_T_21 \| _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_23 = _io_dmem_req_bits_no_resp_T_13 \| _io_dmem_req_bits_no_resp_T_22; // @[package.scala:81:59] wire _io_dmem_req_bits_no_resp_T_24 = _io_dmem_req_bits_no_resp_T_6 \| _io_dmem_req_bits_no_resp_T_23; // @[package.scala:81:59] wire _io_dmem_req_bits_no_resp_T_25 = ~_io_dmem_req_bits_no_resp_T_24; // @[RocketCore.scala:1142:31] wire _io_dmem_req_bits_no_resp_T_26 = ~ex_ctrl_fp; // @[RocketCore.scala:243:20, :1142:60] wire _io_dmem_req_bits_no_resp_T_27 = ex_waddr == 5'h0; // @[RocketCore.scala:453:36, :1142:84] wire _io_dmem_req_bits_no_resp_T_28 = _io_dmem_req_bits_no_resp_T_26 & _io_dmem_req_bits_no_resp_T_27; // @[RocketCore.scala:1142:{60,72,84}] assign _io_dmem_req_bits_no_resp_T_29 = _io_dmem_req_bits_no_resp_T_25 \| _io_dmem_req_bits_no_resp_T_28; // @[RocketCore.scala:1142:{31,56,72}] assign io_dmem_req_bits_no_resp_0 = _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:153:7, :1142:56] assign _io_dmem_s1_data_data_T = mem_ctrl_fp ? io_fpu_store_data_0 : mem_reg_rs2; // @[RocketCore.scala:153:7, :244:21, :283:24, :1148:63] assign io_dmem_s1_data_data_0 = _io_dmem_s1_data_data_T; // @[RocketCore.scala:153:7, :1148:63] wire _io_dmem_s1_kill_T = killm_common \| mem_ldst_xcpt; // @[RocketCore.scala:700:68, :1151:35, :1278:14] wire _io_dmem_s1_kill_T_1 = _io_dmem_s1_kill_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :1151:{35,52}] assign _io_dmem_s1_kill_T_2 = _io_dmem_s1_kill_T_1; // @[RocketCore.scala:1151:{52,68}] assign io_dmem_s1_kill_0 = _io_dmem_s1_kill_T_2; // @[RocketCore.scala:153:7, :1151:68] wire _io_dmem_keep_clock_enabled_T = _ibuf_io_inst_0_valid & id_ctrl_mem; // @[RocketCore.scala:311:20, :321:21, :1154:55] wire _io_dmem_keep_clock_enabled_T_1 = ~_csr_io_csr_stall; // @[RocketCore.scala:341:19, :1154:73] assign _io_dmem_keep_clock_enabled_T_2 = _io_dmem_keep_clock_enabled_T & _io_dmem_keep_clock_enabled_T_1; // @[RocketCore.scala:1154:{55,70,73}] assign io_dmem_keep_clock_enabled_0 = _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:153:7, :1154:70] wire _io_rocc_cmd_valid_T_1 = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47, :1156:56] assign _io_rocc_cmd_valid_T_2 = _io_rocc_cmd_valid_T & _io_rocc_cmd_valid_T_1; // @[RocketCore.scala:1156:{37,53,56}] assign io_rocc_cmd_valid = _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:153:7, :1156:53] wire [6:0] _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_funct = _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rs2 = _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rs1 = _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xd = _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xs1 = _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xs2 = _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rd = _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:153:7, :1159:48] wire [6:0] _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_opcode = _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:153:7, :1159:48] assign _io_rocc_cmd_bits_inst_T = _io_rocc_cmd_bits_inst_WIRE_1[6:0]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_opcode = _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_1 = _io_rocc_cmd_bits_inst_WIRE_1[11:7]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rd = _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_2 = _io_rocc_cmd_bits_inst_WIRE_1[12]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xs2 = _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_3 = _io_rocc_cmd_bits_inst_WIRE_1[13]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xs1 = _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_4 = _io_rocc_cmd_bits_inst_WIRE_1[14]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xd = _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_5 = _io_rocc_cmd_bits_inst_WIRE_1[19:15]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rs1 = _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_6 = _io_rocc_cmd_bits_inst_WIRE_1[24:20]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rs2 = _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_7 = _io_rocc_cmd_bits_inst_WIRE_1[31:25]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_funct = _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48] wire [4:0] _unpause_T = _csr_io_time[4:0]; // @[RocketCore.scala:341:19, :1164:28] wire _unpause_T_1 = _unpause_T == 5'h0; // @[RocketCore.scala:1164:{28,62}] wire _unpause_T_2 = _unpause_T_1 \| _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19, :1164:{62,70}] wire _unpause_T_3 = _unpause_T_2 \| io_dmem_perf_release_0; // @[RocketCore.scala:153:7, :1164:{70,94}] wire unpause = _unpause_T_3 \| take_pc_mem_wb; // @[RocketCore.scala:307:35, :1164:{94,118}] reg icache_blocked_REG; // @[RocketCore.scala:1183:55] wire _icache_blocked_T = io_imem_resp_valid_0 \| icache_blocked_REG; // @[RocketCore.scala:153:7, :1183:{45,55}] wire icache_blocked = ~_icache_blocked_T; // @[RocketCore.scala:1183:{24,45}] wire _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1192:52] wire [63:0] _coreMonitorBundle_pc_T_3; // @[package.scala:132:15] wire _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1194:37] wire [4:0] _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1198:42] wire [4:0] _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1200:42] wire coreMonitorBundle_excpt; // @[RocketCore.scala:1186:31] wire [2:0] coreMonitorBundle_priv_mode; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_hartid; // @[RocketCore.scala:1186:31] wire [31:0] coreMonitorBundle_timer; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_valid; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_pc; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_wrenx; // @[RocketCore.scala:1186:31] wire [4:0] coreMonitorBundle_rd0src; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_rd0val; // @[RocketCore.scala:1186:31] wire [4:0] coreMonitorBundle_rd1src; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_rd1val; // @[RocketCore.scala:1186:31] wire [31:0] coreMonitorBundle_inst; // @[RocketCore.scala:1186:31] wire [63:0] _GEN_71 = {63'h0, io_hartid_0}; // @[RocketCore.scala:153:7, :1190:28] assign coreMonitorBundle_hartid = _GEN_71; // @[RocketCore.scala:1186:31, :1190:28] wire [63:0] xrfWriteBundle_hartid; // @[RocketCore.scala:1249:28] assign xrfWriteBundle_hartid = _GEN_71; // @[RocketCore.scala:1190:28, :1249:28] assign coreMonitorBundle_timer = _coreMonitorBundle_timer_T; // @[RocketCore.scala:1186:31, :1191:41] wire _coreMonitorBundle_valid_T = ~_csr_io_trace_0_exception; // @[RocketCore.scala:341:19, :1192:55] assign _coreMonitorBundle_valid_T_1 = _csr_io_trace_0_valid & _coreMonitorBundle_valid_T; // @[RocketCore.scala:341:19, :1192:{52,55}] assign coreMonitorBundle_valid = _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1186:31, :1192:52] wire [39:0] _coreMonitorBundle_pc_T; // @[RocketCore.scala:1193:48] wire _coreMonitorBundle_pc_T_1 = _coreMonitorBundle_pc_T[39]; // @[package.scala:132:38] wire [23:0] _coreMonitorBundle_pc_T_2 = {24{_coreMonitorBundle_pc_T_1}}; // @[package.scala:132:{20,38}] assign _coreMonitorBundle_pc_T_3 = {_coreMonitorBundle_pc_T_2, _coreMonitorBundle_pc_T}; // @[package.scala:132:{15,20}] assign coreMonitorBundle_pc = _coreMonitorBundle_pc_T_3; // @[package.scala:132:15] wire _coreMonitorBundle_wrenx_T = ~wb_set_sboard; // @[RocketCore.scala:756:69, :1194:40] assign _coreMonitorBundle_wrenx_T_1 = wb_wen & _coreMonitorBundle_wrenx_T; // @[RocketCore.scala:816:25, :1194:{37,40}] assign coreMonitorBundle_wrenx = _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1186:31, :1194:37] assign _coreMonitorBundle_rd0src_T = wb_reg_inst[19:15]; // @[RocketCore.scala:300:24, :1198:42] assign coreMonitorBundle_rd0src = _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1186:31, :1198:42] reg [63:0] coreMonitorBundle_rd0val_REG; // @[RocketCore.scala:1199:46] reg [63:0] coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1199:38] assign coreMonitorBundle_rd0val = coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1186:31, :1199:38] assign _coreMonitorBundle_rd1src_T = wb_reg_inst[24:20]; // @[RocketCore.scala:300:24, :1200:42] assign coreMonitorBundle_rd1src = _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1186:31, :1200:42] reg [63:0] coreMonitorBundle_rd1val_REG; // @[RocketCore.scala:1201:46] reg [63:0] coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1201:38] assign coreMonitorBundle_rd1val = coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1186:31, :1201:38]
Generate the Verilog code corresponding to the following Chisel files. File RouteComputer.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.experimental.decode.{TruthTable, decoder} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import freechips.rocketchip.rocket.DecodeLogic import constellation.channel._ import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo} import constellation.noc.{HasNoCParams} class RouteComputerReq(implicit val p: Parameters) extends Bundle with HasNoCParams { val src_virt_id = UInt(virtualChannelBits.W) val flow = new FlowRoutingBundle } class RouteComputerResp( val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } class RouteComputer( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams with HasNoCParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new RouteComputerReq)) }) val resp = MixedVec(allInParams.map { u => Output(new RouteComputerResp(outParams, egressParams)) }) }) (io.req zip io.resp).zipWithIndex.map { case ((req, resp), i) => req.ready := true.B if (outParams.size == 0) { assert(!req.valid) resp.vc_sel := DontCare } else { def toUInt(t: (Int, FlowRoutingInfo)): UInt = { val l2 = (BigInt(t._1) << req.bits.flow.vnet_id .getWidth) \| t._2.vNetId val l3 = ( l2 << req.bits.flow.ingress_node .getWidth) \| t._2.ingressNode val l4 = ( l3 << req.bits.flow.ingress_node_id.getWidth) \| t._2.ingressNodeId val l5 = ( l4 << req.bits.flow.egress_node .getWidth) \| t._2.egressNode val l6 = ( l5 << req.bits.flow.egress_node_id .getWidth) \| t._2.egressNodeId l6.U(req.bits.getWidth.W) } val flow = req.bits.flow val table = allInParams(i).possibleFlows.toSeq.distinct.map { pI => allInParams(i).channelRoutingInfos.map { cI => var row: String = "b" (0 until nOutputs).foreach { o => (0 until outParams(o).nVirtualChannels).foreach { outVId => row = row + (if (routingRelation(cI, outParams(o).channelRoutingInfos(outVId), pI)) "1" else "0") } } ((cI.vc, pI), row) } }.flatten val addr = req.bits.asUInt val width = outParams.map(_.nVirtualChannels).reduce(_+_) val decoded = if (table.size > 0) { val truthTable = TruthTable( table.map { e => (BitPat(toUInt(e._1)), BitPat(e._2)) }, BitPat("b" + "?" * width) ) Reverse(decoder(addr, truthTable)) } else { 0.U(width.W) } var idx = 0 (0 until nAllOutputs).foreach { o => if (o < nOutputs) { (0 until outParams(o).nVirtualChannels).foreach { outVId => resp.vc_sel(o)(outVId) := decoded(idx) idx += 1 } } else { resp.vc_sel(o)(0) := false.B } } } } }	module RouteComputer_19( // @[RouteComputer.scala:29:7] input [2:0] io_req_4_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_4_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_4_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_4_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_4_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_4_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_3_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_3_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_3_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_3_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_3, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_4, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_5, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_6, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_7, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_3, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_4, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_5, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_6, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_7, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_3, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_4, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_7, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_3, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_4, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_5, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_6, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_4_7, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_3, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_4, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_5, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_6, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_7, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_3, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_4, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_7, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_3, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_4_7, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_3, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_7, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_7, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_4_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_4_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_4_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_4_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_4_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_4_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_4_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_4_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_7 // @[RouteComputer.scala:40:14] ); wire [16:0] decoded_invInputs = ~{io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [16:0] _decoded_andMatrixOutputs_T = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_1 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_2 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_4 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_5 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_7 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_8 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_9 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_11 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_12 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_14 = {decoded_invInputs[0], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_16 = {decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_17 = {decoded_invInputs[0], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_18 = {decoded_invInputs[0], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_19 = {decoded_invInputs[0], decoded_invInputs[3], decoded_invInputs[4], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_21 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_22 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_23 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_25 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_26 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_28 = {decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_30 = {decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_31 = {decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_32 = {decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_33 = {decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[3], decoded_invInputs[4], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] decoded_invInputs_1 = ~{io_req_1_bits_flow_vnet_id, io_req_1_bits_flow_ingress_node, io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [14:0] _decoded_andMatrixOutputs_T_36 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[0], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_38 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[0], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_40 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_41 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_42 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_43 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_47 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_48 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_49 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_50 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_51 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_52 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_53 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_55 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_59 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_61 = {io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_62 = {io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_63 = {io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_64 = {io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_65 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_66 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_67 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_68 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_69 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_70 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_71 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_73 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_74 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_75 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_77 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_78 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_79 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_81 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[0], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_82 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[0], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_85 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_86 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_87 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_88 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_89 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[1], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_90 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[1], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_91 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[1], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_92 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[1], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] decoded_orMatrixOutputs_hi_hi_38 = {&_decoded_andMatrixOutputs_T_36, &_decoded_andMatrixOutputs_T_38}; // @[pla.scala:98:{53,70}, :114:19] wire [16:0] decoded_invInputs_2 = ~{io_req_2_bits_flow_vnet_id, io_req_2_bits_flow_ingress_node, io_req_2_bits_flow_ingress_node_id, io_req_2_bits_flow_egress_node, io_req_2_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [14:0] _decoded_andMatrixOutputs_T_94 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[0], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _decoded_andMatrixOutputs_T_96 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[0], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_97 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_98 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_99 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_100 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_101 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_102 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_103 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_104 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_105 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_109 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_111 = {io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_112 = {io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_113 = {io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_114 = {io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_115 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_116 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_117 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_118 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_119 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_120 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_121 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_123 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_124 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_125 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_127 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[0], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_128 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[0], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_132 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_133 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_134 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_135 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_136 = {decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_137 = {decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_138 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_139 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_140 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_141 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_142 = {decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_143 = {decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] decoded_orMatrixOutputs_hi_hi_58 = {&_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_96}; // @[pla.scala:98:{53,70}, :114:19] wire [16:0] decoded_invInputs_3 = ~{io_req_3_bits_flow_vnet_id, io_req_3_bits_flow_ingress_node, io_req_3_bits_flow_ingress_node_id, io_req_3_bits_flow_egress_node, io_req_3_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [14:0] _decoded_andMatrixOutputs_T_144 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_146 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_148 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_149 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_150 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_159 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_160 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_161 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_162 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_163 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_165 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_166 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_168 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_170 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_171 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_173 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_175 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_177 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_178 = {io_req_3_bits_flow_egress_node_id[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_179 = {io_req_3_bits_flow_egress_node_id[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_186 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_187 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_188 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_189 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_190 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_192 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_193 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_195 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_197 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_198 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_200 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_201 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_202 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_203 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_204 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_205 = {decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_206 = {decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_207 = {decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_208 = {decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_210 = {decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_211 = {decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_212 = {decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_214 = {decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_216 = {decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_217 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_218 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_219 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[1], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_220 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[1], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] decoded_invInputs_4 = ~{io_req_4_bits_flow_vnet_id, io_req_4_bits_flow_ingress_node, io_req_4_bits_flow_ingress_node_id, io_req_4_bits_flow_egress_node, io_req_4_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [2:0] _decoded_andMatrixOutputs_T_221 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], io_req_4_bits_flow_egress_node[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_223 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_224 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_230 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_231 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_232 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[2], decoded_invInputs_4[3], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_233 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_235 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_236 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_237 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_239 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_241 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_242 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_244 = {io_req_4_bits_flow_egress_node_id[0], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_245 = {io_req_4_bits_flow_egress_node_id[0], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_251 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_252 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_253 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[2], decoded_invInputs_4[3], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_254 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_256 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_257 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_258 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_260 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_261 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_262 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_263 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_264 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_265 = {decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_267 = {decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_268 = {decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_269 = {decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_270 = {decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_272 = {decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_273 = {decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_275 = {decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_276 = {decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_277 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_278 = {decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_279 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_280 = {decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[1], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_281 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[1], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_282 = {decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[1], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_283 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[1], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] assign io_resp_4_vc_sel_3_0 = &{decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], decoded_invInputs_4[2], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_4_vc_sel_3_1 = \|{&_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_224, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_231, &_decoded_andMatrixOutputs_T_235, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_252, &_decoded_andMatrixOutputs_T_256}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_3_2 = \|{&_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_224, &_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_231, &_decoded_andMatrixOutputs_T_235, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_252, &_decoded_andMatrixOutputs_T_256, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_264}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_3_3 = \|{&_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_224, &_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_231, &_decoded_andMatrixOutputs_T_235, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_245, &{decoded_invInputs_4[0], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_252, &_decoded_andMatrixOutputs_T_256, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_267}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_3_4 = \|{&_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_224, &_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_231, &_decoded_andMatrixOutputs_T_235, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_245, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_252, &_decoded_andMatrixOutputs_T_256, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_267, &{decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}, &{decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_3_5 = \|{&_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_224, &_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_231, &_decoded_andMatrixOutputs_T_235, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_245, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_252, &_decoded_andMatrixOutputs_T_256, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_267, &_decoded_andMatrixOutputs_T_277, &_decoded_andMatrixOutputs_T_279, &_decoded_andMatrixOutputs_T_281, &_decoded_andMatrixOutputs_T_283}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_3_6 = \|{&_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_224, &_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_231, &_decoded_andMatrixOutputs_T_235, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_245, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_252, &_decoded_andMatrixOutputs_T_256, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_267, &_decoded_andMatrixOutputs_T_277, &_decoded_andMatrixOutputs_T_279, &_decoded_andMatrixOutputs_T_281, &_decoded_andMatrixOutputs_T_283}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_3_7 = \|{&_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_224, &_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_231, &_decoded_andMatrixOutputs_T_235, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_245, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_252, &_decoded_andMatrixOutputs_T_256, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_267, &_decoded_andMatrixOutputs_T_277, &_decoded_andMatrixOutputs_T_279, &_decoded_andMatrixOutputs_T_281, &_decoded_andMatrixOutputs_T_283}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_2_1 = \|{&{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[2], decoded_invInputs_4[3], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_236, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_257}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_2_2 = \|{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_236, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_257}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_2_3 = \|{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_236, &{decoded_invInputs_4[0], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}, &{decoded_invInputs_4[0], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_257, &_decoded_andMatrixOutputs_T_268, &_decoded_andMatrixOutputs_T_270}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_2_4 = \|{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_236, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_257, &_decoded_andMatrixOutputs_T_268, &_decoded_andMatrixOutputs_T_270}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_2_5 = \|{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_236, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_257, &_decoded_andMatrixOutputs_T_268, &_decoded_andMatrixOutputs_T_270}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_2_6 = \|{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_236, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_257, &_decoded_andMatrixOutputs_T_268, &_decoded_andMatrixOutputs_T_270}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_2_7 = \|{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_236, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_257, &_decoded_andMatrixOutputs_T_268, &_decoded_andMatrixOutputs_T_270}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_1 = \|{&{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[0], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[0], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[0], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[0], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[0], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[0], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_2 = \|{&_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_237, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_258}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_3 = \|{&_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_237, &{decoded_invInputs_4[0], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}, &{decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_258, &{decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}, &_decoded_andMatrixOutputs_T_269}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_4 = \|{&_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_237, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_258, &_decoded_andMatrixOutputs_T_265, &_decoded_andMatrixOutputs_T_269}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_5 = \|{&_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_237, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_258, &_decoded_andMatrixOutputs_T_265, &_decoded_andMatrixOutputs_T_269, &_decoded_andMatrixOutputs_T_276, &_decoded_andMatrixOutputs_T_278, &_decoded_andMatrixOutputs_T_280, &_decoded_andMatrixOutputs_T_282}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_6 = \|{&_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_237, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_258, &_decoded_andMatrixOutputs_T_265, &_decoded_andMatrixOutputs_T_269, &_decoded_andMatrixOutputs_T_276, &_decoded_andMatrixOutputs_T_278, &_decoded_andMatrixOutputs_T_280, &_decoded_andMatrixOutputs_T_282}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_7 = \|{&_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_237, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_258, &_decoded_andMatrixOutputs_T_265, &_decoded_andMatrixOutputs_T_269, &_decoded_andMatrixOutputs_T_276, &_decoded_andMatrixOutputs_T_278, &_decoded_andMatrixOutputs_T_280, &_decoded_andMatrixOutputs_T_282}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_0_0 = &_decoded_andMatrixOutputs_T_221; // @[pla.scala:98:{53,70}] assign io_resp_4_vc_sel_0_1 = &_decoded_andMatrixOutputs_T_221; // @[pla.scala:98:{53,70}] assign io_resp_4_vc_sel_0_2 = \|{&_decoded_andMatrixOutputs_T_221, &_decoded_andMatrixOutputs_T_239, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_260, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_263}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_0_3 = \|{&_decoded_andMatrixOutputs_T_221, &_decoded_andMatrixOutputs_T_239, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_260, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_263}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_0_4 = \|{&_decoded_andMatrixOutputs_T_221, &_decoded_andMatrixOutputs_T_239, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_260, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_263, &_decoded_andMatrixOutputs_T_272, &_decoded_andMatrixOutputs_T_273, &_decoded_andMatrixOutputs_T_275}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_0_5 = \|{&_decoded_andMatrixOutputs_T_221, &_decoded_andMatrixOutputs_T_239, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_260, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_263, &_decoded_andMatrixOutputs_T_272, &_decoded_andMatrixOutputs_T_273, &_decoded_andMatrixOutputs_T_275}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_0_6 = \|{&_decoded_andMatrixOutputs_T_221, &_decoded_andMatrixOutputs_T_239, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_260, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_263, &_decoded_andMatrixOutputs_T_272, &_decoded_andMatrixOutputs_T_273, &_decoded_andMatrixOutputs_T_275}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_0_7 = \|{&_decoded_andMatrixOutputs_T_221, &_decoded_andMatrixOutputs_T_239, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_260, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_263, &_decoded_andMatrixOutputs_T_272, &_decoded_andMatrixOutputs_T_273, &_decoded_andMatrixOutputs_T_275}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_0 = \|{&{decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16]}, &{decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_1 = \|{&_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_150, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_159, &_decoded_andMatrixOutputs_T_160, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_187, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_2 = \|{&_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_159, &_decoded_andMatrixOutputs_T_160, &_decoded_andMatrixOutputs_T_162, &_decoded_andMatrixOutputs_T_168, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_195, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_203}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_3 = \|{&_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_159, &_decoded_andMatrixOutputs_T_160, &_decoded_andMatrixOutputs_T_162, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_179, &{decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_195, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_203, &{decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_4 = \|{&_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_159, &_decoded_andMatrixOutputs_T_160, &_decoded_andMatrixOutputs_T_162, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_179, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_195, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_203, &_decoded_andMatrixOutputs_T_207, &{decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}, &{decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_5 = \|{&_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_159, &_decoded_andMatrixOutputs_T_160, &_decoded_andMatrixOutputs_T_162, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_179, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_195, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_203, &_decoded_andMatrixOutputs_T_207, &_decoded_andMatrixOutputs_T_217, &_decoded_andMatrixOutputs_T_218, &_decoded_andMatrixOutputs_T_219, &_decoded_andMatrixOutputs_T_220}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_6 = \|{&_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_159, &_decoded_andMatrixOutputs_T_160, &_decoded_andMatrixOutputs_T_162, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_179, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_195, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_203, &_decoded_andMatrixOutputs_T_207, &_decoded_andMatrixOutputs_T_217, &_decoded_andMatrixOutputs_T_218, &_decoded_andMatrixOutputs_T_219, &_decoded_andMatrixOutputs_T_220}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_4_7 = \|{&_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_159, &_decoded_andMatrixOutputs_T_160, &_decoded_andMatrixOutputs_T_162, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_179, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_195, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_203, &_decoded_andMatrixOutputs_T_207, &_decoded_andMatrixOutputs_T_217, &_decoded_andMatrixOutputs_T_218, &_decoded_andMatrixOutputs_T_219, &_decoded_andMatrixOutputs_T_220}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_2_1 = \|{&{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_161, &_decoded_andMatrixOutputs_T_163, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_170, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_192, &_decoded_andMatrixOutputs_T_197}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_2_2 = \|{&_decoded_andMatrixOutputs_T_161, &_decoded_andMatrixOutputs_T_163, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_170, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_192, &_decoded_andMatrixOutputs_T_197}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_2_3 = \|{&_decoded_andMatrixOutputs_T_161, &_decoded_andMatrixOutputs_T_163, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_170, &{decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}, &{decoded_invInputs_3[0], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}, &{decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_192, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_208, &_decoded_andMatrixOutputs_T_211}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_2_4 = \|{&_decoded_andMatrixOutputs_T_161, &_decoded_andMatrixOutputs_T_163, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_170, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_192, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_208, &_decoded_andMatrixOutputs_T_211}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_2_5 = \|{&_decoded_andMatrixOutputs_T_161, &_decoded_andMatrixOutputs_T_163, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_170, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_192, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_208, &_decoded_andMatrixOutputs_T_211}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_2_6 = \|{&_decoded_andMatrixOutputs_T_161, &_decoded_andMatrixOutputs_T_163, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_170, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_192, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_208, &_decoded_andMatrixOutputs_T_211}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_2_7 = \|{&_decoded_andMatrixOutputs_T_161, &_decoded_andMatrixOutputs_T_163, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_170, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_192, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_208, &_decoded_andMatrixOutputs_T_211}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_1_1 = \|{&{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[3], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[3], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[3], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[3], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[3], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[3], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_1_2 = \|{&_decoded_andMatrixOutputs_T_166, &_decoded_andMatrixOutputs_T_171, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_198}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_1_3 = \|{&_decoded_andMatrixOutputs_T_166, &_decoded_andMatrixOutputs_T_171, &{decoded_invInputs_3[0], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}, &{decoded_invInputs_3[0], decoded_invInputs_3[4], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], decoded_invInputs_3[9], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_198, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_210}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_1_4 = \|{&_decoded_andMatrixOutputs_T_166, &_decoded_andMatrixOutputs_T_171, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_198, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_210}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_1_5 = \|{&_decoded_andMatrixOutputs_T_166, &_decoded_andMatrixOutputs_T_171, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_198, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_210}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_1_6 = \|{&_decoded_andMatrixOutputs_T_166, &_decoded_andMatrixOutputs_T_171, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_198, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_210}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_1_7 = \|{&_decoded_andMatrixOutputs_T_166, &_decoded_andMatrixOutputs_T_171, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_198, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_210}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_0 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_1 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_2 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_175, &_decoded_andMatrixOutputs_T_177, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_3 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_175, &_decoded_andMatrixOutputs_T_177, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_4 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_175, &_decoded_andMatrixOutputs_T_177, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204, &_decoded_andMatrixOutputs_T_212, &_decoded_andMatrixOutputs_T_214, &_decoded_andMatrixOutputs_T_216}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_5 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_175, &_decoded_andMatrixOutputs_T_177, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204, &_decoded_andMatrixOutputs_T_212, &_decoded_andMatrixOutputs_T_214, &_decoded_andMatrixOutputs_T_216}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_6 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_175, &_decoded_andMatrixOutputs_T_177, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204, &_decoded_andMatrixOutputs_T_212, &_decoded_andMatrixOutputs_T_214, &_decoded_andMatrixOutputs_T_216}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_7 = \|{&_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_175, &_decoded_andMatrixOutputs_T_177, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204, &_decoded_andMatrixOutputs_T_212, &_decoded_andMatrixOutputs_T_214, &_decoded_andMatrixOutputs_T_216}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_4_0 = &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[0], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_2_vc_sel_4_1 = \|{&_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_116}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_4_2 = \|{&_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_102, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[3], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_116, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[3], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_4_3 = \|{&_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_112, &_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_121}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_4_4 = \|{&_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_112, &_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_121, &{decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[0], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_4_5 = \|{&_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_112, &_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_121, &_decoded_andMatrixOutputs_T_134, &_decoded_andMatrixOutputs_T_140}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_4_6 = \|{&_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_112, &_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_121, &_decoded_andMatrixOutputs_T_134, &_decoded_andMatrixOutputs_T_140}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_4_7 = \|{&_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_112, &_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_121, &_decoded_andMatrixOutputs_T_134, &_decoded_andMatrixOutputs_T_140}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_0 = &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], decoded_invInputs_2[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_2_vc_sel_3_1 = \|{&_decoded_andMatrixOutputs_T_97, &_decoded_andMatrixOutputs_T_99, &_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_101, &_decoded_andMatrixOutputs_T_103, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_118}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_2 = \|{&_decoded_andMatrixOutputs_T_97, &_decoded_andMatrixOutputs_T_99, &_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_101, &_decoded_andMatrixOutputs_T_103, &_decoded_andMatrixOutputs_T_104, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_123, &_decoded_andMatrixOutputs_T_125}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_3 = \|{&_decoded_andMatrixOutputs_T_97, &_decoded_andMatrixOutputs_T_99, &_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_101, &_decoded_andMatrixOutputs_T_103, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_111, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_123, &_decoded_andMatrixOutputs_T_125}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_4 = \|{&_decoded_andMatrixOutputs_T_97, &_decoded_andMatrixOutputs_T_99, &_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_101, &_decoded_andMatrixOutputs_T_103, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_111, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_123, &_decoded_andMatrixOutputs_T_125, &{decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[2], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}, &{decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}, &{decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_5 = \|{&_decoded_andMatrixOutputs_T_97, &_decoded_andMatrixOutputs_T_99, &_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_101, &_decoded_andMatrixOutputs_T_103, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_111, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_123, &_decoded_andMatrixOutputs_T_125, &_decoded_andMatrixOutputs_T_132, &_decoded_andMatrixOutputs_T_133, &_decoded_andMatrixOutputs_T_135, &_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_138, &_decoded_andMatrixOutputs_T_139, &_decoded_andMatrixOutputs_T_141, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_143}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_6 = \|{&_decoded_andMatrixOutputs_T_97, &_decoded_andMatrixOutputs_T_99, &_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_101, &_decoded_andMatrixOutputs_T_103, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_111, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_123, &_decoded_andMatrixOutputs_T_125, &_decoded_andMatrixOutputs_T_132, &_decoded_andMatrixOutputs_T_133, &_decoded_andMatrixOutputs_T_135, &_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_138, &_decoded_andMatrixOutputs_T_139, &_decoded_andMatrixOutputs_T_141, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_143}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_7 = \|{&_decoded_andMatrixOutputs_T_97, &_decoded_andMatrixOutputs_T_99, &_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_101, &_decoded_andMatrixOutputs_T_103, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_111, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_123, &_decoded_andMatrixOutputs_T_125, &_decoded_andMatrixOutputs_T_132, &_decoded_andMatrixOutputs_T_133, &_decoded_andMatrixOutputs_T_135, &_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_138, &_decoded_andMatrixOutputs_T_139, &_decoded_andMatrixOutputs_T_141, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_143}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_5 = \|{&_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_143}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_6 = \|{&_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_143}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_7 = \|{&_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_143}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_0 = \|decoded_orMatrixOutputs_hi_hi_58; // @[pla.scala:114:{19,36}] assign io_resp_2_vc_sel_0_1 = \|decoded_orMatrixOutputs_hi_hi_58; // @[pla.scala:114:{19,36}] assign io_resp_2_vc_sel_0_2 = \|{&_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_96, &_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_109, &_decoded_andMatrixOutputs_T_119, &_decoded_andMatrixOutputs_T_124}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_3 = \|{&_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_96, &_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_109, &_decoded_andMatrixOutputs_T_119, &_decoded_andMatrixOutputs_T_124}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_4 = \|{&_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_96, &_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_109, &_decoded_andMatrixOutputs_T_119, &_decoded_andMatrixOutputs_T_124, &_decoded_andMatrixOutputs_T_127, &_decoded_andMatrixOutputs_T_128}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_5 = \|{&_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_96, &_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_109, &_decoded_andMatrixOutputs_T_119, &_decoded_andMatrixOutputs_T_124, &_decoded_andMatrixOutputs_T_127, &_decoded_andMatrixOutputs_T_128}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_6 = \|{&_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_96, &_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_109, &_decoded_andMatrixOutputs_T_119, &_decoded_andMatrixOutputs_T_124, &_decoded_andMatrixOutputs_T_127, &_decoded_andMatrixOutputs_T_128}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_7 = \|{&_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_96, &_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_109, &_decoded_andMatrixOutputs_T_119, &_decoded_andMatrixOutputs_T_124, &_decoded_andMatrixOutputs_T_127, &_decoded_andMatrixOutputs_T_128}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_0 = \|{&{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16]}, &{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_1 = \|{&_decoded_andMatrixOutputs_T_41, &_decoded_andMatrixOutputs_T_43, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_48, &_decoded_andMatrixOutputs_T_50, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_66, &_decoded_andMatrixOutputs_T_68, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_2 = \|{&_decoded_andMatrixOutputs_T_41, &_decoded_andMatrixOutputs_T_43, &_decoded_andMatrixOutputs_T_48, &_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_66, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}, &_decoded_andMatrixOutputs_T_79}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_3 = \|{&_decoded_andMatrixOutputs_T_41, &_decoded_andMatrixOutputs_T_43, &_decoded_andMatrixOutputs_T_48, &_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_64, &_decoded_andMatrixOutputs_T_66, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_79}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_4 = \|{&_decoded_andMatrixOutputs_T_41, &_decoded_andMatrixOutputs_T_43, &_decoded_andMatrixOutputs_T_48, &_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_64, &_decoded_andMatrixOutputs_T_66, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_79, &{decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}, &{decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_5 = \|{&_decoded_andMatrixOutputs_T_41, &_decoded_andMatrixOutputs_T_43, &_decoded_andMatrixOutputs_T_48, &_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_64, &_decoded_andMatrixOutputs_T_66, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_79, &_decoded_andMatrixOutputs_T_86, &_decoded_andMatrixOutputs_T_87, &_decoded_andMatrixOutputs_T_90, &_decoded_andMatrixOutputs_T_91}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_6 = \|{&_decoded_andMatrixOutputs_T_41, &_decoded_andMatrixOutputs_T_43, &_decoded_andMatrixOutputs_T_48, &_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_64, &_decoded_andMatrixOutputs_T_66, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_79, &_decoded_andMatrixOutputs_T_86, &_decoded_andMatrixOutputs_T_87, &_decoded_andMatrixOutputs_T_90, &_decoded_andMatrixOutputs_T_91}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_4_7 = \|{&_decoded_andMatrixOutputs_T_41, &_decoded_andMatrixOutputs_T_43, &_decoded_andMatrixOutputs_T_48, &_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_64, &_decoded_andMatrixOutputs_T_66, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_79, &_decoded_andMatrixOutputs_T_86, &_decoded_andMatrixOutputs_T_87, &_decoded_andMatrixOutputs_T_90, &_decoded_andMatrixOutputs_T_91}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_0 = &{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], decoded_invInputs_1[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_1_vc_sel_3_1 = \|{&_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_67}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_2 = \|{&_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_49, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_67, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_3 = \|{&_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_61, &_decoded_andMatrixOutputs_T_63, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_67, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_4 = \|{&_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_61, &_decoded_andMatrixOutputs_T_63, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_67, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77, &{decoded_invInputs_1[0], decoded_invInputs_1[1], decoded_invInputs_1[2], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_5 = \|{&_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_61, &_decoded_andMatrixOutputs_T_63, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_67, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77, &_decoded_andMatrixOutputs_T_85, &_decoded_andMatrixOutputs_T_88, &_decoded_andMatrixOutputs_T_89, &_decoded_andMatrixOutputs_T_92}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_6 = \|{&_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_61, &_decoded_andMatrixOutputs_T_63, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_67, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77, &_decoded_andMatrixOutputs_T_85, &_decoded_andMatrixOutputs_T_88, &_decoded_andMatrixOutputs_T_89, &_decoded_andMatrixOutputs_T_92}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_7 = \|{&_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_61, &_decoded_andMatrixOutputs_T_63, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_67, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77, &_decoded_andMatrixOutputs_T_85, &_decoded_andMatrixOutputs_T_88, &_decoded_andMatrixOutputs_T_89, &_decoded_andMatrixOutputs_T_92}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_1 = \|{&{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_53, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_2 = \|{&_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_53, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_3 = \|{&_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_53, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_4 = \|{&_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_53, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_5 = \|{&_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_53, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_6 = \|{&_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_53, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_7 = \|{&_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_53, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_0 = \|decoded_orMatrixOutputs_hi_hi_38; // @[pla.scala:114:{19,36}] assign io_resp_1_vc_sel_0_1 = \|decoded_orMatrixOutputs_hi_hi_38; // @[pla.scala:114:{19,36}] assign io_resp_1_vc_sel_0_2 = \|{&_decoded_andMatrixOutputs_T_36, &_decoded_andMatrixOutputs_T_38, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_78}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_3 = \|{&_decoded_andMatrixOutputs_T_36, &_decoded_andMatrixOutputs_T_38, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_78}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_4 = \|{&_decoded_andMatrixOutputs_T_36, &_decoded_andMatrixOutputs_T_38, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_78, &_decoded_andMatrixOutputs_T_81, &_decoded_andMatrixOutputs_T_82}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_5 = \|{&_decoded_andMatrixOutputs_T_36, &_decoded_andMatrixOutputs_T_38, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_78, &_decoded_andMatrixOutputs_T_81, &_decoded_andMatrixOutputs_T_82}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_6 = \|{&_decoded_andMatrixOutputs_T_36, &_decoded_andMatrixOutputs_T_38, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_78, &_decoded_andMatrixOutputs_T_81, &_decoded_andMatrixOutputs_T_82}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_7 = \|{&_decoded_andMatrixOutputs_T_36, &_decoded_andMatrixOutputs_T_38, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_78, &_decoded_andMatrixOutputs_T_81, &_decoded_andMatrixOutputs_T_82}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_4_1 = \|{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_4_2 = \|{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_26}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_4_3 = \|{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_12, &{decoded_invInputs[0], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_26, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_4_4 = \|{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_26, &_decoded_andMatrixOutputs_T_32}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_4_5 = \|{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_26, &_decoded_andMatrixOutputs_T_32}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_4_6 = \|{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_26, &_decoded_andMatrixOutputs_T_32}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_4_7 = \|{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_26, &_decoded_andMatrixOutputs_T_32}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_1 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_25}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_2 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_25}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_3 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_25, &_decoded_andMatrixOutputs_T_30}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_4 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_25, &_decoded_andMatrixOutputs_T_30}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_5 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_25, &_decoded_andMatrixOutputs_T_30}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_6 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_25, &_decoded_andMatrixOutputs_T_30}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_7 = \|{&_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_25, &_decoded_andMatrixOutputs_T_30}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_1 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_22}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_2 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_22}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_3 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_22, &_decoded_andMatrixOutputs_T_31, &_decoded_andMatrixOutputs_T_33}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_4 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_22, &_decoded_andMatrixOutputs_T_31, &_decoded_andMatrixOutputs_T_33}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_5 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_22, &_decoded_andMatrixOutputs_T_31, &_decoded_andMatrixOutputs_T_33}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_6 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_22, &_decoded_andMatrixOutputs_T_31, &_decoded_andMatrixOutputs_T_33}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_7 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_22, &_decoded_andMatrixOutputs_T_31, &_decoded_andMatrixOutputs_T_33}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_1 = \|{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_2 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_23}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_3 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_9, &{decoded_invInputs[0], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_23, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_4 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_23, &_decoded_andMatrixOutputs_T_28}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_5 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_23, &_decoded_andMatrixOutputs_T_28}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_6 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_23, &_decoded_andMatrixOutputs_T_28}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_7 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_23, &_decoded_andMatrixOutputs_T_28}; // @[pla.scala:98:{53,70}, :114:{19,36}] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module InputBuffer_1( // @[InputUnit.scala:49:7] input clock, // @[InputUnit.scala:49:7] input reset, // @[InputUnit.scala:49:7] input io_enq_0_valid, // @[InputUnit.scala:51:14] input io_enq_0_bits_head, // @[InputUnit.scala:51:14] input io_enq_0_bits_tail, // @[InputUnit.scala:51:14] input [72:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14] input [4:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14] output io_deq_0_bits_head, // @[InputUnit.scala:51:14] output io_deq_0_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14] output io_deq_1_bits_head, // @[InputUnit.scala:51:14] output io_deq_1_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14] input io_deq_2_ready, // @[InputUnit.scala:51:14] output io_deq_2_valid, // @[InputUnit.scala:51:14] output io_deq_2_bits_head, // @[InputUnit.scala:51:14] output io_deq_2_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14] input io_deq_3_ready, // @[InputUnit.scala:51:14] output io_deq_3_valid, // @[InputUnit.scala:51:14] output io_deq_3_bits_head, // @[InputUnit.scala:51:14] output io_deq_3_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_3_bits_payload, // @[InputUnit.scala:51:14] output io_deq_4_bits_head, // @[InputUnit.scala:51:14] output io_deq_4_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_4_bits_payload, // @[InputUnit.scala:51:14] output io_deq_5_bits_head, // @[InputUnit.scala:51:14] output io_deq_5_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_5_bits_payload, // @[InputUnit.scala:51:14] output io_deq_6_bits_head, // @[InputUnit.scala:51:14] output io_deq_6_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_6_bits_payload, // @[InputUnit.scala:51:14] output io_deq_7_bits_head, // @[InputUnit.scala:51:14] output io_deq_7_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_7_bits_payload, // @[InputUnit.scala:51:14] output io_deq_8_bits_head, // @[InputUnit.scala:51:14] output io_deq_8_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_8_bits_payload, // @[InputUnit.scala:51:14] output io_deq_9_bits_head, // @[InputUnit.scala:51:14] output io_deq_9_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_9_bits_payload, // @[InputUnit.scala:51:14] input io_deq_10_ready, // @[InputUnit.scala:51:14] output io_deq_10_valid, // @[InputUnit.scala:51:14] output io_deq_10_bits_head, // @[InputUnit.scala:51:14] output io_deq_10_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_10_bits_payload, // @[InputUnit.scala:51:14] input io_deq_11_ready, // @[InputUnit.scala:51:14] output io_deq_11_valid, // @[InputUnit.scala:51:14] output io_deq_11_bits_head, // @[InputUnit.scala:51:14] output io_deq_11_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_11_bits_payload, // @[InputUnit.scala:51:14] input io_deq_12_ready, // @[InputUnit.scala:51:14] output io_deq_12_valid, // @[InputUnit.scala:51:14] output io_deq_12_bits_head, // @[InputUnit.scala:51:14] output io_deq_12_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_12_bits_payload, // @[InputUnit.scala:51:14] input io_deq_13_ready, // @[InputUnit.scala:51:14] output io_deq_13_valid, // @[InputUnit.scala:51:14] output io_deq_13_bits_head, // @[InputUnit.scala:51:14] output io_deq_13_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_13_bits_payload, // @[InputUnit.scala:51:14] input io_deq_14_ready, // @[InputUnit.scala:51:14] output io_deq_14_valid, // @[InputUnit.scala:51:14] output io_deq_14_bits_head, // @[InputUnit.scala:51:14] output io_deq_14_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_14_bits_payload, // @[InputUnit.scala:51:14] input io_deq_15_ready, // @[InputUnit.scala:51:14] output io_deq_15_valid, // @[InputUnit.scala:51:14] output io_deq_15_bits_head, // @[InputUnit.scala:51:14] output io_deq_15_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_15_bits_payload, // @[InputUnit.scala:51:14] input io_deq_16_ready, // @[InputUnit.scala:51:14] output io_deq_16_valid, // @[InputUnit.scala:51:14] output io_deq_16_bits_head, // @[InputUnit.scala:51:14] output io_deq_16_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_16_bits_payload, // @[InputUnit.scala:51:14] input io_deq_17_ready, // @[InputUnit.scala:51:14] output io_deq_17_valid, // @[InputUnit.scala:51:14] output io_deq_17_bits_head, // @[InputUnit.scala:51:14] output io_deq_17_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_17_bits_payload, // @[InputUnit.scala:51:14] input io_deq_18_ready, // @[InputUnit.scala:51:14] output io_deq_18_valid, // @[InputUnit.scala:51:14] output io_deq_18_bits_head, // @[InputUnit.scala:51:14] output io_deq_18_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_18_bits_payload, // @[InputUnit.scala:51:14] input io_deq_19_ready, // @[InputUnit.scala:51:14] output io_deq_19_valid, // @[InputUnit.scala:51:14] output io_deq_19_bits_head, // @[InputUnit.scala:51:14] output io_deq_19_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_19_bits_payload, // @[InputUnit.scala:51:14] input io_deq_20_ready, // @[InputUnit.scala:51:14] output io_deq_20_valid, // @[InputUnit.scala:51:14] output io_deq_20_bits_head, // @[InputUnit.scala:51:14] output io_deq_20_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_20_bits_payload, // @[InputUnit.scala:51:14] input io_deq_21_ready, // @[InputUnit.scala:51:14] output io_deq_21_valid, // @[InputUnit.scala:51:14] output io_deq_21_bits_head, // @[InputUnit.scala:51:14] output io_deq_21_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_21_bits_payload // @[InputUnit.scala:51:14] ); wire _qs_21_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_20_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_19_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_18_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_17_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_16_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_15_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_14_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_13_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_12_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_11_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_10_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_9_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_8_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_7_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_6_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_5_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_4_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49] wire [74:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R4_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R5_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R6_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R7_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R8_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R9_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R10_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R11_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R12_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R13_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R14_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R15_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R16_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R17_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R18_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R19_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R20_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R21_data; // @[InputUnit.scala:85:18] reg [5:0] heads_0; // @[InputUnit.scala:86:24] reg [5:0] heads_1; // @[InputUnit.scala:86:24] reg [5:0] heads_2; // @[InputUnit.scala:86:24] reg [5:0] heads_3; // @[InputUnit.scala:86:24] reg [5:0] heads_4; // @[InputUnit.scala:86:24] reg [5:0] heads_5; // @[InputUnit.scala:86:24] reg [5:0] heads_6; // @[InputUnit.scala:86:24] reg [5:0] heads_7; // @[InputUnit.scala:86:24] reg [5:0] heads_8; // @[InputUnit.scala:86:24] reg [5:0] heads_9; // @[InputUnit.scala:86:24] reg [5:0] heads_10; // @[InputUnit.scala:86:24] reg [5:0] heads_11; // @[InputUnit.scala:86:24] reg [5:0] heads_12; // @[InputUnit.scala:86:24] reg [5:0] heads_13; // @[InputUnit.scala:86:24] reg [5:0] heads_14; // @[InputUnit.scala:86:24] reg [5:0] heads_15; // @[InputUnit.scala:86:24] reg [5:0] heads_16; // @[InputUnit.scala:86:24] reg [5:0] heads_17; // @[InputUnit.scala:86:24] reg [5:0] heads_18; // @[InputUnit.scala:86:24] reg [5:0] heads_19; // @[InputUnit.scala:86:24] reg [5:0] heads_20; // @[InputUnit.scala:86:24] reg [5:0] heads_21; // @[InputUnit.scala:86:24] reg [5:0] tails_0; // @[InputUnit.scala:87:24] reg [5:0] tails_1; // @[InputUnit.scala:87:24] reg [5:0] tails_2; // @[InputUnit.scala:87:24] reg [5:0] tails_3; // @[InputUnit.scala:87:24] reg [5:0] tails_4; // @[InputUnit.scala:87:24] reg [5:0] tails_5; // @[InputUnit.scala:87:24] reg [5:0] tails_6; // @[InputUnit.scala:87:24] reg [5:0] tails_7; // @[InputUnit.scala:87:24] reg [5:0] tails_8; // @[InputUnit.scala:87:24] reg [5:0] tails_9; // @[InputUnit.scala:87:24] reg [5:0] tails_10; // @[InputUnit.scala:87:24] reg [5:0] tails_11; // @[InputUnit.scala:87:24] reg [5:0] tails_12; // @[InputUnit.scala:87:24] reg [5:0] tails_13; // @[InputUnit.scala:87:24] reg [5:0] tails_14; // @[InputUnit.scala:87:24] reg [5:0] tails_15; // @[InputUnit.scala:87:24] reg [5:0] tails_16; // @[InputUnit.scala:87:24] reg [5:0] tails_17; // @[InputUnit.scala:87:24] reg [5:0] tails_18; // @[InputUnit.scala:87:24] reg [5:0] tails_19; // @[InputUnit.scala:87:24] reg [5:0] tails_20; // @[InputUnit.scala:87:24] reg [5:0] tails_21; // @[InputUnit.scala:87:24] wire _tails_T_66 = io_enq_0_bits_virt_channel_id == 5'h0; // @[Mux.scala:32:36] wire _tails_T_67 = io_enq_0_bits_virt_channel_id == 5'h1; // @[Mux.scala:32:36] wire _tails_T_68 = io_enq_0_bits_virt_channel_id == 5'h2; // @[Mux.scala:32:36] wire _tails_T_69 = io_enq_0_bits_virt_channel_id == 5'h3; // @[Mux.scala:32:36] wire _tails_T_70 = io_enq_0_bits_virt_channel_id == 5'h4; // @[Mux.scala:32:36] wire _tails_T_71 = io_enq_0_bits_virt_channel_id == 5'h5; // @[Mux.scala:32:36] wire _tails_T_72 = io_enq_0_bits_virt_channel_id == 5'h6; // @[Mux.scala:32:36] wire _tails_T_73 = io_enq_0_bits_virt_channel_id == 5'h7; // @[Mux.scala:32:36] wire _tails_T_74 = io_enq_0_bits_virt_channel_id == 5'h8; // @[Mux.scala:32:36] wire _tails_T_75 = io_enq_0_bits_virt_channel_id == 5'h9; // @[Mux.scala:32:36] wire _tails_T_76 = io_enq_0_bits_virt_channel_id == 5'hA; // @[Mux.scala:32:36] wire _tails_T_77 = io_enq_0_bits_virt_channel_id == 5'hB; // @[Mux.scala:32:36] wire _tails_T_78 = io_enq_0_bits_virt_channel_id == 5'hC; // @[Mux.scala:32:36] wire _tails_T_79 = io_enq_0_bits_virt_channel_id == 5'hD; // @[Mux.scala:32:36] wire _tails_T_80 = io_enq_0_bits_virt_channel_id == 5'hE; // @[Mux.scala:32:36] wire _tails_T_81 = io_enq_0_bits_virt_channel_id == 5'hF; // @[Mux.scala:32:36] wire _tails_T_82 = io_enq_0_bits_virt_channel_id == 5'h10; // @[Mux.scala:32:36] wire _tails_T_83 = io_enq_0_bits_virt_channel_id == 5'h11; // @[Mux.scala:32:36] wire _tails_T_84 = io_enq_0_bits_virt_channel_id == 5'h12; // @[Mux.scala:32:36] wire _tails_T_85 = io_enq_0_bits_virt_channel_id == 5'h13; // @[Mux.scala:32:36] wire _tails_T_86 = io_enq_0_bits_virt_channel_id == 5'h14; // @[Mux.scala:32:36] wire _tails_T_87 = io_enq_0_bits_virt_channel_id == 5'h15; // @[Mux.scala:32:36] wire direct_to_q = (_tails_T_66 & _qs_0_io_enq_ready \| _tails_T_67 & _qs_1_io_enq_ready \| _tails_T_68 & _qs_2_io_enq_ready \| _tails_T_69 & _qs_3_io_enq_ready \| _tails_T_70 & _qs_4_io_enq_ready \| _tails_T_71 & _qs_5_io_enq_ready \| _tails_T_72 & _qs_6_io_enq_ready \| _tails_T_73 & _qs_7_io_enq_ready \| _tails_T_74 & _qs_8_io_enq_ready \| _tails_T_75 & _qs_9_io_enq_ready \| _tails_T_76 & _qs_10_io_enq_ready \| _tails_T_77 & _qs_11_io_enq_ready \| _tails_T_78 & _qs_12_io_enq_ready \| _tails_T_79 & _qs_13_io_enq_ready \| _tails_T_80 & _qs_14_io_enq_ready \| _tails_T_81 & _qs_15_io_enq_ready \| _tails_T_82 & _qs_16_io_enq_ready \| _tails_T_83 & _qs_17_io_enq_ready \| _tails_T_84 & _qs_18_io_enq_ready \| _tails_T_85 & _qs_19_io_enq_ready \| _tails_T_86 & _qs_20_io_enq_ready \| _tails_T_87 & _qs_21_io_enq_ready) & (_tails_T_66 & heads_0 == tails_0 \| _tails_T_67 & heads_1 == tails_1 \| _tails_T_68 & heads_2 == tails_2 \| _tails_T_69 & heads_3 == tails_3 \| _tails_T_70 & heads_4 == tails_4 \| _tails_T_71 & heads_5 == tails_5 \| _tails_T_72 & heads_6 == tails_6 \| _tails_T_73 & heads_7 == tails_7 \| _tails_T_74 & heads_8 == tails_8 \| _tails_T_75 & heads_9 == tails_9 \| _tails_T_76 & heads_10 == tails_10 \| _tails_T_77 & heads_11 == tails_11 \| _tails_T_78 & heads_12 == tails_12 \| _tails_T_79 & heads_13 == tails_13 \| _tails_T_80 & heads_14 == tails_14 \| _tails_T_81 & heads_15 == tails_15 \| _tails_T_82 & heads_16 == tails_16 \| _tails_T_83 & heads_17 == tails_17 \| _tails_T_84 & heads_18 == tails_18 \| _tails_T_85 & heads_19 == tails_19 \| _tails_T_86 & heads_20 == tails_20 \| _tails_T_87 & heads_21 == tails_21); // @[Mux.scala:30:73, :32:36] wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}] wire [31:0][5:0] _GEN = {{tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_21}, {tails_20}, {tails_19}, {tails_18}, {tails_17}, {tails_16}, {tails_15}, {tails_14}, {tails_13}, {tails_12}, {tails_11}, {tails_10}, {tails_9}, {tails_8}, {tails_7}, {tails_6}, {tails_5}, {tails_4}, {tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16] wire _GEN_0 = io_enq_0_bits_virt_channel_id == 5'h0; // @[InputUnit.scala:103:45] wire _GEN_1 = io_enq_0_bits_virt_channel_id == 5'h1; // @[InputUnit.scala:103:45] wire _GEN_2 = io_enq_0_bits_virt_channel_id == 5'h2; // @[InputUnit.scala:103:45] wire _GEN_3 = io_enq_0_bits_virt_channel_id == 5'h3; // @[InputUnit.scala:103:45] wire _GEN_4 = io_enq_0_bits_virt_channel_id == 5'h4; // @[InputUnit.scala:103:45] wire _GEN_5 = io_enq_0_bits_virt_channel_id == 5'h5; // @[InputUnit.scala:103:45] wire _GEN_6 = io_enq_0_bits_virt_channel_id == 5'h6; // @[InputUnit.scala:103:45] wire _GEN_7 = io_enq_0_bits_virt_channel_id == 5'h7; // @[InputUnit.scala:103:45] wire _GEN_8 = io_enq_0_bits_virt_channel_id == 5'h8; // @[InputUnit.scala:103:45] wire _GEN_9 = io_enq_0_bits_virt_channel_id == 5'h9; // @[InputUnit.scala:103:45] wire _GEN_10 = io_enq_0_bits_virt_channel_id == 5'hA; // @[InputUnit.scala:103:45] wire _GEN_11 = io_enq_0_bits_virt_channel_id == 5'hB; // @[InputUnit.scala:103:45] wire _GEN_12 = io_enq_0_bits_virt_channel_id == 5'hC; // @[InputUnit.scala:103:45] wire _GEN_13 = io_enq_0_bits_virt_channel_id == 5'hD; // @[InputUnit.scala:103:45] wire _GEN_14 = io_enq_0_bits_virt_channel_id == 5'hE; // @[InputUnit.scala:103:45] wire _GEN_15 = io_enq_0_bits_virt_channel_id == 5'hF; // @[InputUnit.scala:103:45] wire _GEN_16 = io_enq_0_bits_virt_channel_id == 5'h10; // @[InputUnit.scala:103:45] wire _GEN_17 = io_enq_0_bits_virt_channel_id == 5'h11; // @[InputUnit.scala:103:45] wire _GEN_18 = io_enq_0_bits_virt_channel_id == 5'h12; // @[InputUnit.scala:103:45] wire _GEN_19 = io_enq_0_bits_virt_channel_id == 5'h13; // @[InputUnit.scala:103:45] wire _GEN_20 = io_enq_0_bits_virt_channel_id == 5'h14; // @[InputUnit.scala:103:45] wire _GEN_21 = io_enq_0_bits_virt_channel_id == 5'h15; // @[InputUnit.scala:103:45] wire _GEN_22 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34] wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_4 = heads_4 != tails_4 & _qs_4_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_5 = heads_5 != tails_5 & _qs_5_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_6 = heads_6 != tails_6 & _qs_6_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_7 = heads_7 != tails_7 & _qs_7_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_8 = heads_8 != tails_8 & _qs_8_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_9 = heads_9 != tails_9 & _qs_9_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_10 = heads_10 != tails_10 & _qs_10_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_11 = heads_11 != tails_11 & _qs_11_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_12 = heads_12 != tails_12 & _qs_12_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_13 = heads_13 != tails_13 & _qs_13_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_14 = heads_14 != tails_14 & _qs_14_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_15 = heads_15 != tails_15 & _qs_15_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_16 = heads_16 != tails_16 & _qs_16_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_17 = heads_17 != tails_17 & _qs_17_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_18 = heads_18 != tails_18 & _qs_18_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_19 = heads_19 != tails_19 & _qs_19_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_20 = heads_20 != tails_20 & _qs_20_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_21 = heads_21 != tails_21 & _qs_21_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire [21:0] to_q_oh_enc = can_to_q_0 ? 22'h1 : can_to_q_1 ? 22'h2 : can_to_q_2 ? 22'h4 : can_to_q_3 ? 22'h8 : can_to_q_4 ? 22'h10 : can_to_q_5 ? 22'h20 : can_to_q_6 ? 22'h40 : can_to_q_7 ? 22'h80 : can_to_q_8 ? 22'h100 : can_to_q_9 ? 22'h200 : can_to_q_10 ? 22'h400 : can_to_q_11 ? 22'h800 : can_to_q_12 ? 22'h1000 : can_to_q_13 ? 22'h2000 : can_to_q_14 ? 22'h4000 : can_to_q_15 ? 22'h8000 : can_to_q_16 ? 22'h10000 : can_to_q_17 ? 22'h20000 : can_to_q_18 ? 22'h40000 : can_to_q_19 ? 22'h80000 : can_to_q_20 ? 22'h100000 : {can_to_q_21, 21'h0}; // @[Mux.scala:50:70] wire _GEN_23 = can_to_q_0 \| can_to_q_1 \| can_to_q_2 \| can_to_q_3 \| can_to_q_4 \| can_to_q_5 \| can_to_q_6 \| can_to_q_7 \| can_to_q_8 \| can_to_q_9 \| can_to_q_10 \| can_to_q_11 \| can_to_q_12 \| can_to_q_13 \| can_to_q_14 \| can_to_q_15 \| can_to_q_16 \| can_to_q_17 \| can_to_q_18 \| can_to_q_19 \| can_to_q_20 \| can_to_q_21; // @[package.scala:81:59] wire [5:0] head = (to_q_oh_enc[0] ? heads_0 : 6'h0) \| (to_q_oh_enc[1] ? heads_1 : 6'h0) \| (to_q_oh_enc[2] ? heads_2 : 6'h0) \| (to_q_oh_enc[3] ? heads_3 : 6'h0) \| (to_q_oh_enc[4] ? heads_4 : 6'h0) \| (to_q_oh_enc[5] ? heads_5 : 6'h0) \| (to_q_oh_enc[6] ? heads_6 : 6'h0) \| (to_q_oh_enc[7] ? heads_7 : 6'h0) \| (to_q_oh_enc[8] ? heads_8 : 6'h0) \| (to_q_oh_enc[9] ? heads_9 : 6'h0) \| (to_q_oh_enc[10] ? heads_10 : 6'h0) \| (to_q_oh_enc[11] ? heads_11 : 6'h0) \| (to_q_oh_enc[12] ? heads_12 : 6'h0) \| (to_q_oh_enc[13] ? heads_13 : 6'h0) \| (to_q_oh_enc[14] ? heads_14 : 6'h0) \| (to_q_oh_enc[15] ? heads_15 : 6'h0) \| (to_q_oh_enc[16] ? heads_16 : 6'h0) \| (to_q_oh_enc[17] ? heads_17 : 6'h0) \| (to_q_oh_enc[18] ? heads_18 : 6'h0) \| (to_q_oh_enc[19] ? heads_19 : 6'h0) \| (to_q_oh_enc[20] ? heads_20 : 6'h0) \| (to_q_oh_enc[21] ? heads_21 : 6'h0); // @[OneHot.scala:83:30] wire _GEN_24 = _GEN_23 & to_q_oh_enc[0]; // @[OneHot.scala:83:30] wire _GEN_25 = _GEN_23 & to_q_oh_enc[1]; // @[OneHot.scala:83:30] wire _GEN_26 = _GEN_23 & to_q_oh_enc[2]; // @[OneHot.scala:83:30] wire _GEN_27 = _GEN_23 & to_q_oh_enc[3]; // @[OneHot.scala:83:30] wire _GEN_28 = _GEN_23 & to_q_oh_enc[4]; // @[OneHot.scala:83:30] wire _GEN_29 = _GEN_23 & to_q_oh_enc[5]; // @[OneHot.scala:83:30] wire _GEN_30 = _GEN_23 & to_q_oh_enc[6]; // @[OneHot.scala:83:30] wire _GEN_31 = _GEN_23 & to_q_oh_enc[7]; // @[OneHot.scala:83:30] wire _GEN_32 = _GEN_23 & to_q_oh_enc[8]; // @[OneHot.scala:83:30] wire _GEN_33 = _GEN_23 & to_q_oh_enc[9]; // @[OneHot.scala:83:30] wire _GEN_34 = _GEN_23 & to_q_oh_enc[10]; // @[OneHot.scala:83:30] wire _GEN_35 = _GEN_23 & to_q_oh_enc[11]; // @[OneHot.scala:83:30] wire _GEN_36 = _GEN_23 & to_q_oh_enc[12]; // @[OneHot.scala:83:30] wire _GEN_37 = _GEN_23 & to_q_oh_enc[13]; // @[OneHot.scala:83:30] wire _GEN_38 = _GEN_23 & to_q_oh_enc[14]; // @[OneHot.scala:83:30] wire _GEN_39 = _GEN_23 & to_q_oh_enc[15]; // @[OneHot.scala:83:30] wire _GEN_40 = _GEN_23 & to_q_oh_enc[16]; // @[OneHot.scala:83:30] wire _GEN_41 = _GEN_23 & to_q_oh_enc[17]; // @[OneHot.scala:83:30] wire _GEN_42 = _GEN_23 & to_q_oh_enc[18]; // @[OneHot.scala:83:30] wire _GEN_43 = _GEN_23 & to_q_oh_enc[19]; // @[OneHot.scala:83:30] wire _GEN_44 = _GEN_23 & to_q_oh_enc[20]; // @[OneHot.scala:83:30] wire _GEN_45 = _GEN_23 & to_q_oh_enc[21]; // @[OneHot.scala:83:30] wire [5:0] _tails_T_133 = _GEN[io_enq_0_bits_virt_channel_id] == ({1'h0, {1'h0, {1'h0, {1'h0, {2{_tails_T_68}}} \| {3{_tails_T_69}}} \| (_tails_T_76 ? 4'hB : 4'h0) \| {4{_tails_T_77}}} \| (_tails_T_78 ? 5'h13 : 5'h0) \| (_tails_T_79 ? 5'h17 : 5'h0) \| (_tails_T_80 ? 5'h1B : 5'h0) \| {5{_tails_T_81}}} \| (_tails_T_82 ? 6'h23 : 6'h0) \| (_tails_T_83 ? 6'h27 : 6'h0) \| (_tails_T_84 ? 6'h2B : 6'h0) \| (_tails_T_85 ? 6'h2F : 6'h0) \| (_tails_T_86 ? 6'h33 : 6'h0) \| (_tails_T_87 ? 6'h37 : 6'h0)) ? {_tails_T_82, {_tails_T_78, {_tails_T_76, _tails_T_69, 2'h0} \| (_tails_T_77 ? 4'hC : 4'h0)} \| (_tails_T_79 ? 5'h14 : 5'h0) \| (_tails_T_80 ? 5'h18 : 5'h0) \| (_tails_T_81 ? 5'h1C : 5'h0)} \| (_tails_T_83 ? 6'h24 : 6'h0) \| (_tails_T_84 ? 6'h28 : 6'h0) \| (_tails_T_85 ? 6'h2C : 6'h0) \| (_tails_T_86 ? 6'h30 : 6'h0) \| (_tails_T_87 ? 6'h34 : 6'h0) : _GEN[io_enq_0_bits_virt_channel_id] + 6'h1; // @[Mux.scala:30:73, :32:36] wire [14:0] _to_q_T_2 = {10'h0, to_q_oh_enc[21:17]} \| to_q_oh_enc[15:1]; // @[OneHot.scala:31:18, :32:28] wire [6:0] _to_q_T_4 = _to_q_T_2[14:8] \| _to_q_T_2[6:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] _to_q_T_6 = _to_q_T_4[6:4] \| _to_q_T_4[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire _to_q_T_8 = _to_q_T_6[2] \| _to_q_T_6[0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [4:0] to_q = {\|(to_q_oh_enc[21:16]), \|(_to_q_T_2[14:7]), \|(_to_q_T_4[6:3]), \|(_to_q_T_6[2:1]), _to_q_T_8}; // @[OneHot.scala:30:18, :32:{10,14,28}] wire [5:0] _heads_T_89 = head == ({1'h0, {1'h0, {1'h0, {1'h0, {2{to_q_oh_enc[2]}}} \| {3{to_q_oh_enc[3]}}} \| (to_q_oh_enc[10] ? 4'hB : 4'h0) \| {4{to_q_oh_enc[11]}}} \| (to_q_oh_enc[12] ? 5'h13 : 5'h0) \| (to_q_oh_enc[13] ? 5'h17 : 5'h0) \| (to_q_oh_enc[14] ? 5'h1B : 5'h0) \| {5{to_q_oh_enc[15]}}} \| (to_q_oh_enc[16] ? 6'h23 : 6'h0) \| (to_q_oh_enc[17] ? 6'h27 : 6'h0) \| (to_q_oh_enc[18] ? 6'h2B : 6'h0) \| (to_q_oh_enc[19] ? 6'h2F : 6'h0) \| (to_q_oh_enc[20] ? 6'h33 : 6'h0) \| (to_q_oh_enc[21] ? 6'h37 : 6'h0)) ? {to_q_oh_enc[16], {to_q_oh_enc[12], {to_q_oh_enc[10], to_q_oh_enc[3], 2'h0} \| (to_q_oh_enc[11] ? 4'hC : 4'h0)} \| (to_q_oh_enc[13] ? 5'h14 : 5'h0) \| (to_q_oh_enc[14] ? 5'h18 : 5'h0) \| (to_q_oh_enc[15] ? 5'h1C : 5'h0)} \| (to_q_oh_enc[17] ? 6'h24 : 6'h0) \| (to_q_oh_enc[18] ? 6'h28 : 6'h0) \| (to_q_oh_enc[19] ? 6'h2C : 6'h0) \| (to_q_oh_enc[20] ? 6'h30 : 6'h0) \| (to_q_oh_enc[21] ? 6'h34 : 6'h0) : head + 6'h1; // @[OneHot.scala:83:30] always @(posedge clock) begin // @[InputUnit.scala:49:7] if (reset) begin // @[InputUnit.scala:49:7] heads_0 <= 6'h0; // @[InputUnit.scala:86:24] heads_1 <= 6'h0; // @[InputUnit.scala:86:24] heads_2 <= 6'h0; // @[InputUnit.scala:86:24] heads_3 <= 6'h4; // @[InputUnit.scala:86:24] heads_4 <= 6'h0; // @[InputUnit.scala:86:24] heads_5 <= 6'h0; // @[InputUnit.scala:86:24] heads_6 <= 6'h0; // @[InputUnit.scala:86:24] heads_7 <= 6'h0; // @[InputUnit.scala:86:24] heads_8 <= 6'h0; // @[InputUnit.scala:86:24] heads_9 <= 6'h0; // @[InputUnit.scala:86:24] heads_10 <= 6'h8; // @[InputUnit.scala:86:24] heads_11 <= 6'hC; // @[InputUnit.scala:86:24] heads_12 <= 6'h10; // @[InputUnit.scala:86:24] heads_13 <= 6'h14; // @[InputUnit.scala:86:24] heads_14 <= 6'h18; // @[InputUnit.scala:86:24] heads_15 <= 6'h1C; // @[InputUnit.scala:86:24] heads_16 <= 6'h20; // @[InputUnit.scala:86:24] heads_17 <= 6'h24; // @[InputUnit.scala:86:24] heads_18 <= 6'h28; // @[InputUnit.scala:86:24] heads_19 <= 6'h2C; // @[InputUnit.scala:86:24] heads_20 <= 6'h30; // @[InputUnit.scala:86:24] heads_21 <= 6'h34; // @[InputUnit.scala:86:24] tails_0 <= 6'h0; // @[InputUnit.scala:87:24] tails_1 <= 6'h0; // @[InputUnit.scala:87:24] tails_2 <= 6'h0; // @[InputUnit.scala:87:24] tails_3 <= 6'h4; // @[InputUnit.scala:87:24] tails_4 <= 6'h0; // @[InputUnit.scala:87:24] tails_5 <= 6'h0; // @[InputUnit.scala:87:24] tails_6 <= 6'h0; // @[InputUnit.scala:87:24] tails_7 <= 6'h0; // @[InputUnit.scala:87:24] tails_8 <= 6'h0; // @[InputUnit.scala:87:24] tails_9 <= 6'h0; // @[InputUnit.scala:87:24] tails_10 <= 6'h8; // @[InputUnit.scala:87:24] tails_11 <= 6'hC; // @[InputUnit.scala:87:24] tails_12 <= 6'h10; // @[InputUnit.scala:87:24] tails_13 <= 6'h14; // @[InputUnit.scala:87:24] tails_14 <= 6'h18; // @[InputUnit.scala:87:24] tails_15 <= 6'h1C; // @[InputUnit.scala:87:24] tails_16 <= 6'h20; // @[InputUnit.scala:87:24] tails_17 <= 6'h24; // @[InputUnit.scala:87:24] tails_18 <= 6'h28; // @[InputUnit.scala:87:24] tails_19 <= 6'h2C; // @[InputUnit.scala:87:24] tails_20 <= 6'h30; // @[InputUnit.scala:87:24] tails_21 <= 6'h34; // @[InputUnit.scala:87:24] end else begin // @[InputUnit.scala:49:7] if (_GEN_23 & {to_q_oh_enc[21:16], \|(_to_q_T_2[14:7]), \|(_to_q_T_4[6:3]), \|(_to_q_T_6[2:1]), _to_q_T_8} == 10'h0) // @[OneHot.scala:30:18, :32:{10,14,28}] heads_0 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h1) // @[OneHot.scala:32:10] heads_1 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h2) // @[OneHot.scala:32:10] heads_2 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h3) // @[OneHot.scala:32:10] heads_3 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h4) // @[OneHot.scala:32:10] heads_4 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h5) // @[OneHot.scala:32:10] heads_5 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h6) // @[OneHot.scala:32:10] heads_6 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h7) // @[OneHot.scala:32:10] heads_7 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h8) // @[OneHot.scala:32:10] heads_8 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h9) // @[OneHot.scala:32:10] heads_9 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hA) // @[OneHot.scala:32:10] heads_10 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hB) // @[OneHot.scala:32:10] heads_11 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hC) // @[OneHot.scala:32:10] heads_12 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hD) // @[OneHot.scala:32:10] heads_13 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hE) // @[OneHot.scala:32:10] heads_14 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hF) // @[OneHot.scala:32:10] heads_15 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h10) // @[OneHot.scala:32:10] heads_16 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h11) // @[OneHot.scala:32:10] heads_17 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h12) // @[OneHot.scala:32:10] heads_18 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h13) // @[OneHot.scala:32:10] heads_19 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h14) // @[OneHot.scala:32:10] heads_20 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h15) // @[OneHot.scala:32:10] heads_21 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_0 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_1 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_2 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_3) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_3 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_4) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_4 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_5) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_5 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_6) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_6 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_7) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_7 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_8) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_8 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_9) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_9 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_10) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_10 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_11) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_11 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_12) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_12 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_13) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_13 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_14) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_14 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_15) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_15 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_16) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_16 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_17) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_17 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_18) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_18 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_19) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_19 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_20) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_20 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_21) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_21 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_20( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [4099:0] _c_sizes_set_T_1 = 4100'h0; // @[Monitor.scala:768:52] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79] wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77] wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35] wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35] wire [2055:0] c_sizes_set = 2056'h0; // @[Monitor.scala:741:34] wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34] wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34] wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 9'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 9'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 9'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_22 = _uncommonBits_T_22[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_23 = _uncommonBits_T_23[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_34 = _uncommonBits_T_34[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_35 = _uncommonBits_T_35[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_46 = _uncommonBits_T_46[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_47 = _uncommonBits_T_47[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_51 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_57 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_63 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_69 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 7'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 7'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 7'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 7'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 9'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 9'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 9'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1727 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1727; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1727; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [8:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1800 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1800; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1800; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1800; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [8:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [256:0] inflight; // @[Monitor.scala:614:27] reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [2055:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [256:0] a_set; // @[Monitor.scala:626:34] wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [2055:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [11:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [2055:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [2055:0] _a_size_lookup_T_6 = {2048'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [2055:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[2055:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [511:0] _GEN_3 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [511:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1653 = _T_1727 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1653 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1653 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1653 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [11:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1653 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [11:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [4099:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1653 ? _a_sizes_set_T_1[2055:0] : 2056'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [256:0] d_clr; // @[Monitor.scala:664:34] wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [2055:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1699 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1699 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1668 = _T_1800 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1668 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1668 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [4110:0] _d_sizes_clr_T_5 = 4111'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1668 ? _d_sizes_clr_T_5[2055:0] : 2056'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [256:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [1027:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [2055:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [2055:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [2055:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [256:0] inflight_1; // @[Monitor.scala:726:35] wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [2055:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [2055:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [2055:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [2055:0] _c_size_lookup_T_6 = {2048'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [2055:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[2055:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [256:0] d_clr_1; // @[Monitor.scala:774:34] wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [2055:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1771 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1771 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1753 = _T_1800 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1753 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1753 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [4110:0] _d_sizes_clr_T_11 = 4111'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1753 ? _d_sizes_clr_T_11[2055:0] : 2056'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113] wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [2055:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [2055:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File IOHandler.scala: package shuttle.dmem import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ class IOHandler(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Decoupled(new ShuttleDMemReq)) val resp = Decoupled(new ShuttleDMemResp) val mem_access = Decoupled(new TLBundleA(edge.bundle)) val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle))) val replay_next = Output(Bool()) val store_pending = Output(Bool()) }) def beatOffset(addr: UInt) = addr.extract(beatOffBits - 1, wordOffBits) def wordFromBeat(addr: UInt, dat: UInt) = { val shift = Cat(beatOffset(addr), 0.U((wordOffBits + log2Up(wordBytes)).W)) (dat >> shift)(wordBits - 1, 0) } val req = Reg(new ShuttleDMemReq) val grant_word = Reg(UInt(wordBits.W)) val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4) val state = RegInit(s_idle) io.req.ready := (state === s_idle) val loadgen = new LoadGen(req.size, req.signed, req.addr, grant_word, false.B, wordBytes) val a_source = id.U val a_address = req.addr val a_size = req.size val a_data = Fill(beatWords, req.data) val get = edge.Get(a_source, a_address, a_size)._2 val put = edge.Put(a_source, a_address, a_size, a_data)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(req.cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array( M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert(state === s_idle \|\| !isAMO(req.cmd)) (0.U).asTypeOf(new TLBundleA(edge.bundle)) } assert(state === s_idle \|\| req.cmd =/= M_XSC) io.mem_access.valid := (state === s_mem_access) io.mem_access.bits := Mux(isAMO(req.cmd), atomics, Mux(isRead(req.cmd), get, put)) io.replay_next := (state === s_mem_ack) \|\| io.resp.valid && !io.resp.ready io.resp.valid := (state === s_resp) io.resp.bits.tag := req.tag io.resp.bits.has_data := isRead(req.cmd) io.resp.bits.data := loadgen.data io.resp.bits.size := req.size io.store_pending := state =/= s_idle && isWrite(req.cmd) when (io.req.fire) { req := io.req.bits state := s_mem_access } when (io.mem_access.fire) { state := s_mem_ack } when (state === s_mem_ack && io.mem_ack.valid) { state := s_resp when (isRead(req.cmd)) { grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data) } } when (io.resp.fire) { state := s_idle } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out }	module IOHandler( // @[IOHandler.scala:13:7] input clock, // @[IOHandler.scala:13:7] input reset, // @[IOHandler.scala:13:7] output io_req_ready, // @[IOHandler.scala:14:14] input io_req_valid, // @[IOHandler.scala:14:14] input [39:0] io_req_bits_addr, // @[IOHandler.scala:14:14] input [6:0] io_req_bits_tag, // @[IOHandler.scala:14:14] input [4:0] io_req_bits_cmd, // @[IOHandler.scala:14:14] input [1:0] io_req_bits_size, // @[IOHandler.scala:14:14] input io_req_bits_signed, // @[IOHandler.scala:14:14] input [63:0] io_req_bits_data, // @[IOHandler.scala:14:14] input [7:0] io_req_bits_mask, // @[IOHandler.scala:14:14] input io_resp_ready, // @[IOHandler.scala:14:14] output io_resp_valid, // @[IOHandler.scala:14:14] output io_resp_bits_has_data, // @[IOHandler.scala:14:14] output [6:0] io_resp_bits_tag, // @[IOHandler.scala:14:14] output [63:0] io_resp_bits_data, // @[IOHandler.scala:14:14] output [1:0] io_resp_bits_size, // @[IOHandler.scala:14:14] input io_mem_access_ready, // @[IOHandler.scala:14:14] output io_mem_access_valid, // @[IOHandler.scala:14:14] output [2:0] io_mem_access_bits_opcode, // @[IOHandler.scala:14:14] output [2:0] io_mem_access_bits_param, // @[IOHandler.scala:14:14] output [3:0] io_mem_access_bits_size, // @[IOHandler.scala:14:14] output [2:0] io_mem_access_bits_source, // @[IOHandler.scala:14:14] output [31:0] io_mem_access_bits_address, // @[IOHandler.scala:14:14] output [7:0] io_mem_access_bits_mask, // @[IOHandler.scala:14:14] output [63:0] io_mem_access_bits_data, // @[IOHandler.scala:14:14] input io_mem_ack_valid, // @[IOHandler.scala:14:14] input [2:0] io_mem_ack_bits_opcode, // @[IOHandler.scala:14:14] input [1:0] io_mem_ack_bits_param, // @[IOHandler.scala:14:14] input [3:0] io_mem_ack_bits_size, // @[IOHandler.scala:14:14] input [2:0] io_mem_ack_bits_source, // @[IOHandler.scala:14:14] input [2:0] io_mem_ack_bits_sink, // @[IOHandler.scala:14:14] input io_mem_ack_bits_denied, // @[IOHandler.scala:14:14] input [63:0] io_mem_ack_bits_data, // @[IOHandler.scala:14:14] input io_mem_ack_bits_corrupt, // @[IOHandler.scala:14:14] output io_replay_next, // @[IOHandler.scala:14:14] output io_store_pending // @[IOHandler.scala:14:14] ); wire io_req_valid_0 = io_req_valid; // @[IOHandler.scala:13:7] wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[IOHandler.scala:13:7] wire [6:0] io_req_bits_tag_0 = io_req_bits_tag; // @[IOHandler.scala:13:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[IOHandler.scala:13:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[IOHandler.scala:13:7] wire io_req_bits_signed_0 = io_req_bits_signed; // @[IOHandler.scala:13:7] wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[IOHandler.scala:13:7] wire [7:0] io_req_bits_mask_0 = io_req_bits_mask; // @[IOHandler.scala:13:7] wire io_resp_ready_0 = io_resp_ready; // @[IOHandler.scala:13:7] wire io_mem_access_ready_0 = io_mem_access_ready; // @[IOHandler.scala:13:7] wire io_mem_ack_valid_0 = io_mem_ack_valid; // @[IOHandler.scala:13:7] wire [2:0] io_mem_ack_bits_opcode_0 = io_mem_ack_bits_opcode; // @[IOHandler.scala:13:7] wire [1:0] io_mem_ack_bits_param_0 = io_mem_ack_bits_param; // @[IOHandler.scala:13:7] wire [3:0] io_mem_ack_bits_size_0 = io_mem_ack_bits_size; // @[IOHandler.scala:13:7] wire [2:0] io_mem_ack_bits_source_0 = io_mem_ack_bits_source; // @[IOHandler.scala:13:7] wire [2:0] io_mem_ack_bits_sink_0 = io_mem_ack_bits_sink; // @[IOHandler.scala:13:7] wire io_mem_ack_bits_denied_0 = io_mem_ack_bits_denied; // @[IOHandler.scala:13:7] wire [63:0] io_mem_ack_bits_data_0 = io_mem_ack_bits_data; // @[IOHandler.scala:13:7] wire io_mem_ack_bits_corrupt_0 = io_mem_ack_bits_corrupt; // @[IOHandler.scala:13:7] wire io_mem_access_bits_corrupt = 1'h0; // @[IOHandler.scala:13:7] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire _put_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _put_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire _atomics_WIRE_corrupt = 1'h0; // @[IOHandler.scala:47:38] wire _atomics_legal_T_46 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_52 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_100 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_106 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_154 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_160 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_208 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_214 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_262 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_268 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_316 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_322 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_370 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_376 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_424 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_430 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_478 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_484 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_T_1_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _atomics_T_3_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _atomics_T_5_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _atomics_T_7_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _atomics_T_9_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _atomics_T_11_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _atomics_T_13_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _atomics_T_15_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire atomics_corrupt = 1'h0; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_42_corrupt = 1'h0; // @[IOHandler.scala:65:57] wire _io_mem_access_bits_T_43_corrupt = 1'h0; // @[IOHandler.scala:65:28] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire [6:0] grant_word_shift = 7'h0; // @[IOHandler.scala:26:20] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] get_source = 3'h4; // @[Edges.scala:460:17] wire [2:0] put_source = 3'h4; // @[Edges.scala:480:17] wire [2:0] atomics_a_source = 3'h4; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_source = 3'h4; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_source = 3'h4; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_source = 3'h4; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [2:0] atomics_a_4_source = 3'h4; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_source = 3'h4; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_source = 3'h4; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_source = 3'h4; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_source = 3'h4; // @[Edges.scala:517:17] wire [2:0] _io_mem_access_bits_T_42_source = 3'h4; // @[IOHandler.scala:65:57] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[IOHandler.scala:47:38] wire [2:0] _atomics_WIRE_param = 3'h0; // @[IOHandler.scala:47:38] wire [2:0] _atomics_WIRE_source = 3'h0; // @[IOHandler.scala:47:38] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] _io_mem_access_bits_T_42_param = 3'h0; // @[IOHandler.scala:65:57] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_54 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_55 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_56 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_57 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_108 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_109 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_110 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_111 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_162 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_163 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_164 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_165 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_216 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_217 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_270 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_271 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_272 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_273 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_324 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_325 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_326 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_327 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_378 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_379 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_380 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_381 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_432 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_433 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_434 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_435 = 1'h1; // @[Parameters.scala:684:29] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [63:0] get_data = 64'h0; // @[Edges.scala:460:17] wire [63:0] _atomics_WIRE_data = 64'h0; // @[IOHandler.scala:47:38] wire [7:0] _atomics_WIRE_mask = 8'h0; // @[IOHandler.scala:47:38] wire [31:0] _atomics_WIRE_address = 32'h0; // @[IOHandler.scala:47:38] wire [3:0] _atomics_WIRE_size = 4'h0; // @[IOHandler.scala:47:38] wire _io_req_ready_T; // @[IOHandler.scala:35:26] wire _io_resp_valid_T; // @[IOHandler.scala:68:27] wire _io_resp_bits_has_data_T_24; // @[Consts.scala:89:68] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_mem_access_valid_T; // @[IOHandler.scala:64:33] wire [2:0] _io_mem_access_bits_T_43_opcode; // @[IOHandler.scala:65:28] wire [2:0] _io_mem_access_bits_T_43_param; // @[IOHandler.scala:65:28] wire [3:0] _io_mem_access_bits_T_43_size; // @[IOHandler.scala:65:28] wire [2:0] _io_mem_access_bits_T_43_source; // @[IOHandler.scala:65:28] wire [31:0] _io_mem_access_bits_T_43_address; // @[IOHandler.scala:65:28] wire [7:0] _io_mem_access_bits_T_43_mask; // @[IOHandler.scala:65:28] wire [63:0] _io_mem_access_bits_T_43_data; // @[IOHandler.scala:65:28] wire [63:0] _grant_word_T = io_mem_ack_bits_data_0; // @[IOHandler.scala:13:7, :27:10] wire _io_replay_next_T_3; // @[IOHandler.scala:67:43] wire _io_store_pending_T_24; // @[IOHandler.scala:73:40] wire io_req_ready_0; // @[IOHandler.scala:13:7] wire io_resp_bits_has_data_0; // @[IOHandler.scala:13:7] wire [6:0] io_resp_bits_tag_0; // @[IOHandler.scala:13:7] wire [63:0] io_resp_bits_data_0; // @[IOHandler.scala:13:7] wire [1:0] io_resp_bits_size_0; // @[IOHandler.scala:13:7] wire io_resp_valid_0; // @[IOHandler.scala:13:7] wire [2:0] io_mem_access_bits_opcode_0; // @[IOHandler.scala:13:7] wire [2:0] io_mem_access_bits_param_0; // @[IOHandler.scala:13:7] wire [3:0] io_mem_access_bits_size_0; // @[IOHandler.scala:13:7] wire [2:0] io_mem_access_bits_source_0; // @[IOHandler.scala:13:7] wire [31:0] io_mem_access_bits_address_0; // @[IOHandler.scala:13:7] wire [7:0] io_mem_access_bits_mask_0; // @[IOHandler.scala:13:7] wire [63:0] io_mem_access_bits_data_0; // @[IOHandler.scala:13:7] wire io_mem_access_valid_0; // @[IOHandler.scala:13:7] wire io_replay_next_0; // @[IOHandler.scala:13:7] wire io_store_pending_0; // @[IOHandler.scala:13:7] reg [39:0] req_addr; // @[IOHandler.scala:30:16] wire [39:0] _get_legal_T_14 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _put_legal_T_14 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_4 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_58 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_112 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_166 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_220 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_274 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_328 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_382 = req_addr; // @[IOHandler.scala:30:16] wire [39:0] _atomics_legal_T_436 = req_addr; // @[IOHandler.scala:30:16] reg [6:0] req_tag; // @[IOHandler.scala:30:16] assign io_resp_bits_tag_0 = req_tag; // @[IOHandler.scala:13:7, :30:16] reg [4:0] req_cmd; // @[IOHandler.scala:30:16] reg [1:0] req_size; // @[IOHandler.scala:30:16] assign io_resp_bits_size_0 = req_size; // @[IOHandler.scala:13:7, :30:16] wire [1:0] size = req_size; // @[IOHandler.scala:30:16] reg req_signed; // @[IOHandler.scala:30:16] reg [63:0] req_data; // @[IOHandler.scala:30:16] wire [63:0] put_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_1_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_2_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_3_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_4_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_5_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_6_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_7_data = req_data; // @[IOHandler.scala:30:16] wire [63:0] atomics_a_8_data = req_data; // @[IOHandler.scala:30:16] reg [7:0] req_mask; // @[IOHandler.scala:30:16] reg [63:0] grant_word; // @[IOHandler.scala:31:23] reg [1:0] state; // @[IOHandler.scala:34:22] assign _io_req_ready_T = ~(\|state); // @[IOHandler.scala:34:22, :35:26] assign io_req_ready_0 = _io_req_ready_T; // @[IOHandler.scala:13:7, :35:26] wire [39:0] _GEN = {req_addr[39:14], req_addr[13:0] ^ 14'h3000}; // @[IOHandler.scala:30:16] wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31] assign _get_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31] assign _put_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_62 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'h9A012000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_0 = {req_addr[39:17], req_addr[16:0] ^ 17'h10000}; // @[IOHandler.scala:30:16] wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_63; // @[Parameters.scala:137:31] assign _put_legal_T_63 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_47; // @[Parameters.scala:137:31] assign _atomics_legal_T_47 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_101; // @[Parameters.scala:137:31] assign _atomics_legal_T_101 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_155; // @[Parameters.scala:137:31] assign _atomics_legal_T_155 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_209; // @[Parameters.scala:137:31] assign _atomics_legal_T_209 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_263; // @[Parameters.scala:137:31] assign _atomics_legal_T_263 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_317; // @[Parameters.scala:137:31] assign _atomics_legal_T_317 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_371; // @[Parameters.scala:137:31] assign _atomics_legal_T_371 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_425; // @[Parameters.scala:137:31] assign _atomics_legal_T_425 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_479; // @[Parameters.scala:137:31] assign _atomics_legal_T_479 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'h98013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {req_addr[39:26], req_addr[25:0] ^ 26'h2000000}; // @[IOHandler.scala:30:16] wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31] assign _get_legal_T_29 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46] wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {req_addr[39:28], req_addr[27:0] ^ 28'h8000000}; // @[IOHandler.scala:30:16] wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31] assign _get_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31] assign _get_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31] assign _put_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31] assign _put_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31] assign _atomics_legal_T_19 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31] assign _atomics_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_73; // @[Parameters.scala:137:31] assign _atomics_legal_T_73 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_78; // @[Parameters.scala:137:31] assign _atomics_legal_T_78 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_127; // @[Parameters.scala:137:31] assign _atomics_legal_T_127 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_132; // @[Parameters.scala:137:31] assign _atomics_legal_T_132 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_181; // @[Parameters.scala:137:31] assign _atomics_legal_T_181 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_186; // @[Parameters.scala:137:31] assign _atomics_legal_T_186 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_235; // @[Parameters.scala:137:31] assign _atomics_legal_T_235 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_240; // @[Parameters.scala:137:31] assign _atomics_legal_T_240 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_289; // @[Parameters.scala:137:31] assign _atomics_legal_T_289 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_294; // @[Parameters.scala:137:31] assign _atomics_legal_T_294 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_343; // @[Parameters.scala:137:31] assign _atomics_legal_T_343 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_348; // @[Parameters.scala:137:31] assign _atomics_legal_T_348 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_397; // @[Parameters.scala:137:31] assign _atomics_legal_T_397 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_402; // @[Parameters.scala:137:31] assign _atomics_legal_T_402 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_451; // @[Parameters.scala:137:31] assign _atomics_legal_T_451 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_456; // @[Parameters.scala:137:31] assign _atomics_legal_T_456 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46] wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46] wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {req_addr[39:29], req_addr[28:0] ^ 29'h10000000}; // @[IOHandler.scala:30:16] wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31] assign _get_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31] assign _put_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_29; // @[Parameters.scala:137:31] assign _atomics_legal_T_29 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_83; // @[Parameters.scala:137:31] assign _atomics_legal_T_83 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_137; // @[Parameters.scala:137:31] assign _atomics_legal_T_137 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_191; // @[Parameters.scala:137:31] assign _atomics_legal_T_191 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_245; // @[Parameters.scala:137:31] assign _atomics_legal_T_245 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_299; // @[Parameters.scala:137:31] assign _atomics_legal_T_299 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_353; // @[Parameters.scala:137:31] assign _atomics_legal_T_353 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_407; // @[Parameters.scala:137:31] assign _atomics_legal_T_407 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_461; // @[Parameters.scala:137:31] assign _atomics_legal_T_461 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46] wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] get_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] put_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_1_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_2_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_3_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_4_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_5_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_6_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_7_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [31:0] atomics_a_8_address = req_addr[31:0]; // @[IOHandler.scala:30:16] wire [39:0] _GEN_4 = {req_addr[39:32], req_addr[31:0] ^ 32'h80000000}; // @[IOHandler.scala:30:16] wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31] assign _get_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31] assign _put_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_34; // @[Parameters.scala:137:31] assign _atomics_legal_T_34 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_88; // @[Parameters.scala:137:31] assign _atomics_legal_T_88 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_142; // @[Parameters.scala:137:31] assign _atomics_legal_T_142 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_196; // @[Parameters.scala:137:31] assign _atomics_legal_T_196 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_250; // @[Parameters.scala:137:31] assign _atomics_legal_T_250 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_304; // @[Parameters.scala:137:31] assign _atomics_legal_T_304 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_358; // @[Parameters.scala:137:31] assign _atomics_legal_T_358 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_412; // @[Parameters.scala:137:31] assign _atomics_legal_T_412 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_466; // @[Parameters.scala:137:31] assign _atomics_legal_T_466 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46] wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_54 = _get_legal_T_18 \| _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_55 = _get_legal_T_54 \| _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_56 = _get_legal_T_55 \| _get_legal_T_33; // @[Parameters.scala:685:42] wire _get_legal_T_57 = _get_legal_T_56 \| _get_legal_T_38; // @[Parameters.scala:685:42] wire _get_legal_T_58 = _get_legal_T_57 \| _get_legal_T_43; // @[Parameters.scala:685:42] wire _get_legal_T_59 = _get_legal_T_58 \| _get_legal_T_48; // @[Parameters.scala:685:42] wire _get_legal_T_60 = _get_legal_T_59 \| _get_legal_T_53; // @[Parameters.scala:685:42] wire _get_legal_T_61 = _get_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_62 \| _get_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [7:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_5 = {2'h0, req_size}; // @[IOHandler.scala:30:16] assign get_size = _GEN_5; // @[Edges.scala:460:17, :463:15] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_5; // @[Edges.scala:463:15, :480:17] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [2:0] _GEN_6 = {1'h0, req_size}; // @[IOHandler.scala:30:16] wire [2:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_6; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_0_1 = &req_size; // @[IOHandler.scala:30:16] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = req_addr[2]; // @[IOHandler.scala:30:16] wire put_a_mask_sub_sub_bit = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_1 = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_2 = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_3 = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_4 = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_5 = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_6 = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_7 = req_addr[2]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_bit_8 = req_addr[2]; // @[IOHandler.scala:30:16] wire _io_resp_bits_data_shifted_T = req_addr[2]; // @[IOHandler.scala:30:16] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = req_addr[1]; // @[IOHandler.scala:30:16] wire put_a_mask_sub_bit = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_1 = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_2 = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_3 = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_4 = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_5 = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_6 = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_7 = req_addr[1]; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_bit_8 = req_addr[1]; // @[IOHandler.scala:30:16] wire _io_resp_bits_data_shifted_T_3 = req_addr[1]; // @[IOHandler.scala:30:16] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = req_addr[0]; // @[IOHandler.scala:30:16] wire put_a_mask_bit = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_1 = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_2 = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_3 = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_4 = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_5 = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_6 = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_7 = req_addr[0]; // @[IOHandler.scala:30:16] wire atomics_a_mask_bit_8 = req_addr[0]; // @[IOHandler.scala:30:16] wire _io_resp_bits_data_shifted_T_6 = req_addr[0]; // @[IOHandler.scala:30:16] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 \| _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 \| _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_69 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_7 = {req_addr[39:21], req_addr[20:0] ^ 21'h100000}; // @[IOHandler.scala:30:16] wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31] assign _atomics_legal_T_9 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_63; // @[Parameters.scala:137:31] assign _atomics_legal_T_63 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_117; // @[Parameters.scala:137:31] assign _atomics_legal_T_117 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_171; // @[Parameters.scala:137:31] assign _atomics_legal_T_171 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_225; // @[Parameters.scala:137:31] assign _atomics_legal_T_225 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_279; // @[Parameters.scala:137:31] assign _atomics_legal_T_279 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_333; // @[Parameters.scala:137:31] assign _atomics_legal_T_333 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_387; // @[Parameters.scala:137:31] assign _atomics_legal_T_387 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_441; // @[Parameters.scala:137:31] assign _atomics_legal_T_441 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_8 = {req_addr[39:26], req_addr[25:0] ^ 26'h2010000}; // @[IOHandler.scala:30:16] wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31] assign _put_legal_T_29 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31] assign _atomics_legal_T_14 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_68; // @[Parameters.scala:137:31] assign _atomics_legal_T_68 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_122; // @[Parameters.scala:137:31] assign _atomics_legal_T_122 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_176; // @[Parameters.scala:137:31] assign _atomics_legal_T_176 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_230; // @[Parameters.scala:137:31] assign _atomics_legal_T_230 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_284; // @[Parameters.scala:137:31] assign _atomics_legal_T_284 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_338; // @[Parameters.scala:137:31] assign _atomics_legal_T_338 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_392; // @[Parameters.scala:137:31] assign _atomics_legal_T_392 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_446; // @[Parameters.scala:137:31] assign _atomics_legal_T_446 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46] wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46] wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46] wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46] wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46] wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_54 = _put_legal_T_18 \| _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_55 = _put_legal_T_54 \| _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_56 = _put_legal_T_55 \| _put_legal_T_33; // @[Parameters.scala:685:42] wire _put_legal_T_57 = _put_legal_T_56 \| _put_legal_T_38; // @[Parameters.scala:685:42] wire _put_legal_T_58 = _put_legal_T_57 \| _put_legal_T_43; // @[Parameters.scala:685:42] wire _put_legal_T_59 = _put_legal_T_58 \| _put_legal_T_48; // @[Parameters.scala:685:42] wire _put_legal_T_60 = _put_legal_T_59 \| _put_legal_T_53; // @[Parameters.scala:685:42] wire _put_legal_T_61 = _put_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [40:0] _put_legal_T_64 = {1'h0, _put_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_65 = _put_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_66 = _put_legal_T_65; // @[Parameters.scala:137:46] wire _put_legal_T_67 = _put_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_70 = _put_legal_T_69 \| _put_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire put_legal = _put_legal_T_70; // @[Parameters.scala:686:26] wire [7:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [7:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_0_1 = &req_size; // @[IOHandler.scala:30:16] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 \| _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 \| _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46] wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46] wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46] wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46] wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46] wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_30 = {1'h0, _atomics_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_31 = _atomics_legal_T_30 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_32 = _atomics_legal_T_31; // @[Parameters.scala:137:46] wire _atomics_legal_T_33 = _atomics_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_35 = {1'h0, _atomics_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_36 = _atomics_legal_T_35 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36; // @[Parameters.scala:137:46] wire _atomics_legal_T_38 = _atomics_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_39 = _atomics_legal_T_8 \| _atomics_legal_T_13; // @[Parameters.scala:685:42] wire _atomics_legal_T_40 = _atomics_legal_T_39 \| _atomics_legal_T_18; // @[Parameters.scala:685:42] wire _atomics_legal_T_41 = _atomics_legal_T_40 \| _atomics_legal_T_23; // @[Parameters.scala:685:42] wire _atomics_legal_T_42 = _atomics_legal_T_41 \| _atomics_legal_T_28; // @[Parameters.scala:685:42] wire _atomics_legal_T_43 = _atomics_legal_T_42 \| _atomics_legal_T_33; // @[Parameters.scala:685:42] wire _atomics_legal_T_44 = _atomics_legal_T_43 \| _atomics_legal_T_38; // @[Parameters.scala:685:42] wire _atomics_legal_T_45 = _atomics_legal_T_44; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_53 = _atomics_legal_T_45; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_48 = {1'h0, _atomics_legal_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_49 = _atomics_legal_T_48 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_50 = _atomics_legal_T_49; // @[Parameters.scala:137:46] wire _atomics_legal_T_51 = _atomics_legal_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal = _atomics_legal_T_53; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_59 = {1'h0, _atomics_legal_T_58}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_60 = _atomics_legal_T_59 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_61 = _atomics_legal_T_60; // @[Parameters.scala:137:46] wire _atomics_legal_T_62 = _atomics_legal_T_61 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_64 = {1'h0, _atomics_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_65 = _atomics_legal_T_64 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65; // @[Parameters.scala:137:46] wire _atomics_legal_T_67 = _atomics_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_69 = {1'h0, _atomics_legal_T_68}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_70 = _atomics_legal_T_69 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70; // @[Parameters.scala:137:46] wire _atomics_legal_T_72 = _atomics_legal_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_74 = {1'h0, _atomics_legal_T_73}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_75 = _atomics_legal_T_74 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75; // @[Parameters.scala:137:46] wire _atomics_legal_T_77 = _atomics_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_79 = {1'h0, _atomics_legal_T_78}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_80 = _atomics_legal_T_79 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:137:46] wire _atomics_legal_T_82 = _atomics_legal_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46] wire _atomics_legal_T_87 = _atomics_legal_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_89 = {1'h0, _atomics_legal_T_88}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_90 = _atomics_legal_T_89 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_91 = _atomics_legal_T_90; // @[Parameters.scala:137:46] wire _atomics_legal_T_92 = _atomics_legal_T_91 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_93 = _atomics_legal_T_62 \| _atomics_legal_T_67; // @[Parameters.scala:685:42] wire _atomics_legal_T_94 = _atomics_legal_T_93 \| _atomics_legal_T_72; // @[Parameters.scala:685:42] wire _atomics_legal_T_95 = _atomics_legal_T_94 \| _atomics_legal_T_77; // @[Parameters.scala:685:42] wire _atomics_legal_T_96 = _atomics_legal_T_95 \| _atomics_legal_T_82; // @[Parameters.scala:685:42] wire _atomics_legal_T_97 = _atomics_legal_T_96 \| _atomics_legal_T_87; // @[Parameters.scala:685:42] wire _atomics_legal_T_98 = _atomics_legal_T_97 \| _atomics_legal_T_92; // @[Parameters.scala:685:42] wire _atomics_legal_T_99 = _atomics_legal_T_98; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_107 = _atomics_legal_T_99; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_102 = {1'h0, _atomics_legal_T_101}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_103 = _atomics_legal_T_102 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_104 = _atomics_legal_T_103; // @[Parameters.scala:137:46] wire _atomics_legal_T_105 = _atomics_legal_T_104 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_1 = _atomics_legal_T_107; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [7:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_1 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size_1 & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size_1 & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size_1 & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size_1 & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size_1 & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size_1 & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size_1 & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size_1 & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_113 = {1'h0, _atomics_legal_T_112}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_114 = _atomics_legal_T_113 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:137:46] wire _atomics_legal_T_116 = _atomics_legal_T_115 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_118 = {1'h0, _atomics_legal_T_117}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_119 = _atomics_legal_T_118 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_120 = _atomics_legal_T_119; // @[Parameters.scala:137:46] wire _atomics_legal_T_121 = _atomics_legal_T_120 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46] wire _atomics_legal_T_126 = _atomics_legal_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_128 = {1'h0, _atomics_legal_T_127}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_129 = _atomics_legal_T_128 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_130 = _atomics_legal_T_129; // @[Parameters.scala:137:46] wire _atomics_legal_T_131 = _atomics_legal_T_130 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_133 = {1'h0, _atomics_legal_T_132}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_134 = _atomics_legal_T_133 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_135 = _atomics_legal_T_134; // @[Parameters.scala:137:46] wire _atomics_legal_T_136 = _atomics_legal_T_135 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_138 = {1'h0, _atomics_legal_T_137}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_139 = _atomics_legal_T_138 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_140 = _atomics_legal_T_139; // @[Parameters.scala:137:46] wire _atomics_legal_T_141 = _atomics_legal_T_140 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_143 = {1'h0, _atomics_legal_T_142}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_144 = _atomics_legal_T_143 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_145 = _atomics_legal_T_144; // @[Parameters.scala:137:46] wire _atomics_legal_T_146 = _atomics_legal_T_145 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_147 = _atomics_legal_T_116 \| _atomics_legal_T_121; // @[Parameters.scala:685:42] wire _atomics_legal_T_148 = _atomics_legal_T_147 \| _atomics_legal_T_126; // @[Parameters.scala:685:42] wire _atomics_legal_T_149 = _atomics_legal_T_148 \| _atomics_legal_T_131; // @[Parameters.scala:685:42] wire _atomics_legal_T_150 = _atomics_legal_T_149 \| _atomics_legal_T_136; // @[Parameters.scala:685:42] wire _atomics_legal_T_151 = _atomics_legal_T_150 \| _atomics_legal_T_141; // @[Parameters.scala:685:42] wire _atomics_legal_T_152 = _atomics_legal_T_151 \| _atomics_legal_T_146; // @[Parameters.scala:685:42] wire _atomics_legal_T_153 = _atomics_legal_T_152; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_161 = _atomics_legal_T_153; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_156 = {1'h0, _atomics_legal_T_155}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_157 = _atomics_legal_T_156 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_158 = _atomics_legal_T_157; // @[Parameters.scala:137:46] wire _atomics_legal_T_159 = _atomics_legal_T_158 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_2 = _atomics_legal_T_161; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [7:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_2 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_2 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_2 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_2 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_2 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_2 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_2 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_2 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_2 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_167 = {1'h0, _atomics_legal_T_166}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_168 = _atomics_legal_T_167 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_169 = _atomics_legal_T_168; // @[Parameters.scala:137:46] wire _atomics_legal_T_170 = _atomics_legal_T_169 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_172 = {1'h0, _atomics_legal_T_171}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_173 = _atomics_legal_T_172 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_174 = _atomics_legal_T_173; // @[Parameters.scala:137:46] wire _atomics_legal_T_175 = _atomics_legal_T_174 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_177 = {1'h0, _atomics_legal_T_176}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_178 = _atomics_legal_T_177 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_179 = _atomics_legal_T_178; // @[Parameters.scala:137:46] wire _atomics_legal_T_180 = _atomics_legal_T_179 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_182 = {1'h0, _atomics_legal_T_181}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_183 = _atomics_legal_T_182 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_184 = _atomics_legal_T_183; // @[Parameters.scala:137:46] wire _atomics_legal_T_185 = _atomics_legal_T_184 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_187 = {1'h0, _atomics_legal_T_186}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_188 = _atomics_legal_T_187 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_189 = _atomics_legal_T_188; // @[Parameters.scala:137:46] wire _atomics_legal_T_190 = _atomics_legal_T_189 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_192 = {1'h0, _atomics_legal_T_191}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_193 = _atomics_legal_T_192 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_194 = _atomics_legal_T_193; // @[Parameters.scala:137:46] wire _atomics_legal_T_195 = _atomics_legal_T_194 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_197 = {1'h0, _atomics_legal_T_196}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_198 = _atomics_legal_T_197 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_199 = _atomics_legal_T_198; // @[Parameters.scala:137:46] wire _atomics_legal_T_200 = _atomics_legal_T_199 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_201 = _atomics_legal_T_170 \| _atomics_legal_T_175; // @[Parameters.scala:685:42] wire _atomics_legal_T_202 = _atomics_legal_T_201 \| _atomics_legal_T_180; // @[Parameters.scala:685:42] wire _atomics_legal_T_203 = _atomics_legal_T_202 \| _atomics_legal_T_185; // @[Parameters.scala:685:42] wire _atomics_legal_T_204 = _atomics_legal_T_203 \| _atomics_legal_T_190; // @[Parameters.scala:685:42] wire _atomics_legal_T_205 = _atomics_legal_T_204 \| _atomics_legal_T_195; // @[Parameters.scala:685:42] wire _atomics_legal_T_206 = _atomics_legal_T_205 \| _atomics_legal_T_200; // @[Parameters.scala:685:42] wire _atomics_legal_T_207 = _atomics_legal_T_206; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_215 = _atomics_legal_T_207; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_210 = {1'h0, _atomics_legal_T_209}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_211 = _atomics_legal_T_210 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_212 = _atomics_legal_T_211; // @[Parameters.scala:137:46] wire _atomics_legal_T_213 = _atomics_legal_T_212 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_3 = _atomics_legal_T_215; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [7:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_3 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_3 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_3 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_3 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_3 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_3 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_3 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_3 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_3 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_221 = {1'h0, _atomics_legal_T_220}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_222 = _atomics_legal_T_221 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_223 = _atomics_legal_T_222; // @[Parameters.scala:137:46] wire _atomics_legal_T_224 = _atomics_legal_T_223 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_226 = {1'h0, _atomics_legal_T_225}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_227 = _atomics_legal_T_226 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_228 = _atomics_legal_T_227; // @[Parameters.scala:137:46] wire _atomics_legal_T_229 = _atomics_legal_T_228 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_231 = {1'h0, _atomics_legal_T_230}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_232 = _atomics_legal_T_231 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:137:46] wire _atomics_legal_T_234 = _atomics_legal_T_233 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_236 = {1'h0, _atomics_legal_T_235}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_237 = _atomics_legal_T_236 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_238 = _atomics_legal_T_237; // @[Parameters.scala:137:46] wire _atomics_legal_T_239 = _atomics_legal_T_238 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_241 = {1'h0, _atomics_legal_T_240}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_242 = _atomics_legal_T_241 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_243 = _atomics_legal_T_242; // @[Parameters.scala:137:46] wire _atomics_legal_T_244 = _atomics_legal_T_243 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_246 = {1'h0, _atomics_legal_T_245}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_248 = _atomics_legal_T_247; // @[Parameters.scala:137:46] wire _atomics_legal_T_249 = _atomics_legal_T_248 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_251 = {1'h0, _atomics_legal_T_250}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_253 = _atomics_legal_T_252; // @[Parameters.scala:137:46] wire _atomics_legal_T_254 = _atomics_legal_T_253 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_255 = _atomics_legal_T_224 \| _atomics_legal_T_229; // @[Parameters.scala:685:42] wire _atomics_legal_T_256 = _atomics_legal_T_255 \| _atomics_legal_T_234; // @[Parameters.scala:685:42] wire _atomics_legal_T_257 = _atomics_legal_T_256 \| _atomics_legal_T_239; // @[Parameters.scala:685:42] wire _atomics_legal_T_258 = _atomics_legal_T_257 \| _atomics_legal_T_244; // @[Parameters.scala:685:42] wire _atomics_legal_T_259 = _atomics_legal_T_258 \| _atomics_legal_T_249; // @[Parameters.scala:685:42] wire _atomics_legal_T_260 = _atomics_legal_T_259 \| _atomics_legal_T_254; // @[Parameters.scala:685:42] wire _atomics_legal_T_261 = _atomics_legal_T_260; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_269 = _atomics_legal_T_261; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_264 = {1'h0, _atomics_legal_T_263}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_265 = _atomics_legal_T_264 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_266 = _atomics_legal_T_265; // @[Parameters.scala:137:46] wire _atomics_legal_T_267 = _atomics_legal_T_266 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_4 = _atomics_legal_T_269; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [7:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_4 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_4 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_4 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_4 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_4 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_4 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_4 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_4 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_4 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_275 = {1'h0, _atomics_legal_T_274}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_276 = _atomics_legal_T_275 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_277 = _atomics_legal_T_276; // @[Parameters.scala:137:46] wire _atomics_legal_T_278 = _atomics_legal_T_277 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_280 = {1'h0, _atomics_legal_T_279}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_281 = _atomics_legal_T_280 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_282 = _atomics_legal_T_281; // @[Parameters.scala:137:46] wire _atomics_legal_T_283 = _atomics_legal_T_282 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_285 = {1'h0, _atomics_legal_T_284}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_286 = _atomics_legal_T_285 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_287 = _atomics_legal_T_286; // @[Parameters.scala:137:46] wire _atomics_legal_T_288 = _atomics_legal_T_287 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_290 = {1'h0, _atomics_legal_T_289}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_291 = _atomics_legal_T_290 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_292 = _atomics_legal_T_291; // @[Parameters.scala:137:46] wire _atomics_legal_T_293 = _atomics_legal_T_292 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_295 = {1'h0, _atomics_legal_T_294}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_296 = _atomics_legal_T_295 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_297 = _atomics_legal_T_296; // @[Parameters.scala:137:46] wire _atomics_legal_T_298 = _atomics_legal_T_297 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_300 = {1'h0, _atomics_legal_T_299}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_301 = _atomics_legal_T_300 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_302 = _atomics_legal_T_301; // @[Parameters.scala:137:46] wire _atomics_legal_T_303 = _atomics_legal_T_302 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46] wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_309 = _atomics_legal_T_278 \| _atomics_legal_T_283; // @[Parameters.scala:685:42] wire _atomics_legal_T_310 = _atomics_legal_T_309 \| _atomics_legal_T_288; // @[Parameters.scala:685:42] wire _atomics_legal_T_311 = _atomics_legal_T_310 \| _atomics_legal_T_293; // @[Parameters.scala:685:42] wire _atomics_legal_T_312 = _atomics_legal_T_311 \| _atomics_legal_T_298; // @[Parameters.scala:685:42] wire _atomics_legal_T_313 = _atomics_legal_T_312 \| _atomics_legal_T_303; // @[Parameters.scala:685:42] wire _atomics_legal_T_314 = _atomics_legal_T_313 \| _atomics_legal_T_308; // @[Parameters.scala:685:42] wire _atomics_legal_T_315 = _atomics_legal_T_314; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_323 = _atomics_legal_T_315; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_318 = {1'h0, _atomics_legal_T_317}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_319 = _atomics_legal_T_318 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_320 = _atomics_legal_T_319; // @[Parameters.scala:137:46] wire _atomics_legal_T_321 = _atomics_legal_T_320 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_5 = _atomics_legal_T_323; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [7:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_5 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_5 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_5 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_5 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_5 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_5 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_5 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_5 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_5 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_329 = {1'h0, _atomics_legal_T_328}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_330 = _atomics_legal_T_329 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_331 = _atomics_legal_T_330; // @[Parameters.scala:137:46] wire _atomics_legal_T_332 = _atomics_legal_T_331 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_334 = {1'h0, _atomics_legal_T_333}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_335 = _atomics_legal_T_334 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_336 = _atomics_legal_T_335; // @[Parameters.scala:137:46] wire _atomics_legal_T_337 = _atomics_legal_T_336 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_339 = {1'h0, _atomics_legal_T_338}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_340 = _atomics_legal_T_339 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_341 = _atomics_legal_T_340; // @[Parameters.scala:137:46] wire _atomics_legal_T_342 = _atomics_legal_T_341 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_344 = {1'h0, _atomics_legal_T_343}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_345 = _atomics_legal_T_344 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_346 = _atomics_legal_T_345; // @[Parameters.scala:137:46] wire _atomics_legal_T_347 = _atomics_legal_T_346 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_349 = {1'h0, _atomics_legal_T_348}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_350 = _atomics_legal_T_349 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:137:46] wire _atomics_legal_T_352 = _atomics_legal_T_351 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_354 = {1'h0, _atomics_legal_T_353}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_355 = _atomics_legal_T_354 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_356 = _atomics_legal_T_355; // @[Parameters.scala:137:46] wire _atomics_legal_T_357 = _atomics_legal_T_356 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_359 = {1'h0, _atomics_legal_T_358}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_360 = _atomics_legal_T_359 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_361 = _atomics_legal_T_360; // @[Parameters.scala:137:46] wire _atomics_legal_T_362 = _atomics_legal_T_361 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_363 = _atomics_legal_T_332 \| _atomics_legal_T_337; // @[Parameters.scala:685:42] wire _atomics_legal_T_364 = _atomics_legal_T_363 \| _atomics_legal_T_342; // @[Parameters.scala:685:42] wire _atomics_legal_T_365 = _atomics_legal_T_364 \| _atomics_legal_T_347; // @[Parameters.scala:685:42] wire _atomics_legal_T_366 = _atomics_legal_T_365 \| _atomics_legal_T_352; // @[Parameters.scala:685:42] wire _atomics_legal_T_367 = _atomics_legal_T_366 \| _atomics_legal_T_357; // @[Parameters.scala:685:42] wire _atomics_legal_T_368 = _atomics_legal_T_367 \| _atomics_legal_T_362; // @[Parameters.scala:685:42] wire _atomics_legal_T_369 = _atomics_legal_T_368; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_377 = _atomics_legal_T_369; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_372 = {1'h0, _atomics_legal_T_371}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_373 = _atomics_legal_T_372 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_374 = _atomics_legal_T_373; // @[Parameters.scala:137:46] wire _atomics_legal_T_375 = _atomics_legal_T_374 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_6 = _atomics_legal_T_377; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [7:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_6 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_6 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_6 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_6 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_6 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_6 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_6 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_6 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_6 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_383 = {1'h0, _atomics_legal_T_382}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_384 = _atomics_legal_T_383 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_385 = _atomics_legal_T_384; // @[Parameters.scala:137:46] wire _atomics_legal_T_386 = _atomics_legal_T_385 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_388 = {1'h0, _atomics_legal_T_387}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_389 = _atomics_legal_T_388 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_390 = _atomics_legal_T_389; // @[Parameters.scala:137:46] wire _atomics_legal_T_391 = _atomics_legal_T_390 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_393 = {1'h0, _atomics_legal_T_392}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_394 = _atomics_legal_T_393 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_395 = _atomics_legal_T_394; // @[Parameters.scala:137:46] wire _atomics_legal_T_396 = _atomics_legal_T_395 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_398 = {1'h0, _atomics_legal_T_397}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_399 = _atomics_legal_T_398 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_400 = _atomics_legal_T_399; // @[Parameters.scala:137:46] wire _atomics_legal_T_401 = _atomics_legal_T_400 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_403 = {1'h0, _atomics_legal_T_402}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_404 = _atomics_legal_T_403 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_405 = _atomics_legal_T_404; // @[Parameters.scala:137:46] wire _atomics_legal_T_406 = _atomics_legal_T_405 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_408 = {1'h0, _atomics_legal_T_407}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_409 = _atomics_legal_T_408 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_410 = _atomics_legal_T_409; // @[Parameters.scala:137:46] wire _atomics_legal_T_411 = _atomics_legal_T_410 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_413 = {1'h0, _atomics_legal_T_412}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_414 = _atomics_legal_T_413 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_415 = _atomics_legal_T_414; // @[Parameters.scala:137:46] wire _atomics_legal_T_416 = _atomics_legal_T_415 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_417 = _atomics_legal_T_386 \| _atomics_legal_T_391; // @[Parameters.scala:685:42] wire _atomics_legal_T_418 = _atomics_legal_T_417 \| _atomics_legal_T_396; // @[Parameters.scala:685:42] wire _atomics_legal_T_419 = _atomics_legal_T_418 \| _atomics_legal_T_401; // @[Parameters.scala:685:42] wire _atomics_legal_T_420 = _atomics_legal_T_419 \| _atomics_legal_T_406; // @[Parameters.scala:685:42] wire _atomics_legal_T_421 = _atomics_legal_T_420 \| _atomics_legal_T_411; // @[Parameters.scala:685:42] wire _atomics_legal_T_422 = _atomics_legal_T_421 \| _atomics_legal_T_416; // @[Parameters.scala:685:42] wire _atomics_legal_T_423 = _atomics_legal_T_422; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_431 = _atomics_legal_T_423; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_426 = {1'h0, _atomics_legal_T_425}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_427 = _atomics_legal_T_426 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_428 = _atomics_legal_T_427; // @[Parameters.scala:137:46] wire _atomics_legal_T_429 = _atomics_legal_T_428 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_7 = _atomics_legal_T_431; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [7:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_7 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_7 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_7 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_7 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_7 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_7 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_7 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_7 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_7 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_437 = {1'h0, _atomics_legal_T_436}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_438 = _atomics_legal_T_437 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_439 = _atomics_legal_T_438; // @[Parameters.scala:137:46] wire _atomics_legal_T_440 = _atomics_legal_T_439 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_442 = {1'h0, _atomics_legal_T_441}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_443 = _atomics_legal_T_442 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_444 = _atomics_legal_T_443; // @[Parameters.scala:137:46] wire _atomics_legal_T_445 = _atomics_legal_T_444 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_447 = {1'h0, _atomics_legal_T_446}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_448 = _atomics_legal_T_447 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_449 = _atomics_legal_T_448; // @[Parameters.scala:137:46] wire _atomics_legal_T_450 = _atomics_legal_T_449 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_452 = {1'h0, _atomics_legal_T_451}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_453 = _atomics_legal_T_452 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_454 = _atomics_legal_T_453; // @[Parameters.scala:137:46] wire _atomics_legal_T_455 = _atomics_legal_T_454 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_457 = {1'h0, _atomics_legal_T_456}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_458 = _atomics_legal_T_457 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_459 = _atomics_legal_T_458; // @[Parameters.scala:137:46] wire _atomics_legal_T_460 = _atomics_legal_T_459 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_462 = {1'h0, _atomics_legal_T_461}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_463 = _atomics_legal_T_462 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_464 = _atomics_legal_T_463; // @[Parameters.scala:137:46] wire _atomics_legal_T_465 = _atomics_legal_T_464 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_467 = {1'h0, _atomics_legal_T_466}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_468 = _atomics_legal_T_467 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_469 = _atomics_legal_T_468; // @[Parameters.scala:137:46] wire _atomics_legal_T_470 = _atomics_legal_T_469 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_471 = _atomics_legal_T_440 \| _atomics_legal_T_445; // @[Parameters.scala:685:42] wire _atomics_legal_T_472 = _atomics_legal_T_471 \| _atomics_legal_T_450; // @[Parameters.scala:685:42] wire _atomics_legal_T_473 = _atomics_legal_T_472 \| _atomics_legal_T_455; // @[Parameters.scala:685:42] wire _atomics_legal_T_474 = _atomics_legal_T_473 \| _atomics_legal_T_460; // @[Parameters.scala:685:42] wire _atomics_legal_T_475 = _atomics_legal_T_474 \| _atomics_legal_T_465; // @[Parameters.scala:685:42] wire _atomics_legal_T_476 = _atomics_legal_T_475 \| _atomics_legal_T_470; // @[Parameters.scala:685:42] wire _atomics_legal_T_477 = _atomics_legal_T_476; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_485 = _atomics_legal_T_477; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_480 = {1'h0, _atomics_legal_T_479}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_481 = _atomics_legal_T_480 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_482 = _atomics_legal_T_481; // @[Parameters.scala:137:46] wire _atomics_legal_T_483 = _atomics_legal_T_482 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_8 = _atomics_legal_T_485; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [7:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_8 = &req_size; // @[IOHandler.scala:30:16] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_8 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_8 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_8 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_8 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_8 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_8 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_8 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_8 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire _T_17 = req_cmd == 5'h4; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T; // @[IOHandler.scala:47:67] assign _atomics_T = _T_17; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T; // @[package.scala:16:47] assign _io_mem_access_bits_T = _T_17; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_24; // @[package.scala:16:47] assign _io_mem_access_bits_T_24 = _T_17; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_7; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_7 = _T_17; // @[IOHandler.scala:47:67] wire _io_store_pending_T_6; // @[package.scala:16:47] assign _io_store_pending_T_6 = _T_17; // @[IOHandler.scala:47:67] wire [2:0] _GEN_9 = _atomics_T ? 3'h3 : 3'h0; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_1_opcode; // @[IOHandler.scala:47:67] assign _atomics_T_1_opcode = _GEN_9; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_1_param; // @[IOHandler.scala:47:67] assign _atomics_T_1_param = _GEN_9; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_1_source = {_atomics_T, 2'h0}; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 8'h0; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 64'h0; // @[IOHandler.scala:47:67] wire _T_18 = req_cmd == 5'h9; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_2; // @[IOHandler.scala:47:67] assign _atomics_T_2 = _T_18; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_1; // @[package.scala:16:47] assign _io_mem_access_bits_T_1 = _T_18; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_25; // @[package.scala:16:47] assign _io_mem_access_bits_T_25 = _T_18; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_8; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_8 = _T_18; // @[IOHandler.scala:47:67] wire _io_store_pending_T_7; // @[package.scala:16:47] assign _io_store_pending_T_7 = _T_18; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_3_source = _atomics_T_2 ? 3'h4 : _atomics_T_1_source; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[IOHandler.scala:47:67] wire _T_19 = req_cmd == 5'hA; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_4; // @[IOHandler.scala:47:67] assign _atomics_T_4 = _T_19; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_2; // @[package.scala:16:47] assign _io_mem_access_bits_T_2 = _T_19; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_26; // @[package.scala:16:47] assign _io_mem_access_bits_T_26 = _T_19; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_9; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_9 = _T_19; // @[IOHandler.scala:47:67] wire _io_store_pending_T_8; // @[package.scala:16:47] assign _io_store_pending_T_8 = _T_19; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_5_source = _atomics_T_4 ? 3'h4 : _atomics_T_3_source; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[IOHandler.scala:47:67] wire _T_20 = req_cmd == 5'hB; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_6; // @[IOHandler.scala:47:67] assign _atomics_T_6 = _T_20; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_3; // @[package.scala:16:47] assign _io_mem_access_bits_T_3 = _T_20; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_27; // @[package.scala:16:47] assign _io_mem_access_bits_T_27 = _T_20; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_10; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_10 = _T_20; // @[IOHandler.scala:47:67] wire _io_store_pending_T_9; // @[package.scala:16:47] assign _io_store_pending_T_9 = _T_20; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_7_source = _atomics_T_6 ? 3'h4 : _atomics_T_5_source; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[IOHandler.scala:47:67] wire _T_24 = req_cmd == 5'h8; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_8; // @[IOHandler.scala:47:67] assign _atomics_T_8 = _T_24; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_7; // @[package.scala:16:47] assign _io_mem_access_bits_T_7 = _T_24; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_31; // @[package.scala:16:47] assign _io_mem_access_bits_T_31 = _T_24; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_14; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_14 = _T_24; // @[IOHandler.scala:47:67] wire _io_store_pending_T_13; // @[package.scala:16:47] assign _io_store_pending_T_13 = _T_24; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_9_source = _atomics_T_8 ? 3'h4 : _atomics_T_7_source; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[IOHandler.scala:47:67] wire _T_25 = req_cmd == 5'hC; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_10; // @[IOHandler.scala:47:67] assign _atomics_T_10 = _T_25; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_8; // @[package.scala:16:47] assign _io_mem_access_bits_T_8 = _T_25; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_32; // @[package.scala:16:47] assign _io_mem_access_bits_T_32 = _T_25; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_15; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_15 = _T_25; // @[IOHandler.scala:47:67] wire _io_store_pending_T_14; // @[package.scala:16:47] assign _io_store_pending_T_14 = _T_25; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_11_source = _atomics_T_10 ? 3'h4 : _atomics_T_9_source; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[IOHandler.scala:47:67] wire _T_26 = req_cmd == 5'hD; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_12; // @[IOHandler.scala:47:67] assign _atomics_T_12 = _T_26; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_9; // @[package.scala:16:47] assign _io_mem_access_bits_T_9 = _T_26; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_33; // @[package.scala:16:47] assign _io_mem_access_bits_T_33 = _T_26; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_16; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_16 = _T_26; // @[IOHandler.scala:47:67] wire _io_store_pending_T_15; // @[package.scala:16:47] assign _io_store_pending_T_15 = _T_26; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_13_source = _atomics_T_12 ? 3'h4 : _atomics_T_11_source; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[IOHandler.scala:47:67] wire _T_27 = req_cmd == 5'hE; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_14; // @[IOHandler.scala:47:67] assign _atomics_T_14 = _T_27; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_10; // @[package.scala:16:47] assign _io_mem_access_bits_T_10 = _T_27; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_34; // @[package.scala:16:47] assign _io_mem_access_bits_T_34 = _T_27; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_17; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_17 = _T_27; // @[IOHandler.scala:47:67] wire _io_store_pending_T_16; // @[package.scala:16:47] assign _io_store_pending_T_16 = _T_27; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[IOHandler.scala:47:67] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[IOHandler.scala:47:67] wire [2:0] _atomics_T_15_source = _atomics_T_14 ? 3'h4 : _atomics_T_13_source; // @[IOHandler.scala:47:67] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[IOHandler.scala:47:67] wire [7:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[IOHandler.scala:47:67] wire [63:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[IOHandler.scala:47:67] wire _T_28 = req_cmd == 5'hF; // @[IOHandler.scala:30:16, :47:67] wire _atomics_T_16; // @[IOHandler.scala:47:67] assign _atomics_T_16 = _T_28; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_11; // @[package.scala:16:47] assign _io_mem_access_bits_T_11 = _T_28; // @[IOHandler.scala:47:67] wire _io_mem_access_bits_T_35; // @[package.scala:16:47] assign _io_mem_access_bits_T_35 = _T_28; // @[IOHandler.scala:47:67] wire _io_resp_bits_has_data_T_18; // @[package.scala:16:47] assign _io_resp_bits_has_data_T_18 = _T_28; // @[IOHandler.scala:47:67] wire _io_store_pending_T_17; // @[package.scala:16:47] assign _io_store_pending_T_17 = _T_28; // @[IOHandler.scala:47:67] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[IOHandler.scala:47:67] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[IOHandler.scala:47:67] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[IOHandler.scala:47:67] wire [2:0] atomics_source = _atomics_T_16 ? 3'h4 : _atomics_T_15_source; // @[IOHandler.scala:47:67] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[IOHandler.scala:47:67] wire [7:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[IOHandler.scala:47:67] wire [63:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[IOHandler.scala:47:67]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_115( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_203 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_337( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_81 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire \|\| io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) \|\| !io.outCol.fire) assert(!(state === 1.U) \|\| !io.inRow.fire) }	module PE_204( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File alu.scala: // This is borrowed from rocket, and modified to be hardcoded to 32b. // I will leave it as an excercise to the reader to make a parameterizable ALU // that doesn't generate extra hardware for 32b. I also didn't carefully // consider the function encodings. - Chris package sodor.stage3 import chisel3._ import chisel3.util._ import sodor.common._ import sodor.stage3.Constants._ object ALU { // TODO is this the optimal encoding? val SZ_ALU_FN = 4 val ALU_X = 0.U // TODO use a more optimal decode table, which uses "???" format val ALU_ADD = 0.U val ALU_SLL = 1.U val ALU_XOR = 4.U val ALU_OR = 6.U val ALU_AND = 7.U val ALU_SRL = 5.U val ALU_SUB = 10.U val ALU_SRA = 11.U val ALU_SLT = 12.U val ALU_SLTU = 14.U val ALU_COPY1= 8.U def isSub(cmd: UInt) = cmd(3) def isSLTU(cmd: UInt) = cmd(1) } import ALU._ class ALUIO(implicit val conf: SodorCoreParams) extends Bundle { val fn = Input(UInt(SZ_ALU_FN.W)) val in2 = Input(UInt(conf.xprlen.W)) val in1 = Input(UInt(conf.xprlen.W)) val out = Output(UInt(conf.xprlen.W)) val adder_out = Output(UInt(conf.xprlen.W)) } class ALU(implicit val conf: SodorCoreParams) extends Module { val io = IO(new ALUIO) val msb = conf.xprlen-1 // ADD, SUB val sum = io.in1 + Mux(isSub(io.fn), -io.in2, io.in2) // SLT, SLTU val less = Mux(io.in1(msb) === io.in2(msb), sum(msb), Mux(isSLTU(io.fn), io.in2(msb), io.in1(msb))) require(conf.xprlen == 32) // SLL, SRL, SRA val shamt = io.in2(4,0).asUInt val shin_r = io.in1(31,0) val shin = Mux(io.fn === ALU_SRL \|\| io.fn === ALU_SRA, shin_r, Reverse(shin_r)) val shout_r = (Cat(isSub(io.fn) & shin(msb), shin).asSInt >> shamt)(msb,0) val shout_l = Reverse(shout_r) val bitwise_logic = Mux(io.fn === ALU_AND, io.in1 & io.in2, Mux(io.fn === ALU_OR, io.in1 \| io.in2, Mux(io.fn === ALU_XOR, io.in1 ^ io.in2, io.in1))) // ALU_COPY1 val out_xpr_length = Mux(io.fn === ALU_ADD \|\| io.fn === ALU_SUB, sum, Mux(io.fn === ALU_SLT \|\| io.fn === ALU_SLTU, less, Mux(io.fn === ALU_SRL \|\| io.fn === ALU_SRA, shout_r, Mux(io.fn === ALU_SLL, shout_l, bitwise_logic)))) io.out := out_xpr_length(31,0).asUInt io.adder_out := sum }	module ALU( // @[alu.scala:43:7] input clock, // @[alu.scala:43:7] input reset, // @[alu.scala:43:7] input [3:0] io_fn, // @[alu.scala:45:14] input [31:0] io_in2, // @[alu.scala:45:14] input [31:0] io_in1, // @[alu.scala:45:14] output [31:0] io_out, // @[alu.scala:45:14] output [31:0] io_adder_out // @[alu.scala:45:14] ); wire [3:0] io_fn_0 = io_fn; // @[alu.scala:43:7] wire [31:0] io_in2_0 = io_in2; // @[alu.scala:43:7] wire [31:0] io_in1_0 = io_in1; // @[alu.scala:43:7] wire [31:0] _shin_T_4 = 32'hFFFF; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_1 = 32'hFFFF; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_3 = 32'hFFFF0000; // @[alu.scala:60:74] wire [31:0] _shin_T_9 = 32'hFFFF0000; // @[alu.scala:60:74] wire [31:0] _shout_l_T = 32'hFFFF0000; // @[alu.scala:62:24] wire [31:0] _shout_l_T_6 = 32'hFFFF0000; // @[alu.scala:62:24] wire [23:0] _shin_T_12 = 24'hFFFF; // @[alu.scala:60:74, :62:24] wire [23:0] _shout_l_T_9 = 24'hFFFF; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_13 = 32'hFFFF00; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_10 = 32'hFFFF00; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_14 = 32'hFF00FF; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_11 = 32'hFF00FF; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_19 = 32'hFF00FF00; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_16 = 32'hFF00FF00; // @[alu.scala:60:74, :62:24] wire [27:0] _shin_T_22 = 28'hFF00FF; // @[alu.scala:60:74, :62:24] wire [27:0] _shout_l_T_19 = 28'hFF00FF; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_23 = 32'hFF00FF0; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_20 = 32'hFF00FF0; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_24 = 32'hF0F0F0F; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_21 = 32'hF0F0F0F; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_29 = 32'hF0F0F0F0; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_26 = 32'hF0F0F0F0; // @[alu.scala:60:74, :62:24] wire [29:0] _shin_T_32 = 30'hF0F0F0F; // @[alu.scala:60:74, :62:24] wire [29:0] _shout_l_T_29 = 30'hF0F0F0F; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_33 = 32'h3C3C3C3C; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_30 = 32'h3C3C3C3C; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_34 = 32'h33333333; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_31 = 32'h33333333; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_39 = 32'hCCCCCCCC; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_36 = 32'hCCCCCCCC; // @[alu.scala:60:74, :62:24] wire [30:0] _shin_T_42 = 31'h33333333; // @[alu.scala:60:74, :62:24] wire [30:0] _shout_l_T_39 = 31'h33333333; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_43 = 32'h66666666; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_40 = 32'h66666666; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_44 = 32'h55555555; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_41 = 32'h55555555; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_49 = 32'hAAAAAAAA; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_46 = 32'hAAAAAAAA; // @[alu.scala:60:74, :62:24] wire [31:0] shin_r = io_in1_0; // @[alu.scala:43:7, :59:22] wire [31:0] _io_out_T; // @[alu.scala:77:27] wire [31:0] sum; // @[alu.scala:50:20] wire [31:0] io_out_0; // @[alu.scala:43:7] wire [31:0] io_adder_out_0; // @[alu.scala:43:7] wire _sum_T = io_fn_0[3]; // @[alu.scala:30:29, :43:7] wire _shout_r_T = io_fn_0[3]; // @[alu.scala:30:29, :43:7] wire [32:0] _sum_T_1 = 33'h0 - {1'h0, io_in2_0}; // @[alu.scala:43:7, :50:40] wire [31:0] _sum_T_2 = _sum_T_1[31:0]; // @[alu.scala:50:40] wire [31:0] _sum_T_3 = _sum_T ? _sum_T_2 : io_in2_0; // @[alu.scala:30:29, :43:7, :50:{25,40}] wire [32:0] _sum_T_4 = {1'h0, io_in1_0} + {1'h0, _sum_T_3}; // @[alu.scala:43:7, :50:{20,25,40}] assign sum = _sum_T_4[31:0]; // @[alu.scala:50:20] assign io_adder_out_0 = sum; // @[alu.scala:43:7, :50:20] wire _less_T = io_in1_0[31]; // @[alu.scala:43:7, :53:26] wire _less_T_6 = io_in1_0[31]; // @[alu.scala:43:7, :53:26, :54:53] wire _less_T_1 = io_in2_0[31]; // @[alu.scala:43:7, :53:42] wire _less_T_5 = io_in2_0[31]; // @[alu.scala:43:7, :53:42, :54:40] wire _less_T_2 = _less_T == _less_T_1; // @[alu.scala:53:{26,32,42}] wire _less_T_3 = sum[31]; // @[alu.scala:50:20, :53:52] wire _less_T_4 = io_fn_0[1]; // @[alu.scala:31:30, :43:7] wire _less_T_7 = _less_T_4 ? _less_T_5 : _less_T_6; // @[alu.scala:31:30, :54:{18,40,53}] wire less = _less_T_2 ? _less_T_3 : _less_T_7; // @[alu.scala:53:{19,32,52}, :54:18] wire [4:0] shamt = io_in2_0[4:0]; // @[alu.scala:43:7, :58:21] wire _GEN = io_fn_0 == 4'h5; // @[alu.scala:43:7, :60:24] wire _shin_T; // @[alu.scala:60:24] assign _shin_T = _GEN; // @[alu.scala:60:24] wire _out_xpr_length_T_6; // @[alu.scala:73:15] assign _out_xpr_length_T_6 = _GEN; // @[alu.scala:60:24, :73:15] wire _GEN_0 = io_fn_0 == 4'hB; // @[alu.scala:43:7, :60:46] wire _shin_T_1; // @[alu.scala:60:46] assign _shin_T_1 = _GEN_0; // @[alu.scala:60:46] wire _out_xpr_length_T_7; // @[alu.scala:73:36] assign _out_xpr_length_T_7 = _GEN_0; // @[alu.scala:60:46, :73:36] wire _shin_T_2 = _shin_T \| _shin_T_1; // @[alu.scala:60:{24,37,46}] wire [15:0] _shin_T_5 = shin_r[31:16]; // @[alu.scala:59:22, :60:74] wire [31:0] _shin_T_6 = {16'h0, _shin_T_5}; // @[alu.scala:60:74] wire [15:0] _shin_T_7 = shin_r[15:0]; // @[alu.scala:59:22, :60:74] wire [31:0] _shin_T_8 = {_shin_T_7, 16'h0}; // @[alu.scala:60:74] wire [31:0] _shin_T_10 = _shin_T_8 & 32'hFFFF0000; // @[alu.scala:60:74] wire [31:0] _shin_T_11 = _shin_T_6 \| _shin_T_10; // @[alu.scala:60:74] wire [23:0] _shin_T_15 = _shin_T_11[31:8]; // @[alu.scala:60:74] wire [31:0] _shin_T_16 = {8'h0, _shin_T_15 & 24'hFF00FF}; // @[alu.scala:60:74, :62:24] wire [23:0] _shin_T_17 = _shin_T_11[23:0]; // @[alu.scala:60:74] wire [31:0] _shin_T_18 = {_shin_T_17, 8'h0}; // @[alu.scala:60:74] wire [31:0] _shin_T_20 = _shin_T_18 & 32'hFF00FF00; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_21 = _shin_T_16 \| _shin_T_20; // @[alu.scala:60:74] wire [27:0] _shin_T_25 = _shin_T_21[31:4]; // @[alu.scala:60:74] wire [31:0] _shin_T_26 = {4'h0, _shin_T_25 & 28'hF0F0F0F}; // @[alu.scala:60:74, :62:24] wire [27:0] _shin_T_27 = _shin_T_21[27:0]; // @[alu.scala:60:74] wire [31:0] _shin_T_28 = {_shin_T_27, 4'h0}; // @[alu.scala:60:74] wire [31:0] _shin_T_30 = _shin_T_28 & 32'hF0F0F0F0; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_31 = _shin_T_26 \| _shin_T_30; // @[alu.scala:60:74] wire [29:0] _shin_T_35 = _shin_T_31[31:2]; // @[alu.scala:60:74] wire [31:0] _shin_T_36 = {2'h0, _shin_T_35 & 30'h33333333}; // @[alu.scala:60:74, :62:24] wire [29:0] _shin_T_37 = _shin_T_31[29:0]; // @[alu.scala:60:74] wire [31:0] _shin_T_38 = {_shin_T_37, 2'h0}; // @[alu.scala:60:74] wire [31:0] _shin_T_40 = _shin_T_38 & 32'hCCCCCCCC; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_41 = _shin_T_36 \| _shin_T_40; // @[alu.scala:60:74] wire [30:0] _shin_T_45 = _shin_T_41[31:1]; // @[alu.scala:60:74] wire [31:0] _shin_T_46 = {1'h0, _shin_T_45 & 31'h55555555}; // @[alu.scala:50:40, :60:74, :62:24] wire [30:0] _shin_T_47 = _shin_T_41[30:0]; // @[alu.scala:60:74] wire [31:0] _shin_T_48 = {_shin_T_47, 1'h0}; // @[alu.scala:50:40, :60:74] wire [31:0] _shin_T_50 = _shin_T_48 & 32'hAAAAAAAA; // @[alu.scala:60:74, :62:24] wire [31:0] _shin_T_51 = _shin_T_46 \| _shin_T_50; // @[alu.scala:60:74] wire [31:0] shin = _shin_T_2 ? shin_r : _shin_T_51; // @[alu.scala:59:22, :60:{17,37,74}] wire _shout_r_T_1 = shin[31]; // @[alu.scala:60:17, :61:41] wire _shout_r_T_2 = _shout_r_T & _shout_r_T_1; // @[alu.scala:30:29, :61:{35,41}] wire [32:0] _shout_r_T_3 = {_shout_r_T_2, shin}; // @[alu.scala:60:17, :61:{21,35}] wire [32:0] _shout_r_T_4 = _shout_r_T_3; // @[alu.scala:61:{21,54}] wire [32:0] _shout_r_T_5 = $signed($signed(_shout_r_T_4) >>> shamt); // @[alu.scala:58:21, :61:{54,61}] wire [31:0] shout_r = _shout_r_T_5[31:0]; // @[alu.scala:61:{61,70}] wire [15:0] _shout_l_T_2 = shout_r[31:16]; // @[alu.scala:61:70, :62:24] wire [31:0] _shout_l_T_3 = {16'h0, _shout_l_T_2}; // @[alu.scala:60:74, :62:24] wire [15:0] _shout_l_T_4 = shout_r[15:0]; // @[alu.scala:61:70, :62:24] wire [31:0] _shout_l_T_5 = {_shout_l_T_4, 16'h0}; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_7 = _shout_l_T_5 & 32'hFFFF0000; // @[alu.scala:62:24] wire [31:0] _shout_l_T_8 = _shout_l_T_3 \| _shout_l_T_7; // @[alu.scala:62:24] wire [23:0] _shout_l_T_12 = _shout_l_T_8[31:8]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_13 = {8'h0, _shout_l_T_12 & 24'hFF00FF}; // @[alu.scala:60:74, :62:24] wire [23:0] _shout_l_T_14 = _shout_l_T_8[23:0]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_15 = {_shout_l_T_14, 8'h0}; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_17 = _shout_l_T_15 & 32'hFF00FF00; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_18 = _shout_l_T_13 \| _shout_l_T_17; // @[alu.scala:62:24] wire [27:0] _shout_l_T_22 = _shout_l_T_18[31:4]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_23 = {4'h0, _shout_l_T_22 & 28'hF0F0F0F}; // @[alu.scala:60:74, :62:24] wire [27:0] _shout_l_T_24 = _shout_l_T_18[27:0]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_25 = {_shout_l_T_24, 4'h0}; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_27 = _shout_l_T_25 & 32'hF0F0F0F0; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_28 = _shout_l_T_23 \| _shout_l_T_27; // @[alu.scala:62:24] wire [29:0] _shout_l_T_32 = _shout_l_T_28[31:2]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_33 = {2'h0, _shout_l_T_32 & 30'h33333333}; // @[alu.scala:60:74, :62:24] wire [29:0] _shout_l_T_34 = _shout_l_T_28[29:0]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_35 = {_shout_l_T_34, 2'h0}; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_37 = _shout_l_T_35 & 32'hCCCCCCCC; // @[alu.scala:60:74, :62:24] wire [31:0] _shout_l_T_38 = _shout_l_T_33 \| _shout_l_T_37; // @[alu.scala:62:24] wire [30:0] _shout_l_T_42 = _shout_l_T_38[31:1]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_43 = {1'h0, _shout_l_T_42 & 31'h55555555}; // @[alu.scala:50:40, :60:74, :62:24] wire [30:0] _shout_l_T_44 = _shout_l_T_38[30:0]; // @[alu.scala:62:24] wire [31:0] _shout_l_T_45 = {_shout_l_T_44, 1'h0}; // @[alu.scala:50:40, :62:24] wire [31:0] _shout_l_T_47 = _shout_l_T_45 & 32'hAAAAAAAA; // @[alu.scala:60:74, :62:24] wire [31:0] shout_l = _shout_l_T_43 \| _shout_l_T_47; // @[alu.scala:62:24] wire _bitwise_logic_T = io_fn_0 == 4'h7; // @[alu.scala:43:7, :65:15] wire [31:0] _bitwise_logic_T_1 = io_in1_0 & io_in2_0; // @[alu.scala:43:7, :65:35] wire _bitwise_logic_T_2 = io_fn_0 == 4'h6; // @[alu.scala:43:7, :66:15] wire [31:0] _bitwise_logic_T_3 = io_in1_0 \| io_in2_0; // @[alu.scala:43:7, :66:35] wire _bitwise_logic_T_4 = io_fn_0 == 4'h4; // @[alu.scala:43:7, :67:15] wire [31:0] _bitwise_logic_T_5 = io_in1_0 ^ io_in2_0; // @[alu.scala:43:7, :67:35] wire [31:0] _bitwise_logic_T_6 = _bitwise_logic_T_4 ? _bitwise_logic_T_5 : io_in1_0; // @[alu.scala:43:7, :67:{8,15,35}] wire [31:0] _bitwise_logic_T_7 = _bitwise_logic_T_2 ? _bitwise_logic_T_3 : _bitwise_logic_T_6; // @[alu.scala:66:{8,15,35}, :67:8] wire [31:0] bitwise_logic = _bitwise_logic_T ? _bitwise_logic_T_1 : _bitwise_logic_T_7; // @[alu.scala:65:{8,15,35}, :66:8] wire _out_xpr_length_T = io_fn_0 == 4'h0; // @[alu.scala:43:7, :60:74, :71:15] wire _out_xpr_length_T_1 = io_fn_0 == 4'hA; // @[alu.scala:43:7, :71:36] wire _out_xpr_length_T_2 = _out_xpr_length_T \| _out_xpr_length_T_1; // @[alu.scala:71:{15,27,36}] wire _out_xpr_length_T_3 = io_fn_0 == 4'hC; // @[alu.scala:43:7, :72:15] wire _out_xpr_length_T_4 = io_fn_0 == 4'hE; // @[alu.scala:43:7, :72:36] wire _out_xpr_length_T_5 = _out_xpr_length_T_3 \| _out_xpr_length_T_4; // @[alu.scala:72:{15,27,36}] wire _out_xpr_length_T_8 = _out_xpr_length_T_6 \| _out_xpr_length_T_7; // @[alu.scala:73:{15,27,36}] wire _out_xpr_length_T_9 = io_fn_0 == 4'h1; // @[alu.scala:43:7, :74:15] wire [31:0] _out_xpr_length_T_10 = _out_xpr_length_T_9 ? shout_l : bitwise_logic; // @[alu.scala:62:24, :65:8, :74:{8,15}] wire [31:0] _out_xpr_length_T_11 = _out_xpr_length_T_8 ? shout_r : _out_xpr_length_T_10; // @[alu.scala:61:70, :73:{8,27}, :74:8] wire [31:0] _out_xpr_length_T_12 = _out_xpr_length_T_5 ? {31'h0, less} : _out_xpr_length_T_11; // @[alu.scala:53:19, :72:{8,27}, :73:8] wire [31:0] out_xpr_length = _out_xpr_length_T_2 ? sum : _out_xpr_length_T_12; // @[alu.scala:50:20, :71:{8,27}, :72:8] assign _io_out_T = out_xpr_length; // @[alu.scala:71:8, :77:27] assign io_out_0 = _io_out_T; // @[alu.scala:43:7, :77:27] assign io_out = io_out_0; // @[alu.scala:43:7] assign io_adder_out = io_adder_out_0; // @[alu.scala:43:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File FunctionalUnit.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ import saturn.insns.{VectorInstruction} abstract class FunctionalUnitIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val iss = new Bundle { val valid = Input(Bool()) val op = Input(new ExecuteMicroOp) val ready = Output(Bool()) } val scalar_write = Decoupled(new ScalarWrite) val set_vxsat = Output(Bool()) val set_fflags = Output(Valid(UInt(5.W))) } class PipelinedFunctionalUnitIO(depth: Int)(implicit p: Parameters) extends FunctionalUnitIO { val write = Valid(new VectorWrite(dLen)) val pipe = Input(Vec(depth, Valid(new ExecuteMicroOp))) val pipe0_stall = Output(Bool()) } class IterativeFunctionalUnitIO(implicit p: Parameters) extends FunctionalUnitIO { val write = Decoupled(new VectorWrite(dLen)) val hazard = Output(Valid(new PipeHazard(10))) val acc = Output(Bool()) val tail = Output(Bool()) val busy = Output(Bool()) } trait FunctionalUnitFactory { def insns: Seq[VectorInstruction] def generate(implicit p: Parameters): FunctionalUnit } abstract class FunctionalUnit(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io: FunctionalUnitIO } abstract class PipelinedFunctionalUnit(val depth: Int)(implicit p: Parameters) extends FunctionalUnit()(p) { val io = IO(new PipelinedFunctionalUnitIO(depth)) require (depth > 0) def narrow2_expand(bits: Seq[UInt], eew: UInt, upper: Bool, sext: Bool): Vec[UInt] = { val narrow_eew = (0 until 3).map { eew => Wire(Vec(dLenB >> (eew + 1), UInt((16 << eew).W))) } for (eew <- 0 until 3) { val in_vec = bits.grouped(1 << eew).map(g => VecInit(g).asUInt).toSeq for (i <- 0 until dLenB >> (eew + 1)) { val lo = Mux(upper, in_vec(i + (dLenB >> (eew + 1))), in_vec(i)) val hi = Fill(16 << eew, lo((8 << eew)-1) && sext) narrow_eew(eew)(i) := Cat(hi, lo) } } VecInit(narrow_eew.map(_.asUInt))(eew).asTypeOf(Vec(dLenB, UInt(8.W))) } } abstract class IterativeFunctionalUnit(implicit p: Parameters) extends FunctionalUnit()(p) { val io = IO(new IterativeFunctionalUnitIO) val valid = RegInit(false.B) val op = Reg(new ExecuteMicroOp) val last = Wire(Bool()) io.busy := valid io.hazard.bits.latency := DontCare when (io.iss.valid && io.iss.ready) { valid := true.B op := io.iss.op } .elsewhen (last) { valid := false.B } } File Bundles.scala: package saturn.common import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ class VectorMemMacroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val debug_id = UInt(debugIdSz.W) val base_offset = UInt(pgIdxBits.W) val page = UInt((paddrBits - pgIdxBits).W) val stride = UInt(pgIdxBits.W) val segstart = UInt(3.W) val segend = UInt(3.W) val vstart = UInt(log2Ceil(maxVLMax).W) val vl = UInt((1+log2Ceil(maxVLMax)).W) val mop = UInt(2.W) val vm = Bool() val nf = UInt(3.W) val idx_size = UInt(2.W) val elem_size = UInt(2.W) val whole_reg = Bool() val store = Bool() val fast_sg = Bool() def indexed = !mop.isOneOf(mopUnit, mopStrided) def seg_nf = Mux(whole_reg, 0.U, nf) def wr_nf = Mux(whole_reg, nf, 0.U) } class VectorIssueInst(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val pc = UInt(vaddrBitsExtended.W) val bits = UInt(32.W) val vconfig = new VConfig val vstart = UInt(log2Ceil(maxVLMax).W) val segstart = UInt(3.W) val segend = UInt(3.W) val rs1_data = UInt(xLen.W) val rs2_data = UInt(xLen.W) val page = UInt((paddrBits - pgIdxBits).W) val vat = UInt(vParams.vatSz.W) val rm = UInt(3.W) val emul = UInt(2.W) val fast_sg = Bool() val debug_id = UInt(debugIdSz.W) val mop = UInt(2.W) // stored separately from bits since dispatch may need to set this def opcode = bits(6,0) def store = opcode(5) def mem_idx_size = bits(13,12) def mem_elem_size = Mux(mop(0), vconfig.vtype.vsew, bits(13,12)) def vm = bits(25) def orig_mop = bits(27,26) def umop = bits(24,20) def nf = bits(31,29) def wr = orig_mop === mopUnit && umop === lumopWhole def seg_nf = Mux(wr, 0.U, nf) def wr_nf = Mux(wr, nf, 0.U) def vmu = opcode.isOneOf(opcLoad, opcStore) def rs1 = bits(19,15) def rs2 = bits(24,20) def rd = bits(11,7) def may_write_v0 = rd === 0.U && opcode =/= opcStore def funct3 = bits(14,12) def imm5 = bits(19,15) def imm5_sext = Cat(Fill(59, imm5(4)), imm5) def funct6 = bits(31,26) def writes_xrf = !vmu && ((funct3 === OPMVV && opmf6 === OPMFunct6.wrxunary0) \|\| (funct3 === OPFVV && opff6 === OPFFunct6.wrfunary0)) def writes_frf = !vmu && (funct3 === OPFVV) def isOpi = funct3.isOneOf(OPIVV, OPIVI, OPIVX) def isOpm = funct3.isOneOf(OPMVV, OPMVX) def isOpf = funct3.isOneOf(OPFVV, OPFVF) def opmf6 = Mux(isOpm, OPMFunct6(funct6), OPMFunct6.illegal) def opif6 = Mux(isOpi, OPIFunct6(funct6), OPIFunct6.illegal) def opff6 = Mux(isOpf, OPFFunct6(funct6), OPFFunct6.illegal) } class BackendIssueInst(implicit p: Parameters) extends VectorIssueInst()(p) { val reduction = Bool() // accumulates into vd[0] val scalar_to_vd0 = Bool() // mv scalar to vd[0] val wide_vd = Bool() // vd reads/writes at 2xSEW val wide_vs2 = Bool() // vs2 reads at 2xSEW val writes_mask = Bool() // writes dest as a mask val reads_vs1_mask = Bool() // vs1 read as mask val reads_vs2_mask = Bool() // vs2 read as mask val rs1_is_rs2 = Bool() val nf_log2 = UInt(2.W) val renv1 = Bool() val renv2 = Bool() val renvd = Bool() val renvm = Bool() val wvd = Bool() } class IssueQueueInst(nSeqs: Int)(implicit p: Parameters) extends BackendIssueInst()(p) { val seq = UInt(nSeqs.W) } class VectorWrite(writeBits: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val eg = UInt(log2Ceil(32 * vLen / writeBits).W) def bankId = if (vrfBankBits == 0) 0.U else eg(vrfBankBits-1,0) val data = UInt(writeBits.W) val mask = UInt(writeBits.W) } class ScalarWrite extends Bundle { val data = UInt(64.W) val fp = Bool() val size = UInt(2.W) val rd = UInt(5.W) } class VectorReadReq(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val eg = UInt(log2Ceil(egsTotal).W) val oldest = Bool() } class VectorReadIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val req = Decoupled(new VectorReadReq) val resp = Input(UInt(dLen.W)) } class VectorIndexAccessIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val ready = Output(Bool()) val valid = Input(Bool()) val vrs = Input(UInt(5.W)) val eidx = Input(UInt((1+log2Ceil(maxVLMax)).W)) val eew = Input(UInt(2.W)) val idx = Output(UInt(64.W)) } class VectorMaskAccessIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val ready = Output(Bool()) val valid = Input(Bool()) val eidx = Input(UInt((1+log2Ceil(maxVLMax)).W)) val mask = Output(Bool()) } class MaskedByte(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val debug_id = UInt(debugIdSz.W) val data = UInt(8.W) val mask = Bool() } class ExecuteMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val eidx = UInt(log2Ceil(maxVLMax).W) val vl = UInt((1+log2Ceil(maxVLMax)).W) val rvs1_data = UInt(dLen.W) val rvs2_data = UInt(dLen.W) val rvd_data = UInt(dLen.W) val rvm_data = UInt(dLen.W) val rvs1_elem = UInt(64.W) val rvs2_elem = UInt(64.W) val rvd_elem = UInt(64.W) val rvs1_eew = UInt(2.W) val rvs2_eew = UInt(2.W) val rvd_eew = UInt(2.W) val vd_eew = UInt(2.W) val rmask = UInt(dLenB.W) val wmask = UInt(dLenB.W) val full_tail_mask = UInt(dLen.W) val wvd_eg = UInt(log2Ceil(egsTotal).W) val funct3 = UInt(3.W) def isOpi = funct3.isOneOf(OPIVV, OPIVI, OPIVX) def isOpm = funct3.isOneOf(OPMVV, OPMVX) def isOpf = funct3.isOneOf(OPFVV, OPFVF) def opmf6 = Mux(isOpm, OPMFunct6(funct6), OPMFunct6.illegal) def opif6 = Mux(isOpi, OPIFunct6(funct6), OPIFunct6.illegal) def opff6 = Mux(isOpf, OPFFunct6(funct6), OPFFunct6.illegal) def vd_eew8 = vd_eew === 0.U def vd_eew16 = vd_eew === 1.U def vd_eew32 = vd_eew === 2.U def vd_eew64 = vd_eew === 3.U val funct6 = UInt(6.W) val rs1 = UInt(5.W) val rs2 = UInt(5.W) val rd = UInt(5.W) val vm = Bool() val head = Bool() val tail = Bool() val vat = UInt(vParams.vatSz.W) val acc = Bool() val rm = UInt(3.W) def vxrm = rm(1,0) def frm = rm } class StoreDataMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val stdata = UInt(dLen.W) val stmask = UInt(dLenB.W) val debug_id = UInt(debugIdSz.W) val tail = Bool() val vat = UInt(vParams.vatSz.W) def asMaskedBytes = { val bytes = Wire(Vec(dLenB, new MaskedByte)) for (i <- 0 until dLenB) { bytes(i).data := stdata(((i+1)8)-1,i8) bytes(i).mask := stmask(i) bytes(i).debug_id := debug_id } bytes } } class LoadRespMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val wvd_eg = UInt(log2Ceil(egsTotal).W) val wmask = UInt(dLenB.W) val tail = Bool() val debug_id = UInt(debugIdSz.W) val vat = UInt(vParams.vatSz.W) } class PermuteMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val renv2 = Bool() val renvm = Bool() val rvs2_data = UInt(dLen.W) val eidx = UInt(log2Ceil(maxVLMax).W) val rvs2_eew = UInt(2.W) val rvm_data = UInt(dLen.W) val vmu = Bool() val vl = UInt((1+log2Ceil(maxVLMax)).W) val tail = Bool() } class PipeHazard(pipe_depth: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val latency = UInt(log2Ceil(pipe_depth).W) val eg = UInt(log2Ceil(egsTotal).W) def eg_oh = UIntToOH(eg) } class SequencerHazard(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val vat = UInt(vParams.vatSz.W) val rintent = UInt(egsTotal.W) val wintent = UInt(egsTotal.W) } class InstructionHazard(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val vat = UInt(vParams.vatSz.W) val rintent = UInt(32.W) val wintent = UInt(32.W) } File SegmentedMultiplyPipe.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ import saturn.insns._ case class IntegerMultiplyFactory(depth: Int, segmented: Boolean) extends FunctionalUnitFactory { def base_insns = Seq( MUL.VV, MUL.VX, MULH.VV, MULH.VX, MULHU.VV, MULHU.VX, MULHSU.VV, MULHSU.VX, WMUL.VV, WMUL.VX, WMULU.VV, WMULU.VX, WMULSU.VV, WMULSU.VX, MACC.VV, MACC.VX, NMSAC.VV, NMSAC.VX, MADD.VV, MADD.VX, NMSUB.VV, NMSUB.VX, WMACC.VV, WMACC.VX, WMACCU.VV, WMACCU.VX, WMACCSU.VV , WMACCSU.VX, WMACCUS.VV, WMACCUS.VX, SMUL.VV, SMUL.VX) def insns = if (segmented) base_insns else base_insns.map(_.elementWise) def generate(implicit p: Parameters) = if (segmented) { new SegmentedMultiplyPipe(depth)(p) } else { new ElementwiseMultiplyPipe(depth)(p) } } class SegmentedMultiplyPipe(depth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit(depth)(p) { val supported_insns = IntegerMultiplyFactory(depth, true).insns io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched io.set_vxsat := false.B io.set_fflags.valid := false.B io.set_fflags.bits := DontCare val ctrl = new VectorDecoder(io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, 0.U, 0.U, supported_insns, Seq( MULHi, MULSign1, MULSign2, MULSwapVdV2, MULAccumulate, MULSub)) val in_eew = io.pipe(0).bits.rvs1_eew val out_eew = io.pipe(0).bits.vd_eew val in_vs1 = io.pipe(0).bits.rvs1_data val in_vs2 = io.pipe(0).bits.rvs2_data val in_vd = io.pipe(0).bits.rvd_data val mul_in1 = in_vs1 val mul_in2 = Mux(ctrl.bool(MULSwapVdV2), in_vd, in_vs2) val multipliers = Seq.fill(dLenB >> 3)(Module(new MultiplyBlock)) for (i <- 0 until (dLenB >> 3)) { multipliers(i).io.in1_signed := ctrl.bool(MULSign1) multipliers(i).io.in2_signed := ctrl.bool(MULSign2) multipliers(i).io.eew := io.pipe(0).bits.rvs1_eew multipliers(i).io.in1 := mul_in1.asTypeOf(Vec(dLenB >> 3, UInt(64.W)))(i) multipliers(i).io.in2 := mul_in2.asTypeOf(Vec(dLenB >> 3, UInt(64.W)))(i) } val mul_out_comb = VecInit(multipliers.map(_.io.out_data)).asUInt //////////////////////////////////////////////////////////////////////////////////////////// // Pipeline Stages Before Adder Array //////////////////////////////////////////////////////////////////////////////////////////// val mul_out = Pipe(io.pipe(0).valid, mul_out_comb, depth-2).bits val in_eew_pipe = io.pipe(depth-2).bits.rvs1_eew val out_eew_pipe = io.pipe(depth-2).bits.vd_eew val ctrl_wmul = out_eew_pipe > in_eew_pipe val ctrl_smul = io.pipe(depth-2).bits.isOpi val ctrl_MULSub = Pipe(io.pipe(0).valid, ctrl.bool(MULSub), depth-2).bits val ctrl_MULSwapVdV2 = Pipe(io.pipe(0).valid, ctrl.bool(MULSwapVdV2), depth-2).bits val ctrl_MULAccumulate = Pipe(io.pipe(0).valid, ctrl.bool(MULAccumulate), depth-2).bits val ctrl_MULHi = Pipe(io.pipe(0).valid, ctrl.bool(MULHi), depth-2).bits val in_vs2_pipe = io.pipe(depth-2).bits.rvs2_data val in_vd_pipe = io.pipe(depth-2).bits.rvd_data //////////////////////////////////////////////////////////////////////////////////////////// val hi = VecInit.tabulate(4)({sew => VecInit(mul_out.asTypeOf(Vec((2dLenB) >> sew, UInt((8 << sew).W))).grouped(2).map(_.last).toSeq).asUInt })(in_eew_pipe) val lo = VecInit.tabulate(4)({sew => VecInit(mul_out.asTypeOf(Vec((2dLenB) >> sew, UInt((8 << sew).W))).grouped(2).map(_.head).toSeq).asUInt })(in_eew_pipe) val half_sel = (io.pipe(depth-2).bits.eidx >> (dLenOffBits.U - out_eew_pipe))(0) val wide = Mux(half_sel, mul_out >> dLen, mul_out)(dLen-1,0) val (smul_clipped, smul_sat) = { val smul_arr = Module(new VectorSMul) smul_arr.io.mul_in := mul_out smul_arr.io.eew := out_eew_pipe smul_arr.io.vxrm := io.pipe(depth-2).bits.vxrm (smul_arr.io.clipped, smul_arr.io.sat) } val adder_arr = Module(new AdderArray(dLenB)) adder_arr.io.in1 := Mux(ctrl_wmul, wide, lo).asTypeOf(Vec(dLenB, UInt(8.W))) adder_arr.io.in2 := Mux(ctrl_MULAccumulate, Mux(ctrl_MULSwapVdV2, in_vs2_pipe, in_vd_pipe), 0.U(dLen.W)).asTypeOf(Vec(dLenB, UInt(8.W))) adder_arr.io.incr := VecInit.fill(dLenB)(false.B) adder_arr.io.mask_carry := 0.U adder_arr.io.signed := DontCare adder_arr.io.eew := out_eew_pipe adder_arr.io.avg := false.B adder_arr.io.rm := DontCare adder_arr.io.sub := ctrl_MULSub adder_arr.io.cmask := false.B val add_out = adder_arr.io.out val out = Mux(ctrl_smul, smul_clipped, 0.U) \| Mux(ctrl_MULHi, hi, 0.U) \| Mux(!ctrl_smul && !ctrl_MULHi, add_out.asUInt, 0.U) val pipe_out = Pipe(io.pipe(depth-2).valid, out, 1).bits val vxsat = Mux(ctrl_smul, smul_sat, 0.U) & io.pipe(depth-2).bits.wmask val pipe_vxsat = Pipe(io.pipe(depth-2).valid, vxsat, 1).bits io.pipe0_stall := false.B io.write.valid := io.pipe(depth-1).valid io.write.bits.eg := io.pipe(depth-1).bits.wvd_eg io.write.bits.data := pipe_out io.write.bits.mask := FillInterleaved(8, io.pipe(depth-1).bits.wmask) io.set_vxsat := io.pipe(depth-1).valid && (pipe_vxsat =/= 0.U) io.scalar_write.valid := false.B io.scalar_write.bits := DontCare } class MultiplyBlock extends Module { val xLen = 64 val io = IO(new Bundle { val in1_signed = Input(Bool()) val in2_signed = Input(Bool()) val eew = Input(UInt(2.W)) val in1 = Input(UInt(xLen.W)) val in2 = Input(UInt(xLen.W)) val out_data = Output(UInt((2xLen).W)) }) val mul64 = Module(new Multiplier(64)) mul64.io.in1_signed := io.in1_signed mul64.io.in2_signed := io.in2_signed mul64.io.in1 := io.in1 mul64.io.in2 := io.in2 val mul32 = Module(new Multiplier(32)) mul32.io.in1_signed := io.in1_signed mul32.io.in2_signed := io.in2_signed mul32.io.in1 := io.in1(63,32) mul32.io.in2 := io.in2(63,32) val mul16 = Seq.tabulate(2) { i => val indh = 32(i+1) - 1 val indl = 32i + 16 val in1 = io.in1(indh, indl) val in2 = io.in2(indh, indl) val mul = Module(new Multiplier(16)) mul.io.in1_signed := io.in1_signed mul.io.in2_signed := io.in2_signed mul.io.in1 := in1 mul.io.in2 := in2 mul } val mul8 = Seq.tabulate(4) { i => val indh = 16(i+1) - 1 val indl = 16i + 8 val in1 = io.in1(indh, indl) val in2 = io.in2(indh, indl) val mul = Module(new Multiplier(8)) mul.io.in1_signed := io.in1_signed mul.io.in2_signed := io.in2_signed mul.io.in1 := in1 mul.io.in2 := in2 mul } when (io.eew === 0.U) { mul16(1).io.in1 := Cat(Fill(8, io.in1_signed && io.in1(55)), io.in1(55, 48)) mul16(1).io.in2 := Cat(Fill(8, io.in2_signed && io.in2(55)), io.in2(55, 48)) mul32.io.in1 := Cat(Fill(8, io.in1_signed && io.in1(39)), io.in1(39, 32)) mul32.io.in2 := Cat(Fill(8, io.in2_signed && io.in2(39)), io.in2(39, 32)) mul16(0).io.in1 := Cat(Fill(8, io.in1_signed && io.in1(23)), io.in1(23, 16)) mul16(0).io.in2 := Cat(Fill(8, io.in2_signed && io.in2(23)), io.in2(23, 16)) mul64.io.in1 := Cat(Fill(8, io.in1_signed && io.in1(7)), io.in1(7,0)) mul64.io.in2 := Cat(Fill(8, io.in2_signed && io.in2(7)), io.in2(7,0)) io.out_data := Cat(mul8(3).io.out_data, mul16(1).io.out_data(15,0), mul8(2).io.out_data, mul32.io.out_data(15,0), mul8(1).io.out_data, mul16(0).io.out_data(15,0), mul8(0).io.out_data, mul64.io.out_data(15,0)) } .elsewhen (io.eew === 1.U) { mul32.io.in1 := Cat(Fill(16, io.in1_signed && io.in1(47)), io.in1(47, 32)) mul32.io.in2 := Cat(Fill(16, io.in2_signed && io.in2(47)), io.in2(47, 32)) mul64.io.in1 := Cat(Fill(16, io.in1_signed && io.in1(15)), io.in1(15,0)) mul64.io.in2 := Cat(Fill(16, io.in2_signed && io.in2(15)), io.in2(15,0)) io.out_data := Cat(mul16(1).io.out_data, mul32.io.out_data(31,0), mul16(0).io.out_data, mul64.io.out_data(31,0)) } .elsewhen (io.eew === 2.U) { mul64.io.in1 := Cat(Fill(32, io.in1_signed && io.in1(31)), io.in1(31,0)) mul64.io.in2 := Cat(Fill(32, io.in2_signed && io.in2(31)), io.in2(31,0)) io.out_data := Cat(mul32.io.out_data, mul64.io.out_data(63,0)) } .otherwise { io.out_data := mul64.io.out_data } } class Multiplier(width: Int) extends Module { val io = IO(new Bundle { val in1_signed = Input(Bool()) val in2_signed = Input(Bool()) val in1 = Input(UInt(width.W)) val in2 = Input(UInt(width.W)) val out_data = Output(UInt((2width).W)) }) val lhs = Cat(io.in1_signed && io.in1(width-1), io.in1).asSInt val rhs = Cat(io.in2_signed && io.in2(width-1), io.in2).asSInt val prod = lhs * rhs io.out_data := prod(2width-1,0) } class VectorSMul(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val eew = Input(UInt(2.W)) val vxrm = Input(UInt(2.W)) val mul_in = Input(UInt((2dLen).W)) val clipped = Output(UInt((dLen).W)) val sat = Output(UInt(dLenB.W)) }) val sat_sew = Wire(Vec(4, UInt(dLenB.W))) val clipped_sew = Wire(Vec(4, UInt(dLen.W))) for (sew <- 0 until 4) { val wideProds = io.mul_in.asTypeOf(Vec(dLenB >> sew, SInt((16 << sew).W))) val smul = wideProds.map { wideElem => val rounding_incr = RoundingIncrement(io.vxrm, wideElem((8 << sew)-1, 0)) (wideElem >> ((8 << sew) - 1)) + Cat(0.U(1.W), rounding_incr).asSInt } val clip_neg = (-1 << ((8 << sew)-1)).S val clip_pos = ((1 << ((8 << sew)-1)) - 1).S val clip_hi = smul.map{ _ > clip_pos } val clip_lo = smul.map{ _ < clip_neg } clipped_sew(sew) := smul.zipWithIndex.map { case (sm, i) => val long = Mux(clip_hi(i), clip_pos, 0.S) \| Mux(clip_lo(i), clip_neg, 0.S) \| Mux(!clip_hi(i) && !clip_lo(i), sm, 0.S) long((8 << sew)-1, 0) }.asUInt val sat_vec_sew = smul.zipWithIndex.map { case (sm, i) => clip_hi(i) \|\| clip_lo(i) } sat_sew(sew) := FillInterleaved((1 << sew), sat_vec_sew) } io.clipped := clipped_sew(io.eew) io.sat := sat_sew(io.eew) }	module SegmentedMultiplyPipe( // @[SegmentedMultiplyPipe.scala:31:7] input clock, // @[SegmentedMultiplyPipe.scala:31:7] input [2:0] io_iss_op_funct3, // @[FunctionalUnit.scala:49:14] input [5:0] io_iss_op_funct6, // @[FunctionalUnit.scala:49:14] output io_iss_ready, // @[FunctionalUnit.scala:49:14] output io_set_vxsat, // @[FunctionalUnit.scala:49:14] output io_write_valid, // @[FunctionalUnit.scala:49:14] output [6:0] io_write_bits_eg, // @[FunctionalUnit.scala:49:14] output [63:0] io_write_bits_data, // @[FunctionalUnit.scala:49:14] output [63:0] io_write_bits_mask, // @[FunctionalUnit.scala:49:14] input io_pipe_0_valid, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_rvs1_data, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_rvs2_data, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_rvd_data, // @[FunctionalUnit.scala:49:14] input [1:0] io_pipe_0_bits_rvs1_eew, // @[FunctionalUnit.scala:49:14] input [2:0] io_pipe_0_bits_funct3, // @[FunctionalUnit.scala:49:14] input [5:0] io_pipe_0_bits_funct6, // @[FunctionalUnit.scala:49:14] input io_pipe_1_valid, // @[FunctionalUnit.scala:49:14] input [7:0] io_pipe_1_bits_eidx, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_1_bits_rvs2_data, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_1_bits_rvd_data, // @[FunctionalUnit.scala:49:14] input [1:0] io_pipe_1_bits_rvs1_eew, // @[FunctionalUnit.scala:49:14] input [1:0] io_pipe_1_bits_vd_eew, // @[FunctionalUnit.scala:49:14] input [7:0] io_pipe_1_bits_wmask, // @[FunctionalUnit.scala:49:14] input [2:0] io_pipe_1_bits_funct3, // @[FunctionalUnit.scala:49:14] input [2:0] io_pipe_1_bits_rm, // @[FunctionalUnit.scala:49:14] input io_pipe_2_valid, // @[FunctionalUnit.scala:49:14] input [7:0] io_pipe_2_bits_wmask, // @[FunctionalUnit.scala:49:14] input [6:0] io_pipe_2_bits_wvd_eg // @[FunctionalUnit.scala:49:14] ); wire [7:0] _adder_arr_io_out_0; // @[SegmentedMultiplyPipe.scala:96:25] wire [7:0] _adder_arr_io_out_1; // @[SegmentedMultiplyPipe.scala:96:25] wire [7:0] _adder_arr_io_out_2; // @[SegmentedMultiplyPipe.scala:96:25] wire [7:0] _adder_arr_io_out_3; // @[SegmentedMultiplyPipe.scala:96:25] wire [7:0] _adder_arr_io_out_4; // @[SegmentedMultiplyPipe.scala:96:25] wire [7:0] _adder_arr_io_out_5; // @[SegmentedMultiplyPipe.scala:96:25] wire [7:0] _adder_arr_io_out_6; // @[SegmentedMultiplyPipe.scala:96:25] wire [7:0] _adder_arr_io_out_7; // @[SegmentedMultiplyPipe.scala:96:25] wire [63:0] _smul_arr_io_clipped; // @[SegmentedMultiplyPipe.scala:89:26] wire [7:0] _smul_arr_io_sat; // @[SegmentedMultiplyPipe.scala:89:26] wire [127:0] _multipliers_0_io_out_data; // @[SegmentedMultiplyPipe.scala:52:48] wire [4:0] _GEN = ~(io_iss_op_funct6[4:0]); // @[pla.scala:78:21] wire [4:0] _GEN_0 = ~(io_pipe_0_bits_funct6[4:0]); // @[pla.scala:78:21] wire [1:0] _decode_andMatrixOutputs_T_1 = {_GEN_0[2], _GEN_0[4]}; // @[pla.scala:78:21, :91:29, :98:53] reg [127:0] mul_out_pipe_b; // @[Valid.scala:142:26] reg ctrl_MULSub_pipe_b; // @[Valid.scala:142:26] reg ctrl_MULSwapVdV2_pipe_b; // @[Valid.scala:142:26] reg ctrl_MULAccumulate_pipe_b; // @[Valid.scala:142:26] reg ctrl_MULHi_pipe_b; // @[Valid.scala:142:26] wire [7:0] _half_sel_T_2 = io_pipe_1_bits_eidx >> 2'h3 - io_pipe_1_bits_vd_eew; // @[SegmentedMultiplyPipe.scala:85:{46,64}] wire [3:0][63:0] _GEN_1 = {{mul_out_pipe_b[63:0]}, {{mul_out_pipe_b[95:64], mul_out_pipe_b[31:0]}}, {{mul_out_pipe_b[111:96], mul_out_pipe_b[79:64], mul_out_pipe_b[47:32], mul_out_pipe_b[15:0]}}, {{mul_out_pipe_b[119:112], mul_out_pipe_b[103:96], mul_out_pipe_b[87:80], mul_out_pipe_b[71:64], mul_out_pipe_b[55:48], mul_out_pipe_b[39:32], mul_out_pipe_b[23:16], mul_out_pipe_b[7:0]}}}; // @[Valid.scala:142:26] wire [63:0] _GEN_2 = io_pipe_1_bits_vd_eew > io_pipe_1_bits_rvs1_eew ? (_half_sel_T_2[0] ? mul_out_pipe_b[127:64] : mul_out_pipe_b[63:0]) : _GEN_1[io_pipe_1_bits_rvs1_eew]; // @[Valid.scala:142:26] wire [63:0] _GEN_3 = ctrl_MULAccumulate_pipe_b ? (ctrl_MULSwapVdV2_pipe_b ? io_pipe_1_bits_rvs2_data : io_pipe_1_bits_rvd_data) : 64'h0; // @[Valid.scala:142:26] reg [63:0] pipe_out_pipe_b; // @[Valid.scala:142:26] reg [7:0] pipe_vxsat_pipe_b; // @[Valid.scala:142:26] wire ctrl_smul = io_pipe_1_bits_funct3 == 3'h0 \| io_pipe_1_bits_funct3 == 3'h3 \| io_pipe_1_bits_funct3 == 3'h4; // @[SegmentedMultiplyPipe.scala:31:7] wire [3:0][63:0] _GEN_4 = {{mul_out_pipe_b[127:64]}, {{mul_out_pipe_b[127:96], mul_out_pipe_b[63:32]}}, {{mul_out_pipe_b[127:112], mul_out_pipe_b[95:80], mul_out_pipe_b[63:48], mul_out_pipe_b[31:16]}}, {{mul_out_pipe_b[127:120], mul_out_pipe_b[111:104], mul_out_pipe_b[95:88], mul_out_pipe_b[79:72], mul_out_pipe_b[63:56], mul_out_pipe_b[47:40], mul_out_pipe_b[31:24], mul_out_pipe_b[15:8]}}}; // @[Valid.scala:142:26] always @(posedge clock) begin // @[SegmentedMultiplyPipe.scala:31:7] if (io_pipe_0_valid) begin // @[FunctionalUnit.scala:49:14] mul_out_pipe_b <= _multipliers_0_io_out_data; // @[Valid.scala:142:26] ctrl_MULSub_pipe_b <= &{io_pipe_0_bits_funct6[1], io_pipe_0_bits_funct6[3], _GEN_0[4]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] ctrl_MULSwapVdV2_pipe_b <= &_decode_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] ctrl_MULAccumulate_pipe_b <= \|{&_decode_andMatrixOutputs_T_1, &{io_pipe_0_bits_funct6[2], io_pipe_0_bits_funct6[3]}}; // @[pla.scala:90:45, :98:{53,70}, :114:{19,36}] ctrl_MULHi_pipe_b <= \|{&{_GEN_0[0], _GEN_0[3]}, &{io_pipe_0_bits_funct6[1], _GEN_0[3], io_pipe_0_bits_funct3[1]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] end if (io_pipe_1_valid) begin // @[FunctionalUnit.scala:49:14] pipe_out_pipe_b <= (ctrl_smul ? _smul_arr_io_clipped : 64'h0) \| (ctrl_MULHi_pipe_b ? _GEN_4[io_pipe_1_bits_rvs1_eew] : 64'h0) \| (ctrl_smul \| ctrl_MULHi_pipe_b ? 64'h0 : {_adder_arr_io_out_7, _adder_arr_io_out_6, _adder_arr_io_out_5, _adder_arr_io_out_4, _adder_arr_io_out_3, _adder_arr_io_out_2, _adder_arr_io_out_1, _adder_arr_io_out_0}); // @[Valid.scala:142:26] pipe_vxsat_pipe_b <= (ctrl_smul ? _smul_arr_io_sat : 8'h0) & io_pipe_1_bits_wmask; // @[Valid.scala:142:26] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File FSECompressorDicBuilder.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants import ZstdConsts._ class FSECompTransformationTable extends Bundle { val nbbit = UInt(32.W) val findstate = UInt(32.W) val from_last_symbol = Bool() } class FSECompressorDicBuilderIO(val interleave_cnt: Int)(implicit p: Parameters) extends Bundle { val nb_seq = Flipped(Decoupled(UInt(64.W))) val ll_stream = Flipped(new MemLoaderConsumerBundle) val ll_table_log = Decoupled(UInt(4.W)) val symbol_info = Vec(interleave_cnt, Flipped(Decoupled(new FSESymbolInfo))) val symbolTT_info = Vec(interleave_cnt, Decoupled(new FSECompTransformationTable)) val state_table_idx = Vec(interleave_cnt, Input(UInt(16.W))) val new_state = Vec(interleave_cnt, Valid(UInt(16.W))) val header_writes = Decoupled(new WriterBundle) val predefined_mode = Decoupled(Bool()) val lookup_done = Flipped(Decoupled(Bool())) } // NOTE : about 4 * 2^tableLog Bytes of on-chip regs class FSECompressorDicBuilder( val printInfo: String, val interleave_cnt: Int, val as_zstd_submodule: Boolean, val max_symbol_value: Int, val max_table_log: Int, val predefined_table_log: Int, val mark_end_of_header: Boolean = false) (implicit p: Parameters) extends Module { val io = IO(new FSECompressorDicBuilderIO(interleave_cnt)) def BIT_highbit32(x: UInt): UInt = { // add assertion about x width? val highBit = 31.U - PriorityEncoder(Reverse(x)) highBit } val rtbTable_initialized = RegInit(false.B) val rtbTable = RegInit(VecInit(Seq.fill(8)(0.U(32.W)))) when (!rtbTable_initialized) { rtbTable(0) := 0.U rtbTable(1) := 473195.U rtbTable(2) := 504333.U rtbTable(3) := 520860.U rtbTable(4) := 550000.U rtbTable(5) := 700000.U rtbTable(6) := 750000.U rtbTable(7) := 830000.U rtbTable_initialized := true.B } val LL_symbolTTDeltaNbBitsDefaultValues = List( 327552, 327584, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393152, 393152, 393152, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 327584, 393088, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152 ) val LL_symbolTTDeltaFindStateDefaultValues = List( -4, 1, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 28, 29, 30, 30, 32, 34, 36, 38, 40, 42, 44, 46, 47, 51, 54, 55, 56, 57, 58, 59, 60, 61, 62 ) val LL_DefaultTableU16 = List( 64, 65, 86, 107, 66, 87, 108, 88, 109, 67, 110, 68, 89, 90, 111, 69, 112, 70, 91, 92, 113, 71, 114, 72, 93, 94, 115, 73, 116, 95, 74, 117, 75, 96, 97, 118, 76, 119, 77, 98, 99, 120, 78, 121, 79, 100, 101, 122, 80, 123, 81, 102, 103, 82, 104, 83, 105, 84, 106, 85, 127, 126, 125, 124 ) val OF_symbolTTDeltaNbBitsDefaultValues = List( 327648, 327648, 327648, 327648, 327648, 327648, 327616, 327616, 327616, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648 ) val OF_symbolTTDeltaFindStateDefaultValues = List( -1, 0, 1, 2, 3, 4, 4, 6, 8, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 ) val OF_DefaultTableU16 = List( 32, 55, 46, 37, 51, 42, 33, 56, 38, 47, 43, 52, 34, 57, 48, 39, 53, 44, 35, 58, 49, 40, 54, 45, 36, 50, 41, 63, 62, 61, 60, 59 ) val ML_symbolTTDeltaNbBitsDefaultValues = List( 393152, 327552, 327584, 393088, 393088, 393088, 393088, 393088, 393088, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152 ) val ML_symbolTTDeltaFindStateDefaultValues = List( -1, -3, 2, 6, 8, 10, 12, 14, 16, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62 ) val ML_DefaultTableU16 = List( 64, 65, 86, 107, 108, 66, 87, 109, 67, 88, 89, 110, 68, 111, 69, 90, 91, 112, 70, 113, 92, 71, 114, 93, 72, 115, 94, 73, 116, 95, 74, 117, 96, 75, 118, 97, 76, 119, 98, 77, 120, 99, 78, 100, 79, 101, 80, 102, 81, 103, 82, 104, 83, 105, 84, 106, 85, 127, 126, 125, 124, 123, 122, 121 ) // Tie up wires io.ll_stream.output_ready := false.B io.ll_stream.user_consumed_bytes := 0.U io.nb_seq.ready := false.B val predefined_mode_q = Module(new Queue(Bool(), 4)) predefined_mode_q.io.enq.valid := false.B predefined_mode_q.io.enq.bits := false.B io.predefined_mode <> predefined_mode_q.io.deq val sIdle = 0.U val sCount = 1.U val sNormalizeCount = 2.U val sBuildCTableSymbolStartPositions = 3.U val sBuildCTableSpreadSymbols = 4.U val sBuildCTableBuildTable = 5.U val sBuildCTableSymbolTT = 6.U val sWriteCTable = 7.U val sLookup = 8.U val dicBuilderState = RegInit(0.U(4.W)) val COLLECT_STAT_PROCESS_BYTES = p(FSECompressDicBuilderProcessedStatBytesPerCycle) val COLLECT_STAT_PROCESS_BYTES_LOG2 = log2Ceil(COLLECT_STAT_PROCESS_BYTES + 1) val tableLogLL = max_table_log // Always use maximum possible tableLog since dictionary lookups are basically free??????? val maxSymbolLL = max_symbol_value val maxSymbolLLPlus1 = max_symbol_value + 1 /////////////////////////////////////////////////////////////////////////// // sCount /////////////////////////////////////////////////////////////////////////// val ll_count = RegInit(VecInit(Seq.fill(maxSymbolLLPlus1)(0.U(32.W)))) val ll_max_symbol_value = RegInit(0.U(32.W)) val ll_nbseq_1 = RegInit(0.U(64.W)) val input_ll_symbols = WireInit(VecInit(Seq.fill(COLLECT_STAT_PROCESS_BYTES)(0.U(8.W)))) for (i <- 0 until COLLECT_STAT_PROCESS_BYTES) { input_ll_symbols(i) := io.ll_stream.output_data >> (i8).U } dontTouch(input_ll_symbols) val avail_bytes = io.ll_stream.available_output_bytes val table = Seq.fill(maxSymbolLLPlus1)(WireInit(VecInit(Seq.fill(COLLECT_STAT_PROCESS_BYTES)(0.U(1.W))))) for (i <- 0 until maxSymbolLLPlus1) { for (j <- 0 until COLLECT_STAT_PROCESS_BYTES) { table(i)(j) := Mux(j.U < avail_bytes && (input_ll_symbols(j) === i.U), 1.U, 0.U) } } val stat_sum = WireInit(VecInit(Seq.fill(maxSymbolLLPlus1)(0.U(COLLECT_STAT_PROCESS_BYTES_LOG2.W)))) for (i <- 0 until maxSymbolLLPlus1) { stat_sum(i) := table(i).reduce(_ +& _) } val has_value = WireInit(VecInit(Seq.fill(maxSymbolLLPlus1)(0.U(1.W)))) for (i <- 0 until maxSymbolLLPlus1) { has_value(i) := Mux(stat_sum(i) > 0.U, 1.U, 0.U) } val has_value_cat = Cat(has_value) val cur_max_value = (maxSymbolLLPlus1 - 1).U - PriorityEncoder(has_value_cat) when (dicBuilderState === sCount) { when (io.ll_stream.output_valid) { for (i <- 0 until maxSymbolLLPlus1) { ll_count(i) := ll_count(i) + stat_sum(i) } ll_max_symbol_value := Mux(ll_max_symbol_value > cur_max_value, ll_max_symbol_value, cur_max_value) } } /////////////////////////////////////////////////////////////////////////// // sNormalizeCount (FSE_normalizeCount) /////////////////////////////////////////////////////////////////////////// / * { static U32 const rtbTable[] = { 0, 473195, 504333, 520860, 550000, 700000, 750000, 830000 }; * short const lowProbCount = useLowProbCount ? -1 : 1; * U64 const scale = 62 - tableLog; * U64 const step = ZSTD_div64((U64)1<<62, (U32)total); * U64 const vStep = 1ULL<<(scale-20); * int stillToDistribute = 1<<tableLog; * unsigned s; * unsigned largest=0; * short largestP=0; * U32 lowThreshold = (U32)(total >> tableLog); * for (s=0; s<=maxSymbolValue; s++) { * if (count[s] == total) return 0; // rle special case * if (count[s] == 0) { normalizedCounter[s]=0; continue; } * if (count[s] <= lowThreshold) { * normalizedCounter[s] = lowProbCount; * stillToDistribute--; * } else { * short proba = (short)((count[s]step) >> scale); if (proba<8) { * U64 restToBeat = vStep * rtbTable[proba]; * proba += (count[s]step) - ((U64)proba<<scale) > restToBeat; } * if (proba > largestP) { largestP=proba; largest=s; } * normalizedCounter[s] = proba; * stillToDistribute -= proba; * } } * if (-stillToDistribute >= (normalizedCounter[largest] >> 1)) { * // corner case, need another normalization method * size_t const errorCode = FSE_normalizeM2(normalizedCounter, tableLog, count, total, maxSymbolValue, lowProbCount); * if (FSE_isError(errorCode)) return errorCode; * } * else normalizedCounter[largest] += (short)stillToDistribute; / val neg_one_uint16 = (1 << 16) - 1 // val ll_useLowProbCount = ll_nbseq_1 >= 2048.U // don't use lowProb stuff for now, (small comp ratio gains for thousands of cycle tradeoff) val ll_useLowProbCount = ll_nbseq_1 >= BigInt("FFFFFFFF", 16).U val ll_lowProbCount = Wire(UInt(16.W)) ll_lowProbCount := Mux(ll_useLowProbCount, neg_one_uint16.U, 1.U) val ll_scale = Wire(UInt(7.W)) ll_scale := 62.U - tableLogLL.U val ll_step = Wire(UInt(64.W)) ll_step := BigInt("4000000000000000", 16).U / ll_nbseq_1 val ll_scale_20 = Wire(UInt(7.W)) ll_scale_20 := ll_scale - 20.U val ll_vStep = Wire(UInt(64.W)) ll_vStep := 1.U << ll_scale_20 val ll_still_to_distribute = (1 << tableLogLL).U val ll_lowThreshold = Wire(UInt(32.W)) ll_lowThreshold := ll_nbseq_1 >> tableLogLL.U val ll_proba_base = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) val ll_proba = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) val ll_count_times_step = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(64.W)))) for (i <- 0 until maxSymbolLL + 1) { ll_count_times_step(i) := ll_count(i) ll_step ll_proba_base(i) := ll_count_times_step(i) >> ll_scale val restToBeat = ll_vStep * rtbTable(ll_proba_base(i)) val ll_add_to_proba_base = Mux(ll_count(i) * ll_step - (ll_proba_base(i) << ll_scale) > restToBeat, 1.U, 0.U) ll_proba(i) := Mux(ll_proba_base(i) < 8.U, ll_proba_base(i) + ll_add_to_proba_base, ll_proba_base(i)) } val ll_normalizedCounter = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) val ll_normalizedCounterMaxAdjusted = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) val ll_count_has_nbseq_1_as_value = ll_count.map{ case count => count === ll_nbseq_1 }.reduce(_ \|\| _) val ll_rle = ll_count_has_nbseq_1_as_value for (i <- 0 until maxSymbolLL + 1) { ll_normalizedCounter(i) := Mux(ll_count(i) === 0.U, 0.U, Mux(ll_count(i) <= ll_lowThreshold, ll_lowProbCount, ll_proba(i))) } val ll_smallOrEqToLowThresholdCount = ll_count.map{ case count => ((count <= ll_lowThreshold) && (count > 0.U)).asUInt }.reduce(_ +& _) val ll_largerThanLowThresholdProbaSum = ll_count.zipWithIndex.map{ case (count, idx) => Mux((count === ll_nbseq_1) \|\| (count === 0.U) \|\| (count <= ll_lowThreshold), 0.U, ll_proba(idx)) }.reduce(_ +& _) val ll_normalizedCounterMax = ll_normalizedCounter.reduceTree((a, b) => Mux(a > b, a, b)) val ll_normalizedCounterIdx = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) for (i <- 0 until maxSymbolLL + 1) { ll_normalizedCounterIdx(i) := i.U } val ll_normalizedCounterMaxIdx = ll_normalizedCounter.zip(ll_normalizedCounterIdx).reduce{ (x, y) => (Mux(x._1 < y._1, y._1, x._1), Mux(x._1 < y._1, y._2, x._2)) }._2 val ll_nxtStillToDistribute = (ll_still_to_distribute - ll_largerThanLowThresholdProbaSum - ll_smallOrEqToLowThresholdCount).asSInt val ll_negNxtStillToDistribute = (-1).S * ll_nxtStillToDistribute val fse_normalize_corner_case = ll_negNxtStillToDistribute >= (ll_normalizedCounterMax >> 1.U).asSInt val fse_normalize_corner_case_reg = RegInit(false.B) when (dicBuilderState === sNormalizeCount && predefined_mode_q.io.enq.ready) { predefined_mode_q.io.enq.valid := true.B for (i <- 0 until maxSymbolLL + 1) { val ll_ncountSumStill2Dist = (ll_normalizedCounter(i).asSInt + ll_nxtStillToDistribute).asUInt ll_normalizedCounterMaxAdjusted(i) := Mux(i.U === ll_normalizedCounterMaxIdx, ll_ncountSumStill2Dist, ll_normalizedCounter(i)) } // Force predefined mode when we encounter normalization corner case fse_normalize_corner_case_reg := fse_normalize_corner_case predefined_mode_q.io.enq.bits := fse_normalize_corner_case when (fse_normalize_corner_case) { CompressAccelLogger.logInfo(printInfo + " DICBUILDER ForcePredefinedMode\n") } } // insert registers to avoid critical path issues val ll_normalizedCounterReg = RegInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) when (dicBuilderState === sNormalizeCount) { for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_count(%d): %d\n", i.U, ll_count(i)) } CompressAccelLogger.logInfo(printInfo + " ll_lowProbCount: %d\n", ll_lowProbCount) CompressAccelLogger.logInfo(printInfo + " ll_scale: %d\n", ll_scale) CompressAccelLogger.logInfo(printInfo + " ll_scale_20: %d\n", ll_scale_20) CompressAccelLogger.logInfo(printInfo + " ll_step: %d\n", ll_step) CompressAccelLogger.logInfo(printInfo + " ll_vStep: %d\n", ll_vStep) CompressAccelLogger.logInfo(printInfo + " ll_still_to_distribute: %d\n", ll_still_to_distribute) CompressAccelLogger.logInfo(printInfo + " ll_lowThreshold: %d\n", ll_lowThreshold) for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_count_times_step(%d): %d\n", i.U, ll_count_times_step(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_proba_base(%d): %d\n", i.U, ll_proba_base(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_proba(%d): %d\n", i.U, ll_proba(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounter(%d): %d\n", i.U, ll_normalizedCounter(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounterMaxAdjusted(%d): %d\n", i.U, ll_normalizedCounterMaxAdjusted(i)) } CompressAccelLogger.logInfo(printInfo + " ll_smallOrEqToLowThresholdCount: %d\n", ll_smallOrEqToLowThresholdCount) CompressAccelLogger.logInfo(printInfo + " ll_largerThanLowThresholdProbaSum: %d\n", ll_largerThanLowThresholdProbaSum) CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounterMax: %d\n", ll_normalizedCounterMax) CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounterMaxIdx: %d\n", ll_normalizedCounterMaxIdx) CompressAccelLogger.logInfo(printInfo + " ll_nxtStillToDistribute: %d\n", ll_nxtStillToDistribute) CompressAccelLogger.logInfo(printInfo + " ll_negNxtStillToDistribute: %d\n", ll_negNxtStillToDistribute) CompressAccelLogger.logInfo(printInfo + " (ll_normalizedCounterMax >> 1.U).asSInt: %d\n", (ll_normalizedCounterMax >> 1.U).asSInt) } /////////////////////////////////////////////////////////////////////////// // sBuildCTableSymbolStartPositions /////////////////////////////////////////////////////////////////////////// val LL_TABLESIZE = 1 << tableLogLL val ll_maxSV1 = ll_max_symbol_value + 1.U val ll_tableSize = LL_TABLESIZE.U val ll_tableMask = ll_tableSize - 1.U val ll_cumul = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) val ll_tableSymbol = RegInit(VecInit(Seq.fill(LL_TABLESIZE)(0.U(8.W)))) val ll_highThresholdBeforeCumul = WireInit(0.U(32.W)) ll_highThresholdBeforeCumul := ll_tableSize - 1.U val ll_normCountEqsNegOne = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(8.W)))) val ll_normCountEqsNegOneCumul = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(8.W)))) val ll_normCountEqsNegOneSum = ll_normCountEqsNegOne.reduce(_ +& _) val ll_highThresholdAfterCumul = RegInit(0.U(32.W)) val ll_cumulReg = RegInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) /////////////////////////////////////////////////////////////////////////// // sBuildCTableSpreadSymbols /////////////////////////////////////////////////////////////////////////// val LL_SPREAD_TABLE_SIZE = LL_TABLESIZE + 8 val ll_spread = RegInit(VecInit(Seq.fill(LL_SPREAD_TABLE_SIZE)(0.U(8.W)))) val add = BigInt("0101010101010101", 16) val ll_pos = RegInit(0.U(64.W)) val ll_s = RegInit(0.U(64.W)) val ll_sv = RegInit(0.U(64.W)) val ll_fse_tablestep = (ll_tableSize >> 1.U) + (ll_tableSize >> 3.U) + 3.U /////////////////////////////////////////////////////////////////////////// // sBuildCTableBuildTable / sBuildCTableSymbolTT /////////////////////////////////////////////////////////////////////////// val ll_tableU16 = RegInit(VecInit(Seq.fill(LL_TABLESIZE)(0.U(16.W)))) val ll_symbolTTDeltaNbBits = RegInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(32.W)))) val ll_symbolTTDeltaFindState = RegInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.S(32.W)))) val ll_total = RegInit(0.U(32.W)) val normCount = Wire(UInt(32.W)) normCount := ll_normalizedCounterReg(ll_s) /////////////////////////////////////////////////////////////////////////// // sLookup /////////////////////////////////////////////////////////////////////////// val symbolTT_lookup_fire_and_last_vec = WireInit(VecInit(Seq.fill(interleave_cnt)(false.B))) for (i <- 0 until interleave_cnt) { val cur_symbol = io.symbol_info(i).bits.symbol val last_symbol = io.symbol_info(i).bits.last_symbol val symbolTT_lookup_fire = DecoupledHelper( io.symbol_info(i).valid, io.symbolTT_info(i).ready, dicBuilderState === sLookup) io.symbol_info(i).ready := symbolTT_lookup_fire.fire(io.symbol_info(i).valid) io.symbolTT_info(i).valid := symbolTT_lookup_fire.fire(io.symbolTT_info(i).ready) io.symbolTT_info(i).bits.nbbit := ll_symbolTTDeltaNbBits(cur_symbol) io.symbolTT_info(i).bits.findstate := ll_symbolTTDeltaFindState(cur_symbol).asUInt io.symbolTT_info(i).bits.from_last_symbol := last_symbol io.new_state(i).valid := (dicBuilderState === sLookup) io.new_state(i).bits := ll_tableU16(io.state_table_idx(i)) symbolTT_lookup_fire_and_last_vec(i) := symbolTT_lookup_fire.fire && last_symbol } val dictionary_lookup_done = symbolTT_lookup_fire_and_last_vec.reduce(_ \|\| _) // this is okay since we know for sure that in huffman, the fse compressor will // not be kicked-off unless there are enough symobls to compress val use_predefined_mode = (io.nb_seq.bits <= ZSTD_SEQUENCE_PREDEFINED_MODE_LIMIT.U) \|\| fse_normalize_corner_case_reg val ll_table_log_fired = RegInit(false.B) io.ll_table_log.bits := Mux(use_predefined_mode, predefined_table_log.U, tableLogLL.U) io.ll_table_log.valid := !ll_table_log_fired && (dicBuilderState === sLookup) when (io.ll_table_log.fire) { ll_table_log_fired := true.B } val print_table = RegInit(true.B) val write_header_started = RegInit(false.B) val nbBits = RegInit(0.U(32.W)) val remaining = RegInit(0.U(32.W)) val threshold = RegInit(0.U(32.W)) val symbol = RegInit(0.U(32.W)) val alphabetSize = ll_max_symbol_value + 1.U val previousIs0 = RegInit(false.B) val bitStream = RegInit(0.U(64.W)) val bitCount = RegInit(0.U(7.W)) val writeBitStream = RegInit(false.B) // TODO : optimize to write & update bitStream at the same time val start = RegInit(0.U(32.W)) val start_initialized = RegInit(false.B) val skip_zeros_done = RegInit(false.B) val skip_24_done = RegInit(false.B) val skip_3_done = RegInit(false.B) val writeBitStreamPrev0 = RegInit(false.B) val FSE_MIN_TABLELOG = 5 io.header_writes.valid := false.B io.header_writes.bits.data := 0.U io.header_writes.bits.validbytes := 0.U io.header_writes.bits.end_of_message := false.B val shifted_thresholds = WireInit(VecInit(Seq.fill(tableLogLL+1)(0.U(32.W)))) shifted_thresholds(0) := threshold for (i <- 1 until tableLogLL + 1) { shifted_thresholds(i) := shifted_thresholds(i-1) >> 1.U } val shifted_threshold_small_or_eq_remaining = WireInit(VecInit(Seq.fill(tableLogLL+1)(0.U(32.W)))) val nxt_shifted_threshold_idx = shifted_threshold_small_or_eq_remaining.reduce(_ + _) io.lookup_done.ready := true.B when (io.lookup_done.valid) { for (i <- 0 until maxSymbolLL+1) { ll_count(i) := 0.U } ll_max_symbol_value := 0.U ll_nbseq_1 := 0.U for (i <- 0 until maxSymbolLL + 1) { ll_normalizedCounterReg(i) := 0.U } for (i <- 0 until LL_TABLESIZE) { ll_tableSymbol(i) := 0.U } ll_highThresholdAfterCumul := 0.U for (i <- 0 until maxSymbolLL + 1) { ll_cumulReg(i) := 0.U } for (i <- 0 until LL_SPREAD_TABLE_SIZE) { ll_spread(i) := 0.U } ll_pos := 0.U ll_s := 0.U ll_sv := 0.U for (i <- 0 until LL_TABLESIZE) { ll_tableU16(i) := 0.U } for (i <- 0 until maxSymbolLL+ 1) { ll_symbolTTDeltaNbBits(i) := 0.U ll_symbolTTDeltaFindState(i) := 0.S } ll_total := 0.U ll_table_log_fired := false.B fse_normalize_corner_case_reg := false.B print_table := true.B write_header_started := false.B nbBits := 0.U remaining := 0.U threshold := 0.U symbol := 0.U previousIs0 := false.B bitStream := 0.U bitCount := 0.U writeBitStream := false.B start := 0.U start_initialized := false.B skip_zeros_done := false.B skip_24_done := false.B skip_3_done := false.B writeBitStreamPrev0 := false.B } switch (dicBuilderState) { is (sIdle) { when (io.ll_stream.output_valid && io.nb_seq.valid) { dicBuilderState := sCount } } is (sCount) { io.ll_stream.output_ready := predefined_mode_q.io.enq.ready io.ll_stream.user_consumed_bytes := Mux(io.ll_stream.available_output_bytes < COLLECT_STAT_PROCESS_BYTES.U, io.ll_stream.available_output_bytes, COLLECT_STAT_PROCESS_BYTES.U) when (io.ll_stream.output_valid) { for (i <- 0 until maxSymbolLL + 1) { ll_count(i) := ll_count(i) + stat_sum(i) } ll_max_symbol_value := Mux(ll_max_symbol_value > cur_max_value, ll_max_symbol_value, cur_max_value) } when (predefined_mode_q.io.enq.ready && io.ll_stream.output_valid && io.ll_stream.output_last_chunk && (io.ll_stream.user_consumed_bytes === io.ll_stream.available_output_bytes)) { // zstd_compress_sequences.c 271 // if (count[codeTable[nbSeq-1]] > 1) { // count[codeTable[nbSeq-1]]--; // nbSeq_1--; // } if (as_zstd_submodule) { val ll_last_codetable = input_ll_symbols(io.ll_stream.user_consumed_bytes - 1.U) val ll_count_last_codetable = ll_count(ll_last_codetable) val ll_last_statcount = stat_sum(ll_last_codetable) val ll_last_count = ll_count_last_codetable + ll_last_statcount val do_subtract = ll_last_count > 1.U ll_nbseq_1 := Mux(do_subtract, io.nb_seq.bits - 1.U, io.nb_seq.bits) ll_count(ll_last_codetable) := Mux(do_subtract, ll_last_count - 1.U, ll_last_count) } else { ll_nbseq_1 := io.nb_seq.bits } when (!use_predefined_mode) { dicBuilderState := sNormalizeCount } .otherwise { // TODO : set io.ll_stream.output_ready to true & move on to sLookup without going through sCount dicBuilderState := sLookup predefined_mode_q.io.enq.valid := true.B predefined_mode_q.io.enq.bits := true.B if (printInfo == "LL") { for (i <- 0 until 36) { ll_symbolTTDeltaNbBits(i) := LL_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := LL_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 64) { ll_tableU16(i) := LL_DefaultTableU16(i).U } } else if (printInfo == "ML") { for (i <- 0 until 53) { ll_symbolTTDeltaNbBits(i) := ML_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := ML_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 64) { ll_tableU16(i) := ML_DefaultTableU16(i).U } } else if (printInfo == "OF") { for (i <- 0 until 29) { ll_symbolTTDeltaNbBits(i) := OF_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := OF_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 32) { ll_tableU16(i) := OF_DefaultTableU16(i).U } } } } } is (sNormalizeCount) { CompressAccelLogger.logInfo(printInfo + "ll_nbseq_1: %d\n", ll_nbseq_1) for (i <- 0 until maxSymbolLL + 1) { ll_normalizedCounterReg(i) := ll_normalizedCounterMaxAdjusted(i) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_proba_base(%d): %d\n", i.U, ll_proba_base(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_proba(%d): %d\n", i.U, ll_proba(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_proba(%d): %d\n", i.U, ll_proba(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounter(%d): %d\n", i.U, ll_normalizedCounter(i)) } CompressAccelLogger.logInfo(printInfo + " ll_lowThreshold: %d\n", ll_lowThreshold) CompressAccelLogger.logInfo(printInfo + " ll_lowProbCount: %d\n", ll_lowProbCount) // Takes only one cycle when (predefined_mode_q.io.enq.ready) { when (fse_normalize_corner_case) { dicBuilderState := sLookup if (printInfo == "LL") { for (i <- 0 until 36) { ll_symbolTTDeltaNbBits(i) := LL_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := LL_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 64) { ll_tableU16(i) := LL_DefaultTableU16(i).U } } else if (printInfo == "ML") { for (i <- 0 until 53) { ll_symbolTTDeltaNbBits(i) := ML_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := ML_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 64) { ll_tableU16(i) := ML_DefaultTableU16(i).U } } else if (printInfo == "OF") { for (i <- 0 until 29) { ll_symbolTTDeltaNbBits(i) := OF_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := OF_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 32) { ll_tableU16(i) := OF_DefaultTableU16(i).U } } } .otherwise { dicBuilderState := sBuildCTableSymbolStartPositions } } } is (sBuildCTableSymbolStartPositions) { ll_normCountEqsNegOneCumul(0) := ll_normCountEqsNegOne(0) for (i <- 1 until maxSymbolLL + 1) { when (ll_normalizedCounterReg(i-1) === neg_one_uint16.U) { ll_normCountEqsNegOne(i-1) := 1.U ll_cumul(i) := ll_cumul(i-1) + 1.U ll_tableSymbol(ll_highThresholdBeforeCumul - ll_normCountEqsNegOneCumul(i-1) + 1.U) := (i-1).U } .otherwise { ll_cumul(i) := ll_cumul(i-1) + ll_normalizedCounterReg(i-1) } ll_normCountEqsNegOneCumul(i) := ll_normCountEqsNegOneCumul(i-1) + ll_normCountEqsNegOne(i) } ll_cumul(ll_maxSV1) := ll_tableSize + 1.U ll_highThresholdAfterCumul := ll_highThresholdBeforeCumul - ll_normCountEqsNegOneSum for (i <- 0 until maxSymbolLL + 1) { ll_cumulReg(i) := ll_cumul(i) } // Takes only one cycle dicBuilderState := sBuildCTableSpreadSymbols } is (sBuildCTableSpreadSymbols) { when (ll_highThresholdAfterCumul === ll_tableSize - 1.U) { ll_s := ll_s + 1.U ll_sv := ll_sv + add.U val n = ll_normalizedCounterReg(ll_s) val write_spread_cnt = n >> 3.U val write_extra = (n & 7.U) =/= 0.U val write_spread_cnt_wrapped = write_spread_cnt +& write_extra.asUInt val write_spread_bytes = write_spread_cnt_wrapped << 3.U ll_pos := ll_pos + n // pos + n for (i <- 0 until LL_SPREAD_TABLE_SIZE) { when ((i.U >= ll_pos) && (i.U < ll_pos + write_spread_bytes)) { val shift_bytes = (i.U - ll_pos)(2, 0) val shift_bits = shift_bytes << 3.U ll_spread(i) := ll_sv >> shift_bits } } when (ll_s === ll_maxSV1) { for (i <- 0 until LL_TABLESIZE) { val uPosition = (i.U * ll_fse_tablestep) & ll_tableMask when ((i.U >= ll_pos) && (i.U < ll_pos + write_spread_bytes)) { val shift_bytes = (i.U - ll_pos)(2, 0) val shift_bits = shift_bytes << 3.U ll_tableSymbol(uPosition) := ll_sv >> shift_bits } .otherwise { ll_tableSymbol(uPosition) := ll_spread(i) } } dicBuilderState := sBuildCTableBuildTable ll_s := 0.U } } .otherwise { CompressAccelLogger.logInfo(printInfo + " Doesn't support low probability cases") assert(false.B, "Doesn't support low probability cases") } } is (sBuildCTableBuildTable) { // 2^tableLogLL cycles ll_s := ll_s + 1.U val s = ll_tableSymbol(ll_s) ll_cumulReg(s) := ll_cumulReg(s) + 1.U ll_tableU16(ll_cumulReg(s)) := ll_tableSize + ll_s when (ll_s === ll_tableSize - 1.U) { ll_s := 0.U dicBuilderState := sBuildCTableSymbolTT } } is (sBuildCTableSymbolTT) { ll_s := ll_s + 1.U when (normCount === 0.U) { ll_symbolTTDeltaNbBits(ll_s) := (((tableLogLL + 1) << 16) - (1 << tableLogLL)).U ll_symbolTTDeltaFindState(ll_s) := 0.S } .elsewhen (normCount === 1.U) { // ignore low-prob (normCount === -1.S) for now ll_symbolTTDeltaNbBits(ll_s) := (((tableLogLL) << 16) - (1 << tableLogLL)).U ll_symbolTTDeltaFindState(ll_s) := (ll_total - 1.U).asSInt ll_total := ll_total + 1.U } .otherwise { val maxBitsOut = tableLogLL.U - BIT_highbit32(normCount - 1.U) val minStatePlus = normCount << maxBitsOut(3, 0) ll_symbolTTDeltaNbBits(ll_s) := (maxBitsOut << 16.U) - minStatePlus ll_symbolTTDeltaFindState(ll_s) := (ll_total - normCount).asSInt ll_total := ll_total + normCount } when (ll_s === ll_max_symbol_value) { ll_s := 0.U dicBuilderState := sWriteCTable } } is (sWriteCTable) { when (!write_header_started) { write_header_started := true.B remaining := ll_tableSize + 1.U threshold := ll_tableSize nbBits := (tableLogLL + 1).U bitStream := (tableLogLL - FSE_MIN_TABLELOG).U bitCount := 4.U } .otherwise { when ((symbol < alphabetSize) && (remaining > 1.U)) { when(writeBitStream) { when (io.header_writes.ready) { writeBitStream := false.B bitStream := bitStream >> 16.U bitCount := bitCount - 16.U CompressAccelLogger.logInfo(printInfo + " bitStream(7, 0): %d\n", bitStream(7, 0)) CompressAccelLogger.logInfo(printInfo + " bitStream(15, 8): %d\n", bitStream(15, 8)) } io.header_writes.valid := true.B io.header_writes.bits.data := bitStream io.header_writes.bits.validbytes := 2.U } .elsewhen (writeBitStreamPrev0) { when (io.header_writes.ready) { writeBitStreamPrev0 := false.B bitStream := bitStream >> 16.U CompressAccelLogger.logInfo(printInfo + "writeBitStreamPrev0") } io.header_writes.valid := true.B io.header_writes.bits.data := bitStream io.header_writes.bits.validbytes := 2.U } .elsewhen (previousIs0) { when (!start_initialized) { start := symbol start_initialized := true.B CompressAccelLogger.logInfo(printInfo + " start: %d\n", symbol) } .elsewhen (!skip_zeros_done) { val cur_norm_count = ll_normalizedCounterReg(symbol) when (cur_norm_count =/= 0.U) { skip_zeros_done := true.B CompressAccelLogger.logInfo(printInfo + " symbol: %d\n", symbol) } .otherwise { symbol := symbol + 1.U when ((symbol + 1.U) === alphabetSize) { assert(false.B, printInfo + " Wrong distribution for FSE compression\n"); } } } .elsewhen (!skip_24_done) { when (symbol >= start + 24.U) { start := start + 24.U bitStream := bitStream + (BigInt("FFFF", 16).U << bitCount) writeBitStreamPrev0 := true.B } .otherwise { skip_24_done := true.B CompressAccelLogger.logInfo(printInfo + " skip_24_done\n") } CompressAccelLogger.logInfo(printInfo + " skip_24\n") } .elsewhen (!skip_3_done) { when (symbol >= start + 3.U) { start := start + 3.U bitStream := bitStream + (3.U << bitCount) bitCount := bitCount + 2.U } .otherwise { skip_3_done := true.B CompressAccelLogger.logInfo(printInfo + " skip_3_done\n") } CompressAccelLogger.logInfo(printInfo + " skip_3\n") } .otherwise { bitStream := bitStream + ((symbol - start) << bitCount) bitCount := bitCount + 2.U previousIs0 := false.B start := 0.U start_initialized := false.B skip_zeros_done := false.B skip_24_done := false.B skip_3_done := false.B when (bitCount > 16.U) { writeBitStream := true.B } CompressAccelLogger.logInfo(printInfo + " previousIs0_done\n") } } .otherwise { val count = ll_normalizedCounterReg(symbol) symbol := symbol + 1.U val max = ((threshold << 1.U) - 1.U) - remaining // fse_compress.c 327 ????? // remaining := remaining - Mux(count < 0.S, (-1.S)count, count) val nxt_remaining = remaining - count remaining := nxt_remaining val count1 = count + 1.U val count1_max = Mux(count1 >= threshold, count1 + max, count1) val nxt_bitCount = bitCount + nbBits - Mux(count1_max < max, 1.U, 0.U) bitStream := bitStream + (count1_max << bitCount) bitCount := nxt_bitCount writeBitStream := nxt_bitCount > 16.U previousIs0 := (count1_max === 1.U) assert(remaining >= 1.U, "Not enough remaining for FSE header writes\n") CompressAccelLogger.logInfo(printInfo + " previousIs0: %d\n", (count1_max === 1.U)) CompressAccelLogger.logInfo(printInfo + " alphabetSize: %d\n", alphabetSize) CompressAccelLogger.logInfo(printInfo + " symbol: %d\n", symbol) CompressAccelLogger.logInfo(printInfo + " threshold: %d\n", threshold) CompressAccelLogger.logInfo(printInfo + " max: %d\n", max) CompressAccelLogger.logInfo(printInfo + " remaining: %d\n", remaining) CompressAccelLogger.logInfo(printInfo + " nxt_remaining: %d\n", nxt_remaining) CompressAccelLogger.logInfo(printInfo + " count: %d\n", count) CompressAccelLogger.logInfo(printInfo + " count1_max: %d\n", count1_max) CompressAccelLogger.logInfo(printInfo + " nxt_bitCount: %d\n", nxt_bitCount) CompressAccelLogger.logInfo(printInfo + " writeBitStream: %d\n", writeBitStream) CompressAccelLogger.logInfo(printInfo + " BitStream: 0x%x\n", (bitStream + (count1_max << bitCount))) for (i <- 0 until tableLogLL + 1) { shifted_threshold_small_or_eq_remaining(i) := Mux(nxt_remaining < shifted_thresholds(i), 1.U, 0.U) } threshold := shifted_thresholds(nxt_shifted_threshold_idx) nbBits := nbBits - nxt_shifted_threshold_idx } } .otherwise { io.header_writes.valid := true.B io.header_writes.bits.data := bitStream io.header_writes.bits.validbytes := ((bitCount + 7.U) >> 3.U) if (mark_end_of_header) { io.header_writes.bits.end_of_message := true.B } when (io.header_writes.ready) { dicBuilderState := sLookup bitStream := 0.U bitCount := 0.U } } } } is (sLookup) { when (print_table) { print_table := false.B // for (i <- 0 until maxSymbolLL + 1) { // CompressAccelLogger.logInfo(printInfo + " ll_count(%d): %d\n", i.U, ll_count(i)) // } CompressAccelLogger.logInfo(printInfo + " ll_max_symbol_value: %d\n", ll_max_symbol_value) for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounterReg(%d): %d\n", i.U, ll_normalizedCounterReg(i)) } for (i <- 0 until LL_TABLESIZE) { CompressAccelLogger.logInfo(printInfo + " ll_tableSymbol(%d): %d\n", i.U, ll_tableSymbol(i)) } CompressAccelLogger.logInfo(printInfo + " ll_highThresholdAfterCumul: %d\n", ll_highThresholdAfterCumul) for (i <- 0 until LL_SPREAD_TABLE_SIZE) { CompressAccelLogger.logInfo(printInfo + " ll_spread(%d): %d\n", i.U, ll_spread(i)) } CompressAccelLogger.logInfo(printInfo + " ll_fse_tablestep: %d\n", ll_fse_tablestep) for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " symbolTTDeltaNbBits(%d): %d, ll_symbolTTDeltaFindState(%d): %d\n", i.U, ll_symbolTTDeltaNbBits(i), i.U, ll_symbolTTDeltaFindState(i).asSInt) } for (i <- 0 until (1 << tableLogLL)) { CompressAccelLogger.logInfo(printInfo + " ll_tableU16(%d): %d\n", i.U, ll_tableU16(i)) } } when (io.lookup_done.valid) { io.nb_seq.ready := true.B dicBuilderState := sIdle } } } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /* Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File Util.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants object CompressAccelLogger { def logInfo(format: String, args: Bits)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_)) } def logCritical(format: String, args: Bits)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U if (p(CompressAccelPrintfEnable)) { printf(midas.targetutils.SynthesizePrintf("cy: %d, ", loginfo_cycles)) printf(midas.targetutils.SynthesizePrintf(format, args:_)) } else { printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_)) } } def logWaveStyle(format: String, args: Bits)(implicit p: Parameters) { } } object CompressAccelParams { }	module FSECompressorDicBuilder_2( // @[FSECompressorDicBuilder.scala:39:7] input clock, // @[FSECompressorDicBuilder.scala:39:7] input reset, // @[FSECompressorDicBuilder.scala:39:7] output io_nb_seq_ready, // @[FSECompressorDicBuilder.scala:48:14] input io_nb_seq_valid, // @[FSECompressorDicBuilder.scala:48:14] input [63:0] io_nb_seq_bits, // @[FSECompressorDicBuilder.scala:48:14] output [5:0] io_ll_stream_user_consumed_bytes, // @[FSECompressorDicBuilder.scala:48:14] input [5:0] io_ll_stream_available_output_bytes, // @[FSECompressorDicBuilder.scala:48:14] input io_ll_stream_output_valid, // @[FSECompressorDicBuilder.scala:48:14] output io_ll_stream_output_ready, // @[FSECompressorDicBuilder.scala:48:14] input [255:0] io_ll_stream_output_data, // @[FSECompressorDicBuilder.scala:48:14] input io_ll_stream_output_last_chunk, // @[FSECompressorDicBuilder.scala:48:14] input io_ll_table_log_ready, // @[FSECompressorDicBuilder.scala:48:14] output io_ll_table_log_valid, // @[FSECompressorDicBuilder.scala:48:14] output [3:0] io_ll_table_log_bits, // @[FSECompressorDicBuilder.scala:48:14] output io_symbol_info_0_ready, // @[FSECompressorDicBuilder.scala:48:14] input io_symbol_info_0_valid, // @[FSECompressorDicBuilder.scala:48:14] input [7:0] io_symbol_info_0_bits_symbol, // @[FSECompressorDicBuilder.scala:48:14] input io_symbol_info_0_bits_last_symbol, // @[FSECompressorDicBuilder.scala:48:14] input io_symbolTT_info_0_ready, // @[FSECompressorDicBuilder.scala:48:14] output io_symbolTT_info_0_valid, // @[FSECompressorDicBuilder.scala:48:14] output [31:0] io_symbolTT_info_0_bits_nbbit, // @[FSECompressorDicBuilder.scala:48:14] output [31:0] io_symbolTT_info_0_bits_findstate, // @[FSECompressorDicBuilder.scala:48:14] output io_symbolTT_info_0_bits_from_last_symbol, // @[FSECompressorDicBuilder.scala:48:14] input [15:0] io_state_table_idx_0, // @[FSECompressorDicBuilder.scala:48:14] output io_new_state_0_valid, // @[FSECompressorDicBuilder.scala:48:14] output [15:0] io_new_state_0_bits, // @[FSECompressorDicBuilder.scala:48:14] input io_header_writes_ready, // @[FSECompressorDicBuilder.scala:48:14] output io_header_writes_valid, // @[FSECompressorDicBuilder.scala:48:14] output [255:0] io_header_writes_bits_data, // @[FSECompressorDicBuilder.scala:48:14] output [5:0] io_header_writes_bits_validbytes, // @[FSECompressorDicBuilder.scala:48:14] output io_header_writes_bits_end_of_message, // @[FSECompressorDicBuilder.scala:48:14] input io_predefined_mode_ready, // @[FSECompressorDicBuilder.scala:48:14] output io_predefined_mode_valid, // @[FSECompressorDicBuilder.scala:48:14] output io_predefined_mode_bits, // @[FSECompressorDicBuilder.scala:48:14] input io_lookup_done_valid // @[FSECompressorDicBuilder.scala:48:14] ); wire [15:0] ll_normalizedCounter_30; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_29; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_28; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_27; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_26; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_25; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_24; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_23; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_22; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_21; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_20; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_19; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_18; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_17; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_16; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_15; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_14; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_13; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_12; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_11; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_10; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_9; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_8; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_7; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_6; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_5; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_4; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_3; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_2; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_1; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_0; // @[FSECompressorDicBuilder.scala:277:38] wire _predefined_mode_q_io_enq_ready; // @[FSECompressorDicBuilder.scala:141:33] wire io_nb_seq_valid_0 = io_nb_seq_valid; // @[FSECompressorDicBuilder.scala:39:7] wire [63:0] io_nb_seq_bits_0 = io_nb_seq_bits; // @[FSECompressorDicBuilder.scala:39:7] wire [5:0] io_ll_stream_available_output_bytes_0 = io_ll_stream_available_output_bytes; // @[FSECompressorDicBuilder.scala:39:7] wire io_ll_stream_output_valid_0 = io_ll_stream_output_valid; // @[FSECompressorDicBuilder.scala:39:7] wire [255:0] io_ll_stream_output_data_0 = io_ll_stream_output_data; // @[FSECompressorDicBuilder.scala:39:7] wire io_ll_stream_output_last_chunk_0 = io_ll_stream_output_last_chunk; // @[FSECompressorDicBuilder.scala:39:7] wire io_ll_table_log_ready_0 = io_ll_table_log_ready; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbol_info_0_valid_0 = io_symbol_info_0_valid; // @[FSECompressorDicBuilder.scala:39:7] wire [7:0] io_symbol_info_0_bits_symbol_0 = io_symbol_info_0_bits_symbol; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbol_info_0_bits_last_symbol_0 = io_symbol_info_0_bits_last_symbol; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbolTT_info_0_ready_0 = io_symbolTT_info_0_ready; // @[FSECompressorDicBuilder.scala:39:7] wire [15:0] io_state_table_idx_0_0 = io_state_table_idx_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_header_writes_ready_0 = io_header_writes_ready; // @[FSECompressorDicBuilder.scala:39:7] wire io_predefined_mode_ready_0 = io_predefined_mode_ready; // @[FSECompressorDicBuilder.scala:39:7] wire io_lookup_done_valid_0 = io_lookup_done_valid; // @[FSECompressorDicBuilder.scala:39:7] wire [31:0] _rtbTable_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_7 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _ll_count_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_7 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_8 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_9 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_10 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_11 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_12 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_13 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_14 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_15 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_16 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_17 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_18 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_19 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_20 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_21 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_22 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_23 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_24 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_25 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_26 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_27 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_28 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_29 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_30 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_31 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_7 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_8 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_9 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_10 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_11 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_12 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_13 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_14 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_15 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_16 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_17 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_18 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_19 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_20 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_21 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_22 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_23 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_24 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_25 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_26 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_27 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_28 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_29 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_30 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_31 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_7 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_8 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_9 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_10 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_11 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_12 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_13 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_14 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_15 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_16 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_17 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_18 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_19 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_20 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_21 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_22 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_23 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_24 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_25 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_26 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_27 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_28 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_29 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_30 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_31 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _shifted_thresholds_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire io_lookup_done_ready = 1'h1; // @[FSECompressorDicBuilder.scala:39:7] wire io_lookup_done_bits = 1'h1; // @[FSECompressorDicBuilder.scala:39:7] wire [6:0] _ll_cumul_T_1 = 7'h41; // @[FSECompressorDicBuilder.scala:703:43] wire [6:0] _remaining_T_1 = 7'h41; // @[FSECompressorDicBuilder.scala:793:35] wire [31:0] _maxBitsOut_highBit_T_46 = 32'hAAAAAAAA; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_41 = 32'h55555555; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_40 = 32'h66666666; // @[FSECompressorDicBuilder.scala:52:49] wire [30:0] _maxBitsOut_highBit_T_39 = 31'h33333333; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_36 = 32'hCCCCCCCC; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_31 = 32'h33333333; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_30 = 32'h3C3C3C3C; // @[FSECompressorDicBuilder.scala:52:49] wire [29:0] _maxBitsOut_highBit_T_29 = 30'hF0F0F0F; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_26 = 32'hF0F0F0F0; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_21 = 32'hF0F0F0F; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_20 = 32'hFF00FF0; // @[FSECompressorDicBuilder.scala:52:49] wire [27:0] _maxBitsOut_highBit_T_19 = 28'hFF00FF; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_16 = 32'hFF00FF00; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_11 = 32'hFF00FF; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_10 = 32'hFFFF00; // @[FSECompressorDicBuilder.scala:52:49] wire [23:0] _maxBitsOut_highBit_T_9 = 24'hFFFF; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T = 32'hFFFF0000; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_6 = 32'hFFFF0000; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_1 = 32'hFFFF; // @[FSECompressorDicBuilder.scala:52:49] wire _table_WIRE_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_1_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_1_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_1_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_1_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_2_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_2_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_2_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_2_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_3_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_3_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_3_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_3_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_4_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_4_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_4_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_4_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_5_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_5_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_5_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_5_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_6_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_6_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_6_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_6_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_7_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_7_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_7_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_7_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_8_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_8_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_8_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_8_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_9_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_9_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_9_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_9_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_10_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_10_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_10_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_10_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_11_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_11_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_11_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_11_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_12_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_12_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_12_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_12_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_13_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_13_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_13_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_13_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_14_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_14_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_14_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_14_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_15_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_15_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_15_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_15_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_16_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_16_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_16_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_16_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_17_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_17_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_17_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_17_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_18_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_18_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_18_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_18_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_19_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_19_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_19_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_19_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_20_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_20_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_20_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_20_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_21_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_21_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_21_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_21_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_22_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_22_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_22_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_22_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_23_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_23_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_23_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_23_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_24_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_24_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_24_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_24_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_25_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_25_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_25_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_25_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_26_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_26_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_26_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_26_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_27_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_27_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_27_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_27_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_28_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_28_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_28_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_28_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_29_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_29_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_29_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_29_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_30_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_30_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_30_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_30_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_31_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_31_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_31_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_31_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _has_value_WIRE_0 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_1 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_2 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_3 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_4 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_5 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_6 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_7 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_8 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_9 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_10 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_11 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_12 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_13 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_14 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_15 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_16 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_17 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_18 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_19 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_20 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_21 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_22 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_23 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_24 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_25 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_26 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_27 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_28 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_29 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_30 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_31 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _symbolTT_lookup_fire_and_last_vec_WIRE_0 = 1'h0; // @[FSECompressorDicBuilder.scala:422:59] wire [12:0] uPosition_63 = 13'h15; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_63 = 13'hA95; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_62 = 13'h2A; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_62 = 13'hA6A; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_61 = 13'h3F; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_61 = 13'hA3F; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_60 = 13'h14; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_60 = 13'hA14; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_59 = 13'h29; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_59 = 13'h9E9; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_58 = 13'h3E; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_58 = 13'h9BE; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_57 = 13'h13; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_57 = 13'h993; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_56 = 13'h28; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_56 = 13'h968; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_55 = 13'h3D; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_55 = 13'h93D; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_54 = 13'h12; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_54 = 13'h912; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_53 = 13'h27; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_53 = 13'h8E7; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_52 = 13'h3C; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_52 = 13'h8BC; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_51 = 13'h11; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_51 = 13'h891; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_50 = 13'h26; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_50 = 13'h866; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_49 = 13'h3B; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_49 = 13'h83B; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_48 = 13'h10; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_48 = 13'h810; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_47 = 13'h25; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_47 = 13'h7E5; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_46 = 13'h3A; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_46 = 13'h7BA; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_45 = 13'hF; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_45 = 13'h78F; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_44 = 13'h24; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_44 = 13'h764; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_43 = 13'h39; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_43 = 13'h739; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_42 = 13'hE; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_42 = 13'h70E; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_41 = 13'h23; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_41 = 13'h6E3; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_40 = 13'h38; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_40 = 13'h6B8; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_39 = 13'hD; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_39 = 13'h68D; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_38 = 13'h22; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_38 = 13'h662; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_37 = 13'h37; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_37 = 13'h637; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_36 = 13'hC; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_36 = 13'h60C; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_35 = 13'h21; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_35 = 13'h5E1; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_34 = 13'h36; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_34 = 13'h5B6; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_33 = 13'hB; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_33 = 13'h58B; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_32 = 13'h20; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_32 = 13'h560; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_31 = 12'h35; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_31 = 12'h535; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_30 = 12'hA; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_30 = 12'h50A; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_29 = 12'h1F; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_29 = 12'h4DF; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_28 = 12'h34; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_28 = 12'h4B4; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_27 = 12'h9; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_27 = 12'h489; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_26 = 12'h1E; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_26 = 12'h45E; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_25 = 12'h33; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_25 = 12'h433; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_24 = 12'h8; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_24 = 12'h408; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_23 = 12'h1D; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_23 = 12'h3DD; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_22 = 12'h32; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_22 = 12'h3B2; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_21 = 12'h7; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_21 = 12'h387; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_20 = 12'h1C; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_20 = 12'h35C; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_19 = 12'h31; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_19 = 12'h331; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_18 = 12'h6; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_18 = 12'h306; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_17 = 12'h1B; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_17 = 12'h2DB; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_16 = 12'h30; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_16 = 12'h2B0; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_15 = 11'h5; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_15 = 11'h285; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_14 = 11'h1A; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_14 = 11'h25A; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_13 = 11'h2F; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_13 = 11'h22F; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_12 = 11'h4; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_12 = 11'h204; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_11 = 11'h19; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_11 = 11'h1D9; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_10 = 11'h2E; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_10 = 11'h1AE; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_9 = 11'h3; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_9 = 11'h183; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_8 = 11'h18; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_8 = 11'h158; // @[FSECompressorDicBuilder.scala:736:34] wire [9:0] uPosition_7 = 10'h2D; // @[FSECompressorDicBuilder.scala:736:54] wire [9:0] _uPosition_T_7 = 10'h12D; // @[FSECompressorDicBuilder.scala:736:34] wire [9:0] uPosition_6 = 10'h2; // @[FSECompressorDicBuilder.scala:736:54] wire [9:0] _uPosition_T_6 = 10'h102; // @[FSECompressorDicBuilder.scala:736:34] wire [9:0] uPosition_5 = 10'h17; // @[FSECompressorDicBuilder.scala:736:54] wire [9:0] _uPosition_T_5 = 10'hD7; // @[FSECompressorDicBuilder.scala:736:34] wire [9:0] uPosition_4 = 10'h2C; // @[FSECompressorDicBuilder.scala:736:54] wire [9:0] _uPosition_T_4 = 10'hAC; // @[FSECompressorDicBuilder.scala:736:34] wire [8:0] uPosition_3 = 9'h1; // @[FSECompressorDicBuilder.scala:736:54] wire [8:0] _uPosition_T_3 = 9'h81; // @[FSECompressorDicBuilder.scala:736:34] wire [8:0] uPosition_2 = 9'h16; // @[FSECompressorDicBuilder.scala:736:54] wire [8:0] _uPosition_T_2 = 9'h56; // @[FSECompressorDicBuilder.scala:736:34] wire [7:0] _ll_fse_tablestep_T_4 = 8'h2B; // @[FSECompressorDicBuilder.scala:405:72] wire [7:0] _uPosition_T_1 = 8'h2B; // @[FSECompressorDicBuilder.scala:736:34] wire [7:0] uPosition_1 = 8'h2B; // @[FSECompressorDicBuilder.scala:736:54] wire [7:0] _input_ll_symbols_WIRE_0 = 8'h0; // @[FSECompressorDicBuilder.scala:172:42] wire [7:0] _input_ll_symbols_WIRE_1 = 8'h0; // @[FSECompressorDicBuilder.scala:172:42] wire [7:0] _input_ll_symbols_WIRE_2 = 8'h0; // @[FSECompressorDicBuilder.scala:172:42] wire [7:0] _input_ll_symbols_WIRE_3 = 8'h0; // @[FSECompressorDicBuilder.scala:172:42] wire [7:0] _ll_tableSymbol_WIRE_0 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_1 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_2 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_3 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_4 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_5 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_6 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_7 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_8 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_9 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_10 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_11 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_12 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_13 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_14 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_15 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_16 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_17 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_18 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_19 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_20 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_21 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_22 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_23 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_24 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_25 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_26 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_27 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_28 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_29 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_30 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_31 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_32 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_33 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_34 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_35 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_36 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_37 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_38 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_39 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_40 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_41 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_42 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_43 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_44 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_45 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_46 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_47 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_48 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_49 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_50 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_51 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_52 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_53 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_54 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_55 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_56 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_57 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_58 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_59 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_60 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_61 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_62 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_63 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_normCountEqsNegOne_WIRE_0 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_1 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_2 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_3 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_4 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_5 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_6 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_7 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_8 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_9 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_10 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_11 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_12 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_13 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_14 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_15 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_16 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_17 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_18 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_19 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_20 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_21 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_22 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_23 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_24 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_25 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_26 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_27 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_28 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_29 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_30 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_31 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] ll_normCountEqsNegOne_31 = 8'h0; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_0 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_1 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_2 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_3 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_4 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_5 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_6 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_7 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_8 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_9 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_10 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_11 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_12 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_13 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_14 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_15 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_16 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_17 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_18 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_19 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_20 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_21 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_22 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_23 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_24 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_25 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_26 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_27 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_28 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_29 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_30 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_31 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_spread_WIRE_0 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_1 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_2 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_3 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_4 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_5 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_6 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_7 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_8 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_9 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_10 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_11 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_12 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_13 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_14 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_15 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_16 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_17 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_18 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_19 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_20 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_21 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_22 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_23 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_24 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_25 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_26 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_27 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_28 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_29 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_30 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_31 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_32 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_33 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_34 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_35 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_36 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_37 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_38 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_39 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_40 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_41 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_42 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_43 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_44 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_45 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_46 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_47 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_48 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_49 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_50 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_51 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_52 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_53 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_54 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_55 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_56 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_57 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_58 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_59 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_60 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_61 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_62 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_63 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_64 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_65 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_66 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_67 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_68 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_69 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_70 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_71 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _uPosition_T = 8'h0; // @[FSECompressorDicBuilder.scala:736:34] wire [7:0] uPosition = 8'h0; // @[FSECompressorDicBuilder.scala:736:54] wire [15:0] _ll_proba_base_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_normalizedCounter_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterIdx_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] ll_normalizedCounterIdx_0 = 16'h0; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] _ll_normalizedCounterReg_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_cumul_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumulReg_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_tableU16_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_32 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_33 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_34 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_35 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_36 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_37 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_38 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_39 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_40 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_41 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_42 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_43 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_44 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_45 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_46 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_47 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_48 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_49 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_50 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_51 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_52 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_53 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_54 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_55 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_56 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_57 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_58 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_59 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_60 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_61 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_62 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_63 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [6:0] ll_fse_tablestep = 7'h2B; // @[FSECompressorDicBuilder.scala:405:72] wire [6:0] _ll_fse_tablestep_T_3 = 7'h28; // @[FSECompressorDicBuilder.scala:405:48] wire [7:0] _ll_fse_tablestep_T_2 = 8'h28; // @[FSECompressorDicBuilder.scala:405:48] wire [31:0] ll_highThresholdBeforeCumul = 32'h3F; // @[FSECompressorDicBuilder.scala:385:45] wire [6:0] ll_tableMask = 7'h3F; // @[FSECompressorDicBuilder.scala:381:35] wire [6:0] _ll_highThresholdBeforeCumul_T_1 = 7'h3F; // @[FSECompressorDicBuilder.scala:386:47] wire [15:0] ll_normalizedCounterIdx_31 = 16'h1F; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_30 = 16'h1E; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_29 = 16'h1D; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_28 = 16'h1C; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_27 = 16'h1B; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_26 = 16'h1A; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_25 = 16'h19; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_24 = 16'h18; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_23 = 16'h17; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_22 = 16'h16; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_21 = 16'h15; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_20 = 16'h14; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_19 = 16'h13; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_18 = 16'h12; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_17 = 16'h11; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_16 = 16'h10; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_15 = 16'hF; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_14 = 16'hE; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_13 = 16'hD; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_12 = 16'hC; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_11 = 16'hB; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_10 = 16'hA; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_9 = 16'h9; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_8 = 16'h8; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_7 = 16'h7; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_6 = 16'h6; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_5 = 16'h5; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_4 = 16'h4; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_3 = 16'h3; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_2 = 16'h2; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_1 = 16'h1; // @[FSECompressorDicBuilder.scala:301:41] wire [63:0] ll_vStep = 64'h1000000000; // @[FSECompressorDicBuilder.scala:257:22] wire [127:0] _ll_vStep_T = 128'h1000000000; // @[FSECompressorDicBuilder.scala:258:19] wire [6:0] ll_scale_20 = 7'h24; // @[FSECompressorDicBuilder.scala:255:25] wire [6:0] _ll_scale_20_T_1 = 7'h24; // @[FSECompressorDicBuilder.scala:256:27] wire [7:0] _ll_scale_20_T = 8'h24; // @[FSECompressorDicBuilder.scala:256:27] wire [6:0] ll_scale = 7'h38; // @[FSECompressorDicBuilder.scala:251:22] wire [6:0] _ll_scale_T = 7'h38; // @[FSECompressorDicBuilder.scala:252:20] wire [5:0] _ll_scale_T_1 = 6'h38; // @[FSECompressorDicBuilder.scala:252:20] wire [7:0] _ll_cumul_T = 8'h41; // @[FSECompressorDicBuilder.scala:703:43] wire [7:0] _remaining_T = 8'h41; // @[FSECompressorDicBuilder.scala:793:35] wire [6:0] _ll_fse_tablestep_T_1 = 7'h8; // @[FSECompressorDicBuilder.scala:405:64] wire [6:0] _ll_fse_tablestep_T = 7'h20; // @[FSECompressorDicBuilder.scala:405:40] wire [7:0] _ll_tableMask_T = 8'h3F; // @[FSECompressorDicBuilder.scala:381:35] wire [7:0] _ll_highThresholdBeforeCumul_T = 8'h3F; // @[FSECompressorDicBuilder.scala:386:47] wire [2:0] _stat_sum_WIRE_0 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_1 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_2 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_3 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_4 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_5 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_6 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_7 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_8 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_9 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_10 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_11 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_12 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_13 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_14 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_15 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_16 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_17 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_18 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_19 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_20 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_21 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_22 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_23 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_24 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_25 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_26 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_27 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_28 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_29 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_30 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_31 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [63:0] _ll_count_times_step_WIRE_0 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_1 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_2 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_3 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_4 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_5 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_6 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_7 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_8 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_9 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_10 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_11 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_12 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_13 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_14 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_15 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_16 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_17 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_18 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_19 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_20 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_21 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_22 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_23 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_24 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_25 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_26 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_27 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_28 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_29 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_30 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_31 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [255:0] _input_ll_symbols_0_T = io_ll_stream_output_data_0; // @[FSECompressorDicBuilder.scala:39:7, :174:53] wire _io_ll_table_log_valid_T_2; // @[FSECompressorDicBuilder.scala:453:48] wire _io_symbol_info_0_ready_T; // @[Misc.scala:26:53] wire io_symbolTT_info_0_bits_from_last_symbol_0 = io_symbol_info_0_bits_last_symbol_0; // @[FSECompressorDicBuilder.scala:39:7] wire _io_symbolTT_info_0_valid_T; // @[Misc.scala:26:53] wire [31:0] _io_symbolTT_info_0_bits_findstate_T_1; // @[FSECompressorDicBuilder.scala:435:81] wire _io_new_state_0_valid_T; // @[FSECompressorDicBuilder.scala:438:47] wire io_nb_seq_ready_0; // @[FSECompressorDicBuilder.scala:39:7] wire [5:0] io_ll_stream_user_consumed_bytes_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_ll_stream_output_ready_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_ll_table_log_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire [3:0] io_ll_table_log_bits_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbol_info_0_ready_0; // @[FSECompressorDicBuilder.scala:39:7] wire [31:0] io_symbolTT_info_0_bits_nbbit_0; // @[FSECompressorDicBuilder.scala:39:7] wire [31:0] io_symbolTT_info_0_bits_findstate_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbolTT_info_0_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_new_state_0_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire [15:0] io_new_state_0_bits_0; // @[FSECompressorDicBuilder.scala:39:7] wire [255:0] io_header_writes_bits_data_0; // @[FSECompressorDicBuilder.scala:39:7] wire [5:0] io_header_writes_bits_validbytes_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_header_writes_bits_end_of_message_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_header_writes_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_predefined_mode_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_predefined_mode_bits_0; // @[FSECompressorDicBuilder.scala:39:7] reg rtbTable_initialized; // @[FSECompressorDicBuilder.scala:56:37] reg [31:0] rtbTable_1; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_2; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_3; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_4; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_5; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_6; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_7; // @[FSECompressorDicBuilder.scala:57:25] reg [3:0] dicBuilderState; // @[FSECompressorDicBuilder.scala:156:32] reg [31:0] ll_count_0; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_1; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_2; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_3; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_4; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_5; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_6; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_7; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_8; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_9; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_10; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_11; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_12; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_13; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_14; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_15; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_16; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_17; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_18; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_19; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_20; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_21; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_22; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_23; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_24; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_25; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_26; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_27; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_28; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_29; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_30; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_31; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_max_symbol_value; // @[FSECompressorDicBuilder.scala:170:36] reg [63:0] ll_nbseq_1; // @[FSECompressorDicBuilder.scala:171:27] wire [7:0] input_ll_symbols_0; // @[FSECompressorDicBuilder.scala:172:34] wire [7:0] input_ll_symbols_1; // @[FSECompressorDicBuilder.scala:172:34] wire [7:0] input_ll_symbols_2; // @[FSECompressorDicBuilder.scala:172:34] wire [7:0] input_ll_symbols_3; // @[FSECompressorDicBuilder.scala:172:34] assign input_ll_symbols_0 = _input_ll_symbols_0_T[7:0]; // @[FSECompressorDicBuilder.scala:172:34, :174:{25,53}] wire [255:0] _input_ll_symbols_1_T = {8'h0, io_ll_stream_output_data_0[255:8]}; // @[FSECompressorDicBuilder.scala:39:7, :174:53] assign input_ll_symbols_1 = _input_ll_symbols_1_T[7:0]; // @[FSECompressorDicBuilder.scala:172:34, :174:{25,53}] wire [255:0] _input_ll_symbols_2_T = {16'h0, io_ll_stream_output_data_0[255:16]}; // @[FSECompressorDicBuilder.scala:39:7, :174:53] assign input_ll_symbols_2 = _input_ll_symbols_2_T[7:0]; // @[FSECompressorDicBuilder.scala:172:34, :174:{25,53}] wire [255:0] _input_ll_symbols_3_T = {24'h0, io_ll_stream_output_data_0[255:24]}; // @[FSECompressorDicBuilder.scala:39:7, :174:53] assign input_ll_symbols_3 = _input_ll_symbols_3_T[7:0]; // @[FSECompressorDicBuilder.scala:172:34, :174:{25,53}] wire _table_0_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_0_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_0_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_0_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_0_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_0_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_0_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_0_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_1_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_1_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_1_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_1_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_1_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_1_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_1_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_1_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_2_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_2_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_2_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_2_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_2_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_2_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_2_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_2_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_3_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_3_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_3_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_3_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_3_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_3_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_3_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_3_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_4_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_4_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_4_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_4_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_4_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_4_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_4_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_4_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_5_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_5_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_5_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_5_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_5_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_5_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_5_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_5_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_6_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_6_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_6_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_6_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_6_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_6_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_6_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_6_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_7_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_7_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_7_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_7_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_7_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_7_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_7_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_7_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_8_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_8_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_8_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_8_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_8_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_8_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_8_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_8_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_9_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_9_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_9_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_9_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_9_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_9_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_9_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_9_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_10_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_10_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_10_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_10_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_10_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_10_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_10_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_10_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_11_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_11_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_11_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_11_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_11_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_11_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_11_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_11_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_12_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_12_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_12_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_12_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_12_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_12_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_12_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_12_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_13_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_13_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_13_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_13_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_13_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_13_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_13_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_13_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_14_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_14_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_14_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_14_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_14_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_14_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_14_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_14_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_15_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_15_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_15_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_15_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_15_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_15_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_15_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_15_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_16_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_16_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_16_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_16_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_16_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_16_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_16_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_16_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_17_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_17_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_17_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_17_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_17_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_17_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_17_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_17_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_18_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_18_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_18_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_18_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_18_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_18_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_18_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_18_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_19_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_19_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_19_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_19_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_19_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_19_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_19_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_19_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_20_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_20_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_20_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_20_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_20_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_20_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_20_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_20_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_21_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_21_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_21_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_21_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_21_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_21_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_21_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_21_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_22_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_22_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_22_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_22_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_22_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_22_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_22_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_22_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_23_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_23_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_23_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_23_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_23_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_23_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_23_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_23_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_24_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_24_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_24_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_24_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_24_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_24_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_24_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_24_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_25_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_25_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_25_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_25_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_25_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_25_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_25_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_25_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_26_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_26_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_26_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_26_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_26_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_26_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_26_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_26_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_27_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_27_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_27_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_27_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_27_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_27_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_27_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_27_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_28_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_28_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_28_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_28_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_28_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_28_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_28_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_28_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_29_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_29_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_29_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_29_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_29_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_29_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_29_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_29_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_30_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_30_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_30_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_30_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_30_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_30_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_30_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_30_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_31_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_31_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_31_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_31_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_31_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_31_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_31_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_31_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_0_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_0_0_T_1 = input_ll_symbols_0 == 8'h0; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_0_0_T_2 = _table_0_0_T & _table_0_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_0_0_T_3 = _table_0_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_0_0 = _table_0_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_0_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_0_1_T_1 = input_ll_symbols_1 == 8'h0; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_0_1_T_2 = _table_0_1_T & _table_0_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_0_1_T_3 = _table_0_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_0_1 = _table_0_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _GEN = io_ll_stream_available_output_bytes_0 > 6'h2; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_0_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_0_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_1_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_1_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_2_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_2_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_3_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_3_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_4_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_4_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_5_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_5_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_6_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_6_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_7_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_7_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_8_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_8_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_9_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_9_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_10_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_10_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_11_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_11_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_12_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_12_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_13_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_13_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_14_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_14_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_15_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_15_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_16_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_16_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_17_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_17_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_18_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_18_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_19_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_19_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_20_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_20_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_21_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_21_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_22_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_22_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_23_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_23_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_24_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_24_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_25_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_25_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_26_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_26_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_27_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_27_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_28_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_28_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_29_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_29_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_30_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_30_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_31_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_31_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_0_2_T_1 = input_ll_symbols_2 == 8'h0; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_0_2_T_2 = _table_0_2_T & _table_0_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_0_2_T_3 = _table_0_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_0_2 = _table_0_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_0_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_0_3_T_1 = input_ll_symbols_3 == 8'h0; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_0_3_T_2 = _table_0_3_T & _table_0_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_0_3_T_3 = _table_0_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_0_3 = _table_0_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_1_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_1_0_T_1 = input_ll_symbols_0 == 8'h1; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_1_0_T_2 = _table_1_0_T & _table_1_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_1_0_T_3 = _table_1_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_1_0 = _table_1_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_1_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_1_1_T_1 = input_ll_symbols_1 == 8'h1; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_1_1_T_2 = _table_1_1_T & _table_1_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_1_1_T_3 = _table_1_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_1_1 = _table_1_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_1_2_T_1 = input_ll_symbols_2 == 8'h1; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_1_2_T_2 = _table_1_2_T & _table_1_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_1_2_T_3 = _table_1_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_1_2 = _table_1_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_1_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_1_3_T_1 = input_ll_symbols_3 == 8'h1; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_1_3_T_2 = _table_1_3_T & _table_1_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_1_3_T_3 = _table_1_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_1_3 = _table_1_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_2_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_2_0_T_1 = input_ll_symbols_0 == 8'h2; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_2_0_T_2 = _table_2_0_T & _table_2_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_2_0_T_3 = _table_2_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_2_0 = _table_2_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_2_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_2_1_T_1 = input_ll_symbols_1 == 8'h2; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_2_1_T_2 = _table_2_1_T & _table_2_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_2_1_T_3 = _table_2_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_2_1 = _table_2_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_2_2_T_1 = input_ll_symbols_2 == 8'h2; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_2_2_T_2 = _table_2_2_T & _table_2_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_2_2_T_3 = _table_2_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_2_2 = _table_2_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_2_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_2_3_T_1 = input_ll_symbols_3 == 8'h2; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_2_3_T_2 = _table_2_3_T & _table_2_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_2_3_T_3 = _table_2_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_2_3 = _table_2_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_3_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_3_0_T_1 = input_ll_symbols_0 == 8'h3; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_3_0_T_2 = _table_3_0_T & _table_3_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_3_0_T_3 = _table_3_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_3_0 = _table_3_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_3_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_3_1_T_1 = input_ll_symbols_1 == 8'h3; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_3_1_T_2 = _table_3_1_T & _table_3_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_3_1_T_3 = _table_3_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_3_1 = _table_3_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_3_2_T_1 = input_ll_symbols_2 == 8'h3; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_3_2_T_2 = _table_3_2_T & _table_3_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_3_2_T_3 = _table_3_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_3_2 = _table_3_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_3_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_3_3_T_1 = input_ll_symbols_3 == 8'h3; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_3_3_T_2 = _table_3_3_T & _table_3_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_3_3_T_3 = _table_3_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_3_3 = _table_3_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_4_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_4_0_T_1 = input_ll_symbols_0 == 8'h4; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_4_0_T_2 = _table_4_0_T & _table_4_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_4_0_T_3 = _table_4_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_4_0 = _table_4_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_4_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_4_1_T_1 = input_ll_symbols_1 == 8'h4; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_4_1_T_2 = _table_4_1_T & _table_4_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_4_1_T_3 = _table_4_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_4_1 = _table_4_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_4_2_T_1 = input_ll_symbols_2 == 8'h4; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_4_2_T_2 = _table_4_2_T & _table_4_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_4_2_T_3 = _table_4_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_4_2 = _table_4_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_4_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_4_3_T_1 = input_ll_symbols_3 == 8'h4; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_4_3_T_2 = _table_4_3_T & _table_4_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_4_3_T_3 = _table_4_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_4_3 = _table_4_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_5_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_5_0_T_1 = input_ll_symbols_0 == 8'h5; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_5_0_T_2 = _table_5_0_T & _table_5_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_5_0_T_3 = _table_5_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_5_0 = _table_5_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_5_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_5_1_T_1 = input_ll_symbols_1 == 8'h5; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_5_1_T_2 = _table_5_1_T & _table_5_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_5_1_T_3 = _table_5_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_5_1 = _table_5_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_5_2_T_1 = input_ll_symbols_2 == 8'h5; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_5_2_T_2 = _table_5_2_T & _table_5_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_5_2_T_3 = _table_5_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_5_2 = _table_5_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_5_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_5_3_T_1 = input_ll_symbols_3 == 8'h5; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_5_3_T_2 = _table_5_3_T & _table_5_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_5_3_T_3 = _table_5_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_5_3 = _table_5_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_6_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_6_0_T_1 = input_ll_symbols_0 == 8'h6; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_6_0_T_2 = _table_6_0_T & _table_6_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_6_0_T_3 = _table_6_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_6_0 = _table_6_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_6_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_6_1_T_1 = input_ll_symbols_1 == 8'h6; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_6_1_T_2 = _table_6_1_T & _table_6_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_6_1_T_3 = _table_6_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_6_1 = _table_6_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_6_2_T_1 = input_ll_symbols_2 == 8'h6; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_6_2_T_2 = _table_6_2_T & _table_6_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_6_2_T_3 = _table_6_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_6_2 = _table_6_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_6_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_6_3_T_1 = input_ll_symbols_3 == 8'h6; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_6_3_T_2 = _table_6_3_T & _table_6_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_6_3_T_3 = _table_6_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_6_3 = _table_6_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_7_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_7_0_T_1 = input_ll_symbols_0 == 8'h7; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_7_0_T_2 = _table_7_0_T & _table_7_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_7_0_T_3 = _table_7_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_7_0 = _table_7_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_7_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_7_1_T_1 = input_ll_symbols_1 == 8'h7; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_7_1_T_2 = _table_7_1_T & _table_7_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_7_1_T_3 = _table_7_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_7_1 = _table_7_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_7_2_T_1 = input_ll_symbols_2 == 8'h7; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_7_2_T_2 = _table_7_2_T & _table_7_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_7_2_T_3 = _table_7_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_7_2 = _table_7_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_7_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_7_3_T_1 = input_ll_symbols_3 == 8'h7; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_7_3_T_2 = _table_7_3_T & _table_7_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_7_3_T_3 = _table_7_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_7_3 = _table_7_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_8_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_8_0_T_1 = input_ll_symbols_0 == 8'h8; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_8_0_T_2 = _table_8_0_T & _table_8_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_8_0_T_3 = _table_8_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_8_0 = _table_8_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_8_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_8_1_T_1 = input_ll_symbols_1 == 8'h8; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_8_1_T_2 = _table_8_1_T & _table_8_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_8_1_T_3 = _table_8_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_8_1 = _table_8_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_8_2_T_1 = input_ll_symbols_2 == 8'h8; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_8_2_T_2 = _table_8_2_T & _table_8_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_8_2_T_3 = _table_8_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_8_2 = _table_8_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_8_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_8_3_T_1 = input_ll_symbols_3 == 8'h8; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_8_3_T_2 = _table_8_3_T & _table_8_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_8_3_T_3 = _table_8_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_8_3 = _table_8_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_9_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_9_0_T_1 = input_ll_symbols_0 == 8'h9; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_9_0_T_2 = _table_9_0_T & _table_9_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_9_0_T_3 = _table_9_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_9_0 = _table_9_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_9_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_9_1_T_1 = input_ll_symbols_1 == 8'h9; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_9_1_T_2 = _table_9_1_T & _table_9_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_9_1_T_3 = _table_9_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_9_1 = _table_9_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_9_2_T_1 = input_ll_symbols_2 == 8'h9; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_9_2_T_2 = _table_9_2_T & _table_9_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_9_2_T_3 = _table_9_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_9_2 = _table_9_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_9_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_9_3_T_1 = input_ll_symbols_3 == 8'h9; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_9_3_T_2 = _table_9_3_T & _table_9_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_9_3_T_3 = _table_9_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_9_3 = _table_9_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_10_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_10_0_T_1 = input_ll_symbols_0 == 8'hA; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_10_0_T_2 = _table_10_0_T & _table_10_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_10_0_T_3 = _table_10_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_10_0 = _table_10_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_10_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_10_1_T_1 = input_ll_symbols_1 == 8'hA; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_10_1_T_2 = _table_10_1_T & _table_10_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_10_1_T_3 = _table_10_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_10_1 = _table_10_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_10_2_T_1 = input_ll_symbols_2 == 8'hA; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_10_2_T_2 = _table_10_2_T & _table_10_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_10_2_T_3 = _table_10_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_10_2 = _table_10_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_10_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_10_3_T_1 = input_ll_symbols_3 == 8'hA; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_10_3_T_2 = _table_10_3_T & _table_10_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_10_3_T_3 = _table_10_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_10_3 = _table_10_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_11_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_11_0_T_1 = input_ll_symbols_0 == 8'hB; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_11_0_T_2 = _table_11_0_T & _table_11_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_11_0_T_3 = _table_11_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_11_0 = _table_11_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_11_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_11_1_T_1 = input_ll_symbols_1 == 8'hB; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_11_1_T_2 = _table_11_1_T & _table_11_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_11_1_T_3 = _table_11_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_11_1 = _table_11_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_11_2_T_1 = input_ll_symbols_2 == 8'hB; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_11_2_T_2 = _table_11_2_T & _table_11_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_11_2_T_3 = _table_11_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_11_2 = _table_11_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_11_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_11_3_T_1 = input_ll_symbols_3 == 8'hB; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_11_3_T_2 = _table_11_3_T & _table_11_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_11_3_T_3 = _table_11_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_11_3 = _table_11_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_12_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_12_0_T_1 = input_ll_symbols_0 == 8'hC; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_12_0_T_2 = _table_12_0_T & _table_12_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_12_0_T_3 = _table_12_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_12_0 = _table_12_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_12_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_12_1_T_1 = input_ll_symbols_1 == 8'hC; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_12_1_T_2 = _table_12_1_T & _table_12_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_12_1_T_3 = _table_12_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_12_1 = _table_12_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_12_2_T_1 = input_ll_symbols_2 == 8'hC; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_12_2_T_2 = _table_12_2_T & _table_12_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_12_2_T_3 = _table_12_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_12_2 = _table_12_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_12_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_12_3_T_1 = input_ll_symbols_3 == 8'hC; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_12_3_T_2 = _table_12_3_T & _table_12_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_12_3_T_3 = _table_12_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_12_3 = _table_12_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_13_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_13_0_T_1 = input_ll_symbols_0 == 8'hD; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_13_0_T_2 = _table_13_0_T & _table_13_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_13_0_T_3 = _table_13_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_13_0 = _table_13_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_13_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_13_1_T_1 = input_ll_symbols_1 == 8'hD; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_13_1_T_2 = _table_13_1_T & _table_13_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_13_1_T_3 = _table_13_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_13_1 = _table_13_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_13_2_T_1 = input_ll_symbols_2 == 8'hD; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_13_2_T_2 = _table_13_2_T & _table_13_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_13_2_T_3 = _table_13_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_13_2 = _table_13_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_13_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_13_3_T_1 = input_ll_symbols_3 == 8'hD; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_13_3_T_2 = _table_13_3_T & _table_13_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_13_3_T_3 = _table_13_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_13_3 = _table_13_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_14_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_14_0_T_1 = input_ll_symbols_0 == 8'hE; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_14_0_T_2 = _table_14_0_T & _table_14_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_14_0_T_3 = _table_14_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_14_0 = _table_14_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_14_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_14_1_T_1 = input_ll_symbols_1 == 8'hE; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_14_1_T_2 = _table_14_1_T & _table_14_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_14_1_T_3 = _table_14_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_14_1 = _table_14_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_14_2_T_1 = input_ll_symbols_2 == 8'hE; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_14_2_T_2 = _table_14_2_T & _table_14_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_14_2_T_3 = _table_14_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_14_2 = _table_14_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_14_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_14_3_T_1 = input_ll_symbols_3 == 8'hE; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_14_3_T_2 = _table_14_3_T & _table_14_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_14_3_T_3 = _table_14_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_14_3 = _table_14_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_15_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_15_0_T_1 = input_ll_symbols_0 == 8'hF; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_15_0_T_2 = _table_15_0_T & _table_15_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_15_0_T_3 = _table_15_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_15_0 = _table_15_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_15_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_15_1_T_1 = input_ll_symbols_1 == 8'hF; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_15_1_T_2 = _table_15_1_T & _table_15_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_15_1_T_3 = _table_15_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_15_1 = _table_15_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_15_2_T_1 = input_ll_symbols_2 == 8'hF; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_15_2_T_2 = _table_15_2_T & _table_15_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_15_2_T_3 = _table_15_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_15_2 = _table_15_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_15_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_15_3_T_1 = input_ll_symbols_3 == 8'hF; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_15_3_T_2 = _table_15_3_T & _table_15_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_15_3_T_3 = _table_15_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_15_3 = _table_15_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_16_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_16_0_T_1 = input_ll_symbols_0 == 8'h10; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_16_0_T_2 = _table_16_0_T & _table_16_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_16_0_T_3 = _table_16_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_16_0 = _table_16_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_16_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_16_1_T_1 = input_ll_symbols_1 == 8'h10; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_16_1_T_2 = _table_16_1_T & _table_16_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_16_1_T_3 = _table_16_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_16_1 = _table_16_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_16_2_T_1 = input_ll_symbols_2 == 8'h10; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_16_2_T_2 = _table_16_2_T & _table_16_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_16_2_T_3 = _table_16_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_16_2 = _table_16_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_16_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_16_3_T_1 = input_ll_symbols_3 == 8'h10; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_16_3_T_2 = _table_16_3_T & _table_16_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_16_3_T_3 = _table_16_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_16_3 = _table_16_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_17_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_17_0_T_1 = input_ll_symbols_0 == 8'h11; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_17_0_T_2 = _table_17_0_T & _table_17_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_17_0_T_3 = _table_17_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_17_0 = _table_17_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_17_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_17_1_T_1 = input_ll_symbols_1 == 8'h11; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_17_1_T_2 = _table_17_1_T & _table_17_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_17_1_T_3 = _table_17_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_17_1 = _table_17_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_17_2_T_1 = input_ll_symbols_2 == 8'h11; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_17_2_T_2 = _table_17_2_T & _table_17_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_17_2_T_3 = _table_17_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_17_2 = _table_17_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_17_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_17_3_T_1 = input_ll_symbols_3 == 8'h11; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_17_3_T_2 = _table_17_3_T & _table_17_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_17_3_T_3 = _table_17_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_17_3 = _table_17_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_18_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_18_0_T_1 = input_ll_symbols_0 == 8'h12; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_18_0_T_2 = _table_18_0_T & _table_18_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_18_0_T_3 = _table_18_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_18_0 = _table_18_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_18_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_18_1_T_1 = input_ll_symbols_1 == 8'h12; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_18_1_T_2 = _table_18_1_T & _table_18_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_18_1_T_3 = _table_18_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_18_1 = _table_18_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_18_2_T_1 = input_ll_symbols_2 == 8'h12; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_18_2_T_2 = _table_18_2_T & _table_18_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_18_2_T_3 = _table_18_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_18_2 = _table_18_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_18_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_18_3_T_1 = input_ll_symbols_3 == 8'h12; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_18_3_T_2 = _table_18_3_T & _table_18_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_18_3_T_3 = _table_18_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_18_3 = _table_18_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_19_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_19_0_T_1 = input_ll_symbols_0 == 8'h13; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_19_0_T_2 = _table_19_0_T & _table_19_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_19_0_T_3 = _table_19_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_19_0 = _table_19_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_19_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_19_1_T_1 = input_ll_symbols_1 == 8'h13; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_19_1_T_2 = _table_19_1_T & _table_19_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_19_1_T_3 = _table_19_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_19_1 = _table_19_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_19_2_T_1 = input_ll_symbols_2 == 8'h13; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_19_2_T_2 = _table_19_2_T & _table_19_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_19_2_T_3 = _table_19_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_19_2 = _table_19_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_19_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_19_3_T_1 = input_ll_symbols_3 == 8'h13; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_19_3_T_2 = _table_19_3_T & _table_19_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_19_3_T_3 = _table_19_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_19_3 = _table_19_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_20_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_20_0_T_1 = input_ll_symbols_0 == 8'h14; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_20_0_T_2 = _table_20_0_T & _table_20_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_20_0_T_3 = _table_20_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_20_0 = _table_20_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_20_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_20_1_T_1 = input_ll_symbols_1 == 8'h14; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_20_1_T_2 = _table_20_1_T & _table_20_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_20_1_T_3 = _table_20_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_20_1 = _table_20_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_20_2_T_1 = input_ll_symbols_2 == 8'h14; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_20_2_T_2 = _table_20_2_T & _table_20_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_20_2_T_3 = _table_20_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_20_2 = _table_20_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_20_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_20_3_T_1 = input_ll_symbols_3 == 8'h14; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_20_3_T_2 = _table_20_3_T & _table_20_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_20_3_T_3 = _table_20_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_20_3 = _table_20_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_21_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_21_0_T_1 = input_ll_symbols_0 == 8'h15; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_21_0_T_2 = _table_21_0_T & _table_21_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_21_0_T_3 = _table_21_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_21_0 = _table_21_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_21_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_21_1_T_1 = input_ll_symbols_1 == 8'h15; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_21_1_T_2 = _table_21_1_T & _table_21_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_21_1_T_3 = _table_21_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_21_1 = _table_21_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_21_2_T_1 = input_ll_symbols_2 == 8'h15; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_21_2_T_2 = _table_21_2_T & _table_21_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_21_2_T_3 = _table_21_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_21_2 = _table_21_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_21_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_21_3_T_1 = input_ll_symbols_3 == 8'h15; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_21_3_T_2 = _table_21_3_T & _table_21_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_21_3_T_3 = _table_21_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_21_3 = _table_21_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_22_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_22_0_T_1 = input_ll_symbols_0 == 8'h16; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_22_0_T_2 = _table_22_0_T & _table_22_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_22_0_T_3 = _table_22_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_22_0 = _table_22_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_22_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_22_1_T_1 = input_ll_symbols_1 == 8'h16; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_22_1_T_2 = _table_22_1_T & _table_22_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_22_1_T_3 = _table_22_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_22_1 = _table_22_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_22_2_T_1 = input_ll_symbols_2 == 8'h16; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_22_2_T_2 = _table_22_2_T & _table_22_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_22_2_T_3 = _table_22_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_22_2 = _table_22_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_22_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_22_3_T_1 = input_ll_symbols_3 == 8'h16; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_22_3_T_2 = _table_22_3_T & _table_22_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_22_3_T_3 = _table_22_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_22_3 = _table_22_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_23_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_23_0_T_1 = input_ll_symbols_0 == 8'h17; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_23_0_T_2 = _table_23_0_T & _table_23_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_23_0_T_3 = _table_23_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_23_0 = _table_23_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_23_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_23_1_T_1 = input_ll_symbols_1 == 8'h17; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_23_1_T_2 = _table_23_1_T & _table_23_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_23_1_T_3 = _table_23_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_23_1 = _table_23_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_23_2_T_1 = input_ll_symbols_2 == 8'h17; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_23_2_T_2 = _table_23_2_T & _table_23_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_23_2_T_3 = _table_23_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_23_2 = _table_23_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_23_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_23_3_T_1 = input_ll_symbols_3 == 8'h17; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_23_3_T_2 = _table_23_3_T & _table_23_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_23_3_T_3 = _table_23_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_23_3 = _table_23_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_24_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_24_0_T_1 = input_ll_symbols_0 == 8'h18; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_24_0_T_2 = _table_24_0_T & _table_24_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_24_0_T_3 = _table_24_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_24_0 = _table_24_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_24_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_24_1_T_1 = input_ll_symbols_1 == 8'h18; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_24_1_T_2 = _table_24_1_T & _table_24_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_24_1_T_3 = _table_24_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_24_1 = _table_24_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_24_2_T_1 = input_ll_symbols_2 == 8'h18; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_24_2_T_2 = _table_24_2_T & _table_24_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_24_2_T_3 = _table_24_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_24_2 = _table_24_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_24_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_24_3_T_1 = input_ll_symbols_3 == 8'h18; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_24_3_T_2 = _table_24_3_T & _table_24_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_24_3_T_3 = _table_24_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_24_3 = _table_24_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_25_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_25_0_T_1 = input_ll_symbols_0 == 8'h19; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_25_0_T_2 = _table_25_0_T & _table_25_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_25_0_T_3 = _table_25_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_25_0 = _table_25_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_25_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_25_1_T_1 = input_ll_symbols_1 == 8'h19; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_25_1_T_2 = _table_25_1_T & _table_25_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_25_1_T_3 = _table_25_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_25_1 = _table_25_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_25_2_T_1 = input_ll_symbols_2 == 8'h19; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_25_2_T_2 = _table_25_2_T & _table_25_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_25_2_T_3 = _table_25_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_25_2 = _table_25_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_25_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_25_3_T_1 = input_ll_symbols_3 == 8'h19; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_25_3_T_2 = _table_25_3_T & _table_25_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_25_3_T_3 = _table_25_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_25_3 = _table_25_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_26_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_26_0_T_1 = input_ll_symbols_0 == 8'h1A; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_26_0_T_2 = _table_26_0_T & _table_26_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_26_0_T_3 = _table_26_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_26_0 = _table_26_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_26_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_26_1_T_1 = input_ll_symbols_1 == 8'h1A; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_26_1_T_2 = _table_26_1_T & _table_26_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_26_1_T_3 = _table_26_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_26_1 = _table_26_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_26_2_T_1 = input_ll_symbols_2 == 8'h1A; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_26_2_T_2 = _table_26_2_T & _table_26_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_26_2_T_3 = _table_26_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_26_2 = _table_26_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_26_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_26_3_T_1 = input_ll_symbols_3 == 8'h1A; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_26_3_T_2 = _table_26_3_T & _table_26_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_26_3_T_3 = _table_26_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_26_3 = _table_26_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_27_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_27_0_T_1 = input_ll_symbols_0 == 8'h1B; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_27_0_T_2 = _table_27_0_T & _table_27_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_27_0_T_3 = _table_27_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_27_0 = _table_27_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_27_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_27_1_T_1 = input_ll_symbols_1 == 8'h1B; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_27_1_T_2 = _table_27_1_T & _table_27_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_27_1_T_3 = _table_27_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_27_1 = _table_27_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_27_2_T_1 = input_ll_symbols_2 == 8'h1B; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_27_2_T_2 = _table_27_2_T & _table_27_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_27_2_T_3 = _table_27_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_27_2 = _table_27_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_27_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_27_3_T_1 = input_ll_symbols_3 == 8'h1B; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_27_3_T_2 = _table_27_3_T & _table_27_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_27_3_T_3 = _table_27_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_27_3 = _table_27_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_28_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_28_0_T_1 = input_ll_symbols_0 == 8'h1C; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_28_0_T_2 = _table_28_0_T & _table_28_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_28_0_T_3 = _table_28_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_28_0 = _table_28_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_28_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_28_1_T_1 = input_ll_symbols_1 == 8'h1C; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_28_1_T_2 = _table_28_1_T & _table_28_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_28_1_T_3 = _table_28_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_28_1 = _table_28_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_28_2_T_1 = input_ll_symbols_2 == 8'h1C; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_28_2_T_2 = _table_28_2_T & _table_28_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_28_2_T_3 = _table_28_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_28_2 = _table_28_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_28_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_28_3_T_1 = input_ll_symbols_3 == 8'h1C; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_28_3_T_2 = _table_28_3_T & _table_28_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_28_3_T_3 = _table_28_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_28_3 = _table_28_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_29_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_29_0_T_1 = input_ll_symbols_0 == 8'h1D; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_29_0_T_2 = _table_29_0_T & _table_29_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_29_0_T_3 = _table_29_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_29_0 = _table_29_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_29_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_29_1_T_1 = input_ll_symbols_1 == 8'h1D; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_29_1_T_2 = _table_29_1_T & _table_29_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_29_1_T_3 = _table_29_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_29_1 = _table_29_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_29_2_T_1 = input_ll_symbols_2 == 8'h1D; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_29_2_T_2 = _table_29_2_T & _table_29_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_29_2_T_3 = _table_29_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_29_2 = _table_29_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_29_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_29_3_T_1 = input_ll_symbols_3 == 8'h1D; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_29_3_T_2 = _table_29_3_T & _table_29_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_29_3_T_3 = _table_29_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_29_3 = _table_29_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_30_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_30_0_T_1 = input_ll_symbols_0 == 8'h1E; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_30_0_T_2 = _table_30_0_T & _table_30_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_30_0_T_3 = _table_30_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_30_0 = _table_30_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_30_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_30_1_T_1 = input_ll_symbols_1 == 8'h1E; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_30_1_T_2 = _table_30_1_T & _table_30_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_30_1_T_3 = _table_30_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_30_1 = _table_30_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_30_2_T_1 = input_ll_symbols_2 == 8'h1E; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_30_2_T_2 = _table_30_2_T & _table_30_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_30_2_T_3 = _table_30_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_30_2 = _table_30_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_30_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_30_3_T_1 = input_ll_symbols_3 == 8'h1E; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_30_3_T_2 = _table_30_3_T & _table_30_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_30_3_T_3 = _table_30_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_30_3 = _table_30_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_31_0_T = \|io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_31_0_T_1 = input_ll_symbols_0 == 8'h1F; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_31_0_T_2 = _table_31_0_T & _table_31_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_31_0_T_3 = _table_31_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_31_0 = _table_31_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_31_1_T = \|(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_31_1_T_1 = input_ll_symbols_1 == 8'h1F; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_31_1_T_2 = _table_31_1_T & _table_31_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_31_1_T_3 = _table_31_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_31_1 = _table_31_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_31_2_T_1 = input_ll_symbols_2 == 8'h1F; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_31_2_T_2 = _table_31_2_T & _table_31_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_31_2_T_3 = _table_31_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_31_2 = _table_31_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_31_3_T = \|(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_31_3_T_1 = input_ll_symbols_3 == 8'h1F; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_31_3_T_2 = _table_31_3_T & _table_31_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_31_3_T_3 = _table_31_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_31_3 = _table_31_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire [2:0] stat_sum_0; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_1; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_2; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_3; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_4; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_5; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_6; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_7; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_8; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_9; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_10; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_11; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_12; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_13; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_14; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_15; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_16; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_17; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_18; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_19; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_20; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_21; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_22; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_23; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_24; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_25; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_26; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_27; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_28; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_29; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_30; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_31; // @[FSECompressorDicBuilder.scala:186:26] wire [1:0] _stat_sum_0_T = {1'h0, table_0_0} + {1'h0, table_0_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_0_T_1 = {1'h0, _stat_sum_0_T} + {2'h0, table_0_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_0_T_2 = {1'h0, _stat_sum_0_T_1} + {3'h0, table_0_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_0 = _stat_sum_0_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_1_T = {1'h0, table_1_0} + {1'h0, table_1_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_1_T_1 = {1'h0, _stat_sum_1_T} + {2'h0, table_1_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_1_T_2 = {1'h0, _stat_sum_1_T_1} + {3'h0, table_1_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_1 = _stat_sum_1_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_2_T = {1'h0, table_2_0} + {1'h0, table_2_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_2_T_1 = {1'h0, _stat_sum_2_T} + {2'h0, table_2_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_2_T_2 = {1'h0, _stat_sum_2_T_1} + {3'h0, table_2_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_2 = _stat_sum_2_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_3_T = {1'h0, table_3_0} + {1'h0, table_3_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_3_T_1 = {1'h0, _stat_sum_3_T} + {2'h0, table_3_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_3_T_2 = {1'h0, _stat_sum_3_T_1} + {3'h0, table_3_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_3 = _stat_sum_3_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_4_T = {1'h0, table_4_0} + {1'h0, table_4_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_4_T_1 = {1'h0, _stat_sum_4_T} + {2'h0, table_4_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_4_T_2 = {1'h0, _stat_sum_4_T_1} + {3'h0, table_4_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_4 = _stat_sum_4_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_5_T = {1'h0, table_5_0} + {1'h0, table_5_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_5_T_1 = {1'h0, _stat_sum_5_T} + {2'h0, table_5_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_5_T_2 = {1'h0, _stat_sum_5_T_1} + {3'h0, table_5_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_5 = _stat_sum_5_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_6_T = {1'h0, table_6_0} + {1'h0, table_6_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_6_T_1 = {1'h0, _stat_sum_6_T} + {2'h0, table_6_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_6_T_2 = {1'h0, _stat_sum_6_T_1} + {3'h0, table_6_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_6 = _stat_sum_6_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_7_T = {1'h0, table_7_0} + {1'h0, table_7_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_7_T_1 = {1'h0, _stat_sum_7_T} + {2'h0, table_7_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_7_T_2 = {1'h0, _stat_sum_7_T_1} + {3'h0, table_7_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_7 = _stat_sum_7_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_8_T = {1'h0, table_8_0} + {1'h0, table_8_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_8_T_1 = {1'h0, _stat_sum_8_T} + {2'h0, table_8_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_8_T_2 = {1'h0, _stat_sum_8_T_1} + {3'h0, table_8_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_8 = _stat_sum_8_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_9_T = {1'h0, table_9_0} + {1'h0, table_9_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_9_T_1 = {1'h0, _stat_sum_9_T} + {2'h0, table_9_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_9_T_2 = {1'h0, _stat_sum_9_T_1} + {3'h0, table_9_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_9 = _stat_sum_9_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_10_T = {1'h0, table_10_0} + {1'h0, table_10_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_10_T_1 = {1'h0, _stat_sum_10_T} + {2'h0, table_10_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_10_T_2 = {1'h0, _stat_sum_10_T_1} + {3'h0, table_10_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_10 = _stat_sum_10_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_11_T = {1'h0, table_11_0} + {1'h0, table_11_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_11_T_1 = {1'h0, _stat_sum_11_T} + {2'h0, table_11_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_11_T_2 = {1'h0, _stat_sum_11_T_1} + {3'h0, table_11_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_11 = _stat_sum_11_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_12_T = {1'h0, table_12_0} + {1'h0, table_12_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_12_T_1 = {1'h0, _stat_sum_12_T} + {2'h0, table_12_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_12_T_2 = {1'h0, _stat_sum_12_T_1} + {3'h0, table_12_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_12 = _stat_sum_12_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_13_T = {1'h0, table_13_0} + {1'h0, table_13_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_13_T_1 = {1'h0, _stat_sum_13_T} + {2'h0, table_13_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_13_T_2 = {1'h0, _stat_sum_13_T_1} + {3'h0, table_13_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_13 = _stat_sum_13_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_14_T = {1'h0, table_14_0} + {1'h0, table_14_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_14_T_1 = {1'h0, _stat_sum_14_T} + {2'h0, table_14_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_14_T_2 = {1'h0, _stat_sum_14_T_1} + {3'h0, table_14_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_14 = _stat_sum_14_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_15_T = {1'h0, table_15_0} + {1'h0, table_15_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_15_T_1 = {1'h0, _stat_sum_15_T} + {2'h0, table_15_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_15_T_2 = {1'h0, _stat_sum_15_T_1} + {3'h0, table_15_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_15 = _stat_sum_15_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_16_T = {1'h0, table_16_0} + {1'h0, table_16_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_16_T_1 = {1'h0, _stat_sum_16_T} + {2'h0, table_16_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_16_T_2 = {1'h0, _stat_sum_16_T_1} + {3'h0, table_16_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_16 = _stat_sum_16_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_17_T = {1'h0, table_17_0} + {1'h0, table_17_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_17_T_1 = {1'h0, _stat_sum_17_T} + {2'h0, table_17_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_17_T_2 = {1'h0, _stat_sum_17_T_1} + {3'h0, table_17_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_17 = _stat_sum_17_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_18_T = {1'h0, table_18_0} + {1'h0, table_18_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_18_T_1 = {1'h0, _stat_sum_18_T} + {2'h0, table_18_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_18_T_2 = {1'h0, _stat_sum_18_T_1} + {3'h0, table_18_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_18 = _stat_sum_18_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_19_T = {1'h0, table_19_0} + {1'h0, table_19_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_19_T_1 = {1'h0, _stat_sum_19_T} + {2'h0, table_19_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_19_T_2 = {1'h0, _stat_sum_19_T_1} + {3'h0, table_19_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_19 = _stat_sum_19_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_20_T = {1'h0, table_20_0} + {1'h0, table_20_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_20_T_1 = {1'h0, _stat_sum_20_T} + {2'h0, table_20_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_20_T_2 = {1'h0, _stat_sum_20_T_1} + {3'h0, table_20_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_20 = _stat_sum_20_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_21_T = {1'h0, table_21_0} + {1'h0, table_21_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_21_T_1 = {1'h0, _stat_sum_21_T} + {2'h0, table_21_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_21_T_2 = {1'h0, _stat_sum_21_T_1} + {3'h0, table_21_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_21 = _stat_sum_21_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_22_T = {1'h0, table_22_0} + {1'h0, table_22_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_22_T_1 = {1'h0, _stat_sum_22_T} + {2'h0, table_22_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_22_T_2 = {1'h0, _stat_sum_22_T_1} + {3'h0, table_22_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_22 = _stat_sum_22_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_23_T = {1'h0, table_23_0} + {1'h0, table_23_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_23_T_1 = {1'h0, _stat_sum_23_T} + {2'h0, table_23_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_23_T_2 = {1'h0, _stat_sum_23_T_1} + {3'h0, table_23_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_23 = _stat_sum_23_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_24_T = {1'h0, table_24_0} + {1'h0, table_24_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_24_T_1 = {1'h0, _stat_sum_24_T} + {2'h0, table_24_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_24_T_2 = {1'h0, _stat_sum_24_T_1} + {3'h0, table_24_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_24 = _stat_sum_24_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_25_T = {1'h0, table_25_0} + {1'h0, table_25_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_25_T_1 = {1'h0, _stat_sum_25_T} + {2'h0, table_25_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_25_T_2 = {1'h0, _stat_sum_25_T_1} + {3'h0, table_25_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_25 = _stat_sum_25_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_26_T = {1'h0, table_26_0} + {1'h0, table_26_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_26_T_1 = {1'h0, _stat_sum_26_T} + {2'h0, table_26_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_26_T_2 = {1'h0, _stat_sum_26_T_1} + {3'h0, table_26_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_26 = _stat_sum_26_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_27_T = {1'h0, table_27_0} + {1'h0, table_27_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_27_T_1 = {1'h0, _stat_sum_27_T} + {2'h0, table_27_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_27_T_2 = {1'h0, _stat_sum_27_T_1} + {3'h0, table_27_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_27 = _stat_sum_27_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_28_T = {1'h0, table_28_0} + {1'h0, table_28_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_28_T_1 = {1'h0, _stat_sum_28_T} + {2'h0, table_28_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_28_T_2 = {1'h0, _stat_sum_28_T_1} + {3'h0, table_28_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_28 = _stat_sum_28_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_29_T = {1'h0, table_29_0} + {1'h0, table_29_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_29_T_1 = {1'h0, _stat_sum_29_T} + {2'h0, table_29_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_29_T_2 = {1'h0, _stat_sum_29_T_1} + {3'h0, table_29_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_29 = _stat_sum_29_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_30_T = {1'h0, table_30_0} + {1'h0, table_30_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_30_T_1 = {1'h0, _stat_sum_30_T} + {2'h0, table_30_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_30_T_2 = {1'h0, _stat_sum_30_T_1} + {3'h0, table_30_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_30 = _stat_sum_30_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_31_T = {1'h0, table_31_0} + {1'h0, table_31_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_31_T_1 = {1'h0, _stat_sum_31_T} + {2'h0, table_31_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_31_T_2 = {1'h0, _stat_sum_31_T_1} + {3'h0, table_31_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_31 = _stat_sum_31_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire _has_value_0_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_1_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_2_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_3_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_4_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_5_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_6_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_7_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_8_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_9_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_10_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_11_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_12_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_13_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_14_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_15_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_16_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_17_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_18_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_19_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_20_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_21_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_22_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_23_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_24_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_25_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_26_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_27_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_28_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_29_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_30_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_31_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire has_value_0; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_1; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_2; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_3; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_4; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_5; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_6; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_7; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_8; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_9; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_10; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_11; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_12; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_13; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_14; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_15; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_16; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_17; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_18; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_19; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_20; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_21; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_22; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_23; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_24; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_25; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_26; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_27; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_28; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_29; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_30; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_31; // @[FSECompressorDicBuilder.scala:191:27] wire _has_value_0_T = \|stat_sum_0; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_0_T_1 = _has_value_0_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_0 = _has_value_0_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_1_T = \|stat_sum_1; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_1_T_1 = _has_value_1_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_1 = _has_value_1_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_2_T = \|stat_sum_2; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_2_T_1 = _has_value_2_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_2 = _has_value_2_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_3_T = \|stat_sum_3; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_3_T_1 = _has_value_3_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_3 = _has_value_3_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_4_T = \|stat_sum_4; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_4_T_1 = _has_value_4_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_4 = _has_value_4_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_5_T = \|stat_sum_5; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_5_T_1 = _has_value_5_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_5 = _has_value_5_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_6_T = \|stat_sum_6; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_6_T_1 = _has_value_6_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_6 = _has_value_6_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_7_T = \|stat_sum_7; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_7_T_1 = _has_value_7_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_7 = _has_value_7_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_8_T = \|stat_sum_8; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_8_T_1 = _has_value_8_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_8 = _has_value_8_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_9_T = \|stat_sum_9; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_9_T_1 = _has_value_9_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_9 = _has_value_9_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_10_T = \|stat_sum_10; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_10_T_1 = _has_value_10_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_10 = _has_value_10_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_11_T = \|stat_sum_11; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_11_T_1 = _has_value_11_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_11 = _has_value_11_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_12_T = \|stat_sum_12; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_12_T_1 = _has_value_12_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_12 = _has_value_12_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_13_T = \|stat_sum_13; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_13_T_1 = _has_value_13_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_13 = _has_value_13_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_14_T = \|stat_sum_14; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_14_T_1 = _has_value_14_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_14 = _has_value_14_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_15_T = \|stat_sum_15; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_15_T_1 = _has_value_15_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_15 = _has_value_15_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_16_T = \|stat_sum_16; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_16_T_1 = _has_value_16_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_16 = _has_value_16_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_17_T = \|stat_sum_17; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_17_T_1 = _has_value_17_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_17 = _has_value_17_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_18_T = \|stat_sum_18; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_18_T_1 = _has_value_18_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_18 = _has_value_18_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_19_T = \|stat_sum_19; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_19_T_1 = _has_value_19_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_19 = _has_value_19_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_20_T = \|stat_sum_20; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_20_T_1 = _has_value_20_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_20 = _has_value_20_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_21_T = \|stat_sum_21; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_21_T_1 = _has_value_21_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_21 = _has_value_21_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_22_T = \|stat_sum_22; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_22_T_1 = _has_value_22_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_22 = _has_value_22_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_23_T = \|stat_sum_23; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_23_T_1 = _has_value_23_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_23 = _has_value_23_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_24_T = \|stat_sum_24; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_24_T_1 = _has_value_24_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_24 = _has_value_24_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_25_T = \|stat_sum_25; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_25_T_1 = _has_value_25_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_25 = _has_value_25_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_26_T = \|stat_sum_26; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_26_T_1 = _has_value_26_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_26 = _has_value_26_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_27_T = \|stat_sum_27; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_27_T_1 = _has_value_27_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_27 = _has_value_27_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_28_T = \|stat_sum_28; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_28_T_1 = _has_value_28_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_28 = _has_value_28_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_29_T = \|stat_sum_29; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_29_T_1 = _has_value_29_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_29 = _has_value_29_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_30_T = \|stat_sum_30; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_30_T_1 = _has_value_30_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_30 = _has_value_30_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_31_T = \|stat_sum_31; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_31_T_1 = _has_value_31_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_31 = _has_value_31_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire [1:0] has_value_cat_lo_lo_lo_lo = {has_value_30, has_value_31}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_lo_lo_lo_hi = {has_value_28, has_value_29}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_lo_lo_lo = {has_value_cat_lo_lo_lo_hi, has_value_cat_lo_lo_lo_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [1:0] has_value_cat_lo_lo_hi_lo = {has_value_26, has_value_27}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_lo_lo_hi_hi = {has_value_24, has_value_25}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_lo_lo_hi = {has_value_cat_lo_lo_hi_hi, has_value_cat_lo_lo_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [7:0] has_value_cat_lo_lo = {has_value_cat_lo_lo_hi, has_value_cat_lo_lo_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [1:0] has_value_cat_lo_hi_lo_lo = {has_value_22, has_value_23}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_lo_hi_lo_hi = {has_value_20, has_value_21}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_lo_hi_lo = {has_value_cat_lo_hi_lo_hi, has_value_cat_lo_hi_lo_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [1:0] has_value_cat_lo_hi_hi_lo = {has_value_18, has_value_19}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_lo_hi_hi_hi = {has_value_16, has_value_17}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_lo_hi_hi = {has_value_cat_lo_hi_hi_hi, has_value_cat_lo_hi_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [7:0] has_value_cat_lo_hi = {has_value_cat_lo_hi_hi, has_value_cat_lo_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [15:0] has_value_cat_lo = {has_value_cat_lo_hi, has_value_cat_lo_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [1:0] has_value_cat_hi_lo_lo_lo = {has_value_14, has_value_15}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_hi_lo_lo_hi = {has_value_12, has_value_13}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_hi_lo_lo = {has_value_cat_hi_lo_lo_hi, has_value_cat_hi_lo_lo_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [1:0] has_value_cat_hi_lo_hi_lo = {has_value_10, has_value_11}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_hi_lo_hi_hi = {has_value_8, has_value_9}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_hi_lo_hi = {has_value_cat_hi_lo_hi_hi, has_value_cat_hi_lo_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [7:0] has_value_cat_hi_lo = {has_value_cat_hi_lo_hi, has_value_cat_hi_lo_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [1:0] has_value_cat_hi_hi_lo_lo = {has_value_6, has_value_7}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_hi_hi_lo_hi = {has_value_4, has_value_5}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_hi_hi_lo = {has_value_cat_hi_hi_lo_hi, has_value_cat_hi_hi_lo_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [1:0] has_value_cat_hi_hi_hi_lo = {has_value_2, has_value_3}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_hi_hi_hi_hi = {has_value_0, has_value_1}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_hi_hi_hi = {has_value_cat_hi_hi_hi_hi, has_value_cat_hi_hi_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [7:0] has_value_cat_hi_hi = {has_value_cat_hi_hi_hi, has_value_cat_hi_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [15:0] has_value_cat_hi = {has_value_cat_hi_hi, has_value_cat_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [31:0] has_value_cat = {has_value_cat_hi, has_value_cat_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire _cur_max_value_T = has_value_cat[0]; // @[OneHot.scala:48:45] wire _cur_max_value_T_1 = has_value_cat[1]; // @[OneHot.scala:48:45] wire _cur_max_value_T_2 = has_value_cat[2]; // @[OneHot.scala:48:45] wire _cur_max_value_T_3 = has_value_cat[3]; // @[OneHot.scala:48:45] wire _cur_max_value_T_4 = has_value_cat[4]; // @[OneHot.scala:48:45] wire _cur_max_value_T_5 = has_value_cat[5]; // @[OneHot.scala:48:45] wire _cur_max_value_T_6 = has_value_cat[6]; // @[OneHot.scala:48:45] wire _cur_max_value_T_7 = has_value_cat[7]; // @[OneHot.scala:48:45] wire _cur_max_value_T_8 = has_value_cat[8]; // @[OneHot.scala:48:45] wire _cur_max_value_T_9 = has_value_cat[9]; // @[OneHot.scala:48:45] wire _cur_max_value_T_10 = has_value_cat[10]; // @[OneHot.scala:48:45] wire _cur_max_value_T_11 = has_value_cat[11]; // @[OneHot.scala:48:45] wire _cur_max_value_T_12 = has_value_cat[12]; // @[OneHot.scala:48:45] wire _cur_max_value_T_13 = has_value_cat[13]; // @[OneHot.scala:48:45] wire _cur_max_value_T_14 = has_value_cat[14]; // @[OneHot.scala:48:45] wire _cur_max_value_T_15 = has_value_cat[15]; // @[OneHot.scala:48:45] wire _cur_max_value_T_16 = has_value_cat[16]; // @[OneHot.scala:48:45] wire _cur_max_value_T_17 = has_value_cat[17]; // @[OneHot.scala:48:45] wire _cur_max_value_T_18 = has_value_cat[18]; // @[OneHot.scala:48:45] wire _cur_max_value_T_19 = has_value_cat[19]; // @[OneHot.scala:48:45] wire _cur_max_value_T_20 = has_value_cat[20]; // @[OneHot.scala:48:45] wire _cur_max_value_T_21 = has_value_cat[21]; // @[OneHot.scala:48:45] wire _cur_max_value_T_22 = has_value_cat[22]; // @[OneHot.scala:48:45] wire _cur_max_value_T_23 = has_value_cat[23]; // @[OneHot.scala:48:45] wire _cur_max_value_T_24 = has_value_cat[24]; // @[OneHot.scala:48:45] wire _cur_max_value_T_25 = has_value_cat[25]; // @[OneHot.scala:48:45] wire _cur_max_value_T_26 = has_value_cat[26]; // @[OneHot.scala:48:45] wire _cur_max_value_T_27 = has_value_cat[27]; // @[OneHot.scala:48:45] wire _cur_max_value_T_28 = has_value_cat[28]; // @[OneHot.scala:48:45] wire _cur_max_value_T_29 = has_value_cat[29]; // @[OneHot.scala:48:45] wire _cur_max_value_T_30 = has_value_cat[30]; // @[OneHot.scala:48:45] wire _cur_max_value_T_31 = has_value_cat[31]; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_32 = {4'hF, ~_cur_max_value_T_30}; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_33 = _cur_max_value_T_29 ? 5'h1D : _cur_max_value_T_32; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_34 = _cur_max_value_T_28 ? 5'h1C : _cur_max_value_T_33; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_35 = _cur_max_value_T_27 ? 5'h1B : _cur_max_value_T_34; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_36 = _cur_max_value_T_26 ? 5'h1A : _cur_max_value_T_35; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_37 = _cur_max_value_T_25 ? 5'h19 : _cur_max_value_T_36; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_38 = _cur_max_value_T_24 ? 5'h18 : _cur_max_value_T_37; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_39 = _cur_max_value_T_23 ? 5'h17 : _cur_max_value_T_38; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_40 = _cur_max_value_T_22 ? 5'h16 : _cur_max_value_T_39; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_41 = _cur_max_value_T_21 ? 5'h15 : _cur_max_value_T_40; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_42 = _cur_max_value_T_20 ? 5'h14 : _cur_max_value_T_41; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_43 = _cur_max_value_T_19 ? 5'h13 : _cur_max_value_T_42; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_44 = _cur_max_value_T_18 ? 5'h12 : _cur_max_value_T_43; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_45 = _cur_max_value_T_17 ? 5'h11 : _cur_max_value_T_44; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_46 = _cur_max_value_T_16 ? 5'h10 : _cur_max_value_T_45; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_47 = _cur_max_value_T_15 ? 5'hF : _cur_max_value_T_46; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_48 = _cur_max_value_T_14 ? 5'hE : _cur_max_value_T_47; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_49 = _cur_max_value_T_13 ? 5'hD : _cur_max_value_T_48; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_50 = _cur_max_value_T_12 ? 5'hC : _cur_max_value_T_49; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_51 = _cur_max_value_T_11 ? 5'hB : _cur_max_value_T_50; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_52 = _cur_max_value_T_10 ? 5'hA : _cur_max_value_T_51; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_53 = _cur_max_value_T_9 ? 5'h9 : _cur_max_value_T_52; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_54 = _cur_max_value_T_8 ? 5'h8 : _cur_max_value_T_53; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_55 = _cur_max_value_T_7 ? 5'h7 : _cur_max_value_T_54; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_56 = _cur_max_value_T_6 ? 5'h6 : _cur_max_value_T_55; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_57 = _cur_max_value_T_5 ? 5'h5 : _cur_max_value_T_56; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_58 = _cur_max_value_T_4 ? 5'h4 : _cur_max_value_T_57; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_59 = _cur_max_value_T_3 ? 5'h3 : _cur_max_value_T_58; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_60 = _cur_max_value_T_2 ? 5'h2 : _cur_max_value_T_59; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_61 = _cur_max_value_T_1 ? 5'h1 : _cur_max_value_T_60; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_62 = _cur_max_value_T ? 5'h0 : _cur_max_value_T_61; // @[OneHot.scala:48:45] wire [5:0] _cur_max_value_T_63 = 6'h1F - {1'h0, _cur_max_value_T_62}; // @[Mux.scala:50:70] wire [4:0] cur_max_value = _cur_max_value_T_63[4:0]; // @[FSECompressorDicBuilder.scala:196:48] wire _T_839 = dicBuilderState == 4'h1; // @[FSECompressorDicBuilder.scala:156:32, :198:25] wire [32:0] _GEN_0 = {1'h0, ll_count_0} + {30'h0, stat_sum_0}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_0_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_0_T = _GEN_0; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_0_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_0_T_2 = _GEN_0; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_0_T_1 = _ll_count_0_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_1 = {1'h0, ll_count_1} + {30'h0, stat_sum_1}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_1_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_1_T = _GEN_1; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_1_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_1_T_2 = _GEN_1; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_1_T_1 = _ll_count_1_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_2 = {1'h0, ll_count_2} + {30'h0, stat_sum_2}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_2_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_2_T = _GEN_2; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_2_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_2_T_2 = _GEN_2; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_2_T_1 = _ll_count_2_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_3 = {1'h0, ll_count_3} + {30'h0, stat_sum_3}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_3_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_3_T = _GEN_3; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_3_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_3_T_2 = _GEN_3; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_3_T_1 = _ll_count_3_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_4 = {1'h0, ll_count_4} + {30'h0, stat_sum_4}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_4_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_4_T = _GEN_4; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_4_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_4_T_2 = _GEN_4; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_4_T_1 = _ll_count_4_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_5 = {1'h0, ll_count_5} + {30'h0, stat_sum_5}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_5_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_5_T = _GEN_5; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_5_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_5_T_2 = _GEN_5; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_5_T_1 = _ll_count_5_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_6 = {1'h0, ll_count_6} + {30'h0, stat_sum_6}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_6_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_6_T = _GEN_6; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_6_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_6_T_2 = _GEN_6; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_6_T_1 = _ll_count_6_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_7 = {1'h0, ll_count_7} + {30'h0, stat_sum_7}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_7_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_7_T = _GEN_7; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_7_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_7_T_2 = _GEN_7; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_7_T_1 = _ll_count_7_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_8 = {1'h0, ll_count_8} + {30'h0, stat_sum_8}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_8_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_8_T = _GEN_8; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_8_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_8_T_2 = _GEN_8; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_8_T_1 = _ll_count_8_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_9 = {1'h0, ll_count_9} + {30'h0, stat_sum_9}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_9_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_9_T = _GEN_9; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_9_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_9_T_2 = _GEN_9; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_9_T_1 = _ll_count_9_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_10 = {1'h0, ll_count_10} + {30'h0, stat_sum_10}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_10_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_10_T = _GEN_10; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_10_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_10_T_2 = _GEN_10; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_10_T_1 = _ll_count_10_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_11 = {1'h0, ll_count_11} + {30'h0, stat_sum_11}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_11_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_11_T = _GEN_11; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_11_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_11_T_2 = _GEN_11; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_11_T_1 = _ll_count_11_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_12 = {1'h0, ll_count_12} + {30'h0, stat_sum_12}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_12_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_12_T = _GEN_12; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_12_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_12_T_2 = _GEN_12; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_12_T_1 = _ll_count_12_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_13 = {1'h0, ll_count_13} + {30'h0, stat_sum_13}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_13_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_13_T = _GEN_13; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_13_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_13_T_2 = _GEN_13; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_13_T_1 = _ll_count_13_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_14 = {1'h0, ll_count_14} + {30'h0, stat_sum_14}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_14_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_14_T = _GEN_14; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_14_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_14_T_2 = _GEN_14; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_14_T_1 = _ll_count_14_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_15 = {1'h0, ll_count_15} + {30'h0, stat_sum_15}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_15_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_15_T = _GEN_15; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_15_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_15_T_2 = _GEN_15; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_15_T_1 = _ll_count_15_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_16 = {1'h0, ll_count_16} + {30'h0, stat_sum_16}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_16_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_16_T = _GEN_16; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_16_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_16_T_2 = _GEN_16; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_16_T_1 = _ll_count_16_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_17 = {1'h0, ll_count_17} + {30'h0, stat_sum_17}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_17_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_17_T = _GEN_17; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_17_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_17_T_2 = _GEN_17; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_17_T_1 = _ll_count_17_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_18 = {1'h0, ll_count_18} + {30'h0, stat_sum_18}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_18_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_18_T = _GEN_18; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_18_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_18_T_2 = _GEN_18; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_18_T_1 = _ll_count_18_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_19 = {1'h0, ll_count_19} + {30'h0, stat_sum_19}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_19_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_19_T = _GEN_19; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_19_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_19_T_2 = _GEN_19; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_19_T_1 = _ll_count_19_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_20 = {1'h0, ll_count_20} + {30'h0, stat_sum_20}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_20_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_20_T = _GEN_20; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_20_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_20_T_2 = _GEN_20; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_20_T_1 = _ll_count_20_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_21 = {1'h0, ll_count_21} + {30'h0, stat_sum_21}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_21_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_21_T = _GEN_21; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_21_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_21_T_2 = _GEN_21; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_21_T_1 = _ll_count_21_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_22 = {1'h0, ll_count_22} + {30'h0, stat_sum_22}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_22_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_22_T = _GEN_22; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_22_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_22_T_2 = _GEN_22; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_22_T_1 = _ll_count_22_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_23 = {1'h0, ll_count_23} + {30'h0, stat_sum_23}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_23_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_23_T = _GEN_23; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_23_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_23_T_2 = _GEN_23; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_23_T_1 = _ll_count_23_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_24 = {1'h0, ll_count_24} + {30'h0, stat_sum_24}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_24_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_24_T = _GEN_24; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_24_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_24_T_2 = _GEN_24; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_24_T_1 = _ll_count_24_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_25 = {1'h0, ll_count_25} + {30'h0, stat_sum_25}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_25_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_25_T = _GEN_25; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_25_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_25_T_2 = _GEN_25; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_25_T_1 = _ll_count_25_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_26 = {1'h0, ll_count_26} + {30'h0, stat_sum_26}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_26_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_26_T = _GEN_26; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_26_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_26_T_2 = _GEN_26; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_26_T_1 = _ll_count_26_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_27 = {1'h0, ll_count_27} + {30'h0, stat_sum_27}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_27_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_27_T = _GEN_27; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_27_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_27_T_2 = _GEN_27; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_27_T_1 = _ll_count_27_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_28 = {1'h0, ll_count_28} + {30'h0, stat_sum_28}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_28_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_28_T = _GEN_28; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_28_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_28_T_2 = _GEN_28; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_28_T_1 = _ll_count_28_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_29 = {1'h0, ll_count_29} + {30'h0, stat_sum_29}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_29_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_29_T = _GEN_29; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_29_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_29_T_2 = _GEN_29; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_29_T_1 = _ll_count_29_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_30 = {1'h0, ll_count_30} + {30'h0, stat_sum_30}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_30_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_30_T = _GEN_30; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_30_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_30_T_2 = _GEN_30; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_30_T_1 = _ll_count_30_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_31 = {1'h0, ll_count_31} + {30'h0, stat_sum_31}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_31_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_31_T = _GEN_31; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_31_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_31_T_2 = _GEN_31; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_31_T_1 = _ll_count_31_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [31:0] _GEN_32 = {27'h0, cur_max_value}; // @[FSECompressorDicBuilder.scala:196:48, :204:54] wire _GEN_33 = ll_max_symbol_value > _GEN_32; // @[FSECompressorDicBuilder.scala:170:36, :204:54] wire _ll_max_symbol_value_T; // @[FSECompressorDicBuilder.scala:204:54] assign _ll_max_symbol_value_T = _GEN_33; // @[FSECompressorDicBuilder.scala:204:54] wire _ll_max_symbol_value_T_2; // @[FSECompressorDicBuilder.scala:569:56] assign _ll_max_symbol_value_T_2 = _GEN_33; // @[FSECompressorDicBuilder.scala:204:54, :569:56] wire [31:0] _ll_max_symbol_value_T_1 = _ll_max_symbol_value_T ? ll_max_symbol_value : _GEN_32; // @[FSECompressorDicBuilder.scala:170:36, :204:{33,54}] wire ll_useLowProbCount = ll_nbseq_1 > 64'hFFFFFFFE; // @[FSECompressorDicBuilder.scala:171:27, :248:39] wire [15:0] _ll_lowProbCount_T; // @[FSECompressorDicBuilder.scala:250:25] wire [15:0] ll_lowProbCount; // @[FSECompressorDicBuilder.scala:249:29] assign _ll_lowProbCount_T = ll_useLowProbCount ? 16'hFFFF : 16'h1; // @[FSECompressorDicBuilder.scala:248:39, :250:25] assign ll_lowProbCount = _ll_lowProbCount_T; // @[FSECompressorDicBuilder.scala:249:29, :250:25] wire [63:0] ll_step; // @[FSECompressorDicBuilder.scala:253:21] wire [63:0] _GEN_34 = 64'h4000000000000000 / ll_nbseq_1; // @[FSECompressorDicBuilder.scala:171:27, :254:47] wire [62:0] _ll_step_T = _GEN_34[62:0]; // @[FSECompressorDicBuilder.scala:254:47] assign ll_step = {1'h0, _ll_step_T}; // @[FSECompressorDicBuilder.scala:253:21, :254:{11,47}] wire [31:0] ll_lowThreshold; // @[FSECompressorDicBuilder.scala:260:29] wire [63:0] _ll_lowThreshold_T = {6'h0, ll_nbseq_1[63:6]}; // @[FSECompressorDicBuilder.scala:171:27, :261:33] assign ll_lowThreshold = _ll_lowThreshold_T[31:0]; // @[FSECompressorDicBuilder.scala:260:29, :261:{19,33}] wire [15:0] ll_proba_base_0; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_1; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_2; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_3; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_4; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_5; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_6; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_7; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_8; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_9; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_10; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_11; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_12; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_13; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_14; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_15; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_16; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_17; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_18; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_19; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_20; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_21; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_22; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_23; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_24; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_25; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_26; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_27; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_28; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_29; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_30; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_31; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] _ll_proba_0_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_1_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_2_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_3_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_4_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_5_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_6_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_7_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_8_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_9_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_10_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_11_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_12_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_13_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_14_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_15_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_16_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_17_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_18_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_19_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_20_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_21_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_22_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_23_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_24_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_25_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_26_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_27_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_28_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_29_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_30_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_31_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] ll_proba_0; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_1; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_2; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_3; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_4; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_5; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_6; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_7; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_8; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_9; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_10; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_11; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_12; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_13; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_14; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_15; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_16; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_17; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_18; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_19; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_20; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_21; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_22; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_23; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_24; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_25; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_26; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_27; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_28; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_29; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_30; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_31; // @[FSECompressorDicBuilder.scala:265:26] wire [63:0] ll_count_times_step_0; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_1; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_2; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_3; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_4; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_5; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_6; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_7; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_8; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_9; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_10; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_11; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_12; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_13; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_14; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_15; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_16; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_17; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_18; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_19; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_20; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_21; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_22; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_23; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_24; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_25; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_26; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_27; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_28; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_29; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_30; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_31; // @[FSECompressorDicBuilder.scala:266:37] wire [95:0] _GEN_35 = {32'h0, ll_step}; // @[FSECompressorDicBuilder.scala:253:21, :268:43] wire [95:0] _GEN_36 = {64'h0, ll_count_0} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_0_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_0_T = _GEN_36; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T = _GEN_36; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_0 = _ll_count_times_step_0_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_0_T = {56'h0, ll_count_times_step_0[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_0 = _ll_proba_base_0_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T = ll_proba_base_0[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [7:0][31:0] _GEN_37 = {{rtbTable_7}, {rtbTable_6}, {rtbTable_5}, {rtbTable_4}, {rtbTable_3}, {rtbTable_2}, {rtbTable_1}, {32'h0}}; // @[FSECompressorDicBuilder.scala:57:25, :271:31] wire [95:0] restToBeat = {28'h0, _GEN_37[_restToBeat_T], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_1 = {71'h0, ll_proba_base_0, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_2 = {48'h0, _ll_add_to_proba_base_T} - {1'h0, _ll_add_to_proba_base_T_1}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_3 = _ll_add_to_proba_base_T_2[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_4 = _ll_add_to_proba_base_T_3 > {47'h0, restToBeat}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base = _ll_add_to_proba_base_T_4; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_0_T = ll_proba_base_0 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_0_T_1 = {1'h0, ll_proba_base_0} + {16'h0, ll_add_to_proba_base}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_0_T_2 = _ll_proba_0_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_0_T_3 = _ll_proba_0_T ? _ll_proba_0_T_2 : ll_proba_base_0; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_0 = _ll_proba_0_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_38 = {64'h0, ll_count_1} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_1_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_1_T = _GEN_38; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_5; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_5 = _GEN_38; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_1 = _ll_count_times_step_1_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_1_T = {56'h0, ll_count_times_step_1[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_1 = _ll_proba_base_1_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_1 = ll_proba_base_1[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_1 = {28'h0, _GEN_37[_restToBeat_T_1], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_6 = {71'h0, ll_proba_base_1, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_7 = {48'h0, _ll_add_to_proba_base_T_5} - {1'h0, _ll_add_to_proba_base_T_6}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_8 = _ll_add_to_proba_base_T_7[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_9 = _ll_add_to_proba_base_T_8 > {47'h0, restToBeat_1}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_1 = _ll_add_to_proba_base_T_9; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_1_T = ll_proba_base_1 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_1_T_1 = {1'h0, ll_proba_base_1} + {16'h0, ll_add_to_proba_base_1}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_1_T_2 = _ll_proba_1_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_1_T_3 = _ll_proba_1_T ? _ll_proba_1_T_2 : ll_proba_base_1; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_1 = _ll_proba_1_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_39 = {64'h0, ll_count_2} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_2_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_2_T = _GEN_39; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_10; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_10 = _GEN_39; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_2 = _ll_count_times_step_2_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_2_T = {56'h0, ll_count_times_step_2[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_2 = _ll_proba_base_2_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_2 = ll_proba_base_2[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_2 = {28'h0, _GEN_37[_restToBeat_T_2], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_11 = {71'h0, ll_proba_base_2, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_12 = {48'h0, _ll_add_to_proba_base_T_10} - {1'h0, _ll_add_to_proba_base_T_11}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_13 = _ll_add_to_proba_base_T_12[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_14 = _ll_add_to_proba_base_T_13 > {47'h0, restToBeat_2}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_2 = _ll_add_to_proba_base_T_14; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_2_T = ll_proba_base_2 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_2_T_1 = {1'h0, ll_proba_base_2} + {16'h0, ll_add_to_proba_base_2}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_2_T_2 = _ll_proba_2_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_2_T_3 = _ll_proba_2_T ? _ll_proba_2_T_2 : ll_proba_base_2; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_2 = _ll_proba_2_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_40 = {64'h0, ll_count_3} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_3_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_3_T = _GEN_40; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_15; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_15 = _GEN_40; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_3 = _ll_count_times_step_3_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_3_T = {56'h0, ll_count_times_step_3[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_3 = _ll_proba_base_3_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_3 = ll_proba_base_3[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_3 = {28'h0, _GEN_37[_restToBeat_T_3], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_16 = {71'h0, ll_proba_base_3, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_17 = {48'h0, _ll_add_to_proba_base_T_15} - {1'h0, _ll_add_to_proba_base_T_16}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_18 = _ll_add_to_proba_base_T_17[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_19 = _ll_add_to_proba_base_T_18 > {47'h0, restToBeat_3}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_3 = _ll_add_to_proba_base_T_19; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_3_T = ll_proba_base_3 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_3_T_1 = {1'h0, ll_proba_base_3} + {16'h0, ll_add_to_proba_base_3}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_3_T_2 = _ll_proba_3_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_3_T_3 = _ll_proba_3_T ? _ll_proba_3_T_2 : ll_proba_base_3; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_3 = _ll_proba_3_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_41 = {64'h0, ll_count_4} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_4_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_4_T = _GEN_41; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_20; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_20 = _GEN_41; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_4 = _ll_count_times_step_4_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_4_T = {56'h0, ll_count_times_step_4[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_4 = _ll_proba_base_4_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_4 = ll_proba_base_4[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_4 = {28'h0, _GEN_37[_restToBeat_T_4], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_21 = {71'h0, ll_proba_base_4, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_22 = {48'h0, _ll_add_to_proba_base_T_20} - {1'h0, _ll_add_to_proba_base_T_21}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_23 = _ll_add_to_proba_base_T_22[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_24 = _ll_add_to_proba_base_T_23 > {47'h0, restToBeat_4}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_4 = _ll_add_to_proba_base_T_24; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_4_T = ll_proba_base_4 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_4_T_1 = {1'h0, ll_proba_base_4} + {16'h0, ll_add_to_proba_base_4}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_4_T_2 = _ll_proba_4_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_4_T_3 = _ll_proba_4_T ? _ll_proba_4_T_2 : ll_proba_base_4; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_4 = _ll_proba_4_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_42 = {64'h0, ll_count_5} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_5_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_5_T = _GEN_42; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_25; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_25 = _GEN_42; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_5 = _ll_count_times_step_5_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_5_T = {56'h0, ll_count_times_step_5[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_5 = _ll_proba_base_5_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_5 = ll_proba_base_5[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_5 = {28'h0, _GEN_37[_restToBeat_T_5], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_26 = {71'h0, ll_proba_base_5, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_27 = {48'h0, _ll_add_to_proba_base_T_25} - {1'h0, _ll_add_to_proba_base_T_26}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_28 = _ll_add_to_proba_base_T_27[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_29 = _ll_add_to_proba_base_T_28 > {47'h0, restToBeat_5}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_5 = _ll_add_to_proba_base_T_29; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_5_T = ll_proba_base_5 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_5_T_1 = {1'h0, ll_proba_base_5} + {16'h0, ll_add_to_proba_base_5}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_5_T_2 = _ll_proba_5_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_5_T_3 = _ll_proba_5_T ? _ll_proba_5_T_2 : ll_proba_base_5; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_5 = _ll_proba_5_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_43 = {64'h0, ll_count_6} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_6_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_6_T = _GEN_43; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_30; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_30 = _GEN_43; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_6 = _ll_count_times_step_6_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_6_T = {56'h0, ll_count_times_step_6[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_6 = _ll_proba_base_6_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_6 = ll_proba_base_6[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_6 = {28'h0, _GEN_37[_restToBeat_T_6], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_31 = {71'h0, ll_proba_base_6, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_32 = {48'h0, _ll_add_to_proba_base_T_30} - {1'h0, _ll_add_to_proba_base_T_31}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_33 = _ll_add_to_proba_base_T_32[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_34 = _ll_add_to_proba_base_T_33 > {47'h0, restToBeat_6}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_6 = _ll_add_to_proba_base_T_34; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_6_T = ll_proba_base_6 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_6_T_1 = {1'h0, ll_proba_base_6} + {16'h0, ll_add_to_proba_base_6}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_6_T_2 = _ll_proba_6_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_6_T_3 = _ll_proba_6_T ? _ll_proba_6_T_2 : ll_proba_base_6; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_6 = _ll_proba_6_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_44 = {64'h0, ll_count_7} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_7_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_7_T = _GEN_44; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_35; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_35 = _GEN_44; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_7 = _ll_count_times_step_7_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_7_T = {56'h0, ll_count_times_step_7[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_7 = _ll_proba_base_7_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_7 = ll_proba_base_7[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_7 = {28'h0, _GEN_37[_restToBeat_T_7], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_36 = {71'h0, ll_proba_base_7, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_37 = {48'h0, _ll_add_to_proba_base_T_35} - {1'h0, _ll_add_to_proba_base_T_36}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_38 = _ll_add_to_proba_base_T_37[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_39 = _ll_add_to_proba_base_T_38 > {47'h0, restToBeat_7}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_7 = _ll_add_to_proba_base_T_39; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_7_T = ll_proba_base_7 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_7_T_1 = {1'h0, ll_proba_base_7} + {16'h0, ll_add_to_proba_base_7}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_7_T_2 = _ll_proba_7_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_7_T_3 = _ll_proba_7_T ? _ll_proba_7_T_2 : ll_proba_base_7; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_7 = _ll_proba_7_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_45 = {64'h0, ll_count_8} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_8_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_8_T = _GEN_45; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_40; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_40 = _GEN_45; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_8 = _ll_count_times_step_8_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_8_T = {56'h0, ll_count_times_step_8[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_8 = _ll_proba_base_8_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_8 = ll_proba_base_8[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_8 = {28'h0, _GEN_37[_restToBeat_T_8], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_41 = {71'h0, ll_proba_base_8, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_42 = {48'h0, _ll_add_to_proba_base_T_40} - {1'h0, _ll_add_to_proba_base_T_41}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_43 = _ll_add_to_proba_base_T_42[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_44 = _ll_add_to_proba_base_T_43 > {47'h0, restToBeat_8}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_8 = _ll_add_to_proba_base_T_44; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_8_T = ll_proba_base_8 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_8_T_1 = {1'h0, ll_proba_base_8} + {16'h0, ll_add_to_proba_base_8}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_8_T_2 = _ll_proba_8_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_8_T_3 = _ll_proba_8_T ? _ll_proba_8_T_2 : ll_proba_base_8; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_8 = _ll_proba_8_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_46 = {64'h0, ll_count_9} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_9_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_9_T = _GEN_46; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_45; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_45 = _GEN_46; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_9 = _ll_count_times_step_9_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_9_T = {56'h0, ll_count_times_step_9[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_9 = _ll_proba_base_9_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_9 = ll_proba_base_9[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_9 = {28'h0, _GEN_37[_restToBeat_T_9], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_46 = {71'h0, ll_proba_base_9, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_47 = {48'h0, _ll_add_to_proba_base_T_45} - {1'h0, _ll_add_to_proba_base_T_46}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_48 = _ll_add_to_proba_base_T_47[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_49 = _ll_add_to_proba_base_T_48 > {47'h0, restToBeat_9}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_9 = _ll_add_to_proba_base_T_49; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_9_T = ll_proba_base_9 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_9_T_1 = {1'h0, ll_proba_base_9} + {16'h0, ll_add_to_proba_base_9}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_9_T_2 = _ll_proba_9_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_9_T_3 = _ll_proba_9_T ? _ll_proba_9_T_2 : ll_proba_base_9; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_9 = _ll_proba_9_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_47 = {64'h0, ll_count_10} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_10_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_10_T = _GEN_47; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_50; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_50 = _GEN_47; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_10 = _ll_count_times_step_10_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_10_T = {56'h0, ll_count_times_step_10[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_10 = _ll_proba_base_10_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_10 = ll_proba_base_10[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_10 = {28'h0, _GEN_37[_restToBeat_T_10], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_51 = {71'h0, ll_proba_base_10, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_52 = {48'h0, _ll_add_to_proba_base_T_50} - {1'h0, _ll_add_to_proba_base_T_51}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_53 = _ll_add_to_proba_base_T_52[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_54 = _ll_add_to_proba_base_T_53 > {47'h0, restToBeat_10}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_10 = _ll_add_to_proba_base_T_54; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_10_T = ll_proba_base_10 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_10_T_1 = {1'h0, ll_proba_base_10} + {16'h0, ll_add_to_proba_base_10}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_10_T_2 = _ll_proba_10_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_10_T_3 = _ll_proba_10_T ? _ll_proba_10_T_2 : ll_proba_base_10; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_10 = _ll_proba_10_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_48 = {64'h0, ll_count_11} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_11_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_11_T = _GEN_48; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_55; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_55 = _GEN_48; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_11 = _ll_count_times_step_11_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_11_T = {56'h0, ll_count_times_step_11[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_11 = _ll_proba_base_11_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_11 = ll_proba_base_11[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_11 = {28'h0, _GEN_37[_restToBeat_T_11], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_56 = {71'h0, ll_proba_base_11, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_57 = {48'h0, _ll_add_to_proba_base_T_55} - {1'h0, _ll_add_to_proba_base_T_56}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_58 = _ll_add_to_proba_base_T_57[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_59 = _ll_add_to_proba_base_T_58 > {47'h0, restToBeat_11}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_11 = _ll_add_to_proba_base_T_59; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_11_T = ll_proba_base_11 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_11_T_1 = {1'h0, ll_proba_base_11} + {16'h0, ll_add_to_proba_base_11}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_11_T_2 = _ll_proba_11_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_11_T_3 = _ll_proba_11_T ? _ll_proba_11_T_2 : ll_proba_base_11; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_11 = _ll_proba_11_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_49 = {64'h0, ll_count_12} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_12_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_12_T = _GEN_49; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_60; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_60 = _GEN_49; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_12 = _ll_count_times_step_12_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_12_T = {56'h0, ll_count_times_step_12[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_12 = _ll_proba_base_12_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_12 = ll_proba_base_12[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_12 = {28'h0, _GEN_37[_restToBeat_T_12], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_61 = {71'h0, ll_proba_base_12, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_62 = {48'h0, _ll_add_to_proba_base_T_60} - {1'h0, _ll_add_to_proba_base_T_61}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_63 = _ll_add_to_proba_base_T_62[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_64 = _ll_add_to_proba_base_T_63 > {47'h0, restToBeat_12}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_12 = _ll_add_to_proba_base_T_64; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_12_T = ll_proba_base_12 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_12_T_1 = {1'h0, ll_proba_base_12} + {16'h0, ll_add_to_proba_base_12}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_12_T_2 = _ll_proba_12_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_12_T_3 = _ll_proba_12_T ? _ll_proba_12_T_2 : ll_proba_base_12; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_12 = _ll_proba_12_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_50 = {64'h0, ll_count_13} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_13_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_13_T = _GEN_50; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_65; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_65 = _GEN_50; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_13 = _ll_count_times_step_13_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_13_T = {56'h0, ll_count_times_step_13[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_13 = _ll_proba_base_13_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_13 = ll_proba_base_13[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_13 = {28'h0, _GEN_37[_restToBeat_T_13], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_66 = {71'h0, ll_proba_base_13, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_67 = {48'h0, _ll_add_to_proba_base_T_65} - {1'h0, _ll_add_to_proba_base_T_66}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_68 = _ll_add_to_proba_base_T_67[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_69 = _ll_add_to_proba_base_T_68 > {47'h0, restToBeat_13}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_13 = _ll_add_to_proba_base_T_69; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_13_T = ll_proba_base_13 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_13_T_1 = {1'h0, ll_proba_base_13} + {16'h0, ll_add_to_proba_base_13}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_13_T_2 = _ll_proba_13_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_13_T_3 = _ll_proba_13_T ? _ll_proba_13_T_2 : ll_proba_base_13; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_13 = _ll_proba_13_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_51 = {64'h0, ll_count_14} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_14_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_14_T = _GEN_51; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_70; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_70 = _GEN_51; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_14 = _ll_count_times_step_14_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_14_T = {56'h0, ll_count_times_step_14[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_14 = _ll_proba_base_14_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_14 = ll_proba_base_14[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_14 = {28'h0, _GEN_37[_restToBeat_T_14], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_71 = {71'h0, ll_proba_base_14, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_72 = {48'h0, _ll_add_to_proba_base_T_70} - {1'h0, _ll_add_to_proba_base_T_71}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_73 = _ll_add_to_proba_base_T_72[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_74 = _ll_add_to_proba_base_T_73 > {47'h0, restToBeat_14}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_14 = _ll_add_to_proba_base_T_74; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_14_T = ll_proba_base_14 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_14_T_1 = {1'h0, ll_proba_base_14} + {16'h0, ll_add_to_proba_base_14}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_14_T_2 = _ll_proba_14_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_14_T_3 = _ll_proba_14_T ? _ll_proba_14_T_2 : ll_proba_base_14; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_14 = _ll_proba_14_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_52 = {64'h0, ll_count_15} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_15_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_15_T = _GEN_52; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_75; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_75 = _GEN_52; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_15 = _ll_count_times_step_15_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_15_T = {56'h0, ll_count_times_step_15[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_15 = _ll_proba_base_15_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_15 = ll_proba_base_15[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_15 = {28'h0, _GEN_37[_restToBeat_T_15], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_76 = {71'h0, ll_proba_base_15, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_77 = {48'h0, _ll_add_to_proba_base_T_75} - {1'h0, _ll_add_to_proba_base_T_76}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_78 = _ll_add_to_proba_base_T_77[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_79 = _ll_add_to_proba_base_T_78 > {47'h0, restToBeat_15}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_15 = _ll_add_to_proba_base_T_79; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_15_T = ll_proba_base_15 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_15_T_1 = {1'h0, ll_proba_base_15} + {16'h0, ll_add_to_proba_base_15}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_15_T_2 = _ll_proba_15_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_15_T_3 = _ll_proba_15_T ? _ll_proba_15_T_2 : ll_proba_base_15; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_15 = _ll_proba_15_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_53 = {64'h0, ll_count_16} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_16_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_16_T = _GEN_53; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_80; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_80 = _GEN_53; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_16 = _ll_count_times_step_16_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_16_T = {56'h0, ll_count_times_step_16[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_16 = _ll_proba_base_16_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_16 = ll_proba_base_16[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_16 = {28'h0, _GEN_37[_restToBeat_T_16], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_81 = {71'h0, ll_proba_base_16, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_82 = {48'h0, _ll_add_to_proba_base_T_80} - {1'h0, _ll_add_to_proba_base_T_81}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_83 = _ll_add_to_proba_base_T_82[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_84 = _ll_add_to_proba_base_T_83 > {47'h0, restToBeat_16}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_16 = _ll_add_to_proba_base_T_84; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_16_T = ll_proba_base_16 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_16_T_1 = {1'h0, ll_proba_base_16} + {16'h0, ll_add_to_proba_base_16}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_16_T_2 = _ll_proba_16_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_16_T_3 = _ll_proba_16_T ? _ll_proba_16_T_2 : ll_proba_base_16; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_16 = _ll_proba_16_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_54 = {64'h0, ll_count_17} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_17_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_17_T = _GEN_54; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_85; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_85 = _GEN_54; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_17 = _ll_count_times_step_17_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_17_T = {56'h0, ll_count_times_step_17[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_17 = _ll_proba_base_17_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_17 = ll_proba_base_17[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_17 = {28'h0, _GEN_37[_restToBeat_T_17], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_86 = {71'h0, ll_proba_base_17, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_87 = {48'h0, _ll_add_to_proba_base_T_85} - {1'h0, _ll_add_to_proba_base_T_86}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_88 = _ll_add_to_proba_base_T_87[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_89 = _ll_add_to_proba_base_T_88 > {47'h0, restToBeat_17}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_17 = _ll_add_to_proba_base_T_89; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_17_T = ll_proba_base_17 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_17_T_1 = {1'h0, ll_proba_base_17} + {16'h0, ll_add_to_proba_base_17}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_17_T_2 = _ll_proba_17_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_17_T_3 = _ll_proba_17_T ? _ll_proba_17_T_2 : ll_proba_base_17; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_17 = _ll_proba_17_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_55 = {64'h0, ll_count_18} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_18_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_18_T = _GEN_55; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_90; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_90 = _GEN_55; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_18 = _ll_count_times_step_18_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_18_T = {56'h0, ll_count_times_step_18[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_18 = _ll_proba_base_18_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_18 = ll_proba_base_18[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_18 = {28'h0, _GEN_37[_restToBeat_T_18], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_91 = {71'h0, ll_proba_base_18, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_92 = {48'h0, _ll_add_to_proba_base_T_90} - {1'h0, _ll_add_to_proba_base_T_91}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_93 = _ll_add_to_proba_base_T_92[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_94 = _ll_add_to_proba_base_T_93 > {47'h0, restToBeat_18}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_18 = _ll_add_to_proba_base_T_94; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_18_T = ll_proba_base_18 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_18_T_1 = {1'h0, ll_proba_base_18} + {16'h0, ll_add_to_proba_base_18}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_18_T_2 = _ll_proba_18_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_18_T_3 = _ll_proba_18_T ? _ll_proba_18_T_2 : ll_proba_base_18; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_18 = _ll_proba_18_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_56 = {64'h0, ll_count_19} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_19_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_19_T = _GEN_56; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_95; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_95 = _GEN_56; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_19 = _ll_count_times_step_19_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_19_T = {56'h0, ll_count_times_step_19[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_19 = _ll_proba_base_19_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_19 = ll_proba_base_19[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_19 = {28'h0, _GEN_37[_restToBeat_T_19], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_96 = {71'h0, ll_proba_base_19, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_97 = {48'h0, _ll_add_to_proba_base_T_95} - {1'h0, _ll_add_to_proba_base_T_96}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_98 = _ll_add_to_proba_base_T_97[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_99 = _ll_add_to_proba_base_T_98 > {47'h0, restToBeat_19}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_19 = _ll_add_to_proba_base_T_99; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_19_T = ll_proba_base_19 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_19_T_1 = {1'h0, ll_proba_base_19} + {16'h0, ll_add_to_proba_base_19}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_19_T_2 = _ll_proba_19_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_19_T_3 = _ll_proba_19_T ? _ll_proba_19_T_2 : ll_proba_base_19; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_19 = _ll_proba_19_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_57 = {64'h0, ll_count_20} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_20_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_20_T = _GEN_57; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_100; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_100 = _GEN_57; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_20 = _ll_count_times_step_20_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_20_T = {56'h0, ll_count_times_step_20[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_20 = _ll_proba_base_20_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_20 = ll_proba_base_20[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_20 = {28'h0, _GEN_37[_restToBeat_T_20], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_101 = {71'h0, ll_proba_base_20, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_102 = {48'h0, _ll_add_to_proba_base_T_100} - {1'h0, _ll_add_to_proba_base_T_101}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_103 = _ll_add_to_proba_base_T_102[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_104 = _ll_add_to_proba_base_T_103 > {47'h0, restToBeat_20}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_20 = _ll_add_to_proba_base_T_104; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_20_T = ll_proba_base_20 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_20_T_1 = {1'h0, ll_proba_base_20} + {16'h0, ll_add_to_proba_base_20}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_20_T_2 = _ll_proba_20_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_20_T_3 = _ll_proba_20_T ? _ll_proba_20_T_2 : ll_proba_base_20; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_20 = _ll_proba_20_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_58 = {64'h0, ll_count_21} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_21_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_21_T = _GEN_58; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_105; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_105 = _GEN_58; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_21 = _ll_count_times_step_21_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_21_T = {56'h0, ll_count_times_step_21[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_21 = _ll_proba_base_21_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_21 = ll_proba_base_21[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_21 = {28'h0, _GEN_37[_restToBeat_T_21], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_106 = {71'h0, ll_proba_base_21, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_107 = {48'h0, _ll_add_to_proba_base_T_105} - {1'h0, _ll_add_to_proba_base_T_106}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_108 = _ll_add_to_proba_base_T_107[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_109 = _ll_add_to_proba_base_T_108 > {47'h0, restToBeat_21}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_21 = _ll_add_to_proba_base_T_109; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_21_T = ll_proba_base_21 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_21_T_1 = {1'h0, ll_proba_base_21} + {16'h0, ll_add_to_proba_base_21}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_21_T_2 = _ll_proba_21_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_21_T_3 = _ll_proba_21_T ? _ll_proba_21_T_2 : ll_proba_base_21; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_21 = _ll_proba_21_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_59 = {64'h0, ll_count_22} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_22_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_22_T = _GEN_59; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_110; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_110 = _GEN_59; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_22 = _ll_count_times_step_22_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_22_T = {56'h0, ll_count_times_step_22[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_22 = _ll_proba_base_22_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_22 = ll_proba_base_22[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_22 = {28'h0, _GEN_37[_restToBeat_T_22], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_111 = {71'h0, ll_proba_base_22, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_112 = {48'h0, _ll_add_to_proba_base_T_110} - {1'h0, _ll_add_to_proba_base_T_111}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_113 = _ll_add_to_proba_base_T_112[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_114 = _ll_add_to_proba_base_T_113 > {47'h0, restToBeat_22}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_22 = _ll_add_to_proba_base_T_114; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_22_T = ll_proba_base_22 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_22_T_1 = {1'h0, ll_proba_base_22} + {16'h0, ll_add_to_proba_base_22}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_22_T_2 = _ll_proba_22_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_22_T_3 = _ll_proba_22_T ? _ll_proba_22_T_2 : ll_proba_base_22; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_22 = _ll_proba_22_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_60 = {64'h0, ll_count_23} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_23_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_23_T = _GEN_60; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_115; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_115 = _GEN_60; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_23 = _ll_count_times_step_23_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_23_T = {56'h0, ll_count_times_step_23[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_23 = _ll_proba_base_23_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_23 = ll_proba_base_23[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_23 = {28'h0, _GEN_37[_restToBeat_T_23], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_116 = {71'h0, ll_proba_base_23, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_117 = {48'h0, _ll_add_to_proba_base_T_115} - {1'h0, _ll_add_to_proba_base_T_116}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_118 = _ll_add_to_proba_base_T_117[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_119 = _ll_add_to_proba_base_T_118 > {47'h0, restToBeat_23}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_23 = _ll_add_to_proba_base_T_119; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_23_T = ll_proba_base_23 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_23_T_1 = {1'h0, ll_proba_base_23} + {16'h0, ll_add_to_proba_base_23}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_23_T_2 = _ll_proba_23_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_23_T_3 = _ll_proba_23_T ? _ll_proba_23_T_2 : ll_proba_base_23; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_23 = _ll_proba_23_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_61 = {64'h0, ll_count_24} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_24_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_24_T = _GEN_61; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_120; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_120 = _GEN_61; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_24 = _ll_count_times_step_24_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_24_T = {56'h0, ll_count_times_step_24[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_24 = _ll_proba_base_24_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_24 = ll_proba_base_24[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_24 = {28'h0, _GEN_37[_restToBeat_T_24], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_121 = {71'h0, ll_proba_base_24, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_122 = {48'h0, _ll_add_to_proba_base_T_120} - {1'h0, _ll_add_to_proba_base_T_121}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_123 = _ll_add_to_proba_base_T_122[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_124 = _ll_add_to_proba_base_T_123 > {47'h0, restToBeat_24}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_24 = _ll_add_to_proba_base_T_124; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_24_T = ll_proba_base_24 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_24_T_1 = {1'h0, ll_proba_base_24} + {16'h0, ll_add_to_proba_base_24}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_24_T_2 = _ll_proba_24_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_24_T_3 = _ll_proba_24_T ? _ll_proba_24_T_2 : ll_proba_base_24; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_24 = _ll_proba_24_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_62 = {64'h0, ll_count_25} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_25_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_25_T = _GEN_62; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_125; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_125 = _GEN_62; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_25 = _ll_count_times_step_25_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_25_T = {56'h0, ll_count_times_step_25[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_25 = _ll_proba_base_25_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_25 = ll_proba_base_25[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_25 = {28'h0, _GEN_37[_restToBeat_T_25], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_126 = {71'h0, ll_proba_base_25, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_127 = {48'h0, _ll_add_to_proba_base_T_125} - {1'h0, _ll_add_to_proba_base_T_126}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_128 = _ll_add_to_proba_base_T_127[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_129 = _ll_add_to_proba_base_T_128 > {47'h0, restToBeat_25}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_25 = _ll_add_to_proba_base_T_129; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_25_T = ll_proba_base_25 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_25_T_1 = {1'h0, ll_proba_base_25} + {16'h0, ll_add_to_proba_base_25}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_25_T_2 = _ll_proba_25_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_25_T_3 = _ll_proba_25_T ? _ll_proba_25_T_2 : ll_proba_base_25; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_25 = _ll_proba_25_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_63 = {64'h0, ll_count_26} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_26_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_26_T = _GEN_63; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_130; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_130 = _GEN_63; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_26 = _ll_count_times_step_26_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_26_T = {56'h0, ll_count_times_step_26[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_26 = _ll_proba_base_26_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_26 = ll_proba_base_26[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_26 = {28'h0, _GEN_37[_restToBeat_T_26], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_131 = {71'h0, ll_proba_base_26, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_132 = {48'h0, _ll_add_to_proba_base_T_130} - {1'h0, _ll_add_to_proba_base_T_131}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_133 = _ll_add_to_proba_base_T_132[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_134 = _ll_add_to_proba_base_T_133 > {47'h0, restToBeat_26}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_26 = _ll_add_to_proba_base_T_134; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_26_T = ll_proba_base_26 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_26_T_1 = {1'h0, ll_proba_base_26} + {16'h0, ll_add_to_proba_base_26}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_26_T_2 = _ll_proba_26_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_26_T_3 = _ll_proba_26_T ? _ll_proba_26_T_2 : ll_proba_base_26; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_26 = _ll_proba_26_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_64 = {64'h0, ll_count_27} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_27_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_27_T = _GEN_64; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_135; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_135 = _GEN_64; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_27 = _ll_count_times_step_27_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_27_T = {56'h0, ll_count_times_step_27[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_27 = _ll_proba_base_27_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_27 = ll_proba_base_27[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_27 = {28'h0, _GEN_37[_restToBeat_T_27], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_136 = {71'h0, ll_proba_base_27, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_137 = {48'h0, _ll_add_to_proba_base_T_135} - {1'h0, _ll_add_to_proba_base_T_136}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_138 = _ll_add_to_proba_base_T_137[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_139 = _ll_add_to_proba_base_T_138 > {47'h0, restToBeat_27}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_27 = _ll_add_to_proba_base_T_139; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_27_T = ll_proba_base_27 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_27_T_1 = {1'h0, ll_proba_base_27} + {16'h0, ll_add_to_proba_base_27}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_27_T_2 = _ll_proba_27_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_27_T_3 = _ll_proba_27_T ? _ll_proba_27_T_2 : ll_proba_base_27; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_27 = _ll_proba_27_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_65 = {64'h0, ll_count_28} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_28_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_28_T = _GEN_65; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_140; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_140 = _GEN_65; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_28 = _ll_count_times_step_28_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_28_T = {56'h0, ll_count_times_step_28[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_28 = _ll_proba_base_28_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_28 = ll_proba_base_28[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_28 = {28'h0, _GEN_37[_restToBeat_T_28], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_141 = {71'h0, ll_proba_base_28, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_142 = {48'h0, _ll_add_to_proba_base_T_140} - {1'h0, _ll_add_to_proba_base_T_141}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_143 = _ll_add_to_proba_base_T_142[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_144 = _ll_add_to_proba_base_T_143 > {47'h0, restToBeat_28}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_28 = _ll_add_to_proba_base_T_144; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_28_T = ll_proba_base_28 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_28_T_1 = {1'h0, ll_proba_base_28} + {16'h0, ll_add_to_proba_base_28}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_28_T_2 = _ll_proba_28_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_28_T_3 = _ll_proba_28_T ? _ll_proba_28_T_2 : ll_proba_base_28; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_28 = _ll_proba_28_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_66 = {64'h0, ll_count_29} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_29_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_29_T = _GEN_66; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_145; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_145 = _GEN_66; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_29 = _ll_count_times_step_29_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_29_T = {56'h0, ll_count_times_step_29[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_29 = _ll_proba_base_29_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_29 = ll_proba_base_29[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_29 = {28'h0, _GEN_37[_restToBeat_T_29], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_146 = {71'h0, ll_proba_base_29, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_147 = {48'h0, _ll_add_to_proba_base_T_145} - {1'h0, _ll_add_to_proba_base_T_146}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_148 = _ll_add_to_proba_base_T_147[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_149 = _ll_add_to_proba_base_T_148 > {47'h0, restToBeat_29}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_29 = _ll_add_to_proba_base_T_149; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_29_T = ll_proba_base_29 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_29_T_1 = {1'h0, ll_proba_base_29} + {16'h0, ll_add_to_proba_base_29}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_29_T_2 = _ll_proba_29_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_29_T_3 = _ll_proba_29_T ? _ll_proba_29_T_2 : ll_proba_base_29; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_29 = _ll_proba_29_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_67 = {64'h0, ll_count_30} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_30_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_30_T = _GEN_67; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_150; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_150 = _GEN_67; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_30 = _ll_count_times_step_30_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_30_T = {56'h0, ll_count_times_step_30[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_30 = _ll_proba_base_30_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_30 = ll_proba_base_30[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_30 = {28'h0, _GEN_37[_restToBeat_T_30], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_151 = {71'h0, ll_proba_base_30, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_152 = {48'h0, _ll_add_to_proba_base_T_150} - {1'h0, _ll_add_to_proba_base_T_151}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_153 = _ll_add_to_proba_base_T_152[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_154 = _ll_add_to_proba_base_T_153 > {47'h0, restToBeat_30}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_30 = _ll_add_to_proba_base_T_154; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_30_T = ll_proba_base_30 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_30_T_1 = {1'h0, ll_proba_base_30} + {16'h0, ll_add_to_proba_base_30}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_30_T_2 = _ll_proba_30_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_30_T_3 = _ll_proba_30_T ? _ll_proba_30_T_2 : ll_proba_base_30; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_30 = _ll_proba_30_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_68 = {64'h0, ll_count_31} * _GEN_35; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_31_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_31_T = _GEN_68; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_155; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_155 = _GEN_68; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_31 = _ll_count_times_step_31_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_31_T = {56'h0, ll_count_times_step_31[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_31 = _ll_proba_base_31_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_31 = ll_proba_base_31[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_31 = {28'h0, _GEN_37[_restToBeat_T_31], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_156 = {71'h0, ll_proba_base_31, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_157 = {48'h0, _ll_add_to_proba_base_T_155} - {1'h0, _ll_add_to_proba_base_T_156}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_158 = _ll_add_to_proba_base_T_157[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_159 = _ll_add_to_proba_base_T_158 > {47'h0, restToBeat_31}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_31 = _ll_add_to_proba_base_T_159; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_31_T = ll_proba_base_31 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_31_T_1 = {1'h0, ll_proba_base_31} + {16'h0, ll_add_to_proba_base_31}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_31_T_2 = _ll_proba_31_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_31_T_3 = _ll_proba_31_T ? _ll_proba_31_T_2 : ll_proba_base_31; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_31 = _ll_proba_31_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [15:0] _ll_normalizedCounter_0_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_normalizedCounter_1_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T = ll_normalizedCounter_0; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_2_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_4 = ll_normalizedCounter_1; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_3_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_8 = ll_normalizedCounter_2; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_4_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_12 = ll_normalizedCounter_3; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_5_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_16 = ll_normalizedCounter_4; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_6_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_20 = ll_normalizedCounter_5; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_7_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_24 = ll_normalizedCounter_6; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_8_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_28 = ll_normalizedCounter_7; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_9_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_32 = ll_normalizedCounter_8; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_10_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_36 = ll_normalizedCounter_9; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_11_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_40 = ll_normalizedCounter_10; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_12_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_44 = ll_normalizedCounter_11; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_13_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_48 = ll_normalizedCounter_12; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_14_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_52 = ll_normalizedCounter_13; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_15_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_56 = ll_normalizedCounter_14; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_16_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_60 = ll_normalizedCounter_15; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_17_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_64 = ll_normalizedCounter_16; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_18_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_68 = ll_normalizedCounter_17; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_19_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_72 = ll_normalizedCounter_18; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_20_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_76 = ll_normalizedCounter_19; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_21_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_80 = ll_normalizedCounter_20; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_22_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_84 = ll_normalizedCounter_21; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_23_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_88 = ll_normalizedCounter_22; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_24_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_92 = ll_normalizedCounter_23; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_25_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_96 = ll_normalizedCounter_24; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_26_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_100 = ll_normalizedCounter_25; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_27_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_104 = ll_normalizedCounter_26; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_28_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_108 = ll_normalizedCounter_27; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_29_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_112 = ll_normalizedCounter_28; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_30_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_116 = ll_normalizedCounter_29; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_31_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_120 = ll_normalizedCounter_30; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] ll_normalizedCounter_31; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] _ll_ncountSumStill2Dist_T_124 = ll_normalizedCounter_31; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] ll_normalizedCounterMaxAdjusted_0; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_1; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_2; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_3; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_4; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_5; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_6; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_7; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_8; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_9; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_10; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_11; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_12; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_13; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_14; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_15; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_16; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_17; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_18; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_19; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_20; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_21; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_22; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_23; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_24; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_25; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_26; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_27; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_28; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_29; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_30; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_31; // @[FSECompressorDicBuilder.scala:278:49] wire _GEN_69 = {32'h0, ll_count_0} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T = _GEN_69; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T = _GEN_69; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_70 = {32'h0, ll_count_1} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_1; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_1 = _GEN_70; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_6; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_6 = _GEN_70; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_71 = {32'h0, ll_count_2} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_2; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_2 = _GEN_71; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_12; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_12 = _GEN_71; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_72 = {32'h0, ll_count_3} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_3; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_3 = _GEN_72; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_18; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_18 = _GEN_72; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_73 = {32'h0, ll_count_4} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_4; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_4 = _GEN_73; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_24; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_24 = _GEN_73; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_74 = {32'h0, ll_count_5} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_5; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_5 = _GEN_74; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_30; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_30 = _GEN_74; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_75 = {32'h0, ll_count_6} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_6; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_6 = _GEN_75; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_36; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_36 = _GEN_75; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_76 = {32'h0, ll_count_7} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_7; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_7 = _GEN_76; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_42; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_42 = _GEN_76; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_77 = {32'h0, ll_count_8} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_8; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_8 = _GEN_77; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_48; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_48 = _GEN_77; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_78 = {32'h0, ll_count_9} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_9; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_9 = _GEN_78; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_54; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_54 = _GEN_78; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_79 = {32'h0, ll_count_10} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_10; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_10 = _GEN_79; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_60; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_60 = _GEN_79; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_80 = {32'h0, ll_count_11} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_11; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_11 = _GEN_80; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_66; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_66 = _GEN_80; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_81 = {32'h0, ll_count_12} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_12; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_12 = _GEN_81; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_72; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_72 = _GEN_81; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_82 = {32'h0, ll_count_13} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_13; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_13 = _GEN_82; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_78; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_78 = _GEN_82; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_83 = {32'h0, ll_count_14} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_14; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_14 = _GEN_83; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_84; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_84 = _GEN_83; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_84 = {32'h0, ll_count_15} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_15; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_15 = _GEN_84; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_90; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_90 = _GEN_84; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_85 = {32'h0, ll_count_16} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_16; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_16 = _GEN_85; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_96; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_96 = _GEN_85; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_86 = {32'h0, ll_count_17} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_17; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_17 = _GEN_86; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_102; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_102 = _GEN_86; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_87 = {32'h0, ll_count_18} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_18; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_18 = _GEN_87; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_108; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_108 = _GEN_87; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_88 = {32'h0, ll_count_19} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_19; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_19 = _GEN_88; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_114; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_114 = _GEN_88; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_89 = {32'h0, ll_count_20} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_20; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_20 = _GEN_89; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_120; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_120 = _GEN_89; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_90 = {32'h0, ll_count_21} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_21; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_21 = _GEN_90; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_126; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_126 = _GEN_90; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_91 = {32'h0, ll_count_22} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_22; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_22 = _GEN_91; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_132; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_132 = _GEN_91; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_92 = {32'h0, ll_count_23} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_23; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_23 = _GEN_92; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_138; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_138 = _GEN_92; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_93 = {32'h0, ll_count_24} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_24; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_24 = _GEN_93; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_144; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_144 = _GEN_93; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_94 = {32'h0, ll_count_25} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_25; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_25 = _GEN_94; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_150; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_150 = _GEN_94; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_95 = {32'h0, ll_count_26} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_26; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_26 = _GEN_95; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_156; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_156 = _GEN_95; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_96 = {32'h0, ll_count_27} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_27; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_27 = _GEN_96; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_162; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_162 = _GEN_96; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_97 = {32'h0, ll_count_28} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_28; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_28 = _GEN_97; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_168; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_168 = _GEN_97; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_98 = {32'h0, ll_count_29} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_29; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_29 = _GEN_98; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_174; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_174 = _GEN_98; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_99 = {32'h0, ll_count_30} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_30; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_30 = _GEN_99; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_180; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_180 = _GEN_99; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_100 = {32'h0, ll_count_31} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_31; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_31 = _GEN_100; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_186; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_186 = _GEN_100; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _ll_count_has_nbseq_1_as_value_T_32 = _ll_count_has_nbseq_1_as_value_T \| _ll_count_has_nbseq_1_as_value_T_1; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_33 = _ll_count_has_nbseq_1_as_value_T_32 \| _ll_count_has_nbseq_1_as_value_T_2; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_34 = _ll_count_has_nbseq_1_as_value_T_33 \| _ll_count_has_nbseq_1_as_value_T_3; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_35 = _ll_count_has_nbseq_1_as_value_T_34 \| _ll_count_has_nbseq_1_as_value_T_4; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_36 = _ll_count_has_nbseq_1_as_value_T_35 \| _ll_count_has_nbseq_1_as_value_T_5; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_37 = _ll_count_has_nbseq_1_as_value_T_36 \| _ll_count_has_nbseq_1_as_value_T_6; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_38 = _ll_count_has_nbseq_1_as_value_T_37 \| _ll_count_has_nbseq_1_as_value_T_7; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_39 = _ll_count_has_nbseq_1_as_value_T_38 \| _ll_count_has_nbseq_1_as_value_T_8; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_40 = _ll_count_has_nbseq_1_as_value_T_39 \| _ll_count_has_nbseq_1_as_value_T_9; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_41 = _ll_count_has_nbseq_1_as_value_T_40 \| _ll_count_has_nbseq_1_as_value_T_10; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_42 = _ll_count_has_nbseq_1_as_value_T_41 \| _ll_count_has_nbseq_1_as_value_T_11; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_43 = _ll_count_has_nbseq_1_as_value_T_42 \| _ll_count_has_nbseq_1_as_value_T_12; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_44 = _ll_count_has_nbseq_1_as_value_T_43 \| _ll_count_has_nbseq_1_as_value_T_13; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_45 = _ll_count_has_nbseq_1_as_value_T_44 \| _ll_count_has_nbseq_1_as_value_T_14; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_46 = _ll_count_has_nbseq_1_as_value_T_45 \| _ll_count_has_nbseq_1_as_value_T_15; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_47 = _ll_count_has_nbseq_1_as_value_T_46 \| _ll_count_has_nbseq_1_as_value_T_16; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_48 = _ll_count_has_nbseq_1_as_value_T_47 \| _ll_count_has_nbseq_1_as_value_T_17; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_49 = _ll_count_has_nbseq_1_as_value_T_48 \| _ll_count_has_nbseq_1_as_value_T_18; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_50 = _ll_count_has_nbseq_1_as_value_T_49 \| _ll_count_has_nbseq_1_as_value_T_19; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_51 = _ll_count_has_nbseq_1_as_value_T_50 \| _ll_count_has_nbseq_1_as_value_T_20; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_52 = _ll_count_has_nbseq_1_as_value_T_51 \| _ll_count_has_nbseq_1_as_value_T_21; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_53 = _ll_count_has_nbseq_1_as_value_T_52 \| _ll_count_has_nbseq_1_as_value_T_22; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_54 = _ll_count_has_nbseq_1_as_value_T_53 \| _ll_count_has_nbseq_1_as_value_T_23; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_55 = _ll_count_has_nbseq_1_as_value_T_54 \| _ll_count_has_nbseq_1_as_value_T_24; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_56 = _ll_count_has_nbseq_1_as_value_T_55 \| _ll_count_has_nbseq_1_as_value_T_25; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_57 = _ll_count_has_nbseq_1_as_value_T_56 \| _ll_count_has_nbseq_1_as_value_T_26; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_58 = _ll_count_has_nbseq_1_as_value_T_57 \| _ll_count_has_nbseq_1_as_value_T_27; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_59 = _ll_count_has_nbseq_1_as_value_T_58 \| _ll_count_has_nbseq_1_as_value_T_28; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_60 = _ll_count_has_nbseq_1_as_value_T_59 \| _ll_count_has_nbseq_1_as_value_T_29; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_61 = _ll_count_has_nbseq_1_as_value_T_60 \| _ll_count_has_nbseq_1_as_value_T_30; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire ll_count_has_nbseq_1_as_value = _ll_count_has_nbseq_1_as_value_T_61 \| _ll_count_has_nbseq_1_as_value_T_31; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _GEN_101 = ll_count_0 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_0_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_0_T = _GEN_101; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_1; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_1 = _GEN_101; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_102 = ll_count_0 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_0_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_0_T_1 = _GEN_102; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T = _GEN_102; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_3; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_3 = _GEN_102; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_0_T_2 = _ll_normalizedCounter_0_T_1 ? ll_lowProbCount : ll_proba_0; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_0_T_3 = _ll_normalizedCounter_0_T ? 16'h0 : _ll_normalizedCounter_0_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_0 = _ll_normalizedCounter_0_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_103 = ll_count_1 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_1_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_1_T = _GEN_103; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_7; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_7 = _GEN_103; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_104 = ll_count_1 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_1_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_1_T_1 = _GEN_104; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_3; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_3 = _GEN_104; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_9; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_9 = _GEN_104; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_1_T_2 = _ll_normalizedCounter_1_T_1 ? ll_lowProbCount : ll_proba_1; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_1_T_3 = _ll_normalizedCounter_1_T ? 16'h0 : _ll_normalizedCounter_1_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_1 = _ll_normalizedCounter_1_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_105 = ll_count_2 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_2_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_2_T = _GEN_105; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_13; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_13 = _GEN_105; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_106 = ll_count_2 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_2_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_2_T_1 = _GEN_106; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_6; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_6 = _GEN_106; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_15; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_15 = _GEN_106; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_2_T_2 = _ll_normalizedCounter_2_T_1 ? ll_lowProbCount : ll_proba_2; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_2_T_3 = _ll_normalizedCounter_2_T ? 16'h0 : _ll_normalizedCounter_2_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_2 = _ll_normalizedCounter_2_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_107 = ll_count_3 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_3_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_3_T = _GEN_107; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_19; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_19 = _GEN_107; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_108 = ll_count_3 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_3_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_3_T_1 = _GEN_108; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_9; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_9 = _GEN_108; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_21; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_21 = _GEN_108; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_3_T_2 = _ll_normalizedCounter_3_T_1 ? ll_lowProbCount : ll_proba_3; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_3_T_3 = _ll_normalizedCounter_3_T ? 16'h0 : _ll_normalizedCounter_3_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_3 = _ll_normalizedCounter_3_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_109 = ll_count_4 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_4_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_4_T = _GEN_109; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_25; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_25 = _GEN_109; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_110 = ll_count_4 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_4_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_4_T_1 = _GEN_110; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_12; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_12 = _GEN_110; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_27; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_27 = _GEN_110; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_4_T_2 = _ll_normalizedCounter_4_T_1 ? ll_lowProbCount : ll_proba_4; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_4_T_3 = _ll_normalizedCounter_4_T ? 16'h0 : _ll_normalizedCounter_4_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_4 = _ll_normalizedCounter_4_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_111 = ll_count_5 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_5_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_5_T = _GEN_111; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_31; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_31 = _GEN_111; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_112 = ll_count_5 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_5_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_5_T_1 = _GEN_112; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_15; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_15 = _GEN_112; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_33; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_33 = _GEN_112; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_5_T_2 = _ll_normalizedCounter_5_T_1 ? ll_lowProbCount : ll_proba_5; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_5_T_3 = _ll_normalizedCounter_5_T ? 16'h0 : _ll_normalizedCounter_5_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_5 = _ll_normalizedCounter_5_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_113 = ll_count_6 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_6_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_6_T = _GEN_113; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_37; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_37 = _GEN_113; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_114 = ll_count_6 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_6_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_6_T_1 = _GEN_114; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_18; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_18 = _GEN_114; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_39; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_39 = _GEN_114; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_6_T_2 = _ll_normalizedCounter_6_T_1 ? ll_lowProbCount : ll_proba_6; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_6_T_3 = _ll_normalizedCounter_6_T ? 16'h0 : _ll_normalizedCounter_6_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_6 = _ll_normalizedCounter_6_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_115 = ll_count_7 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_7_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_7_T = _GEN_115; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_43; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_43 = _GEN_115; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_116 = ll_count_7 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_7_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_7_T_1 = _GEN_116; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_21; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_21 = _GEN_116; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_45; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_45 = _GEN_116; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_7_T_2 = _ll_normalizedCounter_7_T_1 ? ll_lowProbCount : ll_proba_7; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_7_T_3 = _ll_normalizedCounter_7_T ? 16'h0 : _ll_normalizedCounter_7_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_7 = _ll_normalizedCounter_7_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_117 = ll_count_8 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_8_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_8_T = _GEN_117; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_49; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_49 = _GEN_117; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_118 = ll_count_8 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_8_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_8_T_1 = _GEN_118; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_24; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_24 = _GEN_118; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_51; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_51 = _GEN_118; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_8_T_2 = _ll_normalizedCounter_8_T_1 ? ll_lowProbCount : ll_proba_8; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_8_T_3 = _ll_normalizedCounter_8_T ? 16'h0 : _ll_normalizedCounter_8_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_8 = _ll_normalizedCounter_8_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_119 = ll_count_9 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_9_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_9_T = _GEN_119; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_55; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_55 = _GEN_119; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_120 = ll_count_9 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_9_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_9_T_1 = _GEN_120; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_27; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_27 = _GEN_120; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_57; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_57 = _GEN_120; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_9_T_2 = _ll_normalizedCounter_9_T_1 ? ll_lowProbCount : ll_proba_9; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_9_T_3 = _ll_normalizedCounter_9_T ? 16'h0 : _ll_normalizedCounter_9_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_9 = _ll_normalizedCounter_9_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_121 = ll_count_10 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_10_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_10_T = _GEN_121; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_61; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_61 = _GEN_121; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_122 = ll_count_10 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_10_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_10_T_1 = _GEN_122; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_30; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_30 = _GEN_122; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_63; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_63 = _GEN_122; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_10_T_2 = _ll_normalizedCounter_10_T_1 ? ll_lowProbCount : ll_proba_10; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_10_T_3 = _ll_normalizedCounter_10_T ? 16'h0 : _ll_normalizedCounter_10_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_10 = _ll_normalizedCounter_10_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_123 = ll_count_11 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_11_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_11_T = _GEN_123; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_67; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_67 = _GEN_123; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_124 = ll_count_11 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_11_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_11_T_1 = _GEN_124; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_33; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_33 = _GEN_124; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_69; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_69 = _GEN_124; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_11_T_2 = _ll_normalizedCounter_11_T_1 ? ll_lowProbCount : ll_proba_11; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_11_T_3 = _ll_normalizedCounter_11_T ? 16'h0 : _ll_normalizedCounter_11_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_11 = _ll_normalizedCounter_11_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_125 = ll_count_12 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_12_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_12_T = _GEN_125; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_73; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_73 = _GEN_125; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_126 = ll_count_12 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_12_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_12_T_1 = _GEN_126; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_36; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_36 = _GEN_126; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_75; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_75 = _GEN_126; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_12_T_2 = _ll_normalizedCounter_12_T_1 ? ll_lowProbCount : ll_proba_12; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_12_T_3 = _ll_normalizedCounter_12_T ? 16'h0 : _ll_normalizedCounter_12_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_12 = _ll_normalizedCounter_12_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_127 = ll_count_13 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_13_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_13_T = _GEN_127; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_79; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_79 = _GEN_127; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_128 = ll_count_13 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_13_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_13_T_1 = _GEN_128; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_39; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_39 = _GEN_128; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_81; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_81 = _GEN_128; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_13_T_2 = _ll_normalizedCounter_13_T_1 ? ll_lowProbCount : ll_proba_13; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_13_T_3 = _ll_normalizedCounter_13_T ? 16'h0 : _ll_normalizedCounter_13_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_13 = _ll_normalizedCounter_13_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_129 = ll_count_14 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_14_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_14_T = _GEN_129; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_85; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_85 = _GEN_129; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_130 = ll_count_14 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_14_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_14_T_1 = _GEN_130; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_42; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_42 = _GEN_130; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_87; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_87 = _GEN_130; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_14_T_2 = _ll_normalizedCounter_14_T_1 ? ll_lowProbCount : ll_proba_14; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_14_T_3 = _ll_normalizedCounter_14_T ? 16'h0 : _ll_normalizedCounter_14_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_14 = _ll_normalizedCounter_14_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_131 = ll_count_15 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_15_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_15_T = _GEN_131; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_91; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_91 = _GEN_131; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_132 = ll_count_15 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_15_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_15_T_1 = _GEN_132; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_45; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_45 = _GEN_132; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_93; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_93 = _GEN_132; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_15_T_2 = _ll_normalizedCounter_15_T_1 ? ll_lowProbCount : ll_proba_15; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_15_T_3 = _ll_normalizedCounter_15_T ? 16'h0 : _ll_normalizedCounter_15_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_15 = _ll_normalizedCounter_15_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_133 = ll_count_16 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_16_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_16_T = _GEN_133; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_97; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_97 = _GEN_133; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_134 = ll_count_16 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_16_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_16_T_1 = _GEN_134; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_48; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_48 = _GEN_134; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_99; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_99 = _GEN_134; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_16_T_2 = _ll_normalizedCounter_16_T_1 ? ll_lowProbCount : ll_proba_16; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_16_T_3 = _ll_normalizedCounter_16_T ? 16'h0 : _ll_normalizedCounter_16_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_16 = _ll_normalizedCounter_16_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_135 = ll_count_17 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_17_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_17_T = _GEN_135; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_103; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_103 = _GEN_135; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_136 = ll_count_17 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_17_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_17_T_1 = _GEN_136; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_51; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_51 = _GEN_136; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_105; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_105 = _GEN_136; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_17_T_2 = _ll_normalizedCounter_17_T_1 ? ll_lowProbCount : ll_proba_17; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_17_T_3 = _ll_normalizedCounter_17_T ? 16'h0 : _ll_normalizedCounter_17_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_17 = _ll_normalizedCounter_17_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_137 = ll_count_18 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_18_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_18_T = _GEN_137; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_109; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_109 = _GEN_137; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_138 = ll_count_18 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_18_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_18_T_1 = _GEN_138; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_54; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_54 = _GEN_138; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_111; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_111 = _GEN_138; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_18_T_2 = _ll_normalizedCounter_18_T_1 ? ll_lowProbCount : ll_proba_18; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_18_T_3 = _ll_normalizedCounter_18_T ? 16'h0 : _ll_normalizedCounter_18_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_18 = _ll_normalizedCounter_18_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_139 = ll_count_19 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_19_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_19_T = _GEN_139; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_115; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_115 = _GEN_139; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_140 = ll_count_19 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_19_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_19_T_1 = _GEN_140; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_57; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_57 = _GEN_140; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_117; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_117 = _GEN_140; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_19_T_2 = _ll_normalizedCounter_19_T_1 ? ll_lowProbCount : ll_proba_19; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_19_T_3 = _ll_normalizedCounter_19_T ? 16'h0 : _ll_normalizedCounter_19_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_19 = _ll_normalizedCounter_19_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_141 = ll_count_20 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_20_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_20_T = _GEN_141; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_121; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_121 = _GEN_141; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_142 = ll_count_20 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_20_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_20_T_1 = _GEN_142; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_60; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_60 = _GEN_142; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_123; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_123 = _GEN_142; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_20_T_2 = _ll_normalizedCounter_20_T_1 ? ll_lowProbCount : ll_proba_20; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_20_T_3 = _ll_normalizedCounter_20_T ? 16'h0 : _ll_normalizedCounter_20_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_20 = _ll_normalizedCounter_20_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_143 = ll_count_21 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_21_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_21_T = _GEN_143; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_127; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_127 = _GEN_143; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_144 = ll_count_21 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_21_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_21_T_1 = _GEN_144; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_63; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_63 = _GEN_144; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_129; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_129 = _GEN_144; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_21_T_2 = _ll_normalizedCounter_21_T_1 ? ll_lowProbCount : ll_proba_21; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_21_T_3 = _ll_normalizedCounter_21_T ? 16'h0 : _ll_normalizedCounter_21_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_21 = _ll_normalizedCounter_21_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_145 = ll_count_22 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_22_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_22_T = _GEN_145; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_133; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_133 = _GEN_145; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_146 = ll_count_22 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_22_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_22_T_1 = _GEN_146; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_66; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_66 = _GEN_146; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_135; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_135 = _GEN_146; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_22_T_2 = _ll_normalizedCounter_22_T_1 ? ll_lowProbCount : ll_proba_22; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_22_T_3 = _ll_normalizedCounter_22_T ? 16'h0 : _ll_normalizedCounter_22_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_22 = _ll_normalizedCounter_22_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_147 = ll_count_23 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_23_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_23_T = _GEN_147; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_139; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_139 = _GEN_147; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_148 = ll_count_23 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_23_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_23_T_1 = _GEN_148; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_69; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_69 = _GEN_148; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_141; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_141 = _GEN_148; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_23_T_2 = _ll_normalizedCounter_23_T_1 ? ll_lowProbCount : ll_proba_23; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_23_T_3 = _ll_normalizedCounter_23_T ? 16'h0 : _ll_normalizedCounter_23_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_23 = _ll_normalizedCounter_23_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_149 = ll_count_24 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_24_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_24_T = _GEN_149; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_145; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_145 = _GEN_149; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_150 = ll_count_24 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_24_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_24_T_1 = _GEN_150; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_72; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_72 = _GEN_150; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_147; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_147 = _GEN_150; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_24_T_2 = _ll_normalizedCounter_24_T_1 ? ll_lowProbCount : ll_proba_24; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_24_T_3 = _ll_normalizedCounter_24_T ? 16'h0 : _ll_normalizedCounter_24_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_24 = _ll_normalizedCounter_24_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_151 = ll_count_25 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_25_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_25_T = _GEN_151; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_151; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_151 = _GEN_151; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_152 = ll_count_25 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_25_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_25_T_1 = _GEN_152; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_75; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_75 = _GEN_152; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_153; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_153 = _GEN_152; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_25_T_2 = _ll_normalizedCounter_25_T_1 ? ll_lowProbCount : ll_proba_25; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_25_T_3 = _ll_normalizedCounter_25_T ? 16'h0 : _ll_normalizedCounter_25_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_25 = _ll_normalizedCounter_25_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_153 = ll_count_26 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_26_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_26_T = _GEN_153; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_157; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_157 = _GEN_153; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_154 = ll_count_26 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_26_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_26_T_1 = _GEN_154; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_78; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_78 = _GEN_154; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_159; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_159 = _GEN_154; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_26_T_2 = _ll_normalizedCounter_26_T_1 ? ll_lowProbCount : ll_proba_26; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_26_T_3 = _ll_normalizedCounter_26_T ? 16'h0 : _ll_normalizedCounter_26_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_26 = _ll_normalizedCounter_26_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_155 = ll_count_27 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_27_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_27_T = _GEN_155; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_163; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_163 = _GEN_155; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_156 = ll_count_27 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_27_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_27_T_1 = _GEN_156; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_81; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_81 = _GEN_156; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_165; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_165 = _GEN_156; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_27_T_2 = _ll_normalizedCounter_27_T_1 ? ll_lowProbCount : ll_proba_27; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_27_T_3 = _ll_normalizedCounter_27_T ? 16'h0 : _ll_normalizedCounter_27_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_27 = _ll_normalizedCounter_27_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_157 = ll_count_28 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_28_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_28_T = _GEN_157; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_169; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_169 = _GEN_157; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_158 = ll_count_28 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_28_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_28_T_1 = _GEN_158; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_84; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_84 = _GEN_158; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_171; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_171 = _GEN_158; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_28_T_2 = _ll_normalizedCounter_28_T_1 ? ll_lowProbCount : ll_proba_28; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_28_T_3 = _ll_normalizedCounter_28_T ? 16'h0 : _ll_normalizedCounter_28_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_28 = _ll_normalizedCounter_28_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_159 = ll_count_29 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_29_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_29_T = _GEN_159; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_175; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_175 = _GEN_159; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_160 = ll_count_29 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_29_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_29_T_1 = _GEN_160; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_87; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_87 = _GEN_160; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_177; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_177 = _GEN_160; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_29_T_2 = _ll_normalizedCounter_29_T_1 ? ll_lowProbCount : ll_proba_29; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_29_T_3 = _ll_normalizedCounter_29_T ? 16'h0 : _ll_normalizedCounter_29_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_29 = _ll_normalizedCounter_29_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_161 = ll_count_30 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_30_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_30_T = _GEN_161; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_181; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_181 = _GEN_161; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_162 = ll_count_30 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_30_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_30_T_1 = _GEN_162; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_90; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_90 = _GEN_162; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_183; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_183 = _GEN_162; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_30_T_2 = _ll_normalizedCounter_30_T_1 ? ll_lowProbCount : ll_proba_30; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_30_T_3 = _ll_normalizedCounter_30_T ? 16'h0 : _ll_normalizedCounter_30_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_30 = _ll_normalizedCounter_30_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_163 = ll_count_31 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_31_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_31_T = _GEN_163; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_187; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_187 = _GEN_163; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_164 = ll_count_31 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_31_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_31_T_1 = _GEN_164; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_93; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_93 = _GEN_164; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_189; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_189 = _GEN_164; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_31_T_2 = _ll_normalizedCounter_31_T_1 ? ll_lowProbCount : ll_proba_31; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_31_T_3 = _ll_normalizedCounter_31_T ? 16'h0 : _ll_normalizedCounter_31_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_31 = _ll_normalizedCounter_31_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _ll_smallOrEqToLowThresholdCount_T_1 = \|ll_count_0; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_2 = _ll_smallOrEqToLowThresholdCount_T & _ll_smallOrEqToLowThresholdCount_T_1; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_4 = \|ll_count_1; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_5 = _ll_smallOrEqToLowThresholdCount_T_3 & _ll_smallOrEqToLowThresholdCount_T_4; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_7 = \|ll_count_2; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_8 = _ll_smallOrEqToLowThresholdCount_T_6 & _ll_smallOrEqToLowThresholdCount_T_7; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_10 = \|ll_count_3; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_11 = _ll_smallOrEqToLowThresholdCount_T_9 & _ll_smallOrEqToLowThresholdCount_T_10; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_13 = \|ll_count_4; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_14 = _ll_smallOrEqToLowThresholdCount_T_12 & _ll_smallOrEqToLowThresholdCount_T_13; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_16 = \|ll_count_5; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_17 = _ll_smallOrEqToLowThresholdCount_T_15 & _ll_smallOrEqToLowThresholdCount_T_16; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_19 = \|ll_count_6; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_20 = _ll_smallOrEqToLowThresholdCount_T_18 & _ll_smallOrEqToLowThresholdCount_T_19; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_22 = \|ll_count_7; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_23 = _ll_smallOrEqToLowThresholdCount_T_21 & _ll_smallOrEqToLowThresholdCount_T_22; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_25 = \|ll_count_8; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_26 = _ll_smallOrEqToLowThresholdCount_T_24 & _ll_smallOrEqToLowThresholdCount_T_25; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_28 = \|ll_count_9; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_29 = _ll_smallOrEqToLowThresholdCount_T_27 & _ll_smallOrEqToLowThresholdCount_T_28; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_31 = \|ll_count_10; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_32 = _ll_smallOrEqToLowThresholdCount_T_30 & _ll_smallOrEqToLowThresholdCount_T_31; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_34 = \|ll_count_11; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_35 = _ll_smallOrEqToLowThresholdCount_T_33 & _ll_smallOrEqToLowThresholdCount_T_34; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_37 = \|ll_count_12; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_38 = _ll_smallOrEqToLowThresholdCount_T_36 & _ll_smallOrEqToLowThresholdCount_T_37; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_40 = \|ll_count_13; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_41 = _ll_smallOrEqToLowThresholdCount_T_39 & _ll_smallOrEqToLowThresholdCount_T_40; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_43 = \|ll_count_14; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_44 = _ll_smallOrEqToLowThresholdCount_T_42 & _ll_smallOrEqToLowThresholdCount_T_43; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_46 = \|ll_count_15; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_47 = _ll_smallOrEqToLowThresholdCount_T_45 & _ll_smallOrEqToLowThresholdCount_T_46; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_49 = \|ll_count_16; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_50 = _ll_smallOrEqToLowThresholdCount_T_48 & _ll_smallOrEqToLowThresholdCount_T_49; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_52 = \|ll_count_17; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_53 = _ll_smallOrEqToLowThresholdCount_T_51 & _ll_smallOrEqToLowThresholdCount_T_52; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_55 = \|ll_count_18; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_56 = _ll_smallOrEqToLowThresholdCount_T_54 & _ll_smallOrEqToLowThresholdCount_T_55; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_58 = \|ll_count_19; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_59 = _ll_smallOrEqToLowThresholdCount_T_57 & _ll_smallOrEqToLowThresholdCount_T_58; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_61 = \|ll_count_20; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_62 = _ll_smallOrEqToLowThresholdCount_T_60 & _ll_smallOrEqToLowThresholdCount_T_61; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_64 = \|ll_count_21; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_65 = _ll_smallOrEqToLowThresholdCount_T_63 & _ll_smallOrEqToLowThresholdCount_T_64; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_67 = \|ll_count_22; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_68 = _ll_smallOrEqToLowThresholdCount_T_66 & _ll_smallOrEqToLowThresholdCount_T_67; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_70 = \|ll_count_23; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_71 = _ll_smallOrEqToLowThresholdCount_T_69 & _ll_smallOrEqToLowThresholdCount_T_70; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_73 = \|ll_count_24; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_74 = _ll_smallOrEqToLowThresholdCount_T_72 & _ll_smallOrEqToLowThresholdCount_T_73; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_76 = \|ll_count_25; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_77 = _ll_smallOrEqToLowThresholdCount_T_75 & _ll_smallOrEqToLowThresholdCount_T_76; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_79 = \|ll_count_26; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_80 = _ll_smallOrEqToLowThresholdCount_T_78 & _ll_smallOrEqToLowThresholdCount_T_79; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_82 = \|ll_count_27; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_83 = _ll_smallOrEqToLowThresholdCount_T_81 & _ll_smallOrEqToLowThresholdCount_T_82; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_85 = \|ll_count_28; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_86 = _ll_smallOrEqToLowThresholdCount_T_84 & _ll_smallOrEqToLowThresholdCount_T_85; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_88 = \|ll_count_29; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_89 = _ll_smallOrEqToLowThresholdCount_T_87 & _ll_smallOrEqToLowThresholdCount_T_88; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_91 = \|ll_count_30; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_92 = _ll_smallOrEqToLowThresholdCount_T_90 & _ll_smallOrEqToLowThresholdCount_T_91; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_94 = \|ll_count_31; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_95 = _ll_smallOrEqToLowThresholdCount_T_93 & _ll_smallOrEqToLowThresholdCount_T_94; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire [1:0] _ll_smallOrEqToLowThresholdCount_T_96 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_2} + {1'h0, _ll_smallOrEqToLowThresholdCount_T_5}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [2:0] _ll_smallOrEqToLowThresholdCount_T_97 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_96} + {2'h0, _ll_smallOrEqToLowThresholdCount_T_8}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [3:0] _ll_smallOrEqToLowThresholdCount_T_98 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_97} + {3'h0, _ll_smallOrEqToLowThresholdCount_T_11}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [4:0] _ll_smallOrEqToLowThresholdCount_T_99 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_98} + {4'h0, _ll_smallOrEqToLowThresholdCount_T_14}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [5:0] _ll_smallOrEqToLowThresholdCount_T_100 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_99} + {5'h0, _ll_smallOrEqToLowThresholdCount_T_17}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [6:0] _ll_smallOrEqToLowThresholdCount_T_101 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_100} + {6'h0, _ll_smallOrEqToLowThresholdCount_T_20}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [7:0] _ll_smallOrEqToLowThresholdCount_T_102 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_101} + {7'h0, _ll_smallOrEqToLowThresholdCount_T_23}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [8:0] _ll_smallOrEqToLowThresholdCount_T_103 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_102} + {8'h0, _ll_smallOrEqToLowThresholdCount_T_26}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [9:0] _ll_smallOrEqToLowThresholdCount_T_104 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_103} + {9'h0, _ll_smallOrEqToLowThresholdCount_T_29}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [10:0] _ll_smallOrEqToLowThresholdCount_T_105 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_104} + {10'h0, _ll_smallOrEqToLowThresholdCount_T_32}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [11:0] _ll_smallOrEqToLowThresholdCount_T_106 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_105} + {11'h0, _ll_smallOrEqToLowThresholdCount_T_35}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [12:0] _ll_smallOrEqToLowThresholdCount_T_107 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_106} + {12'h0, _ll_smallOrEqToLowThresholdCount_T_38}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [13:0] _ll_smallOrEqToLowThresholdCount_T_108 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_107} + {13'h0, _ll_smallOrEqToLowThresholdCount_T_41}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [14:0] _ll_smallOrEqToLowThresholdCount_T_109 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_108} + {14'h0, _ll_smallOrEqToLowThresholdCount_T_44}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [15:0] _ll_smallOrEqToLowThresholdCount_T_110 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_109} + {15'h0, _ll_smallOrEqToLowThresholdCount_T_47}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [16:0] _ll_smallOrEqToLowThresholdCount_T_111 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_110} + {16'h0, _ll_smallOrEqToLowThresholdCount_T_50}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [17:0] _ll_smallOrEqToLowThresholdCount_T_112 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_111} + {17'h0, _ll_smallOrEqToLowThresholdCount_T_53}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [18:0] _ll_smallOrEqToLowThresholdCount_T_113 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_112} + {18'h0, _ll_smallOrEqToLowThresholdCount_T_56}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [19:0] _ll_smallOrEqToLowThresholdCount_T_114 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_113} + {19'h0, _ll_smallOrEqToLowThresholdCount_T_59}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [20:0] _ll_smallOrEqToLowThresholdCount_T_115 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_114} + {20'h0, _ll_smallOrEqToLowThresholdCount_T_62}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [21:0] _ll_smallOrEqToLowThresholdCount_T_116 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_115} + {21'h0, _ll_smallOrEqToLowThresholdCount_T_65}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [22:0] _ll_smallOrEqToLowThresholdCount_T_117 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_116} + {22'h0, _ll_smallOrEqToLowThresholdCount_T_68}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [23:0] _ll_smallOrEqToLowThresholdCount_T_118 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_117} + {23'h0, _ll_smallOrEqToLowThresholdCount_T_71}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [24:0] _ll_smallOrEqToLowThresholdCount_T_119 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_118} + {24'h0, _ll_smallOrEqToLowThresholdCount_T_74}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [25:0] _ll_smallOrEqToLowThresholdCount_T_120 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_119} + {25'h0, _ll_smallOrEqToLowThresholdCount_T_77}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [26:0] _ll_smallOrEqToLowThresholdCount_T_121 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_120} + {26'h0, _ll_smallOrEqToLowThresholdCount_T_80}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [27:0] _ll_smallOrEqToLowThresholdCount_T_122 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_121} + {27'h0, _ll_smallOrEqToLowThresholdCount_T_83}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [28:0] _ll_smallOrEqToLowThresholdCount_T_123 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_122} + {28'h0, _ll_smallOrEqToLowThresholdCount_T_86}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [29:0] _ll_smallOrEqToLowThresholdCount_T_124 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_123} + {29'h0, _ll_smallOrEqToLowThresholdCount_T_89}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [30:0] _ll_smallOrEqToLowThresholdCount_T_125 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_124} + {30'h0, _ll_smallOrEqToLowThresholdCount_T_92}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [31:0] ll_smallOrEqToLowThresholdCount = {1'h0, _ll_smallOrEqToLowThresholdCount_T_125} + {31'h0, _ll_smallOrEqToLowThresholdCount_T_95}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire _ll_largerThanLowThresholdProbaSum_T_2 = _ll_largerThanLowThresholdProbaSum_T \| _ll_largerThanLowThresholdProbaSum_T_1; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_4 = _ll_largerThanLowThresholdProbaSum_T_2 \| _ll_largerThanLowThresholdProbaSum_T_3; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_5 = _ll_largerThanLowThresholdProbaSum_T_4 ? 16'h0 : ll_proba_0; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_8 = _ll_largerThanLowThresholdProbaSum_T_6 \| _ll_largerThanLowThresholdProbaSum_T_7; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_10 = _ll_largerThanLowThresholdProbaSum_T_8 \| _ll_largerThanLowThresholdProbaSum_T_9; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_11 = _ll_largerThanLowThresholdProbaSum_T_10 ? 16'h0 : ll_proba_1; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_14 = _ll_largerThanLowThresholdProbaSum_T_12 \| _ll_largerThanLowThresholdProbaSum_T_13; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_16 = _ll_largerThanLowThresholdProbaSum_T_14 \| _ll_largerThanLowThresholdProbaSum_T_15; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_17 = _ll_largerThanLowThresholdProbaSum_T_16 ? 16'h0 : ll_proba_2; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_20 = _ll_largerThanLowThresholdProbaSum_T_18 \| _ll_largerThanLowThresholdProbaSum_T_19; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_22 = _ll_largerThanLowThresholdProbaSum_T_20 \| _ll_largerThanLowThresholdProbaSum_T_21; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_23 = _ll_largerThanLowThresholdProbaSum_T_22 ? 16'h0 : ll_proba_3; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_26 = _ll_largerThanLowThresholdProbaSum_T_24 \| _ll_largerThanLowThresholdProbaSum_T_25; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_28 = _ll_largerThanLowThresholdProbaSum_T_26 \| _ll_largerThanLowThresholdProbaSum_T_27; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_29 = _ll_largerThanLowThresholdProbaSum_T_28 ? 16'h0 : ll_proba_4; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_32 = _ll_largerThanLowThresholdProbaSum_T_30 \| _ll_largerThanLowThresholdProbaSum_T_31; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_34 = _ll_largerThanLowThresholdProbaSum_T_32 \| _ll_largerThanLowThresholdProbaSum_T_33; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_35 = _ll_largerThanLowThresholdProbaSum_T_34 ? 16'h0 : ll_proba_5; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_38 = _ll_largerThanLowThresholdProbaSum_T_36 \| _ll_largerThanLowThresholdProbaSum_T_37; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_40 = _ll_largerThanLowThresholdProbaSum_T_38 \| _ll_largerThanLowThresholdProbaSum_T_39; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_41 = _ll_largerThanLowThresholdProbaSum_T_40 ? 16'h0 : ll_proba_6; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_44 = _ll_largerThanLowThresholdProbaSum_T_42 \| _ll_largerThanLowThresholdProbaSum_T_43; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_46 = _ll_largerThanLowThresholdProbaSum_T_44 \| _ll_largerThanLowThresholdProbaSum_T_45; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_47 = _ll_largerThanLowThresholdProbaSum_T_46 ? 16'h0 : ll_proba_7; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_50 = _ll_largerThanLowThresholdProbaSum_T_48 \| _ll_largerThanLowThresholdProbaSum_T_49; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_52 = _ll_largerThanLowThresholdProbaSum_T_50 \| _ll_largerThanLowThresholdProbaSum_T_51; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_53 = _ll_largerThanLowThresholdProbaSum_T_52 ? 16'h0 : ll_proba_8; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_56 = _ll_largerThanLowThresholdProbaSum_T_54 \| _ll_largerThanLowThresholdProbaSum_T_55; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_58 = _ll_largerThanLowThresholdProbaSum_T_56 \| _ll_largerThanLowThresholdProbaSum_T_57; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_59 = _ll_largerThanLowThresholdProbaSum_T_58 ? 16'h0 : ll_proba_9; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_62 = _ll_largerThanLowThresholdProbaSum_T_60 \| _ll_largerThanLowThresholdProbaSum_T_61; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_64 = _ll_largerThanLowThresholdProbaSum_T_62 \| _ll_largerThanLowThresholdProbaSum_T_63; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_65 = _ll_largerThanLowThresholdProbaSum_T_64 ? 16'h0 : ll_proba_10; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_68 = _ll_largerThanLowThresholdProbaSum_T_66 \| _ll_largerThanLowThresholdProbaSum_T_67; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_70 = _ll_largerThanLowThresholdProbaSum_T_68 \| _ll_largerThanLowThresholdProbaSum_T_69; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_71 = _ll_largerThanLowThresholdProbaSum_T_70 ? 16'h0 : ll_proba_11; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_74 = _ll_largerThanLowThresholdProbaSum_T_72 \| _ll_largerThanLowThresholdProbaSum_T_73; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_76 = _ll_largerThanLowThresholdProbaSum_T_74 \| _ll_largerThanLowThresholdProbaSum_T_75; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_77 = _ll_largerThanLowThresholdProbaSum_T_76 ? 16'h0 : ll_proba_12; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_80 = _ll_largerThanLowThresholdProbaSum_T_78 \| _ll_largerThanLowThresholdProbaSum_T_79; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_82 = _ll_largerThanLowThresholdProbaSum_T_80 \| _ll_largerThanLowThresholdProbaSum_T_81; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_83 = _ll_largerThanLowThresholdProbaSum_T_82 ? 16'h0 : ll_proba_13; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_86 = _ll_largerThanLowThresholdProbaSum_T_84 \| _ll_largerThanLowThresholdProbaSum_T_85; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_88 = _ll_largerThanLowThresholdProbaSum_T_86 \| _ll_largerThanLowThresholdProbaSum_T_87; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_89 = _ll_largerThanLowThresholdProbaSum_T_88 ? 16'h0 : ll_proba_14; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_92 = _ll_largerThanLowThresholdProbaSum_T_90 \| _ll_largerThanLowThresholdProbaSum_T_91; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_94 = _ll_largerThanLowThresholdProbaSum_T_92 \| _ll_largerThanLowThresholdProbaSum_T_93; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_95 = _ll_largerThanLowThresholdProbaSum_T_94 ? 16'h0 : ll_proba_15; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_98 = _ll_largerThanLowThresholdProbaSum_T_96 \| _ll_largerThanLowThresholdProbaSum_T_97; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_100 = _ll_largerThanLowThresholdProbaSum_T_98 \| _ll_largerThanLowThresholdProbaSum_T_99; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_101 = _ll_largerThanLowThresholdProbaSum_T_100 ? 16'h0 : ll_proba_16; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_104 = _ll_largerThanLowThresholdProbaSum_T_102 \| _ll_largerThanLowThresholdProbaSum_T_103; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_106 = _ll_largerThanLowThresholdProbaSum_T_104 \| _ll_largerThanLowThresholdProbaSum_T_105; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_107 = _ll_largerThanLowThresholdProbaSum_T_106 ? 16'h0 : ll_proba_17; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_110 = _ll_largerThanLowThresholdProbaSum_T_108 \| _ll_largerThanLowThresholdProbaSum_T_109; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_112 = _ll_largerThanLowThresholdProbaSum_T_110 \| _ll_largerThanLowThresholdProbaSum_T_111; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_113 = _ll_largerThanLowThresholdProbaSum_T_112 ? 16'h0 : ll_proba_18; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_116 = _ll_largerThanLowThresholdProbaSum_T_114 \| _ll_largerThanLowThresholdProbaSum_T_115; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_118 = _ll_largerThanLowThresholdProbaSum_T_116 \| _ll_largerThanLowThresholdProbaSum_T_117; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_119 = _ll_largerThanLowThresholdProbaSum_T_118 ? 16'h0 : ll_proba_19; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_122 = _ll_largerThanLowThresholdProbaSum_T_120 \| _ll_largerThanLowThresholdProbaSum_T_121; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_124 = _ll_largerThanLowThresholdProbaSum_T_122 \| _ll_largerThanLowThresholdProbaSum_T_123; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_125 = _ll_largerThanLowThresholdProbaSum_T_124 ? 16'h0 : ll_proba_20; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_128 = _ll_largerThanLowThresholdProbaSum_T_126 \| _ll_largerThanLowThresholdProbaSum_T_127; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_130 = _ll_largerThanLowThresholdProbaSum_T_128 \| _ll_largerThanLowThresholdProbaSum_T_129; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_131 = _ll_largerThanLowThresholdProbaSum_T_130 ? 16'h0 : ll_proba_21; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_134 = _ll_largerThanLowThresholdProbaSum_T_132 \| _ll_largerThanLowThresholdProbaSum_T_133; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_136 = _ll_largerThanLowThresholdProbaSum_T_134 \| _ll_largerThanLowThresholdProbaSum_T_135; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_137 = _ll_largerThanLowThresholdProbaSum_T_136 ? 16'h0 : ll_proba_22; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_140 = _ll_largerThanLowThresholdProbaSum_T_138 \| _ll_largerThanLowThresholdProbaSum_T_139; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_142 = _ll_largerThanLowThresholdProbaSum_T_140 \| _ll_largerThanLowThresholdProbaSum_T_141; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_143 = _ll_largerThanLowThresholdProbaSum_T_142 ? 16'h0 : ll_proba_23; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_146 = _ll_largerThanLowThresholdProbaSum_T_144 \| _ll_largerThanLowThresholdProbaSum_T_145; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_148 = _ll_largerThanLowThresholdProbaSum_T_146 \| _ll_largerThanLowThresholdProbaSum_T_147; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_149 = _ll_largerThanLowThresholdProbaSum_T_148 ? 16'h0 : ll_proba_24; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_152 = _ll_largerThanLowThresholdProbaSum_T_150 \| _ll_largerThanLowThresholdProbaSum_T_151; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_154 = _ll_largerThanLowThresholdProbaSum_T_152 \| _ll_largerThanLowThresholdProbaSum_T_153; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_155 = _ll_largerThanLowThresholdProbaSum_T_154 ? 16'h0 : ll_proba_25; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_158 = _ll_largerThanLowThresholdProbaSum_T_156 \| _ll_largerThanLowThresholdProbaSum_T_157; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_160 = _ll_largerThanLowThresholdProbaSum_T_158 \| _ll_largerThanLowThresholdProbaSum_T_159; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_161 = _ll_largerThanLowThresholdProbaSum_T_160 ? 16'h0 : ll_proba_26; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_164 = _ll_largerThanLowThresholdProbaSum_T_162 \| _ll_largerThanLowThresholdProbaSum_T_163; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_166 = _ll_largerThanLowThresholdProbaSum_T_164 \| _ll_largerThanLowThresholdProbaSum_T_165; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_167 = _ll_largerThanLowThresholdProbaSum_T_166 ? 16'h0 : ll_proba_27; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_170 = _ll_largerThanLowThresholdProbaSum_T_168 \| _ll_largerThanLowThresholdProbaSum_T_169; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_172 = _ll_largerThanLowThresholdProbaSum_T_170 \| _ll_largerThanLowThresholdProbaSum_T_171; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_173 = _ll_largerThanLowThresholdProbaSum_T_172 ? 16'h0 : ll_proba_28; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_176 = _ll_largerThanLowThresholdProbaSum_T_174 \| _ll_largerThanLowThresholdProbaSum_T_175; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_178 = _ll_largerThanLowThresholdProbaSum_T_176 \| _ll_largerThanLowThresholdProbaSum_T_177; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_179 = _ll_largerThanLowThresholdProbaSum_T_178 ? 16'h0 : ll_proba_29; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_182 = _ll_largerThanLowThresholdProbaSum_T_180 \| _ll_largerThanLowThresholdProbaSum_T_181; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_184 = _ll_largerThanLowThresholdProbaSum_T_182 \| _ll_largerThanLowThresholdProbaSum_T_183; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_185 = _ll_largerThanLowThresholdProbaSum_T_184 ? 16'h0 : ll_proba_30; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_188 = _ll_largerThanLowThresholdProbaSum_T_186 \| _ll_largerThanLowThresholdProbaSum_T_187; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_190 = _ll_largerThanLowThresholdProbaSum_T_188 \| _ll_largerThanLowThresholdProbaSum_T_189; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_191 = _ll_largerThanLowThresholdProbaSum_T_190 ? 16'h0 : ll_proba_31; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire [16:0] _ll_largerThanLowThresholdProbaSum_T_192 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_5} + {1'h0, _ll_largerThanLowThresholdProbaSum_T_11}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [17:0] _ll_largerThanLowThresholdProbaSum_T_193 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_192} + {2'h0, _ll_largerThanLowThresholdProbaSum_T_17}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [18:0] _ll_largerThanLowThresholdProbaSum_T_194 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_193} + {3'h0, _ll_largerThanLowThresholdProbaSum_T_23}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [19:0] _ll_largerThanLowThresholdProbaSum_T_195 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_194} + {4'h0, _ll_largerThanLowThresholdProbaSum_T_29}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [20:0] _ll_largerThanLowThresholdProbaSum_T_196 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_195} + {5'h0, _ll_largerThanLowThresholdProbaSum_T_35}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [21:0] _ll_largerThanLowThresholdProbaSum_T_197 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_196} + {6'h0, _ll_largerThanLowThresholdProbaSum_T_41}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [22:0] _ll_largerThanLowThresholdProbaSum_T_198 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_197} + {7'h0, _ll_largerThanLowThresholdProbaSum_T_47}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [23:0] _ll_largerThanLowThresholdProbaSum_T_199 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_198} + {8'h0, _ll_largerThanLowThresholdProbaSum_T_53}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [24:0] _ll_largerThanLowThresholdProbaSum_T_200 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_199} + {9'h0, _ll_largerThanLowThresholdProbaSum_T_59}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [25:0] _ll_largerThanLowThresholdProbaSum_T_201 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_200} + {10'h0, _ll_largerThanLowThresholdProbaSum_T_65}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [26:0] _ll_largerThanLowThresholdProbaSum_T_202 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_201} + {11'h0, _ll_largerThanLowThresholdProbaSum_T_71}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [27:0] _ll_largerThanLowThresholdProbaSum_T_203 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_202} + {12'h0, _ll_largerThanLowThresholdProbaSum_T_77}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [28:0] _ll_largerThanLowThresholdProbaSum_T_204 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_203} + {13'h0, _ll_largerThanLowThresholdProbaSum_T_83}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [29:0] _ll_largerThanLowThresholdProbaSum_T_205 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_204} + {14'h0, _ll_largerThanLowThresholdProbaSum_T_89}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [30:0] _ll_largerThanLowThresholdProbaSum_T_206 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_205} + {15'h0, _ll_largerThanLowThresholdProbaSum_T_95}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [31:0] _ll_largerThanLowThresholdProbaSum_T_207 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_206} + {16'h0, _ll_largerThanLowThresholdProbaSum_T_101}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [32:0] _ll_largerThanLowThresholdProbaSum_T_208 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_207} + {17'h0, _ll_largerThanLowThresholdProbaSum_T_107}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [33:0] _ll_largerThanLowThresholdProbaSum_T_209 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_208} + {18'h0, _ll_largerThanLowThresholdProbaSum_T_113}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [34:0] _ll_largerThanLowThresholdProbaSum_T_210 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_209} + {19'h0, _ll_largerThanLowThresholdProbaSum_T_119}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [35:0] _ll_largerThanLowThresholdProbaSum_T_211 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_210} + {20'h0, _ll_largerThanLowThresholdProbaSum_T_125}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [36:0] _ll_largerThanLowThresholdProbaSum_T_212 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_211} + {21'h0, _ll_largerThanLowThresholdProbaSum_T_131}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [37:0] _ll_largerThanLowThresholdProbaSum_T_213 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_212} + {22'h0, _ll_largerThanLowThresholdProbaSum_T_137}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [38:0] _ll_largerThanLowThresholdProbaSum_T_214 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_213} + {23'h0, _ll_largerThanLowThresholdProbaSum_T_143}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [39:0] _ll_largerThanLowThresholdProbaSum_T_215 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_214} + {24'h0, _ll_largerThanLowThresholdProbaSum_T_149}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [40:0] _ll_largerThanLowThresholdProbaSum_T_216 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_215} + {25'h0, _ll_largerThanLowThresholdProbaSum_T_155}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [41:0] _ll_largerThanLowThresholdProbaSum_T_217 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_216} + {26'h0, _ll_largerThanLowThresholdProbaSum_T_161}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [42:0] _ll_largerThanLowThresholdProbaSum_T_218 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_217} + {27'h0, _ll_largerThanLowThresholdProbaSum_T_167}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [43:0] _ll_largerThanLowThresholdProbaSum_T_219 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_218} + {28'h0, _ll_largerThanLowThresholdProbaSum_T_173}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [44:0] _ll_largerThanLowThresholdProbaSum_T_220 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_219} + {29'h0, _ll_largerThanLowThresholdProbaSum_T_179}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [45:0] _ll_largerThanLowThresholdProbaSum_T_221 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_220} + {30'h0, _ll_largerThanLowThresholdProbaSum_T_185}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [46:0] ll_largerThanLowThresholdProbaSum = {1'h0, _ll_largerThanLowThresholdProbaSum_T_221} + {31'h0, _ll_largerThanLowThresholdProbaSum_T_191}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire _ll_normalizedCounterMax_T = ll_normalizedCounter_0 > ll_normalizedCounter_1; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_1 = _ll_normalizedCounterMax_T ? ll_normalizedCounter_0 : ll_normalizedCounter_1; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_2 = ll_normalizedCounter_2 > ll_normalizedCounter_3; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_3 = _ll_normalizedCounterMax_T_2 ? ll_normalizedCounter_2 : ll_normalizedCounter_3; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_4 = ll_normalizedCounter_4 > ll_normalizedCounter_5; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_5 = _ll_normalizedCounterMax_T_4 ? ll_normalizedCounter_4 : ll_normalizedCounter_5; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_6 = ll_normalizedCounter_6 > ll_normalizedCounter_7; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_7 = _ll_normalizedCounterMax_T_6 ? ll_normalizedCounter_6 : ll_normalizedCounter_7; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_8 = ll_normalizedCounter_8 > ll_normalizedCounter_9; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_9 = _ll_normalizedCounterMax_T_8 ? ll_normalizedCounter_8 : ll_normalizedCounter_9; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_10 = ll_normalizedCounter_10 > ll_normalizedCounter_11; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_11 = _ll_normalizedCounterMax_T_10 ? ll_normalizedCounter_10 : ll_normalizedCounter_11; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_12 = ll_normalizedCounter_12 > ll_normalizedCounter_13; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_13 = _ll_normalizedCounterMax_T_12 ? ll_normalizedCounter_12 : ll_normalizedCounter_13; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_14 = ll_normalizedCounter_14 > ll_normalizedCounter_15; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_15 = _ll_normalizedCounterMax_T_14 ? ll_normalizedCounter_14 : ll_normalizedCounter_15; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_16 = ll_normalizedCounter_16 > ll_normalizedCounter_17; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_17 = _ll_normalizedCounterMax_T_16 ? ll_normalizedCounter_16 : ll_normalizedCounter_17; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_18 = ll_normalizedCounter_18 > ll_normalizedCounter_19; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_19 = _ll_normalizedCounterMax_T_18 ? ll_normalizedCounter_18 : ll_normalizedCounter_19; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_20 = ll_normalizedCounter_20 > ll_normalizedCounter_21; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_21 = _ll_normalizedCounterMax_T_20 ? ll_normalizedCounter_20 : ll_normalizedCounter_21; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_22 = ll_normalizedCounter_22 > ll_normalizedCounter_23; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_23 = _ll_normalizedCounterMax_T_22 ? ll_normalizedCounter_22 : ll_normalizedCounter_23; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_24 = ll_normalizedCounter_24 > ll_normalizedCounter_25; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_25 = _ll_normalizedCounterMax_T_24 ? ll_normalizedCounter_24 : ll_normalizedCounter_25; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_26 = ll_normalizedCounter_26 > ll_normalizedCounter_27; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_27 = _ll_normalizedCounterMax_T_26 ? ll_normalizedCounter_26 : ll_normalizedCounter_27; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_28 = ll_normalizedCounter_28 > ll_normalizedCounter_29; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_29 = _ll_normalizedCounterMax_T_28 ? ll_normalizedCounter_28 : ll_normalizedCounter_29; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_30 = ll_normalizedCounter_30 > ll_normalizedCounter_31; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_31 = _ll_normalizedCounterMax_T_30 ? ll_normalizedCounter_30 : ll_normalizedCounter_31; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_32 = _ll_normalizedCounterMax_T_1 > _ll_normalizedCounterMax_T_3; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_33 = _ll_normalizedCounterMax_T_32 ? _ll_normalizedCounterMax_T_1 : _ll_normalizedCounterMax_T_3; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_34 = _ll_normalizedCounterMax_T_5 > _ll_normalizedCounterMax_T_7; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_35 = _ll_normalizedCounterMax_T_34 ? _ll_normalizedCounterMax_T_5 : _ll_normalizedCounterMax_T_7; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_36 = _ll_normalizedCounterMax_T_9 > _ll_normalizedCounterMax_T_11; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_37 = _ll_normalizedCounterMax_T_36 ? _ll_normalizedCounterMax_T_9 : _ll_normalizedCounterMax_T_11; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_38 = _ll_normalizedCounterMax_T_13 > _ll_normalizedCounterMax_T_15; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_39 = _ll_normalizedCounterMax_T_38 ? _ll_normalizedCounterMax_T_13 : _ll_normalizedCounterMax_T_15; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_40 = _ll_normalizedCounterMax_T_17 > _ll_normalizedCounterMax_T_19; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_41 = _ll_normalizedCounterMax_T_40 ? _ll_normalizedCounterMax_T_17 : _ll_normalizedCounterMax_T_19; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_42 = _ll_normalizedCounterMax_T_21 > _ll_normalizedCounterMax_T_23; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_43 = _ll_normalizedCounterMax_T_42 ? _ll_normalizedCounterMax_T_21 : _ll_normalizedCounterMax_T_23; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_44 = _ll_normalizedCounterMax_T_25 > _ll_normalizedCounterMax_T_27; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_45 = _ll_normalizedCounterMax_T_44 ? _ll_normalizedCounterMax_T_25 : _ll_normalizedCounterMax_T_27; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_46 = _ll_normalizedCounterMax_T_29 > _ll_normalizedCounterMax_T_31; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_47 = _ll_normalizedCounterMax_T_46 ? _ll_normalizedCounterMax_T_29 : _ll_normalizedCounterMax_T_31; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_48 = _ll_normalizedCounterMax_T_33 > _ll_normalizedCounterMax_T_35; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_49 = _ll_normalizedCounterMax_T_48 ? _ll_normalizedCounterMax_T_33 : _ll_normalizedCounterMax_T_35; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_50 = _ll_normalizedCounterMax_T_37 > _ll_normalizedCounterMax_T_39; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_51 = _ll_normalizedCounterMax_T_50 ? _ll_normalizedCounterMax_T_37 : _ll_normalizedCounterMax_T_39; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_52 = _ll_normalizedCounterMax_T_41 > _ll_normalizedCounterMax_T_43; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_53 = _ll_normalizedCounterMax_T_52 ? _ll_normalizedCounterMax_T_41 : _ll_normalizedCounterMax_T_43; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_54 = _ll_normalizedCounterMax_T_45 > _ll_normalizedCounterMax_T_47; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_55 = _ll_normalizedCounterMax_T_54 ? _ll_normalizedCounterMax_T_45 : _ll_normalizedCounterMax_T_47; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_56 = _ll_normalizedCounterMax_T_49 > _ll_normalizedCounterMax_T_51; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_57 = _ll_normalizedCounterMax_T_56 ? _ll_normalizedCounterMax_T_49 : _ll_normalizedCounterMax_T_51; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_58 = _ll_normalizedCounterMax_T_53 > _ll_normalizedCounterMax_T_55; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_59 = _ll_normalizedCounterMax_T_58 ? _ll_normalizedCounterMax_T_53 : _ll_normalizedCounterMax_T_55; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_60 = _ll_normalizedCounterMax_T_57 > _ll_normalizedCounterMax_T_59; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] ll_normalizedCounterMax = _ll_normalizedCounterMax_T_60 ? _ll_normalizedCounterMax_T_57 : _ll_normalizedCounterMax_T_59; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _GEN_165 = ll_normalizedCounter_0 < ll_normalizedCounter_1; // @[FSECompressorDicBuilder.scala:277:38, :307:15] wire _ll_normalizedCounterMaxIdx_T; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T = _GEN_165; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_2; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_2 = _GEN_165; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_1 = _ll_normalizedCounterMaxIdx_T ? ll_normalizedCounter_1 : ll_normalizedCounter_0; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_3 = {15'h0, _ll_normalizedCounterMaxIdx_T_2}; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_166 = _ll_normalizedCounterMaxIdx_T_1 < ll_normalizedCounter_2; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_4; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_4 = _GEN_166; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_6; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_6 = _GEN_166; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_5 = _ll_normalizedCounterMaxIdx_T_4 ? ll_normalizedCounter_2 : _ll_normalizedCounterMaxIdx_T_1; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_7 = _ll_normalizedCounterMaxIdx_T_6 ? 16'h2 : _ll_normalizedCounterMaxIdx_T_3; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_167 = _ll_normalizedCounterMaxIdx_T_5 < ll_normalizedCounter_3; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_8; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_8 = _GEN_167; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_10; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_10 = _GEN_167; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_9 = _ll_normalizedCounterMaxIdx_T_8 ? ll_normalizedCounter_3 : _ll_normalizedCounterMaxIdx_T_5; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_11 = _ll_normalizedCounterMaxIdx_T_10 ? 16'h3 : _ll_normalizedCounterMaxIdx_T_7; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_168 = _ll_normalizedCounterMaxIdx_T_9 < ll_normalizedCounter_4; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_12; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_12 = _GEN_168; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_14; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_14 = _GEN_168; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_13 = _ll_normalizedCounterMaxIdx_T_12 ? ll_normalizedCounter_4 : _ll_normalizedCounterMaxIdx_T_9; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_15 = _ll_normalizedCounterMaxIdx_T_14 ? 16'h4 : _ll_normalizedCounterMaxIdx_T_11; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_169 = _ll_normalizedCounterMaxIdx_T_13 < ll_normalizedCounter_5; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_16; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_16 = _GEN_169; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_18; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_18 = _GEN_169; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_17 = _ll_normalizedCounterMaxIdx_T_16 ? ll_normalizedCounter_5 : _ll_normalizedCounterMaxIdx_T_13; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_19 = _ll_normalizedCounterMaxIdx_T_18 ? 16'h5 : _ll_normalizedCounterMaxIdx_T_15; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_170 = _ll_normalizedCounterMaxIdx_T_17 < ll_normalizedCounter_6; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_20; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_20 = _GEN_170; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_22; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_22 = _GEN_170; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_21 = _ll_normalizedCounterMaxIdx_T_20 ? ll_normalizedCounter_6 : _ll_normalizedCounterMaxIdx_T_17; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_23 = _ll_normalizedCounterMaxIdx_T_22 ? 16'h6 : _ll_normalizedCounterMaxIdx_T_19; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_171 = _ll_normalizedCounterMaxIdx_T_21 < ll_normalizedCounter_7; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_24; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_24 = _GEN_171; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_26; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_26 = _GEN_171; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_25 = _ll_normalizedCounterMaxIdx_T_24 ? ll_normalizedCounter_7 : _ll_normalizedCounterMaxIdx_T_21; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_27 = _ll_normalizedCounterMaxIdx_T_26 ? 16'h7 : _ll_normalizedCounterMaxIdx_T_23; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_172 = _ll_normalizedCounterMaxIdx_T_25 < ll_normalizedCounter_8; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_28; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_28 = _GEN_172; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_30; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_30 = _GEN_172; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_29 = _ll_normalizedCounterMaxIdx_T_28 ? ll_normalizedCounter_8 : _ll_normalizedCounterMaxIdx_T_25; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_31 = _ll_normalizedCounterMaxIdx_T_30 ? 16'h8 : _ll_normalizedCounterMaxIdx_T_27; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_173 = _ll_normalizedCounterMaxIdx_T_29 < ll_normalizedCounter_9; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_32; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_32 = _GEN_173; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_34; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_34 = _GEN_173; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_33 = _ll_normalizedCounterMaxIdx_T_32 ? ll_normalizedCounter_9 : _ll_normalizedCounterMaxIdx_T_29; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_35 = _ll_normalizedCounterMaxIdx_T_34 ? 16'h9 : _ll_normalizedCounterMaxIdx_T_31; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_174 = _ll_normalizedCounterMaxIdx_T_33 < ll_normalizedCounter_10; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_36; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_36 = _GEN_174; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_38; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_38 = _GEN_174; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_37 = _ll_normalizedCounterMaxIdx_T_36 ? ll_normalizedCounter_10 : _ll_normalizedCounterMaxIdx_T_33; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_39 = _ll_normalizedCounterMaxIdx_T_38 ? 16'hA : _ll_normalizedCounterMaxIdx_T_35; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_175 = _ll_normalizedCounterMaxIdx_T_37 < ll_normalizedCounter_11; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_40; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_40 = _GEN_175; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_42; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_42 = _GEN_175; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_41 = _ll_normalizedCounterMaxIdx_T_40 ? ll_normalizedCounter_11 : _ll_normalizedCounterMaxIdx_T_37; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_43 = _ll_normalizedCounterMaxIdx_T_42 ? 16'hB : _ll_normalizedCounterMaxIdx_T_39; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_176 = _ll_normalizedCounterMaxIdx_T_41 < ll_normalizedCounter_12; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_44; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_44 = _GEN_176; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_46; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_46 = _GEN_176; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_45 = _ll_normalizedCounterMaxIdx_T_44 ? ll_normalizedCounter_12 : _ll_normalizedCounterMaxIdx_T_41; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_47 = _ll_normalizedCounterMaxIdx_T_46 ? 16'hC : _ll_normalizedCounterMaxIdx_T_43; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_177 = _ll_normalizedCounterMaxIdx_T_45 < ll_normalizedCounter_13; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_48; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_48 = _GEN_177; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_50; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_50 = _GEN_177; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_49 = _ll_normalizedCounterMaxIdx_T_48 ? ll_normalizedCounter_13 : _ll_normalizedCounterMaxIdx_T_45; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_51 = _ll_normalizedCounterMaxIdx_T_50 ? 16'hD : _ll_normalizedCounterMaxIdx_T_47; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_178 = _ll_normalizedCounterMaxIdx_T_49 < ll_normalizedCounter_14; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_52; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_52 = _GEN_178; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_54; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_54 = _GEN_178; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_53 = _ll_normalizedCounterMaxIdx_T_52 ? ll_normalizedCounter_14 : _ll_normalizedCounterMaxIdx_T_49; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_55 = _ll_normalizedCounterMaxIdx_T_54 ? 16'hE : _ll_normalizedCounterMaxIdx_T_51; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_179 = _ll_normalizedCounterMaxIdx_T_53 < ll_normalizedCounter_15; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_56; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_56 = _GEN_179; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_58; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_58 = _GEN_179; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_57 = _ll_normalizedCounterMaxIdx_T_56 ? ll_normalizedCounter_15 : _ll_normalizedCounterMaxIdx_T_53; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_59 = _ll_normalizedCounterMaxIdx_T_58 ? 16'hF : _ll_normalizedCounterMaxIdx_T_55; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_180 = _ll_normalizedCounterMaxIdx_T_57 < ll_normalizedCounter_16; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_60; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_60 = _GEN_180; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_62; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_62 = _GEN_180; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_61 = _ll_normalizedCounterMaxIdx_T_60 ? ll_normalizedCounter_16 : _ll_normalizedCounterMaxIdx_T_57; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_63 = _ll_normalizedCounterMaxIdx_T_62 ? 16'h10 : _ll_normalizedCounterMaxIdx_T_59; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_181 = _ll_normalizedCounterMaxIdx_T_61 < ll_normalizedCounter_17; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_64; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_64 = _GEN_181; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_66; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_66 = _GEN_181; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_65 = _ll_normalizedCounterMaxIdx_T_64 ? ll_normalizedCounter_17 : _ll_normalizedCounterMaxIdx_T_61; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_67 = _ll_normalizedCounterMaxIdx_T_66 ? 16'h11 : _ll_normalizedCounterMaxIdx_T_63; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_182 = _ll_normalizedCounterMaxIdx_T_65 < ll_normalizedCounter_18; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_68; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_68 = _GEN_182; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_70; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_70 = _GEN_182; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_69 = _ll_normalizedCounterMaxIdx_T_68 ? ll_normalizedCounter_18 : _ll_normalizedCounterMaxIdx_T_65; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_71 = _ll_normalizedCounterMaxIdx_T_70 ? 16'h12 : _ll_normalizedCounterMaxIdx_T_67; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_183 = _ll_normalizedCounterMaxIdx_T_69 < ll_normalizedCounter_19; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_72; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_72 = _GEN_183; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_74; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_74 = _GEN_183; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_73 = _ll_normalizedCounterMaxIdx_T_72 ? ll_normalizedCounter_19 : _ll_normalizedCounterMaxIdx_T_69; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_75 = _ll_normalizedCounterMaxIdx_T_74 ? 16'h13 : _ll_normalizedCounterMaxIdx_T_71; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_184 = _ll_normalizedCounterMaxIdx_T_73 < ll_normalizedCounter_20; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_76; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_76 = _GEN_184; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_78; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_78 = _GEN_184; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_77 = _ll_normalizedCounterMaxIdx_T_76 ? ll_normalizedCounter_20 : _ll_normalizedCounterMaxIdx_T_73; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_79 = _ll_normalizedCounterMaxIdx_T_78 ? 16'h14 : _ll_normalizedCounterMaxIdx_T_75; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_185 = _ll_normalizedCounterMaxIdx_T_77 < ll_normalizedCounter_21; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_80; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_80 = _GEN_185; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_82; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_82 = _GEN_185; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_81 = _ll_normalizedCounterMaxIdx_T_80 ? ll_normalizedCounter_21 : _ll_normalizedCounterMaxIdx_T_77; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_83 = _ll_normalizedCounterMaxIdx_T_82 ? 16'h15 : _ll_normalizedCounterMaxIdx_T_79; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_186 = _ll_normalizedCounterMaxIdx_T_81 < ll_normalizedCounter_22; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_84; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_84 = _GEN_186; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_86; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_86 = _GEN_186; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_85 = _ll_normalizedCounterMaxIdx_T_84 ? ll_normalizedCounter_22 : _ll_normalizedCounterMaxIdx_T_81; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_87 = _ll_normalizedCounterMaxIdx_T_86 ? 16'h16 : _ll_normalizedCounterMaxIdx_T_83; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_187 = _ll_normalizedCounterMaxIdx_T_85 < ll_normalizedCounter_23; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_88; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_88 = _GEN_187; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_90; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_90 = _GEN_187; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_89 = _ll_normalizedCounterMaxIdx_T_88 ? ll_normalizedCounter_23 : _ll_normalizedCounterMaxIdx_T_85; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_91 = _ll_normalizedCounterMaxIdx_T_90 ? 16'h17 : _ll_normalizedCounterMaxIdx_T_87; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_188 = _ll_normalizedCounterMaxIdx_T_89 < ll_normalizedCounter_24; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_92; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_92 = _GEN_188; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_94; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_94 = _GEN_188; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_93 = _ll_normalizedCounterMaxIdx_T_92 ? ll_normalizedCounter_24 : _ll_normalizedCounterMaxIdx_T_89; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_95 = _ll_normalizedCounterMaxIdx_T_94 ? 16'h18 : _ll_normalizedCounterMaxIdx_T_91; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_189 = _ll_normalizedCounterMaxIdx_T_93 < ll_normalizedCounter_25; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_96; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_96 = _GEN_189; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_98; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_98 = _GEN_189; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_97 = _ll_normalizedCounterMaxIdx_T_96 ? ll_normalizedCounter_25 : _ll_normalizedCounterMaxIdx_T_93; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_99 = _ll_normalizedCounterMaxIdx_T_98 ? 16'h19 : _ll_normalizedCounterMaxIdx_T_95; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_190 = _ll_normalizedCounterMaxIdx_T_97 < ll_normalizedCounter_26; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_100; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_100 = _GEN_190; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_102; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_102 = _GEN_190; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_101 = _ll_normalizedCounterMaxIdx_T_100 ? ll_normalizedCounter_26 : _ll_normalizedCounterMaxIdx_T_97; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_103 = _ll_normalizedCounterMaxIdx_T_102 ? 16'h1A : _ll_normalizedCounterMaxIdx_T_99; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_191 = _ll_normalizedCounterMaxIdx_T_101 < ll_normalizedCounter_27; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_104; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_104 = _GEN_191; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_106; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_106 = _GEN_191; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_105 = _ll_normalizedCounterMaxIdx_T_104 ? ll_normalizedCounter_27 : _ll_normalizedCounterMaxIdx_T_101; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_107 = _ll_normalizedCounterMaxIdx_T_106 ? 16'h1B : _ll_normalizedCounterMaxIdx_T_103; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_192 = _ll_normalizedCounterMaxIdx_T_105 < ll_normalizedCounter_28; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_108; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_108 = _GEN_192; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_110; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_110 = _GEN_192; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_109 = _ll_normalizedCounterMaxIdx_T_108 ? ll_normalizedCounter_28 : _ll_normalizedCounterMaxIdx_T_105; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_111 = _ll_normalizedCounterMaxIdx_T_110 ? 16'h1C : _ll_normalizedCounterMaxIdx_T_107; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_193 = _ll_normalizedCounterMaxIdx_T_109 < ll_normalizedCounter_29; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_112; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_112 = _GEN_193; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_114; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_114 = _GEN_193; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_113 = _ll_normalizedCounterMaxIdx_T_112 ? ll_normalizedCounter_29 : _ll_normalizedCounterMaxIdx_T_109; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_115 = _ll_normalizedCounterMaxIdx_T_114 ? 16'h1D : _ll_normalizedCounterMaxIdx_T_111; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_194 = _ll_normalizedCounterMaxIdx_T_113 < ll_normalizedCounter_30; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_116; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_116 = _GEN_194; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_118; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_118 = _GEN_194; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_117 = _ll_normalizedCounterMaxIdx_T_116 ? ll_normalizedCounter_30 : _ll_normalizedCounterMaxIdx_T_113; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_119 = _ll_normalizedCounterMaxIdx_T_118 ? 16'h1E : _ll_normalizedCounterMaxIdx_T_115; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_195 = _ll_normalizedCounterMaxIdx_T_117 < ll_normalizedCounter_31; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_120; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_120 = _GEN_195; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_122; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_122 = _GEN_195; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_121 = _ll_normalizedCounterMaxIdx_T_120 ? ll_normalizedCounter_31 : _ll_normalizedCounterMaxIdx_T_117; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] ll_normalizedCounterMaxIdx = _ll_normalizedCounterMaxIdx_T_122 ? 16'h1F : _ll_normalizedCounterMaxIdx_T_119; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire [47:0] _ll_nxtStillToDistribute_T = 48'h40 - {1'h0, ll_largerThanLowThresholdProbaSum}; // @[FSECompressorDicBuilder.scala:298:14, :310:57] wire [46:0] _ll_nxtStillToDistribute_T_1 = _ll_nxtStillToDistribute_T[46:0]; // @[FSECompressorDicBuilder.scala:310:57] wire [47:0] _ll_nxtStillToDistribute_T_2 = {1'h0, _ll_nxtStillToDistribute_T_1} - {16'h0, ll_smallOrEqToLowThresholdCount}; // @[FSECompressorDicBuilder.scala:292:14, :310:{57,93}] wire [46:0] _ll_nxtStillToDistribute_T_3 = _ll_nxtStillToDistribute_T_2[46:0]; // @[FSECompressorDicBuilder.scala:310:93] wire [46:0] ll_nxtStillToDistribute = _ll_nxtStillToDistribute_T_3; // @[FSECompressorDicBuilder.scala:310:{93,128}] wire [47:0] _GEN_196 = {ll_nxtStillToDistribute[46], ll_nxtStillToDistribute}; // @[FSECompressorDicBuilder.scala:310:128, :311:43] wire [47:0] ll_negNxtStillToDistribute = _GEN_196 * 48'hFFFFFFFFFFFF; // @[FSECompressorDicBuilder.scala:311:43] wire [15:0] _fse_normalize_corner_case_T = {1'h0, ll_normalizedCounterMax[15:1]}; // @[FSECompressorDicBuilder.scala:300:78, :313:90] wire [15:0] _fse_normalize_corner_case_T_1 = _fse_normalize_corner_case_T; // @[FSECompressorDicBuilder.scala:313:{90,98}] wire fse_normalize_corner_case = $signed(ll_negNxtStillToDistribute) >= $signed({{32{_fse_normalize_corner_case_T_1[15]}}, _fse_normalize_corner_case_T_1}); // @[FSECompressorDicBuilder.scala:311:43, :313:{62,98}] reg fse_normalize_corner_case_reg; // @[FSECompressorDicBuilder.scala:314:46] wire _T_846 = dicBuilderState == 4'h2; // @[FSECompressorDicBuilder.scala:156:32, :316:25] wire _T_3 = _T_846 & _predefined_mode_q_io_enq_ready; // @[FSECompressorDicBuilder.scala:141:33, :316:{25,45}] wire [47:0] _ll_ncountSumStill2Dist_T_1 = {{32{_ll_ncountSumStill2Dist_T[15]}}, _ll_ncountSumStill2Dist_T} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_2 = _ll_ncountSumStill2Dist_T_1[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_3 = _ll_ncountSumStill2Dist_T_2; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist = _ll_ncountSumStill2Dist_T_3; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_0_T = ll_normalizedCounterMaxIdx == 16'h0; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_0_T_1 = _ll_normalizedCounterMaxAdjusted_0_T ? ll_ncountSumStill2Dist : {31'h0, ll_normalizedCounter_0}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_0 = _T_3 ? _ll_normalizedCounterMaxAdjusted_0_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_5 = {{32{_ll_ncountSumStill2Dist_T_4[15]}}, _ll_ncountSumStill2Dist_T_4} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_6 = _ll_ncountSumStill2Dist_T_5[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_7 = _ll_ncountSumStill2Dist_T_6; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_1 = _ll_ncountSumStill2Dist_T_7; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_1_T = ll_normalizedCounterMaxIdx == 16'h1; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_1_T_1 = _ll_normalizedCounterMaxAdjusted_1_T ? ll_ncountSumStill2Dist_1 : {31'h0, ll_normalizedCounter_1}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_1 = _T_3 ? _ll_normalizedCounterMaxAdjusted_1_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_9 = {{32{_ll_ncountSumStill2Dist_T_8[15]}}, _ll_ncountSumStill2Dist_T_8} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_10 = _ll_ncountSumStill2Dist_T_9[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_11 = _ll_ncountSumStill2Dist_T_10; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_2 = _ll_ncountSumStill2Dist_T_11; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_2_T = ll_normalizedCounterMaxIdx == 16'h2; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_2_T_1 = _ll_normalizedCounterMaxAdjusted_2_T ? ll_ncountSumStill2Dist_2 : {31'h0, ll_normalizedCounter_2}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_2 = _T_3 ? _ll_normalizedCounterMaxAdjusted_2_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_13 = {{32{_ll_ncountSumStill2Dist_T_12[15]}}, _ll_ncountSumStill2Dist_T_12} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_14 = _ll_ncountSumStill2Dist_T_13[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_15 = _ll_ncountSumStill2Dist_T_14; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_3 = _ll_ncountSumStill2Dist_T_15; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_3_T = ll_normalizedCounterMaxIdx == 16'h3; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_3_T_1 = _ll_normalizedCounterMaxAdjusted_3_T ? ll_ncountSumStill2Dist_3 : {31'h0, ll_normalizedCounter_3}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_3 = _T_3 ? _ll_normalizedCounterMaxAdjusted_3_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_17 = {{32{_ll_ncountSumStill2Dist_T_16[15]}}, _ll_ncountSumStill2Dist_T_16} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_18 = _ll_ncountSumStill2Dist_T_17[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_19 = _ll_ncountSumStill2Dist_T_18; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_4 = _ll_ncountSumStill2Dist_T_19; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_4_T = ll_normalizedCounterMaxIdx == 16'h4; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_4_T_1 = _ll_normalizedCounterMaxAdjusted_4_T ? ll_ncountSumStill2Dist_4 : {31'h0, ll_normalizedCounter_4}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_4 = _T_3 ? _ll_normalizedCounterMaxAdjusted_4_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_21 = {{32{_ll_ncountSumStill2Dist_T_20[15]}}, _ll_ncountSumStill2Dist_T_20} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_22 = _ll_ncountSumStill2Dist_T_21[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_23 = _ll_ncountSumStill2Dist_T_22; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_5 = _ll_ncountSumStill2Dist_T_23; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_5_T = ll_normalizedCounterMaxIdx == 16'h5; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_5_T_1 = _ll_normalizedCounterMaxAdjusted_5_T ? ll_ncountSumStill2Dist_5 : {31'h0, ll_normalizedCounter_5}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_5 = _T_3 ? _ll_normalizedCounterMaxAdjusted_5_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_25 = {{32{_ll_ncountSumStill2Dist_T_24[15]}}, _ll_ncountSumStill2Dist_T_24} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_26 = _ll_ncountSumStill2Dist_T_25[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_27 = _ll_ncountSumStill2Dist_T_26; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_6 = _ll_ncountSumStill2Dist_T_27; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_6_T = ll_normalizedCounterMaxIdx == 16'h6; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_6_T_1 = _ll_normalizedCounterMaxAdjusted_6_T ? ll_ncountSumStill2Dist_6 : {31'h0, ll_normalizedCounter_6}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_6 = _T_3 ? _ll_normalizedCounterMaxAdjusted_6_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_29 = {{32{_ll_ncountSumStill2Dist_T_28[15]}}, _ll_ncountSumStill2Dist_T_28} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_30 = _ll_ncountSumStill2Dist_T_29[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_31 = _ll_ncountSumStill2Dist_T_30; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_7 = _ll_ncountSumStill2Dist_T_31; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_7_T = ll_normalizedCounterMaxIdx == 16'h7; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_7_T_1 = _ll_normalizedCounterMaxAdjusted_7_T ? ll_ncountSumStill2Dist_7 : {31'h0, ll_normalizedCounter_7}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_7 = _T_3 ? _ll_normalizedCounterMaxAdjusted_7_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_33 = {{32{_ll_ncountSumStill2Dist_T_32[15]}}, _ll_ncountSumStill2Dist_T_32} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_34 = _ll_ncountSumStill2Dist_T_33[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_35 = _ll_ncountSumStill2Dist_T_34; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_8 = _ll_ncountSumStill2Dist_T_35; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_8_T = ll_normalizedCounterMaxIdx == 16'h8; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_8_T_1 = _ll_normalizedCounterMaxAdjusted_8_T ? ll_ncountSumStill2Dist_8 : {31'h0, ll_normalizedCounter_8}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_8 = _T_3 ? _ll_normalizedCounterMaxAdjusted_8_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_37 = {{32{_ll_ncountSumStill2Dist_T_36[15]}}, _ll_ncountSumStill2Dist_T_36} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_38 = _ll_ncountSumStill2Dist_T_37[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_39 = _ll_ncountSumStill2Dist_T_38; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_9 = _ll_ncountSumStill2Dist_T_39; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_9_T = ll_normalizedCounterMaxIdx == 16'h9; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_9_T_1 = _ll_normalizedCounterMaxAdjusted_9_T ? ll_ncountSumStill2Dist_9 : {31'h0, ll_normalizedCounter_9}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_9 = _T_3 ? _ll_normalizedCounterMaxAdjusted_9_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_41 = {{32{_ll_ncountSumStill2Dist_T_40[15]}}, _ll_ncountSumStill2Dist_T_40} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_42 = _ll_ncountSumStill2Dist_T_41[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_43 = _ll_ncountSumStill2Dist_T_42; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_10 = _ll_ncountSumStill2Dist_T_43; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_10_T = ll_normalizedCounterMaxIdx == 16'hA; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_10_T_1 = _ll_normalizedCounterMaxAdjusted_10_T ? ll_ncountSumStill2Dist_10 : {31'h0, ll_normalizedCounter_10}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_10 = _T_3 ? _ll_normalizedCounterMaxAdjusted_10_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_45 = {{32{_ll_ncountSumStill2Dist_T_44[15]}}, _ll_ncountSumStill2Dist_T_44} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_46 = _ll_ncountSumStill2Dist_T_45[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_47 = _ll_ncountSumStill2Dist_T_46; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_11 = _ll_ncountSumStill2Dist_T_47; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_11_T = ll_normalizedCounterMaxIdx == 16'hB; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_11_T_1 = _ll_normalizedCounterMaxAdjusted_11_T ? ll_ncountSumStill2Dist_11 : {31'h0, ll_normalizedCounter_11}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_11 = _T_3 ? _ll_normalizedCounterMaxAdjusted_11_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_49 = {{32{_ll_ncountSumStill2Dist_T_48[15]}}, _ll_ncountSumStill2Dist_T_48} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_50 = _ll_ncountSumStill2Dist_T_49[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_51 = _ll_ncountSumStill2Dist_T_50; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_12 = _ll_ncountSumStill2Dist_T_51; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_12_T = ll_normalizedCounterMaxIdx == 16'hC; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_12_T_1 = _ll_normalizedCounterMaxAdjusted_12_T ? ll_ncountSumStill2Dist_12 : {31'h0, ll_normalizedCounter_12}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_12 = _T_3 ? _ll_normalizedCounterMaxAdjusted_12_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_53 = {{32{_ll_ncountSumStill2Dist_T_52[15]}}, _ll_ncountSumStill2Dist_T_52} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_54 = _ll_ncountSumStill2Dist_T_53[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_55 = _ll_ncountSumStill2Dist_T_54; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_13 = _ll_ncountSumStill2Dist_T_55; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_13_T = ll_normalizedCounterMaxIdx == 16'hD; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_13_T_1 = _ll_normalizedCounterMaxAdjusted_13_T ? ll_ncountSumStill2Dist_13 : {31'h0, ll_normalizedCounter_13}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_13 = _T_3 ? _ll_normalizedCounterMaxAdjusted_13_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_57 = {{32{_ll_ncountSumStill2Dist_T_56[15]}}, _ll_ncountSumStill2Dist_T_56} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_58 = _ll_ncountSumStill2Dist_T_57[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_59 = _ll_ncountSumStill2Dist_T_58; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_14 = _ll_ncountSumStill2Dist_T_59; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_14_T = ll_normalizedCounterMaxIdx == 16'hE; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_14_T_1 = _ll_normalizedCounterMaxAdjusted_14_T ? ll_ncountSumStill2Dist_14 : {31'h0, ll_normalizedCounter_14}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_14 = _T_3 ? _ll_normalizedCounterMaxAdjusted_14_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_61 = {{32{_ll_ncountSumStill2Dist_T_60[15]}}, _ll_ncountSumStill2Dist_T_60} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_62 = _ll_ncountSumStill2Dist_T_61[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_63 = _ll_ncountSumStill2Dist_T_62; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_15 = _ll_ncountSumStill2Dist_T_63; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_15_T = ll_normalizedCounterMaxIdx == 16'hF; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_15_T_1 = _ll_normalizedCounterMaxAdjusted_15_T ? ll_ncountSumStill2Dist_15 : {31'h0, ll_normalizedCounter_15}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_15 = _T_3 ? _ll_normalizedCounterMaxAdjusted_15_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_65 = {{32{_ll_ncountSumStill2Dist_T_64[15]}}, _ll_ncountSumStill2Dist_T_64} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_66 = _ll_ncountSumStill2Dist_T_65[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_67 = _ll_ncountSumStill2Dist_T_66; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_16 = _ll_ncountSumStill2Dist_T_67; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_16_T = ll_normalizedCounterMaxIdx == 16'h10; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_16_T_1 = _ll_normalizedCounterMaxAdjusted_16_T ? ll_ncountSumStill2Dist_16 : {31'h0, ll_normalizedCounter_16}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_16 = _T_3 ? _ll_normalizedCounterMaxAdjusted_16_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_69 = {{32{_ll_ncountSumStill2Dist_T_68[15]}}, _ll_ncountSumStill2Dist_T_68} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_70 = _ll_ncountSumStill2Dist_T_69[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_71 = _ll_ncountSumStill2Dist_T_70; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_17 = _ll_ncountSumStill2Dist_T_71; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_17_T = ll_normalizedCounterMaxIdx == 16'h11; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_17_T_1 = _ll_normalizedCounterMaxAdjusted_17_T ? ll_ncountSumStill2Dist_17 : {31'h0, ll_normalizedCounter_17}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_17 = _T_3 ? _ll_normalizedCounterMaxAdjusted_17_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_73 = {{32{_ll_ncountSumStill2Dist_T_72[15]}}, _ll_ncountSumStill2Dist_T_72} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_74 = _ll_ncountSumStill2Dist_T_73[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_75 = _ll_ncountSumStill2Dist_T_74; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_18 = _ll_ncountSumStill2Dist_T_75; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_18_T = ll_normalizedCounterMaxIdx == 16'h12; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_18_T_1 = _ll_normalizedCounterMaxAdjusted_18_T ? ll_ncountSumStill2Dist_18 : {31'h0, ll_normalizedCounter_18}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_18 = _T_3 ? _ll_normalizedCounterMaxAdjusted_18_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_77 = {{32{_ll_ncountSumStill2Dist_T_76[15]}}, _ll_ncountSumStill2Dist_T_76} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_78 = _ll_ncountSumStill2Dist_T_77[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_79 = _ll_ncountSumStill2Dist_T_78; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_19 = _ll_ncountSumStill2Dist_T_79; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_19_T = ll_normalizedCounterMaxIdx == 16'h13; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_19_T_1 = _ll_normalizedCounterMaxAdjusted_19_T ? ll_ncountSumStill2Dist_19 : {31'h0, ll_normalizedCounter_19}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_19 = _T_3 ? _ll_normalizedCounterMaxAdjusted_19_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_81 = {{32{_ll_ncountSumStill2Dist_T_80[15]}}, _ll_ncountSumStill2Dist_T_80} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_82 = _ll_ncountSumStill2Dist_T_81[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_83 = _ll_ncountSumStill2Dist_T_82; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_20 = _ll_ncountSumStill2Dist_T_83; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_20_T = ll_normalizedCounterMaxIdx == 16'h14; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_20_T_1 = _ll_normalizedCounterMaxAdjusted_20_T ? ll_ncountSumStill2Dist_20 : {31'h0, ll_normalizedCounter_20}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_20 = _T_3 ? _ll_normalizedCounterMaxAdjusted_20_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_85 = {{32{_ll_ncountSumStill2Dist_T_84[15]}}, _ll_ncountSumStill2Dist_T_84} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_86 = _ll_ncountSumStill2Dist_T_85[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_87 = _ll_ncountSumStill2Dist_T_86; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_21 = _ll_ncountSumStill2Dist_T_87; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_21_T = ll_normalizedCounterMaxIdx == 16'h15; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_21_T_1 = _ll_normalizedCounterMaxAdjusted_21_T ? ll_ncountSumStill2Dist_21 : {31'h0, ll_normalizedCounter_21}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_21 = _T_3 ? _ll_normalizedCounterMaxAdjusted_21_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_89 = {{32{_ll_ncountSumStill2Dist_T_88[15]}}, _ll_ncountSumStill2Dist_T_88} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_90 = _ll_ncountSumStill2Dist_T_89[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_91 = _ll_ncountSumStill2Dist_T_90; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_22 = _ll_ncountSumStill2Dist_T_91; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_22_T = ll_normalizedCounterMaxIdx == 16'h16; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_22_T_1 = _ll_normalizedCounterMaxAdjusted_22_T ? ll_ncountSumStill2Dist_22 : {31'h0, ll_normalizedCounter_22}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_22 = _T_3 ? _ll_normalizedCounterMaxAdjusted_22_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_93 = {{32{_ll_ncountSumStill2Dist_T_92[15]}}, _ll_ncountSumStill2Dist_T_92} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_94 = _ll_ncountSumStill2Dist_T_93[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_95 = _ll_ncountSumStill2Dist_T_94; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_23 = _ll_ncountSumStill2Dist_T_95; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_23_T = ll_normalizedCounterMaxIdx == 16'h17; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_23_T_1 = _ll_normalizedCounterMaxAdjusted_23_T ? ll_ncountSumStill2Dist_23 : {31'h0, ll_normalizedCounter_23}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_23 = _T_3 ? _ll_normalizedCounterMaxAdjusted_23_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_97 = {{32{_ll_ncountSumStill2Dist_T_96[15]}}, _ll_ncountSumStill2Dist_T_96} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_98 = _ll_ncountSumStill2Dist_T_97[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_99 = _ll_ncountSumStill2Dist_T_98; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_24 = _ll_ncountSumStill2Dist_T_99; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_24_T = ll_normalizedCounterMaxIdx == 16'h18; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_24_T_1 = _ll_normalizedCounterMaxAdjusted_24_T ? ll_ncountSumStill2Dist_24 : {31'h0, ll_normalizedCounter_24}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_24 = _T_3 ? _ll_normalizedCounterMaxAdjusted_24_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_101 = {{32{_ll_ncountSumStill2Dist_T_100[15]}}, _ll_ncountSumStill2Dist_T_100} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_102 = _ll_ncountSumStill2Dist_T_101[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_103 = _ll_ncountSumStill2Dist_T_102; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_25 = _ll_ncountSumStill2Dist_T_103; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_25_T = ll_normalizedCounterMaxIdx == 16'h19; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_25_T_1 = _ll_normalizedCounterMaxAdjusted_25_T ? ll_ncountSumStill2Dist_25 : {31'h0, ll_normalizedCounter_25}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_25 = _T_3 ? _ll_normalizedCounterMaxAdjusted_25_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_105 = {{32{_ll_ncountSumStill2Dist_T_104[15]}}, _ll_ncountSumStill2Dist_T_104} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_106 = _ll_ncountSumStill2Dist_T_105[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_107 = _ll_ncountSumStill2Dist_T_106; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_26 = _ll_ncountSumStill2Dist_T_107; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_26_T = ll_normalizedCounterMaxIdx == 16'h1A; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_26_T_1 = _ll_normalizedCounterMaxAdjusted_26_T ? ll_ncountSumStill2Dist_26 : {31'h0, ll_normalizedCounter_26}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_26 = _T_3 ? _ll_normalizedCounterMaxAdjusted_26_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_109 = {{32{_ll_ncountSumStill2Dist_T_108[15]}}, _ll_ncountSumStill2Dist_T_108} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_110 = _ll_ncountSumStill2Dist_T_109[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_111 = _ll_ncountSumStill2Dist_T_110; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_27 = _ll_ncountSumStill2Dist_T_111; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_27_T = ll_normalizedCounterMaxIdx == 16'h1B; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_27_T_1 = _ll_normalizedCounterMaxAdjusted_27_T ? ll_ncountSumStill2Dist_27 : {31'h0, ll_normalizedCounter_27}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_27 = _T_3 ? _ll_normalizedCounterMaxAdjusted_27_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_113 = {{32{_ll_ncountSumStill2Dist_T_112[15]}}, _ll_ncountSumStill2Dist_T_112} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_114 = _ll_ncountSumStill2Dist_T_113[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_115 = _ll_ncountSumStill2Dist_T_114; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_28 = _ll_ncountSumStill2Dist_T_115; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_28_T = ll_normalizedCounterMaxIdx == 16'h1C; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_28_T_1 = _ll_normalizedCounterMaxAdjusted_28_T ? ll_ncountSumStill2Dist_28 : {31'h0, ll_normalizedCounter_28}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_28 = _T_3 ? _ll_normalizedCounterMaxAdjusted_28_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_117 = {{32{_ll_ncountSumStill2Dist_T_116[15]}}, _ll_ncountSumStill2Dist_T_116} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_118 = _ll_ncountSumStill2Dist_T_117[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_119 = _ll_ncountSumStill2Dist_T_118; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_29 = _ll_ncountSumStill2Dist_T_119; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_29_T = ll_normalizedCounterMaxIdx == 16'h1D; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_29_T_1 = _ll_normalizedCounterMaxAdjusted_29_T ? ll_ncountSumStill2Dist_29 : {31'h0, ll_normalizedCounter_29}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_29 = _T_3 ? _ll_normalizedCounterMaxAdjusted_29_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_121 = {{32{_ll_ncountSumStill2Dist_T_120[15]}}, _ll_ncountSumStill2Dist_T_120} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_122 = _ll_ncountSumStill2Dist_T_121[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_123 = _ll_ncountSumStill2Dist_T_122; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_30 = _ll_ncountSumStill2Dist_T_123; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_30_T = ll_normalizedCounterMaxIdx == 16'h1E; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_30_T_1 = _ll_normalizedCounterMaxAdjusted_30_T ? ll_ncountSumStill2Dist_30 : {31'h0, ll_normalizedCounter_30}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_30 = _T_3 ? _ll_normalizedCounterMaxAdjusted_30_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [47:0] _ll_ncountSumStill2Dist_T_125 = {{32{_ll_ncountSumStill2Dist_T_124[15]}}, _ll_ncountSumStill2Dist_T_124} + _GEN_196; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [46:0] _ll_ncountSumStill2Dist_T_126 = _ll_ncountSumStill2Dist_T_125[46:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] _ll_ncountSumStill2Dist_T_127 = _ll_ncountSumStill2Dist_T_126; // @[FSECompressorDicBuilder.scala:320:68] wire [46:0] ll_ncountSumStill2Dist_31 = _ll_ncountSumStill2Dist_T_127; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_31_T = ll_normalizedCounterMaxIdx == 16'h1F; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [46:0] _ll_normalizedCounterMaxAdjusted_31_T_1 = _ll_normalizedCounterMaxAdjusted_31_T ? ll_ncountSumStill2Dist_31 : {31'h0, ll_normalizedCounter_31}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_31 = _T_3 ? _ll_normalizedCounterMaxAdjusted_31_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [15:0] ll_normalizedCounterReg_0; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_1; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_2; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_3; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_4; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_5; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_6; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_7; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_8; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_9; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_10; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_11; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_12; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_13; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_14; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_15; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_16; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_17; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_18; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_19; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_20; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_21; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_22; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_23; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_24; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_25; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_26; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_27; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_28; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_29; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_30; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_31; // @[FSECompressorDicBuilder.scala:337:40] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_43; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_86 = {1'h0, loginfo_cycles_43} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_87 = _loginfo_cycles_T_86[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_44; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_88 = {1'h0, loginfo_cycles_44} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_89 = _loginfo_cycles_T_88[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_45; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_90 = {1'h0, loginfo_cycles_45} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_91 = _loginfo_cycles_T_90[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_46; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_92 = {1'h0, loginfo_cycles_46} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_93 = _loginfo_cycles_T_92[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_47; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_94 = {1'h0, loginfo_cycles_47} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_95 = _loginfo_cycles_T_94[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_48; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_96 = {1'h0, loginfo_cycles_48} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_97 = _loginfo_cycles_T_96[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_49; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_98 = {1'h0, loginfo_cycles_49} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_99 = _loginfo_cycles_T_98[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_50; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_100 = {1'h0, loginfo_cycles_50} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_101 = _loginfo_cycles_T_100[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_51; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_102 = {1'h0, loginfo_cycles_51} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_103 = _loginfo_cycles_T_102[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_52; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_104 = {1'h0, loginfo_cycles_52} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_105 = _loginfo_cycles_T_104[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_53; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_106 = {1'h0, loginfo_cycles_53} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_107 = _loginfo_cycles_T_106[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_54; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_108 = {1'h0, loginfo_cycles_54} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_109 = _loginfo_cycles_T_108[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_55; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_110 = {1'h0, loginfo_cycles_55} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_111 = _loginfo_cycles_T_110[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_56; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_112 = {1'h0, loginfo_cycles_56} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_113 = _loginfo_cycles_T_112[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_57; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_114 = {1'h0, loginfo_cycles_57} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_115 = _loginfo_cycles_T_114[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_58; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_116 = {1'h0, loginfo_cycles_58} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_117 = _loginfo_cycles_T_116[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_59; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_118 = {1'h0, loginfo_cycles_59} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_119 = _loginfo_cycles_T_118[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_60; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_120 = {1'h0, loginfo_cycles_60} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_121 = _loginfo_cycles_T_120[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_61; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_122 = {1'h0, loginfo_cycles_61} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_123 = _loginfo_cycles_T_122[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_62; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_124 = {1'h0, loginfo_cycles_62} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_125 = _loginfo_cycles_T_124[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_63; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_126 = {1'h0, loginfo_cycles_63} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_127 = _loginfo_cycles_T_126[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_64; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_128 = {1'h0, loginfo_cycles_64} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_129 = _loginfo_cycles_T_128[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_65; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_130 = {1'h0, loginfo_cycles_65} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_131 = _loginfo_cycles_T_130[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_66; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_132 = {1'h0, loginfo_cycles_66} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_133 = _loginfo_cycles_T_132[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_67; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_134 = {1'h0, loginfo_cycles_67} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_135 = _loginfo_cycles_T_134[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_68; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_136 = {1'h0, loginfo_cycles_68} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_137 = _loginfo_cycles_T_136[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_69; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_138 = {1'h0, loginfo_cycles_69} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_139 = _loginfo_cycles_T_138[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_70; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_140 = {1'h0, loginfo_cycles_70} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_141 = _loginfo_cycles_T_140[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_71; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_142 = {1'h0, loginfo_cycles_71} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_143 = _loginfo_cycles_T_142[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_72; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_144 = {1'h0, loginfo_cycles_72} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_145 = _loginfo_cycles_T_144[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_73; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_146 = {1'h0, loginfo_cycles_73} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_147 = _loginfo_cycles_T_146[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_74; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_148 = {1'h0, loginfo_cycles_74} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_149 = _loginfo_cycles_T_148[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_75; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_150 = {1'h0, loginfo_cycles_75} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_151 = _loginfo_cycles_T_150[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_76; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_152 = {1'h0, loginfo_cycles_76} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_153 = _loginfo_cycles_T_152[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_77; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_154 = {1'h0, loginfo_cycles_77} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_155 = _loginfo_cycles_T_154[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_78; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_156 = {1'h0, loginfo_cycles_78} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_157 = _loginfo_cycles_T_156[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_79; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_158 = {1'h0, loginfo_cycles_79} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_159 = _loginfo_cycles_T_158[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_80; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_160 = {1'h0, loginfo_cycles_80} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_161 = _loginfo_cycles_T_160[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_81; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_162 = {1'h0, loginfo_cycles_81} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_163 = _loginfo_cycles_T_162[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_82; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_164 = {1'h0, loginfo_cycles_82} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_165 = _loginfo_cycles_T_164[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_83; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_166 = {1'h0, loginfo_cycles_83} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_167 = _loginfo_cycles_T_166[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_84; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_168 = {1'h0, loginfo_cycles_84} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_169 = _loginfo_cycles_T_168[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_85; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_170 = {1'h0, loginfo_cycles_85} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_171 = _loginfo_cycles_T_170[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_86; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_172 = {1'h0, loginfo_cycles_86} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_173 = _loginfo_cycles_T_172[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_87; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_174 = {1'h0, loginfo_cycles_87} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_175 = _loginfo_cycles_T_174[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_88; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_176 = {1'h0, loginfo_cycles_88} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_177 = _loginfo_cycles_T_176[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_89; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_178 = {1'h0, loginfo_cycles_89} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_179 = _loginfo_cycles_T_178[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_90; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_180 = {1'h0, loginfo_cycles_90} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_181 = _loginfo_cycles_T_180[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_91; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_182 = {1'h0, loginfo_cycles_91} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_183 = _loginfo_cycles_T_182[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_92; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_184 = {1'h0, loginfo_cycles_92} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_185 = _loginfo_cycles_T_184[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_93; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_186 = {1'h0, loginfo_cycles_93} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_187 = _loginfo_cycles_T_186[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_94; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_188 = {1'h0, loginfo_cycles_94} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_189 = _loginfo_cycles_T_188[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_95; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_190 = {1'h0, loginfo_cycles_95} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_191 = _loginfo_cycles_T_190[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_96; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_192 = {1'h0, loginfo_cycles_96} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_193 = _loginfo_cycles_T_192[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_97; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_194 = {1'h0, loginfo_cycles_97} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_195 = _loginfo_cycles_T_194[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_98; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_196 = {1'h0, loginfo_cycles_98} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_197 = _loginfo_cycles_T_196[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_99; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_198 = {1'h0, loginfo_cycles_99} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_199 = _loginfo_cycles_T_198[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_100; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_200 = {1'h0, loginfo_cycles_100} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_201 = _loginfo_cycles_T_200[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_101; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_202 = {1'h0, loginfo_cycles_101} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_203 = _loginfo_cycles_T_202[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_102; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_204 = {1'h0, loginfo_cycles_102} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_205 = _loginfo_cycles_T_204[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_103; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_206 = {1'h0, loginfo_cycles_103} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_207 = _loginfo_cycles_T_206[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_104; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_208 = {1'h0, loginfo_cycles_104} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_209 = _loginfo_cycles_T_208[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_105; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_210 = {1'h0, loginfo_cycles_105} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_211 = _loginfo_cycles_T_210[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_106; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_212 = {1'h0, loginfo_cycles_106} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_213 = _loginfo_cycles_T_212[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_107; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_214 = {1'h0, loginfo_cycles_107} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_215 = _loginfo_cycles_T_214[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_108; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_216 = {1'h0, loginfo_cycles_108} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_217 = _loginfo_cycles_T_216[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_109; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_218 = {1'h0, loginfo_cycles_109} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_219 = _loginfo_cycles_T_218[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_110; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_220 = {1'h0, loginfo_cycles_110} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_221 = _loginfo_cycles_T_220[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_111; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_222 = {1'h0, loginfo_cycles_111} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_223 = _loginfo_cycles_T_222[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_112; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_224 = {1'h0, loginfo_cycles_112} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_225 = _loginfo_cycles_T_224[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_113; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_226 = {1'h0, loginfo_cycles_113} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_227 = _loginfo_cycles_T_226[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_114; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_228 = {1'h0, loginfo_cycles_114} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_229 = _loginfo_cycles_T_228[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_115; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_230 = {1'h0, loginfo_cycles_115} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_231 = _loginfo_cycles_T_230[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_116; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_232 = {1'h0, loginfo_cycles_116} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_233 = _loginfo_cycles_T_232[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_117; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_234 = {1'h0, loginfo_cycles_117} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_235 = _loginfo_cycles_T_234[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_118; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_236 = {1'h0, loginfo_cycles_118} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_237 = _loginfo_cycles_T_236[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_119; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_238 = {1'h0, loginfo_cycles_119} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_239 = _loginfo_cycles_T_238[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_120; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_240 = {1'h0, loginfo_cycles_120} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_241 = _loginfo_cycles_T_240[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_121; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_242 = {1'h0, loginfo_cycles_121} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_243 = _loginfo_cycles_T_242[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_122; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_244 = {1'h0, loginfo_cycles_122} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_245 = _loginfo_cycles_T_244[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_123; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_246 = {1'h0, loginfo_cycles_123} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_247 = _loginfo_cycles_T_246[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_124; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_248 = {1'h0, loginfo_cycles_124} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_249 = _loginfo_cycles_T_248[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_125; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_250 = {1'h0, loginfo_cycles_125} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_251 = _loginfo_cycles_T_250[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_126; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_252 = {1'h0, loginfo_cycles_126} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_253 = _loginfo_cycles_T_252[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_127; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_254 = {1'h0, loginfo_cycles_127} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_255 = _loginfo_cycles_T_254[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_128; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_256 = {1'h0, loginfo_cycles_128} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_257 = _loginfo_cycles_T_256[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_129; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_258 = {1'h0, loginfo_cycles_129} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_259 = _loginfo_cycles_T_258[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_130; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_260 = {1'h0, loginfo_cycles_130} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_261 = _loginfo_cycles_T_260[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_131; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_262 = {1'h0, loginfo_cycles_131} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_263 = _loginfo_cycles_T_262[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_132; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_264 = {1'h0, loginfo_cycles_132} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_265 = _loginfo_cycles_T_264[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_133; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_266 = {1'h0, loginfo_cycles_133} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_267 = _loginfo_cycles_T_266[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_134; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_268 = {1'h0, loginfo_cycles_134} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_269 = _loginfo_cycles_T_268[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_135; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_270 = {1'h0, loginfo_cycles_135} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_271 = _loginfo_cycles_T_270[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_136; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_272 = {1'h0, loginfo_cycles_136} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_273 = _loginfo_cycles_T_272[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_137; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_274 = {1'h0, loginfo_cycles_137} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_275 = _loginfo_cycles_T_274[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_138; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_276 = {1'h0, loginfo_cycles_138} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_277 = _loginfo_cycles_T_276[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_139; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_278 = {1'h0, loginfo_cycles_139} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_279 = _loginfo_cycles_T_278[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_140; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_280 = {1'h0, loginfo_cycles_140} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_281 = _loginfo_cycles_T_280[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_141; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_282 = {1'h0, loginfo_cycles_141} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_283 = _loginfo_cycles_T_282[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_142; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_284 = {1'h0, loginfo_cycles_142} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_285 = _loginfo_cycles_T_284[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_143; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_286 = {1'h0, loginfo_cycles_143} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_287 = _loginfo_cycles_T_286[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_144; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_288 = {1'h0, loginfo_cycles_144} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_289 = _loginfo_cycles_T_288[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_145; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_290 = {1'h0, loginfo_cycles_145} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_291 = _loginfo_cycles_T_290[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_146; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_292 = {1'h0, loginfo_cycles_146} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_293 = _loginfo_cycles_T_292[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_147; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_294 = {1'h0, loginfo_cycles_147} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_295 = _loginfo_cycles_T_294[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_148; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_296 = {1'h0, loginfo_cycles_148} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_297 = _loginfo_cycles_T_296[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_149; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_298 = {1'h0, loginfo_cycles_149} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_299 = _loginfo_cycles_T_298[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_150; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_300 = {1'h0, loginfo_cycles_150} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_301 = _loginfo_cycles_T_300[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_151; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_302 = {1'h0, loginfo_cycles_151} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_303 = _loginfo_cycles_T_302[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_152; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_304 = {1'h0, loginfo_cycles_152} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_305 = _loginfo_cycles_T_304[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_153; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_306 = {1'h0, loginfo_cycles_153} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_307 = _loginfo_cycles_T_306[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_154; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_308 = {1'h0, loginfo_cycles_154} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_309 = _loginfo_cycles_T_308[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_155; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_310 = {1'h0, loginfo_cycles_155} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_311 = _loginfo_cycles_T_310[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_156; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_312 = {1'h0, loginfo_cycles_156} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_313 = _loginfo_cycles_T_312[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_157; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_314 = {1'h0, loginfo_cycles_157} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_315 = _loginfo_cycles_T_314[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_158; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_316 = {1'h0, loginfo_cycles_158} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_317 = _loginfo_cycles_T_316[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_159; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_318 = {1'h0, loginfo_cycles_159} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_319 = _loginfo_cycles_T_318[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_160; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_320 = {1'h0, loginfo_cycles_160} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_321 = _loginfo_cycles_T_320[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_161; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_322 = {1'h0, loginfo_cycles_161} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_323 = _loginfo_cycles_T_322[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_162; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_324 = {1'h0, loginfo_cycles_162} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_325 = _loginfo_cycles_T_324[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_163; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_326 = {1'h0, loginfo_cycles_163} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_327 = _loginfo_cycles_T_326[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_164; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_328 = {1'h0, loginfo_cycles_164} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_329 = _loginfo_cycles_T_328[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_165; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_330 = {1'h0, loginfo_cycles_165} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_331 = _loginfo_cycles_T_330[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_166; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_332 = {1'h0, loginfo_cycles_166} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_333 = _loginfo_cycles_T_332[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_167; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_334 = {1'h0, loginfo_cycles_167} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_335 = _loginfo_cycles_T_334[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_168; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_336 = {1'h0, loginfo_cycles_168} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_337 = _loginfo_cycles_T_336[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_169; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_338 = {1'h0, loginfo_cycles_169} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_339 = _loginfo_cycles_T_338[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_170; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_340 = {1'h0, loginfo_cycles_170} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_341 = _loginfo_cycles_T_340[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_171; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_342 = {1'h0, loginfo_cycles_171} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_343 = _loginfo_cycles_T_342[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_172; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_344 = {1'h0, loginfo_cycles_172} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_345 = _loginfo_cycles_T_344[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_173; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_346 = {1'h0, loginfo_cycles_173} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_347 = _loginfo_cycles_T_346[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_174; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_348 = {1'h0, loginfo_cycles_174} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_349 = _loginfo_cycles_T_348[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_175; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_350 = {1'h0, loginfo_cycles_175} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_351 = _loginfo_cycles_T_350[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_176; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_352 = {1'h0, loginfo_cycles_176} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_353 = _loginfo_cycles_T_352[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_177; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_354 = {1'h0, loginfo_cycles_177} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_355 = _loginfo_cycles_T_354[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_178; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_356 = {1'h0, loginfo_cycles_178} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_357 = _loginfo_cycles_T_356[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_179; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_358 = {1'h0, loginfo_cycles_179} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_359 = _loginfo_cycles_T_358[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_180; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_360 = {1'h0, loginfo_cycles_180} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_361 = _loginfo_cycles_T_360[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_181; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_362 = {1'h0, loginfo_cycles_181} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_363 = _loginfo_cycles_T_362[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_182; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_364 = {1'h0, loginfo_cycles_182} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_365 = _loginfo_cycles_T_364[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_183; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_366 = {1'h0, loginfo_cycles_183} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_367 = _loginfo_cycles_T_366[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_184; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_368 = {1'h0, loginfo_cycles_184} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_369 = _loginfo_cycles_T_368[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_185; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_370 = {1'h0, loginfo_cycles_185} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_371 = _loginfo_cycles_T_370[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_186; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_372 = {1'h0, loginfo_cycles_186} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_373 = _loginfo_cycles_T_372[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_187; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_374 = {1'h0, loginfo_cycles_187} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_375 = _loginfo_cycles_T_374[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_188; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_376 = {1'h0, loginfo_cycles_188} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_377 = _loginfo_cycles_T_376[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_189; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_378 = {1'h0, loginfo_cycles_189} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_379 = _loginfo_cycles_T_378[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_190; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_380 = {1'h0, loginfo_cycles_190} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_381 = _loginfo_cycles_T_380[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_191; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_382 = {1'h0, loginfo_cycles_191} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_383 = _loginfo_cycles_T_382[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_192; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_384 = {1'h0, loginfo_cycles_192} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_385 = _loginfo_cycles_T_384[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_193; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_386 = {1'h0, loginfo_cycles_193} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_387 = _loginfo_cycles_T_386[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_194; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_388 = {1'h0, loginfo_cycles_194} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_389 = _loginfo_cycles_T_388[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_195; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_390 = {1'h0, loginfo_cycles_195} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_391 = _loginfo_cycles_T_390[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_196; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_392 = {1'h0, loginfo_cycles_196} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_393 = _loginfo_cycles_T_392[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_197; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_394 = {1'h0, loginfo_cycles_197} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_395 = _loginfo_cycles_T_394[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_198; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_396 = {1'h0, loginfo_cycles_198} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_397 = _loginfo_cycles_T_396[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_199; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_398 = {1'h0, loginfo_cycles_199} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_399 = _loginfo_cycles_T_398[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_200; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_400 = {1'h0, loginfo_cycles_200} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_401 = _loginfo_cycles_T_400[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_201; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_402 = {1'h0, loginfo_cycles_201} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_403 = _loginfo_cycles_T_402[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_202; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_404 = {1'h0, loginfo_cycles_202} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_405 = _loginfo_cycles_T_404[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_203; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_406 = {1'h0, loginfo_cycles_203} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_407 = _loginfo_cycles_T_406[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_204; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_408 = {1'h0, loginfo_cycles_204} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_409 = _loginfo_cycles_T_408[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_205; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_410 = {1'h0, loginfo_cycles_205} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_411 = _loginfo_cycles_T_410[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_206; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_412 = {1'h0, loginfo_cycles_206} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_413 = _loginfo_cycles_T_412[63:0]; // @[Util.scala:19:38] wire [32:0] _GEN_197 = {1'h0, ll_max_symbol_value} + 33'h1; // @[FSECompressorDicBuilder.scala:170:36, :379:39] wire [32:0] _ll_maxSV1_T; // @[FSECompressorDicBuilder.scala:379:39] assign _ll_maxSV1_T = _GEN_197; // @[FSECompressorDicBuilder.scala:379:39] wire [32:0] _alphabetSize_T; // @[FSECompressorDicBuilder.scala:466:42] assign _alphabetSize_T = _GEN_197; // @[FSECompressorDicBuilder.scala:379:39, :466:42] wire [31:0] ll_maxSV1 = _ll_maxSV1_T[31:0]; // @[FSECompressorDicBuilder.scala:379:39] wire [15:0] ll_cumul_0; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_1; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_2; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_3; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_4; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_5; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_6; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_7; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_8; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_9; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_10; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_11; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_12; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_13; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_14; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_15; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_16; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_17; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_18; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_19; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_20; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_21; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_22; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_23; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_24; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_25; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_26; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_27; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_28; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_29; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_30; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_31; // @[FSECompressorDicBuilder.scala:382:26] reg [7:0] ll_tableSymbol_0; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_1; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_2; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_3; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_4; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_5; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_6; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_7; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_8; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_9; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_10; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_11; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_12; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_13; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_14; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_15; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_16; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_17; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_18; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_19; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_20; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_21; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_22; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_23; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_24; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_25; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_26; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_27; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_28; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_29; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_30; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_31; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_32; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_33; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_34; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_35; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_36; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_37; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_38; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_39; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_40; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_41; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_42; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_43; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_44; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_45; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_46; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_47; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_48; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_49; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_50; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_51; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_52; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_53; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_54; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_55; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_56; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_57; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_58; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_59; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_60; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_61; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_62; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_63; // @[FSECompressorDicBuilder.scala:383:31] wire [7:0] ll_normCountEqsNegOne_0; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_1; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_2; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_3; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_4; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_5; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_6; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_7; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_8; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_9; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_10; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_11; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_12; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_13; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_14; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_15; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_16; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_17; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_18; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_19; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_20; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_21; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_22; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_23; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_24; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_25; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_26; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_27; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_28; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_29; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_30; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOneCumul_0; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_1; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_2; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_3; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_4; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_5; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_6; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_7; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_8; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_9; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_10; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_11; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_12; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_13; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_14; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_15; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_16; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_17; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_18; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_19; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_20; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_21; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_22; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_23; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_24; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_25; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_26; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_27; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_28; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_29; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_30; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_31; // @[FSECompressorDicBuilder.scala:389:44] wire [8:0] _GEN_198 = {1'h0, ll_normCountEqsNegOne_1}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [8:0] _ll_normCountEqsNegOneSum_T = {1'h0, ll_normCountEqsNegOne_0} + _GEN_198; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [9:0] _ll_normCountEqsNegOneSum_T_1 = {1'h0, _ll_normCountEqsNegOneSum_T} + {2'h0, ll_normCountEqsNegOne_2}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [10:0] _ll_normCountEqsNegOneSum_T_2 = {1'h0, _ll_normCountEqsNegOneSum_T_1} + {3'h0, ll_normCountEqsNegOne_3}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [11:0] _ll_normCountEqsNegOneSum_T_3 = {1'h0, _ll_normCountEqsNegOneSum_T_2} + {4'h0, ll_normCountEqsNegOne_4}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [12:0] _ll_normCountEqsNegOneSum_T_4 = {1'h0, _ll_normCountEqsNegOneSum_T_3} + {5'h0, ll_normCountEqsNegOne_5}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [13:0] _ll_normCountEqsNegOneSum_T_5 = {1'h0, _ll_normCountEqsNegOneSum_T_4} + {6'h0, ll_normCountEqsNegOne_6}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [14:0] _ll_normCountEqsNegOneSum_T_6 = {1'h0, _ll_normCountEqsNegOneSum_T_5} + {7'h0, ll_normCountEqsNegOne_7}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [15:0] _ll_normCountEqsNegOneSum_T_7 = {1'h0, _ll_normCountEqsNegOneSum_T_6} + {8'h0, ll_normCountEqsNegOne_8}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [16:0] _ll_normCountEqsNegOneSum_T_8 = {1'h0, _ll_normCountEqsNegOneSum_T_7} + {9'h0, ll_normCountEqsNegOne_9}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [17:0] _ll_normCountEqsNegOneSum_T_9 = {1'h0, _ll_normCountEqsNegOneSum_T_8} + {10'h0, ll_normCountEqsNegOne_10}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [18:0] _ll_normCountEqsNegOneSum_T_10 = {1'h0, _ll_normCountEqsNegOneSum_T_9} + {11'h0, ll_normCountEqsNegOne_11}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [19:0] _ll_normCountEqsNegOneSum_T_11 = {1'h0, _ll_normCountEqsNegOneSum_T_10} + {12'h0, ll_normCountEqsNegOne_12}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [20:0] _ll_normCountEqsNegOneSum_T_12 = {1'h0, _ll_normCountEqsNegOneSum_T_11} + {13'h0, ll_normCountEqsNegOne_13}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [21:0] _ll_normCountEqsNegOneSum_T_13 = {1'h0, _ll_normCountEqsNegOneSum_T_12} + {14'h0, ll_normCountEqsNegOne_14}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [22:0] _ll_normCountEqsNegOneSum_T_14 = {1'h0, _ll_normCountEqsNegOneSum_T_13} + {15'h0, ll_normCountEqsNegOne_15}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [23:0] _ll_normCountEqsNegOneSum_T_15 = {1'h0, _ll_normCountEqsNegOneSum_T_14} + {16'h0, ll_normCountEqsNegOne_16}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [24:0] _ll_normCountEqsNegOneSum_T_16 = {1'h0, _ll_normCountEqsNegOneSum_T_15} + {17'h0, ll_normCountEqsNegOne_17}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [25:0] _ll_normCountEqsNegOneSum_T_17 = {1'h0, _ll_normCountEqsNegOneSum_T_16} + {18'h0, ll_normCountEqsNegOne_18}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [26:0] _ll_normCountEqsNegOneSum_T_18 = {1'h0, _ll_normCountEqsNegOneSum_T_17} + {19'h0, ll_normCountEqsNegOne_19}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [27:0] _ll_normCountEqsNegOneSum_T_19 = {1'h0, _ll_normCountEqsNegOneSum_T_18} + {20'h0, ll_normCountEqsNegOne_20}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [28:0] _ll_normCountEqsNegOneSum_T_20 = {1'h0, _ll_normCountEqsNegOneSum_T_19} + {21'h0, ll_normCountEqsNegOne_21}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [29:0] _ll_normCountEqsNegOneSum_T_21 = {1'h0, _ll_normCountEqsNegOneSum_T_20} + {22'h0, ll_normCountEqsNegOne_22}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [30:0] _ll_normCountEqsNegOneSum_T_22 = {1'h0, _ll_normCountEqsNegOneSum_T_21} + {23'h0, ll_normCountEqsNegOne_23}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [31:0] _ll_normCountEqsNegOneSum_T_23 = {1'h0, _ll_normCountEqsNegOneSum_T_22} + {24'h0, ll_normCountEqsNegOne_24}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [32:0] _ll_normCountEqsNegOneSum_T_24 = {1'h0, _ll_normCountEqsNegOneSum_T_23} + {25'h0, ll_normCountEqsNegOne_25}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [33:0] _ll_normCountEqsNegOneSum_T_25 = {1'h0, _ll_normCountEqsNegOneSum_T_24} + {26'h0, ll_normCountEqsNegOne_26}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [34:0] _ll_normCountEqsNegOneSum_T_26 = {1'h0, _ll_normCountEqsNegOneSum_T_25} + {27'h0, ll_normCountEqsNegOne_27}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [35:0] _ll_normCountEqsNegOneSum_T_27 = {1'h0, _ll_normCountEqsNegOneSum_T_26} + {28'h0, ll_normCountEqsNegOne_28}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [36:0] _ll_normCountEqsNegOneSum_T_28 = {1'h0, _ll_normCountEqsNegOneSum_T_27} + {29'h0, ll_normCountEqsNegOne_29}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [37:0] _ll_normCountEqsNegOneSum_T_29 = {1'h0, _ll_normCountEqsNegOneSum_T_28} + {30'h0, ll_normCountEqsNegOne_30}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [38:0] ll_normCountEqsNegOneSum = {1'h0, _ll_normCountEqsNegOneSum_T_29}; // @[FSECompressorDicBuilder.scala:390:65] reg [31:0] ll_highThresholdAfterCumul; // @[FSECompressorDicBuilder.scala:392:43] reg [15:0] ll_cumulReg_0; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_1; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_2; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_3; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_4; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_5; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_6; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_7; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_8; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_9; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_10; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_11; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_12; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_13; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_14; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_15; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_16; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_17; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_18; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_19; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_20; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_21; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_22; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_23; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_24; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_25; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_26; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_27; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_28; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_29; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_30; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_31; // @[FSECompressorDicBuilder.scala:394:28] reg [7:0] ll_spread_0; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_1; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_2; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_3; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_4; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_5; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_6; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_7; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_8; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_9; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_10; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_11; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_12; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_13; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_14; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_15; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_16; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_17; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_18; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_19; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_20; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_21; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_22; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_23; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_24; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_25; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_26; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_27; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_28; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_29; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_30; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_31; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_32; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_33; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_34; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_35; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_36; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_37; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_38; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_39; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_40; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_41; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_42; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_43; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_44; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_45; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_46; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_47; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_48; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_49; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_50; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_51; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_52; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_53; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_54; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_55; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_56; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_57; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_58; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_59; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_60; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_61; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_62; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_63; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_64; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_65; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_66; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_67; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_68; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_69; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_70; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_71; // @[FSECompressorDicBuilder.scala:400:26] reg [63:0] ll_pos; // @[FSECompressorDicBuilder.scala:402:23] reg [63:0] ll_s; // @[FSECompressorDicBuilder.scala:403:21] reg [63:0] ll_sv; // @[FSECompressorDicBuilder.scala:404:22] reg [15:0] ll_tableU16_0; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_1; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_2; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_3; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_4; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_5; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_6; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_7; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_8; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_9; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_10; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_11; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_12; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_13; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_14; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_15; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_16; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_17; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_18; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_19; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_20; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_21; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_22; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_23; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_24; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_25; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_26; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_27; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_28; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_29; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_30; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_31; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_32; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_33; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_34; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_35; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_36; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_37; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_38; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_39; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_40; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_41; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_42; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_43; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_44; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_45; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_46; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_47; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_48; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_49; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_50; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_51; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_52; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_53; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_54; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_55; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_56; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_57; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_58; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_59; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_60; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_61; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_62; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_63; // @[FSECompressorDicBuilder.scala:411:28] reg [31:0] ll_symbolTTDeltaNbBits_0; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_1; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_2; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_3; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_4; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_5; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_6; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_7; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_8; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_9; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_10; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_11; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_12; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_13; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_14; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_15; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_16; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_17; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_18; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_19; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_20; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_21; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_22; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_23; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_24; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_25; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_26; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_27; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_28; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_29; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_30; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_31; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaFindState_0; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_1; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_2; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_3; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_4; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_5; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_6; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_7; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_8; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_9; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_10; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_11; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_12; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_13; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_14; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_15; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_16; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_17; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_18; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_19; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_20; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_21; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_22; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_23; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_24; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_25; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_26; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_27; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_28; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_29; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_30; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_31; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_total; // @[FSECompressorDicBuilder.scala:414:25] wire [31:0] normCount; // @[FSECompressorDicBuilder.scala:415:23] wire [4:0] _normCount_T = ll_s[4:0]; // @[FSECompressorDicBuilder.scala:403:21] wire [4:0] _n_T = ll_s[4:0]; // @[FSECompressorDicBuilder.scala:403:21] wire [31:0][15:0] _GEN_199 = {{ll_normalizedCounterReg_31}, {ll_normalizedCounterReg_30}, {ll_normalizedCounterReg_29}, {ll_normalizedCounterReg_28}, {ll_normalizedCounterReg_27}, {ll_normalizedCounterReg_26}, {ll_normalizedCounterReg_25}, {ll_normalizedCounterReg_24}, {ll_normalizedCounterReg_23}, {ll_normalizedCounterReg_22}, {ll_normalizedCounterReg_21}, {ll_normalizedCounterReg_20}, {ll_normalizedCounterReg_19}, {ll_normalizedCounterReg_18}, {ll_normalizedCounterReg_17}, {ll_normalizedCounterReg_16}, {ll_normalizedCounterReg_15}, {ll_normalizedCounterReg_14}, {ll_normalizedCounterReg_13}, {ll_normalizedCounterReg_12}, {ll_normalizedCounterReg_11}, {ll_normalizedCounterReg_10}, {ll_normalizedCounterReg_9}, {ll_normalizedCounterReg_8}, {ll_normalizedCounterReg_7}, {ll_normalizedCounterReg_6}, {ll_normalizedCounterReg_5}, {ll_normalizedCounterReg_4}, {ll_normalizedCounterReg_3}, {ll_normalizedCounterReg_2}, {ll_normalizedCounterReg_1}, {ll_normalizedCounterReg_0}}; // @[FSECompressorDicBuilder.scala:337:40, :416:13] assign normCount = {16'h0, _GEN_199[_normCount_T]}; // @[FSECompressorDicBuilder.scala:415:23, :416:13] wire _symbolTT_lookup_fire_and_last_vec_0_T_2; // @[FSECompressorDicBuilder.scala:441:71] wire symbolTT_lookup_fire_and_last_vec_0; // @[FSECompressorDicBuilder.scala:422:51] wire _T_2517 = dicBuilderState == 4'h8; // @[FSECompressorDicBuilder.scala:156:32, :429:23] assign _io_new_state_0_valid_T = _T_2517; // @[FSECompressorDicBuilder.scala:429:23, :438:47] wire _io_ll_table_log_valid_T_1; // @[FSECompressorDicBuilder.scala:453:68] assign _io_ll_table_log_valid_T_1 = _T_2517; // @[FSECompressorDicBuilder.scala:429:23, :453:68] assign _io_symbol_info_0_ready_T = io_symbolTT_info_0_ready_0 & _T_2517; // @[Misc.scala:26:53] assign io_symbol_info_0_ready_0 = _io_symbol_info_0_ready_T; // @[Misc.scala:26:53] assign _io_symbolTT_info_0_valid_T = io_symbol_info_0_valid_0 & _T_2517; // @[Misc.scala:26:53] assign io_symbolTT_info_0_valid_0 = _io_symbolTT_info_0_valid_T; // @[Misc.scala:26:53] wire [4:0] _io_symbolTT_info_0_bits_nbbit_T = io_symbol_info_0_bits_symbol_0[4:0]; // @[FSECompressorDicBuilder.scala:39:7] wire [4:0] _io_symbolTT_info_0_bits_findstate_T = io_symbol_info_0_bits_symbol_0[4:0]; // @[FSECompressorDicBuilder.scala:39:7] wire [31:0][31:0] _GEN_200 = {{ll_symbolTTDeltaNbBits_31}, {ll_symbolTTDeltaNbBits_30}, {ll_symbolTTDeltaNbBits_29}, {ll_symbolTTDeltaNbBits_28}, {ll_symbolTTDeltaNbBits_27}, {ll_symbolTTDeltaNbBits_26}, {ll_symbolTTDeltaNbBits_25}, {ll_symbolTTDeltaNbBits_24}, {ll_symbolTTDeltaNbBits_23}, {ll_symbolTTDeltaNbBits_22}, {ll_symbolTTDeltaNbBits_21}, {ll_symbolTTDeltaNbBits_20}, {ll_symbolTTDeltaNbBits_19}, {ll_symbolTTDeltaNbBits_18}, {ll_symbolTTDeltaNbBits_17}, {ll_symbolTTDeltaNbBits_16}, {ll_symbolTTDeltaNbBits_15}, {ll_symbolTTDeltaNbBits_14}, {ll_symbolTTDeltaNbBits_13}, {ll_symbolTTDeltaNbBits_12}, {ll_symbolTTDeltaNbBits_11}, {ll_symbolTTDeltaNbBits_10}, {ll_symbolTTDeltaNbBits_9}, {ll_symbolTTDeltaNbBits_8}, {ll_symbolTTDeltaNbBits_7}, {ll_symbolTTDeltaNbBits_6}, {ll_symbolTTDeltaNbBits_5}, {ll_symbolTTDeltaNbBits_4}, {ll_symbolTTDeltaNbBits_3}, {ll_symbolTTDeltaNbBits_2}, {ll_symbolTTDeltaNbBits_1}, {ll_symbolTTDeltaNbBits_0}}; // @[FSECompressorDicBuilder.scala:412:39, :434:36] assign io_symbolTT_info_0_bits_nbbit_0 = _GEN_200[_io_symbolTT_info_0_bits_nbbit_T]; // @[FSECompressorDicBuilder.scala:39:7, :434:36] wire [31:0][31:0] _GEN_201 = {{ll_symbolTTDeltaFindState_31}, {ll_symbolTTDeltaFindState_30}, {ll_symbolTTDeltaFindState_29}, {ll_symbolTTDeltaFindState_28}, {ll_symbolTTDeltaFindState_27}, {ll_symbolTTDeltaFindState_26}, {ll_symbolTTDeltaFindState_25}, {ll_symbolTTDeltaFindState_24}, {ll_symbolTTDeltaFindState_23}, {ll_symbolTTDeltaFindState_22}, {ll_symbolTTDeltaFindState_21}, {ll_symbolTTDeltaFindState_20}, {ll_symbolTTDeltaFindState_19}, {ll_symbolTTDeltaFindState_18}, {ll_symbolTTDeltaFindState_17}, {ll_symbolTTDeltaFindState_16}, {ll_symbolTTDeltaFindState_15}, {ll_symbolTTDeltaFindState_14}, {ll_symbolTTDeltaFindState_13}, {ll_symbolTTDeltaFindState_12}, {ll_symbolTTDeltaFindState_11}, {ll_symbolTTDeltaFindState_10}, {ll_symbolTTDeltaFindState_9}, {ll_symbolTTDeltaFindState_8}, {ll_symbolTTDeltaFindState_7}, {ll_symbolTTDeltaFindState_6}, {ll_symbolTTDeltaFindState_5}, {ll_symbolTTDeltaFindState_4}, {ll_symbolTTDeltaFindState_3}, {ll_symbolTTDeltaFindState_2}, {ll_symbolTTDeltaFindState_1}, {ll_symbolTTDeltaFindState_0}}; // @[FSECompressorDicBuilder.scala:413:42, :435:81] assign _io_symbolTT_info_0_bits_findstate_T_1 = _GEN_201[_io_symbolTT_info_0_bits_findstate_T]; // @[FSECompressorDicBuilder.scala:435:81] assign io_symbolTT_info_0_bits_findstate_0 = _io_symbolTT_info_0_bits_findstate_T_1; // @[FSECompressorDicBuilder.scala:39:7, :435:81] assign io_new_state_0_valid_0 = _io_new_state_0_valid_T; // @[FSECompressorDicBuilder.scala:39:7, :438:47] wire [5:0] _io_new_state_0_bits_T = io_state_table_idx_0_0[5:0]; // @[FSECompressorDicBuilder.scala:39:7] wire [63:0][15:0] _GEN_202 = {{ll_tableU16_63}, {ll_tableU16_62}, {ll_tableU16_61}, {ll_tableU16_60}, {ll_tableU16_59}, {ll_tableU16_58}, {ll_tableU16_57}, {ll_tableU16_56}, {ll_tableU16_55}, {ll_tableU16_54}, {ll_tableU16_53}, {ll_tableU16_52}, {ll_tableU16_51}, {ll_tableU16_50}, {ll_tableU16_49}, {ll_tableU16_48}, {ll_tableU16_47}, {ll_tableU16_46}, {ll_tableU16_45}, {ll_tableU16_44}, {ll_tableU16_43}, {ll_tableU16_42}, {ll_tableU16_41}, {ll_tableU16_40}, {ll_tableU16_39}, {ll_tableU16_38}, {ll_tableU16_37}, {ll_tableU16_36}, {ll_tableU16_35}, {ll_tableU16_34}, {ll_tableU16_33}, {ll_tableU16_32}, {ll_tableU16_31}, {ll_tableU16_30}, {ll_tableU16_29}, {ll_tableU16_28}, {ll_tableU16_27}, {ll_tableU16_26}, {ll_tableU16_25}, {ll_tableU16_24}, {ll_tableU16_23}, {ll_tableU16_22}, {ll_tableU16_21}, {ll_tableU16_20}, {ll_tableU16_19}, {ll_tableU16_18}, {ll_tableU16_17}, {ll_tableU16_16}, {ll_tableU16_15}, {ll_tableU16_14}, {ll_tableU16_13}, {ll_tableU16_12}, {ll_tableU16_11}, {ll_tableU16_10}, {ll_tableU16_9}, {ll_tableU16_8}, {ll_tableU16_7}, {ll_tableU16_6}, {ll_tableU16_5}, {ll_tableU16_4}, {ll_tableU16_3}, {ll_tableU16_2}, {ll_tableU16_1}, {ll_tableU16_0}}; // @[FSECompressorDicBuilder.scala:411:28, :439:26] assign io_new_state_0_bits_0 = _GEN_202[_io_new_state_0_bits_T]; // @[FSECompressorDicBuilder.scala:39:7, :439:26] wire _symbolTT_lookup_fire_and_last_vec_0_T = io_symbol_info_0_valid_0 & io_symbolTT_info_0_ready_0; // @[Misc.scala:29:18] wire _symbolTT_lookup_fire_and_last_vec_0_T_1 = _symbolTT_lookup_fire_and_last_vec_0_T & _T_2517; // @[Misc.scala:29:18] assign _symbolTT_lookup_fire_and_last_vec_0_T_2 = _symbolTT_lookup_fire_and_last_vec_0_T_1 & io_symbol_info_0_bits_last_symbol_0; // @[Misc.scala:29:18] assign symbolTT_lookup_fire_and_last_vec_0 = _symbolTT_lookup_fire_and_last_vec_0_T_2; // @[FSECompressorDicBuilder.scala:422:51, :441:71] wire _use_predefined_mode_T = io_nb_seq_bits_0 < 64'h15; // @[FSECompressorDicBuilder.scala:39:7, :449:45] wire use_predefined_mode = _use_predefined_mode_T \| fse_normalize_corner_case_reg; // @[FSECompressorDicBuilder.scala:314:46, :449:{45,87}] reg ll_table_log_fired; // @[FSECompressorDicBuilder.scala:451:35] wire [2:0] _io_ll_table_log_bits_T = use_predefined_mode ? 3'h5 : 3'h6; // @[FSECompressorDicBuilder.scala:449:87, :452:30] assign io_ll_table_log_bits_0 = {1'h0, _io_ll_table_log_bits_T}; // @[FSECompressorDicBuilder.scala:39:7, :452:{24,30}] wire _io_ll_table_log_valid_T = ~ll_table_log_fired; // @[FSECompressorDicBuilder.scala:451:35, :453:28] assign _io_ll_table_log_valid_T_2 = _io_ll_table_log_valid_T & _io_ll_table_log_valid_T_1; // @[FSECompressorDicBuilder.scala:453:{28,48,68}] assign io_ll_table_log_valid_0 = _io_ll_table_log_valid_T_2; // @[FSECompressorDicBuilder.scala:39:7, :453:48] reg print_table; // @[FSECompressorDicBuilder.scala:458:28] reg write_header_started; // @[FSECompressorDicBuilder.scala:461:37] reg [31:0] nbBits; // @[FSECompressorDicBuilder.scala:462:23] reg [31:0] remaining; // @[FSECompressorDicBuilder.scala:463:26] reg [31:0] threshold; // @[FSECompressorDicBuilder.scala:464:26] wire [31:0] shifted_thresholds_0 = threshold; // @[FSECompressorDicBuilder.scala:464:26, :484:36] reg [31:0] symbol; // @[FSECompressorDicBuilder.scala:465:23] wire [31:0] alphabetSize = _alphabetSize_T[31:0]; // @[FSECompressorDicBuilder.scala:466:42] reg previousIs0; // @[FSECompressorDicBuilder.scala:467:28] reg [63:0] bitStream; // @[FSECompressorDicBuilder.scala:468:26] reg [6:0] bitCount; // @[FSECompressorDicBuilder.scala:469:25] reg writeBitStream; // @[FSECompressorDicBuilder.scala:470:31] reg [31:0] start; // @[FSECompressorDicBuilder.scala:471:22] reg start_initialized; // @[FSECompressorDicBuilder.scala:472:34] reg skip_zeros_done; // @[FSECompressorDicBuilder.scala:473:32] reg skip_24_done; // @[FSECompressorDicBuilder.scala:474:29] reg skip_3_done; // @[FSECompressorDicBuilder.scala:475:28] reg writeBitStreamPrev0; // @[FSECompressorDicBuilder.scala:476:36] wire [31:0] _shifted_thresholds_1_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] _shifted_thresholds_2_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] _shifted_thresholds_3_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] _shifted_thresholds_4_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] _shifted_thresholds_5_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] _shifted_thresholds_6_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] shifted_thresholds_1; // @[FSECompressorDicBuilder.scala:484:36] wire [31:0] shifted_thresholds_2; // @[FSECompressorDicBuilder.scala:484:36] wire [31:0] shifted_thresholds_3; // @[FSECompressorDicBuilder.scala:484:36] wire [31:0] shifted_thresholds_4; // @[FSECompressorDicBuilder.scala:484:36] wire [31:0] shifted_thresholds_5; // @[FSECompressorDicBuilder.scala:484:36] wire [31:0] shifted_thresholds_6; // @[FSECompressorDicBuilder.scala:484:36] assign _shifted_thresholds_1_T = {1'h0, shifted_thresholds_0[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_1 = _shifted_thresholds_1_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign _shifted_thresholds_2_T = {1'h0, shifted_thresholds_1[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_2 = _shifted_thresholds_2_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign _shifted_thresholds_3_T = {1'h0, shifted_thresholds_2[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_3 = _shifted_thresholds_3_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign _shifted_thresholds_4_T = {1'h0, shifted_thresholds_3[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_4 = _shifted_thresholds_4_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign _shifted_thresholds_5_T = {1'h0, shifted_thresholds_4[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_5 = _shifted_thresholds_5_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign _shifted_thresholds_6_T = {1'h0, shifted_thresholds_5[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_6 = _shifted_thresholds_6_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] wire [31:0] shifted_threshold_small_or_eq_remaining_0; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_1; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_2; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_3; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_4; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_5; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_6; // @[FSECompressorDicBuilder.scala:490:57] wire [32:0] _nxt_shifted_threshold_idx_T = {1'h0, shifted_threshold_small_or_eq_remaining_0} + {1'h0, shifted_threshold_small_or_eq_remaining_1}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] _nxt_shifted_threshold_idx_T_1 = _nxt_shifted_threshold_idx_T[31:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nxt_shifted_threshold_idx_T_2 = {1'h0, _nxt_shifted_threshold_idx_T_1} + {1'h0, shifted_threshold_small_or_eq_remaining_2}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] _nxt_shifted_threshold_idx_T_3 = _nxt_shifted_threshold_idx_T_2[31:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nxt_shifted_threshold_idx_T_4 = {1'h0, _nxt_shifted_threshold_idx_T_3} + {1'h0, shifted_threshold_small_or_eq_remaining_3}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] _nxt_shifted_threshold_idx_T_5 = _nxt_shifted_threshold_idx_T_4[31:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nxt_shifted_threshold_idx_T_6 = {1'h0, _nxt_shifted_threshold_idx_T_5} + {1'h0, shifted_threshold_small_or_eq_remaining_4}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] _nxt_shifted_threshold_idx_T_7 = _nxt_shifted_threshold_idx_T_6[31:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nxt_shifted_threshold_idx_T_8 = {1'h0, _nxt_shifted_threshold_idx_T_7} + {1'h0, shifted_threshold_small_or_eq_remaining_5}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] _nxt_shifted_threshold_idx_T_9 = _nxt_shifted_threshold_idx_T_8[31:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nxt_shifted_threshold_idx_T_10 = {1'h0, _nxt_shifted_threshold_idx_T_9} + {1'h0, shifted_threshold_small_or_eq_remaining_6}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] nxt_shifted_threshold_idx = _nxt_shifted_threshold_idx_T_10[31:0]; // @[FSECompressorDicBuilder.scala:491:84] assign io_ll_stream_output_ready_0 = (\|dicBuilderState) & _T_839 & _predefined_mode_q_io_enq_ready; // @[FSECompressorDicBuilder.scala:39:7, :137:29, :141:33, :156:32, :198:25, :551:28, :559:33] wire _io_ll_stream_user_consumed_bytes_T = io_ll_stream_available_output_bytes_0 < 6'h4; // @[FSECompressorDicBuilder.scala:39:7, :560:83] wire [5:0] _io_ll_stream_user_consumed_bytes_T_1 = _io_ll_stream_user_consumed_bytes_T ? io_ll_stream_available_output_bytes_0 : 6'h4; // @[FSECompressorDicBuilder.scala:39:7, :560:{46,83}] wire _GEN_203 = (\|dicBuilderState) & _T_839; // @[FSECompressorDicBuilder.scala:138:36, :156:32, :198:25, :551:28] assign io_ll_stream_user_consumed_bytes_0 = _GEN_203 ? _io_ll_stream_user_consumed_bytes_T_1 : 6'h0; // @[FSECompressorDicBuilder.scala:39:7, :138:36, :551:28, :560:46] wire [31:0] _ll_count_0_T_3 = _ll_count_0_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_1_T_3 = _ll_count_1_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_2_T_3 = _ll_count_2_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_3_T_3 = _ll_count_3_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_4_T_3 = _ll_count_4_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_5_T_3 = _ll_count_5_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_6_T_3 = _ll_count_6_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_7_T_3 = _ll_count_7_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_8_T_3 = _ll_count_8_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_9_T_3 = _ll_count_9_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_10_T_3 = _ll_count_10_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_11_T_3 = _ll_count_11_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_12_T_3 = _ll_count_12_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_13_T_3 = _ll_count_13_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_14_T_3 = _ll_count_14_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_15_T_3 = _ll_count_15_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_16_T_3 = _ll_count_16_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_17_T_3 = _ll_count_17_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_18_T_3 = _ll_count_18_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_19_T_3 = _ll_count_19_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_20_T_3 = _ll_count_20_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_21_T_3 = _ll_count_21_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_22_T_3 = _ll_count_22_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_23_T_3 = _ll_count_23_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_24_T_3 = _ll_count_24_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_25_T_3 = _ll_count_25_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_26_T_3 = _ll_count_26_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_27_T_3 = _ll_count_27_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_28_T_3 = _ll_count_28_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_29_T_3 = _ll_count_29_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_30_T_3 = _ll_count_30_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_31_T_3 = _ll_count_31_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_max_symbol_value_T_3 = _ll_max_symbol_value_T_2 ? ll_max_symbol_value : _GEN_32; // @[FSECompressorDicBuilder.scala:170:36, :204:54, :569:{35,56}] wire _T_843 = _predefined_mode_q_io_enq_ready & io_ll_stream_output_valid_0 & io_ll_stream_output_last_chunk_0 & io_ll_stream_user_consumed_bytes_0 == io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :141:33, :572:{44,73,107,144}] wire [6:0] _ll_last_codetable_T = {1'h0, io_ll_stream_user_consumed_bytes_0} - 7'h1; // @[FSECompressorDicBuilder.scala:39:7, :579:85] wire [5:0] _ll_last_codetable_T_1 = _ll_last_codetable_T[5:0]; // @[FSECompressorDicBuilder.scala:579:85] wire [1:0] _ll_last_codetable_T_2 = _ll_last_codetable_T_1[1:0]; // @[FSECompressorDicBuilder.scala:579:85] wire [3:0][7:0] _GEN_204 = {{input_ll_symbols_3}, {input_ll_symbols_2}, {input_ll_symbols_1}, {input_ll_symbols_0}}; // @[FSECompressorDicBuilder.scala:172:34] wire [4:0] _ll_count_last_codetable_T = _GEN_204[_ll_last_codetable_T_2][4:0]; wire [4:0] _ll_last_statcount_T = _GEN_204[_ll_last_codetable_T_2][4:0]; wire [31:0][31:0] _GEN_205 = {{ll_count_31}, {ll_count_30}, {ll_count_29}, {ll_count_28}, {ll_count_27}, {ll_count_26}, {ll_count_25}, {ll_count_24}, {ll_count_23}, {ll_count_22}, {ll_count_21}, {ll_count_20}, {ll_count_19}, {ll_count_18}, {ll_count_17}, {ll_count_16}, {ll_count_15}, {ll_count_14}, {ll_count_13}, {ll_count_12}, {ll_count_11}, {ll_count_10}, {ll_count_9}, {ll_count_8}, {ll_count_7}, {ll_count_6}, {ll_count_5}, {ll_count_4}, {ll_count_3}, {ll_count_2}, {ll_count_1}, {ll_count_0}}; // @[FSECompressorDicBuilder.scala:169:25, :583:55] wire [31:0][2:0] _GEN_206 = {{stat_sum_31}, {stat_sum_30}, {stat_sum_29}, {stat_sum_28}, {stat_sum_27}, {stat_sum_26}, {stat_sum_25}, {stat_sum_24}, {stat_sum_23}, {stat_sum_22}, {stat_sum_21}, {stat_sum_20}, {stat_sum_19}, {stat_sum_18}, {stat_sum_17}, {stat_sum_16}, {stat_sum_15}, {stat_sum_14}, {stat_sum_13}, {stat_sum_12}, {stat_sum_11}, {stat_sum_10}, {stat_sum_9}, {stat_sum_8}, {stat_sum_7}, {stat_sum_6}, {stat_sum_5}, {stat_sum_4}, {stat_sum_3}, {stat_sum_2}, {stat_sum_1}, {stat_sum_0}}; // @[FSECompressorDicBuilder.scala:186:26, :583:55] wire [32:0] _ll_last_count_T = {1'h0, _GEN_205[_ll_count_last_codetable_T]} + {30'h0, _GEN_206[_ll_last_statcount_T]}; // @[FSECompressorDicBuilder.scala:583:55] wire [31:0] ll_last_count = _ll_last_count_T[31:0]; // @[FSECompressorDicBuilder.scala:583:55] wire do_subtract = \|(ll_last_count[31:1]); // @[FSECompressorDicBuilder.scala:583:55, :584:43] wire [64:0] _ll_nbseq_1_T = {1'h0, io_nb_seq_bits_0} - 65'h1; // @[FSECompressorDicBuilder.scala:39:7, :585:57] wire [63:0] _ll_nbseq_1_T_1 = _ll_nbseq_1_T[63:0]; // @[FSECompressorDicBuilder.scala:585:57] wire [63:0] _ll_nbseq_1_T_2 = do_subtract ? _ll_nbseq_1_T_1 : io_nb_seq_bits_0; // @[FSECompressorDicBuilder.scala:39:7, :584:43, :585:{28,57}] wire _GEN_207 = _T_839 & _T_843; // @[FSECompressorDicBuilder.scala:198:25, :494:31, :551:28, :572:{44,73,107,186}, :585:22] wire [32:0] _ll_count_T = {1'h0, ll_last_count} - 33'h1; // @[FSECompressorDicBuilder.scala:583:55, :586:73] wire [31:0] _ll_count_T_1 = _ll_count_T[31:0]; // @[FSECompressorDicBuilder.scala:586:73] wire [31:0] _ll_count_T_2 = do_subtract ? _ll_count_T_1 : ll_last_count; // @[FSECompressorDicBuilder.scala:583:55, :584:43, :586:{45,73}] wire _GEN_208 = (\|dicBuilderState) & _GEN_207 & use_predefined_mode; // @[FSECompressorDicBuilder.scala:156:32, :316:80, :449:87, :494:31, :551:28, :572:186, :585:22, :591:37] reg [63:0] loginfo_cycles_207; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_414 = {1'h0, loginfo_cycles_207} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_415 = _loginfo_cycles_T_414[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_208; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_416 = {1'h0, loginfo_cycles_208} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_417 = _loginfo_cycles_T_416[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_209; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_418 = {1'h0, loginfo_cycles_209} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_419 = _loginfo_cycles_T_418[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_210; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_420 = {1'h0, loginfo_cycles_210} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_421 = _loginfo_cycles_T_420[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_211; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_422 = {1'h0, loginfo_cycles_211} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_423 = _loginfo_cycles_T_422[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_212; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_424 = {1'h0, loginfo_cycles_212} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_425 = _loginfo_cycles_T_424[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_213; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_426 = {1'h0, loginfo_cycles_213} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_427 = _loginfo_cycles_T_426[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_214; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_428 = {1'h0, loginfo_cycles_214} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_429 = _loginfo_cycles_T_428[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_215; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_430 = {1'h0, loginfo_cycles_215} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_431 = _loginfo_cycles_T_430[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_216; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_432 = {1'h0, loginfo_cycles_216} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_433 = _loginfo_cycles_T_432[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_217; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_434 = {1'h0, loginfo_cycles_217} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_435 = _loginfo_cycles_T_434[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_218; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_436 = {1'h0, loginfo_cycles_218} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_437 = _loginfo_cycles_T_436[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_219; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_438 = {1'h0, loginfo_cycles_219} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_439 = _loginfo_cycles_T_438[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_220; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_440 = {1'h0, loginfo_cycles_220} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_441 = _loginfo_cycles_T_440[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_221; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_442 = {1'h0, loginfo_cycles_221} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_443 = _loginfo_cycles_T_442[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_222; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_444 = {1'h0, loginfo_cycles_222} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_445 = _loginfo_cycles_T_444[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_223; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_446 = {1'h0, loginfo_cycles_223} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_447 = _loginfo_cycles_T_446[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_224; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_448 = {1'h0, loginfo_cycles_224} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_449 = _loginfo_cycles_T_448[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_225; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_450 = {1'h0, loginfo_cycles_225} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_451 = _loginfo_cycles_T_450[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_226; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_452 = {1'h0, loginfo_cycles_226} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_453 = _loginfo_cycles_T_452[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_227; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_454 = {1'h0, loginfo_cycles_227} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_455 = _loginfo_cycles_T_454[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_228; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_456 = {1'h0, loginfo_cycles_228} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_457 = _loginfo_cycles_T_456[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_229; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_458 = {1'h0, loginfo_cycles_229} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_459 = _loginfo_cycles_T_458[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_230; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_460 = {1'h0, loginfo_cycles_230} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_461 = _loginfo_cycles_T_460[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_231; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_462 = {1'h0, loginfo_cycles_231} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_463 = _loginfo_cycles_T_462[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_232; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_464 = {1'h0, loginfo_cycles_232} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_465 = _loginfo_cycles_T_464[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_233; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_466 = {1'h0, loginfo_cycles_233} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_467 = _loginfo_cycles_T_466[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_234; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_468 = {1'h0, loginfo_cycles_234} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_469 = _loginfo_cycles_T_468[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_235; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_470 = {1'h0, loginfo_cycles_235} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_471 = _loginfo_cycles_T_470[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_236; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_472 = {1'h0, loginfo_cycles_236} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_473 = _loginfo_cycles_T_472[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_237; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_474 = {1'h0, loginfo_cycles_237} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_475 = _loginfo_cycles_T_474[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_238; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_476 = {1'h0, loginfo_cycles_238} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_477 = _loginfo_cycles_T_476[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_239; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_478 = {1'h0, loginfo_cycles_239} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_479 = _loginfo_cycles_T_478[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_240; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_480 = {1'h0, loginfo_cycles_240} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_481 = _loginfo_cycles_T_480[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_241; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_482 = {1'h0, loginfo_cycles_241} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_483 = _loginfo_cycles_T_482[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_242; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_484 = {1'h0, loginfo_cycles_242} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_485 = _loginfo_cycles_T_484[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_243; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_486 = {1'h0, loginfo_cycles_243} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_487 = _loginfo_cycles_T_486[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_244; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_488 = {1'h0, loginfo_cycles_244} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_489 = _loginfo_cycles_T_488[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_245; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_490 = {1'h0, loginfo_cycles_245} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_491 = _loginfo_cycles_T_490[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_246; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_492 = {1'h0, loginfo_cycles_246} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_493 = _loginfo_cycles_T_492[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_247; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_494 = {1'h0, loginfo_cycles_247} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_495 = _loginfo_cycles_T_494[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_248; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_496 = {1'h0, loginfo_cycles_248} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_497 = _loginfo_cycles_T_496[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_249; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_498 = {1'h0, loginfo_cycles_249} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_499 = _loginfo_cycles_T_498[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_250; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_500 = {1'h0, loginfo_cycles_250} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_501 = _loginfo_cycles_T_500[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_251; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_502 = {1'h0, loginfo_cycles_251} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_503 = _loginfo_cycles_T_502[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_252; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_504 = {1'h0, loginfo_cycles_252} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_505 = _loginfo_cycles_T_504[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_253; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_506 = {1'h0, loginfo_cycles_253} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_507 = _loginfo_cycles_T_506[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_254; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_508 = {1'h0, loginfo_cycles_254} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_509 = _loginfo_cycles_T_508[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_255; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_510 = {1'h0, loginfo_cycles_255} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_511 = _loginfo_cycles_T_510[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_256; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_512 = {1'h0, loginfo_cycles_256} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_513 = _loginfo_cycles_T_512[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_257; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_514 = {1'h0, loginfo_cycles_257} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_515 = _loginfo_cycles_T_514[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_258; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_516 = {1'h0, loginfo_cycles_258} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_517 = _loginfo_cycles_T_516[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_259; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_518 = {1'h0, loginfo_cycles_259} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_519 = _loginfo_cycles_T_518[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_260; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_520 = {1'h0, loginfo_cycles_260} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_521 = _loginfo_cycles_T_520[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_261; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_522 = {1'h0, loginfo_cycles_261} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_523 = _loginfo_cycles_T_522[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_262; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_524 = {1'h0, loginfo_cycles_262} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_525 = _loginfo_cycles_T_524[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_263; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_526 = {1'h0, loginfo_cycles_263} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_527 = _loginfo_cycles_T_526[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_264; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_528 = {1'h0, loginfo_cycles_264} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_529 = _loginfo_cycles_T_528[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_265; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_530 = {1'h0, loginfo_cycles_265} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_531 = _loginfo_cycles_T_530[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_266; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_532 = {1'h0, loginfo_cycles_266} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_533 = _loginfo_cycles_T_532[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_267; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_534 = {1'h0, loginfo_cycles_267} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_535 = _loginfo_cycles_T_534[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_268; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_536 = {1'h0, loginfo_cycles_268} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_537 = _loginfo_cycles_T_536[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_269; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_538 = {1'h0, loginfo_cycles_269} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_539 = _loginfo_cycles_T_538[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_270; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_540 = {1'h0, loginfo_cycles_270} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_541 = _loginfo_cycles_T_540[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_271; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_542 = {1'h0, loginfo_cycles_271} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_543 = _loginfo_cycles_T_542[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_272; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_544 = {1'h0, loginfo_cycles_272} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_545 = _loginfo_cycles_T_544[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_273; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_546 = {1'h0, loginfo_cycles_273} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_547 = _loginfo_cycles_T_546[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_274; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_548 = {1'h0, loginfo_cycles_274} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_549 = _loginfo_cycles_T_548[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_275; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_550 = {1'h0, loginfo_cycles_275} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_551 = _loginfo_cycles_T_550[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_276; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_552 = {1'h0, loginfo_cycles_276} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_553 = _loginfo_cycles_T_552[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_277; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_554 = {1'h0, loginfo_cycles_277} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_555 = _loginfo_cycles_T_554[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_278; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_556 = {1'h0, loginfo_cycles_278} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_557 = _loginfo_cycles_T_556[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_279; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_558 = {1'h0, loginfo_cycles_279} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_559 = _loginfo_cycles_T_558[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_280; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_560 = {1'h0, loginfo_cycles_280} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_561 = _loginfo_cycles_T_560[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_281; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_562 = {1'h0, loginfo_cycles_281} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_563 = _loginfo_cycles_T_562[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_282; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_564 = {1'h0, loginfo_cycles_282} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_565 = _loginfo_cycles_T_564[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_283; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_566 = {1'h0, loginfo_cycles_283} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_567 = _loginfo_cycles_T_566[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_284; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_568 = {1'h0, loginfo_cycles_284} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_569 = _loginfo_cycles_T_568[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_285; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_570 = {1'h0, loginfo_cycles_285} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_571 = _loginfo_cycles_T_570[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_286; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_572 = {1'h0, loginfo_cycles_286} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_573 = _loginfo_cycles_T_572[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_287; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_574 = {1'h0, loginfo_cycles_287} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_575 = _loginfo_cycles_T_574[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_288; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_576 = {1'h0, loginfo_cycles_288} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_577 = _loginfo_cycles_T_576[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_289; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_578 = {1'h0, loginfo_cycles_289} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_579 = _loginfo_cycles_T_578[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_290; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_580 = {1'h0, loginfo_cycles_290} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_581 = _loginfo_cycles_T_580[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_291; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_582 = {1'h0, loginfo_cycles_291} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_583 = _loginfo_cycles_T_582[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_292; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_584 = {1'h0, loginfo_cycles_292} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_585 = _loginfo_cycles_T_584[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_293; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_586 = {1'h0, loginfo_cycles_293} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_587 = _loginfo_cycles_T_586[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_294; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_588 = {1'h0, loginfo_cycles_294} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_589 = _loginfo_cycles_T_588[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_295; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_590 = {1'h0, loginfo_cycles_295} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_591 = _loginfo_cycles_T_590[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_296; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_592 = {1'h0, loginfo_cycles_296} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_593 = _loginfo_cycles_T_592[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_297; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_594 = {1'h0, loginfo_cycles_297} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_595 = _loginfo_cycles_T_594[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_298; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_596 = {1'h0, loginfo_cycles_298} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_597 = _loginfo_cycles_T_596[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_299; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_598 = {1'h0, loginfo_cycles_299} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_599 = _loginfo_cycles_T_598[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_300; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_600 = {1'h0, loginfo_cycles_300} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_601 = _loginfo_cycles_T_600[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_301; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_602 = {1'h0, loginfo_cycles_301} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_603 = _loginfo_cycles_T_602[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_302; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_604 = {1'h0, loginfo_cycles_302} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_605 = _loginfo_cycles_T_604[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_303; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_606 = {1'h0, loginfo_cycles_303} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_607 = _loginfo_cycles_T_606[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_304; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_608 = {1'h0, loginfo_cycles_304} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_609 = _loginfo_cycles_T_608[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_305; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_610 = {1'h0, loginfo_cycles_305} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_611 = _loginfo_cycles_T_610[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_306; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_612 = {1'h0, loginfo_cycles_306} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_613 = _loginfo_cycles_T_612[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_307; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_614 = {1'h0, loginfo_cycles_307} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_615 = _loginfo_cycles_T_614[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_308; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_616 = {1'h0, loginfo_cycles_308} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_617 = _loginfo_cycles_T_616[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_309; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_618 = {1'h0, loginfo_cycles_309} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_619 = _loginfo_cycles_T_618[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_310; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_620 = {1'h0, loginfo_cycles_310} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_621 = _loginfo_cycles_T_620[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_311; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_622 = {1'h0, loginfo_cycles_311} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_623 = _loginfo_cycles_T_622[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_312; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_624 = {1'h0, loginfo_cycles_312} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_625 = _loginfo_cycles_T_624[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_313; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_626 = {1'h0, loginfo_cycles_313} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_627 = _loginfo_cycles_T_626[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_314; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_628 = {1'h0, loginfo_cycles_314} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_629 = _loginfo_cycles_T_628[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_315; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_630 = {1'h0, loginfo_cycles_315} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_631 = _loginfo_cycles_T_630[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_316; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_632 = {1'h0, loginfo_cycles_316} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_633 = _loginfo_cycles_T_632[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_317; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_634 = {1'h0, loginfo_cycles_317} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_635 = _loginfo_cycles_T_634[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_318; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_636 = {1'h0, loginfo_cycles_318} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_637 = _loginfo_cycles_T_636[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_319; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_638 = {1'h0, loginfo_cycles_319} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_639 = _loginfo_cycles_T_638[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_320; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_640 = {1'h0, loginfo_cycles_320} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_641 = _loginfo_cycles_T_640[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_321; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_642 = {1'h0, loginfo_cycles_321} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_643 = _loginfo_cycles_T_642[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_322; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_644 = {1'h0, loginfo_cycles_322} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_645 = _loginfo_cycles_T_644[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_323; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_646 = {1'h0, loginfo_cycles_323} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_647 = _loginfo_cycles_T_646[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_324; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_648 = {1'h0, loginfo_cycles_324} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_649 = _loginfo_cycles_T_648[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_325; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_650 = {1'h0, loginfo_cycles_325} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_651 = _loginfo_cycles_T_650[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_326; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_652 = {1'h0, loginfo_cycles_326} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_653 = _loginfo_cycles_T_652[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_327; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_654 = {1'h0, loginfo_cycles_327} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_655 = _loginfo_cycles_T_654[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_328; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_656 = {1'h0, loginfo_cycles_328} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_657 = _loginfo_cycles_T_656[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_329; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_658 = {1'h0, loginfo_cycles_329} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_659 = _loginfo_cycles_T_658[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_330; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_660 = {1'h0, loginfo_cycles_330} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_661 = _loginfo_cycles_T_660[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_331; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_662 = {1'h0, loginfo_cycles_331} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_663 = _loginfo_cycles_T_662[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_332; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_664 = {1'h0, loginfo_cycles_332} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_665 = _loginfo_cycles_T_664[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_333; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_666 = {1'h0, loginfo_cycles_333} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_667 = _loginfo_cycles_T_666[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_334; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_668 = {1'h0, loginfo_cycles_334} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_669 = _loginfo_cycles_T_668[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_335; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_670 = {1'h0, loginfo_cycles_335} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_671 = _loginfo_cycles_T_670[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_336; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_672 = {1'h0, loginfo_cycles_336} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_673 = _loginfo_cycles_T_672[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_337; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_674 = {1'h0, loginfo_cycles_337} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_675 = _loginfo_cycles_T_674[63:0]; // @[Util.scala:19:38] wire _T_1371 = dicBuilderState == 4'h3; // @[FSECompressorDicBuilder.scala:156:32, :551:28] wire _GEN_209 = ~(\|dicBuilderState) \| _T_839 \| _T_846; // @[FSECompressorDicBuilder.scala:156:32, :198:25, :316:25, :389:44, :551:28] wire _GEN_210 = _GEN_209 \| ~_T_1371; // @[FSECompressorDicBuilder.scala:389:44, :551:28] assign ll_normCountEqsNegOneCumul_0 = _GEN_210 ? 8'h0 : ll_normCountEqsNegOne_0; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :551:28] assign ll_normCountEqsNegOne_0 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_0)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_211 = {1'h0, ll_cumul_0}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_1_T = _GEN_211 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_1_T_1 = _ll_cumul_1_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_1_T_2 = _GEN_211 + {1'h0, ll_normalizedCounterReg_0}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_1_T_3 = _ll_cumul_1_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_1_T = {1'h0, ll_normCountEqsNegOneCumul_0} + _GEN_198; // @[FSECompressorDicBuilder.scala:389:44, :390:65, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_1_T_1 = _ll_normCountEqsNegOneCumul_1_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_1 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_1_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_1 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_1)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_212 = {1'h0, ll_cumul_1}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_2_T = _GEN_212 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_2_T_1 = _ll_cumul_2_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_2_T_2 = _GEN_212 + {1'h0, ll_normalizedCounterReg_1}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_2_T_3 = _ll_cumul_2_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_2_T = {1'h0, ll_normCountEqsNegOneCumul_1} + {1'h0, ll_normCountEqsNegOne_2}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_2_T_1 = _ll_normCountEqsNegOneCumul_2_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_2 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_2_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_2 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_2)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_213 = {1'h0, ll_cumul_2}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_3_T = _GEN_213 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_3_T_1 = _ll_cumul_3_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_3_T_2 = _GEN_213 + {1'h0, ll_normalizedCounterReg_2}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_3_T_3 = _ll_cumul_3_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_3_T = {1'h0, ll_normCountEqsNegOneCumul_2} + {1'h0, ll_normCountEqsNegOne_3}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_3_T_1 = _ll_normCountEqsNegOneCumul_3_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_3 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_3_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_3 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_3)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_214 = {1'h0, ll_cumul_3}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_4_T = _GEN_214 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_4_T_1 = _ll_cumul_4_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_4_T_2 = _GEN_214 + {1'h0, ll_normalizedCounterReg_3}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_4_T_3 = _ll_cumul_4_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_4_T = {1'h0, ll_normCountEqsNegOneCumul_3} + {1'h0, ll_normCountEqsNegOne_4}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_4_T_1 = _ll_normCountEqsNegOneCumul_4_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_4 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_4_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_4 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_4)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_215 = {1'h0, ll_cumul_4}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_5_T = _GEN_215 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_5_T_1 = _ll_cumul_5_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_5_T_2 = _GEN_215 + {1'h0, ll_normalizedCounterReg_4}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_5_T_3 = _ll_cumul_5_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_5_T = {1'h0, ll_normCountEqsNegOneCumul_4} + {1'h0, ll_normCountEqsNegOne_5}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_5_T_1 = _ll_normCountEqsNegOneCumul_5_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_5 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_5_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_5 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_5)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_216 = {1'h0, ll_cumul_5}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_6_T = _GEN_216 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_6_T_1 = _ll_cumul_6_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_6_T_2 = _GEN_216 + {1'h0, ll_normalizedCounterReg_5}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_6_T_3 = _ll_cumul_6_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_6_T = {1'h0, ll_normCountEqsNegOneCumul_5} + {1'h0, ll_normCountEqsNegOne_6}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_6_T_1 = _ll_normCountEqsNegOneCumul_6_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_6 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_6_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_6 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_6)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_217 = {1'h0, ll_cumul_6}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_7_T = _GEN_217 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_7_T_1 = _ll_cumul_7_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_7_T_2 = _GEN_217 + {1'h0, ll_normalizedCounterReg_6}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_7_T_3 = _ll_cumul_7_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_7_T = {1'h0, ll_normCountEqsNegOneCumul_6} + {1'h0, ll_normCountEqsNegOne_7}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_7_T_1 = _ll_normCountEqsNegOneCumul_7_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_7 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_7_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_7 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_7)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_218 = {1'h0, ll_cumul_7}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_8_T = _GEN_218 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_8_T_1 = _ll_cumul_8_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_8_T_2 = _GEN_218 + {1'h0, ll_normalizedCounterReg_7}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_8_T_3 = _ll_cumul_8_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_8_T = {1'h0, ll_normCountEqsNegOneCumul_7} + {1'h0, ll_normCountEqsNegOne_8}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_8_T_1 = _ll_normCountEqsNegOneCumul_8_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_8 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_8_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_8 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_8)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_219 = {1'h0, ll_cumul_8}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_9_T = _GEN_219 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_9_T_1 = _ll_cumul_9_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_9_T_2 = _GEN_219 + {1'h0, ll_normalizedCounterReg_8}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_9_T_3 = _ll_cumul_9_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_9_T = {1'h0, ll_normCountEqsNegOneCumul_8} + {1'h0, ll_normCountEqsNegOne_9}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_9_T_1 = _ll_normCountEqsNegOneCumul_9_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_9 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_9_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_9 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_9)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_220 = {1'h0, ll_cumul_9}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_10_T = _GEN_220 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_10_T_1 = _ll_cumul_10_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_10_T_2 = _GEN_220 + {1'h0, ll_normalizedCounterReg_9}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_10_T_3 = _ll_cumul_10_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_10_T = {1'h0, ll_normCountEqsNegOneCumul_9} + {1'h0, ll_normCountEqsNegOne_10}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_10_T_1 = _ll_normCountEqsNegOneCumul_10_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_10 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_10_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_10 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_10)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_221 = {1'h0, ll_cumul_10}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_11_T = _GEN_221 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_11_T_1 = _ll_cumul_11_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_11_T_2 = _GEN_221 + {1'h0, ll_normalizedCounterReg_10}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_11_T_3 = _ll_cumul_11_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_11_T = {1'h0, ll_normCountEqsNegOneCumul_10} + {1'h0, ll_normCountEqsNegOne_11}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_11_T_1 = _ll_normCountEqsNegOneCumul_11_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_11 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_11_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_11 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_11)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_222 = {1'h0, ll_cumul_11}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_12_T = _GEN_222 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_12_T_1 = _ll_cumul_12_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_12_T_2 = _GEN_222 + {1'h0, ll_normalizedCounterReg_11}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_12_T_3 = _ll_cumul_12_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_12_T = {1'h0, ll_normCountEqsNegOneCumul_11} + {1'h0, ll_normCountEqsNegOne_12}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_12_T_1 = _ll_normCountEqsNegOneCumul_12_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_12 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_12_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_12 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_12)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_223 = {1'h0, ll_cumul_12}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_13_T = _GEN_223 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_13_T_1 = _ll_cumul_13_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_13_T_2 = _GEN_223 + {1'h0, ll_normalizedCounterReg_12}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_13_T_3 = _ll_cumul_13_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_13_T = {1'h0, ll_normCountEqsNegOneCumul_12} + {1'h0, ll_normCountEqsNegOne_13}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_13_T_1 = _ll_normCountEqsNegOneCumul_13_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_13 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_13_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_13 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_13)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_224 = {1'h0, ll_cumul_13}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_14_T = _GEN_224 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_14_T_1 = _ll_cumul_14_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_14_T_2 = _GEN_224 + {1'h0, ll_normalizedCounterReg_13}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_14_T_3 = _ll_cumul_14_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_14_T = {1'h0, ll_normCountEqsNegOneCumul_13} + {1'h0, ll_normCountEqsNegOne_14}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_14_T_1 = _ll_normCountEqsNegOneCumul_14_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_14 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_14_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_14 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_14)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_225 = {1'h0, ll_cumul_14}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_15_T = _GEN_225 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_15_T_1 = _ll_cumul_15_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_15_T_2 = _GEN_225 + {1'h0, ll_normalizedCounterReg_14}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_15_T_3 = _ll_cumul_15_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_15_T = {1'h0, ll_normCountEqsNegOneCumul_14} + {1'h0, ll_normCountEqsNegOne_15}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_15_T_1 = _ll_normCountEqsNegOneCumul_15_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_15 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_15_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_15 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_15)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_226 = {1'h0, ll_cumul_15}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_16_T = _GEN_226 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_16_T_1 = _ll_cumul_16_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_16_T_2 = _GEN_226 + {1'h0, ll_normalizedCounterReg_15}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_16_T_3 = _ll_cumul_16_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_16_T = {1'h0, ll_normCountEqsNegOneCumul_15} + {1'h0, ll_normCountEqsNegOne_16}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_16_T_1 = _ll_normCountEqsNegOneCumul_16_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_16 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_16_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_16 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_16)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_227 = {1'h0, ll_cumul_16}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_17_T = _GEN_227 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_17_T_1 = _ll_cumul_17_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_17_T_2 = _GEN_227 + {1'h0, ll_normalizedCounterReg_16}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_17_T_3 = _ll_cumul_17_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_17_T = {1'h0, ll_normCountEqsNegOneCumul_16} + {1'h0, ll_normCountEqsNegOne_17}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_17_T_1 = _ll_normCountEqsNegOneCumul_17_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_17 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_17_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_17 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_17)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_228 = {1'h0, ll_cumul_17}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_18_T = _GEN_228 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_18_T_1 = _ll_cumul_18_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_18_T_2 = _GEN_228 + {1'h0, ll_normalizedCounterReg_17}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_18_T_3 = _ll_cumul_18_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_18_T = {1'h0, ll_normCountEqsNegOneCumul_17} + {1'h0, ll_normCountEqsNegOne_18}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_18_T_1 = _ll_normCountEqsNegOneCumul_18_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_18 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_18_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_18 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_18)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_229 = {1'h0, ll_cumul_18}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_19_T = _GEN_229 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_19_T_1 = _ll_cumul_19_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_19_T_2 = _GEN_229 + {1'h0, ll_normalizedCounterReg_18}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_19_T_3 = _ll_cumul_19_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_19_T = {1'h0, ll_normCountEqsNegOneCumul_18} + {1'h0, ll_normCountEqsNegOne_19}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_19_T_1 = _ll_normCountEqsNegOneCumul_19_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_19 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_19_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_19 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_19)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_230 = {1'h0, ll_cumul_19}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_20_T = _GEN_230 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_20_T_1 = _ll_cumul_20_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_20_T_2 = _GEN_230 + {1'h0, ll_normalizedCounterReg_19}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_20_T_3 = _ll_cumul_20_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_20_T = {1'h0, ll_normCountEqsNegOneCumul_19} + {1'h0, ll_normCountEqsNegOne_20}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_20_T_1 = _ll_normCountEqsNegOneCumul_20_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_20 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_20_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_20 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_20)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_231 = {1'h0, ll_cumul_20}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_21_T = _GEN_231 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_21_T_1 = _ll_cumul_21_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_21_T_2 = _GEN_231 + {1'h0, ll_normalizedCounterReg_20}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_21_T_3 = _ll_cumul_21_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_21_T = {1'h0, ll_normCountEqsNegOneCumul_20} + {1'h0, ll_normCountEqsNegOne_21}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_21_T_1 = _ll_normCountEqsNegOneCumul_21_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_21 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_21_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_21 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_21)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_232 = {1'h0, ll_cumul_21}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_22_T = _GEN_232 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_22_T_1 = _ll_cumul_22_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_22_T_2 = _GEN_232 + {1'h0, ll_normalizedCounterReg_21}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_22_T_3 = _ll_cumul_22_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_22_T = {1'h0, ll_normCountEqsNegOneCumul_21} + {1'h0, ll_normCountEqsNegOne_22}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_22_T_1 = _ll_normCountEqsNegOneCumul_22_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_22 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_22_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_22 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_22)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_233 = {1'h0, ll_cumul_22}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_23_T = _GEN_233 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_23_T_1 = _ll_cumul_23_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_23_T_2 = _GEN_233 + {1'h0, ll_normalizedCounterReg_22}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_23_T_3 = _ll_cumul_23_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_23_T = {1'h0, ll_normCountEqsNegOneCumul_22} + {1'h0, ll_normCountEqsNegOne_23}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_23_T_1 = _ll_normCountEqsNegOneCumul_23_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_23 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_23_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_23 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_23)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_234 = {1'h0, ll_cumul_23}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_24_T = _GEN_234 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_24_T_1 = _ll_cumul_24_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_24_T_2 = _GEN_234 + {1'h0, ll_normalizedCounterReg_23}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_24_T_3 = _ll_cumul_24_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_24_T = {1'h0, ll_normCountEqsNegOneCumul_23} + {1'h0, ll_normCountEqsNegOne_24}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_24_T_1 = _ll_normCountEqsNegOneCumul_24_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_24 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_24_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_24 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_24)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_235 = {1'h0, ll_cumul_24}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_25_T = _GEN_235 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_25_T_1 = _ll_cumul_25_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_25_T_2 = _GEN_235 + {1'h0, ll_normalizedCounterReg_24}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_25_T_3 = _ll_cumul_25_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_25_T = {1'h0, ll_normCountEqsNegOneCumul_24} + {1'h0, ll_normCountEqsNegOne_25}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_25_T_1 = _ll_normCountEqsNegOneCumul_25_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_25 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_25_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_25 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_25)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_236 = {1'h0, ll_cumul_25}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_26_T = _GEN_236 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_26_T_1 = _ll_cumul_26_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_26_T_2 = _GEN_236 + {1'h0, ll_normalizedCounterReg_25}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_26_T_3 = _ll_cumul_26_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_26_T = {1'h0, ll_normCountEqsNegOneCumul_25} + {1'h0, ll_normCountEqsNegOne_26}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_26_T_1 = _ll_normCountEqsNegOneCumul_26_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_26 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_26_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_26 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_26)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_237 = {1'h0, ll_cumul_26}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_27_T = _GEN_237 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_27_T_1 = _ll_cumul_27_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_27_T_2 = _GEN_237 + {1'h0, ll_normalizedCounterReg_26}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_27_T_3 = _ll_cumul_27_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_27_T = {1'h0, ll_normCountEqsNegOneCumul_26} + {1'h0, ll_normCountEqsNegOne_27}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_27_T_1 = _ll_normCountEqsNegOneCumul_27_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_27 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_27_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_27 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_27)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_238 = {1'h0, ll_cumul_27}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_28_T = _GEN_238 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_28_T_1 = _ll_cumul_28_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_28_T_2 = _GEN_238 + {1'h0, ll_normalizedCounterReg_27}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_28_T_3 = _ll_cumul_28_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_28_T = {1'h0, ll_normCountEqsNegOneCumul_27} + {1'h0, ll_normCountEqsNegOne_28}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_28_T_1 = _ll_normCountEqsNegOneCumul_28_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_28 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_28_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_28 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_28)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_239 = {1'h0, ll_cumul_28}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_29_T = _GEN_239 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_29_T_1 = _ll_cumul_29_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_29_T_2 = _GEN_239 + {1'h0, ll_normalizedCounterReg_28}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_29_T_3 = _ll_cumul_29_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_29_T = {1'h0, ll_normCountEqsNegOneCumul_28} + {1'h0, ll_normCountEqsNegOne_29}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_29_T_1 = _ll_normCountEqsNegOneCumul_29_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_29 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_29_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_29 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_29)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_240 = {1'h0, ll_cumul_29}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_30_T = _GEN_240 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_30_T_1 = _ll_cumul_30_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_30_T_2 = _GEN_240 + {1'h0, ll_normalizedCounterReg_29}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_30_T_3 = _ll_cumul_30_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_30_T = {1'h0, ll_normCountEqsNegOneCumul_29} + {1'h0, ll_normCountEqsNegOne_30}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_30_T_1 = _ll_normCountEqsNegOneCumul_30_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_30 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_30_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_30 = _GEN_209 ? 8'h0 : {7'h0, _T_1371 & (&ll_normalizedCounterReg_30)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_241 = {1'h0, ll_cumul_30}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_31_T = _GEN_241 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_31_T_1 = _ll_cumul_31_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_31_T_2 = _GEN_241 + {1'h0, ll_normalizedCounterReg_30}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_31_T_3 = _ll_cumul_31_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_31_T = {1'h0, ll_normCountEqsNegOneCumul_30}; // @[FSECompressorDicBuilder.scala:389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_31_T_1 = _ll_normCountEqsNegOneCumul_31_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_31 = _GEN_210 ? 8'h0 : _ll_normCountEqsNegOneCumul_31_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_cumul_0 = _GEN_209 \| ~(_T_1371 & ll_maxSV1[4:0] == 5'h0) ? 16'h0 : 16'h41; // @[FSECompressorDicBuilder.scala:379:39, :382:26, :389:44, :551:28, :703:27] assign ll_cumul_1 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h1 ? 16'h41 : (&ll_normalizedCounterReg_0) ? _ll_cumul_1_T_1 : _ll_cumul_1_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_2 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h2 ? 16'h41 : (&ll_normalizedCounterReg_1) ? _ll_cumul_2_T_1 : _ll_cumul_2_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_3 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h3 ? 16'h41 : (&ll_normalizedCounterReg_2) ? _ll_cumul_3_T_1 : _ll_cumul_3_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_4 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h4 ? 16'h41 : (&ll_normalizedCounterReg_3) ? _ll_cumul_4_T_1 : _ll_cumul_4_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_5 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h5 ? 16'h41 : (&ll_normalizedCounterReg_4) ? _ll_cumul_5_T_1 : _ll_cumul_5_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_6 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h6 ? 16'h41 : (&ll_normalizedCounterReg_5) ? _ll_cumul_6_T_1 : _ll_cumul_6_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_7 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h7 ? 16'h41 : (&ll_normalizedCounterReg_6) ? _ll_cumul_7_T_1 : _ll_cumul_7_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_8 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h8 ? 16'h41 : (&ll_normalizedCounterReg_7) ? _ll_cumul_8_T_1 : _ll_cumul_8_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_9 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h9 ? 16'h41 : (&ll_normalizedCounterReg_8) ? _ll_cumul_9_T_1 : _ll_cumul_9_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_10 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'hA ? 16'h41 : (&ll_normalizedCounterReg_9) ? _ll_cumul_10_T_1 : _ll_cumul_10_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_11 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'hB ? 16'h41 : (&ll_normalizedCounterReg_10) ? _ll_cumul_11_T_1 : _ll_cumul_11_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_12 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'hC ? 16'h41 : (&ll_normalizedCounterReg_11) ? _ll_cumul_12_T_1 : _ll_cumul_12_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_13 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'hD ? 16'h41 : (&ll_normalizedCounterReg_12) ? _ll_cumul_13_T_1 : _ll_cumul_13_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_14 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'hE ? 16'h41 : (&ll_normalizedCounterReg_13) ? _ll_cumul_14_T_1 : _ll_cumul_14_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_15 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'hF ? 16'h41 : (&ll_normalizedCounterReg_14) ? _ll_cumul_15_T_1 : _ll_cumul_15_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_16 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h10 ? 16'h41 : (&ll_normalizedCounterReg_15) ? _ll_cumul_16_T_1 : _ll_cumul_16_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_17 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h11 ? 16'h41 : (&ll_normalizedCounterReg_16) ? _ll_cumul_17_T_1 : _ll_cumul_17_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_18 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h12 ? 16'h41 : (&ll_normalizedCounterReg_17) ? _ll_cumul_18_T_1 : _ll_cumul_18_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_19 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h13 ? 16'h41 : (&ll_normalizedCounterReg_18) ? _ll_cumul_19_T_1 : _ll_cumul_19_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_20 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h14 ? 16'h41 : (&ll_normalizedCounterReg_19) ? _ll_cumul_20_T_1 : _ll_cumul_20_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_21 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h15 ? 16'h41 : (&ll_normalizedCounterReg_20) ? _ll_cumul_21_T_1 : _ll_cumul_21_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_22 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h16 ? 16'h41 : (&ll_normalizedCounterReg_21) ? _ll_cumul_22_T_1 : _ll_cumul_22_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_23 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h17 ? 16'h41 : (&ll_normalizedCounterReg_22) ? _ll_cumul_23_T_1 : _ll_cumul_23_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_24 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h18 ? 16'h41 : (&ll_normalizedCounterReg_23) ? _ll_cumul_24_T_1 : _ll_cumul_24_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_25 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h19 ? 16'h41 : (&ll_normalizedCounterReg_24) ? _ll_cumul_25_T_1 : _ll_cumul_25_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_26 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h1A ? 16'h41 : (&ll_normalizedCounterReg_25) ? _ll_cumul_26_T_1 : _ll_cumul_26_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_27 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h1B ? 16'h41 : (&ll_normalizedCounterReg_26) ? _ll_cumul_27_T_1 : _ll_cumul_27_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_28 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h1C ? 16'h41 : (&ll_normalizedCounterReg_27) ? _ll_cumul_28_T_1 : _ll_cumul_28_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_29 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h1D ? 16'h41 : (&ll_normalizedCounterReg_28) ? _ll_cumul_29_T_1 : _ll_cumul_29_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_30 = _GEN_210 ? 16'h0 : ll_maxSV1[4:0] == 5'h1E ? 16'h41 : (&ll_normalizedCounterReg_29) ? _ll_cumul_30_T_1 : _ll_cumul_30_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_31 = _GEN_210 ? 16'h0 : (&(ll_maxSV1[4:0])) ? 16'h41 : (&ll_normalizedCounterReg_30) ? _ll_cumul_31_T_1 : _ll_cumul_31_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] wire [39:0] _ll_highThresholdAfterCumul_T = 40'h3F - {1'h0, ll_normCountEqsNegOneSum}; // @[FSECompressorDicBuilder.scala:390:65, :704:65] wire [38:0] _ll_highThresholdAfterCumul_T_1 = _ll_highThresholdAfterCumul_T[38:0]; // @[FSECompressorDicBuilder.scala:704:65] wire _T_1559 = dicBuilderState == 4'h4; // @[FSECompressorDicBuilder.scala:156:32, :551:28] wire [64:0] _GEN_242 = {1'h0, ll_s}; // @[FSECompressorDicBuilder.scala:403:21, :716:22] wire [64:0] _GEN_243 = _GEN_242 + 65'h1; // @[FSECompressorDicBuilder.scala:716:22] wire [64:0] _ll_s_T; // @[FSECompressorDicBuilder.scala:716:22] assign _ll_s_T = _GEN_243; // @[FSECompressorDicBuilder.scala:716:22] wire [64:0] _ll_s_T_2; // @[FSECompressorDicBuilder.scala:757:20] assign _ll_s_T_2 = _GEN_243; // @[FSECompressorDicBuilder.scala:716:22, :757:20] wire [64:0] _ll_s_T_4; // @[FSECompressorDicBuilder.scala:768:20] assign _ll_s_T_4 = _GEN_243; // @[FSECompressorDicBuilder.scala:716:22, :768:20] wire [63:0] _ll_s_T_1 = _ll_s_T[63:0]; // @[FSECompressorDicBuilder.scala:716:22] wire [64:0] _ll_sv_T = {1'h0, ll_sv} + 65'h101010101010101; // @[FSECompressorDicBuilder.scala:404:22, :717:24] wire [63:0] _ll_sv_T_1 = _ll_sv_T[63:0]; // @[FSECompressorDicBuilder.scala:717:24] wire [15:0] write_spread_cnt = {3'h0, _GEN_199[_n_T][15:3]}; // @[FSECompressorDicBuilder.scala:416:13, :719:34] wire [15:0] _write_extra_T = {13'h0, _GEN_199[_n_T][2:0]}; // @[FSECompressorDicBuilder.scala:416:13, :719:34, :720:30] wire write_extra = \|_write_extra_T; // @[FSECompressorDicBuilder.scala:720:{30,37}] wire [16:0] write_spread_cnt_wrapped = {1'h0, write_spread_cnt} + {16'h0, write_extra}; // @[FSECompressorDicBuilder.scala:719:34, :720:37, :721:57] wire [19:0] write_spread_bytes = {write_spread_cnt_wrapped, 3'h0}; // @[FSECompressorDicBuilder.scala:721:57, :722:59] wire [64:0] _GEN_244 = {1'h0, ll_pos}; // @[FSECompressorDicBuilder.scala:402:23, :723:26] wire [64:0] _ll_pos_T = _GEN_244 + {49'h0, _GEN_199[_n_T]}; // @[FSECompressorDicBuilder.scala:416:13, :719:34, :723:26] wire [63:0] _ll_pos_T_1 = _ll_pos_T[63:0]; // @[FSECompressorDicBuilder.scala:723:26] wire [64:0] _GEN_245 = 65'h0 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T = _GEN_245; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_144; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_144 = _GEN_245; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_1 = _shift_bytes_T[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes = _shift_bytes_T_1[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits = {shift_bytes, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_0_T = ll_sv >> shift_bits; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_246 = 65'h1 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_2; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_2 = _GEN_246; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_146; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_146 = _GEN_246; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_3 = _shift_bytes_T_2[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_1 = _shift_bytes_T_3[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_1 = {shift_bytes_1, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_1_T = ll_sv >> shift_bits_1; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_247 = 65'h2 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_4; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_4 = _GEN_247; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_148; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_148 = _GEN_247; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_5 = _shift_bytes_T_4[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_2 = _shift_bytes_T_5[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_2 = {shift_bytes_2, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_2_T = ll_sv >> shift_bits_2; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_248 = 65'h3 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_6; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_6 = _GEN_248; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_150; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_150 = _GEN_248; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_7 = _shift_bytes_T_6[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_3 = _shift_bytes_T_7[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_3 = {shift_bytes_3, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_3_T = ll_sv >> shift_bits_3; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_249 = 65'h4 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_8; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_8 = _GEN_249; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_152; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_152 = _GEN_249; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_9 = _shift_bytes_T_8[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_4 = _shift_bytes_T_9[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_4 = {shift_bytes_4, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_4_T = ll_sv >> shift_bits_4; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_250 = 65'h5 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_10; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_10 = _GEN_250; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_154; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_154 = _GEN_250; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_11 = _shift_bytes_T_10[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_5 = _shift_bytes_T_11[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_5 = {shift_bytes_5, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_5_T = ll_sv >> shift_bits_5; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_251 = 65'h6 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_12; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_12 = _GEN_251; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_156; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_156 = _GEN_251; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_13 = _shift_bytes_T_12[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_6 = _shift_bytes_T_13[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_6 = {shift_bytes_6, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_6_T = ll_sv >> shift_bits_6; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_252 = 65'h7 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_14; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_14 = _GEN_252; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_158; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_158 = _GEN_252; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_15 = _shift_bytes_T_14[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_7 = _shift_bytes_T_15[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_7 = {shift_bytes_7, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_7_T = ll_sv >> shift_bits_7; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_253 = 65'h8 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_16; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_16 = _GEN_253; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_160; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_160 = _GEN_253; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_17 = _shift_bytes_T_16[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_8 = _shift_bytes_T_17[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_8 = {shift_bytes_8, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_8_T = ll_sv >> shift_bits_8; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_254 = 65'h9 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_18; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_18 = _GEN_254; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_162; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_162 = _GEN_254; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_19 = _shift_bytes_T_18[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_9 = _shift_bytes_T_19[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_9 = {shift_bytes_9, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_9_T = ll_sv >> shift_bits_9; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_255 = 65'hA - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_20; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_20 = _GEN_255; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_164; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_164 = _GEN_255; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_21 = _shift_bytes_T_20[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_10 = _shift_bytes_T_21[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_10 = {shift_bytes_10, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_10_T = ll_sv >> shift_bits_10; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_256 = 65'hB - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_22; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_22 = _GEN_256; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_166; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_166 = _GEN_256; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_23 = _shift_bytes_T_22[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_11 = _shift_bytes_T_23[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_11 = {shift_bytes_11, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_11_T = ll_sv >> shift_bits_11; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_257 = 65'hC - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_24; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_24 = _GEN_257; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_168; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_168 = _GEN_257; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_25 = _shift_bytes_T_24[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_12 = _shift_bytes_T_25[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_12 = {shift_bytes_12, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_12_T = ll_sv >> shift_bits_12; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_258 = 65'hD - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_26; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_26 = _GEN_258; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_170; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_170 = _GEN_258; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_27 = _shift_bytes_T_26[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_13 = _shift_bytes_T_27[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_13 = {shift_bytes_13, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_13_T = ll_sv >> shift_bits_13; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_259 = 65'hE - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_28; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_28 = _GEN_259; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_172; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_172 = _GEN_259; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_29 = _shift_bytes_T_28[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_14 = _shift_bytes_T_29[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_14 = {shift_bytes_14, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_14_T = ll_sv >> shift_bits_14; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_260 = 65'hF - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_30; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_30 = _GEN_260; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_174; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_174 = _GEN_260; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_31 = _shift_bytes_T_30[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_15 = _shift_bytes_T_31[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_15 = {shift_bytes_15, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_15_T = ll_sv >> shift_bits_15; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_261 = 65'h10 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_32; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_32 = _GEN_261; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_176; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_176 = _GEN_261; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_33 = _shift_bytes_T_32[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_16 = _shift_bytes_T_33[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_16 = {shift_bytes_16, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_16_T = ll_sv >> shift_bits_16; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_262 = 65'h11 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_34; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_34 = _GEN_262; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_178; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_178 = _GEN_262; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_35 = _shift_bytes_T_34[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_17 = _shift_bytes_T_35[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_17 = {shift_bytes_17, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_17_T = ll_sv >> shift_bits_17; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_263 = 65'h12 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_36; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_36 = _GEN_263; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_180; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_180 = _GEN_263; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_37 = _shift_bytes_T_36[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_18 = _shift_bytes_T_37[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_18 = {shift_bytes_18, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_18_T = ll_sv >> shift_bits_18; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_264 = 65'h13 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_38; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_38 = _GEN_264; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_182; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_182 = _GEN_264; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_39 = _shift_bytes_T_38[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_19 = _shift_bytes_T_39[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_19 = {shift_bytes_19, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_19_T = ll_sv >> shift_bits_19; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_265 = 65'h14 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_40; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_40 = _GEN_265; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_184; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_184 = _GEN_265; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_41 = _shift_bytes_T_40[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_20 = _shift_bytes_T_41[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_20 = {shift_bytes_20, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_20_T = ll_sv >> shift_bits_20; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_266 = 65'h15 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_42; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_42 = _GEN_266; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_186; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_186 = _GEN_266; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_43 = _shift_bytes_T_42[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_21 = _shift_bytes_T_43[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_21 = {shift_bytes_21, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_21_T = ll_sv >> shift_bits_21; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_267 = 65'h16 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_44; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_44 = _GEN_267; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_188; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_188 = _GEN_267; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_45 = _shift_bytes_T_44[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_22 = _shift_bytes_T_45[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_22 = {shift_bytes_22, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_22_T = ll_sv >> shift_bits_22; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_268 = 65'h17 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_46; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_46 = _GEN_268; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_190; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_190 = _GEN_268; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_47 = _shift_bytes_T_46[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_23 = _shift_bytes_T_47[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_23 = {shift_bytes_23, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_23_T = ll_sv >> shift_bits_23; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_269 = 65'h18 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_48; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_48 = _GEN_269; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_192; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_192 = _GEN_269; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_49 = _shift_bytes_T_48[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_24 = _shift_bytes_T_49[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_24 = {shift_bytes_24, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_24_T = ll_sv >> shift_bits_24; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_270 = 65'h19 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_50; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_50 = _GEN_270; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_194; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_194 = _GEN_270; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_51 = _shift_bytes_T_50[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_25 = _shift_bytes_T_51[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_25 = {shift_bytes_25, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_25_T = ll_sv >> shift_bits_25; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_271 = 65'h1A - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_52; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_52 = _GEN_271; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_196; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_196 = _GEN_271; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_53 = _shift_bytes_T_52[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_26 = _shift_bytes_T_53[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_26 = {shift_bytes_26, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_26_T = ll_sv >> shift_bits_26; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_272 = 65'h1B - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_54; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_54 = _GEN_272; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_198; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_198 = _GEN_272; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_55 = _shift_bytes_T_54[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_27 = _shift_bytes_T_55[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_27 = {shift_bytes_27, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_27_T = ll_sv >> shift_bits_27; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_273 = 65'h1C - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_56; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_56 = _GEN_273; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_200; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_200 = _GEN_273; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_57 = _shift_bytes_T_56[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_28 = _shift_bytes_T_57[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_28 = {shift_bytes_28, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_28_T = ll_sv >> shift_bits_28; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_274 = 65'h1D - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_58; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_58 = _GEN_274; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_202; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_202 = _GEN_274; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_59 = _shift_bytes_T_58[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_29 = _shift_bytes_T_59[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_29 = {shift_bytes_29, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_29_T = ll_sv >> shift_bits_29; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_275 = 65'h1E - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_60; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_60 = _GEN_275; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_204; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_204 = _GEN_275; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_61 = _shift_bytes_T_60[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_30 = _shift_bytes_T_61[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_30 = {shift_bytes_30, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_30_T = ll_sv >> shift_bits_30; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_276 = 65'h1F - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_62; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_62 = _GEN_276; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_206; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_206 = _GEN_276; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_63 = _shift_bytes_T_62[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_31 = _shift_bytes_T_63[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_31 = {shift_bytes_31, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_31_T = ll_sv >> shift_bits_31; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_277 = 65'h20 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_64; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_64 = _GEN_277; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_208; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_208 = _GEN_277; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_65 = _shift_bytes_T_64[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_32 = _shift_bytes_T_65[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_32 = {shift_bytes_32, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_32_T = ll_sv >> shift_bits_32; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_278 = 65'h21 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_66; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_66 = _GEN_278; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_210; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_210 = _GEN_278; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_67 = _shift_bytes_T_66[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_33 = _shift_bytes_T_67[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_33 = {shift_bytes_33, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_33_T = ll_sv >> shift_bits_33; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_279 = 65'h22 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_68; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_68 = _GEN_279; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_212; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_212 = _GEN_279; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_69 = _shift_bytes_T_68[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_34 = _shift_bytes_T_69[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_34 = {shift_bytes_34, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_34_T = ll_sv >> shift_bits_34; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_280 = 65'h23 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_70; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_70 = _GEN_280; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_214; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_214 = _GEN_280; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_71 = _shift_bytes_T_70[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_35 = _shift_bytes_T_71[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_35 = {shift_bytes_35, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_35_T = ll_sv >> shift_bits_35; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_281 = 65'h24 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_72; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_72 = _GEN_281; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_216; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_216 = _GEN_281; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_73 = _shift_bytes_T_72[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_36 = _shift_bytes_T_73[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_36 = {shift_bytes_36, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_36_T = ll_sv >> shift_bits_36; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_282 = 65'h25 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_74; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_74 = _GEN_282; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_218; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_218 = _GEN_282; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_75 = _shift_bytes_T_74[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_37 = _shift_bytes_T_75[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_37 = {shift_bytes_37, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_37_T = ll_sv >> shift_bits_37; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_283 = 65'h26 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_76; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_76 = _GEN_283; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_220; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_220 = _GEN_283; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_77 = _shift_bytes_T_76[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_38 = _shift_bytes_T_77[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_38 = {shift_bytes_38, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_38_T = ll_sv >> shift_bits_38; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_284 = 65'h27 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_78; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_78 = _GEN_284; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_222; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_222 = _GEN_284; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_79 = _shift_bytes_T_78[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_39 = _shift_bytes_T_79[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_39 = {shift_bytes_39, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_39_T = ll_sv >> shift_bits_39; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_285 = 65'h28 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_80; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_80 = _GEN_285; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_224; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_224 = _GEN_285; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_81 = _shift_bytes_T_80[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_40 = _shift_bytes_T_81[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_40 = {shift_bytes_40, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_40_T = ll_sv >> shift_bits_40; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_286 = 65'h29 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_82; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_82 = _GEN_286; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_226; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_226 = _GEN_286; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_83 = _shift_bytes_T_82[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_41 = _shift_bytes_T_83[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_41 = {shift_bytes_41, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_41_T = ll_sv >> shift_bits_41; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_287 = 65'h2A - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_84; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_84 = _GEN_287; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_228; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_228 = _GEN_287; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_85 = _shift_bytes_T_84[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_42 = _shift_bytes_T_85[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_42 = {shift_bytes_42, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_42_T = ll_sv >> shift_bits_42; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_288 = 65'h2B - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_86; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_86 = _GEN_288; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_230; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_230 = _GEN_288; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_87 = _shift_bytes_T_86[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_43 = _shift_bytes_T_87[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_43 = {shift_bytes_43, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_43_T = ll_sv >> shift_bits_43; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_289 = 65'h2C - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_88; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_88 = _GEN_289; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_232; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_232 = _GEN_289; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_89 = _shift_bytes_T_88[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_44 = _shift_bytes_T_89[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_44 = {shift_bytes_44, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_44_T = ll_sv >> shift_bits_44; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_290 = 65'h2D - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_90; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_90 = _GEN_290; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_234; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_234 = _GEN_290; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_91 = _shift_bytes_T_90[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_45 = _shift_bytes_T_91[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_45 = {shift_bytes_45, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_45_T = ll_sv >> shift_bits_45; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_291 = 65'h2E - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_92; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_92 = _GEN_291; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_236; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_236 = _GEN_291; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_93 = _shift_bytes_T_92[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_46 = _shift_bytes_T_93[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_46 = {shift_bytes_46, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_46_T = ll_sv >> shift_bits_46; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_292 = 65'h2F - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_94; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_94 = _GEN_292; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_238; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_238 = _GEN_292; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_95 = _shift_bytes_T_94[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_47 = _shift_bytes_T_95[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_47 = {shift_bytes_47, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_47_T = ll_sv >> shift_bits_47; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_293 = 65'h30 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_96; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_96 = _GEN_293; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_240; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_240 = _GEN_293; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_97 = _shift_bytes_T_96[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_48 = _shift_bytes_T_97[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_48 = {shift_bytes_48, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_48_T = ll_sv >> shift_bits_48; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_294 = 65'h31 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_98; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_98 = _GEN_294; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_242; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_242 = _GEN_294; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_99 = _shift_bytes_T_98[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_49 = _shift_bytes_T_99[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_49 = {shift_bytes_49, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_49_T = ll_sv >> shift_bits_49; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_295 = 65'h32 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_100; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_100 = _GEN_295; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_244; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_244 = _GEN_295; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_101 = _shift_bytes_T_100[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_50 = _shift_bytes_T_101[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_50 = {shift_bytes_50, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_50_T = ll_sv >> shift_bits_50; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_296 = 65'h33 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_102; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_102 = _GEN_296; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_246; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_246 = _GEN_296; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_103 = _shift_bytes_T_102[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_51 = _shift_bytes_T_103[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_51 = {shift_bytes_51, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_51_T = ll_sv >> shift_bits_51; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_297 = 65'h34 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_104; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_104 = _GEN_297; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_248; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_248 = _GEN_297; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_105 = _shift_bytes_T_104[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_52 = _shift_bytes_T_105[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_52 = {shift_bytes_52, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_52_T = ll_sv >> shift_bits_52; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_298 = 65'h35 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_106; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_106 = _GEN_298; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_250; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_250 = _GEN_298; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_107 = _shift_bytes_T_106[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_53 = _shift_bytes_T_107[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_53 = {shift_bytes_53, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_53_T = ll_sv >> shift_bits_53; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_299 = 65'h36 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_108; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_108 = _GEN_299; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_252; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_252 = _GEN_299; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_109 = _shift_bytes_T_108[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_54 = _shift_bytes_T_109[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_54 = {shift_bytes_54, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_54_T = ll_sv >> shift_bits_54; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_300 = 65'h37 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_110; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_110 = _GEN_300; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_254; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_254 = _GEN_300; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_111 = _shift_bytes_T_110[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_55 = _shift_bytes_T_111[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_55 = {shift_bytes_55, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_55_T = ll_sv >> shift_bits_55; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_301 = 65'h38 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_112; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_112 = _GEN_301; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_256; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_256 = _GEN_301; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_113 = _shift_bytes_T_112[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_56 = _shift_bytes_T_113[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_56 = {shift_bytes_56, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_56_T = ll_sv >> shift_bits_56; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_302 = 65'h39 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_114; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_114 = _GEN_302; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_258; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_258 = _GEN_302; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_115 = _shift_bytes_T_114[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_57 = _shift_bytes_T_115[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_57 = {shift_bytes_57, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_57_T = ll_sv >> shift_bits_57; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_303 = 65'h3A - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_116; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_116 = _GEN_303; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_260; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_260 = _GEN_303; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_117 = _shift_bytes_T_116[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_58 = _shift_bytes_T_117[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_58 = {shift_bytes_58, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_58_T = ll_sv >> shift_bits_58; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_304 = 65'h3B - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_118; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_118 = _GEN_304; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_262; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_262 = _GEN_304; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_119 = _shift_bytes_T_118[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_59 = _shift_bytes_T_119[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_59 = {shift_bytes_59, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_59_T = ll_sv >> shift_bits_59; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_305 = 65'h3C - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_120; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_120 = _GEN_305; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_264; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_264 = _GEN_305; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_121 = _shift_bytes_T_120[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_60 = _shift_bytes_T_121[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_60 = {shift_bytes_60, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_60_T = ll_sv >> shift_bits_60; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_306 = 65'h3D - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_122; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_122 = _GEN_306; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_266; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_266 = _GEN_306; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_123 = _shift_bytes_T_122[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_61 = _shift_bytes_T_123[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_61 = {shift_bytes_61, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_61_T = ll_sv >> shift_bits_61; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_307 = 65'h3E - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_124; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_124 = _GEN_307; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_268; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_268 = _GEN_307; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_125 = _shift_bytes_T_124[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_62 = _shift_bytes_T_125[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_62 = {shift_bytes_62, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_62_T = ll_sv >> shift_bits_62; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_308 = 65'h3F - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_126; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_126 = _GEN_308; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_270; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_270 = _GEN_308; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_127 = _shift_bytes_T_126[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_63 = _shift_bytes_T_127[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_63 = {shift_bytes_63, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_63_T = ll_sv >> shift_bits_63; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_128 = 65'h40 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_129 = _shift_bytes_T_128[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_64 = _shift_bytes_T_129[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_64 = {shift_bytes_64, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_64_T = ll_sv >> shift_bits_64; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_130 = 65'h41 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_131 = _shift_bytes_T_130[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_65 = _shift_bytes_T_131[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_65 = {shift_bytes_65, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_65_T = ll_sv >> shift_bits_65; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_132 = 65'h42 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_133 = _shift_bytes_T_132[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_66 = _shift_bytes_T_133[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_66 = {shift_bytes_66, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_66_T = ll_sv >> shift_bits_66; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_134 = 65'h43 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_135 = _shift_bytes_T_134[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_67 = _shift_bytes_T_135[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_67 = {shift_bytes_67, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_67_T = ll_sv >> shift_bits_67; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_136 = 65'h44 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_137 = _shift_bytes_T_136[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_68 = _shift_bytes_T_137[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_68 = {shift_bytes_68, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_68_T = ll_sv >> shift_bits_68; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_138 = 65'h45 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_139 = _shift_bytes_T_138[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_69 = _shift_bytes_T_139[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_69 = {shift_bytes_69, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_69_T = ll_sv >> shift_bits_69; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_140 = 65'h46 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_141 = _shift_bytes_T_140[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_70 = _shift_bytes_T_141[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_70 = {shift_bytes_70, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_70_T = ll_sv >> shift_bits_70; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_142 = 65'h47 - _GEN_244; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_143 = _shift_bytes_T_142[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_71 = _shift_bytes_T_143[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_71 = {shift_bytes_71, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_71_T = ll_sv >> shift_bits_71; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [63:0] _shift_bytes_T_145 = _shift_bytes_T_144[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_72 = _shift_bytes_T_145[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_72 = {shift_bytes_72, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T = ll_sv >> shift_bits_72; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_147 = _shift_bytes_T_146[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_73 = _shift_bytes_T_147[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_73 = {shift_bytes_73, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_1 = ll_sv >> shift_bits_73; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_149 = _shift_bytes_T_148[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_74 = _shift_bytes_T_149[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_74 = {shift_bytes_74, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_2 = ll_sv >> shift_bits_74; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_151 = _shift_bytes_T_150[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_75 = _shift_bytes_T_151[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_75 = {shift_bytes_75, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_3 = ll_sv >> shift_bits_75; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_153 = _shift_bytes_T_152[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_76 = _shift_bytes_T_153[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_76 = {shift_bytes_76, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_4 = ll_sv >> shift_bits_76; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_155 = _shift_bytes_T_154[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_77 = _shift_bytes_T_155[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_77 = {shift_bytes_77, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_5 = ll_sv >> shift_bits_77; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_157 = _shift_bytes_T_156[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_78 = _shift_bytes_T_157[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_78 = {shift_bytes_78, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_6 = ll_sv >> shift_bits_78; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_159 = _shift_bytes_T_158[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_79 = _shift_bytes_T_159[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_79 = {shift_bytes_79, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_7 = ll_sv >> shift_bits_79; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_161 = _shift_bytes_T_160[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_80 = _shift_bytes_T_161[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_80 = {shift_bytes_80, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_8 = ll_sv >> shift_bits_80; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_163 = _shift_bytes_T_162[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_81 = _shift_bytes_T_163[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_81 = {shift_bytes_81, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_9 = ll_sv >> shift_bits_81; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_165 = _shift_bytes_T_164[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_82 = _shift_bytes_T_165[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_82 = {shift_bytes_82, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_10 = ll_sv >> shift_bits_82; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_167 = _shift_bytes_T_166[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_83 = _shift_bytes_T_167[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_83 = {shift_bytes_83, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_11 = ll_sv >> shift_bits_83; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_169 = _shift_bytes_T_168[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_84 = _shift_bytes_T_169[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_84 = {shift_bytes_84, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_12 = ll_sv >> shift_bits_84; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_171 = _shift_bytes_T_170[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_85 = _shift_bytes_T_171[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_85 = {shift_bytes_85, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_13 = ll_sv >> shift_bits_85; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_173 = _shift_bytes_T_172[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_86 = _shift_bytes_T_173[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_86 = {shift_bytes_86, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_14 = ll_sv >> shift_bits_86; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_175 = _shift_bytes_T_174[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_87 = _shift_bytes_T_175[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_87 = {shift_bytes_87, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_15 = ll_sv >> shift_bits_87; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_177 = _shift_bytes_T_176[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_88 = _shift_bytes_T_177[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_88 = {shift_bytes_88, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_16 = ll_sv >> shift_bits_88; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_179 = _shift_bytes_T_178[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_89 = _shift_bytes_T_179[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_89 = {shift_bytes_89, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_17 = ll_sv >> shift_bits_89; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_181 = _shift_bytes_T_180[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_90 = _shift_bytes_T_181[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_90 = {shift_bytes_90, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_18 = ll_sv >> shift_bits_90; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_183 = _shift_bytes_T_182[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_91 = _shift_bytes_T_183[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_91 = {shift_bytes_91, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_19 = ll_sv >> shift_bits_91; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_185 = _shift_bytes_T_184[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_92 = _shift_bytes_T_185[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_92 = {shift_bytes_92, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_20 = ll_sv >> shift_bits_92; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_187 = _shift_bytes_T_186[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_93 = _shift_bytes_T_187[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_93 = {shift_bytes_93, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_21 = ll_sv >> shift_bits_93; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_189 = _shift_bytes_T_188[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_94 = _shift_bytes_T_189[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_94 = {shift_bytes_94, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_22 = ll_sv >> shift_bits_94; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_191 = _shift_bytes_T_190[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_95 = _shift_bytes_T_191[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_95 = {shift_bytes_95, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_23 = ll_sv >> shift_bits_95; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_193 = _shift_bytes_T_192[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_96 = _shift_bytes_T_193[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_96 = {shift_bytes_96, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_24 = ll_sv >> shift_bits_96; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_195 = _shift_bytes_T_194[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_97 = _shift_bytes_T_195[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_97 = {shift_bytes_97, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_25 = ll_sv >> shift_bits_97; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_197 = _shift_bytes_T_196[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_98 = _shift_bytes_T_197[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_98 = {shift_bytes_98, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_26 = ll_sv >> shift_bits_98; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_199 = _shift_bytes_T_198[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_99 = _shift_bytes_T_199[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_99 = {shift_bytes_99, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_27 = ll_sv >> shift_bits_99; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_201 = _shift_bytes_T_200[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_100 = _shift_bytes_T_201[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_100 = {shift_bytes_100, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_28 = ll_sv >> shift_bits_100; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_203 = _shift_bytes_T_202[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_101 = _shift_bytes_T_203[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_101 = {shift_bytes_101, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_29 = ll_sv >> shift_bits_101; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_205 = _shift_bytes_T_204[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_102 = _shift_bytes_T_205[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_102 = {shift_bytes_102, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_30 = ll_sv >> shift_bits_102; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_207 = _shift_bytes_T_206[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_103 = _shift_bytes_T_207[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_103 = {shift_bytes_103, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_31 = ll_sv >> shift_bits_103; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_209 = _shift_bytes_T_208[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_104 = _shift_bytes_T_209[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_104 = {shift_bytes_104, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_32 = ll_sv >> shift_bits_104; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_211 = _shift_bytes_T_210[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_105 = _shift_bytes_T_211[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_105 = {shift_bytes_105, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_33 = ll_sv >> shift_bits_105; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_213 = _shift_bytes_T_212[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_106 = _shift_bytes_T_213[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_106 = {shift_bytes_106, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_34 = ll_sv >> shift_bits_106; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_215 = _shift_bytes_T_214[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_107 = _shift_bytes_T_215[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_107 = {shift_bytes_107, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_35 = ll_sv >> shift_bits_107; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_217 = _shift_bytes_T_216[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_108 = _shift_bytes_T_217[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_108 = {shift_bytes_108, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_36 = ll_sv >> shift_bits_108; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_219 = _shift_bytes_T_218[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_109 = _shift_bytes_T_219[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_109 = {shift_bytes_109, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_37 = ll_sv >> shift_bits_109; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_221 = _shift_bytes_T_220[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_110 = _shift_bytes_T_221[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_110 = {shift_bytes_110, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_38 = ll_sv >> shift_bits_110; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_223 = _shift_bytes_T_222[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_111 = _shift_bytes_T_223[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_111 = {shift_bytes_111, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_39 = ll_sv >> shift_bits_111; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_225 = _shift_bytes_T_224[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_112 = _shift_bytes_T_225[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_112 = {shift_bytes_112, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_40 = ll_sv >> shift_bits_112; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_227 = _shift_bytes_T_226[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_113 = _shift_bytes_T_227[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_113 = {shift_bytes_113, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_41 = ll_sv >> shift_bits_113; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_229 = _shift_bytes_T_228[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_114 = _shift_bytes_T_229[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_114 = {shift_bytes_114, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_42 = ll_sv >> shift_bits_114; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_231 = _shift_bytes_T_230[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_115 = _shift_bytes_T_231[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_115 = {shift_bytes_115, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_43 = ll_sv >> shift_bits_115; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_233 = _shift_bytes_T_232[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_116 = _shift_bytes_T_233[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_116 = {shift_bytes_116, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_44 = ll_sv >> shift_bits_116; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_235 = _shift_bytes_T_234[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_117 = _shift_bytes_T_235[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_117 = {shift_bytes_117, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_45 = ll_sv >> shift_bits_117; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_237 = _shift_bytes_T_236[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_118 = _shift_bytes_T_237[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_118 = {shift_bytes_118, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_46 = ll_sv >> shift_bits_118; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_239 = _shift_bytes_T_238[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_119 = _shift_bytes_T_239[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_119 = {shift_bytes_119, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_47 = ll_sv >> shift_bits_119; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_241 = _shift_bytes_T_240[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_120 = _shift_bytes_T_241[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_120 = {shift_bytes_120, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_48 = ll_sv >> shift_bits_120; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_243 = _shift_bytes_T_242[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_121 = _shift_bytes_T_243[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_121 = {shift_bytes_121, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_49 = ll_sv >> shift_bits_121; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_245 = _shift_bytes_T_244[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_122 = _shift_bytes_T_245[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_122 = {shift_bytes_122, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_50 = ll_sv >> shift_bits_122; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_247 = _shift_bytes_T_246[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_123 = _shift_bytes_T_247[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_123 = {shift_bytes_123, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_51 = ll_sv >> shift_bits_123; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_249 = _shift_bytes_T_248[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_124 = _shift_bytes_T_249[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_124 = {shift_bytes_124, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_52 = ll_sv >> shift_bits_124; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_251 = _shift_bytes_T_250[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_125 = _shift_bytes_T_251[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_125 = {shift_bytes_125, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_53 = ll_sv >> shift_bits_125; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_253 = _shift_bytes_T_252[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_126 = _shift_bytes_T_253[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_126 = {shift_bytes_126, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_54 = ll_sv >> shift_bits_126; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_255 = _shift_bytes_T_254[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_127 = _shift_bytes_T_255[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_127 = {shift_bytes_127, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_55 = ll_sv >> shift_bits_127; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_257 = _shift_bytes_T_256[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_128 = _shift_bytes_T_257[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_128 = {shift_bytes_128, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_56 = ll_sv >> shift_bits_128; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_259 = _shift_bytes_T_258[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_129 = _shift_bytes_T_259[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_129 = {shift_bytes_129, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_57 = ll_sv >> shift_bits_129; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_261 = _shift_bytes_T_260[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_130 = _shift_bytes_T_261[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_130 = {shift_bytes_130, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_58 = ll_sv >> shift_bits_130; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_263 = _shift_bytes_T_262[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_131 = _shift_bytes_T_263[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_131 = {shift_bytes_131, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_59 = ll_sv >> shift_bits_131; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_265 = _shift_bytes_T_264[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_132 = _shift_bytes_T_265[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_132 = {shift_bytes_132, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_60 = ll_sv >> shift_bits_132; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_267 = _shift_bytes_T_266[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_133 = _shift_bytes_T_267[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_133 = {shift_bytes_133, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_61 = ll_sv >> shift_bits_133; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_269 = _shift_bytes_T_268[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_134 = _shift_bytes_T_269[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_134 = {shift_bytes_134, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_62 = ll_sv >> shift_bits_134; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_271 = _shift_bytes_T_270[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_135 = _shift_bytes_T_271[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_135 = {shift_bytes_135, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_63 = ll_sv >> shift_bits_135; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] reg [63:0] loginfo_cycles_338; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_676 = {1'h0, loginfo_cycles_338} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_677 = _loginfo_cycles_T_676[63:0]; // @[Util.scala:19:38] wire _T_2379 = dicBuilderState == 4'h5; // @[FSECompressorDicBuilder.scala:156:32, :551:28] wire [63:0] _ll_s_T_3 = _ll_s_T_2[63:0]; // @[FSECompressorDicBuilder.scala:757:20] wire [5:0] _s_T = ll_s[5:0]; // @[FSECompressorDicBuilder.scala:403:21] wire [63:0][7:0] _GEN_309 = {{ll_tableSymbol_63}, {ll_tableSymbol_62}, {ll_tableSymbol_61}, {ll_tableSymbol_60}, {ll_tableSymbol_59}, {ll_tableSymbol_58}, {ll_tableSymbol_57}, {ll_tableSymbol_56}, {ll_tableSymbol_55}, {ll_tableSymbol_54}, {ll_tableSymbol_53}, {ll_tableSymbol_52}, {ll_tableSymbol_51}, {ll_tableSymbol_50}, {ll_tableSymbol_49}, {ll_tableSymbol_48}, {ll_tableSymbol_47}, {ll_tableSymbol_46}, {ll_tableSymbol_45}, {ll_tableSymbol_44}, {ll_tableSymbol_43}, {ll_tableSymbol_42}, {ll_tableSymbol_41}, {ll_tableSymbol_40}, {ll_tableSymbol_39}, {ll_tableSymbol_38}, {ll_tableSymbol_37}, {ll_tableSymbol_36}, {ll_tableSymbol_35}, {ll_tableSymbol_34}, {ll_tableSymbol_33}, {ll_tableSymbol_32}, {ll_tableSymbol_31}, {ll_tableSymbol_30}, {ll_tableSymbol_29}, {ll_tableSymbol_28}, {ll_tableSymbol_27}, {ll_tableSymbol_26}, {ll_tableSymbol_25}, {ll_tableSymbol_24}, {ll_tableSymbol_23}, {ll_tableSymbol_22}, {ll_tableSymbol_21}, {ll_tableSymbol_20}, {ll_tableSymbol_19}, {ll_tableSymbol_18}, {ll_tableSymbol_17}, {ll_tableSymbol_16}, {ll_tableSymbol_15}, {ll_tableSymbol_14}, {ll_tableSymbol_13}, {ll_tableSymbol_12}, {ll_tableSymbol_11}, {ll_tableSymbol_10}, {ll_tableSymbol_9}, {ll_tableSymbol_8}, {ll_tableSymbol_7}, {ll_tableSymbol_6}, {ll_tableSymbol_5}, {ll_tableSymbol_4}, {ll_tableSymbol_3}, {ll_tableSymbol_2}, {ll_tableSymbol_1}, {ll_tableSymbol_0}}; // @[FSECompressorDicBuilder.scala:383:31] wire [4:0] _ll_cumulReg_T = _GEN_309[_s_T][4:0]; wire [31:0][15:0] _GEN_310 = {{ll_cumulReg_31}, {ll_cumulReg_30}, {ll_cumulReg_29}, {ll_cumulReg_28}, {ll_cumulReg_27}, {ll_cumulReg_26}, {ll_cumulReg_25}, {ll_cumulReg_24}, {ll_cumulReg_23}, {ll_cumulReg_22}, {ll_cumulReg_21}, {ll_cumulReg_20}, {ll_cumulReg_19}, {ll_cumulReg_18}, {ll_cumulReg_17}, {ll_cumulReg_16}, {ll_cumulReg_15}, {ll_cumulReg_14}, {ll_cumulReg_13}, {ll_cumulReg_12}, {ll_cumulReg_11}, {ll_cumulReg_10}, {ll_cumulReg_9}, {ll_cumulReg_8}, {ll_cumulReg_7}, {ll_cumulReg_6}, {ll_cumulReg_5}, {ll_cumulReg_4}, {ll_cumulReg_3}, {ll_cumulReg_2}, {ll_cumulReg_1}, {ll_cumulReg_0}}; // @[FSECompressorDicBuilder.scala:394:28, :759:40] wire [16:0] _ll_cumulReg_T_1 = {1'h0, _GEN_310[_ll_cumulReg_T]} + 17'h1; // @[FSECompressorDicBuilder.scala:759:40] wire [15:0] _ll_cumulReg_T_2 = _ll_cumulReg_T_1[15:0]; // @[FSECompressorDicBuilder.scala:759:40] wire [64:0] _ll_tableU16_T = _GEN_242 + 65'h40; // @[FSECompressorDicBuilder.scala:716:22, :760:51] wire [63:0] _ll_tableU16_T_1 = _ll_tableU16_T[63:0]; // @[FSECompressorDicBuilder.scala:760:51] wire _T_2386 = dicBuilderState == 4'h6; // @[FSECompressorDicBuilder.scala:156:32, :551:28] wire [63:0] _ll_s_T_5 = _ll_s_T_4[63:0]; // @[FSECompressorDicBuilder.scala:768:20] wire [32:0] _GEN_311 = {1'h0, ll_total}; // @[FSECompressorDicBuilder.scala:414:25, :774:54] wire [32:0] _ll_symbolTTDeltaFindState_T = _GEN_311 - 33'h1; // @[FSECompressorDicBuilder.scala:774:54] wire [31:0] _ll_symbolTTDeltaFindState_T_1 = _ll_symbolTTDeltaFindState_T[31:0]; // @[FSECompressorDicBuilder.scala:774:54] wire [31:0] _ll_symbolTTDeltaFindState_T_2 = _ll_symbolTTDeltaFindState_T_1; // @[FSECompressorDicBuilder.scala:774:{54,61}] wire [32:0] _ll_total_T = _GEN_311 + 33'h1; // @[FSECompressorDicBuilder.scala:774:54, :775:30] wire [31:0] _ll_total_T_1 = _ll_total_T[31:0]; // @[FSECompressorDicBuilder.scala:775:30] wire [32:0] _GEN_312 = {1'h0, normCount}; // @[FSECompressorDicBuilder.scala:415:23, :777:65] wire [32:0] _maxBitsOut_T = _GEN_312 - 33'h1; // @[FSECompressorDicBuilder.scala:777:65] wire [31:0] _maxBitsOut_T_1 = _maxBitsOut_T[31:0]; // @[FSECompressorDicBuilder.scala:777:65] wire [15:0] _maxBitsOut_highBit_T_2 = _maxBitsOut_T_1[31:16]; // @[FSECompressorDicBuilder.scala:52:49, :777:65] wire [31:0] _maxBitsOut_highBit_T_3 = {16'h0, _maxBitsOut_highBit_T_2}; // @[FSECompressorDicBuilder.scala:52:49] wire [15:0] _maxBitsOut_highBit_T_4 = _maxBitsOut_T_1[15:0]; // @[FSECompressorDicBuilder.scala:52:49, :777:65] wire [31:0] _maxBitsOut_highBit_T_5 = {_maxBitsOut_highBit_T_4, 16'h0}; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_7 = _maxBitsOut_highBit_T_5 & 32'hFFFF0000; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_8 = _maxBitsOut_highBit_T_3 \| _maxBitsOut_highBit_T_7; // @[FSECompressorDicBuilder.scala:52:49] wire [23:0] _maxBitsOut_highBit_T_12 = _maxBitsOut_highBit_T_8[31:8]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_13 = {8'h0, _maxBitsOut_highBit_T_12 & 24'hFF00FF}; // @[FSECompressorDicBuilder.scala:52:49] wire [23:0] _maxBitsOut_highBit_T_14 = _maxBitsOut_highBit_T_8[23:0]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_15 = {_maxBitsOut_highBit_T_14, 8'h0}; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_17 = _maxBitsOut_highBit_T_15 & 32'hFF00FF00; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_18 = _maxBitsOut_highBit_T_13 \| _maxBitsOut_highBit_T_17; // @[FSECompressorDicBuilder.scala:52:49] wire [27:0] _maxBitsOut_highBit_T_22 = _maxBitsOut_highBit_T_18[31:4]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_23 = {4'h0, _maxBitsOut_highBit_T_22 & 28'hF0F0F0F}; // @[FSECompressorDicBuilder.scala:52:49] wire [27:0] _maxBitsOut_highBit_T_24 = _maxBitsOut_highBit_T_18[27:0]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_25 = {_maxBitsOut_highBit_T_24, 4'h0}; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_27 = _maxBitsOut_highBit_T_25 & 32'hF0F0F0F0; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_28 = _maxBitsOut_highBit_T_23 \| _maxBitsOut_highBit_T_27; // @[FSECompressorDicBuilder.scala:52:49] wire [29:0] _maxBitsOut_highBit_T_32 = _maxBitsOut_highBit_T_28[31:2]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_33 = {2'h0, _maxBitsOut_highBit_T_32 & 30'h33333333}; // @[FSECompressorDicBuilder.scala:52:49] wire [29:0] _maxBitsOut_highBit_T_34 = _maxBitsOut_highBit_T_28[29:0]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_35 = {_maxBitsOut_highBit_T_34, 2'h0}; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_37 = _maxBitsOut_highBit_T_35 & 32'hCCCCCCCC; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_38 = _maxBitsOut_highBit_T_33 \| _maxBitsOut_highBit_T_37; // @[FSECompressorDicBuilder.scala:52:49] wire [30:0] _maxBitsOut_highBit_T_42 = _maxBitsOut_highBit_T_38[31:1]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_43 = {1'h0, _maxBitsOut_highBit_T_42 & 31'h55555555}; // @[FSECompressorDicBuilder.scala:52:49] wire [30:0] _maxBitsOut_highBit_T_44 = _maxBitsOut_highBit_T_38[30:0]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_45 = {_maxBitsOut_highBit_T_44, 1'h0}; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_47 = _maxBitsOut_highBit_T_45 & 32'hAAAAAAAA; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_48 = _maxBitsOut_highBit_T_43 \| _maxBitsOut_highBit_T_47; // @[FSECompressorDicBuilder.scala:52:49] wire _maxBitsOut_highBit_T_49 = _maxBitsOut_highBit_T_48[0]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_50 = _maxBitsOut_highBit_T_48[1]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_51 = _maxBitsOut_highBit_T_48[2]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_52 = _maxBitsOut_highBit_T_48[3]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_53 = _maxBitsOut_highBit_T_48[4]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_54 = _maxBitsOut_highBit_T_48[5]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_55 = _maxBitsOut_highBit_T_48[6]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_56 = _maxBitsOut_highBit_T_48[7]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_57 = _maxBitsOut_highBit_T_48[8]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_58 = _maxBitsOut_highBit_T_48[9]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_59 = _maxBitsOut_highBit_T_48[10]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_60 = _maxBitsOut_highBit_T_48[11]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_61 = _maxBitsOut_highBit_T_48[12]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_62 = _maxBitsOut_highBit_T_48[13]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_63 = _maxBitsOut_highBit_T_48[14]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_64 = _maxBitsOut_highBit_T_48[15]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_65 = _maxBitsOut_highBit_T_48[16]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_66 = _maxBitsOut_highBit_T_48[17]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_67 = _maxBitsOut_highBit_T_48[18]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_68 = _maxBitsOut_highBit_T_48[19]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_69 = _maxBitsOut_highBit_T_48[20]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_70 = _maxBitsOut_highBit_T_48[21]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_71 = _maxBitsOut_highBit_T_48[22]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_72 = _maxBitsOut_highBit_T_48[23]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_73 = _maxBitsOut_highBit_T_48[24]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_74 = _maxBitsOut_highBit_T_48[25]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_75 = _maxBitsOut_highBit_T_48[26]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_76 = _maxBitsOut_highBit_T_48[27]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_77 = _maxBitsOut_highBit_T_48[28]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_78 = _maxBitsOut_highBit_T_48[29]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_79 = _maxBitsOut_highBit_T_48[30]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_80 = _maxBitsOut_highBit_T_48[31]; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_81 = {4'hF, ~_maxBitsOut_highBit_T_79}; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_82 = _maxBitsOut_highBit_T_78 ? 5'h1D : _maxBitsOut_highBit_T_81; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_83 = _maxBitsOut_highBit_T_77 ? 5'h1C : _maxBitsOut_highBit_T_82; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_84 = _maxBitsOut_highBit_T_76 ? 5'h1B : _maxBitsOut_highBit_T_83; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_85 = _maxBitsOut_highBit_T_75 ? 5'h1A : _maxBitsOut_highBit_T_84; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_86 = _maxBitsOut_highBit_T_74 ? 5'h19 : _maxBitsOut_highBit_T_85; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_87 = _maxBitsOut_highBit_T_73 ? 5'h18 : _maxBitsOut_highBit_T_86; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_88 = _maxBitsOut_highBit_T_72 ? 5'h17 : _maxBitsOut_highBit_T_87; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_89 = _maxBitsOut_highBit_T_71 ? 5'h16 : _maxBitsOut_highBit_T_88; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_90 = _maxBitsOut_highBit_T_70 ? 5'h15 : _maxBitsOut_highBit_T_89; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_91 = _maxBitsOut_highBit_T_69 ? 5'h14 : _maxBitsOut_highBit_T_90; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_92 = _maxBitsOut_highBit_T_68 ? 5'h13 : _maxBitsOut_highBit_T_91; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_93 = _maxBitsOut_highBit_T_67 ? 5'h12 : _maxBitsOut_highBit_T_92; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_94 = _maxBitsOut_highBit_T_66 ? 5'h11 : _maxBitsOut_highBit_T_93; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_95 = _maxBitsOut_highBit_T_65 ? 5'h10 : _maxBitsOut_highBit_T_94; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_96 = _maxBitsOut_highBit_T_64 ? 5'hF : _maxBitsOut_highBit_T_95; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_97 = _maxBitsOut_highBit_T_63 ? 5'hE : _maxBitsOut_highBit_T_96; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_98 = _maxBitsOut_highBit_T_62 ? 5'hD : _maxBitsOut_highBit_T_97; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_99 = _maxBitsOut_highBit_T_61 ? 5'hC : _maxBitsOut_highBit_T_98; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_100 = _maxBitsOut_highBit_T_60 ? 5'hB : _maxBitsOut_highBit_T_99; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_101 = _maxBitsOut_highBit_T_59 ? 5'hA : _maxBitsOut_highBit_T_100; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_102 = _maxBitsOut_highBit_T_58 ? 5'h9 : _maxBitsOut_highBit_T_101; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_103 = _maxBitsOut_highBit_T_57 ? 5'h8 : _maxBitsOut_highBit_T_102; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_104 = _maxBitsOut_highBit_T_56 ? 5'h7 : _maxBitsOut_highBit_T_103; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_105 = _maxBitsOut_highBit_T_55 ? 5'h6 : _maxBitsOut_highBit_T_104; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_106 = _maxBitsOut_highBit_T_54 ? 5'h5 : _maxBitsOut_highBit_T_105; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_107 = _maxBitsOut_highBit_T_53 ? 5'h4 : _maxBitsOut_highBit_T_106; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_108 = _maxBitsOut_highBit_T_52 ? 5'h3 : _maxBitsOut_highBit_T_107; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_109 = _maxBitsOut_highBit_T_51 ? 5'h2 : _maxBitsOut_highBit_T_108; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_110 = _maxBitsOut_highBit_T_50 ? 5'h1 : _maxBitsOut_highBit_T_109; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_111 = _maxBitsOut_highBit_T_49 ? 5'h0 : _maxBitsOut_highBit_T_110; // @[OneHot.scala:48:45] wire [5:0] _maxBitsOut_highBit_T_112 = 6'h1F - {1'h0, _maxBitsOut_highBit_T_111}; // @[Mux.scala:50:70] wire [4:0] maxBitsOut_highBit = _maxBitsOut_highBit_T_112[4:0]; // @[FSECompressorDicBuilder.scala:52:24] wire [5:0] _maxBitsOut_T_2 = 6'h6 - {1'h0, maxBitsOut_highBit}; // @[FSECompressorDicBuilder.scala:52:24, :777:39] wire [4:0] maxBitsOut = _maxBitsOut_T_2[4:0]; // @[FSECompressorDicBuilder.scala:777:39] wire [3:0] _minStatePlus_T = maxBitsOut[3:0]; // @[FSECompressorDicBuilder.scala:777:39, :778:51] wire [46:0] minStatePlus = {15'h0, normCount} << _minStatePlus_T; // @[FSECompressorDicBuilder.scala:415:23, :778:{38,51}] wire [35:0] _ll_symbolTTDeltaNbBits_T = {15'h0, maxBitsOut, 16'h0}; // @[FSECompressorDicBuilder.scala:777:39, :779:53] wire [47:0] _ll_symbolTTDeltaNbBits_T_1 = {12'h0, _ll_symbolTTDeltaNbBits_T} - {1'h0, minStatePlus}; // @[FSECompressorDicBuilder.scala:778:38, :779:{53,62}] wire [46:0] _ll_symbolTTDeltaNbBits_T_2 = _ll_symbolTTDeltaNbBits_T_1[46:0]; // @[FSECompressorDicBuilder.scala:779:62] wire [32:0] _ll_symbolTTDeltaFindState_T_3 = _GEN_311 - _GEN_312; // @[FSECompressorDicBuilder.scala:774:54, :777:65, :780:54] wire [31:0] _ll_symbolTTDeltaFindState_T_4 = _ll_symbolTTDeltaFindState_T_3[31:0]; // @[FSECompressorDicBuilder.scala:780:54] wire [31:0] _ll_symbolTTDeltaFindState_T_5 = _ll_symbolTTDeltaFindState_T_4; // @[FSECompressorDicBuilder.scala:780:{54,67}] wire [32:0] _ll_total_T_2 = _GEN_311 + _GEN_312; // @[FSECompressorDicBuilder.scala:774:54, :777:65, :781:30] wire [31:0] _ll_total_T_3 = _ll_total_T_2[31:0]; // @[FSECompressorDicBuilder.scala:781:30] wire _T_2396 = dicBuilderState == 4'h7; // @[FSECompressorDicBuilder.scala:156:32, :551:28] wire _GEN_313 = ~(\|dicBuilderState) \| _T_839 \| _T_846 \| _T_1371 \| _T_1559 \| _T_2379 \| _T_2386; // @[FSECompressorDicBuilder.scala:156:32, :198:25, :316:25, :494:31, :551:28] wire _T_2400 = symbol < alphabetSize & (\|(remaining[31:1])); // @[FSECompressorDicBuilder.scala:463:26, :465:23, :466:42, :799:{23,39,53}] wire [63:0] _GEN_314 = {16'h0, bitStream[63:16]}; // @[FSECompressorDicBuilder.scala:468:26, :803:38] wire [63:0] _bitStream_T; // @[FSECompressorDicBuilder.scala:803:38] assign _bitStream_T = _GEN_314; // @[FSECompressorDicBuilder.scala:803:38] wire [63:0] _bitStream_T_1; // @[FSECompressorDicBuilder.scala:816:38] assign _bitStream_T_1 = _GEN_314; // @[FSECompressorDicBuilder.scala:803:38, :816:38] wire [7:0] _GEN_315 = {1'h0, bitCount}; // @[FSECompressorDicBuilder.scala:469:25, :804:36] wire [7:0] _bitCount_T = _GEN_315 - 8'h10; // @[FSECompressorDicBuilder.scala:804:36] wire [6:0] _bitCount_T_1 = _bitCount_T[6:0]; // @[FSECompressorDicBuilder.scala:804:36] reg [63:0] loginfo_cycles_339; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_678 = {1'h0, loginfo_cycles_339} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_679 = _loginfo_cycles_T_678[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_340; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_680 = {1'h0, loginfo_cycles_340} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_681 = _loginfo_cycles_T_680[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_341; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_682 = {1'h0, loginfo_cycles_341} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_683 = _loginfo_cycles_T_682[63:0]; // @[Util.scala:19:38] wire _GEN_316 = writeBitStream \| writeBitStreamPrev0; // @[FSECompressorDicBuilder.scala:470:31, :476:36, :481:36, :800:32, :812:46, :813:45, :823:46] reg [63:0] loginfo_cycles_342; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_684 = {1'h0, loginfo_cycles_342} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_685 = _loginfo_cycles_T_684[63:0]; // @[Util.scala:19:38] wire [4:0] _cur_norm_count_T = symbol[4:0]; // @[FSECompressorDicBuilder.scala:465:23] wire [4:0] _count_T = symbol[4:0]; // @[FSECompressorDicBuilder.scala:465:23] reg [63:0] loginfo_cycles_343; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_686 = {1'h0, loginfo_cycles_343} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_687 = _loginfo_cycles_T_686[63:0]; // @[Util.scala:19:38] wire [32:0] _GEN_317 = {1'h0, symbol}; // @[FSECompressorDicBuilder.scala:465:23, :835:34] wire [32:0] _symbol_T = _GEN_317 + 33'h1; // @[FSECompressorDicBuilder.scala:835:34] wire [31:0] _symbol_T_1 = _symbol_T[31:0]; // @[FSECompressorDicBuilder.scala:835:34] wire [32:0] _GEN_318 = {1'h0, start}; // @[FSECompressorDicBuilder.scala:471:22, :842:37] wire [32:0] _start_T = _GEN_318 + 33'h18; // @[FSECompressorDicBuilder.scala:842:37, :843:32] wire [31:0] _start_T_1 = _start_T[31:0]; // @[FSECompressorDicBuilder.scala:843:32] wire [142:0] _bitStream_T_2 = 143'hFFFF << bitCount; // @[FSECompressorDicBuilder.scala:469:25, :844:64] wire [143:0] _bitStream_T_3 = {80'h0, bitStream} + {1'h0, _bitStream_T_2}; // @[FSECompressorDicBuilder.scala:468:26, :844:{40,64}] wire [142:0] _bitStream_T_4 = _bitStream_T_3[142:0]; // @[FSECompressorDicBuilder.scala:844:40] reg [63:0] loginfo_cycles_344; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_688 = {1'h0, loginfo_cycles_344} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_689 = _loginfo_cycles_T_688[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_345; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_690 = {1'h0, loginfo_cycles_345} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_691 = _loginfo_cycles_T_690[63:0]; // @[Util.scala:19:38] wire [32:0] _start_T_2 = _GEN_318 + 33'h3; // @[FSECompressorDicBuilder.scala:842:37, :852:37, :853:32] wire [31:0] _start_T_3 = _start_T_2[31:0]; // @[FSECompressorDicBuilder.scala:853:32] wire [128:0] _bitStream_T_5 = 129'h3 << bitCount; // @[FSECompressorDicBuilder.scala:469:25, :854:47] wire [129:0] _bitStream_T_6 = {66'h0, bitStream} + {1'h0, _bitStream_T_5}; // @[FSECompressorDicBuilder.scala:468:26, :854:{40,47}] wire [128:0] _bitStream_T_7 = _bitStream_T_6[128:0]; // @[FSECompressorDicBuilder.scala:854:40] wire [7:0] _GEN_319 = _GEN_315 + 8'h2; // @[FSECompressorDicBuilder.scala:804:36, :855:38] wire [7:0] _bitCount_T_2; // @[FSECompressorDicBuilder.scala:855:38] assign _bitCount_T_2 = _GEN_319; // @[FSECompressorDicBuilder.scala:855:38] wire [7:0] _bitCount_T_4; // @[FSECompressorDicBuilder.scala:863:36] assign _bitCount_T_4 = _GEN_319; // @[FSECompressorDicBuilder.scala:855:38, :863:36] wire [6:0] _bitCount_T_3 = _bitCount_T_2[6:0]; // @[FSECompressorDicBuilder.scala:855:38] reg [63:0] loginfo_cycles_346; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_692 = {1'h0, loginfo_cycles_346} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_693 = _loginfo_cycles_T_692[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_347; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_694 = {1'h0, loginfo_cycles_347} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_695 = _loginfo_cycles_T_694[63:0]; // @[Util.scala:19:38] wire [32:0] _bitStream_T_8 = _GEN_317 - _GEN_318; // @[FSECompressorDicBuilder.scala:835:34, :842:37, :862:49] wire [31:0] _bitStream_T_9 = _bitStream_T_8[31:0]; // @[FSECompressorDicBuilder.scala:862:49] wire [158:0] _bitStream_T_10 = {127'h0, _bitStream_T_9} << bitCount; // @[FSECompressorDicBuilder.scala:469:25, :844:64, :862:{49,58}] wire [159:0] _GEN_320 = {96'h0, bitStream}; // @[FSECompressorDicBuilder.scala:468:26, :862:38] wire [159:0] _bitStream_T_11 = _GEN_320 + {1'h0, _bitStream_T_10}; // @[FSECompressorDicBuilder.scala:862:{38,58}] wire [158:0] _bitStream_T_12 = _bitStream_T_11[158:0]; // @[FSECompressorDicBuilder.scala:862:38] wire [6:0] _bitCount_T_5 = _bitCount_T_4[6:0]; // @[FSECompressorDicBuilder.scala:863:36] reg [63:0] loginfo_cycles_348; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_696 = {1'h0, loginfo_cycles_348} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_697 = _loginfo_cycles_T_696[63:0]; // @[Util.scala:19:38] wire [32:0] _symbol_T_2 = _GEN_317 + 33'h1; // @[FSECompressorDicBuilder.scala:835:34, :878:30] wire [31:0] _symbol_T_3 = _symbol_T_2[31:0]; // @[FSECompressorDicBuilder.scala:878:30] wire [32:0] _max_T = {threshold, 1'h0}; // @[FSECompressorDicBuilder.scala:464:26, :879:35] wire [33:0] _max_T_1 = {1'h0, _max_T} - 34'h1; // @[FSECompressorDicBuilder.scala:879:{35,43}] wire [32:0] _max_T_2 = _max_T_1[32:0]; // @[FSECompressorDicBuilder.scala:879:43] wire [33:0] _max_T_3 = {1'h0, _max_T_2} - {2'h0, remaining}; // @[FSECompressorDicBuilder.scala:463:26, :879:{43,50}] wire [32:0] max = _max_T_3[32:0]; // @[FSECompressorDicBuilder.scala:879:50] wire [32:0] _nxt_remaining_T = {1'h0, remaining} - {17'h0, _GEN_199[_count_T]}; // @[FSECompressorDicBuilder.scala:416:13, :463:26, :882:43] wire [31:0] nxt_remaining = _nxt_remaining_T[31:0]; // @[FSECompressorDicBuilder.scala:882:43] wire _GEN_321 = writeBitStream \| writeBitStreamPrev0 \| previousIs0; // @[FSECompressorDicBuilder.scala:467:28, :470:31, :476:36, :494:31, :800:32, :813:45, :824:37, :883:23] wire [16:0] _count1_T = {1'h0, _GEN_199[_count_T]} + 17'h1; // @[FSECompressorDicBuilder.scala:416:13, :882:43, :885:32] wire [15:0] count1 = _count1_T[15:0]; // @[FSECompressorDicBuilder.scala:885:32] wire _count1_max_T = {16'h0, count1} >= threshold; // @[FSECompressorDicBuilder.scala:464:26, :885:32, :886:41] wire [33:0] _count1_max_T_1 = {18'h0, count1} + {1'h0, max}; // @[FSECompressorDicBuilder.scala:879:50, :885:32, :886:62] wire [32:0] _count1_max_T_2 = _count1_max_T_1[32:0]; // @[FSECompressorDicBuilder.scala:886:62] wire [32:0] count1_max = _count1_max_T ? _count1_max_T_2 : {17'h0, count1}; // @[FSECompressorDicBuilder.scala:885:32, :886:{33,41,62}] wire [32:0] _GEN_322 = {1'h0, nbBits}; // @[FSECompressorDicBuilder.scala:462:23, :887:41] wire [32:0] _nxt_bitCount_T = {26'h0, bitCount} + _GEN_322; // @[FSECompressorDicBuilder.scala:469:25, :887:41] wire [31:0] _nxt_bitCount_T_1 = _nxt_bitCount_T[31:0]; // @[FSECompressorDicBuilder.scala:887:41] wire _nxt_bitCount_T_2 = count1_max < max; // @[FSECompressorDicBuilder.scala:879:50, :886:33, :887:67] wire _nxt_bitCount_T_3 = _nxt_bitCount_T_2; // @[FSECompressorDicBuilder.scala:887:{55,67}] wire [32:0] _nxt_bitCount_T_4 = {1'h0, _nxt_bitCount_T_1} - {32'h0, _nxt_bitCount_T_3}; // @[FSECompressorDicBuilder.scala:887:{41,50,55}] wire [31:0] nxt_bitCount = _nxt_bitCount_T_4[31:0]; // @[FSECompressorDicBuilder.scala:887:50] wire [159:0] _bitStream_T_13 = {127'h0, count1_max} << bitCount; // @[FSECompressorDicBuilder.scala:469:25, :844:64, :886:33, :888:50] wire [160:0] _bitStream_T_14 = {97'h0, bitStream} + {1'h0, _bitStream_T_13}; // @[FSECompressorDicBuilder.scala:468:26, :888:{36,50}] wire [159:0] _bitStream_T_15 = _bitStream_T_14[159:0]; // @[FSECompressorDicBuilder.scala:888:36] wire _writeBitStream_T = nxt_bitCount > 32'h10; // @[FSECompressorDicBuilder.scala:887:50, :890:44] wire _previousIs0_T = count1_max == 33'h1; // @[FSECompressorDicBuilder.scala:886:33, :892:40] reg [63:0] loginfo_cycles_349; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_698 = {1'h0, loginfo_cycles_349} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_699 = _loginfo_cycles_T_698[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_350; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_700 = {1'h0, loginfo_cycles_350} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_701 = _loginfo_cycles_T_700[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_351; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_702 = {1'h0, loginfo_cycles_351} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_703 = _loginfo_cycles_T_702[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_352; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_704 = {1'h0, loginfo_cycles_352} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_705 = _loginfo_cycles_T_704[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_353; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_706 = {1'h0, loginfo_cycles_353} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_707 = _loginfo_cycles_T_706[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_354; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_708 = {1'h0, loginfo_cycles_354} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_709 = _loginfo_cycles_T_708[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_355; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_710 = {1'h0, loginfo_cycles_355} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_711 = _loginfo_cycles_T_710[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_356; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_712 = {1'h0, loginfo_cycles_356} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_713 = _loginfo_cycles_T_712[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_357; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_714 = {1'h0, loginfo_cycles_357} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_715 = _loginfo_cycles_T_714[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_358; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_716 = {1'h0, loginfo_cycles_358} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_717 = _loginfo_cycles_T_716[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_359; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_718 = {1'h0, loginfo_cycles_359} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_719 = _loginfo_cycles_T_718[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_360; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_720 = {1'h0, loginfo_cycles_360} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_721 = _loginfo_cycles_T_720[63:0]; // @[Util.scala:19:38] wire _shifted_threshold_small_or_eq_remaining_0_T = nxt_remaining < shifted_thresholds_0; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_0_T_1 = _shifted_threshold_small_or_eq_remaining_0_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] wire _GEN_323 = _GEN_313 \| ~_T_2396 \| ~write_header_started \| ~_T_2400 \| _GEN_321; // @[FSECompressorDicBuilder.scala:461:37, :490:57, :494:31, :551:28, :791:36, :799:{39,61}, :800:32, :813:45, :824:37, :883:23] assign shifted_threshold_small_or_eq_remaining_0 = _GEN_323 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_0_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_1_T = nxt_remaining < shifted_thresholds_1; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_1_T_1 = _shifted_threshold_small_or_eq_remaining_1_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_1 = _GEN_323 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_1_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_2_T = nxt_remaining < shifted_thresholds_2; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_2_T_1 = _shifted_threshold_small_or_eq_remaining_2_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_2 = _GEN_323 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_2_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_3_T = nxt_remaining < shifted_thresholds_3; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_3_T_1 = _shifted_threshold_small_or_eq_remaining_3_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_3 = _GEN_323 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_3_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_4_T = nxt_remaining < shifted_thresholds_4; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_4_T_1 = _shifted_threshold_small_or_eq_remaining_4_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_4 = _GEN_323 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_4_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_5_T = nxt_remaining < shifted_thresholds_5; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_5_T_1 = _shifted_threshold_small_or_eq_remaining_5_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_5 = _GEN_323 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_5_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_6_T = nxt_remaining < shifted_thresholds_6; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_6_T_1 = _shifted_threshold_small_or_eq_remaining_6_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_6 = _GEN_323 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_6_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire [2:0] _threshold_T = nxt_shifted_threshold_idx[2:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nbBits_T = _GEN_322 - {1'h0, nxt_shifted_threshold_idx}; // @[FSECompressorDicBuilder.scala:491:84, :887:41, :911:30] wire [31:0] _nbBits_T_1 = _nbBits_T[31:0]; // @[FSECompressorDicBuilder.scala:911:30] wire _GEN_324 = ~_T_2400 \| writeBitStream \| writeBitStreamPrev0; // @[FSECompressorDicBuilder.scala:470:31, :476:36, :494:31, :799:{39,61}, :800:32, :810:36, :813:45, :914:34] assign io_header_writes_valid_0 = ~_GEN_313 & _T_2396 & write_header_started & _GEN_324; // @[FSECompressorDicBuilder.scala:39:7, :461:37, :479:26, :494:31, :551:28, :791:36, :799:61, :800:32, :810:36, :813:45, :914:34] assign io_header_writes_bits_data_0 = _GEN_313 \| ~(_T_2396 & write_header_started & _GEN_324) ? 256'h0 : {192'h0, bitStream}; // @[FSECompressorDicBuilder.scala:39:7, :461:37, :468:26, :480:30, :494:31, :551:28, :791:36, :799:61, :800:32, :810:36, :811:40, :813:45, :914:34] wire [7:0] _io_header_writes_bits_validbytes_T = _GEN_315 + 8'h7; // @[FSECompressorDicBuilder.scala:804:36, :916:58] wire [6:0] _io_header_writes_bits_validbytes_T_1 = _io_header_writes_bits_validbytes_T[6:0]; // @[FSECompressorDicBuilder.scala:916:58] wire [6:0] _io_header_writes_bits_validbytes_T_2 = {3'h0, _io_header_writes_bits_validbytes_T_1[6:3]}; // @[FSECompressorDicBuilder.scala:916:{58,65}] assign io_header_writes_bits_validbytes_0 = _GEN_313 \| ~(_T_2396 & write_header_started) ? 6'h0 : _T_2400 ? {4'h0, _GEN_316, 1'h0} : _io_header_writes_bits_validbytes_T_2[5:0]; // @[FSECompressorDicBuilder.scala:39:7, :461:37, :481:36, :494:31, :551:28, :791:36, :799:{39,61}, :800:32, :812:46, :813:45, :823:46, :916:{44,65}] assign io_header_writes_bits_end_of_message_0 = ~_GEN_313 & _T_2396 & write_header_started & ~_T_2400; // @[FSECompressorDicBuilder.scala:39:7, :461:37, :482:40, :494:31, :551:28, :791:36, :799:{39,61}, :919:50] wire _GEN_325 = ~(\|dicBuilderState) \| _T_839 \| _T_846 \| _T_1371 \| _T_1559 \| _T_2379 \| _T_2386 \| _T_2396; // @[FSECompressorDicBuilder.scala:156:32, :198:25, :316:25, :494:31, :551:28] reg [63:0] loginfo_cycles_361; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_722 = {1'h0, loginfo_cycles_361} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_723 = _loginfo_cycles_T_722[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_362; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_724 = {1'h0, loginfo_cycles_362} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_725 = _loginfo_cycles_T_724[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_363; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_726 = {1'h0, loginfo_cycles_363} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_727 = _loginfo_cycles_T_726[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_364; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_728 = {1'h0, loginfo_cycles_364} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_729 = _loginfo_cycles_T_728[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_365; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_730 = {1'h0, loginfo_cycles_365} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_731 = _loginfo_cycles_T_730[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_366; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_732 = {1'h0, loginfo_cycles_366} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_733 = _loginfo_cycles_T_732[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_367; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_734 = {1'h0, loginfo_cycles_367} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_735 = _loginfo_cycles_T_734[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_368; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_736 = {1'h0, loginfo_cycles_368} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_737 = _loginfo_cycles_T_736[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_369; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_738 = {1'h0, loginfo_cycles_369} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_739 = _loginfo_cycles_T_738[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_370; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_740 = {1'h0, loginfo_cycles_370} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_741 = _loginfo_cycles_T_740[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_371; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_742 = {1'h0, loginfo_cycles_371} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_743 = _loginfo_cycles_T_742[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_372; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_744 = {1'h0, loginfo_cycles_372} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_745 = _loginfo_cycles_T_744[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_373; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_746 = {1'h0, loginfo_cycles_373} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_747 = _loginfo_cycles_T_746[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_374; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_748 = {1'h0, loginfo_cycles_374} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_749 = _loginfo_cycles_T_748[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_375; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_750 = {1'h0, loginfo_cycles_375} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_751 = _loginfo_cycles_T_750[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_376; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_752 = {1'h0, loginfo_cycles_376} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_753 = _loginfo_cycles_T_752[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_377; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_754 = {1'h0, loginfo_cycles_377} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_755 = _loginfo_cycles_T_754[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_378; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_756 = {1'h0, loginfo_cycles_378} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_757 = _loginfo_cycles_T_756[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_379; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_758 = {1'h0, loginfo_cycles_379} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_759 = _loginfo_cycles_T_758[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_380; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_760 = {1'h0, loginfo_cycles_380} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_761 = _loginfo_cycles_T_760[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_381; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_762 = {1'h0, loginfo_cycles_381} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_763 = _loginfo_cycles_T_762[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_382; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_764 = {1'h0, loginfo_cycles_382} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_765 = _loginfo_cycles_T_764[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_383; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_766 = {1'h0, loginfo_cycles_383} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_767 = _loginfo_cycles_T_766[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_384; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_768 = {1'h0, loginfo_cycles_384} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_769 = _loginfo_cycles_T_768[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_385; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_770 = {1'h0, loginfo_cycles_385} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_771 = _loginfo_cycles_T_770[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_386; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_772 = {1'h0, loginfo_cycles_386} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_773 = _loginfo_cycles_T_772[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_387; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_774 = {1'h0, loginfo_cycles_387} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_775 = _loginfo_cycles_T_774[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_388; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_776 = {1'h0, loginfo_cycles_388} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_777 = _loginfo_cycles_T_776[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_389; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_778 = {1'h0, loginfo_cycles_389} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_779 = _loginfo_cycles_T_778[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_390; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_780 = {1'h0, loginfo_cycles_390} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_781 = _loginfo_cycles_T_780[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_391; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_782 = {1'h0, loginfo_cycles_391} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_783 = _loginfo_cycles_T_782[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_392; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_784 = {1'h0, loginfo_cycles_392} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_785 = _loginfo_cycles_T_784[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_393; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_786 = {1'h0, loginfo_cycles_393} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_787 = _loginfo_cycles_T_786[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_394; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_788 = {1'h0, loginfo_cycles_394} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_789 = _loginfo_cycles_T_788[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_395; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_790 = {1'h0, loginfo_cycles_395} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_791 = _loginfo_cycles_T_790[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_396; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_792 = {1'h0, loginfo_cycles_396} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_793 = _loginfo_cycles_T_792[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_397; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_794 = {1'h0, loginfo_cycles_397} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_795 = _loginfo_cycles_T_794[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_398; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_796 = {1'h0, loginfo_cycles_398} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_797 = _loginfo_cycles_T_796[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_399; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_798 = {1'h0, loginfo_cycles_399} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_799 = _loginfo_cycles_T_798[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_400; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_800 = {1'h0, loginfo_cycles_400} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_801 = _loginfo_cycles_T_800[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_401; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_802 = {1'h0, loginfo_cycles_401} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_803 = _loginfo_cycles_T_802[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_402; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_804 = {1'h0, loginfo_cycles_402} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_805 = _loginfo_cycles_T_804[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_403; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_806 = {1'h0, loginfo_cycles_403} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_807 = _loginfo_cycles_T_806[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_404; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_808 = {1'h0, loginfo_cycles_404} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_809 = _loginfo_cycles_T_808[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_405; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_810 = {1'h0, loginfo_cycles_405} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_811 = _loginfo_cycles_T_810[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_406; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_812 = {1'h0, loginfo_cycles_406} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_813 = _loginfo_cycles_T_812[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_407; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_814 = {1'h0, loginfo_cycles_407} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_815 = _loginfo_cycles_T_814[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_408; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_816 = {1'h0, loginfo_cycles_408} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_817 = _loginfo_cycles_T_816[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_409; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_818 = {1'h0, loginfo_cycles_409} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_819 = _loginfo_cycles_T_818[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_410; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_820 = {1'h0, loginfo_cycles_410} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_821 = _loginfo_cycles_T_820[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_411; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_822 = {1'h0, loginfo_cycles_411} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_823 = _loginfo_cycles_T_822[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_412; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_824 = {1'h0, loginfo_cycles_412} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_825 = _loginfo_cycles_T_824[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_413; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_826 = {1'h0, loginfo_cycles_413} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_827 = _loginfo_cycles_T_826[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_414; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_828 = {1'h0, loginfo_cycles_414} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_829 = _loginfo_cycles_T_828[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_415; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_830 = {1'h0, loginfo_cycles_415} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_831 = _loginfo_cycles_T_830[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_416; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_832 = {1'h0, loginfo_cycles_416} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_833 = _loginfo_cycles_T_832[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_417; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_834 = {1'h0, loginfo_cycles_417} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_835 = _loginfo_cycles_T_834[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_418; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_836 = {1'h0, loginfo_cycles_418} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_837 = _loginfo_cycles_T_836[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_419; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_838 = {1'h0, loginfo_cycles_419} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_839 = _loginfo_cycles_T_838[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_420; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_840 = {1'h0, loginfo_cycles_420} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_841 = _loginfo_cycles_T_840[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_421; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_842 = {1'h0, loginfo_cycles_421} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_843 = _loginfo_cycles_T_842[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_422; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_844 = {1'h0, loginfo_cycles_422} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_845 = _loginfo_cycles_T_844[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_423; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_846 = {1'h0, loginfo_cycles_423} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_847 = _loginfo_cycles_T_846[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_424; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_848 = {1'h0, loginfo_cycles_424} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_849 = _loginfo_cycles_T_848[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_425; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_850 = {1'h0, loginfo_cycles_425} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_851 = _loginfo_cycles_T_850[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_426; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_852 = {1'h0, loginfo_cycles_426} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_853 = _loginfo_cycles_T_852[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_427; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_854 = {1'h0, loginfo_cycles_427} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_855 = _loginfo_cycles_T_854[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_428; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_856 = {1'h0, loginfo_cycles_428} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_857 = _loginfo_cycles_T_856[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_429; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_858 = {1'h0, loginfo_cycles_429} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_859 = _loginfo_cycles_T_858[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_430; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_860 = {1'h0, loginfo_cycles_430} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_861 = _loginfo_cycles_T_860[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_431; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_862 = {1'h0, loginfo_cycles_431} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_863 = _loginfo_cycles_T_862[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_432; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_864 = {1'h0, loginfo_cycles_432} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_865 = _loginfo_cycles_T_864[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_433; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_866 = {1'h0, loginfo_cycles_433} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_867 = _loginfo_cycles_T_866[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_434; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_868 = {1'h0, loginfo_cycles_434} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_869 = _loginfo_cycles_T_868[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_435; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_870 = {1'h0, loginfo_cycles_435} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_871 = _loginfo_cycles_T_870[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_436; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_872 = {1'h0, loginfo_cycles_436} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_873 = _loginfo_cycles_T_872[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_437; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_874 = {1'h0, loginfo_cycles_437} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_875 = _loginfo_cycles_T_874[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_438; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_876 = {1'h0, loginfo_cycles_438} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_877 = _loginfo_cycles_T_876[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_439; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_878 = {1'h0, loginfo_cycles_439} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_879 = _loginfo_cycles_T_878[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_440; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_880 = {1'h0, loginfo_cycles_440} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_881 = _loginfo_cycles_T_880[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_441; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_882 = {1'h0, loginfo_cycles_441} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_883 = _loginfo_cycles_T_882[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_442; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_884 = {1'h0, loginfo_cycles_442} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_885 = _loginfo_cycles_T_884[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_443; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_886 = {1'h0, loginfo_cycles_443} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_887 = _loginfo_cycles_T_886[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_444; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_888 = {1'h0, loginfo_cycles_444} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_889 = _loginfo_cycles_T_888[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_445; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_890 = {1'h0, loginfo_cycles_445} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_891 = _loginfo_cycles_T_890[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_446; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_892 = {1'h0, loginfo_cycles_446} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_893 = _loginfo_cycles_T_892[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_447; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_894 = {1'h0, loginfo_cycles_447} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_895 = _loginfo_cycles_T_894[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_448; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_896 = {1'h0, loginfo_cycles_448} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_897 = _loginfo_cycles_T_896[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_449; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_898 = {1'h0, loginfo_cycles_449} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_899 = _loginfo_cycles_T_898[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_450; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_900 = {1'h0, loginfo_cycles_450} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_901 = _loginfo_cycles_T_900[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_451; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_902 = {1'h0, loginfo_cycles_451} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_903 = _loginfo_cycles_T_902[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_452; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_904 = {1'h0, loginfo_cycles_452} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_905 = _loginfo_cycles_T_904[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_453; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_906 = {1'h0, loginfo_cycles_453} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_907 = _loginfo_cycles_T_906[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_454; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_908 = {1'h0, loginfo_cycles_454} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_909 = _loginfo_cycles_T_908[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_455; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_910 = {1'h0, loginfo_cycles_455} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_911 = _loginfo_cycles_T_910[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_456; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_912 = {1'h0, loginfo_cycles_456} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_913 = _loginfo_cycles_T_912[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_457; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_914 = {1'h0, loginfo_cycles_457} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_915 = _loginfo_cycles_T_914[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_458; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_916 = {1'h0, loginfo_cycles_458} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_917 = _loginfo_cycles_T_916[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_459; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_918 = {1'h0, loginfo_cycles_459} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_919 = _loginfo_cycles_T_918[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_460; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_920 = {1'h0, loginfo_cycles_460} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_921 = _loginfo_cycles_T_920[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_461; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_922 = {1'h0, loginfo_cycles_461} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_923 = _loginfo_cycles_T_922[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_462; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_924 = {1'h0, loginfo_cycles_462} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_925 = _loginfo_cycles_T_924[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_463; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_926 = {1'h0, loginfo_cycles_463} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_927 = _loginfo_cycles_T_926[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_464; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_928 = {1'h0, loginfo_cycles_464} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_929 = _loginfo_cycles_T_928[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_465; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_930 = {1'h0, loginfo_cycles_465} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_931 = _loginfo_cycles_T_930[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_466; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_932 = {1'h0, loginfo_cycles_466} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_933 = _loginfo_cycles_T_932[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_467; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_934 = {1'h0, loginfo_cycles_467} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_935 = _loginfo_cycles_T_934[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_468; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_936 = {1'h0, loginfo_cycles_468} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_937 = _loginfo_cycles_T_936[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_469; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_938 = {1'h0, loginfo_cycles_469} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_939 = _loginfo_cycles_T_938[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_470; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_940 = {1'h0, loginfo_cycles_470} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_941 = _loginfo_cycles_T_940[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_471; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_942 = {1'h0, loginfo_cycles_471} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_943 = _loginfo_cycles_T_942[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_472; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_944 = {1'h0, loginfo_cycles_472} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_945 = _loginfo_cycles_T_944[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_473; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_946 = {1'h0, loginfo_cycles_473} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_947 = _loginfo_cycles_T_946[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_474; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_948 = {1'h0, loginfo_cycles_474} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_949 = _loginfo_cycles_T_948[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_475; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_950 = {1'h0, loginfo_cycles_475} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_951 = _loginfo_cycles_T_950[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_476; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_952 = {1'h0, loginfo_cycles_476} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_953 = _loginfo_cycles_T_952[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_477; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_954 = {1'h0, loginfo_cycles_477} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_955 = _loginfo_cycles_T_954[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_478; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_956 = {1'h0, loginfo_cycles_478} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_957 = _loginfo_cycles_T_956[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_479; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_958 = {1'h0, loginfo_cycles_479} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_959 = _loginfo_cycles_T_958[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_480; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_960 = {1'h0, loginfo_cycles_480} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_961 = _loginfo_cycles_T_960[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_481; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_962 = {1'h0, loginfo_cycles_481} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_963 = _loginfo_cycles_T_962[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_482; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_964 = {1'h0, loginfo_cycles_482} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_965 = _loginfo_cycles_T_964[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_483; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_966 = {1'h0, loginfo_cycles_483} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_967 = _loginfo_cycles_T_966[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_484; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_968 = {1'h0, loginfo_cycles_484} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_969 = _loginfo_cycles_T_968[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_485; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_970 = {1'h0, loginfo_cycles_485} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_971 = _loginfo_cycles_T_970[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_486; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_972 = {1'h0, loginfo_cycles_486} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_973 = _loginfo_cycles_T_972[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_487; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_974 = {1'h0, loginfo_cycles_487} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_975 = _loginfo_cycles_T_974[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_488; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_976 = {1'h0, loginfo_cycles_488} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_977 = _loginfo_cycles_T_976[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_489; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_978 = {1'h0, loginfo_cycles_489} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_979 = _loginfo_cycles_T_978[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_490; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_980 = {1'h0, loginfo_cycles_490} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_981 = _loginfo_cycles_T_980[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_491; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_982 = {1'h0, loginfo_cycles_491} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_983 = _loginfo_cycles_T_982[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_492; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_984 = {1'h0, loginfo_cycles_492} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_985 = _loginfo_cycles_T_984[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_493; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_986 = {1'h0, loginfo_cycles_493} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_987 = _loginfo_cycles_T_986[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_494; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_988 = {1'h0, loginfo_cycles_494} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_989 = _loginfo_cycles_T_988[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_495; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_990 = {1'h0, loginfo_cycles_495} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_991 = _loginfo_cycles_T_990[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_496; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_992 = {1'h0, loginfo_cycles_496} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_993 = _loginfo_cycles_T_992[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_497; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_994 = {1'h0, loginfo_cycles_497} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_995 = _loginfo_cycles_T_994[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_498; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_996 = {1'h0, loginfo_cycles_498} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_997 = _loginfo_cycles_T_996[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_499; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_998 = {1'h0, loginfo_cycles_499} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_999 = _loginfo_cycles_T_998[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_500; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1000 = {1'h0, loginfo_cycles_500} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1001 = _loginfo_cycles_T_1000[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_501; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1002 = {1'h0, loginfo_cycles_501} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1003 = _loginfo_cycles_T_1002[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_502; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1004 = {1'h0, loginfo_cycles_502} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1005 = _loginfo_cycles_T_1004[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_503; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1006 = {1'h0, loginfo_cycles_503} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1007 = _loginfo_cycles_T_1006[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_504; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1008 = {1'h0, loginfo_cycles_504} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1009 = _loginfo_cycles_T_1008[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_505; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1010 = {1'h0, loginfo_cycles_505} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1011 = _loginfo_cycles_T_1010[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_506; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1012 = {1'h0, loginfo_cycles_506} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1013 = _loginfo_cycles_T_1012[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_507; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1014 = {1'h0, loginfo_cycles_507} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1015 = _loginfo_cycles_T_1014[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_508; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1016 = {1'h0, loginfo_cycles_508} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1017 = _loginfo_cycles_T_1016[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_509; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1018 = {1'h0, loginfo_cycles_509} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1019 = _loginfo_cycles_T_1018[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_510; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1020 = {1'h0, loginfo_cycles_510} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1021 = _loginfo_cycles_T_1020[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_511; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1022 = {1'h0, loginfo_cycles_511} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1023 = _loginfo_cycles_T_1022[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_512; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1024 = {1'h0, loginfo_cycles_512} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1025 = _loginfo_cycles_T_1024[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_513; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1026 = {1'h0, loginfo_cycles_513} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1027 = _loginfo_cycles_T_1026[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_514; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1028 = {1'h0, loginfo_cycles_514} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1029 = _loginfo_cycles_T_1028[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_515; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1030 = {1'h0, loginfo_cycles_515} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1031 = _loginfo_cycles_T_1030[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_516; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1032 = {1'h0, loginfo_cycles_516} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1033 = _loginfo_cycles_T_1032[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_517; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1034 = {1'h0, loginfo_cycles_517} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1035 = _loginfo_cycles_T_1034[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_518; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1036 = {1'h0, loginfo_cycles_518} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1037 = _loginfo_cycles_T_1036[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_519; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1038 = {1'h0, loginfo_cycles_519} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1039 = _loginfo_cycles_T_1038[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_520; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1040 = {1'h0, loginfo_cycles_520} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1041 = _loginfo_cycles_T_1040[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_521; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1042 = {1'h0, loginfo_cycles_521} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1043 = _loginfo_cycles_T_1042[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_522; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1044 = {1'h0, loginfo_cycles_522} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1045 = _loginfo_cycles_T_1044[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_523; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1046 = {1'h0, loginfo_cycles_523} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1047 = _loginfo_cycles_T_1046[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_524; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1048 = {1'h0, loginfo_cycles_524} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1049 = _loginfo_cycles_T_1048[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_525; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1050 = {1'h0, loginfo_cycles_525} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1051 = _loginfo_cycles_T_1050[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_526; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1052 = {1'h0, loginfo_cycles_526} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1053 = _loginfo_cycles_T_1052[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_527; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1054 = {1'h0, loginfo_cycles_527} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1055 = _loginfo_cycles_T_1054[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_528; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1056 = {1'h0, loginfo_cycles_528} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1057 = _loginfo_cycles_T_1056[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_529; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1058 = {1'h0, loginfo_cycles_529} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1059 = _loginfo_cycles_T_1058[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_530; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1060 = {1'h0, loginfo_cycles_530} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1061 = _loginfo_cycles_T_1060[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_531; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1062 = {1'h0, loginfo_cycles_531} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1063 = _loginfo_cycles_T_1062[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_532; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1064 = {1'h0, loginfo_cycles_532} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1065 = _loginfo_cycles_T_1064[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_533; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1066 = {1'h0, loginfo_cycles_533} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1067 = _loginfo_cycles_T_1066[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_534; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1068 = {1'h0, loginfo_cycles_534} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1069 = _loginfo_cycles_T_1068[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_535; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1070 = {1'h0, loginfo_cycles_535} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1071 = _loginfo_cycles_T_1070[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_536; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1072 = {1'h0, loginfo_cycles_536} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1073 = _loginfo_cycles_T_1072[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_537; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1074 = {1'h0, loginfo_cycles_537} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1075 = _loginfo_cycles_T_1074[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_538; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1076 = {1'h0, loginfo_cycles_538} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1077 = _loginfo_cycles_T_1076[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_539; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1078 = {1'h0, loginfo_cycles_539} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1079 = _loginfo_cycles_T_1078[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_540; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1080 = {1'h0, loginfo_cycles_540} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1081 = _loginfo_cycles_T_1080[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_541; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1082 = {1'h0, loginfo_cycles_541} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1083 = _loginfo_cycles_T_1082[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_542; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1084 = {1'h0, loginfo_cycles_542} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1085 = _loginfo_cycles_T_1084[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_543; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1086 = {1'h0, loginfo_cycles_543} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1087 = _loginfo_cycles_T_1086[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_544; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1088 = {1'h0, loginfo_cycles_544} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1089 = _loginfo_cycles_T_1088[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_545; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1090 = {1'h0, loginfo_cycles_545} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1091 = _loginfo_cycles_T_1090[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_546; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1092 = {1'h0, loginfo_cycles_546} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1093 = _loginfo_cycles_T_1092[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_547; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1094 = {1'h0, loginfo_cycles_547} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1095 = _loginfo_cycles_T_1094[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_548; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1096 = {1'h0, loginfo_cycles_548} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1097 = _loginfo_cycles_T_1096[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_549; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1098 = {1'h0, loginfo_cycles_549} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1099 = _loginfo_cycles_T_1098[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_550; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1100 = {1'h0, loginfo_cycles_550} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1101 = _loginfo_cycles_T_1100[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_551; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1102 = {1'h0, loginfo_cycles_551} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1103 = _loginfo_cycles_T_1102[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_552; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1104 = {1'h0, loginfo_cycles_552} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1105 = _loginfo_cycles_T_1104[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_553; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1106 = {1'h0, loginfo_cycles_553} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1107 = _loginfo_cycles_T_1106[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_554; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1108 = {1'h0, loginfo_cycles_554} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1109 = _loginfo_cycles_T_1108[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_555; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1110 = {1'h0, loginfo_cycles_555} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1111 = _loginfo_cycles_T_1110[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_556; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1112 = {1'h0, loginfo_cycles_556} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1113 = _loginfo_cycles_T_1112[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_557; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1114 = {1'h0, loginfo_cycles_557} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1115 = _loginfo_cycles_T_1114[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_558; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1116 = {1'h0, loginfo_cycles_558} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1117 = _loginfo_cycles_T_1116[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_559; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1118 = {1'h0, loginfo_cycles_559} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1119 = _loginfo_cycles_T_1118[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_560; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1120 = {1'h0, loginfo_cycles_560} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1121 = _loginfo_cycles_T_1120[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_561; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1122 = {1'h0, loginfo_cycles_561} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1123 = _loginfo_cycles_T_1122[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_562; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1124 = {1'h0, loginfo_cycles_562} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1125 = _loginfo_cycles_T_1124[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_563; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1126 = {1'h0, loginfo_cycles_563} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1127 = _loginfo_cycles_T_1126[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_564; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1128 = {1'h0, loginfo_cycles_564} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1129 = _loginfo_cycles_T_1128[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_565; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1130 = {1'h0, loginfo_cycles_565} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1131 = _loginfo_cycles_T_1130[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_566; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1132 = {1'h0, loginfo_cycles_566} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1133 = _loginfo_cycles_T_1132[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_567; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1134 = {1'h0, loginfo_cycles_567} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1135 = _loginfo_cycles_T_1134[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_568; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1136 = {1'h0, loginfo_cycles_568} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1137 = _loginfo_cycles_T_1136[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_569; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1138 = {1'h0, loginfo_cycles_569} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1139 = _loginfo_cycles_T_1138[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_570; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1140 = {1'h0, loginfo_cycles_570} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1141 = _loginfo_cycles_T_1140[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_571; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1142 = {1'h0, loginfo_cycles_571} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1143 = _loginfo_cycles_T_1142[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_572; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1144 = {1'h0, loginfo_cycles_572} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1145 = _loginfo_cycles_T_1144[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_573; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1146 = {1'h0, loginfo_cycles_573} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1147 = _loginfo_cycles_T_1146[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_574; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1148 = {1'h0, loginfo_cycles_574} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1149 = _loginfo_cycles_T_1148[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_575; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1150 = {1'h0, loginfo_cycles_575} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1151 = _loginfo_cycles_T_1150[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_576; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1152 = {1'h0, loginfo_cycles_576} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1153 = _loginfo_cycles_T_1152[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_577; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1154 = {1'h0, loginfo_cycles_577} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1155 = _loginfo_cycles_T_1154[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_578; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1156 = {1'h0, loginfo_cycles_578} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1157 = _loginfo_cycles_T_1156[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_579; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1158 = {1'h0, loginfo_cycles_579} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1159 = _loginfo_cycles_T_1158[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_580; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1160 = {1'h0, loginfo_cycles_580} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1161 = _loginfo_cycles_T_1160[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_581; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1162 = {1'h0, loginfo_cycles_581} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1163 = _loginfo_cycles_T_1162[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_582; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1164 = {1'h0, loginfo_cycles_582} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1165 = _loginfo_cycles_T_1164[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_583; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1166 = {1'h0, loginfo_cycles_583} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1167 = _loginfo_cycles_T_1166[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_584; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1168 = {1'h0, loginfo_cycles_584} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1169 = _loginfo_cycles_T_1168[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_585; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1170 = {1'h0, loginfo_cycles_585} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1171 = _loginfo_cycles_T_1170[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_586; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1172 = {1'h0, loginfo_cycles_586} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1173 = _loginfo_cycles_T_1172[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_587; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1174 = {1'h0, loginfo_cycles_587} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1175 = _loginfo_cycles_T_1174[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_588; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1176 = {1'h0, loginfo_cycles_588} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1177 = _loginfo_cycles_T_1176[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_589; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1178 = {1'h0, loginfo_cycles_589} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1179 = _loginfo_cycles_T_1178[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_590; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1180 = {1'h0, loginfo_cycles_590} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1181 = _loginfo_cycles_T_1180[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_591; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1182 = {1'h0, loginfo_cycles_591} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1183 = _loginfo_cycles_T_1182[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_592; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1184 = {1'h0, loginfo_cycles_592} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1185 = _loginfo_cycles_T_1184[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_593; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1186 = {1'h0, loginfo_cycles_593} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1187 = _loginfo_cycles_T_1186[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_594; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1188 = {1'h0, loginfo_cycles_594} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1189 = _loginfo_cycles_T_1188[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_595; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1190 = {1'h0, loginfo_cycles_595} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1191 = _loginfo_cycles_T_1190[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_596; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1192 = {1'h0, loginfo_cycles_596} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1193 = _loginfo_cycles_T_1192[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_597; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1194 = {1'h0, loginfo_cycles_597} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1195 = _loginfo_cycles_T_1194[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_598; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1196 = {1'h0, loginfo_cycles_598} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1197 = _loginfo_cycles_T_1196[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_599; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1198 = {1'h0, loginfo_cycles_599} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1199 = _loginfo_cycles_T_1198[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_600; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1200 = {1'h0, loginfo_cycles_600} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1201 = _loginfo_cycles_T_1200[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_601; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1202 = {1'h0, loginfo_cycles_601} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1203 = _loginfo_cycles_T_1202[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_602; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1204 = {1'h0, loginfo_cycles_602} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1205 = _loginfo_cycles_T_1204[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_603; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1206 = {1'h0, loginfo_cycles_603} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1207 = _loginfo_cycles_T_1206[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_604; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1208 = {1'h0, loginfo_cycles_604} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1209 = _loginfo_cycles_T_1208[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_605; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1210 = {1'h0, loginfo_cycles_605} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1211 = _loginfo_cycles_T_1210[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_606; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1212 = {1'h0, loginfo_cycles_606} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1213 = _loginfo_cycles_T_1212[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_607; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1214 = {1'h0, loginfo_cycles_607} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1215 = _loginfo_cycles_T_1214[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_608; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1216 = {1'h0, loginfo_cycles_608} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1217 = _loginfo_cycles_T_1216[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_609; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1218 = {1'h0, loginfo_cycles_609} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1219 = _loginfo_cycles_T_1218[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_610; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1220 = {1'h0, loginfo_cycles_610} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1221 = _loginfo_cycles_T_1220[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_611; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1222 = {1'h0, loginfo_cycles_611} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1223 = _loginfo_cycles_T_1222[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_612; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1224 = {1'h0, loginfo_cycles_612} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1225 = _loginfo_cycles_T_1224[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_613; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1226 = {1'h0, loginfo_cycles_613} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1227 = _loginfo_cycles_T_1226[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_614; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1228 = {1'h0, loginfo_cycles_614} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1229 = _loginfo_cycles_T_1228[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_615; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1230 = {1'h0, loginfo_cycles_615} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1231 = _loginfo_cycles_T_1230[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_616; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1232 = {1'h0, loginfo_cycles_616} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1233 = _loginfo_cycles_T_1232[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_617; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1234 = {1'h0, loginfo_cycles_617} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1235 = _loginfo_cycles_T_1234[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_618; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1236 = {1'h0, loginfo_cycles_618} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1237 = _loginfo_cycles_T_1236[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_619; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1238 = {1'h0, loginfo_cycles_619} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1239 = _loginfo_cycles_T_1238[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_620; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1240 = {1'h0, loginfo_cycles_620} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1241 = _loginfo_cycles_T_1240[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_621; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1242 = {1'h0, loginfo_cycles_621} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1243 = _loginfo_cycles_T_1242[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_622; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1244 = {1'h0, loginfo_cycles_622} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1245 = _loginfo_cycles_T_1244[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_623; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1246 = {1'h0, loginfo_cycles_623} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1247 = _loginfo_cycles_T_1246[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_624; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1248 = {1'h0, loginfo_cycles_624} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1249 = _loginfo_cycles_T_1248[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_625; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1250 = {1'h0, loginfo_cycles_625} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1251 = _loginfo_cycles_T_1250[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_626; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1252 = {1'h0, loginfo_cycles_626} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1253 = _loginfo_cycles_T_1252[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_627; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_1254 = {1'h0, loginfo_cycles_627} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1255 = _loginfo_cycles_T_1254[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U \|\| codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn \|\| codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U \|\| expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 \|\| FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty \|\| floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) \| Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) \|\| helper(unswizzled, prevT) val curOK = !t.isNaN(x) \|\| x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger \| ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) \| (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL/fmv..x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) \| x, maxType) } // implement NaN unboxing and un-recoding for FS/fmv.x. def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out \| (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR \| (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) \|\| narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt \|\| (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) \|\| maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 \|\| in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B \|\| outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma \|\| cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid \|\| io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm \|\| io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx \|\| mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx \|\| ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm \|\| mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) \| (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint \|\| ex_ctrl.div \|\| ex_ctrl.sqrt \|\| (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_\|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_\|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma \|\| mem_ctrl.fastpipe \|\| mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR \|\| (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 \| memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) \|\| divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid \|\| divSqrt_wen \|\| wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) \| Mux(divSqrt_wen, divSqrt_flags, 0.U) \| Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div \|\| mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags \|\| mem_reg_valid && mem_ctrl.wflags \|\| wb_reg_valid && wb_ctrl.toint \|\| wen.orR \|\| divSqrt_inFlight) io.nack_mem := (write_port_busy \|\| divSqrt_write_port_busy \|\| divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_\|\|_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) \|\| mem_ctrl.div \|\| mem_ctrl.sqrt \|\| mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen \|\| (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) \|\| io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div \|\| divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div \|\| id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B \|\| io.keep_clock_enabled \|\| // chicken bit io.valid \|\| // ID stage req_valid \|\| // EX stage mem_reg_valid \|\| mem_cp_valid \|\| // MEM stage wb_reg_valid \|\| wb_cp_valid \|\| // WB stage wen.orR \|\| divSqrt_inFlight \|\| // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) } File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /* * Object to get the FP rounding mode out of a packed immediate. / object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /* * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) / object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File functional-unit.scala: //**************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Functional Units //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // If regfile bypassing is disabled, then the functional unit must do its own // bypassing in here on the WB stage (i.e., bypassing the io.resp.data) // // TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass? package boom.v3.exu import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ import freechips.rocketchip.tile import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR} import boom.v3.common._ import boom.v3.ifu._ import boom.v3.util._ /t * Functional unit constants / object FUConstants { // bit mask, since a given execution pipeline may support multiple functional units val FUC_SZ = 10 val FU_X = BitPat.dontCare(FUC_SZ) val FU_ALU = 1.U(FUC_SZ.W) val FU_JMP = 2.U(FUC_SZ.W) val FU_MEM = 4.U(FUC_SZ.W) val FU_MUL = 8.U(FUC_SZ.W) val FU_DIV = 16.U(FUC_SZ.W) val FU_CSR = 32.U(FUC_SZ.W) val FU_FPU = 64.U(FUC_SZ.W) val FU_FDV = 128.U(FUC_SZ.W) val FU_I2F = 256.U(FUC_SZ.W) val FU_F2I = 512.U(FUC_SZ.W) // FP stores generate data through FP F2I, and generate address through MemAddrCalc val FU_F2IMEM = 516.U(FUC_SZ.W) } import FUConstants._ /* * Class to tell the FUDecoders what units it needs to support * * @param alu support alu unit? * @param bru support br unit? * @param mem support mem unit? * @param muld support multiple div unit? * @param fpu support FP unit? * @param csr support csr writing unit? * @param fdiv support FP div unit? * @param ifpu support int to FP unit? / class SupportedFuncUnits( val alu: Boolean = false, val jmp: Boolean = false, val mem: Boolean = false, val muld: Boolean = false, val fpu: Boolean = false, val csr: Boolean = false, val fdiv: Boolean = false, val ifpu: Boolean = false) { } /* * Bundle for signals sent to the functional unit * * @param dataWidth width of the data sent to the functional unit / class FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val numOperands = 3 val rs1_data = UInt(dataWidth.W) val rs2_data = UInt(dataWidth.W) val rs3_data = UInt(dataWidth.W) // only used for FMA units val pred_data = Bool() val kill = Bool() // kill everything } /* * Bundle for the signals sent out of the function unit * * @param dataWidth data sent from the functional unit / class FuncUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val predicated = Bool() // Was this response from a predicated-off instruction val data = UInt(dataWidth.W) val fflags = new ValidIO(new FFlagsResp) val addr = UInt((vaddrBits+1).W) // only for maddr -> LSU val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc } /* * Branch resolution information given from the branch unit / class BrResolutionInfo(implicit p: Parameters) extends BoomBundle { val uop = new MicroOp val valid = Bool() val mispredict = Bool() val taken = Bool() // which direction did the branch go? val cfi_type = UInt(CFI_SZ.W) // Info for recalculating the pc for this branch val pc_sel = UInt(2.W) val jalr_target = UInt(vaddrBitsExtended.W) val target_offset = SInt() } class BrUpdateInfo(implicit p: Parameters) extends BoomBundle { // On the first cycle we get masks to kill registers val b1 = new BrUpdateMasks // On the second cycle we get indices to reset pointers val b2 = new BrResolutionInfo } class BrUpdateMasks(implicit p: Parameters) extends BoomBundle { val resolve_mask = UInt(maxBrCount.W) val mispredict_mask = UInt(maxBrCount.W) } /* * Abstract top level functional unit class that wraps a lower level hand made functional unit * * @param isPipelined is the functional unit pipelined? * @param numStages how many pipeline stages does the functional unit have * @param numBypassStages how many bypass stages does the function unit have * @param dataWidth width of the data being operated on in the functional unit * @param hasBranchUnit does this functional unit have a branch unit? / abstract class FunctionalUnit( val isPipelined: Boolean, val numStages: Int, val numBypassStages: Int, val dataWidth: Int, val isJmpUnit: Boolean = false, val isAluUnit: Boolean = false, val isMemAddrCalcUnit: Boolean = false, val needsFcsr: Boolean = false) (implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth))) val resp = (new DecoupledIO(new FuncUnitResp(dataWidth))) val brupdate = Input(new BrUpdateInfo()) val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth)))) // only used by the fpu unit val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null // only used by branch unit val brinfo = if (isAluUnit) Output(new BrResolutionInfo()) else null val get_ftq_pc = if (isJmpUnit) Flipped(new GetPCFromFtqIO()) else null val status = if (isMemAddrCalcUnit) Input(new freechips.rocketchip.rocket.MStatus()) else null // only used by memaddr calc unit val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null }) io.bypass.foreach { b => b.valid := false.B; b.bits := DontCare } io.resp.valid := false.B io.resp.bits := DontCare if (isJmpUnit) { io.get_ftq_pc.ftq_idx := DontCare } } /* * Abstract top level pipelined functional unit * * Note: this helps track which uops get killed while in intermediate stages, * but it is the job of the consumer to check for kills on the same cycle as consumption!!! * * @param numStages how many pipeline stages does the functional unit have * @param numBypassStages how many bypass stages does the function unit have * @param earliestBypassStage first stage that you can start bypassing from * @param dataWidth width of the data being operated on in the functional unit * @param hasBranchUnit does this functional unit have a branch unit? / abstract class PipelinedFunctionalUnit( numStages: Int, numBypassStages: Int, earliestBypassStage: Int, dataWidth: Int, isJmpUnit: Boolean = false, isAluUnit: Boolean = false, isMemAddrCalcUnit: Boolean = false, needsFcsr: Boolean = false )(implicit p: Parameters) extends FunctionalUnit( isPipelined = true, numStages = numStages, numBypassStages = numBypassStages, dataWidth = dataWidth, isJmpUnit = isJmpUnit, isAluUnit = isAluUnit, isMemAddrCalcUnit = isMemAddrCalcUnit, needsFcsr = needsFcsr) { // Pipelined functional unit is always ready. io.req.ready := true.B if (numStages > 0) { val r_valids = RegInit(VecInit(Seq.fill(numStages) { false.B })) val r_uops = Reg(Vec(numStages, new MicroOp())) // handle incoming request r_valids(0) := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill r_uops(0) := io.req.bits.uop r_uops(0).br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop) // handle middle of the pipeline for (i <- 1 until numStages) { r_valids(i) := r_valids(i-1) && !IsKilledByBranch(io.brupdate, r_uops(i-1)) && !io.req.bits.kill r_uops(i) := r_uops(i-1) r_uops(i).br_mask := GetNewBrMask(io.brupdate, r_uops(i-1)) if (numBypassStages > 0) { io.bypass(i-1).bits.uop := r_uops(i-1) } } // handle outgoing (branch could still kill it) // consumer must also check for pipeline flushes (kills) io.resp.valid := r_valids(numStages-1) && !IsKilledByBranch(io.brupdate, r_uops(numStages-1)) io.resp.bits.predicated := false.B io.resp.bits.uop := r_uops(numStages-1) io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_uops(numStages-1)) // bypassing (TODO allow bypass vector to have a different size from numStages) if (numBypassStages > 0 && earliestBypassStage == 0) { io.bypass(0).bits.uop := io.req.bits.uop for (i <- 1 until numBypassStages) { io.bypass(i).bits.uop := r_uops(i-1) } } } else { require (numStages == 0) // pass req straight through to response // valid doesn't check kill signals, let consumer deal with it. // The LSU already handles it and this hurts critical path. io.resp.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) io.resp.bits.predicated := false.B io.resp.bits.uop := io.req.bits.uop io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop) } } /* * Functional unit that wraps RocketChips ALU * * @param isBranchUnit is this a branch unit? * @param numStages how many pipeline stages does the functional unit have * @param dataWidth width of the data being operated on in the functional unit / class ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = numStages, numBypassStages = numStages, isAluUnit = true, earliestBypassStage = 0, dataWidth = dataWidth, isJmpUnit = isJmpUnit) with boom.v3.ifu.HasBoomFrontendParameters { val uop = io.req.bits.uop // immediate generation val imm_xprlen = ImmGen(uop.imm_packed, uop.ctrl.imm_sel) // operand 1 select var op1_data: UInt = null if (isJmpUnit) { // Get the uop PC for jumps val block_pc = AlignPCToBoundary(io.get_ftq_pc.pc, icBlockBytes) val uop_pc = (block_pc \| uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U) op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data, Mux(uop.ctrl.op1_sel.asUInt === OP1_PC , Sext(uop_pc, xLen), 0.U)) } else { op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data, 0.U) } // operand 2 select val op2_data = Mux(uop.ctrl.op2_sel === OP2_IMM, Sext(imm_xprlen.asUInt, xLen), Mux(uop.ctrl.op2_sel === OP2_IMMC, io.req.bits.uop.prs1(4,0), Mux(uop.ctrl.op2_sel === OP2_RS2 , io.req.bits.rs2_data, Mux(uop.ctrl.op2_sel === OP2_NEXT, Mux(uop.is_rvc, 2.U, 4.U), 0.U)))) val alu = Module(new freechips.rocketchip.rocket.ALU()) alu.io.in1 := op1_data.asUInt alu.io.in2 := op2_data.asUInt alu.io.fn := uop.ctrl.op_fcn alu.io.dw := uop.ctrl.fcn_dw // Did I just get killed by the previous cycle's branch, // or by a flush pipeline? val killed = WireInit(false.B) when (io.req.bits.kill \|\| IsKilledByBranch(io.brupdate, uop)) { killed := true.B } val rs1 = io.req.bits.rs1_data val rs2 = io.req.bits.rs2_data val br_eq = (rs1 === rs2) val br_ltu = (rs1.asUInt < rs2.asUInt) val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu \| rs1(xLen-1) & ~rs2(xLen-1)).asBool val pc_sel = MuxLookup(uop.ctrl.br_type, PC_PLUS4)( Seq( BR_N -> PC_PLUS4, BR_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4), BR_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4), BR_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4), BR_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4), BR_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4), BR_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4), BR_J -> PC_BRJMP, BR_JR -> PC_JALR )) val is_taken = io.req.valid && !killed && (uop.is_br \|\| uop.is_jalr \|\| uop.is_jal) && (pc_sel =/= PC_PLUS4) // "mispredict" means that a branch has been resolved and it must be killed val mispredict = WireInit(false.B) val is_br = io.req.valid && !killed && uop.is_br && !uop.is_sfb val is_jal = io.req.valid && !killed && uop.is_jal val is_jalr = io.req.valid && !killed && uop.is_jalr when (is_br \|\| is_jalr) { if (!isJmpUnit) { assert (pc_sel =/= PC_JALR) } when (pc_sel === PC_PLUS4) { mispredict := uop.taken } when (pc_sel === PC_BRJMP) { mispredict := !uop.taken } } val brinfo = Wire(new BrResolutionInfo) // note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit brinfo.valid := is_br \|\| is_jalr brinfo.mispredict := mispredict brinfo.uop := uop brinfo.cfi_type := Mux(is_jalr, CFI_JALR, Mux(is_br , CFI_BR, CFI_X)) brinfo.taken := is_taken brinfo.pc_sel := pc_sel brinfo.jalr_target := DontCare // Branch/Jump Target Calculation // For jumps we read the FTQ, and can calculate the target // For branches we emit the offset for the core to redirect if necessary val target_offset = imm_xprlen(20,0).asSInt brinfo.jalr_target := DontCare if (isJmpUnit) { def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) { ea } else { // Efficient means to compress 64-bit VA into vaddrBits+1 bits. // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)). val a = a0.asSInt >> vaddrBits val msb = Mux(a === 0.S \|\| a === -1.S, ea(vaddrBits), !ea(vaddrBits-1)) Cat(msb, ea(vaddrBits-1,0)) } val jalr_target_base = io.req.bits.rs1_data.asSInt val jalr_target_xlen = Wire(UInt(xLen.W)) jalr_target_xlen := (jalr_target_base + target_offset).asUInt val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt brinfo.jalr_target := jalr_target val cfi_idx = ((uop.pc_lob ^ Mux(io.get_ftq_pc.entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1) when (pc_sel === PC_JALR) { mispredict := !io.get_ftq_pc.next_val \|\| (io.get_ftq_pc.next_pc =/= jalr_target) \|\| !io.get_ftq_pc.entry.cfi_idx.valid \|\| (io.get_ftq_pc.entry.cfi_idx.bits =/= cfi_idx) } } brinfo.target_offset := target_offset io.brinfo := brinfo // Response // TODO add clock gate on resp bits from functional units // io.resp.bits.data := RegEnable(alu.io.out, io.req.valid) // val reg_data = Reg(outType = Bits(width = xLen)) // reg_data := alu.io.out // io.resp.bits.data := reg_data val r_val = RegInit(VecInit(Seq.fill(numStages) { false.B })) val r_data = Reg(Vec(numStages, UInt(xLen.W))) val r_pred = Reg(Vec(numStages, Bool())) val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data, Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data), Mux(io.req.bits.uop.uopc === uopMOV, io.req.bits.rs2_data, alu.io.out)) r_val (0) := io.req.valid r_data(0) := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out) r_pred(0) := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data for (i <- 1 until numStages) { r_val(i) := r_val(i-1) r_data(i) := r_data(i-1) r_pred(i) := r_pred(i-1) } io.resp.bits.data := r_data(numStages-1) io.resp.bits.predicated := r_pred(numStages-1) // Bypass // for the ALU, we can bypass same cycle as compute require (numStages >= 1) require (numBypassStages >= 1) io.bypass(0).valid := io.req.valid io.bypass(0).bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out) for (i <- 1 until numStages) { io.bypass(i).valid := r_val(i-1) io.bypass(i).bits.data := r_data(i-1) } // Exceptions io.resp.bits.fflags.valid := false.B } /* * Functional unit that passes in base+imm to calculate addresses, and passes store data * to the LSU. * For floating point, 65bit FP store-data needs to be decoded into 64bit FP form / class MemAddrCalcUnit(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = 0, numBypassStages = 0, earliestBypassStage = 0, dataWidth = 65, // TODO enable this only if FP is enabled? isMemAddrCalcUnit = true) with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { // perform address calculation val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U, sum(63,vaddrBits) =/= 0.U) val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt val store_data = io.req.bits.rs2_data io.resp.bits.addr := effective_address io.resp.bits.data := store_data if (dataWidth > 63) { assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.resp.bits.data(64).asBool === true.B), "65th bit set in MemAddrCalcUnit.") assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val), "FP store-data should now be going through a different unit.") } assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/= uopLD && io.req.bits.uop.uopc =/= uopSTA), "[maddrcalc] assert we never get store data in here.") // Handle misaligned exceptions val size = io.req.bits.uop.mem_size val misaligned = (size === 1.U && (effective_address(0) =/= 0.U)) \|\| (size === 2.U && (effective_address(1,0) =/= 0.U)) \|\| (size === 3.U && (effective_address(2,0) =/= 0.U)) val bkptu = Module(new BreakpointUnit(nBreakpoints)) bkptu.io.status := io.status bkptu.io.bp := io.bp bkptu.io.pc := DontCare bkptu.io.ea := effective_address bkptu.io.mcontext := io.mcontext bkptu.io.scontext := io.scontext val ma_ld = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned val ma_st = io.req.valid && (io.req.bits.uop.uopc === uopSTA \|\| io.req.bits.uop.uopc === uopAMO_AG) && misaligned val dbg_bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.debug_ld) \|\| (io.req.bits.uop.uopc === uopSTA && bkptu.io.debug_st)) val bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.xcpt_ld) \|\| (io.req.bits.uop.uopc === uopSTA && bkptu.io.xcpt_st)) def checkExceptions(x: Seq[(Bool, UInt)]) = (x.map(_._1).reduce(_\|\|_), PriorityMux(x)) val (xcpt_val, xcpt_cause) = checkExceptions(List( (ma_ld, (Causes.misaligned_load).U), (ma_st, (Causes.misaligned_store).U), (dbg_bp, (CSR.debugTriggerCause).U), (bp, (Causes.breakpoint).U))) io.resp.bits.mxcpt.valid := xcpt_val io.resp.bits.mxcpt.bits := xcpt_cause assert (!(ma_ld && ma_st), "Mutually-exclusive exceptions are firing.") io.resp.bits.sfence.valid := io.req.valid && io.req.bits.uop.mem_cmd === M_SFENCE io.resp.bits.sfence.bits.rs1 := io.req.bits.uop.mem_size(0) io.resp.bits.sfence.bits.rs2 := io.req.bits.uop.mem_size(1) io.resp.bits.sfence.bits.addr := io.req.bits.rs1_data io.resp.bits.sfence.bits.asid := io.req.bits.rs2_data } /* * Functional unit to wrap lower level FPU * * Currently, bypassing is unsupported! * All FP instructions are padded out to the max latency unit for easy * write-port scheduling. / class FPUUnit(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = p(tile.TileKey).core.fpu.get.dfmaLatency, numBypassStages = 0, earliestBypassStage = 0, dataWidth = 65, needsFcsr = true) { val fpu = Module(new FPU()) fpu.io.req.valid := io.req.valid fpu.io.req.bits.uop := io.req.bits.uop fpu.io.req.bits.rs1_data := io.req.bits.rs1_data fpu.io.req.bits.rs2_data := io.req.bits.rs2_data fpu.io.req.bits.rs3_data := io.req.bits.rs3_data fpu.io.req.bits.fcsr_rm := io.fcsr_rm io.resp.bits.data := fpu.io.resp.bits.data io.resp.bits.fflags.valid := fpu.io.resp.bits.fflags.valid io.resp.bits.fflags.bits.uop := io.resp.bits.uop io.resp.bits.fflags.bits.flags := fpu.io.resp.bits.fflags.bits.flags // kill me now } /* * Int to FP conversion functional unit * * @param latency the amount of stages to delay by / class IntToFPUnit(latency: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = latency, numBypassStages = 0, earliestBypassStage = 0, dataWidth = 65, needsFcsr = true) with tile.HasFPUParameters { val fp_decoder = Module(new UOPCodeFPUDecoder) // TODO use a simpler decoder val io_req = io.req.bits fp_decoder.io.uopc := io_req.uop.uopc val fp_ctrl = fp_decoder.io.sigs val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io_req.uop.imm_packed)) val req = Wire(new tile.FPInput) val tag = fp_ctrl.typeTagIn req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl req.rm := fp_rm req.in1 := unbox(io_req.rs1_data, tag, None) req.in2 := unbox(io_req.rs2_data, tag, None) req.in3 := DontCare req.typ := ImmGenTyp(io_req.uop.imm_packed) req.fmt := DontCare // FIXME: this may not be the right thing to do here req.fmaCmd := DontCare assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool), "[func] IntToFP integer input has 65th high-order bit set!") assert (!(io.req.valid && !fp_ctrl.fromint), "[func] Only support fromInt micro-ops.") val ifpu = Module(new tile.IntToFP(intToFpLatency)) ifpu.io.in.valid := io.req.valid ifpu.io.in.bits := req ifpu.io.in.bits.in1 := io_req.rs1_data val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits //io.resp.bits.data := box(ifpu.io.out.bits.data, !io.resp.bits.uop.fp_single) io.resp.bits.data := box(ifpu.io.out.bits.data, out_double) io.resp.bits.fflags.valid := ifpu.io.out.valid io.resp.bits.fflags.bits.uop := io.resp.bits.uop io.resp.bits.fflags.bits.flags := ifpu.io.out.bits.exc } /* * Iterative/unpipelined functional unit, can only hold a single MicroOp at a time * assumes at least one register between request and response * * TODO allow up to N micro-ops simultaneously. * * @param dataWidth width of the data to be passed into the functional unit / abstract class IterativeFunctionalUnit(dataWidth: Int)(implicit p: Parameters) extends FunctionalUnit( isPipelined = false, numStages = 1, numBypassStages = 0, dataWidth = dataWidth) { val r_uop = Reg(new MicroOp()) val do_kill = Wire(Bool()) do_kill := io.req.bits.kill // irrelevant default when (io.req.fire) { // update incoming uop do_kill := IsKilledByBranch(io.brupdate, io.req.bits.uop) \|\| io.req.bits.kill r_uop := io.req.bits.uop r_uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop) } .otherwise { do_kill := IsKilledByBranch(io.brupdate, r_uop) \|\| io.req.bits.kill r_uop.br_mask := GetNewBrMask(io.brupdate, r_uop) } // assumes at least one pipeline register between request and response io.resp.bits.uop := r_uop } /* * Divide functional unit. * * @param dataWidth data to be passed into the functional unit / class DivUnit(dataWidth: Int)(implicit p: Parameters) extends IterativeFunctionalUnit(dataWidth) { // We don't use the iterative multiply functionality here. // Instead we use the PipelinedMultiplier val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth)) // request div.io.req.valid := io.req.valid && !this.do_kill div.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw div.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn div.io.req.bits.in1 := io.req.bits.rs1_data div.io.req.bits.in2 := io.req.bits.rs2_data div.io.req.bits.tag := DontCare io.req.ready := div.io.req.ready // handle pipeline kills and branch misspeculations div.io.kill := this.do_kill // response io.resp.valid := div.io.resp.valid && !this.do_kill div.io.resp.ready := io.resp.ready io.resp.bits.data := div.io.resp.bits.data } /* * Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier * * @param numStages number of pipeline stages * @param dataWidth size of the data being passed into the functional unit */ class PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = numStages, numBypassStages = 0, earliestBypassStage = 0, dataWidth = dataWidth) { val imul = Module(new PipelinedMultiplier(xLen, numStages)) // request imul.io.req.valid := io.req.valid imul.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn imul.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw imul.io.req.bits.in1 := io.req.bits.rs1_data imul.io.req.bits.in2 := io.req.bits.rs2_data imul.io.req.bits.tag := DontCare // response io.resp.bits.data := imul.io.resp.bits.data }	module IntToFPUnit_1( // @[functional-unit.scala:591:7] input clock, // @[functional-unit.scala:591:7] input reset, // @[functional-unit.scala:591:7] input io_req_valid, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14] input [7:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14] input io_req_bits_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_req_bits_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14] input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14] input io_req_bits_kill, // @[functional-unit.scala:168:14] output io_resp_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [7:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [64:0] io_resp_bits_data, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_fflags_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_fflags_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [7:0] io_resp_bits_fflags_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_fflags_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_fflags_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_pdst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_prs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_prs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_prs3, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_fflags_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_flags, // @[functional-unit.scala:168:14] input [7:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14] input io_brupdate_b2_valid, // @[functional-unit.scala:168:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14] input io_brupdate_b2_taken, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14] input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14] input [2:0] io_fcsr_rm // @[functional-unit.scala:168:14] ); wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:591:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:591:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:591:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:591:7] wire [7:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_br_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:591:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:591:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[functional-unit.scala:591:7] wire [64:0] _ifpu_io_out_bits_data; // @[functional-unit.scala:624:20] wire [1:0] _fp_decoder_io_sigs_typeTagIn; // @[functional-unit.scala:600:26] wire [1:0] _fp_decoder_io_sigs_typeTagOut; // @[functional-unit.scala:600:26] wire _fp_decoder_io_sigs_fromint; // @[functional-unit.scala:600:26] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:591:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:591:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:591:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:591:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:591:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:591:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:591:7] wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:591:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:591:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:591:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:591:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:591:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:591:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:591:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:591:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:591:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:591:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:591:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:591:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:591:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:591:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:591:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:591:7] wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:591:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:591:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:591:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:591:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:591:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:591:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:591:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:591:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:591:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:591:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:591:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:591:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:591:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:591:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:591:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:591:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[functional-unit.scala:591:7] wire io_req_ready = 1'h1; // @[functional-unit.scala:591:7] wire _io_resp_bits_data_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42] wire _io_resp_bits_data_opts_bigger_T = 1'h1; // @[FPU.scala:249:56] wire [64:0] io_req_bits_rs3_data = 65'h0; // @[functional-unit.scala:591:7] wire [64:0] req_in3 = 65'h0; // @[functional-unit.scala:605:17] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_ready = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_mxcpt_valid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_valid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_asid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:591:7] wire _r_valids_WIRE_0 = 1'h0; // @[functional-unit.scala:236:35] wire _r_valids_WIRE_1 = 1'h0; // @[functional-unit.scala:236:35] wire req_vec = 1'h0; // @[functional-unit.scala:605:17] wire [39:0] io_resp_bits_addr = 40'h0; // @[functional-unit.scala:591:7] wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[functional-unit.scala:591:7] wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26] wire [1:0] req_fmaCmd = 2'h0; // @[functional-unit.scala:605:17] wire [1:0] req_fmt = 2'h0; // @[functional-unit.scala:605:17] wire _io_resp_valid_T_3; // @[functional-unit.scala:257:47] wire [6:0] io_resp_bits_fflags_bits_uop_uopc_0 = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_fflags_bits_uop_inst_0 = io_resp_bits_uop_inst_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst_0 = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_rvc_0 = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:591:7] wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc_0 = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:591:7] wire [9:0] io_resp_bits_fflags_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type_0 = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_load_0 = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_sta_0 = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_std_0 = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_iw_state_0 = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_br_0 = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_jalr_0 = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_jal_0 = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_sfb_0 = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:591:7] wire [7:0] _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [7:0] io_resp_bits_fflags_bits_uop_br_mask_0 = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_br_tag_0 = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_ftq_idx_0 = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_edge_inst_0 = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob_0 = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_taken_0 = io_resp_bits_uop_taken_0; // @[functional-unit.scala:591:7] wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed_0 = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:591:7] wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr_0 = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_rob_idx_0 = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ldq_idx_0 = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_stq_idx_0 = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx_0 = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_pdst_0 = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_prs1_0 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_prs2_0 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_prs3_0 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_ppred_0 = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs1_busy_0 = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs2_busy_0 = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs3_busy_0 = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ppred_busy_0 = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_stale_pdst_0 = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_exception_0 = io_resp_bits_uop_exception_0; // @[functional-unit.scala:591:7] wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause_0 = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bypassable_0 = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd_0 = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_mem_size_0 = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_mem_signed_0 = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_fence_0 = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_fencei_0 = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_amo_0 = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_uses_ldq_0 = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_uses_stq_0 = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_unique_0 = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_flush_on_commit_0 = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ldst_is_rs1_0 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_ldst_0 = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs1_0 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs2_0 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs3_0 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ldst_val_0 = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype_0 = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype_0 = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype_0 = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_frs3_en_0 = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_fp_val_0 = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_fp_single_0 = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_pf_if_0 = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_ae_if_0 = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_ma_if_0 = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bp_debug_if_0 = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bp_xcpt_if_0 = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc_0 = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc_0 = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:591:7] wire [64:0] _io_resp_bits_data_T_1; // @[package.scala:39:76] wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_valid_0; // @[functional-unit.scala:591:7] wire [64:0] io_resp_bits_data_0; // @[functional-unit.scala:591:7] wire io_resp_valid_0; // @[functional-unit.scala:591:7] reg r_valids_0; // @[functional-unit.scala:236:27] reg r_valids_1; // @[functional-unit.scala:236:27] reg [6:0] r_uops_0_uopc; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_inst; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_debug_inst; // @[functional-unit.scala:237:23] reg r_uops_0_is_rvc; // @[functional-unit.scala:237:23] reg [39:0] r_uops_0_debug_pc; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_iq_type; // @[functional-unit.scala:237:23] reg [9:0] r_uops_0_fu_code; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_iw_state; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_is_br; // @[functional-unit.scala:237:23] reg r_uops_0_is_jalr; // @[functional-unit.scala:237:23] reg r_uops_0_is_jal; // @[functional-unit.scala:237:23] reg r_uops_0_is_sfb; // @[functional-unit.scala:237:23] reg [7:0] r_uops_0_br_mask; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_br_tag; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ftq_idx; // @[functional-unit.scala:237:23] reg r_uops_0_edge_inst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_pc_lob; // @[functional-unit.scala:237:23] reg r_uops_0_taken; // @[functional-unit.scala:237:23] reg [19:0] r_uops_0_imm_packed; // @[functional-unit.scala:237:23] reg [11:0] r_uops_0_csr_addr; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_rob_idx; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ldq_idx; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_stq_idx; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_rxq_idx; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_pdst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_prs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_prs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_prs3; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ppred; // @[functional-unit.scala:237:23] reg r_uops_0_prs1_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs2_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs3_busy; // @[functional-unit.scala:237:23] reg r_uops_0_ppred_busy; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_stale_pdst; // @[functional-unit.scala:237:23] reg r_uops_0_exception; // @[functional-unit.scala:237:23] reg [63:0] r_uops_0_exc_cause; // @[functional-unit.scala:237:23] reg r_uops_0_bypassable; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_mem_cmd; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_mem_size; // @[functional-unit.scala:237:23] reg r_uops_0_mem_signed; // @[functional-unit.scala:237:23] reg r_uops_0_is_fence; // @[functional-unit.scala:237:23] reg r_uops_0_is_fencei; // @[functional-unit.scala:237:23] reg r_uops_0_is_amo; // @[functional-unit.scala:237:23] reg r_uops_0_uses_ldq; // @[functional-unit.scala:237:23] reg r_uops_0_uses_stq; // @[functional-unit.scala:237:23] reg r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23] reg r_uops_0_is_unique; // @[functional-unit.scala:237:23] reg r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_ldst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs3; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_val; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_dst_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23] reg r_uops_0_frs3_en; // @[functional-unit.scala:237:23] reg r_uops_0_fp_val; // @[functional-unit.scala:237:23] reg r_uops_0_fp_single; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_uopc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uopc_0 = r_uops_1_uopc; // @[functional-unit.scala:237:23, :591:7] reg [31:0] r_uops_1_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_inst_0 = r_uops_1_inst; // @[functional-unit.scala:237:23, :591:7] reg [31:0] r_uops_1_debug_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_inst_0 = r_uops_1_debug_inst; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_rvc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_rvc_0 = r_uops_1_is_rvc; // @[functional-unit.scala:237:23, :591:7] reg [39:0] r_uops_1_debug_pc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_pc_0 = r_uops_1_debug_pc; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_iq_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iq_type_0 = r_uops_1_iq_type; // @[functional-unit.scala:237:23, :591:7] reg [9:0] r_uops_1_fu_code; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fu_code_0 = r_uops_1_fu_code; // @[functional-unit.scala:237:23, :591:7] reg [3:0] r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_br_type_0 = r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_load_0 = r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_sta_0 = r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_std_0 = r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_iw_state; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_state_0 = r_uops_1_iw_state; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_br; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_br_0 = r_uops_1_is_br; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_jalr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jalr_0 = r_uops_1_is_jalr; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_jal; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jal_0 = r_uops_1_is_jal; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_sfb; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sfb_0 = r_uops_1_is_sfb; // @[functional-unit.scala:237:23, :591:7] reg [7:0] r_uops_1_br_mask; // @[functional-unit.scala:237:23] reg [2:0] r_uops_1_br_tag; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_br_tag_0 = r_uops_1_br_tag; // @[functional-unit.scala:237:23, :591:7] reg [3:0] r_uops_1_ftq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ftq_idx_0 = r_uops_1_ftq_idx; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_edge_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_edge_inst_0 = r_uops_1_edge_inst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_pc_lob; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pc_lob_0 = r_uops_1_pc_lob; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_taken; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_taken_0 = r_uops_1_taken; // @[functional-unit.scala:237:23, :591:7] reg [19:0] r_uops_1_imm_packed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_imm_packed_0 = r_uops_1_imm_packed; // @[functional-unit.scala:237:23, :591:7] reg [11:0] r_uops_1_csr_addr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_csr_addr_0 = r_uops_1_csr_addr; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_rob_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rob_idx_0 = r_uops_1_rob_idx; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ldq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldq_idx_0 = r_uops_1_ldq_idx; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_stq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stq_idx_0 = r_uops_1_stq_idx; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_rxq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rxq_idx_0 = r_uops_1_rxq_idx; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pdst_0 = r_uops_1_pdst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_prs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_0 = r_uops_1_prs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_prs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_0 = r_uops_1_prs2; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_prs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_0 = r_uops_1_prs3; // @[functional-unit.scala:237:23, :591:7] reg [3:0] r_uops_1_ppred; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_0 = r_uops_1_ppred; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs1_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_busy_0 = r_uops_1_prs1_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs2_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_busy_0 = r_uops_1_prs2_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs3_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_busy_0 = r_uops_1_prs3_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ppred_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_busy_0 = r_uops_1_ppred_busy; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_stale_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stale_pdst_0 = r_uops_1_stale_pdst; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_exception; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exception_0 = r_uops_1_exception; // @[functional-unit.scala:237:23, :591:7] reg [63:0] r_uops_1_exc_cause; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exc_cause_0 = r_uops_1_exc_cause; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bypassable; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bypassable_0 = r_uops_1_bypassable; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_mem_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_cmd_0 = r_uops_1_mem_cmd; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_mem_size; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_size_0 = r_uops_1_mem_size; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_mem_signed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_signed_0 = r_uops_1_mem_signed; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_fence; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fence_0 = r_uops_1_is_fence; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_fencei; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fencei_0 = r_uops_1_is_fencei; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_amo; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_amo_0 = r_uops_1_is_amo; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_uses_ldq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_ldq_0 = r_uops_1_uses_ldq; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_uses_stq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_stq_0 = r_uops_1_uses_stq; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_unique; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_unique_0 = r_uops_1_is_unique; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_flush_on_commit_0 = r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_is_rs1_0 = r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_ldst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_0 = r_uops_1_ldst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_0 = r_uops_1_lrs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_0 = r_uops_1_lrs2; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs3_0 = r_uops_1_lrs3; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ldst_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_val_0 = r_uops_1_ldst_val; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_dst_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_dst_rtype_0 = r_uops_1_dst_rtype; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_rtype_0 = r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_rtype_0 = r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_frs3_en; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_frs3_en_0 = r_uops_1_frs3_en; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_fp_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_val_0 = r_uops_1_fp_val; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_fp_single; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_single_0 = r_uops_1_fp_single; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_pf_if_0 = r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ae_if_0 = r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ma_if_0 = r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_debug_if_0 = r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_xcpt_if_0 = r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_fsrc_0 = r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_tsrc_0 = r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23, :591:7] wire [7:0] _r_valids_0_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51] wire _r_valids_0_T_1 = \|_r_valids_0_T; // @[util.scala:118:{51,59}] wire _r_valids_0_T_2 = ~_r_valids_0_T_1; // @[util.scala:118:59] wire _r_valids_0_T_3 = io_req_valid_0 & _r_valids_0_T_2; // @[functional-unit.scala:240:{33,36}, :591:7] wire _r_valids_0_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :591:7] wire _r_valids_0_T_5 = _r_valids_0_T_3 & _r_valids_0_T_4; // @[functional-unit.scala:240:{33,84,87}] wire [7:0] _r_uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_uops_0_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uops_0_br_mask_T; // @[util.scala:85:{25,27}] wire [7:0] _r_valids_1_T = io_brupdate_b1_mispredict_mask_0 & r_uops_0_br_mask; // @[util.scala:118:51] wire _r_valids_1_T_1 = \|_r_valids_1_T; // @[util.scala:118:{51,59}] wire _r_valids_1_T_2 = ~_r_valids_1_T_1; // @[util.scala:118:59] wire _r_valids_1_T_3 = r_valids_0 & _r_valids_1_T_2; // @[functional-unit.scala:236:27, :246:{36,39}] wire _r_valids_1_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :591:7] wire _r_valids_1_T_5 = _r_valids_1_T_3 & _r_valids_1_T_4; // @[functional-unit.scala:246:{36,83,86}] wire [7:0] _r_uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_uops_1_br_mask_T_1 = r_uops_0_br_mask & _r_uops_1_br_mask_T; // @[util.scala:85:{25,27}] wire [7:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_uops_1_br_mask; // @[util.scala:118:51] wire _io_resp_valid_T_1 = \|_io_resp_valid_T; // @[util.scala:118:{51,59}] wire _io_resp_valid_T_2 = ~_io_resp_valid_T_1; // @[util.scala:118:59] assign _io_resp_valid_T_3 = r_valids_1 & _io_resp_valid_T_2; // @[functional-unit.scala:236:27, :257:{47,50}] assign io_resp_valid_0 = _io_resp_valid_T_3; // @[functional-unit.scala:257:47, :591:7] wire [7:0] _io_resp_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _io_resp_bits_uop_br_mask_T_1 = r_uops_1_br_mask & _io_resp_bits_uop_br_mask_T; // @[util.scala:85:{25,27}] assign io_resp_bits_uop_br_mask_0 = _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [2:0] _fp_rm_T = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire [2:0] _fp_rm_T_2 = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire _fp_rm_T_1 = &_fp_rm_T; // @[util.scala:289:58] wire [2:0] fp_rm = _fp_rm_T_1 ? io_fcsr_rm_0 : _fp_rm_T_2; // @[util.scala:289:58] wire [2:0] req_rm = fp_rm; // @[functional-unit.scala:604:18, :605:17] wire [1:0] _req_typ_T; // @[util.scala:295:59] wire [64:0] _req_in1_T_4; // @[FPU.scala:369:10] wire [64:0] _req_in2_T_4; // @[FPU.scala:369:10] wire req_ldst; // @[functional-unit.scala:605:17] wire req_wen; // @[functional-unit.scala:605:17] wire req_ren1; // @[functional-unit.scala:605:17] wire req_ren2; // @[functional-unit.scala:605:17] wire req_ren3; // @[functional-unit.scala:605:17] wire req_swap12; // @[functional-unit.scala:605:17] wire req_swap23; // @[functional-unit.scala:605:17] wire [1:0] req_typeTagIn; // @[functional-unit.scala:605:17] wire [1:0] req_typeTagOut; // @[functional-unit.scala:605:17] wire req_fromint; // @[functional-unit.scala:605:17] wire req_toint; // @[functional-unit.scala:605:17] wire req_fastpipe; // @[functional-unit.scala:605:17] wire req_fma; // @[functional-unit.scala:605:17] wire req_div; // @[functional-unit.scala:605:17] wire req_sqrt; // @[functional-unit.scala:605:17] wire req_wflags; // @[functional-unit.scala:605:17] wire [1:0] req_typ; // @[functional-unit.scala:605:17] wire [64:0] req_in1; // @[functional-unit.scala:605:17] wire [64:0] req_in2; // @[functional-unit.scala:605:17] wire _req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] req_in1_prev_unswizzled_hi = {_req_in1_prev_unswizzled_T, _req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] req_in1_prev_unswizzled = {req_in1_prev_unswizzled_hi, _req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire req_in1_prev_prev_sign = req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] req_in1_prev_prev_fractIn = req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] req_in1_prev_prev_expIn = req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _req_in1_prev_prev_fractOut_T = {req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] req_in1_prev_prev_fractOut = _req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] req_in1_prev_prev_expOut_expCode = req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _req_in1_prev_prev_expOut_commonCase_T = {4'h0, req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _req_in1_prev_prev_expOut_commonCase_T_1 = _req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] req_in1_prev_prev_expOut_commonCase = _req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _req_in1_prev_prev_expOut_T_5 = req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _req_in1_prev_prev_expOut_T = req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _req_in1_prev_prev_expOut_T_1 = req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _req_in1_prev_prev_expOut_T_2 = _req_in1_prev_prev_expOut_T \| _req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _req_in1_prev_prev_expOut_T_3 = req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _req_in1_prev_prev_expOut_T_4 = {req_in1_prev_prev_expOut_expCode, _req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] req_in1_prev_prev_expOut = _req_in1_prev_prev_expOut_T_2 ? _req_in1_prev_prev_expOut_T_4 : _req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] req_in1_prev_prev_hi = {req_in1_prev_prev_sign, req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] req_in1_floats_0 = {req_in1_prev_prev_hi, req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire req_in1_prev_isbox = &_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire req_in1_oks_0 = req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _req_in1_truncIdx_T; // @[package.scala:38:21] wire req_in1_truncIdx = _req_in1_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _req_in1_T = req_in1_truncIdx; // @[package.scala:38:47, :39:86] wire _req_in1_T_1 = _req_in1_T \| req_in1_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _req_in1_truncIdx_T_1; // @[package.scala:38:21] wire req_in1_truncIdx_1 = _req_in1_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _req_in1_T_2 = req_in1_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _req_in1_T_3 = _req_in1_T_2 ? io_req_bits_rs1_data_0 : req_in1_floats_0; // @[package.scala:39:{76,86}] assign _req_in1_T_4 = _req_in1_T_1 ? _req_in1_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign req_in1 = _req_in1_T_4; // @[FPU.scala:369:10] wire _req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] req_in2_prev_unswizzled_hi = {_req_in2_prev_unswizzled_T, _req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] req_in2_prev_unswizzled = {req_in2_prev_unswizzled_hi, _req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire req_in2_prev_prev_sign = req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] req_in2_prev_prev_fractIn = req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] req_in2_prev_prev_expIn = req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _req_in2_prev_prev_fractOut_T = {req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] req_in2_prev_prev_fractOut = _req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] req_in2_prev_prev_expOut_expCode = req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _req_in2_prev_prev_expOut_commonCase_T = {4'h0, req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _req_in2_prev_prev_expOut_commonCase_T_1 = _req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] req_in2_prev_prev_expOut_commonCase = _req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _req_in2_prev_prev_expOut_T_5 = req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _req_in2_prev_prev_expOut_T = req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _req_in2_prev_prev_expOut_T_1 = req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _req_in2_prev_prev_expOut_T_2 = _req_in2_prev_prev_expOut_T \| _req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _req_in2_prev_prev_expOut_T_3 = req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _req_in2_prev_prev_expOut_T_4 = {req_in2_prev_prev_expOut_expCode, _req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] req_in2_prev_prev_expOut = _req_in2_prev_prev_expOut_T_2 ? _req_in2_prev_prev_expOut_T_4 : _req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] req_in2_prev_prev_hi = {req_in2_prev_prev_sign, req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] req_in2_floats_0 = {req_in2_prev_prev_hi, req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire req_in2_prev_isbox = &_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire req_in2_oks_0 = req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _req_in2_truncIdx_T; // @[package.scala:38:21] wire req_in2_truncIdx = _req_in2_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _req_in2_T = req_in2_truncIdx; // @[package.scala:38:47, :39:86] wire _req_in2_T_1 = _req_in2_T \| req_in2_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _req_in2_truncIdx_T_1; // @[package.scala:38:21] wire req_in2_truncIdx_1 = _req_in2_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _req_in2_T_2 = req_in2_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _req_in2_T_3 = _req_in2_T_2 ? io_req_bits_rs2_data_0 : req_in2_floats_0; // @[package.scala:39:{76,86}] assign _req_in2_T_4 = _req_in2_T_1 ? _req_in2_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign req_in2 = _req_in2_T_4; // @[FPU.scala:369:10] assign _req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59] assign req_typ = _req_typ_T; // @[util.scala:295:59]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_112( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_192 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_181( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_198 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }	module rockettile_icache_data_arrays_2( // @[DescribedSRAM.scala:17:26] input [6:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [255:0] RW0_wdata, output [255:0] RW0_rdata, input [7:0] RW0_wmask ); rockettile_icache_data_arrays_0_ext rockettile_icache_data_arrays_0_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_5( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [8:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [64:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [64:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [53:0] _roundMask_T = 54'h0; // @[RoundAnyRawFNToRecFN.scala:153:36] wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [55:0] roundMask = 56'h3; // @[RoundAnyRawFNToRecFN.scala:153:55] wire [56:0] _shiftedRoundMask_T = 57'h3; // @[RoundAnyRawFNToRecFN.scala:162:41] wire [55:0] shiftedRoundMask = 56'h1; // @[RoundAnyRawFNToRecFN.scala:162:53] wire [55:0] _roundPosMask_T = 56'hFFFFFFFFFFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28] wire [55:0] roundPosMask = 56'h2; // @[RoundAnyRawFNToRecFN.scala:163:46] wire [55:0] _roundedSig_T_10 = 56'hFFFFFFFFFFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32] wire [54:0] _roundedSig_T_6 = 55'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [54:0] _roundedSig_T_14 = 55'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [11:0] _expOut_T_6 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [11:0] _expOut_T_9 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [11:0] _expOut_T_12 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [11:0] _expOut_T_5 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [11:0] _expOut_T_8 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [11:0] _expOut_T_11 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:265:18] wire [11:0] _expOut_T_14 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [11:0] _expOut_T_16 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [11:0] _expOut_T_18 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:277:16] wire [11:0] _expOut_T_20 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:278:16] wire [51:0] _fractOut_T_2 = 52'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [51:0] _fractOut_T_4 = 52'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:288:41] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32] wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22] wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22] wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53, :288:41] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T \| _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire [12:0] _sAdjustedExp_T = {{4{io_in_sExp_0[8]}}, io_in_sExp_0} + 13'h780; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25] wire [11:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[11:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14] wire [12:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}] wire [54:0] _adjustedSig_T = io_in_sig_0[64:10]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23] wire [9:0] _adjustedSig_T_1 = io_in_sig_0[9:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26] wire _adjustedSig_T_2 = \|_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}] wire [55:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60] wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [55:0] _roundPosBit_T = adjustedSig & 56'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [55:0] _anyRoundExtra_T = adjustedSig & 56'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49] wire _GEN = roundingMode_near_even \| roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 \| _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [55:0] _roundedSig_T = adjustedSig \| 56'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32] wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [54:0] _roundedSig_T_7 = {54'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}] wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [55:0] _roundedSig_T_11 = adjustedSig & 56'hFFFFFFFFFFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}] wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [54:0] _roundedSig_T_15 = {54'h0, _roundedSig_T_13}; // @[RoundAnyRawFNToRecFN.scala:181:{24,42}] wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} \| _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [13:0] sRoundedExp = {sAdjustedExp[12], sAdjustedExp} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}] assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 \| _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T \| roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T_1 = roundMagUp \| roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [11:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [11:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [11:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17] wire [11:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [11:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [11:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15] wire [11:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73] wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}] wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? 52'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13] wire [51:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_175( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_431 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_191( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_447 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_175( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth2 - 1)) }) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) \|\| (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf \|\| io.b.isInf val notNaN_isZeroOut = io.a.isZero \|\| io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth2 - 1, 0) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ io.invalidExc := isSigNaNRawFloat(io.a) \|\| isSigNaNRawFloat(io.b) \|\| notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN \|\| io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module MulRecFN_39( // @[MulRecFN.scala:100:7] input [32:0] io_a, // @[MulRecFN.scala:102:16] input [32:0] io_b, // @[MulRecFN.scala:102:16] output [32:0] io_out // @[MulRecFN.scala:102:16] ); wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26] wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26] wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26] wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7] wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7] wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [32:0] io_out_0; // @[MulRecFN.scala:100:7] wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7] wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] MulRawFN_39 mulRawFN ( // @[MulRecFN.scala:113:26] .io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_invalidExc (_mulRawFN_io_invalidExc), .io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN), .io_rawOut_isInf (_mulRawFN_io_rawOut_isInf), .io_rawOut_isZero (_mulRawFN_io_rawOut_isZero), .io_rawOut_sign (_mulRawFN_io_rawOut_sign), .io_rawOut_sExp (_mulRawFN_io_rawOut_sExp), .io_rawOut_sig (_mulRawFN_io_rawOut_sig) ); // @[MulRecFN.scala:113:26] RoundRawFNToRecFN_e8_s24_111 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15] .io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26] .io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26] .io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26] .io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26] .io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26] .io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26] .io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulRecFN.scala:121:15] assign io_out = io_out_0; // @[MulRecFN.scala:100:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_79( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_92 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in \|\| corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ \|\| !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready \|\| !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel \| count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)outByteswidth-1, ioutByteswidth) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes8-1, edgeOut.manager.beatBytes8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid \|\| full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLWidthWidget32_12( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [255:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [255:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [255:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [255:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [255:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [255:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [255:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] wire [255:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] cated_bits_source; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] cated_bits_address; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_2 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_3 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25] wire [255:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [31:0] cated_bits_mask; // @[WidthWidget.scala:161:25] wire [255:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [191:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[255:64]; // @[Repeater.scala:36:26] wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25] wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [19:0] _repeat_limit_T = 20'h1F << cated_bits_size; // @[package.scala:243:71] wire [4:0] _repeat_limit_T_1 = _repeat_limit_T[4:0]; // @[package.scala:243:{71,76}] wire [4:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire [1:0] repeat_limit = _repeat_limit_T_2[4:3]; // @[package.scala:243:46] reg [1:0] repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = repeat_count == 2'h0; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T \| _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35] wire [2:0] _repeat_count_T = {1'h0, repeat_count} + 3'h1; // @[WidthWidget.scala:105:26, :110:24] wire [1:0] _repeat_count_T_1 = _repeat_count_T[1:0]; // @[WidthWidget.scala:110:24] wire [1:0] repeat_sel = cated_bits_address[4:3]; // @[WidthWidget.scala:116:39, :161:25] wire [1:0] repeat_index = repeat_sel \| repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24] wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_2 = cated_bits_data[191:128]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_2 = _repeat_anonOut_a_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_3 = cated_bits_data[255:192]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_3 = _repeat_anonOut_a_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [3:0][63:0] _GEN = {{repeat_anonOut_a_bits_data_mux_3}, {repeat_anonOut_a_bits_data_mux_2}, {repeat_anonOut_a_bits_data_mux_1}, {repeat_anonOut_a_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30] assign anonOut_a_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_2 = cated_bits_mask[23:16]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_2 = _repeat_anonOut_a_bits_mask_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_3 = cated_bits_mask[31:24]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_3 = _repeat_anonOut_a_bits_mask_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [3:0][7:0] _GEN_0 = {{repeat_anonOut_a_bits_mask_mux_3}, {repeat_anonOut_a_bits_mask_mux_2}, {repeat_anonOut_a_bits_mask_mux_1}, {repeat_anonOut_a_bits_mask_mux_0}}; // @[WidthWidget.scala:128:43, :140:53] assign anonOut_a_bits_mask = _GEN_0[repeat_index]; // @[WidthWidget.scala:126:24, :140:53] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [19:0] _limit_T = 20'h1F << anonOut_d_bits_size; // @[package.scala:243:71] wire [4:0] _limit_T_1 = _limit_T[4:0]; // @[package.scala:243:{71,76}] wire [4:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire [1:0] limit = _limit_T_2[4:3]; // @[package.scala:243:46] reg [1:0] count; // @[WidthWidget.scala:40:27] wire [1:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = count == 2'h0; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T \| _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire [1:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = \|_enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_3 = {count[1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = \|_enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_6 = count ^ 2'h2; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_8 = \|_enable_T_7; // @[WidthWidget.scala:43:{63,72}] wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_9 = ~count; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_11 = \|_enable_T_10; // @[WidthWidget.scala:43:{63,72}] wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = anonOut_d_bits_corrupt \| corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [2:0] _count_T = {1'h0, count} + 3'h1; // @[WidthWidget.scala:40:27, :50:24] wire [1:0] _count_T_1 = _count_T[1:0]; // @[WidthWidget.scala:50:24] wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonOut_d_ready_T_1 = anonIn_d_ready \| _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_0 = enable_0 \| _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_1 = enable_1 \| _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_2 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_2 = enable_2 \| _anonIn_d_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_3 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_3 = enable_3 \| _anonIn_d_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:66:24] wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_2 = anonIn_d_bits_data_masked_enable_2 ? anonIn_d_bits_data_odata_2 : anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_3 = anonIn_d_bits_data_masked_enable_3 ? anonIn_d_bits_data_odata_3 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35] wire [127:0] anonIn_d_bits_data_lo = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [127:0] anonIn_d_bits_data_hi = {anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_hi, anonIn_d_bits_data_lo}; // @[WidthWidget.scala:73:12] assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] repeat_count <= 2'h0; // @[WidthWidget.scala:105:26] count <= 2'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] end else begin // @[WidthWidget.scala:27:9] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= repeat_last ? 2'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35] count <= last ? 2'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23] end anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 \| anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] end if (_anonIn_d_bits_data_T_2) begin // @[WidthWidget.scala:69:23] anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_1 <= anonIn_d_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_2 <= anonIn_d_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88] end always @(posedge) TLMonitor_70 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleA_a32d256s5k3z4u_8 repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonIn_a_ready), .io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_source (cated_bits_source), .io_deq_bits_address (cated_bits_address), .io_deq_bits_mask (cated_bits_mask), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w4_d3_i0_60( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_521 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_522 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_523 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_524 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module InputUnit_54( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_4_1, // @[InputUnit.scala:170:14] input io_out_credit_available_4_2, // @[InputUnit.scala:170:14] input io_out_credit_available_4_3, // @[InputUnit.scala:170:14] input io_out_credit_available_4_4, // @[InputUnit.scala:170:14] input io_out_credit_available_4_5, // @[InputUnit.scala:170:14] input io_out_credit_available_4_6, // @[InputUnit.scala:170:14] input io_out_credit_available_4_7, // @[InputUnit.scala:170:14] input io_out_credit_available_3_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_2, // @[InputUnit.scala:170:14] input io_out_credit_available_3_3, // @[InputUnit.scala:170:14] input io_out_credit_available_3_4, // @[InputUnit.scala:170:14] input io_out_credit_available_3_5, // @[InputUnit.scala:170:14] input io_out_credit_available_3_6, // @[InputUnit.scala:170:14] input io_out_credit_available_3_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [7:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_7; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_7; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_7; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [7:0] mask; // @[InputUnit.scala:250:21] wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] vcalloc_sel = vcalloc_filter[7:0] \| vcalloc_filter[15:8]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_1 \| vcalloc_vals_2 \| vcalloc_vals_3 \| vcalloc_vals_4 \| vcalloc_vals_5 \| vcalloc_vals_6 \| vcalloc_vals_7; // @[package.scala:81:59] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_42( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLFragmenter( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [28:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9] wire [28:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36] wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50] wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50] wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49] wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59] wire find_0 = 1'h1; // @[Parameters.scala:616:12] wire [29:0] _find_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _find_T_3 = 30'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [28:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [11:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [11:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [28:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9] assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9] wire [7:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9] wire [11:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9] wire [28:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49] assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire [2:0] dFragnum = anonOut_d_bits_source[2:0]; // @[Fragmenter.scala:204:41] wire [2:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala:204:41, :206:30] wire _drop_T_1 = dLast; // @[Fragmenter.scala:206:30, :234:37] wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] dsizeOH = _dsizeOH_T; // @[OneHot.scala:65:{12,27}] wire [5:0] _dsizeOH1_T = 6'h7 << anonOut_d_bits_size; // @[package.scala:243:71] wire [2:0] _dsizeOH1_T_1 = _dsizeOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}] wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45] wire _ack_decrement_T = dsizeOH[3]; // @[OneHot.scala:65:27] wire ack_decrement = dHasData \| _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}] wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala:204:41, :218:47] wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:3], _dFirst_size_T[2:0] \| dsizeOH1}; // @[package.scala:243:46] wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35] wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}] wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53] wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}] wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}] wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18] wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18] wire _dFirst_size_T_7 = \|dFirst_size_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} \| dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28] wire _dFirst_size_T_9 = \|dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 \| dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28] wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}] wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}] wire [3:0] _acknum_T = {1'h0, acknum} - {3'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55] wire [2:0] _acknum_T_1 = _acknum_T[2:0]; // @[Fragmenter.scala:221:55] wire [2:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}] wire _dToggle_T = anonOut_d_bits_source[3]; // @[Fragmenter.scala:224:41] wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20] wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}] wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}] assign _anonOut_d_ready_T = anonIn_d_ready \| drop; // @[Fragmenter.scala:234:30, :235:35] assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39] assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}] assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign _anonIn_d_bits_source_T = anonOut_d_bits_source[11:4]; // @[Fragmenter.scala:238:47] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] wire [28:0] _find_T; // @[Parameters.scala:137:31] wire [29:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}] wire _limit_T = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49] wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31] wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}] wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71] wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}] wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30] wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46] wire [3:0] _old_gennum1_T_1 = {1'h0, gennum} - 4'h1; // @[Fragmenter.scala:303:29, :305:79] wire [2:0] _old_gennum1_T_2 = _old_gennum1_T_1[2:0]; // @[Fragmenter.scala:305:79] wire [2:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}] wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40] wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28] wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}] wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}] wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}] wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}] wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}] wire aLast = ~(\|aFragnum); // @[Fragmenter.scala:307:24, :308:30] reg aToggle_r; // @[Fragmenter.scala:309:54] wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}] wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}] wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31] wire _repeater_io_repeat_T_1 = \|aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53] wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}] wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65] wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T \| _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}] wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] \| aFragOH1}; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}] wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}] assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[28:6], _repeater_io_deq_bits_address[5:0] \| _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}] assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] wire [8:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aToggle}; // @[Fragmenter.scala:274:30, :309:23, :317:33] assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, aFragnum}; // @[Fragmenter.scala:307:24, :317:33] assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25]
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_413( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File LoopConv.scala: package gemmini import chisel3._ import chisel3.util._ import chisel3.experimental._ import freechips.rocketchip.tile.RoCCCommand import org.chipsalliance.cde.config.Parameters import GemminiISA._ import LocalAddr._ import Util._ class LoopConvOuterBounds(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int) extends Bundle { val batch_size = UInt(large_iterator_bitwidth.W) val in_row_dim = UInt(small_iterator_bitwidth.W) val in_col_dim = UInt(small_iterator_bitwidth.W) val in_channels = UInt(large_iterator_bitwidth.W) val out_channels = UInt(large_iterator_bitwidth.W) val out_col_dim = UInt(large_iterator_bitwidth.W) val out_row_dim = UInt(large_iterator_bitwidth.W) val out_stride = UInt(large_iterator_bitwidth.W) //stride for output activation val in_stride = UInt(large_iterator_bitwidth.W) //stride for input activation val weight_stride = UInt(large_iterator_bitwidth.W) //stride for weight val pool_out_row_dim = UInt(small_iterator_bitwidth.W) val pool_out_col_dim = UInt(small_iterator_bitwidth.W) val stride = UInt(tiny_iterator_bitwidth.W) val padding = UInt(tiny_iterator_bitwidth.W) val kernel_dim = UInt(tiny_iterator_bitwidth.W) val kernel_dilation = UInt(tiny_iterator_bitwidth.W) val pool_size = UInt(tiny_iterator_bitwidth.W) val pool_stride = UInt(tiny_iterator_bitwidth.W) val pool_padding = UInt(tiny_iterator_bitwidth.W) } class LoopConvInnerBounds(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int) extends Bundle { val batches = UInt(large_iterator_bitwidth.W) val porows = UInt(small_iterator_bitwidth.W) val pocols = UInt(small_iterator_bitwidth.W) val pochs = UInt(large_iterator_bitwidth.W) val krows = UInt(tiny_iterator_bitwidth.W) val kcols = UInt(tiny_iterator_bitwidth.W) val kchs = UInt(large_iterator_bitwidth.W) val lpad = UInt(tiny_iterator_bitwidth.W) val rpad = UInt(tiny_iterator_bitwidth.W) val upad = UInt(tiny_iterator_bitwidth.W) val dpad = UInt(tiny_iterator_bitwidth.W) val plpad = UInt(tiny_iterator_bitwidth.W) val prad = UInt(tiny_iterator_bitwidth.W) val pupad = UInt(tiny_iterator_bitwidth.W) val pdpad = UInt(tiny_iterator_bitwidth.W) val orows = UInt(small_iterator_bitwidth.W) val ocols = UInt(small_iterator_bitwidth.W) } class LoopConvDerivedParams(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int) extends Bundle { val ochs = UInt(large_iterator_bitwidth.W) val irows = UInt(small_iterator_bitwidth.W) val icols = UInt(small_iterator_bitwidth.W) val irows_unpadded = UInt(small_iterator_bitwidth.W) val icols_unpadded = UInt(small_iterator_bitwidth.W) val ichs = UInt(large_iterator_bitwidth.W) val out_channels_per_bank = UInt(small_iterator_bitwidth.W) // TODO this won't work for systolic arrays above 256 in size val in_channels_per_bank = UInt(small_iterator_bitwidth.W) // TODO this won't work for systolic arrays above 256 in size val bias_spad_stride = UInt(large_iterator_bitwidth.W) val input_spad_stride = UInt(large_iterator_bitwidth.W) val weight_spad_stride = UInt(large_iterator_bitwidth.W) // val ex_overwrite = Bool() } class LoopConvLdBiasReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_start = UInt(log2Up(max_acc_addr).W) val dram_addr = UInt(coreMaxAddrBits.W) val no_bias = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvLdBias(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_acc_addr: Int, acc_w: Int, max_block_len_acc: Int, concurrent_loops: Int, latency: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2)(implicit p: Parameters) extends Module { val MVIN_SCALE_IDENTITY = 0x3f800000.U // TODO get this from configs somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvLdBiasReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val wait_for_prev_loop = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, ld = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvLdBiasReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops)) import req.inner_bounds._ import req.derived_params._ val acc_addr_start = req.addr_start // Derived parameters val max_ochs_per_mvin = Mux(ochs < (max_block_len_acc * block_size).U, ochs, (max_block_len_acc * block_size).U) val skip = req.dram_addr === 0.U // Iterators val b = Reg(UInt(large_iterator_bitwidth.W)) val orow = Reg(UInt(small_iterator_bitwidth.W)) val ocol = Reg(UInt(small_iterator_bitwidth.W)) val och = Reg(UInt(large_iterator_bitwidth.W)) // Addresses val dram_offset = och * (acc_w/8).U val dram_addr = Mux(req.no_bias, 0.U, req.dram_addr + LoopConv.castDramOffset(dram_offset)) val spad_addr = acc_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol // Sizes val I = Mux(ocols - ocol > block_size.U, block_size.U, ocols - ocol) val J = Mux(ochs - och > max_ochs_per_mvin, max_ochs_per_mvin, ochs - och) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = UInt() val I = UInt() val J = UInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_mvin_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.scale := MVIN_SCALE_IDENTITY config_cmd_rs1.stride := req.derived_params.bias_spad_stride config_cmd_rs1.pixel_repeats := 1.U config_cmd_rs1.state_id := 2.U config_cmd_rs1.shrink := 0.U config_cmd_rs1._unused := 1.U config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := 0.U val mvin_cmd = Wire(new RoCCCommand) mvin_cmd := DontCare mvin_cmd.inst.funct := LOAD3_CMD mvin_cmd.rs1 := 0.U mvin_cmd.rs2 := 0.U // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !io.wait_for_prev_loop && !skip command_p.io.in.bits.cmd := Mux(state === config, config_cmd, mvin_cmd) command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.I := I command_p.io.in.bits.J := J command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === LOAD3_CMD) { val o = command_p.io.out.bits io.cmd.bits.rs1 := o.dram_addr val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType) mvin_cmd_rs2 := DontCare mvin_cmd_rs2.num_rows := o.I.asUInt mvin_cmd_rs2.num_cols := o.J.asUInt mvin_cmd_rs2.local_addr := cast_to_acc_addr(mvin_cmd_rs2.local_addr, o.spad_addr, accumulate = false.B, read_full = false.B) io.cmd.bits.rs2 := mvin_cmd_rs2.asUInt } // Sending outputs when (skip) { state := idle }.elsewhen(command_p.io.in.fire) { when (state === config) { state := ld }.otherwise { val next_och = floorAdd(och, max_ochs_per_mvin, ochs) val next_ocol = floorAdd(ocol, block_size.U, ocols, next_och === 0.U) val next_orow = floorAdd(orow, 1.U, orows, next_ocol === 0.U && next_och === 0.U) val next_b = floorAdd(b, 1.U, batches, next_orow === 0.U && next_ocol === 0.U && next_och === 0.U) och := next_och ocol := next_ocol orow := next_orow b := next_b state := Mux(next_b === 0.U && next_orow === 0.U && next_ocol === 0.U && next_och === 0.U, idle, ld) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := config b := 0.U orow := 0.U ocol := 0.U och := 0.U } } class LoopConvLdInputReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_start = UInt(log2Up(max_acc_addr).W) val dram_addr = UInt(coreMaxAddrBits.W) val downsample = Bool() val max_pixels_per_row = UInt(small_iterator_bitwidth.W) val input_dilated = Bool() val trans_input_3120 = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvLdInput(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_addr: Int, input_w: Int, max_block_len: Int, concurrent_loops: Int, latency: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2) (implicit p: Parameters) extends Module { val MVIN_SCALE_IDENTITY = 0x3f800000.U // TODO get this from configs somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvLdInputReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val wait_for_prev_loop = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, ld = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvLdInputReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ def undilated(x: UInt): UInt = (x +& req.input_dilated) >> req.input_dilated // Derived parameters val max_ichs_per_mvin = Mux(ichs < (max_block_len * block_size).U, ichs, (max_block_len * block_size).U).zext val max_batches_per_mvin = Mux(batches < (max_block_len * block_size).U, batches, (max_block_len * block_size).U).zext val max_chs_per_mvin = Mux(req.trans_input_3120, max_batches_per_mvin, max_ichs_per_mvin) // Iterators val b = Reg(SInt(large_iterator_bitwidth.W)) val irow = Reg(SInt(small_iterator_bitwidth.W)) val icol = Reg(SInt(small_iterator_bitwidth.W)) val ich = Reg(SInt(large_iterator_bitwidth.W)) // Calculated params val irow_padded = irow +& undilated(upad).zext val icol_padded = icol +& undilated(lpad).zext val is_zeros = irow < 0.S \|\| irow >= irows_unpadded.zext \|\| icol < 0.S \|\| icol >= icols_unpadded.zext val dram_stride = Mux(req.trans_input_3120, batch_size * (input_w/8).U, in_stride * (input_w/8).U) // Addresses val dram_offset = Mux(req.trans_input_3120, (((ich * in_col_dim * in_row_dim +& irowin_col_dim +& icol) batches +& b) * (input_w/8).U).asUInt, (((b * in_row_dim * in_col_dim +& irowin_col_dim +& icol) in_stride +& ich) * (input_w/8).U).asUInt) val dram_addr = Mux(is_zeros, 0.U, req.dram_addr + LoopConv.castDramOffset(dram_offset)) val spad_addr = Mux(req.trans_input_3120, // To prevent Verilator errors, we replace some "/ block_size.U" calls here with ">> log2Up(block_size)" req.addr_start.zext +& (b >> log2Up(block_size)) * input_spad_stride +& ich * (irows >> req.downsample) * (icols >> req.downsample) +& (irow_padded >> req.downsample) * (icols >> req.downsample) +& (icol_padded >> req.downsample), req.addr_start.zext +& (ich >> log2Up(block_size)) * input_spad_stride +& b * (irows >> req.downsample) * (icols >> req.downsample) +& (irow_padded >> req.downsample) * (icols >> req.downsample) +& (icol_padded >> req.downsample)) // Sizes val block_size_downsampled = (block_size.U << req.downsample).asUInt.zext val I = MuxCase( Mux(icols_unpadded.zext -& icol > block_size_downsampled, block_size_downsampled, icols_unpadded.zext -& icol), Seq( (icol < 0.S) -> Mux((0.S-&icol) > block_size.S, block_size.S, 0.S-&icol), (icol >= icols_unpadded.zext) -> Mux(icols_unpadded.zext +& undilated(rpad).zext -& icol > block_size.S, block_size.S, icols_unpadded.zext +& undilated(rpad).zext -& icol) ) ) val K = Mux(req.trans_input_3120, Mux(batches.zext -& b > max_chs_per_mvin, max_chs_per_mvin, batches.zext -& b), Mux(ichs.zext -& ich > max_chs_per_mvin, max_chs_per_mvin, ichs.zext -& ich)) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = SInt() val I = SInt() val K = SInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_mvin_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.scale := MVIN_SCALE_IDENTITY config_cmd_rs1.stride := input_spad_stride config_cmd_rs1.pixel_repeats := req.max_pixels_per_row config_cmd_rs1.state_id := 0.U config_cmd_rs1.shrink := 0.U config_cmd_rs1._unused := 1.U config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := dram_stride << req.downsample val mvin_cmd = Wire(new RoCCCommand) mvin_cmd := DontCare mvin_cmd.inst.funct := LOAD_CMD mvin_cmd.rs1 := 0.U // dram_addr mvin_cmd.rs2 := 0.U // mvin_cmd_rs2 // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !io.wait_for_prev_loop && (req.dram_addr =/= 0.U) command_p.io.in.bits.cmd := Mux(state === config, config_cmd, mvin_cmd) command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.I := I command_p.io.in.bits.K := K command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === LOAD_CMD) { val o = command_p.io.out.bits io.cmd.bits.rs1 := o.dram_addr val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType) mvin_cmd_rs2 := DontCare mvin_cmd_rs2.num_rows := (o.I >> req.downsample).asUInt mvin_cmd_rs2.num_cols := o.K.asUInt mvin_cmd_rs2.local_addr := cast_to_sp_addr(mvin_cmd_rs2.local_addr, o.spad_addr) io.cmd.bits.rs2 := mvin_cmd_rs2.asUInt } // Sending outputs when(req.dram_addr === 0.U){ state := idle }.elsewhen(command_p.io.in.fire) { when (state === config) { state := ld }.otherwise { val b_it = Mux(req.trans_input_3120, max_chs_per_mvin.asUInt, 1.U) val ich_it = Mux(req.trans_input_3120, 1.U, max_chs_per_mvin.asUInt) val next_ich = sFloorAdd(ich, ich_it, ichs.zext, 0.S) val next_icol = sFloorAdd(icol, I.asUInt, (icols_unpadded +& undilated(rpad)).zext, 0.S-&undilated(lpad).zext, next_ich === 0.S) val next_irow = sFloorAdd(irow, 1.U << req.downsample, (irows_unpadded +& undilated(dpad)).zext, 0.S-&undilated(upad).zext, next_icol === 0.S-&undilated(lpad).zext && next_ich === 0.S) val next_b = sFloorAdd(b, b_it, batches.zext, 0.S, next_irow === 0.S-&undilated(upad).zext && next_icol === 0.S-&undilated(lpad).zext && next_ich === 0.S) ich := next_ich icol := next_icol irow := next_irow b := next_b state := Mux(next_b === 0.S && next_irow === 0.S-&undilated(upad).zext && next_icol === 0.S-&undilated(lpad).zext && next_ich === 0.S, idle, ld) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := config b := 0.S irow := 0.S -& ((io.req.bits.inner_bounds.upad +& io.req.bits.input_dilated) >> io.req.bits.input_dilated).zext icol := 0.S -& ((io.req.bits.inner_bounds.lpad +& io.req.bits.input_dilated) >> io.req.bits.input_dilated).zext ich := 0.S } } class LoopConvLdWeightReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_end = UInt(log2Up(max_addr+1).W) val dram_addr = UInt(coreMaxAddrBits.W) val trans_weight_1203 = Bool() val trans_weight_0132 = Bool() val dw = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvLdWeight(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_addr: Int, input_w: Int, max_block_len: Int, concurrent_loops: Int, latency: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2)(implicit p: Parameters) extends Module { val MVIN_SCALE_IDENTITY = 0x3f800000.U // TODO get this from configs somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvLdWeightReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val wait_for_prev_loop = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, ld = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvLdWeightReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ // Derived parameters val max_chs_per_mvin = { val max_ochs_per_mvin = Mux(ochs < (max_block_len * block_size).U, ochs, (max_block_len * block_size).U) val max_kchs_per_mvin = Mux(kchs < (max_block_len * block_size).U, kchs, (max_block_len * block_size).U) Mux(req.trans_weight_0132, max_kchs_per_mvin, max_ochs_per_mvin) } val B_rows = Mux(req.trans_weight_0132, in_channels_per_bank * kcols * krows * ochs, out_channels_per_bank * kcols * krows * kchs) val addr_start = req.addr_end - B_rows val dram_stride = MuxCase(weight_stride, Seq( req.dw -> 1.U, req.trans_weight_1203 -> (kernel_dim * kernel_dim * out_channels), req.trans_weight_0132 -> in_channels )) * (input_w/8).U // Iterators val och = Reg(UInt(large_iterator_bitwidth.W)) val krow = Reg(UInt(tiny_iterator_bitwidth.W)) val kcol = Reg(UInt(tiny_iterator_bitwidth.W)) val kch = Reg(UInt(large_iterator_bitwidth.W)) // Addresses val dram_offset = MuxCase(((krowkernel_dimin_channels +& kcolin_channels +& kch) weight_stride +& och) * (input_w/8).U, Seq( req.dw -> (krow * kernel_dim +& kcol) * (input_w/8).U, req.trans_weight_1203 -> (((kchkernel_dimkernel_dim +& krowkernel_dim +& kcol) out_channels +& och) * (input_w/8).U), req.trans_weight_0132 -> (((krowkernel_dimout_channels +& kcolout_channels +& och) in_channels +& kch) * (input_w/8).U) )) val dram_addr = req.dram_addr + LoopConv.castDramOffset(dram_offset) val spad_addr = Mux(req.trans_weight_0132, // The width expansions are added here solely to prevent Verilator's "WIDTH" warnings, despite making the code uglier addr_start + (kch / block_size.U(kch.getWidth.W)) * krows * kcols * ochs + krow * kcols * ochs + kcol * ochs + och, addr_start + (och / block_size.U(och.getWidth.W)) * krows * kcols * kchs + krow * kcols * kchs + kcol * kchs + kch) // Sizes val J = Mux(req.trans_weight_0132, Mux(kchs - kch > max_chs_per_mvin, max_chs_per_mvin, kchs - kch), Mux(ochs - och > max_chs_per_mvin, max_chs_per_mvin, ochs - och)) val K = Mux(req.trans_weight_0132, Mux(ochs - och > block_size.U, block_size.U, ochs - och), Mux(kchs - kch > block_size.U, block_size.U, kchs - kch)) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = UInt() val K = UInt() val J = UInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_mvin_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.scale := MVIN_SCALE_IDENTITY config_cmd_rs1.stride := req.derived_params.weight_spad_stride config_cmd_rs1.pixel_repeats := 1.U config_cmd_rs1.state_id := 1.U config_cmd_rs1.shrink := 0.U config_cmd_rs1._unused := 1.U config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := dram_stride val mvin_cmd = Wire(new RoCCCommand) mvin_cmd := DontCare mvin_cmd.inst.funct := LOAD2_CMD mvin_cmd.rs1 := 0.U // dram_addr mvin_cmd.rs2 := 0.U // mvin_cmd_rs2 // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !io.wait_for_prev_loop && (req.dram_addr =/= 0.U) command_p.io.in.bits.cmd := Mux(state === config, config_cmd, mvin_cmd) command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.K := K command_p.io.in.bits.J := J command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === LOAD2_CMD) { val o = command_p.io.out.bits io.cmd.bits.rs1 := o.dram_addr val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType) mvin_cmd_rs2 := DontCare mvin_cmd_rs2.num_rows := o.K mvin_cmd_rs2.num_cols := o.J mvin_cmd_rs2.local_addr := cast_to_sp_addr(mvin_cmd_rs2.local_addr, o.spad_addr) io.cmd.bits.rs2 := mvin_cmd_rs2.asUInt } // Sending outputs when(req.dram_addr === 0.U){ state := idle }.elsewhen(command_p.io.in.fire) { when (state === config) { state := ld }.otherwise { val och_it = Mux(req.trans_weight_0132, block_size.U, max_chs_per_mvin) val kch_it = Mux(req.trans_weight_0132, max_chs_per_mvin, block_size.U) val next_kch = floorAdd(kch, kch_it, kchs) val next_kcol = floorAdd(kcol, 1.U, kcols, next_kch === 0.U) val next_krow = floorAdd(krow, 1.U, krows, next_kcol === 0.U && next_kch === 0.U) val next_och = floorAdd(och, och_it, ochs, next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U) kch := next_kch kcol := next_kcol krow := next_krow och := next_och state := Mux(next_och === 0.U && next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U, idle, ld) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := config kch := 0.U kcol := 0.U krow := 0.U och := 0.U } } class LoopConvExecuteReq(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_addr: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val a_addr_start = UInt(log2Up(max_addr).W) val b_addr_end = UInt(log2Up(max_addr+1).W) val c_addr_start = UInt(log2Up(max_acc_addr).W) val wrot180 = Bool() val downsample = Bool() val max_pixels_per_row = UInt(small_iterator_bitwidth.W) val input_dilated = Bool() val trans_weight_0132 = Bool() val trans_input_3120 = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvExecute(block_size: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_addr: Int, max_acc_addr: Int, concurrent_loops: Int, latency: Int, config_ex_rs1_t: ConfigExRs1, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs, compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs)(implicit p: Parameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvExecuteReq(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val lda_completed = Input(Bool()) val ldb_completed = Input(Bool()) val ldd_completed = Input(Bool()) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, pre, comp = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvExecuteReq(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ def undilated(x: UInt): UInt = (x +& req.input_dilated) >> req.input_dilated // Derived parameters val B_rows = Mux(req.trans_weight_0132, in_channels_per_bank * kcols * krows * ochs, out_channels_per_bank * kcols * krows * kchs) val a_addr_start = req.a_addr_start val b_addr_start = req.b_addr_end - B_rows val c_addr_start = /(BigInt(3) << 30).U \|/ req.c_addr_start // Iterators val och = Reg(UInt(large_iterator_bitwidth.W)) val krow = Reg(UInt(tiny_iterator_bitwidth.W)) val kcol = Reg(UInt(tiny_iterator_bitwidth.W)) val kch = Reg(UInt(large_iterator_bitwidth.W)) val b = Reg(UInt(large_iterator_bitwidth.W)) val orow = Reg(UInt(small_iterator_bitwidth.W)) val ocol = Reg(UInt(small_iterator_bitwidth.W)) // TODO kernel-dilation and input-dilation can never be activated at the same time, so we can optimize out some multiplications by kernel_dilation val skip_iteration = state >= pre && req.input_dilated && (((krow * kernel_dilation +& orow -& upad)(0) & req.input_dilated).asBool \|\| ((kcol * kernel_dilation +& ocol -& lpad)(0) & req.input_dilated).asBool) val pixels = Mux(kcols - kcol > req.max_pixels_per_row, req.max_pixels_per_row, kcols - kcol) val irow = undilated(orow * stride +& krow * kernel_dilation) val icol = undilated(ocol * stride +& kcol * kernel_dilation) val I = Mux(req.trans_input_3120, Mux(batches - b > block_size.U, block_size.U, batches - b), undilated(Mux(ocols - ocol > (block_size.U << req.input_dilated).asUInt, (block_size.U << req.input_dilated).asUInt, ocols - ocol))) val J = Mux(ochs - och > block_size.U, block_size.U, ochs - och) val K = pixels * Mux(kchs - kch > block_size.U, block_size.U, kchs - kch) // Addresses val a_addr = Mux(req.trans_input_3120, a_addr_start +& (b / block_size.U) * input_spad_stride +& kch * (irows >> req.downsample) * (icols >> req.downsample) +& (irow >> req.downsample) * (icols >> req.downsample) +& (icol >> req.downsample), a_addr_start +& (kch / block_size.U(kch.getWidth.W)) * input_spad_stride +& b * (irows >> req.downsample) * (icols >> req.downsample) +& (irow >> req.downsample) * (icols >> req.downsample) +& (icol >> req.downsample)) // val c_addr = Mux(ex_overwrite && krow === 0.U && kcol === 0.U && kch === 0.U, d_addr_start, c_addr_start) +& // (och / block_size.U) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol // The width expansions are added here solely to prevent Verilator's "WIDTH" warnings, despite making the code uglier val c_addr = c_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol // val new_weights = b === 0.U && orow === 0.U && ocol === 0.U val new_weights = Reg(Bool()) val krow_rot = Mux(req.wrot180, krows - krow - 1.U, krow) val kcol_rot = Mux(req.wrot180, kcols - kcol - 1.U, kcol) val b_addr = Mux(req.trans_weight_0132, b_addr_start +& (kch / block_size.U(och.getWidth.W)) * krows * kcols * ochs +& krow_rot * kcols * ochs +& kcol_rot * ochs +& och, b_addr_start +& (och / block_size.U(och.getWidth.W)) * krows * kcols * kchs +& krow_rot * kcols * kchs +& kcol_rot * kchs +& kch) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val a_addr = UInt() val b_addr = UInt() val c_addr = UInt() val I = UInt() val J = UInt() val K = UInt() val new_weights = Bool() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_ex_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.a_stride := (irows * icols).asUInt config_cmd_rs1.set_only_strides := 1.U config_cmd_rs1.cmd_type := 0.U val config_cmd_rs2 = Wire(new ConfigExRs2) config_cmd_rs2 := DontCare config_cmd_rs2.c_stride := (orows * ocols).asUInt config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := config_cmd_rs2.asUInt val pre_cmd = Wire(new RoCCCommand) // preload pre_cmd := DontCare pre_cmd.inst.funct := PRELOAD_CMD pre_cmd.rs1 := 0.U//(K << 48) \| (J << 32) \| pre_addr pre_cmd.rs2 := 0.U//(I << 48) \| (J << 32) \| c_addr val comp_cmd = Wire(new RoCCCommand()) // compute.preloaded comp_cmd := DontCare comp_cmd.inst.funct := Mux(new_weights, COMPUTE_AND_FLIP_CMD, COMPUTE_AND_STAY_CMD) comp_cmd.rs1 := 0.U//(I << 48) \| (K << 32) \| a_addr comp_cmd.rs2 := 0.U//(I << 48) \| (J << 32) \| GARBAGE_ADDR val ld_ahead = io.lda_completed && io.ldb_completed && io.ldd_completed // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !skip_iteration && ld_ahead command_p.io.in.bits.cmd := MuxCase(config_cmd, Seq((state === pre) -> pre_cmd, (state === comp) -> comp_cmd)) command_p.io.in.bits.a_addr := a_addr command_p.io.in.bits.b_addr := b_addr command_p.io.in.bits.c_addr := c_addr command_p.io.in.bits.I := I command_p.io.in.bits.J := J command_p.io.in.bits.K := K command_p.io.in.bits.new_weights := new_weights command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === PRELOAD_CMD) { val o = command_p.io.out.bits val pre_cmd_rs1 = Wire(preload_rs1_t.cloneType) pre_cmd_rs1 := DontCare pre_cmd_rs1.num_rows := o.K.asUInt pre_cmd_rs1.num_cols := o.J.asUInt pre_cmd_rs1.local_addr := Mux(o.new_weights, cast_to_sp_addr(pre_cmd_rs1.local_addr, o.b_addr), garbage_addr(pre_cmd_rs1.local_addr)) val pre_cmd_rs2 = Wire(preload_rs2_t.cloneType) pre_cmd_rs2 := DontCare pre_cmd_rs2.num_rows := o.I.asUInt pre_cmd_rs2.num_cols := o.J.asUInt pre_cmd_rs2.local_addr := cast_to_acc_addr(pre_cmd_rs2.local_addr, o.c_addr, accumulate = true.B, read_full = false.B) io.cmd.bits.rs1 := pre_cmd_rs1.asUInt io.cmd.bits.rs2 := pre_cmd_rs2.asUInt }.elsewhen(command_p.io.out.bits.cmd.inst.funct =/= CONFIG_CMD) { val o = command_p.io.out.bits val comp_cmd_rs1 = Wire(compute_rs1_t.cloneType) comp_cmd_rs1 := DontCare comp_cmd_rs1.num_rows := o.I.asUInt comp_cmd_rs1.num_cols := o.K.asUInt comp_cmd_rs1.local_addr := cast_to_sp_addr(comp_cmd_rs1.local_addr, o.a_addr) val comp_cmd_rs2 = Wire(compute_rs2_t.cloneType) comp_cmd_rs2 := DontCare comp_cmd_rs2.num_rows := o.I.asUInt comp_cmd_rs2.num_cols := o.J.asUInt comp_cmd_rs2.local_addr := garbage_addr(comp_cmd_rs2.local_addr) io.cmd.bits.rs1 := comp_cmd_rs1.asUInt io.cmd.bits.rs2 := comp_cmd_rs2.asUInt } // Updating "new_weights" when (state === comp && command_p.io.in.fire) { new_weights := false.B } // Sending outputs when (command_p.io.in.fire \|\| skip_iteration) { when (state === config) { state := pre }.elsewhen (state === pre) { state := comp }.otherwise { val b_it = Mux(req.trans_input_3120, block_size.U, 1.U) val ocol_it = Mux(skip_iteration \|\| req.trans_input_3120, 1.U, block_size.U << req.input_dilated).asUInt val next_ocol = floorAdd(ocol, ocol_it, ocols) val next_orow = floorAdd(orow, 1.U, orows, next_ocol === 0.U) val next_b = floorAdd(b, b_it, batches, next_orow === 0.U && next_ocol === 0.U) val next_kch = floorAdd(kch, block_size.U, kchs, next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) val next_kcol = floorAdd(kcol, req.max_pixels_per_row, kcols, next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) val next_krow = floorAdd(krow, 1.U, krows, next_kcol === 0.U && next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) val next_och = floorAdd(och, block_size.U, ochs, next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) ocol := next_ocol orow := next_orow b := next_b kch := next_kch kcol := next_kcol krow := next_krow och := next_och when (next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) { new_weights := true.B } state := Mux(next_och === 0.U && next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U, idle, pre) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := Mux(io.req.bits.trans_input_3120, config, pre) b := 0.U orow := 0.U ocol := 0.U och := 0.U krow := 0.U kcol := 0.U kch := 0.U new_weights := true.B } } class LoopConvStReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_start = UInt(log2Up(max_acc_addr).W) val dram_addr = UInt(coreMaxAddrBits.W) val no_pool = Bool() val activation = UInt(2.W) // TODO magic number val trans_output_1203 = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvSt(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_acc_addr: Int, input_w: Int, concurrent_loops: Int, latency: Int, config_mvout_rs2_t: ConfigMvoutRs2, mvout_rs2_t: MvoutRs2)(implicit p: Parameters) extends Module { val ACC_SCALE_NO_CHANGE = ~(0.U(32.W)) // TODO get this from ISA description somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvStReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val ex_completed = Input(Bool()) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, st, pre_pool_config, pool, post_pool_config = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvStReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ val acc_addr_start = req.addr_start // Derived parameters val skip = req.dram_addr === 0.U // Iterators val b = Reg(UInt(large_iterator_bitwidth.W)) val orow = Reg(UInt(small_iterator_bitwidth.W)) val ocol = Reg(UInt(small_iterator_bitwidth.W)) val och = Reg(UInt(large_iterator_bitwidth.W)) // Addresses val dram_offset = Mux(req.trans_output_1203, ((orowout_col_dimbatch_size +& ocolbatch_size +& b) out_channels +& och) * (input_w/8).U, ((bout_row_dimout_col_dim +& orowout_col_dim +& ocol) out_stride +& och) * (input_w/8).U) val dram_addr = req.dram_addr + LoopConv.castDramOffset(dram_offset) val spad_addr = acc_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol val pool_dram_addr = req.dram_addr + ((b * pool_out_col_dim * pool_out_row_dim) * out_stride + och) * (input_w/8).U val pool_spad_addr = acc_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols // Sizes val I = Mux(ocols - ocol > block_size.U, block_size.U, ocols - ocol) val J = Mux(ochs - och > block_size.U, block_size.U, ochs - och) val channels = J class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = UInt() val pool_dram_addr = UInt() val pool_spad_addr = UInt() val channels = UInt() val is_pool = Bool() val I = UInt() val J = UInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val mvout_cmd = Wire(new RoCCCommand) mvout_cmd := DontCare mvout_cmd.inst.funct := STORE_CMD mvout_cmd.rs1 := 0.U // dram_addr mvout_cmd.rs2 := 0.U // mvout_cmd_rs2 val pre_pool_config_cmd = Wire(new RoCCCommand) pre_pool_config_cmd := DontCare pre_pool_config_cmd.inst.funct := CONFIG_CMD val pre_pool_config_cmd_rs1 = Wire(new ConfigMvoutRs1) pre_pool_config_cmd_rs1 := DontCare pre_pool_config_cmd_rs1.ocols := ocols pre_pool_config_cmd_rs1.orows := orows pre_pool_config_cmd_rs1.pocols := pocols pre_pool_config_cmd_rs1.porows := porows pre_pool_config_cmd_rs1.pool_out_dim := pool_out_col_dim pre_pool_config_cmd_rs1.lpad := plpad pre_pool_config_cmd_rs1.upad := pupad pre_pool_config_cmd_rs1.pool_size := pool_size pre_pool_config_cmd_rs1.pool_stride := pool_stride pre_pool_config_cmd_rs1.activation := req.activation pre_pool_config_cmd_rs1.cmd_type := CONFIG_STORE pre_pool_config_cmd.rs1 := pre_pool_config_cmd_rs1.asUInt val pre_pool_config_cmd_rs2 = Wire(config_mvout_rs2_t.cloneType) pre_pool_config_cmd_rs2 := DontCare pre_pool_config_cmd_rs2.acc_scale := ACC_SCALE_NO_CHANGE pre_pool_config_cmd_rs2.stride := out_stride * (input_w / 8).U pre_pool_config_cmd.rs2 := pre_pool_config_cmd_rs2.asUInt val post_pool_config_cmd = Wire(new RoCCCommand) post_pool_config_cmd := DontCare post_pool_config_cmd.inst.funct := CONFIG_CMD val post_pool_config_cmd_rs1 = Wire(new ConfigMvoutRs1) post_pool_config_cmd_rs1 := DontCare post_pool_config_cmd_rs1.activation := req.activation post_pool_config_cmd_rs1.cmd_type := CONFIG_STORE post_pool_config_cmd.rs1 := post_pool_config_cmd_rs1.asUInt val post_pool_config_cmd_rs2 = Wire(config_mvout_rs2_t.cloneType) post_pool_config_cmd_rs2 := DontCare post_pool_config_cmd_rs2.acc_scale := ACC_SCALE_NO_CHANGE post_pool_config_cmd_rs2.stride := out_stride * (input_w / 8).U post_pool_config_cmd.rs2 := post_pool_config_cmd_rs2.asUInt val pool_cmd = Wire(new RoCCCommand) pool_cmd := DontCare pool_cmd.inst.funct := STORE_CMD pool_cmd.rs1 := 0.U//pool_dram_addr pool_cmd.rs2 := 0.U//(channels << 32.U) \| pool_spad_addr // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !skip && io.ex_completed command_p.io.in.bits.cmd := MuxLookup(state.asUInt, mvout_cmd)(Seq( pre_pool_config.asUInt -> pre_pool_config_cmd, pool.asUInt -> pool_cmd, post_pool_config.asUInt -> post_pool_config_cmd) ) command_p.io.in.bits.is_pool := state === pool command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.pool_spad_addr := pool_spad_addr command_p.io.in.bits.pool_dram_addr := pool_dram_addr command_p.io.in.bits.channels := channels command_p.io.in.bits.I := I command_p.io.in.bits.J := J command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === STORE_CMD) { val o = command_p.io.out.bits when (o.is_pool) { val pool_mvout_cmd_rs2 = Wire(mvout_rs2_t.cloneType) pool_mvout_cmd_rs2 := DontCare pool_mvout_cmd_rs2.num_cols := o.channels pool_mvout_cmd_rs2.local_addr := cast_to_acc_addr(pool_mvout_cmd_rs2.local_addr, o.pool_spad_addr, accumulate = false.B, read_full = false.B) io.cmd.bits.rs1 := o.pool_dram_addr io.cmd.bits.rs2 := pool_mvout_cmd_rs2.asUInt } .otherwise { val mvout_cmd_rs2 = Wire(mvout_rs2_t.cloneType) mvout_cmd_rs2 := DontCare mvout_cmd_rs2.num_rows := o.I.asUInt mvout_cmd_rs2.num_cols := o.J.asUInt mvout_cmd_rs2.local_addr := cast_to_acc_addr(mvout_cmd_rs2.local_addr, o.spad_addr, accumulate = false.B, read_full = false.B) io.cmd.bits.rs1 := o.dram_addr io.cmd.bits.rs2 := mvout_cmd_rs2.asUInt } } // Sending outputs when (skip) { state := idle }.elsewhen(command_p.io.in.fire) { when (req.no_pool) { val next_och = floorAdd(och, block_size.U, ochs) val next_ocol = floorAdd(ocol, block_size.U, ocols, next_och === 0.U) val next_orow = floorAdd(orow, 1.U, orows, next_ocol === 0.U && next_och === 0.U) val next_b = floorAdd(b, 1.U, batches, next_orow === 0.U && next_ocol === 0.U && next_och === 0.U) och := next_och ocol := next_ocol orow := next_orow b := next_b state := Mux(next_b === 0.U && next_orow === 0.U && next_ocol === 0.U && next_och === 0.U, idle, st) }.elsewhen(state === pre_pool_config) { state := pool }.elsewhen(state === post_pool_config) { state := idle }.otherwise { val next_och = floorAdd(och, block_size.U, ochs) val next_b = floorAdd(b, 1.U, batches, next_och === 0.U) och := next_och b := next_b state := Mux(next_b === 0.U && next_och === 0.U, post_pool_config, pool) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := Mux(io.req.bits.no_pool, st, pre_pool_config) b := 0.U orow := 0.U ocol := 0.U och := 0.U } } class LoopConvState(val block_size: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val coreMaxAddrBits: Int, val max_addr: Int, val max_acc_addr: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val bias_dram_addr = UInt(coreMaxAddrBits.W) val weights_dram_addr = UInt(coreMaxAddrBits.W) val input_dram_addr = UInt(coreMaxAddrBits.W) val output_dram_addr = UInt(coreMaxAddrBits.W) val no_bias = Bool() val wrot180 = Bool() val no_pool = Bool() val downsample = Bool() val input_dilated = Bool() val activation = UInt(2.W) // TODO magic number val trans_output_1203 = Bool() val trans_weight_1203 = Bool() val trans_weight_0132 = Bool() val trans_input_3120 = Bool() val dw = Bool() val max_pixels_per_row = UInt(small_iterator_bitwidth.W) val a_ex_spad_id = UInt(2.W) val b_ex_spad_id = UInt(2.W) val configured = Bool() val running = Bool() val ld_bias_started = Bool() val ld_input_started = Bool() val ld_weights_started = Bool() val ex_started = Bool() val st_started = Bool() val ld_bias_completed = Bool() val ld_input_completed = Bool() val ld_weights_completed = Bool() val ex_completed = Bool() val st_completed = Bool() def all_completed(dummy: Int=0): Bool = ld_bias_completed && ld_input_completed && ld_weights_completed && ex_completed && st_completed val a_addr_start = UInt(log2Up(max_addr).W) val b_addr_end = UInt(log2Up(max_addr+1).W) def derived_params(dummy: Int=0): LoopConvDerivedParams = { import outer_bounds.{stride, kernel_dilation} import inner_bounds.{batches, pochs, orows, ocols, krows, kcols, upad, dpad, lpad, rpad, kchs} val result = Wire(new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)) result.ochs := pochs val dilated_krows = krows + (kernel_dilation - 1.U)(krows - 1.U) val dilated_kcols = kcols + (kernel_dilation - 1.U)(kcols - 1.U) val irows_without_dilation = orows * stride +& dilated_krows -& 1.U val icols_without_dilation = ocols * stride +& dilated_kcols -& 1.U val irows_unpadded_without_dilation = irows_without_dilation -& upad -& dpad val icols_unpadded_without_dilation = icols_without_dilation -& lpad -& rpad def undilated(x: UInt): UInt = (x +& input_dilated) >> input_dilated val irows_unpadded = undilated(irows_unpadded_without_dilation) val icols_unpadded = undilated(icols_unpadded_without_dilation) result.irows := Mux(input_dilated, irows_unpadded +& undilated(upad) +& undilated(dpad), irows_without_dilation) result.icols := Mux(input_dilated, icols_unpadded +& undilated(lpad) +& undilated(rpad), icols_without_dilation) result.irows_unpadded := irows_unpadded result.icols_unpadded := icols_unpadded result.ichs := kchs result.out_channels_per_bank := result.ochs / block_size.U(result.ochs.getWidth.W) +& (result.ochs % block_size.U =/= 0.U) result.in_channels_per_bank := result.ichs / block_size.U(result.ochs.getWidth.W) +& (result.ichs % block_size.U =/= 0.U) result.bias_spad_stride := batches * orows * ocols result.input_spad_stride := Mux(trans_input_3120, result.ichs * (result.irows >> downsample) * (result.icols >> downsample), batches * (result.irows >> downsample) * (result.icols >> downsample)) result.weight_spad_stride := Mux(trans_weight_0132, krows * kcols * pochs, krows * kcols * kchs) // result.ex_overwrite := bias_dram_addr =/= 0.U && no_bias result } def reset(): Unit = { configured := false.B running := false.B ld_bias_started := false.B ld_input_started := false.B ld_weights_started := false.B ex_started := false.B st_started := false.B ld_bias_completed := false.B ld_input_completed := false.B ld_weights_completed := false.B ex_completed := false.B st_completed := false.B } } class LoopConv (block_size: Int, coreMaxAddrBits: Int, reservation_station_size: Int, max_lds: Int, max_exs: Int, max_sts: Int, max_addr: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, dma_max_bytes: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2, config_mvout_rs2_t: ConfigMvoutRs2, mvout_rs2_t: MvoutRs2, config_ex_rs1_t: ConfigExRs1, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs, compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs, has_training_convs: Boolean, has_max_pool: Boolean, has_first_layer_optimizations: Boolean, has_dw_convs: Boolean) (implicit p: Parameters) extends Module { val large_iterator_bitwidth = 16 val small_iterator_bitwidth = 16 // 8 val tiny_iterator_bitwidth = 16 // 4 val max_block_len = (dma_max_bytes / (block_size * (input_w / 8))) max 1 val max_block_len_acc = (dma_max_bytes / (block_size * (acc_w / 8))) max 1 val io = IO(new Bundle { val in = Flipped(Decoupled(new GemminiCmd(reservation_station_size))) val out = Decoupled(new GemminiCmd(reservation_station_size)) val ld_completed = Input(UInt(log2Up(reservation_station_size+1).W)) val st_completed = Input(UInt(log2Up(reservation_station_size+1).W)) val ex_completed = Input(UInt(log2Up(reservation_station_size+1).W)) val busy = Output(Bool()) }) // Create states val concurrent_loops = 2 val loops = Reg(Vec(concurrent_loops, new LoopConvState(block_size, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, coreMaxAddrBits, max_addr, max_acc_addr))) val head_loop_id = RegInit(0.U(log2Up(concurrent_loops).W)) val tail_loop_id = (~head_loop_id).asUInt // This is the loop that we always try to configure if available val head_loop = loops(head_loop_id) val tail_loop = loops(tail_loop_id) val loop_configured = loops.map(_.configured).reduce(_ \|\| _) val loop_being_configured_id = Mux(head_loop.configured, tail_loop_id, head_loop_id) val loop_being_configured = loops(loop_being_configured_id) // Create inner modules val latency = 2 val ld_bias = Module(new LoopConvLdBias(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_acc_addr, acc_w, max_block_len_acc, concurrent_loops, latency, config_mvin_rs1_t, mvin_rs2_t)) val ld_input = Module(new LoopConvLdInput(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, input_w, max_block_len, concurrent_loops, latency, config_mvin_rs1_t, mvin_rs2_t)) val ld_weights = Module(new LoopConvLdWeight(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, input_w, max_block_len, concurrent_loops, latency, config_mvin_rs1_t, mvin_rs2_t)) val ex = Module(new LoopConvExecute(block_size, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops, latency, config_ex_rs1_t, preload_rs1_t, preload_rs2_t, compute_rs1_t, compute_rs2_t)) val st = Module(new LoopConvSt(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_acc_addr, input_w, concurrent_loops, latency, config_mvout_rs2_t, mvout_rs2_t)) // Create command queue val cmd = Queue(io.in) io.busy := cmd.valid \|\| loop_configured // Create arbiter val arb = Module(new Arbiter(new RoCCCommand, 5)) arb.io.in(0) <> st.io.cmd arb.io.in(1) <> ex.io.cmd arb.io.in(2) <> ld_bias.io.cmd arb.io.in(3) <> ld_weights.io.cmd arb.io.in(4) <> ld_input.io.cmd val unrolled_cmd = arb.io.out // Create reservation station utilization counters val ld_utilization = RegInit(0.U(log2Up(max_lds+1).W)) val st_utilization = RegInit(0.U(log2Up(max_sts+1).W)) val ex_utilization = RegInit(0.U(log2Up(max_exs+1).W)) ld_utilization := ld_utilization +& (ld_bias.io.cmd.fire \|\| ld_weights.io.cmd.fire \|\| ld_input.io.cmd.fire) -& io.ld_completed st_utilization := st_utilization +& st.io.cmd.fire -& io.st_completed ex_utilization := ex_utilization +& ex.io.cmd.fire -& io.ex_completed assert(ld_utilization >= io.ld_completed, "ld utilization underflow") assert(st_utilization >= io.st_completed, "st utilization underflow") assert(ex_utilization >= io.ex_completed, "ex utilization underflow") // Wire up unrolled command output val is_loop_run_cmd = cmd.bits.cmd.inst.funct === LOOP_CONV_WS val is_loop_config_cmd = cmd.bits.cmd.inst.funct >= LOOP_CONV_WS_CONFIG_1 && cmd.bits.cmd.inst.funct <= LOOP_CONV_WS_CONFIG_6 val is_loop_cmd = is_loop_run_cmd \|\| is_loop_config_cmd io.out.bits.cmd := Mux(loop_configured, unrolled_cmd.bits, cmd.bits.cmd) io.out.bits.cmd.status := cmd.bits.cmd.status // TODO This is not guaranteed to be the correct fix! We must fix this io.out.bits.rob_id := DontCare io.out.bits.from_matmul_fsm := Mux(loop_configured, false.B, cmd.bits.from_matmul_fsm) io.out.bits.from_conv_fsm := Mux(loop_configured, true.B, cmd.bits.from_conv_fsm) io.out.valid := Mux(loop_configured, unrolled_cmd.valid, cmd.valid && !is_loop_config_cmd && !is_loop_run_cmd) cmd.ready := Mux(is_loop_cmd, !loop_being_configured.configured, !loop_configured && io.out.ready) arb.io.out.ready := io.out.ready // Wire up waiting-for-loads signals val ex_is_waiting_for_loads = loops(ex.io.loop_id).ex_started && !loops(ex.io.loop_id).ex_completed && !(loops(ex.io.loop_id).ld_input_completed && loops(ex.io.loop_id).ld_weights_completed && loops(ex.io.loop_id).ld_bias_completed) ld_bias.io.wait_for_prev_loop := ex_is_waiting_for_loads && ld_bias.io.loop_id =/= ex.io.loop_id ld_weights.io.wait_for_prev_loop := ex_is_waiting_for_loads && ld_weights.io.loop_id =/= ex.io.loop_id ld_input.io.wait_for_prev_loop := ex_is_waiting_for_loads && ld_input.io.loop_id =/= ex.io.loop_id // Wire up overloaded signals ld_bias.io.rob_overloaded := ld_utilization >= max_lds.U ld_input.io.rob_overloaded := ld_utilization >= max_lds.U ld_weights.io.rob_overloaded := ld_utilization >= max_lds.U ex.io.rob_overloaded := ex_utilization >= max_exs.U st.io.rob_overloaded := st_utilization >= max_sts.U // Wire up iterator inputs ex.io.lda_completed := (ld_input.io.loop_id =/= ex.io.loop_id) \|\| ld_input.io.idle ex.io.ldb_completed := (ld_weights.io.loop_id =/= ex.io.loop_id) \|\| ld_weights.io.idle ex.io.ldd_completed := (ld_bias.io.loop_id =/= ex.io.loop_id) \|\| ld_bias.io.idle st.io.ex_completed := (ex.io.loop_id =/= st.io.loop_id) \|\| ex.io.idle // Create config registers when(cmd.valid && is_loop_cmd && !loop_being_configured.configured) { switch (cmd.bits.cmd.inst.funct) { is (LOOP_CONV_WS_CONFIG_1) { loop_being_configured.outer_bounds.out_channels := cmd.bits.cmd.rs1(63, 48) loop_being_configured.outer_bounds.in_channels := cmd.bits.cmd.rs1(47, 32) loop_being_configured.outer_bounds.in_row_dim := cmd.bits.cmd.rs1(31, 16) loop_being_configured.outer_bounds.batch_size := cmd.bits.cmd.rs1(15, 0) loop_being_configured.outer_bounds.padding := cmd.bits.cmd.rs2(63, 56) loop_being_configured.outer_bounds.stride := cmd.bits.cmd.rs2(55, 48) loop_being_configured.outer_bounds.out_col_dim := cmd.bits.cmd.rs2(47, 32) loop_being_configured.outer_bounds.pool_out_row_dim := cmd.bits.cmd.rs2(31, 16) loop_being_configured.outer_bounds.out_row_dim := cmd.bits.cmd.rs2(15, 0) } is (LOOP_CONV_WS_CONFIG_2) { loop_being_configured.outer_bounds.kernel_dim := cmd.bits.cmd.rs1(63, 48) loop_being_configured.outer_bounds.pool_out_col_dim := cmd.bits.cmd.rs1(47, 32) loop_being_configured.outer_bounds.pool_size := (if (!has_max_pool) 1.U else cmd.bits.cmd.rs1(31, 16)) loop_being_configured.outer_bounds.pool_stride := (if (!has_max_pool) 1.U else cmd.bits.cmd.rs1(15, 8)) loop_being_configured.outer_bounds.pool_padding := (if (!has_max_pool) 0.U else cmd.bits.cmd.rs1(7, 0)) loop_being_configured.inner_bounds.batches := cmd.bits.cmd.rs2(63, 48) loop_being_configured.inner_bounds.porows := cmd.bits.cmd.rs2(47, 32) loop_being_configured.inner_bounds.pocols := cmd.bits.cmd.rs2(31, 16) loop_being_configured.inner_bounds.pochs := cmd.bits.cmd.rs2(15, 0) } is (LOOP_CONV_WS_CONFIG_3) { loop_being_configured.inner_bounds.krows := cmd.bits.cmd.rs1(63, 48) loop_being_configured.inner_bounds.kcols := cmd.bits.cmd.rs1(47, 32) loop_being_configured.inner_bounds.kchs := cmd.bits.cmd.rs1(31, 16) loop_being_configured.inner_bounds.lpad := cmd.bits.cmd.rs1(15, 0) loop_being_configured.inner_bounds.rpad := cmd.bits.cmd.rs2(63, 48) loop_being_configured.inner_bounds.upad := cmd.bits.cmd.rs2(47, 32) loop_being_configured.inner_bounds.dpad := cmd.bits.cmd.rs2(31, 24) loop_being_configured.inner_bounds.plpad := cmd.bits.cmd.rs2(23, 16) loop_being_configured.outer_bounds.in_col_dim := cmd.bits.cmd.rs2(15, 0) } is (LOOP_CONV_WS_CONFIG_4) { loop_being_configured.inner_bounds.orows := cmd.bits.cmd.rs1(63, 48) loop_being_configured.inner_bounds.prad := cmd.bits.cmd.rs1(47, 32) loop_being_configured.inner_bounds.pupad := cmd.bits.cmd.rs1(31, 21) loop_being_configured.inner_bounds.pdpad := cmd.bits.cmd.rs1(20, 10) loop_being_configured.outer_bounds.kernel_dilation := cmd.bits.cmd.rs1(9, 0) loop_being_configured.inner_bounds.ocols := cmd.bits.cmd.rs2(15, 0) loop_being_configured.outer_bounds.in_stride := cmd.bits.cmd.rs2(63, 48) loop_being_configured.outer_bounds.weight_stride := cmd.bits.cmd.rs2(47, 32) loop_being_configured.outer_bounds.out_stride := cmd.bits.cmd.rs2(31, 16) } is (LOOP_CONV_WS_CONFIG_5) { loop_being_configured.weights_dram_addr := cmd.bits.cmd.rs1 loop_being_configured.output_dram_addr := cmd.bits.cmd.rs2 } is (LOOP_CONV_WS_CONFIG_6) { loop_being_configured.bias_dram_addr := cmd.bits.cmd.rs1 loop_being_configured.input_dram_addr := cmd.bits.cmd.rs2 } is (LOOP_CONV_WS) { loop_being_configured.no_bias := cmd.bits.cmd.rs1(0) // TODO we added a default value for max_pixels_per_row just to maintain backwards compatibility. we should deprecate and remove it later val config_max_pixels_per_row = cmd.bits.cmd.rs1(15, 8) loop_being_configured.max_pixels_per_row := Mux( !has_first_layer_optimizations.B \|\| config_max_pixels_per_row === 0.U, 1.U, config_max_pixels_per_row) loop_being_configured.a_ex_spad_id := cmd.bits.cmd.rs1(19, 18) loop_being_configured.b_ex_spad_id := cmd.bits.cmd.rs1(17, 16) loop_being_configured.wrot180 := has_training_convs.B && cmd.bits.cmd.rs1(1) loop_being_configured.input_dilated := has_training_convs.B && cmd.bits.cmd.rs2(2) loop_being_configured.trans_output_1203 := has_training_convs.B && cmd.bits.cmd.rs1(2) loop_being_configured.trans_weight_1203 := has_training_convs.B && cmd.bits.cmd.rs1(3) loop_being_configured.trans_weight_0132 := has_training_convs.B && cmd.bits.cmd.rs1(4) loop_being_configured.trans_input_3120 := has_training_convs.B && cmd.bits.cmd.rs1(5) loop_being_configured.dw := has_dw_convs.B && cmd.bits.cmd.rs1(6) loop_being_configured.no_pool := !has_max_pool.B \|\| cmd.bits.cmd.rs2(0) loop_being_configured.activation := cmd.bits.cmd.rs2(4,3) loop_being_configured.downsample := cmd.bits.cmd.rs2(1) loop_being_configured.configured := true.B // assert(!loop_being_configured.input_dilated \|\| loop_being_configured.outer_bounds.stride === 1.U) // assert(!loop_being_configured.downsample \|\| (loop_being_configured.outer_bounds.kernel_dim === 1.U && loop_being_configured.outer_bounds.stride === 2.U)) // TODO add the rest of the conditions that must be true for "downsample" to be enabled } } } // Wire up request signals val ld_bias_addr_start = RegInit(0.U(log2Up(max_acc_addr).W)) val ex_c_addr_start = RegInit(0.U(log2Up(max_acc_addr).W)) val st_addr_start = RegInit(0.U(log2Up(max_acc_addr).W)) val loop_requesting_ld_bias_id = Mux(head_loop.ld_bias_started, tail_loop_id, head_loop_id) val loop_requesting_ld_bias = loops(loop_requesting_ld_bias_id) ld_bias.io.req.bits.outer_bounds := loop_requesting_ld_bias.outer_bounds ld_bias.io.req.bits.inner_bounds := loop_requesting_ld_bias.inner_bounds ld_bias.io.req.bits.derived_params := loop_requesting_ld_bias.derived_params() ld_bias.io.req.bits.addr_start := ld_bias_addr_start ld_bias.io.req.bits.dram_addr := loop_requesting_ld_bias.bias_dram_addr ld_bias.io.req.bits.no_bias := loop_requesting_ld_bias.no_bias ld_bias.io.req.bits.loop_id := loop_requesting_ld_bias_id ld_bias.io.req.valid := !loop_requesting_ld_bias.ld_bias_started && loop_requesting_ld_bias.configured when (ld_bias.io.req.fire) { loop_requesting_ld_bias.running := true.B loop_requesting_ld_bias.ld_bias_started := true.B // when (loop_requesting_ld_bias.bias_dram_addr =/= 0.U) { when (loop_requesting_ld_bias.output_dram_addr =/= 0.U) { ld_bias_addr_start := floorAdd(ld_bias_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U) } } val loop_requesting_ld_input_id = Mux(head_loop.ld_input_started, tail_loop_id, head_loop_id) val loop_requesting_ld_input = loops(loop_requesting_ld_input_id) ld_input.io.req.bits.outer_bounds := loop_requesting_ld_input.outer_bounds ld_input.io.req.bits.inner_bounds := loop_requesting_ld_input.inner_bounds ld_input.io.req.bits.derived_params := loop_requesting_ld_input.derived_params() ld_input.io.req.bits.addr_start := Mux(loop_requesting_ld_input.a_ex_spad_id === 0.U, loop_requesting_ld_input.a_addr_start, (loop_requesting_ld_input.a_ex_spad_id - 1.U) * (max_addr / concurrent_loops).U) ld_input.io.req.bits.dram_addr := loop_requesting_ld_input.input_dram_addr ld_input.io.req.bits.downsample := loop_requesting_ld_input.downsample ld_input.io.req.bits.max_pixels_per_row := loop_requesting_ld_input.max_pixels_per_row ld_input.io.req.bits.input_dilated := loop_requesting_ld_input.input_dilated ld_input.io.req.bits.trans_input_3120 := loop_requesting_ld_input.trans_input_3120 ld_input.io.req.bits.loop_id := loop_requesting_ld_input_id ld_input.io.req.valid := !loop_requesting_ld_input.ld_input_started && loop_requesting_ld_input.configured when (ld_input.io.req.fire) { loop_requesting_ld_input.running := true.B loop_requesting_ld_input.ld_input_started := true.B } val loop_requesting_ld_weights_id = Mux(head_loop.ld_weights_started, tail_loop_id, head_loop_id) val loop_requesting_ld_weights = loops(loop_requesting_ld_weights_id) ld_weights.io.req.bits.outer_bounds := loop_requesting_ld_weights.outer_bounds ld_weights.io.req.bits.inner_bounds := loop_requesting_ld_weights.inner_bounds ld_weights.io.req.bits.derived_params := loop_requesting_ld_weights.derived_params() ld_weights.io.req.bits.addr_end := Mux(loop_requesting_ld_weights.b_ex_spad_id === 0.U, loop_requesting_ld_weights.b_addr_end, (loop_requesting_ld_weights.b_ex_spad_id) * (max_addr / concurrent_loops).U) ld_weights.io.req.bits.dram_addr := loop_requesting_ld_weights.weights_dram_addr ld_weights.io.req.bits.trans_weight_1203 := loop_requesting_ld_weights.trans_weight_1203 ld_weights.io.req.bits.trans_weight_0132 := loop_requesting_ld_weights.trans_weight_0132 ld_weights.io.req.bits.dw := loop_requesting_ld_weights.dw ld_weights.io.req.bits.loop_id := loop_requesting_ld_weights_id ld_weights.io.req.valid := !loop_requesting_ld_weights.ld_weights_started && loop_requesting_ld_weights.configured when (ld_weights.io.req.fire) { loop_requesting_ld_weights.running := true.B loop_requesting_ld_weights.ld_weights_started := true.B } val loop_requesting_ex_id = Mux(head_loop.ex_started, tail_loop_id, head_loop_id) val loop_requesting_ex = loops(loop_requesting_ex_id) ex.io.req.bits.outer_bounds := loop_requesting_ex.outer_bounds ex.io.req.bits.inner_bounds := loop_requesting_ex.inner_bounds ex.io.req.bits.derived_params := loop_requesting_ex.derived_params() ex.io.req.bits.a_addr_start := Mux(loop_requesting_ex.a_ex_spad_id === 0.U, loop_requesting_ex.a_addr_start, (loop_requesting_ex.a_ex_spad_id - 1.U) * (max_addr / concurrent_loops).U) ex.io.req.bits.b_addr_end := Mux(loop_requesting_ex.b_ex_spad_id === 0.U, loop_requesting_ex.b_addr_end, (loop_requesting_ex.b_ex_spad_id) * (max_addr / concurrent_loops).U) ex.io.req.bits.c_addr_start := ex_c_addr_start ex.io.req.bits.wrot180 := loop_requesting_ex.wrot180 ex.io.req.bits.downsample := loop_requesting_ex.downsample ex.io.req.bits.max_pixels_per_row := loop_requesting_ex.max_pixels_per_row ex.io.req.bits.input_dilated := loop_requesting_ex.input_dilated ex.io.req.bits.trans_weight_0132 := loop_requesting_ex.trans_weight_0132 ex.io.req.bits.trans_input_3120 := loop_requesting_ex.trans_input_3120 ex.io.req.bits.loop_id := loop_requesting_ex_id ex.io.req.valid := !loop_requesting_ex.ex_started && loop_requesting_ex.ld_bias_started && loop_requesting_ex.ld_input_started && loop_requesting_ex.ld_weights_started && loop_requesting_ex.configured when (ex.io.req.fire) { loop_requesting_ex.running := true.B loop_requesting_ex.ex_started := true.B when (loop_requesting_ex.output_dram_addr =/= 0.U) { ex_c_addr_start := floorAdd(ex_c_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U) } } val loop_requesting_st_id = Mux(head_loop.st_started, tail_loop_id, head_loop_id) val loop_requesting_st = loops(loop_requesting_st_id) st.io.req.bits.outer_bounds := loop_requesting_st.outer_bounds st.io.req.bits.inner_bounds := loop_requesting_st.inner_bounds st.io.req.bits.derived_params := loop_requesting_st.derived_params() st.io.req.bits.addr_start := st_addr_start st.io.req.bits.dram_addr := loop_requesting_st.output_dram_addr st.io.req.bits.no_pool := loop_requesting_st.no_pool st.io.req.bits.activation := loop_requesting_st.activation st.io.req.bits.trans_output_1203 := loop_requesting_st.trans_output_1203 st.io.req.bits.loop_id := loop_requesting_st_id st.io.req.valid := !loop_requesting_st.st_started && loop_requesting_st.ex_started && loop_requesting_st.configured when (st.io.req.fire) { loop_requesting_st.running := true.B loop_requesting_st.st_started := true.B when (loop_requesting_st.output_dram_addr =/= 0.U) { st_addr_start := floorAdd(st_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U) } } // Handle completed signals when (ld_bias.io.idle && loops(ld_bias.io.loop_id).running && loops(ld_bias.io.loop_id).ld_bias_started) { loops(ld_bias.io.loop_id).ld_bias_completed := true.B } when (ld_input.io.idle && loops(ld_input.io.loop_id).running && loops(ld_input.io.loop_id).ld_input_started) { loops(ld_input.io.loop_id).ld_input_completed := true.B } when (ld_weights.io.idle && loops(ld_weights.io.loop_id).running && loops(ld_weights.io.loop_id).ld_weights_started) { loops(ld_weights.io.loop_id).ld_weights_completed := true.B } when (ex.io.idle && loops(ex.io.loop_id).running && loops(ex.io.loop_id).ex_started) { loops(ex.io.loop_id).ex_completed := true.B } when (st.io.idle && loops(st.io.loop_id).running && loops(st.io.loop_id).st_started) { loops(st.io.loop_id).st_completed := true.B } when (head_loop.running && head_loop.all_completed()) { head_loop.reset() head_loop_id := ~head_loop_id } // Resets when (reset.asBool) { loops.zipWithIndex.foreach { case (l, i) => l.reset() l.a_addr_start := (i * (max_addr / concurrent_loops)).U l.b_addr_end := ((i+1) * (max_addr / concurrent_loops)).U } } } object LoopConv { def apply(in: DecoupledIO[GemminiCmd], ld_completed: UInt, st_completed: UInt, ex_completed: UInt, block_size: Int, coreMaxAddrBits: Int, rob_size: Int, max_lds: Int, max_exs: Int, max_sts: Int, max_addr: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, dma_max_bytes: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2, config_mvout_rs2_t: ConfigMvoutRs2, mvout_rs2_t: MvoutRs2, config_ex_rs1_t: ConfigExRs1, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs, compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs, has_training_convs: Boolean, has_max_pool: Boolean, has_first_layer_optimizations: Boolean, has_dw_convs: Boolean) (implicit p: Parameters): (DecoupledIO[GemminiCmd], Bool) = { val mod = Module(new LoopConv(block_size, coreMaxAddrBits, rob_size, max_lds, max_exs, max_sts, max_addr, max_acc_addr, input_w, acc_w, dma_max_bytes, config_mvin_rs1_t, mvin_rs2_t, config_mvout_rs2_t, mvout_rs2_t, config_ex_rs1_t, preload_rs1_t, preload_rs2_t, compute_rs1_t, compute_rs2_t, has_training_convs, has_max_pool, has_first_layer_optimizations, has_dw_convs)) mod.io.in <> in mod.io.ld_completed := ld_completed mod.io.st_completed := st_completed mod.io.ex_completed := ex_completed (mod.io.out, mod.io.busy) } def castDramOffset(dram_offset: UInt): UInt = { // Cast dram offsets to 32 bits max dram_offset & "hFFFFFFFF".U } } File LocalAddr.scala: package gemmini import chisel3._ import chisel3.util._ class LocalAddr(sp_banks: Int, sp_bank_entries: Int, acc_banks: Int, acc_bank_entries: Int) extends Bundle { private val localAddrBits = 32 // TODO magic number private val spAddrBits = log2Ceil(sp_banks * sp_bank_entries) private val accAddrBits = log2Ceil(acc_banks * acc_bank_entries) private val maxAddrBits = spAddrBits max accAddrBits private val spBankBits = log2Up(sp_banks) private val spBankRowBits = log2Up(sp_bank_entries) private val accBankBits = log2Up(acc_banks) val accBankRowBits = log2Up(acc_bank_entries) val spRows = sp_banks * sp_bank_entries val is_acc_addr = Bool() val accumulate = Bool() val read_full_acc_row = Bool() val norm_cmd = NormCmd() private val metadata_w = is_acc_addr.getWidth + accumulate.getWidth + read_full_acc_row.getWidth + norm_cmd.getWidth assert(maxAddrBits + metadata_w < 32) val garbage = UInt(((localAddrBits - maxAddrBits - metadata_w - 1) max 0).W) val garbage_bit = if (localAddrBits - maxAddrBits >= metadata_w + 1) UInt(1.W) else UInt(0.W) val data = UInt(maxAddrBits.W) def sp_bank(dummy: Int = 0) = if (spAddrBits == spBankRowBits) 0.U else data(spAddrBits - 1, spBankRowBits) def sp_row(dummy: Int = 0) = data(spBankRowBits - 1, 0) def acc_bank(dummy: Int = 0) = if (accAddrBits == accBankRowBits) 0.U else data(accAddrBits - 1, accBankRowBits) def acc_row(dummy: Int = 0) = data(accBankRowBits - 1, 0) def full_sp_addr(dummy: Int = 0) = data(spAddrBits - 1, 0) def full_acc_addr(dummy: Int = 0) = data(accAddrBits - 1, 0) def is_same_address(other: LocalAddr): Bool = is_acc_addr === other.is_acc_addr && data === other.data def is_same_address(other: UInt): Bool = is_same_address(other.asTypeOf(this)) def is_garbage(dummy: Int = 0) = is_acc_addr && accumulate && read_full_acc_row && data.andR && (if (garbage_bit.getWidth > 0) garbage_bit.asBool else true.B) def +(other: UInt) = { require(isPow2(sp_bank_entries)) // TODO remove this requirement require(isPow2(acc_bank_entries)) // TODO remove this requirement val result = WireInit(this) result.data := data + other result } def <=(other: LocalAddr) = is_acc_addr === other.is_acc_addr && Mux(is_acc_addr, full_acc_addr() <= other.full_acc_addr(), full_sp_addr() <= other.full_sp_addr()) def <(other: LocalAddr) = is_acc_addr === other.is_acc_addr && Mux(is_acc_addr, full_acc_addr() < other.full_acc_addr(), full_sp_addr() < other.full_sp_addr()) def >(other: LocalAddr) = is_acc_addr === other.is_acc_addr && Mux(is_acc_addr, full_acc_addr() > other.full_acc_addr(), full_sp_addr() > other.full_sp_addr()) def add_with_overflow(other: UInt): Tuple2[LocalAddr, Bool] = { require(isPow2(sp_bank_entries)) // TODO remove this requirement require(isPow2(acc_bank_entries)) // TODO remove this requirement val sum = data +& other val overflow = Mux(is_acc_addr, sum(accAddrBits), sum(spAddrBits)) val result = WireInit(this) result.data := sum(maxAddrBits - 1, 0) (result, overflow) } // This function can only be used with non-accumulator addresses. Returns both new address and underflow def floorSub(other: UInt, floor: UInt): (LocalAddr, Bool) = { require(isPow2(sp_bank_entries)) // TODO remove this requirement require(isPow2(acc_bank_entries)) // TODO remove this requirement val underflow = data < (floor +& other) val result = WireInit(this) result.data := Mux(underflow, floor, data - other) (result, underflow) } def make_this_garbage(dummy: Int = 0): Unit = { is_acc_addr := true.B accumulate := true.B read_full_acc_row := true.B garbage_bit := 1.U data := ~(0.U(maxAddrBits.W)) } } object LocalAddr { def cast_to_local_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = { // This convenience function is basically the same as calling "asTypeOf(local_addr_t)". However, this convenience // function will also cast unnecessary garbage bits to 0, which may help reduce multiplier/adder bitwidths val result = WireInit(t.asTypeOf(local_addr_t)) if (result.garbage_bit.getWidth > 0) result.garbage := 0.U result } def cast_to_sp_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = { // This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage // address val result = WireInit(cast_to_local_addr(local_addr_t, t)) result.is_acc_addr := false.B result.accumulate := false.B result.read_full_acc_row := false.B // assert(!result.garbage_bit, "cast_to_sp_addr doesn't work on garbage addresses") result } def cast_to_acc_addr[T <: Data](local_addr_t: LocalAddr, t: T, accumulate: Bool, read_full: Bool): LocalAddr = { // This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage // address val result = WireInit(cast_to_local_addr(local_addr_t, t)) result.is_acc_addr := true.B result.accumulate := accumulate result.read_full_acc_row := read_full // assert(!result.garbage_bit, "cast_to_acc_addr doesn't work on garbage addresses") result } def garbage_addr(local_addr_t: LocalAddr): LocalAddr = { val result = Wire(chiselTypeOf(local_addr_t)) result := DontCare result.make_this_garbage() result } } File Util.scala: package gemmini import chisel3._ import chisel3.util._ object Util { def wrappingAdd(u: UInt, n: UInt, max_plus_one: Int): UInt = { val max = max_plus_one - 1 if (max == 0) { 0.U } else { assert(n <= max.U, "cannot wrapAdd when n is larger than max") Mux(u >= max.U - n + 1.U && n =/= 0.U, n - (max.U - u) - 1.U, u + n) } } def wrappingAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = { val max = max_plus_one - 1.U assert(n <= max \|\| max === 0.U, "cannot wrapAdd when n is larger than max, unless max is 0") /* Mux(!en, u, Mux (max === 0.U, 0.U, Mux(u >= max - n + 1.U && n =/= 0.U, n - (max - u) - 1.U, u + n))) */ MuxCase(u + n, Seq( (!en) -> u, (max === 0.U) -> 0.U, (u >= max - n + 1.U && n =/= 0.U) -> (n - (max - u) - 1.U) )) } def satAdd(u: UInt, v: UInt, max: UInt): UInt = { Mux(u +& v > max, max, u + v) } def floorAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = { val max = max_plus_one - 1.U MuxCase(u + n, Seq( (!en) -> u, ((u +& n) > max) -> 0.U )) } def sFloorAdd(s: SInt, n: UInt, max_plus_one: SInt, min: SInt, en: Bool = true.B): SInt = { val max = max_plus_one - 1.S MuxCase(s + n.zext, Seq( (!en) -> s, ((s +& n.zext) > max) -> min )) } def wrappingSub(u: UInt, n: UInt, max_plus_one: Int): UInt = { val max = max_plus_one - 1 assert(n <= max.U, "cannot wrapSub when n is larger than max") Mux(u < n, max.U - (n-u) + 1.U, u - n) } def ceilingDivide(numer: Int, denom: Int): Int = { if (numer % denom == 0) { numer / denom } else { numer / denom + 1} } def closestLowerPowerOf2(u: UInt): UInt = { // TODO figure out a more efficient way of doing this. Is this many muxes really necessary? val exp = u.asBools.zipWithIndex.map { case (b, i) => Mux(b, i.U, 0.U) }.reduce((acc, u) => Mux(acc > u, acc, u)) (1.U << exp).asUInt } def closestAlignedLowerPowerOf2(u: UInt, addr: UInt, stride: UInt, rowBytes: Int): UInt = { val lgRowBytes = log2Ceil(rowBytes) // TODO figure out a more efficient way of doing this. Is this many muxes really necessary? val exp = u.asBools.zipWithIndex.map { case (b, i) => Mux(b && addr(i + lgRowBytes - 1, 0) === 0.U && stride(i + lgRowBytes - 1, 0) === 0.U, i.U, 0.U) }.reduce((acc, u) => Mux(acc > u, acc, u)) (1.U << exp).asUInt } // This function will return "next" with a 0-cycle delay when the "enable" signal is high. It's like a queue with // the "pipe" and "flow" parameters set to "true" def RegEnableThru[T <: Data](next: T, enable: Bool): T = { val buf = RegEnable(next, enable) Mux(enable, next, buf) } def RegEnableThru[T <: Data](next: T, init: T, enable: Bool): T = { val buf = RegEnable(next, init, enable) Mux(enable, next, buf) } def maxOf(u1: UInt, u2: UInt): UInt = { Mux(u1 > u2, u1, u2) } def maxOf[T <: Data](x: T, y: T)(implicit ev: Arithmetic[T]): T = { import ev._ Mux(x > y, x, y) } def minOf(u1: UInt, u2: UInt): UInt = { Mux(u1 < u2, u1, u2) } def accumulateTree[T <: Data](xs: Seq[T])(implicit ev: Arithmetic[T]): T = { import ev._ assert(xs.nonEmpty, "can't accumulate 0 elements") if (xs.length == 1) { xs.head } else { val upperRowLen = 1 << log2Ceil(xs.length) val upperRow = xs.padTo(upperRowLen, xs.head.zero) val pairs = upperRow.grouped(2) val lowerRow = pairs.map { case Seq(a, b) => a + b } accumulateTree(lowerRow.toSeq) } } // An undirectioned Valid bundle class UDValid[T <: Data](t: T) extends Bundle { val valid = Bool() val bits = t.cloneType def push(b: T): Unit = { valid := true.B bits := b } def pop(dummy: Int = 0): T = { valid := false.B bits } } object UDValid { def apply[T <: Data](t: T): UDValid[T] = new UDValid(t) } // creates a Reg and the next-state Wire, and returns both def regwire(bits: Int) = { val wire = Wire(UInt(bits.W)) val reg = RegNext(wire) wire := reg // default wire to read from reg (reg, wire) } }	module LoopConvLdInput( // @[LoopConv.scala:235:7] input clock, // @[LoopConv.scala:235:7] input reset, // @[LoopConv.scala:235:7] output io_req_ready, // @[LoopConv.scala:241:14] input io_req_valid, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_batch_size, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_in_row_dim, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_in_col_dim, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_in_channels, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_out_channels, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_out_col_dim, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_out_row_dim, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_out_stride, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_in_stride, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_weight_stride, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_pool_out_row_dim, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_pool_out_col_dim, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_stride, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_padding, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_kernel_dim, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_kernel_dilation, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_pool_size, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_pool_stride, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_outer_bounds_pool_padding, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_batches, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_porows, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_pocols, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_pochs, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_krows, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_kcols, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_kchs, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_lpad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_rpad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_upad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_dpad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_plpad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_prad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_pupad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_pdpad, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_orows, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_inner_bounds_ocols, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_ochs, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_irows, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_icols, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_irows_unpadded, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_icols_unpadded, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_ichs, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_out_channels_per_bank, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_in_channels_per_bank, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_bias_spad_stride, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_input_spad_stride, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_derived_params_weight_spad_stride, // @[LoopConv.scala:241:14] input [13:0] io_req_bits_addr_start, // @[LoopConv.scala:241:14] input [39:0] io_req_bits_dram_addr, // @[LoopConv.scala:241:14] input io_req_bits_downsample, // @[LoopConv.scala:241:14] input [15:0] io_req_bits_max_pixels_per_row, // @[LoopConv.scala:241:14] input io_req_bits_input_dilated, // @[LoopConv.scala:241:14] input io_req_bits_trans_input_3120, // @[LoopConv.scala:241:14] input io_req_bits_loop_id, // @[LoopConv.scala:241:14] input io_cmd_ready, // @[LoopConv.scala:241:14] output io_cmd_valid, // @[LoopConv.scala:241:14] output [6:0] io_cmd_bits_inst_funct, // @[LoopConv.scala:241:14] output [4:0] io_cmd_bits_inst_rs2, // @[LoopConv.scala:241:14] output [4:0] io_cmd_bits_inst_rs1, // @[LoopConv.scala:241:14] output io_cmd_bits_inst_xd, // @[LoopConv.scala:241:14] output io_cmd_bits_inst_xs1, // @[LoopConv.scala:241:14] output io_cmd_bits_inst_xs2, // @[LoopConv.scala:241:14] output [4:0] io_cmd_bits_inst_rd, // @[LoopConv.scala:241:14] output [6:0] io_cmd_bits_inst_opcode, // @[LoopConv.scala:241:14] output [63:0] io_cmd_bits_rs1, // @[LoopConv.scala:241:14] output [63:0] io_cmd_bits_rs2, // @[LoopConv.scala:241:14] output io_cmd_bits_status_debug, // @[LoopConv.scala:241:14] output io_cmd_bits_status_cease, // @[LoopConv.scala:241:14] output io_cmd_bits_status_wfi, // @[LoopConv.scala:241:14] output [31:0] io_cmd_bits_status_isa, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_dprv, // @[LoopConv.scala:241:14] output io_cmd_bits_status_dv, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_prv, // @[LoopConv.scala:241:14] output io_cmd_bits_status_v, // @[LoopConv.scala:241:14] output io_cmd_bits_status_sd, // @[LoopConv.scala:241:14] output [22:0] io_cmd_bits_status_zero2, // @[LoopConv.scala:241:14] output io_cmd_bits_status_mpv, // @[LoopConv.scala:241:14] output io_cmd_bits_status_gva, // @[LoopConv.scala:241:14] output io_cmd_bits_status_mbe, // @[LoopConv.scala:241:14] output io_cmd_bits_status_sbe, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_sxl, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_uxl, // @[LoopConv.scala:241:14] output io_cmd_bits_status_sd_rv32, // @[LoopConv.scala:241:14] output [7:0] io_cmd_bits_status_zero1, // @[LoopConv.scala:241:14] output io_cmd_bits_status_tsr, // @[LoopConv.scala:241:14] output io_cmd_bits_status_tw, // @[LoopConv.scala:241:14] output io_cmd_bits_status_tvm, // @[LoopConv.scala:241:14] output io_cmd_bits_status_mxr, // @[LoopConv.scala:241:14] output io_cmd_bits_status_sum, // @[LoopConv.scala:241:14] output io_cmd_bits_status_mprv, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_xs, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_fs, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_mpp, // @[LoopConv.scala:241:14] output [1:0] io_cmd_bits_status_vs, // @[LoopConv.scala:241:14] output io_cmd_bits_status_spp, // @[LoopConv.scala:241:14] output io_cmd_bits_status_mpie, // @[LoopConv.scala:241:14] output io_cmd_bits_status_ube, // @[LoopConv.scala:241:14] output io_cmd_bits_status_spie, // @[LoopConv.scala:241:14] output io_cmd_bits_status_upie, // @[LoopConv.scala:241:14] output io_cmd_bits_status_mie, // @[LoopConv.scala:241:14] output io_cmd_bits_status_hie, // @[LoopConv.scala:241:14] output io_cmd_bits_status_sie, // @[LoopConv.scala:241:14] output io_cmd_bits_status_uie, // @[LoopConv.scala:241:14] output io_idle, // @[LoopConv.scala:241:14] input io_rob_overloaded, // @[LoopConv.scala:241:14] input io_wait_for_prev_loop, // @[LoopConv.scala:241:14] output io_loop_id // @[LoopConv.scala:241:14] ); wire _mvin_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:37] wire [13:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:37] wire [6:0] mvin_cmd_rs2_num_cols; // @[LoopConv.scala:355:28] wire [2:0] mvin_cmd_rs2_local_addr_norm_cmd; // @[LoopConv.scala:355:28] wire _command_p_io_in_ready; // @[LoopConv.scala:313:25] wire _command_p_io_out_valid; // @[LoopConv.scala:313:25] wire [6:0] _command_p_io_out_bits_cmd_inst_funct; // @[LoopConv.scala:313:25] wire [63:0] _command_p_io_out_bits_cmd_rs1; // @[LoopConv.scala:313:25] wire [63:0] _command_p_io_out_bits_cmd_rs2; // @[LoopConv.scala:313:25] wire [67:0] _command_p_io_out_bits_dram_addr; // @[LoopConv.scala:313:25] wire [19:0] _command_p_io_out_bits_I; // @[LoopConv.scala:313:25] wire _command_p_io_busy; // @[LoopConv.scala:313:25] wire io_req_valid_0 = io_req_valid; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_batch_size_0 = io_req_bits_outer_bounds_batch_size; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_in_row_dim_0 = io_req_bits_outer_bounds_in_row_dim; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_in_col_dim_0 = io_req_bits_outer_bounds_in_col_dim; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_in_channels_0 = io_req_bits_outer_bounds_in_channels; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_out_channels_0 = io_req_bits_outer_bounds_out_channels; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_out_col_dim_0 = io_req_bits_outer_bounds_out_col_dim; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_out_row_dim_0 = io_req_bits_outer_bounds_out_row_dim; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_out_stride_0 = io_req_bits_outer_bounds_out_stride; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_in_stride_0 = io_req_bits_outer_bounds_in_stride; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_weight_stride_0 = io_req_bits_outer_bounds_weight_stride; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_pool_out_row_dim_0 = io_req_bits_outer_bounds_pool_out_row_dim; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_pool_out_col_dim_0 = io_req_bits_outer_bounds_pool_out_col_dim; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_stride_0 = io_req_bits_outer_bounds_stride; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_padding_0 = io_req_bits_outer_bounds_padding; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_kernel_dim_0 = io_req_bits_outer_bounds_kernel_dim; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_kernel_dilation_0 = io_req_bits_outer_bounds_kernel_dilation; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_pool_size_0 = io_req_bits_outer_bounds_pool_size; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_pool_stride_0 = io_req_bits_outer_bounds_pool_stride; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_outer_bounds_pool_padding_0 = io_req_bits_outer_bounds_pool_padding; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_batches_0 = io_req_bits_inner_bounds_batches; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_porows_0 = io_req_bits_inner_bounds_porows; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_pocols_0 = io_req_bits_inner_bounds_pocols; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_pochs_0 = io_req_bits_inner_bounds_pochs; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_krows_0 = io_req_bits_inner_bounds_krows; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_kcols_0 = io_req_bits_inner_bounds_kcols; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_kchs_0 = io_req_bits_inner_bounds_kchs; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_lpad_0 = io_req_bits_inner_bounds_lpad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_rpad_0 = io_req_bits_inner_bounds_rpad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_upad_0 = io_req_bits_inner_bounds_upad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_dpad_0 = io_req_bits_inner_bounds_dpad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_plpad_0 = io_req_bits_inner_bounds_plpad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_prad_0 = io_req_bits_inner_bounds_prad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_pupad_0 = io_req_bits_inner_bounds_pupad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_pdpad_0 = io_req_bits_inner_bounds_pdpad; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_orows_0 = io_req_bits_inner_bounds_orows; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_inner_bounds_ocols_0 = io_req_bits_inner_bounds_ocols; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_ochs_0 = io_req_bits_derived_params_ochs; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_irows_0 = io_req_bits_derived_params_irows; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_icols_0 = io_req_bits_derived_params_icols; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_irows_unpadded_0 = io_req_bits_derived_params_irows_unpadded; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_icols_unpadded_0 = io_req_bits_derived_params_icols_unpadded; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_ichs_0 = io_req_bits_derived_params_ichs; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_out_channels_per_bank_0 = io_req_bits_derived_params_out_channels_per_bank; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_in_channels_per_bank_0 = io_req_bits_derived_params_in_channels_per_bank; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_bias_spad_stride_0 = io_req_bits_derived_params_bias_spad_stride; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_input_spad_stride_0 = io_req_bits_derived_params_input_spad_stride; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_derived_params_weight_spad_stride_0 = io_req_bits_derived_params_weight_spad_stride; // @[LoopConv.scala:235:7] wire [13:0] io_req_bits_addr_start_0 = io_req_bits_addr_start; // @[LoopConv.scala:235:7] wire [39:0] io_req_bits_dram_addr_0 = io_req_bits_dram_addr; // @[LoopConv.scala:235:7] wire io_req_bits_downsample_0 = io_req_bits_downsample; // @[LoopConv.scala:235:7] wire [15:0] io_req_bits_max_pixels_per_row_0 = io_req_bits_max_pixels_per_row; // @[LoopConv.scala:235:7] wire io_req_bits_input_dilated_0 = io_req_bits_input_dilated; // @[LoopConv.scala:235:7] wire io_req_bits_trans_input_3120_0 = io_req_bits_trans_input_3120; // @[LoopConv.scala:235:7] wire io_req_bits_loop_id_0 = io_req_bits_loop_id; // @[LoopConv.scala:235:7] wire io_cmd_ready_0 = io_cmd_ready; // @[LoopConv.scala:235:7] wire io_rob_overloaded_0 = io_rob_overloaded; // @[LoopConv.scala:235:7] wire io_wait_for_prev_loop_0 = io_wait_for_prev_loop; // @[LoopConv.scala:235:7] wire [2:0] config_cmd_rs1__spacer1 = 3'h0; // @[LoopConv.scala:319:28] wire [2:0] config_cmd_rs1__spacer0 = 3'h0; // @[LoopConv.scala:319:28] wire [1:0] config_cmd_rs1__unused = 2'h1; // @[LoopConv.scala:319:28, :343:41] wire [2:0] config_cmd_rs1_lo_lo = 3'h1; // @[LoopConv.scala:327:36] wire [31:0] config_cmd_rs1_scale = 32'h3F800000; // @[LoopConv.scala:319:28] wire [31:0] config_cmd_rs1_hi_hi_hi = 32'h3F800000; // @[LoopConv.scala:327:36] wire [33:0] config_cmd_rs1_hi_hi = 34'hFE000000; // @[LoopConv.scala:327:36] wire [6:0] mvin_cmd_inst_funct = 7'h2; // @[LoopConv.scala:331:22, :352:46] wire [63:0] mvin_cmd_rs1 = 64'h0; // @[LoopConv.scala:331:22] wire [63:0] mvin_cmd_rs2 = 64'h0; // @[LoopConv.scala:331:22] wire [4:0] config_cmd_inst_rs2 = 5'h0; // @[LoopConv.scala:315:24] wire [4:0] config_cmd_inst_rs1 = 5'h0; // @[LoopConv.scala:315:24] wire [4:0] config_cmd_inst_rd = 5'h0; // @[LoopConv.scala:315:24] wire [4:0] mvin_cmd_inst_rs2 = 5'h0; // @[LoopConv.scala:331:22] wire [4:0] mvin_cmd_inst_rs1 = 5'h0; // @[LoopConv.scala:331:22] wire [4:0] mvin_cmd_inst_rd = 5'h0; // @[LoopConv.scala:331:22] wire [4:0] _command_p_io_in_bits_cmd_T_1_inst_rs2 = 5'h0; // @[LoopConv.scala:343:34] wire [4:0] _command_p_io_in_bits_cmd_T_1_inst_rs1 = 5'h0; // @[LoopConv.scala:343:34] wire [4:0] _command_p_io_in_bits_cmd_T_1_inst_rd = 5'h0; // @[LoopConv.scala:343:34] wire [6:0] config_cmd_inst_funct = 7'h0; // @[LoopConv.scala:315:24] wire [6:0] config_cmd_inst_opcode = 7'h0; // @[LoopConv.scala:315:24] wire [6:0] mvin_cmd_inst_opcode = 7'h0; // @[LoopConv.scala:331:22] wire [6:0] _command_p_io_in_bits_cmd_T_1_inst_opcode = 7'h0; // @[LoopConv.scala:343:34] wire [31:0] config_cmd_status_isa = 32'h0; // @[LoopConv.scala:315:24] wire [31:0] mvin_cmd_status_isa = 32'h0; // @[LoopConv.scala:331:22] wire [31:0] _command_p_io_in_bits_cmd_T_1_status_isa = 32'h0; // @[LoopConv.scala:343:34] wire [22:0] config_cmd_status_zero2 = 23'h0; // @[LoopConv.scala:315:24] wire [22:0] mvin_cmd_status_zero2 = 23'h0; // @[LoopConv.scala:331:22] wire [22:0] _command_p_io_in_bits_cmd_T_1_status_zero2 = 23'h0; // @[LoopConv.scala:343:34] wire [7:0] config_cmd_status_zero1 = 8'h0; // @[LoopConv.scala:315:24] wire [7:0] mvin_cmd_status_zero1 = 8'h0; // @[LoopConv.scala:331:22] wire [7:0] _command_p_io_in_bits_cmd_T_1_status_zero1 = 8'h0; // @[LoopConv.scala:343:34] wire [8:0] mvin_cmd_rs2__spacer1 = 9'h0; // @[LoopConv.scala:355:28] wire [10:0] mvin_cmd_rs2__spacer2 = 11'h0; // @[LoopConv.scala:355:28] wire [10:0] mvin_cmd_rs2_local_addr_garbage = 11'h0; // @[LoopConv.scala:355:28] wire [10:0] mvin_cmd_rs2_local_addr_result_result_garbage = 11'h0; // @[LocalAddr.scala:108:26] wire [10:0] mvin_cmd_rs2_local_addr_result_garbage = 11'h0; // @[LocalAddr.scala:116:26] wire [1:0] config_cmd_status_dprv = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_status_prv = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_status_sxl = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_status_uxl = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_status_xs = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_status_fs = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_status_mpp = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_status_vs = 2'h0; // @[LoopConv.scala:256:22, :315:24] wire [1:0] config_cmd_rs1__spacer2 = 2'h0; // @[LoopConv.scala:256:22, :319:28] wire [1:0] config_cmd_rs1_state_id = 2'h0; // @[LoopConv.scala:256:22, :319:28] wire [1:0] mvin_cmd_status_dprv = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] mvin_cmd_status_prv = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] mvin_cmd_status_sxl = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] mvin_cmd_status_uxl = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] mvin_cmd_status_xs = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] mvin_cmd_status_fs = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] mvin_cmd_status_mpp = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] mvin_cmd_status_vs = 2'h0; // @[LoopConv.scala:256:22, :331:22] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_dprv = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_prv = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_sxl = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_uxl = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_xs = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_fs = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_mpp = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] _command_p_io_in_bits_cmd_T_1_status_vs = 2'h0; // @[LoopConv.scala:256:22, :343:34] wire [1:0] io_cmd_bits_rs2_hi_hi = 2'h0; // @[LoopConv.scala:256:22, :360:37] wire config_cmd_inst_xd = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_inst_xs1 = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_inst_xs2 = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_debug = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_cease = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_wfi = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_dv = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_v = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_sd = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_mpv = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_gva = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_mbe = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_sbe = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_sd_rv32 = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_tsr = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_tw = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_tvm = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_mxr = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_sum = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_mprv = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_spp = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_mpie = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_ube = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_spie = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_upie = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_mie = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_hie = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_sie = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_status_uie = 1'h0; // @[LoopConv.scala:315:24] wire config_cmd_rs1_shrink = 1'h0; // @[LoopConv.scala:319:28] wire mvin_cmd_inst_xd = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_inst_xs1 = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_inst_xs2 = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_debug = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_cease = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_wfi = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_dv = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_v = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_sd = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_mpv = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_gva = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_mbe = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_sbe = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_sd_rv32 = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_tsr = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_tw = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_tvm = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_mxr = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_sum = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_mprv = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_spp = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_mpie = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_ube = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_spie = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_upie = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_mie = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_hie = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_sie = 1'h0; // @[LoopConv.scala:331:22] wire mvin_cmd_status_uie = 1'h0; // @[LoopConv.scala:331:22] wire _io_req_ready_T_2; // @[LoopConv.scala:338:34] wire _command_p_io_in_bits_cmd_T_1_inst_xd = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_inst_xs1 = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_inst_xs2 = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_debug = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_cease = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_wfi = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_dv = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_v = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_sd = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_mpv = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_gva = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_mbe = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_sbe = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_sd_rv32 = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_tsr = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_tw = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_tvm = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_mxr = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_sum = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_mprv = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_spp = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_mpie = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_ube = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_spie = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_upie = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_mie = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_hie = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_sie = 1'h0; // @[LoopConv.scala:343:34] wire _command_p_io_in_bits_cmd_T_1_status_uie = 1'h0; // @[LoopConv.scala:343:34] wire mvin_cmd_rs2_local_addr_is_acc_addr = 1'h0; // @[LoopConv.scala:355:28] wire mvin_cmd_rs2_local_addr_accumulate = 1'h0; // @[LoopConv.scala:355:28] wire mvin_cmd_rs2_local_addr_read_full_acc_row = 1'h0; // @[LoopConv.scala:355:28] wire mvin_cmd_rs2_local_addr_result_is_acc_addr = 1'h0; // @[LocalAddr.scala:116:26] wire mvin_cmd_rs2_local_addr_result_accumulate = 1'h0; // @[LocalAddr.scala:116:26] wire mvin_cmd_rs2_local_addr_result_read_full_acc_row = 1'h0; // @[LocalAddr.scala:116:26] wire _next_ich_T_5 = 1'h0; // @[Util.scala:51:8] wire _io_cmd_valid_T_1; // @[LoopConv.scala:350:42] wire _io_idle_T_2; // @[LoopConv.scala:339:29] wire io_req_ready_0; // @[LoopConv.scala:235:7] wire [6:0] io_cmd_bits_inst_funct_0; // @[LoopConv.scala:235:7] wire [4:0] io_cmd_bits_inst_rs2_0; // @[LoopConv.scala:235:7] wire [4:0] io_cmd_bits_inst_rs1_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_inst_xd_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_inst_xs1_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_inst_xs2_0; // @[LoopConv.scala:235:7] wire [4:0] io_cmd_bits_inst_rd_0; // @[LoopConv.scala:235:7] wire [6:0] io_cmd_bits_inst_opcode_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_debug_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_cease_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_wfi_0; // @[LoopConv.scala:235:7] wire [31:0] io_cmd_bits_status_isa_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_dprv_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_dv_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_prv_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_v_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_sd_0; // @[LoopConv.scala:235:7] wire [22:0] io_cmd_bits_status_zero2_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_mpv_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_gva_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_mbe_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_sbe_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_sxl_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_uxl_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_sd_rv32_0; // @[LoopConv.scala:235:7] wire [7:0] io_cmd_bits_status_zero1_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_tsr_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_tw_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_tvm_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_mxr_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_sum_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_mprv_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_xs_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_fs_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_mpp_0; // @[LoopConv.scala:235:7] wire [1:0] io_cmd_bits_status_vs_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_spp_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_mpie_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_ube_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_spie_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_upie_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_mie_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_hie_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_sie_0; // @[LoopConv.scala:235:7] wire io_cmd_bits_status_uie_0; // @[LoopConv.scala:235:7] wire [63:0] io_cmd_bits_rs1_0; // @[LoopConv.scala:235:7] wire [63:0] io_cmd_bits_rs2_0; // @[LoopConv.scala:235:7] wire io_cmd_valid_0; // @[LoopConv.scala:235:7] wire io_idle_0; // @[LoopConv.scala:235:7] wire io_loop_id_0; // @[LoopConv.scala:235:7] reg [1:0] state; // @[LoopConv.scala:256:22] reg [15:0] req_outer_bounds_batch_size; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_in_row_dim; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_in_col_dim; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_in_channels; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_out_channels; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_out_col_dim; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_out_row_dim; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_out_stride; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_in_stride; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_weight_stride; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_pool_out_row_dim; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_pool_out_col_dim; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_stride; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_padding; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_kernel_dim; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_kernel_dilation; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_pool_size; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_pool_stride; // @[LoopConv.scala:258:16] reg [15:0] req_outer_bounds_pool_padding; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_batches; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_porows; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_pocols; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_pochs; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_krows; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_kcols; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_kchs; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_lpad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_rpad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_upad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_dpad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_plpad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_prad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_pupad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_pdpad; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_orows; // @[LoopConv.scala:258:16] reg [15:0] req_inner_bounds_ocols; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_ochs; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_irows; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_icols; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_irows_unpadded; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_icols_unpadded; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_ichs; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_out_channels_per_bank; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_in_channels_per_bank; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_bias_spad_stride; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_input_spad_stride; // @[LoopConv.scala:258:16] reg [15:0] req_derived_params_weight_spad_stride; // @[LoopConv.scala:258:16] reg [13:0] req_addr_start; // @[LoopConv.scala:258:16] reg [39:0] req_dram_addr; // @[LoopConv.scala:258:16] reg req_downsample; // @[LoopConv.scala:258:16] reg [15:0] req_max_pixels_per_row; // @[LoopConv.scala:258:16] reg req_input_dilated; // @[LoopConv.scala:258:16] reg req_trans_input_3120; // @[LoopConv.scala:258:16] reg req_loop_id; // @[LoopConv.scala:258:16] assign io_loop_id_0 = req_loop_id; // @[LoopConv.scala:235:7, :258:16] wire _max_ichs_per_mvin_T = req_derived_params_ichs < 16'h40; // @[LoopConv.scala:258:16, :266:36] wire [15:0] _max_ichs_per_mvin_T_1 = _max_ichs_per_mvin_T ? req_derived_params_ichs : 16'h40; // @[LoopConv.scala:258:16, :266:{30,36}] wire [16:0] max_ichs_per_mvin = {1'h0, _max_ichs_per_mvin_T_1}; // @[LoopConv.scala:266:{30,108}] wire _max_batches_per_mvin_T = req_inner_bounds_batches < 16'h40; // @[LoopConv.scala:258:16, :266:36, :267:42] wire [15:0] _max_batches_per_mvin_T_1 = _max_batches_per_mvin_T ? req_inner_bounds_batches : 16'h40; // @[LoopConv.scala:258:16, :266:36, :267:{33,42}] wire [16:0] max_batches_per_mvin = {1'h0, _max_batches_per_mvin_T_1}; // @[LoopConv.scala:267:{33,117}] wire [16:0] max_chs_per_mvin = req_trans_input_3120 ? max_batches_per_mvin : max_ichs_per_mvin; // @[LoopConv.scala:258:16, :266:108, :267:117, :268:29] wire [16:0] _b_it_T = max_chs_per_mvin; // @[LoopConv.scala:268:29, :370:61] wire [16:0] _ich_it_T = max_chs_per_mvin; // @[LoopConv.scala:268:29, :371:68] reg [15:0] b; // @[LoopConv.scala:271:14] reg [15:0] irow; // @[LoopConv.scala:272:17] reg [15:0] icol; // @[LoopConv.scala:273:17] reg [15:0] ich; // @[LoopConv.scala:274:16] wire [16:0] _GEN = {16'h0, req_input_dilated}; // @[LoopConv.scala:258:16, :263:37, :279:23] wire [16:0] _GEN_0 = {1'h0, req_inner_bounds_upad} + _GEN; // @[LoopConv.scala:258:16, :263:37] wire [16:0] _irow_padded_T; // @[LoopConv.scala:263:37] assign _irow_padded_T = _GEN_0; // @[LoopConv.scala:263:37] wire [16:0] _next_irow_T_5; // @[LoopConv.scala:263:37] assign _next_irow_T_5 = _GEN_0; // @[LoopConv.scala:263:37] wire [16:0] _next_b_T_1; // @[LoopConv.scala:263:37] assign _next_b_T_1 = _GEN_0; // @[LoopConv.scala:263:37] wire [16:0] _state_T_1; // @[LoopConv.scala:263:37] assign _state_T_1 = _GEN_0; // @[LoopConv.scala:263:37] wire [16:0] _irow_padded_T_1 = _irow_padded_T >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _irow_padded_T_2 = {1'h0, _irow_padded_T_1}; // @[LoopConv.scala:263:59, :277:45] wire [18:0] _GEN_1 = {{3{irow[15]}}, irow}; // @[LoopConv.scala:272:17, :277:26] wire [18:0] irow_padded = _GEN_1 + {_irow_padded_T_2[17], _irow_padded_T_2}; // @[LoopConv.scala:277:{26,45}] wire [16:0] _GEN_2 = {1'h0, req_inner_bounds_lpad} + _GEN; // @[LoopConv.scala:258:16, :263:37] wire [16:0] _icol_padded_T; // @[LoopConv.scala:263:37] assign _icol_padded_T = _GEN_2; // @[LoopConv.scala:263:37] wire [16:0] _next_icol_T_5; // @[LoopConv.scala:263:37] assign _next_icol_T_5 = _GEN_2; // @[LoopConv.scala:263:37] wire [16:0] _next_irow_T_9; // @[LoopConv.scala:263:37] assign _next_irow_T_9 = _GEN_2; // @[LoopConv.scala:263:37] wire [16:0] _next_b_T_6; // @[LoopConv.scala:263:37] assign _next_b_T_6 = _GEN_2; // @[LoopConv.scala:263:37] wire [16:0] _state_T_7; // @[LoopConv.scala:263:37] assign _state_T_7 = _GEN_2; // @[LoopConv.scala:263:37] wire [16:0] _icol_padded_T_1 = _icol_padded_T >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _icol_padded_T_2 = {1'h0, _icol_padded_T_1}; // @[LoopConv.scala:263:59, :278:45] wire [18:0] icol_padded = {{3{icol[15]}}, icol} + {_icol_padded_T_2[17], _icol_padded_T_2}; // @[LoopConv.scala:273:17, :278:{26,45}] wire _is_zeros_T = $signed(irow) < 16'sh0; // @[LoopConv.scala:272:17, :279:23] wire [16:0] _is_zeros_T_1 = {1'h0, req_derived_params_irows_unpadded}; // @[LoopConv.scala:258:16, :279:55] wire [16:0] _GEN_3 = {irow[15], irow}; // @[LoopConv.scala:272:17, :277:26, :279:37] wire _is_zeros_T_2 = $signed(_GEN_3) >= $signed(_is_zeros_T_1); // @[LoopConv.scala:279:{37,55}] wire _is_zeros_T_3 = _is_zeros_T \| _is_zeros_T_2; // @[LoopConv.scala:279:{23,29,37}] wire _GEN_4 = $signed(icol) < 16'sh0; // @[LoopConv.scala:273:17, :279:{23,68}] wire _is_zeros_T_4; // @[LoopConv.scala:279:68] assign _is_zeros_T_4 = _GEN_4; // @[LoopConv.scala:279:68] wire _I_T_6; // @[LoopConv.scala:298:13] assign _I_T_6 = _GEN_4; // @[LoopConv.scala:279:68, :298:13] wire _is_zeros_T_5 = _is_zeros_T_3 \| _is_zeros_T_4; // @[LoopConv.scala:279:{29,60,68}] wire [16:0] _GEN_5 = {1'h0, req_derived_params_icols_unpadded}; // @[LoopConv.scala:258:16, :279:100] wire [16:0] _is_zeros_T_6; // @[LoopConv.scala:279:100] assign _is_zeros_T_6 = _GEN_5; // @[LoopConv.scala:279:100] wire [16:0] _I_T; // @[LoopConv.scala:296:24] assign _I_T = _GEN_5; // @[LoopConv.scala:279:100, :296:24] wire [16:0] _I_T_3; // @[LoopConv.scala:296:102] assign _I_T_3 = _GEN_5; // @[LoopConv.scala:279:100, :296:102] wire [16:0] _I_T_11; // @[LoopConv.scala:299:31] assign _I_T_11 = _GEN_5; // @[LoopConv.scala:279:100, :299:31] wire [16:0] _I_T_13; // @[LoopConv.scala:299:59] assign _I_T_13 = _GEN_5; // @[LoopConv.scala:279:100, :299:59] wire [16:0] _I_T_20; // @[LoopConv.scala:299:141] assign _I_T_20 = _GEN_5; // @[LoopConv.scala:279:100, :299:141] wire [16:0] _GEN_6 = {icol[15], icol}; // @[LoopConv.scala:273:17, :278:26, :279:82] wire _is_zeros_T_7 = $signed(_GEN_6) >= $signed(_is_zeros_T_6); // @[LoopConv.scala:279:{82,100}] wire is_zeros = _is_zeros_T_5 \| _is_zeros_T_7; // @[LoopConv.scala:279:{60,74,82}] wire [16:0] _dram_stride_T = {1'h0, req_outer_bounds_batch_size}; // @[LoopConv.scala:258:16, :281:58] wire [16:0] _GEN_7 = {1'h0, req_outer_bounds_in_stride}; // @[LoopConv.scala:258:16, :281:85] wire [16:0] _dram_stride_T_1; // @[LoopConv.scala:281:85] assign _dram_stride_T_1 = _GEN_7; // @[LoopConv.scala:281:85] wire [16:0] _dram_offset_T_37; // @[LoopConv.scala:285:64] assign _dram_offset_T_37 = _GEN_7; // @[LoopConv.scala:281:85, :285:64] wire [16:0] dram_stride = req_trans_input_3120 ? _dram_stride_T : _dram_stride_T_1; // @[LoopConv.scala:258:16, :281:{24,58,85}] wire [16:0] _GEN_8 = {1'h0, req_outer_bounds_in_col_dim}; // @[LoopConv.scala:258:16, :284:54] wire [16:0] _dram_offset_T; // @[LoopConv.scala:284:54] assign _dram_offset_T = _GEN_8; // @[LoopConv.scala:284:54] wire [16:0] _dram_offset_T_8; // @[LoopConv.scala:284:87] assign _dram_offset_T_8 = _GEN_8; // @[LoopConv.scala:284:{54,87}] wire [16:0] _dram_offset_T_27; // @[LoopConv.scala:285:23] assign _dram_offset_T_27 = _GEN_8; // @[LoopConv.scala:284:54, :285:23] wire [16:0] _dram_offset_T_31; // @[LoopConv.scala:285:43] assign _dram_offset_T_31 = _GEN_8; // @[LoopConv.scala:284:54, :285:43] wire [32:0] _GEN_9 = {{17{ich[15]}}, ich}; // @[LoopConv.scala:274:16, :284:54] wire [32:0] _dram_offset_T_1 = _GEN_9 * {{16{_dram_offset_T[16]}}, _dram_offset_T}; // @[LoopConv.scala:284:54] wire [31:0] _dram_offset_T_2 = _dram_offset_T_1[31:0]; // @[LoopConv.scala:284:54] wire [31:0] _dram_offset_T_3 = _dram_offset_T_2; // @[LoopConv.scala:284:54] wire [16:0] _GEN_10 = {1'h0, req_outer_bounds_in_row_dim}; // @[LoopConv.scala:258:16, :284:67] wire [16:0] _dram_offset_T_4; // @[LoopConv.scala:284:67] assign _dram_offset_T_4 = _GEN_10; // @[LoopConv.scala:284:67] wire [16:0] _dram_offset_T_23; // @[LoopConv.scala:285:10] assign _dram_offset_T_23 = _GEN_10; // @[LoopConv.scala:284:67, :285:10] wire [48:0] _dram_offset_T_5 = {{17{_dram_offset_T_3[31]}}, _dram_offset_T_3} * {{32{_dram_offset_T_4[16]}}, _dram_offset_T_4}; // @[LoopConv.scala:284:{54,67}] wire [47:0] _dram_offset_T_6 = _dram_offset_T_5[47:0]; // @[LoopConv.scala:284:67] wire [47:0] _dram_offset_T_7 = _dram_offset_T_6; // @[LoopConv.scala:284:67] wire [32:0] _GEN_11 = {{17{irow[15]}}, irow}; // @[LoopConv.scala:272:17, :277:26, :284:87] wire [32:0] _dram_offset_T_9 = _GEN_11 * {{16{_dram_offset_T_8[16]}}, _dram_offset_T_8}; // @[LoopConv.scala:284:87] wire [31:0] _dram_offset_T_10 = _dram_offset_T_9[31:0]; // @[LoopConv.scala:284:87] wire [31:0] _dram_offset_T_11 = _dram_offset_T_10; // @[LoopConv.scala:284:87] wire [48:0] _dram_offset_T_12 = {_dram_offset_T_7[47], _dram_offset_T_7} + {{17{_dram_offset_T_11[31]}}, _dram_offset_T_11}; // @[LoopConv.scala:284:{67,80,87}] wire [49:0] _GEN_12 = {{34{icol[15]}}, icol}; // @[LoopConv.scala:273:17, :278:26, :284:99] wire [49:0] _dram_offset_T_13 = {_dram_offset_T_12[48], _dram_offset_T_12} + _GEN_12; // @[LoopConv.scala:284:{80,99}] wire [16:0] _GEN_13 = {1'h0, req_inner_bounds_batches}; // @[LoopConv.scala:258:16, :284:108] wire [16:0] _dram_offset_T_14; // @[LoopConv.scala:284:108] assign _dram_offset_T_14 = _GEN_13; // @[LoopConv.scala:284:108] wire [16:0] _K_T; // @[LoopConv.scala:303:17] assign _K_T = _GEN_13; // @[LoopConv.scala:284:108, :303:17] wire [16:0] _K_T_3; // @[LoopConv.scala:303:73] assign _K_T_3 = _GEN_13; // @[LoopConv.scala:284:108, :303:73] wire [16:0] _next_b_T; // @[LoopConv.scala:378:47] assign _next_b_T = _GEN_13; // @[LoopConv.scala:284:108, :378:47] wire [66:0] _dram_offset_T_15 = {{17{_dram_offset_T_13[49]}}, _dram_offset_T_13} * {{50{_dram_offset_T_14[16]}}, _dram_offset_T_14}; // @[LoopConv.scala:284:{99,108}] wire [65:0] _dram_offset_T_16 = _dram_offset_T_15[65:0]; // @[LoopConv.scala:284:108] wire [65:0] _dram_offset_T_17 = _dram_offset_T_16; // @[LoopConv.scala:284:108] wire [66:0] _dram_offset_T_18 = {_dram_offset_T_17[65], _dram_offset_T_17} + {{51{b[15]}}, b}; // @[LoopConv.scala:271:14, :284:{108,118}] wire [68:0] _dram_offset_T_19 = {{2{_dram_offset_T_18[66]}}, _dram_offset_T_18}; // @[LoopConv.scala:284:{118,124}] wire [67:0] _dram_offset_T_20 = _dram_offset_T_19[67:0]; // @[LoopConv.scala:284:124] wire [67:0] _dram_offset_T_21 = _dram_offset_T_20; // @[LoopConv.scala:284:124] wire [67:0] _dram_offset_T_22 = _dram_offset_T_21; // @[LoopConv.scala:284:{124,141}] wire [32:0] _GEN_14 = {{17{b[15]}}, b}; // @[LoopConv.scala:271:14, :284:118, :285:10] wire [32:0] _dram_offset_T_24 = _GEN_14 * {{16{_dram_offset_T_23[16]}}, _dram_offset_T_23}; // @[LoopConv.scala:285:10] wire [31:0] _dram_offset_T_25 = _dram_offset_T_24[31:0]; // @[LoopConv.scala:285:10] wire [31:0] _dram_offset_T_26 = _dram_offset_T_25; // @[LoopConv.scala:285:10] wire [48:0] _dram_offset_T_28 = {{17{_dram_offset_T_26[31]}}, _dram_offset_T_26} * {{32{_dram_offset_T_27[16]}}, _dram_offset_T_27}; // @[LoopConv.scala:285:{10,23}] wire [47:0] _dram_offset_T_29 = _dram_offset_T_28[47:0]; // @[LoopConv.scala:285:23] wire [47:0] _dram_offset_T_30 = _dram_offset_T_29; // @[LoopConv.scala:285:23] wire [32:0] _dram_offset_T_32 = _GEN_11 * {{16{_dram_offset_T_31[16]}}, _dram_offset_T_31}; // @[LoopConv.scala:284:87, :285:43] wire [31:0] _dram_offset_T_33 = _dram_offset_T_32[31:0]; // @[LoopConv.scala:285:43] wire [31:0] _dram_offset_T_34 = _dram_offset_T_33; // @[LoopConv.scala:285:43] wire [48:0] _dram_offset_T_35 = {_dram_offset_T_30[47], _dram_offset_T_30} + {{17{_dram_offset_T_34[31]}}, _dram_offset_T_34}; // @[LoopConv.scala:285:{23,36,43}] wire [49:0] _dram_offset_T_36 = {_dram_offset_T_35[48], _dram_offset_T_35} + _GEN_12; // @[LoopConv.scala:284:99, :285:{36,55}] wire [66:0] _dram_offset_T_38 = {{17{_dram_offset_T_36[49]}}, _dram_offset_T_36} * {{50{_dram_offset_T_37[16]}}, _dram_offset_T_37}; // @[LoopConv.scala:285:{55,64}] wire [65:0] _dram_offset_T_39 = _dram_offset_T_38[65:0]; // @[LoopConv.scala:285:64] wire [65:0] _dram_offset_T_40 = _dram_offset_T_39; // @[LoopConv.scala:285:64] wire [66:0] _dram_offset_T_41 = {_dram_offset_T_40[65], _dram_offset_T_40} + {{51{ich[15]}}, ich}; // @[LoopConv.scala:274:16, :284:54, :285:{64,76}] wire [68:0] _dram_offset_T_42 = {{2{_dram_offset_T_41[66]}}, _dram_offset_T_41}; // @[LoopConv.scala:285:{76,84}] wire [67:0] _dram_offset_T_43 = _dram_offset_T_42[67:0]; // @[LoopConv.scala:285:84] wire [67:0] _dram_offset_T_44 = _dram_offset_T_43; // @[LoopConv.scala:285:84] wire [67:0] _dram_offset_T_45 = _dram_offset_T_44; // @[LoopConv.scala:285:{84,101}] wire [67:0] dram_offset = req_trans_input_3120 ? _dram_offset_T_22 : _dram_offset_T_45; // @[LoopConv.scala:258:16, :284:{24,141}, :285:101] wire [67:0] _dram_addr_T = {36'h0, dram_offset[31:0]}; // @[LoopConv.scala:284:24, :1556:17] wire [68:0] _dram_addr_T_1 = {29'h0, req_dram_addr} + {1'h0, _dram_addr_T}; // @[LoopConv.scala:258:16, :286:52, :1556:17] wire [67:0] _dram_addr_T_2 = _dram_addr_T_1[67:0]; // @[LoopConv.scala:286:52] wire [67:0] dram_addr = is_zeros ? 68'h0 : _dram_addr_T_2; // @[LoopConv.scala:279:74, :286:{22,52}] wire [14:0] _GEN_15 = {1'h0, req_addr_start}; // @[LoopConv.scala:258:16, :289:20] wire [14:0] _spad_addr_T; // @[LoopConv.scala:289:20] assign _spad_addr_T = _GEN_15; // @[LoopConv.scala:289:20] wire [14:0] _spad_addr_T_27; // @[LoopConv.scala:290:20] assign _spad_addr_T_27 = _GEN_15; // @[LoopConv.scala:289:20, :290:20] wire [11:0] _spad_addr_T_1 = b[15:4]; // @[LoopConv.scala:271:14, :289:31] wire [16:0] _GEN_16 = {1'h0, req_derived_params_input_spad_stride}; // @[LoopConv.scala:258:16, :289:54] wire [16:0] _spad_addr_T_2; // @[LoopConv.scala:289:54] assign _spad_addr_T_2 = _GEN_16; // @[LoopConv.scala:289:54] wire [16:0] _spad_addr_T_29; // @[LoopConv.scala:290:56] assign _spad_addr_T_29 = _GEN_16; // @[LoopConv.scala:289:54, :290:56] wire [28:0] _spad_addr_T_3 = {{17{_spad_addr_T_1[11]}}, _spad_addr_T_1} * {{12{_spad_addr_T_2[16]}}, _spad_addr_T_2}; // @[LoopConv.scala:289:{31,54}] wire [27:0] _spad_addr_T_4 = _spad_addr_T_3[27:0]; // @[LoopConv.scala:289:54] wire [27:0] _spad_addr_T_5 = _spad_addr_T_4; // @[LoopConv.scala:289:54] wire [28:0] _spad_addr_T_6 = {{14{_spad_addr_T[14]}}, _spad_addr_T} + {_spad_addr_T_5[27], _spad_addr_T_5}; // @[LoopConv.scala:289:{20,25,54}] wire [15:0] _GEN_17 = {15'h0, req_downsample}; // @[LoopConv.scala:258:16, :289:90] wire [15:0] _GEN_18 = req_derived_params_irows >> _GEN_17; // @[LoopConv.scala:258:16, :289:90] wire [15:0] _spad_addr_T_7; // @[LoopConv.scala:289:90] assign _spad_addr_T_7 = _GEN_18; // @[LoopConv.scala:289:90] wire [15:0] _spad_addr_T_34; // @[LoopConv.scala:290:90] assign _spad_addr_T_34 = _GEN_18; // @[LoopConv.scala:289:90, :290:90] wire [16:0] _spad_addr_T_8 = {1'h0, _spad_addr_T_7}; // @[LoopConv.scala:289:{81,90}] wire [32:0] _spad_addr_T_9 = _GEN_9 * {{16{_spad_addr_T_8[16]}}, _spad_addr_T_8}; // @[LoopConv.scala:284:54, :289:81] wire [31:0] _spad_addr_T_10 = _spad_addr_T_9[31:0]; // @[LoopConv.scala:289:81] wire [31:0] _spad_addr_T_11 = _spad_addr_T_10; // @[LoopConv.scala:289:81] wire [15:0] _GEN_19 = req_derived_params_icols >> _GEN_17; // @[LoopConv.scala:258:16, :289:{90,118}] wire [15:0] _spad_addr_T_12; // @[LoopConv.scala:289:118] assign _spad_addr_T_12 = _GEN_19; // @[LoopConv.scala:289:118] wire [15:0] _spad_addr_T_19; // @[LoopConv.scala:289:181] assign _spad_addr_T_19 = _GEN_19; // @[LoopConv.scala:289:{118,181}] wire [15:0] _spad_addr_T_39; // @[LoopConv.scala:290:118] assign _spad_addr_T_39 = _GEN_19; // @[LoopConv.scala:289:118, :290:118] wire [15:0] _spad_addr_T_46; // @[LoopConv.scala:290:181] assign _spad_addr_T_46 = _GEN_19; // @[LoopConv.scala:289:118, :290:181] wire [16:0] _spad_addr_T_13 = {1'h0, _spad_addr_T_12}; // @[LoopConv.scala:289:{109,118}] wire [48:0] _spad_addr_T_14 = {{17{_spad_addr_T_11[31]}}, _spad_addr_T_11} * {{32{_spad_addr_T_13[16]}}, _spad_addr_T_13}; // @[LoopConv.scala:289:{81,109}] wire [47:0] _spad_addr_T_15 = _spad_addr_T_14[47:0]; // @[LoopConv.scala:289:109] wire [47:0] _spad_addr_T_16 = _spad_addr_T_15; // @[LoopConv.scala:289:109] wire [48:0] _spad_addr_T_17 = {{20{_spad_addr_T_6[28]}}, _spad_addr_T_6} + {_spad_addr_T_16[47], _spad_addr_T_16}; // @[LoopConv.scala:289:{25,74,109}] wire [18:0] _GEN_20 = {18'h0, req_downsample}; // @[LoopConv.scala:258:16, :289:153] wire [18:0] _GEN_21 = $signed($signed(irow_padded) >>> _GEN_20); // @[LoopConv.scala:277:26, :289:153] wire [18:0] _spad_addr_T_18; // @[LoopConv.scala:289:153] assign _spad_addr_T_18 = _GEN_21; // @[LoopConv.scala:289:153] wire [18:0] _spad_addr_T_45; // @[LoopConv.scala:290:153] assign _spad_addr_T_45 = _GEN_21; // @[LoopConv.scala:289:153, :290:153] wire [16:0] _spad_addr_T_20 = {1'h0, _spad_addr_T_19}; // @[LoopConv.scala:289:{172,181}] wire [35:0] _spad_addr_T_21 = {{17{_spad_addr_T_18[18]}}, _spad_addr_T_18} * {{19{_spad_addr_T_20[16]}}, _spad_addr_T_20}; // @[LoopConv.scala:289:{153,172}] wire [34:0] _spad_addr_T_22 = _spad_addr_T_21[34:0]; // @[LoopConv.scala:289:172] wire [34:0] _spad_addr_T_23 = _spad_addr_T_22; // @[LoopConv.scala:289:172] wire [49:0] _spad_addr_T_24 = {_spad_addr_T_17[48], _spad_addr_T_17} + {{15{_spad_addr_T_23[34]}}, _spad_addr_T_23}; // @[LoopConv.scala:289:{74,137,172}] wire [18:0] _GEN_22 = $signed($signed(icol_padded) >>> _GEN_20); // @[LoopConv.scala:278:26, :289:{153,216}] wire [18:0] _spad_addr_T_25; // @[LoopConv.scala:289:216] assign _spad_addr_T_25 = _GEN_22; // @[LoopConv.scala:289:216] wire [18:0] _spad_addr_T_52; // @[LoopConv.scala:290:216] assign _spad_addr_T_52 = _GEN_22; // @[LoopConv.scala:289:216, :290:216] wire [50:0] _spad_addr_T_26 = {_spad_addr_T_24[49], _spad_addr_T_24} + {{32{_spad_addr_T_25[18]}}, _spad_addr_T_25}; // @[LoopConv.scala:289:{137,200,216}] wire [11:0] _spad_addr_T_28 = ich[15:4]; // @[LoopConv.scala:274:16, :290:33] wire [28:0] _spad_addr_T_30 = {{17{_spad_addr_T_28[11]}}, _spad_addr_T_28} * {{12{_spad_addr_T_29[16]}}, _spad_addr_T_29}; // @[LoopConv.scala:290:{33,56}] wire [27:0] _spad_addr_T_31 = _spad_addr_T_30[27:0]; // @[LoopConv.scala:290:56] wire [27:0] _spad_addr_T_32 = _spad_addr_T_31; // @[LoopConv.scala:290:56] wire [28:0] _spad_addr_T_33 = {{14{_spad_addr_T_27[14]}}, _spad_addr_T_27} + {_spad_addr_T_32[27], _spad_addr_T_32}; // @[LoopConv.scala:290:{20,25,56}] wire [16:0] _spad_addr_T_35 = {1'h0, _spad_addr_T_34}; // @[LoopConv.scala:290:{81,90}] wire [32:0] _spad_addr_T_36 = _GEN_14 * {{16{_spad_addr_T_35[16]}}, _spad_addr_T_35}; // @[LoopConv.scala:285:10, :290:81] wire [31:0] _spad_addr_T_37 = _spad_addr_T_36[31:0]; // @[LoopConv.scala:290:81] wire [31:0] _spad_addr_T_38 = _spad_addr_T_37; // @[LoopConv.scala:290:81] wire [16:0] _spad_addr_T_40 = {1'h0, _spad_addr_T_39}; // @[LoopConv.scala:290:{109,118}] wire [48:0] _spad_addr_T_41 = {{17{_spad_addr_T_38[31]}}, _spad_addr_T_38} * {{32{_spad_addr_T_40[16]}}, _spad_addr_T_40}; // @[LoopConv.scala:290:{81,109}] wire [47:0] _spad_addr_T_42 = _spad_addr_T_41[47:0]; // @[LoopConv.scala:290:109] wire [47:0] _spad_addr_T_43 = _spad_addr_T_42; // @[LoopConv.scala:290:109] wire [48:0] _spad_addr_T_44 = {{20{_spad_addr_T_33[28]}}, _spad_addr_T_33} + {_spad_addr_T_43[47], _spad_addr_T_43}; // @[LoopConv.scala:290:{25,76,109}] wire [16:0] _spad_addr_T_47 = {1'h0, _spad_addr_T_46}; // @[LoopConv.scala:290:{172,181}] wire [35:0] _spad_addr_T_48 = {{17{_spad_addr_T_45[18]}}, _spad_addr_T_45} * {{19{_spad_addr_T_47[16]}}, _spad_addr_T_47}; // @[LoopConv.scala:290:{153,172}] wire [34:0] _spad_addr_T_49 = _spad_addr_T_48[34:0]; // @[LoopConv.scala:290:172] wire [34:0] _spad_addr_T_50 = _spad_addr_T_49; // @[LoopConv.scala:290:172] wire [49:0] _spad_addr_T_51 = {_spad_addr_T_44[48], _spad_addr_T_44} + {{15{_spad_addr_T_50[34]}}, _spad_addr_T_50}; // @[LoopConv.scala:290:{76,137,172}] wire [50:0] _spad_addr_T_53 = {_spad_addr_T_51[49], _spad_addr_T_51} + {{32{_spad_addr_T_52[18]}}, _spad_addr_T_52}; // @[LoopConv.scala:290:{137,200,216}] wire [50:0] spad_addr = req_trans_input_3120 ? _spad_addr_T_26 : _spad_addr_T_53; // @[LoopConv.scala:258:16, :287:22, :289:200, :290:200] wire [5:0] _block_size_downsampled_T = 6'h10 << req_downsample; // @[LoopConv.scala:258:16, :293:46] wire [6:0] block_size_downsampled = {1'h0, _block_size_downsampled_T}; // @[LoopConv.scala:293:{46,72}] wire [17:0] _GEN_23 = {{2{icol[15]}}, icol}; // @[LoopConv.scala:273:17, :278:26, :296:29] wire [17:0] _I_T_1 = {_I_T[16], _I_T} - _GEN_23; // @[LoopConv.scala:296:{24,29}] wire [17:0] _GEN_24 = {{11{block_size_downsampled[6]}}, block_size_downsampled}; // @[LoopConv.scala:293:72, :296:37] wire _I_T_2 = $signed(_I_T_1) > $signed(_GEN_24); // @[LoopConv.scala:296:{29,37}] wire [17:0] _I_T_4 = {_I_T_3[16], _I_T_3} - _GEN_23; // @[LoopConv.scala:296:{29,102,107}] wire [17:0] _I_T_5 = _I_T_2 ? _GEN_24 : _I_T_4; // @[LoopConv.scala:296:{8,37,107}] wire [16:0] _GEN_25 = 17'h0 - _GEN_6; // @[LoopConv.scala:279:{23,82}, :298:31] wire [16:0] _I_T_7; // @[LoopConv.scala:298:31] assign _I_T_7 = _GEN_25; // @[LoopConv.scala:279:23, :298:31] wire [16:0] _I_T_9; // @[LoopConv.scala:298:72] assign _I_T_9 = _GEN_25; // @[LoopConv.scala:279:23, :298:{31,72}] wire _I_T_8 = $signed(_I_T_7) > 17'sh10; // @[LoopConv.scala:298:{31,39}] wire [16:0] _I_T_10 = _I_T_8 ? 17'h10 : _I_T_9; // @[LoopConv.scala:298:{26,39,72}] wire _I_T_12 = $signed(_GEN_6) >= $signed(_I_T_11); // @[LoopConv.scala:279:82, :299:{13,31}] wire [16:0] _GEN_26 = {1'h0, req_inner_bounds_rpad} + _GEN; // @[LoopConv.scala:258:16, :263:37] wire [16:0] _I_T_14; // @[LoopConv.scala:263:37] assign _I_T_14 = _GEN_26; // @[LoopConv.scala:263:37] wire [16:0] _I_T_21; // @[LoopConv.scala:263:37] assign _I_T_21 = _GEN_26; // @[LoopConv.scala:263:37] wire [16:0] _next_icol_T_1; // @[LoopConv.scala:263:37] assign _next_icol_T_1 = _GEN_26; // @[LoopConv.scala:263:37] wire [16:0] _I_T_15 = _I_T_14 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _I_T_16 = {1'h0, _I_T_15}; // @[LoopConv.scala:263:59, :299:83] wire [18:0] _I_T_17 = {{2{_I_T_13[16]}}, _I_T_13} + {_I_T_16[17], _I_T_16}; // @[LoopConv.scala:299:{59,64,83}] wire [19:0] _GEN_27 = {{4{icol[15]}}, icol}; // @[LoopConv.scala:273:17, :278:26, :299:88] wire [19:0] _I_T_18 = {_I_T_17[18], _I_T_17} - _GEN_27; // @[LoopConv.scala:299:{64,88}] wire _I_T_19 = $signed(_I_T_18) > 20'sh10; // @[LoopConv.scala:299:{88,96}] wire [16:0] _I_T_22 = _I_T_21 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _I_T_23 = {1'h0, _I_T_22}; // @[LoopConv.scala:263:59, :299:165] wire [18:0] _I_T_24 = {{2{_I_T_20[16]}}, _I_T_20} + {_I_T_23[17], _I_T_23}; // @[LoopConv.scala:299:{141,146,165}] wire [19:0] _I_T_25 = {_I_T_24[18], _I_T_24} - _GEN_27; // @[LoopConv.scala:299:{88,146,170}] wire [19:0] _I_T_26 = _I_T_19 ? 20'h10 : _I_T_25; // @[LoopConv.scala:299:{43,96,170}] wire [19:0] _I_T_27 = _I_T_12 ? _I_T_26 : {{2{_I_T_5[17]}}, _I_T_5}; // @[Mux.scala:126:16] wire [19:0] I = _I_T_6 ? {{3{_I_T_10[16]}}, _I_T_10} : _I_T_27; // @[Mux.scala:126:16] wire [19:0] _next_icol_T = I; // @[Mux.scala:126:16] wire [17:0] _GEN_28 = {{2{b[15]}}, b}; // @[LoopConv.scala:271:14, :284:118, :303:22] wire [17:0] _K_T_1 = {_K_T[16], _K_T} - _GEN_28; // @[LoopConv.scala:303:{17,22}] wire [17:0] _GEN_29 = {max_chs_per_mvin[16], max_chs_per_mvin}; // @[LoopConv.scala:268:29, :303:27] wire _K_T_2 = $signed(_K_T_1) > $signed(_GEN_29); // @[LoopConv.scala:303:{22,27}] wire [17:0] _K_T_4 = {_K_T_3[16], _K_T_3} - _GEN_28; // @[LoopConv.scala:303:{22,73,78}] wire [17:0] _K_T_5 = _K_T_2 ? _GEN_29 : _K_T_4; // @[LoopConv.scala:303:{8,27,78}] wire [16:0] _GEN_30 = {1'h0, req_derived_params_ichs}; // @[LoopConv.scala:258:16, :304:14] wire [16:0] _K_T_6; // @[LoopConv.scala:304:14] assign _K_T_6 = _GEN_30; // @[LoopConv.scala:304:14] wire [16:0] _K_T_9; // @[LoopConv.scala:304:69] assign _K_T_9 = _GEN_30; // @[LoopConv.scala:304:{14,69}] wire [16:0] _next_ich_T; // @[LoopConv.scala:373:50] assign _next_ich_T = _GEN_30; // @[LoopConv.scala:304:14, :373:50] wire [17:0] _GEN_31 = {{2{ich[15]}}, ich}; // @[LoopConv.scala:274:16, :284:54, :304:19] wire [17:0] _K_T_7 = {_K_T_6[16], _K_T_6} - _GEN_31; // @[LoopConv.scala:304:{14,19}] wire _K_T_8 = $signed(_K_T_7) > $signed(_GEN_29); // @[LoopConv.scala:303:27, :304:{19,26}] wire [17:0] _K_T_10 = {_K_T_9[16], _K_T_9} - _GEN_31; // @[LoopConv.scala:304:{19,69,74}] wire [17:0] _K_T_11 = _K_T_8 ? _GEN_29 : _K_T_10; // @[LoopConv.scala:303:27, :304:{8,26,74}] wire [17:0] K = req_trans_input_3120 ? _K_T_5 : _K_T_11; // @[LoopConv.scala:258:16, :302:14, :303:8, :304:8] wire [63:0] _config_cmd_rs1_T; // @[LoopConv.scala:327:36] wire [63:0] config_cmd_rs1; // @[LoopConv.scala:315:24] wire [63:0] config_cmd_rs2; // @[LoopConv.scala:315:24] wire [13:0] config_cmd_rs1_stride; // @[LoopConv.scala:319:28] wire [4:0] config_cmd_rs1_pixel_repeats; // @[LoopConv.scala:319:28] assign config_cmd_rs1_stride = req_derived_params_input_spad_stride[13:0]; // @[LoopConv.scala:258:16, :319:28, :322:25] assign config_cmd_rs1_pixel_repeats = req_max_pixels_per_row[4:0]; // @[LoopConv.scala:258:16, :319:28, :323:32] wire [7:0] config_cmd_rs1_lo_hi_hi = {config_cmd_rs1_pixel_repeats, 3'h0}; // @[LoopConv.scala:319:28, :327:36] wire [9:0] config_cmd_rs1_lo_hi = {config_cmd_rs1_lo_hi_hi, 2'h0}; // @[LoopConv.scala:256:22, :327:36] wire [12:0] config_cmd_rs1_lo = {config_cmd_rs1_lo_hi, 3'h1}; // @[LoopConv.scala:327:36] wire [16:0] config_cmd_rs1_hi_lo = {config_cmd_rs1_stride, 3'h0}; // @[LoopConv.scala:319:28, :327:36] wire [50:0] config_cmd_rs1_hi = {34'hFE000000, config_cmd_rs1_hi_lo}; // @[LoopConv.scala:327:36] assign _config_cmd_rs1_T = {config_cmd_rs1_hi, config_cmd_rs1_lo}; // @[LoopConv.scala:327:36] assign config_cmd_rs1 = _config_cmd_rs1_T; // @[LoopConv.scala:315:24, :327:36] wire [17:0] _config_cmd_rs2_T = {1'h0, dram_stride} << req_downsample; // @[LoopConv.scala:258:16, :281:24, :329:33] assign config_cmd_rs2 = {46'h0, _config_cmd_rs2_T}; // @[LoopConv.scala:315:24, :329:{18,33}] wire _io_req_ready_T = ~(\|state); // @[LoopConv.scala:256:22, :338:25] wire _io_req_ready_T_1 = ~_command_p_io_busy; // @[LoopConv.scala:313:25, :338:37] assign _io_req_ready_T_2 = _io_req_ready_T & _io_req_ready_T_1; // @[LoopConv.scala:338:{25,34,37}] assign io_req_ready_0 = _io_req_ready_T_2; // @[LoopConv.scala:235:7, :338:34] wire _io_idle_T = ~(\|state); // @[LoopConv.scala:256:22, :338:25, :339:20] wire _io_idle_T_1 = ~_command_p_io_busy; // @[LoopConv.scala:313:25, :338:37, :339:32] assign _io_idle_T_2 = _io_idle_T & _io_idle_T_1; // @[LoopConv.scala:339:{20,29,32}] assign io_idle_0 = _io_idle_T_2; // @[LoopConv.scala:235:7, :339:29] wire _command_p_io_in_valid_T = \|state; // @[LoopConv.scala:256:22, :338:25, :342:34] wire _command_p_io_in_valid_T_1 = ~io_wait_for_prev_loop_0; // @[LoopConv.scala:235:7, :342:46] wire _command_p_io_in_valid_T_2 = _command_p_io_in_valid_T & _command_p_io_in_valid_T_1; // @[LoopConv.scala:342:{34,43,46}] wire _command_p_io_in_valid_T_3 = \|req_dram_addr; // @[LoopConv.scala:258:16, :342:87] wire _command_p_io_in_valid_T_4 = _command_p_io_in_valid_T_2 & _command_p_io_in_valid_T_3; // @[LoopConv.scala:342:{43,69,87}] wire _command_p_io_in_bits_cmd_T = state == 2'h1; // @[LoopConv.scala:256:22, :343:41] wire [6:0] _command_p_io_in_bits_cmd_T_1_inst_funct = {5'h0, ~_command_p_io_in_bits_cmd_T, 1'h0}; // @[LoopConv.scala:343:{34,41}] wire [63:0] _command_p_io_in_bits_cmd_T_1_rs1 = _command_p_io_in_bits_cmd_T ? config_cmd_rs1 : 64'h0; // @[LoopConv.scala:315:24, :343:{34,41}] wire [63:0] _command_p_io_in_bits_cmd_T_1_rs2 = _command_p_io_in_bits_cmd_T ? config_cmd_rs2 : 64'h0; // @[LoopConv.scala:315:24, :343:{34,41}] wire _command_p_io_out_ready_T = ~io_rob_overloaded_0; // @[LoopConv.scala:235:7, :349:45] wire _command_p_io_out_ready_T_1 = io_cmd_ready_0 & _command_p_io_out_ready_T; // @[LoopConv.scala:235:7, :349:{42,45}] wire _io_cmd_valid_T = ~io_rob_overloaded_0; // @[LoopConv.scala:235:7, :349:45, :350:45] assign _io_cmd_valid_T_1 = _command_p_io_out_valid & _io_cmd_valid_T; // @[LoopConv.scala:313:25, :350:{42,45}] assign io_cmd_valid_0 = _io_cmd_valid_T_1; // @[LoopConv.scala:235:7, :350:42] wire _T = _command_p_io_out_bits_cmd_inst_funct == 7'h2; // @[LoopConv.scala:313:25, :352:46] assign io_cmd_bits_rs1_0 = _T ? _command_p_io_out_bits_dram_addr[63:0] : _command_p_io_out_bits_cmd_rs1; // @[LoopConv.scala:235:7, :313:25, :351:15, :352:{46,60}, :354:21] wire [6:0] io_cmd_bits_rs2_lo_hi_1 = mvin_cmd_rs2_num_cols; // @[LoopConv.scala:355:28, :360:37] wire [2:0] mvin_cmd_rs2_local_addr_result_norm_cmd; // @[LocalAddr.scala:116:26] wire [2:0] _io_cmd_bits_rs2_T = mvin_cmd_rs2_local_addr_norm_cmd; // @[LoopConv.scala:355:28, :360:37] wire mvin_cmd_rs2_local_addr_result_garbage_bit; // @[LocalAddr.scala:116:26] wire [13:0] mvin_cmd_rs2_local_addr_result_data; // @[LocalAddr.scala:116:26] wire mvin_cmd_rs2_local_addr_garbage_bit; // @[LoopConv.scala:355:28] wire [13:0] mvin_cmd_rs2_local_addr_data; // @[LoopConv.scala:355:28] wire [4:0] mvin_cmd_rs2_num_rows; // @[LoopConv.scala:355:28] wire [19:0] _mvin_cmd_rs2_num_rows_T = $signed($signed(_command_p_io_out_bits_I) >>> req_downsample); // @[LoopConv.scala:258:16, :313:25, :357:35] wire [19:0] _mvin_cmd_rs2_num_rows_T_1 = _mvin_cmd_rs2_num_rows_T; // @[LoopConv.scala:357:{35,54}] assign mvin_cmd_rs2_num_rows = _mvin_cmd_rs2_num_rows_T_1[4:0]; // @[LoopConv.scala:355:28, :357:{27,54}] wire [17:0] _mvin_cmd_rs2_num_cols_T; // @[LoopConv.scala:358:34] assign mvin_cmd_rs2_num_cols = _mvin_cmd_rs2_num_cols_T[6:0]; // @[LoopConv.scala:355:28, :358:{27,34}] wire _mvin_cmd_rs2_local_addr_result_result_T_7; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_is_acc_addr = _mvin_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:{26,37}] wire _mvin_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_accumulate = _mvin_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:{26,37}] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_read_full_acc_row = _mvin_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:{26,37}] wire [10:0] _mvin_cmd_rs2_local_addr_result_result_T_3; // @[LocalAddr.scala:108:37] wire [2:0] mvin_cmd_rs2_local_addr_result_result_norm_cmd = _mvin_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:{26,37}] wire _mvin_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [13:0] _mvin_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_garbage_bit = _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:{26,37}] wire [13:0] mvin_cmd_rs2_local_addr_result_result_data = _mvin_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:{26,37}] wire [50:0] _mvin_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] wire [31:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_1 = _mvin_cmd_rs2_local_addr_result_result_T[31:0]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_1 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[13:0]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_data = _mvin_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_2 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[14]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage_bit = _mvin_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_3 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[25:15]; // @[LocalAddr.scala:108:37] wire [10:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage = _mvin_cmd_rs2_local_addr_result_result_T_3; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_T_4 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[28:26]; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_2 = _mvin_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_3 = _mvin_cmd_rs2_local_addr_result_result_WIRE_2; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_norm_cmd = _mvin_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_5 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[29]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row = _mvin_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_6 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[30]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_accumulate = _mvin_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_7 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[31]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr = _mvin_cmd_rs2_local_addr_result_result_T_7; // @[LocalAddr.scala:108:37] assign mvin_cmd_rs2_local_addr_result_norm_cmd = mvin_cmd_rs2_local_addr_result_result_norm_cmd; // @[LocalAddr.scala:108:26, :116:26] assign mvin_cmd_rs2_local_addr_result_garbage_bit = mvin_cmd_rs2_local_addr_result_result_garbage_bit; // @[LocalAddr.scala:108:26, :116:26] assign mvin_cmd_rs2_local_addr_result_data = mvin_cmd_rs2_local_addr_result_result_data; // @[LocalAddr.scala:108:26, :116:26] assign mvin_cmd_rs2_local_addr_norm_cmd = mvin_cmd_rs2_local_addr_result_norm_cmd; // @[LoopConv.scala:355:28] assign mvin_cmd_rs2_local_addr_garbage_bit = mvin_cmd_rs2_local_addr_result_garbage_bit; // @[LoopConv.scala:355:28] assign mvin_cmd_rs2_local_addr_data = mvin_cmd_rs2_local_addr_result_data; // @[LoopConv.scala:355:28] wire [11:0] io_cmd_bits_rs2_lo_hi = {11'h0, mvin_cmd_rs2_local_addr_garbage_bit}; // @[LoopConv.scala:355:28, :360:37] wire [25:0] io_cmd_bits_rs2_lo = {io_cmd_bits_rs2_lo_hi, mvin_cmd_rs2_local_addr_data}; // @[LoopConv.scala:355:28, :360:37] wire [3:0] io_cmd_bits_rs2_hi_lo = {1'h0, _io_cmd_bits_rs2_T}; // @[LoopConv.scala:360:37] wire [5:0] io_cmd_bits_rs2_hi = {2'h0, io_cmd_bits_rs2_hi_lo}; // @[LoopConv.scala:256:22, :360:37] wire [31:0] _io_cmd_bits_rs2_T_1 = {io_cmd_bits_rs2_hi, io_cmd_bits_rs2_lo}; // @[LoopConv.scala:360:37] wire [38:0] io_cmd_bits_rs2_lo_1 = {io_cmd_bits_rs2_lo_hi_1, _io_cmd_bits_rs2_T_1}; // @[LoopConv.scala:360:37] wire [15:0] io_cmd_bits_rs2_hi_hi_1 = {11'h0, mvin_cmd_rs2_num_rows}; // @[LoopConv.scala:355:28, :360:37] wire [24:0] io_cmd_bits_rs2_hi_1 = {io_cmd_bits_rs2_hi_hi_1, 9'h0}; // @[LoopConv.scala:360:37] wire [63:0] _io_cmd_bits_rs2_T_2 = {io_cmd_bits_rs2_hi_1, io_cmd_bits_rs2_lo_1}; // @[LoopConv.scala:360:37] assign io_cmd_bits_rs2_0 = _T ? _io_cmd_bits_rs2_T_2 : _command_p_io_out_bits_cmd_rs2; // @[LoopConv.scala:235:7, :313:25, :351:15, :352:{46,60}, :360:{21,37}] wire [16:0] b_it = req_trans_input_3120 ? _b_it_T : 17'h1; // @[LoopConv.scala:258:16, :281:58, :370:{21,61}] wire [16:0] ich_it = req_trans_input_3120 ? 17'h1 : _ich_it_T; // @[LoopConv.scala:258:16, :281:58, :371:{23,68}] wire [17:0] _next_ich_max_T = {_next_ich_T[16], _next_ich_T} - 18'h1; // @[Util.scala:48:28] wire [16:0] _next_ich_max_T_1 = _next_ich_max_T[16:0]; // @[Util.scala:48:28] wire [16:0] next_ich_max = _next_ich_max_T_1; // @[Util.scala:48:28] wire [17:0] _GEN_32 = {1'h0, ich_it}; // @[Util.scala:50:19] wire [17:0] _next_ich_T_1; // @[Util.scala:50:19] assign _next_ich_T_1 = _GEN_32; // @[Util.scala:50:19] wire [17:0] _next_ich_T_6; // @[Util.scala:52:16] assign _next_ich_T_6 = _GEN_32; // @[Util.scala:50:19, :52:16] wire [18:0] _GEN_33 = {{3{ich[15]}}, ich}; // @[Util.scala:50:15] wire [18:0] _next_ich_T_2 = _GEN_33 + {_next_ich_T_1[17], _next_ich_T_1}; // @[Util.scala:50:{15,19}] wire [17:0] _next_ich_T_3 = _next_ich_T_2[17:0]; // @[Util.scala:50:15] wire [17:0] _next_ich_T_4 = _next_ich_T_3; // @[Util.scala:50:15] wire [18:0] _next_ich_T_7 = _GEN_33 + {_next_ich_T_6[17], _next_ich_T_6}; // @[Util.scala:50:15, :52:{11,16}] wire _next_ich_T_8 = $signed(_next_ich_T_7) > $signed({{2{next_ich_max[16]}}, next_ich_max}); // @[Util.scala:48:28, :52:{11,22}] wire [17:0] _next_ich_T_9 = _next_ich_T_8 ? 18'h0 : _next_ich_T_4; // @[Mux.scala:126:16] wire [17:0] next_ich = _next_ich_T_9; // @[Mux.scala:126:16] wire [16:0] _next_icol_T_2 = _next_icol_T_1 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _next_icol_T_3 = {2'h0, req_derived_params_icols_unpadded} + {1'h0, _next_icol_T_2}; // @[LoopConv.scala:256:22, :258:16, :263:59, :374:65] wire [18:0] _next_icol_T_4 = {1'h0, _next_icol_T_3}; // @[LoopConv.scala:374:{65,85}] wire [16:0] _next_icol_T_6 = _next_icol_T_5 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _next_icol_T_7 = {1'h0, _next_icol_T_6}; // @[LoopConv.scala:263:59, :374:112] wire [18:0] _next_icol_T_8 = 19'h0 - {_next_icol_T_7[17], _next_icol_T_7}; // @[LoopConv.scala:279:23, :357:35, :374:{94,112}] wire _GEN_34 = next_ich == 18'h0; // @[Mux.scala:126:16] wire _next_icol_T_9; // @[LoopConv.scala:375:18] assign _next_icol_T_9 = _GEN_34; // @[LoopConv.scala:375:18] wire _next_irow_T_14; // @[LoopConv.scala:377:61] assign _next_irow_T_14 = _GEN_34; // @[LoopConv.scala:375:18, :377:61] wire _next_b_T_12; // @[LoopConv.scala:379:104] assign _next_b_T_12 = _GEN_34; // @[LoopConv.scala:375:18, :379:104] wire _state_T_13; // @[LoopConv.scala:386:133] assign _state_T_13 = _GEN_34; // @[LoopConv.scala:375:18, :386:133] wire [19:0] _next_icol_max_T = {_next_icol_T_4[18], _next_icol_T_4} - 20'h1; // @[Util.scala:48:28] wire [18:0] _next_icol_max_T_1 = _next_icol_max_T[18:0]; // @[Util.scala:48:28] wire [18:0] next_icol_max = _next_icol_max_T_1; // @[Util.scala:48:28] wire [20:0] _GEN_35 = {1'h0, _next_icol_T}; // @[Util.scala:50:19] wire [20:0] _next_icol_T_10; // @[Util.scala:50:19] assign _next_icol_T_10 = _GEN_35; // @[Util.scala:50:19] wire [20:0] _next_icol_T_15; // @[Util.scala:52:16] assign _next_icol_T_15 = _GEN_35; // @[Util.scala:50:19, :52:16] wire [21:0] _GEN_36 = {{6{icol[15]}}, icol}; // @[Util.scala:50:15] wire [21:0] _next_icol_T_11 = _GEN_36 + {_next_icol_T_10[20], _next_icol_T_10}; // @[Util.scala:50:{15,19}] wire [20:0] _next_icol_T_12 = _next_icol_T_11[20:0]; // @[Util.scala:50:15] wire [20:0] _next_icol_T_13 = _next_icol_T_12; // @[Util.scala:50:15] wire _next_icol_T_14 = ~_next_icol_T_9; // @[Util.scala:51:8] wire [21:0] _next_icol_T_16 = _GEN_36 + {_next_icol_T_15[20], _next_icol_T_15}; // @[Util.scala:50:15, :52:{11,16}] wire _next_icol_T_17 = $signed(_next_icol_T_16) > $signed({{3{next_icol_max[18]}}, next_icol_max}); // @[Util.scala:48:28, :52:{11,22}] wire [20:0] _next_icol_T_18 = _next_icol_T_17 ? {{2{_next_icol_T_8[18]}}, _next_icol_T_8} : _next_icol_T_13; // @[Mux.scala:126:16] wire [20:0] next_icol = _next_icol_T_14 ? {{5{icol[15]}}, icol} : _next_icol_T_18; // @[Mux.scala:126:16] wire [1:0] _next_irow_T = 2'h1 << req_downsample; // @[LoopConv.scala:258:16, :343:41, :376:43] wire [16:0] _next_irow_T_1 = {1'h0, req_inner_bounds_dpad} + _GEN; // @[LoopConv.scala:258:16, :263:37] wire [16:0] _next_irow_T_2 = _next_irow_T_1 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _next_irow_T_3 = {2'h0, req_derived_params_irows_unpadded} + {1'h0, _next_irow_T_2}; // @[LoopConv.scala:256:22, :258:16, :263:59, :376:78] wire [18:0] _next_irow_T_4 = {1'h0, _next_irow_T_3}; // @[LoopConv.scala:376:{78,98}] wire [16:0] _next_irow_T_6 = _next_irow_T_5 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _next_irow_T_7 = {1'h0, _next_irow_T_6}; // @[LoopConv.scala:263:59, :376:125] wire [18:0] _next_irow_T_8 = 19'h0 - {_next_irow_T_7[17], _next_irow_T_7}; // @[LoopConv.scala:279:23, :357:35, :376:{107,125}] wire [16:0] _next_irow_T_10 = _next_irow_T_9 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _next_irow_T_11 = {1'h0, _next_irow_T_10}; // @[LoopConv.scala:263:59, :377:44] wire [18:0] _next_irow_T_12 = 19'h0 - {_next_irow_T_11[17], _next_irow_T_11}; // @[LoopConv.scala:279:23, :357:35, :377:{26,44}] wire _next_irow_T_13 = next_icol == {{2{_next_irow_T_12[18]}}, _next_irow_T_12}; // @[Mux.scala:126:16] wire _next_irow_T_15 = _next_irow_T_13 & _next_irow_T_14; // @[LoopConv.scala:377:{19,49,61}] wire [19:0] _next_irow_max_T = {_next_irow_T_4[18], _next_irow_T_4} - 20'h1; // @[Util.scala:48:28] wire [18:0] _next_irow_max_T_1 = _next_irow_max_T[18:0]; // @[Util.scala:48:28] wire [18:0] next_irow_max = _next_irow_max_T_1; // @[Util.scala:48:28] wire [2:0] _GEN_37 = {1'h0, _next_irow_T}; // @[Util.scala:50:19] wire [2:0] _next_irow_T_16; // @[Util.scala:50:19] assign _next_irow_T_16 = _GEN_37; // @[Util.scala:50:19] wire [2:0] _next_irow_T_21; // @[Util.scala:52:16] assign _next_irow_T_21 = _GEN_37; // @[Util.scala:50:19, :52:16] wire [16:0] _next_irow_T_17 = _GEN_3 + {{14{_next_irow_T_16[2]}}, _next_irow_T_16}; // @[Util.scala:50:{15,19}] wire [15:0] _next_irow_T_18 = _next_irow_T_17[15:0]; // @[Util.scala:50:15] wire [15:0] _next_irow_T_19 = _next_irow_T_18; // @[Util.scala:50:15] wire _next_irow_T_20 = ~_next_irow_T_15; // @[Util.scala:51:8] wire [16:0] _next_irow_T_22 = _GEN_3 + {{14{_next_irow_T_21[2]}}, _next_irow_T_21}; // @[Util.scala:52:{11,16}] wire _next_irow_T_23 = $signed({{2{_next_irow_T_22[16]}}, _next_irow_T_22}) > $signed(next_irow_max); // @[Util.scala:48:28, :52:{11,22}] wire [18:0] _next_irow_T_24 = _next_irow_T_23 ? _next_irow_T_8 : {{3{_next_irow_T_19[15]}}, _next_irow_T_19}; // @[Mux.scala:126:16] wire [18:0] next_irow = _next_irow_T_20 ? _GEN_1 : _next_irow_T_24; // @[Mux.scala:126:16] wire [16:0] _next_b_T_2 = _next_b_T_1 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _next_b_T_3 = {1'h0, _next_b_T_2}; // @[LoopConv.scala:263:59, :379:44] wire [18:0] _next_b_T_4 = 19'h0 - {_next_b_T_3[17], _next_b_T_3}; // @[LoopConv.scala:279:23, :357:35, :379:{26,44}] wire _next_b_T_5 = next_irow == _next_b_T_4; // @[Mux.scala:126:16] wire [16:0] _next_b_T_7 = _next_b_T_6 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _next_b_T_8 = {1'h0, _next_b_T_7}; // @[LoopConv.scala:263:59, :379:87] wire [18:0] _next_b_T_9 = 19'h0 - {_next_b_T_8[17], _next_b_T_8}; // @[LoopConv.scala:279:23, :357:35, :379:{69,87}] wire _next_b_T_10 = next_icol == {{2{_next_b_T_9[18]}}, _next_b_T_9}; // @[Mux.scala:126:16] wire _next_b_T_11 = _next_b_T_5 & _next_b_T_10; // @[LoopConv.scala:379:{19,49,62}] wire _next_b_T_13 = _next_b_T_11 & _next_b_T_12; // @[LoopConv.scala:379:{49,92,104}] wire [17:0] _next_b_max_T = {_next_b_T[16], _next_b_T} - 18'h1; // @[Util.scala:48:28] wire [16:0] _next_b_max_T_1 = _next_b_max_T[16:0]; // @[Util.scala:48:28] wire [16:0] next_b_max = _next_b_max_T_1; // @[Util.scala:48:28] wire [17:0] _GEN_38 = {1'h0, b_it}; // @[Util.scala:50:19] wire [17:0] _next_b_T_14; // @[Util.scala:50:19] assign _next_b_T_14 = _GEN_38; // @[Util.scala:50:19] wire [17:0] _next_b_T_19; // @[Util.scala:52:16] assign _next_b_T_19 = _GEN_38; // @[Util.scala:50:19, :52:16] wire [18:0] _GEN_39 = {{3{b[15]}}, b}; // @[Util.scala:50:15] wire [18:0] _next_b_T_15 = _GEN_39 + {_next_b_T_14[17], _next_b_T_14}; // @[Util.scala:50:{15,19}] wire [17:0] _next_b_T_16 = _next_b_T_15[17:0]; // @[Util.scala:50:15] wire [17:0] _next_b_T_17 = _next_b_T_16; // @[Util.scala:50:15] wire _next_b_T_18 = ~_next_b_T_13; // @[Util.scala:51:8] wire [18:0] _next_b_T_20 = _GEN_39 + {_next_b_T_19[17], _next_b_T_19}; // @[Util.scala:50:15, :52:{11,16}] wire _next_b_T_21 = $signed(_next_b_T_20) > $signed({{2{next_b_max[16]}}, next_b_max}); // @[Util.scala:48:28, :52:{11,22}] wire [17:0] _next_b_T_22 = _next_b_T_21 ? 18'h0 : _next_b_T_17; // @[Mux.scala:126:16] wire [17:0] next_b = _next_b_T_18 ? _GEN_28 : _next_b_T_22; // @[Mux.scala:126:16] wire _state_T = next_b == 18'h0; // @[Mux.scala:126:16] wire [16:0] _state_T_2 = _state_T_1 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _state_T_3 = {1'h0, _state_T_2}; // @[LoopConv.scala:263:59, :386:73] wire [18:0] _state_T_4 = 19'h0 - {_state_T_3[17], _state_T_3}; // @[LoopConv.scala:279:23, :357:35, :386:{55,73}] wire _state_T_5 = next_irow == _state_T_4; // @[Mux.scala:126:16] wire _state_T_6 = _state_T & _state_T_5; // @[LoopConv.scala:386:{27,35,48}] wire [16:0] _state_T_8 = _state_T_7 >> _GEN; // @[LoopConv.scala:263:{37,59}] wire [17:0] _state_T_9 = {1'h0, _state_T_8}; // @[LoopConv.scala:263:59, :386:116] wire [18:0] _state_T_10 = 19'h0 - {_state_T_9[17], _state_T_9}; // @[LoopConv.scala:279:23, :357:35, :386:{98,116}] wire _state_T_11 = next_icol == {{2{_state_T_10[18]}}, _state_T_10}; // @[Mux.scala:126:16] wire _state_T_12 = _state_T_6 & _state_T_11; // @[LoopConv.scala:386:{35,78,91}] wire _state_T_14 = _state_T_12 & _state_T_13; // @[LoopConv.scala:386:{78,121,133}] wire [1:0] _state_T_15 = {~_state_T_14, 1'h0}; // @[LoopConv.scala:386:{19,121}] wire [16:0] _GEN_40 = {16'h0, io_req_bits_input_dilated_0}; // @[LoopConv.scala:235:7, :279:23, :396:52] wire [16:0] _irow_T = {1'h0, io_req_bits_inner_bounds_upad_0} + _GEN_40; // @[LoopConv.scala:235:7, :396:52] wire [16:0] _irow_T_1 = _irow_T >> _GEN_40; // @[LoopConv.scala:396:{52,82}] wire [17:0] _irow_T_2 = {1'h0, _irow_T_1}; // @[LoopConv.scala:396:{82,112}] wire [18:0] _irow_T_3 = 19'h0 - {_irow_T_2[17], _irow_T_2}; // @[LoopConv.scala:279:23, :357:35, :396:{17,112}] wire [16:0] _icol_T = {1'h0, io_req_bits_inner_bounds_lpad_0} + _GEN_40; // @[LoopConv.scala:235:7, :396:52, :397:52] wire [16:0] _icol_T_1 = _icol_T >> _GEN_40; // @[LoopConv.scala:396:52, :397:{52,82}] wire [17:0] _icol_T_2 = {1'h0, _icol_T_1}; // @[LoopConv.scala:397:{82,112}] wire [18:0] _icol_T_3 = 19'h0 - {_icol_T_2[17], _icol_T_2}; // @[LoopConv.scala:279:23, :357:35, :397:{17,112}] wire _T_2 = _command_p_io_in_ready & _command_p_io_in_valid_T_4; // @[Decoupled.scala:51:35] wire _T_4 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[LoopConv.scala:235:7] if (reset) // @[LoopConv.scala:235:7] state <= 2'h0; // @[LoopConv.scala:256:22] else if (_T_4) // @[Decoupled.scala:51:35] state <= 2'h1; // @[LoopConv.scala:256:22, :343:41] else if (\|req_dram_addr) begin // @[LoopConv.scala:258:16, :342:87] if (_T_2) // @[Decoupled.scala:51:35] state <= _command_p_io_in_bits_cmd_T ? 2'h2 : _state_T_15; // @[LoopConv.scala:256:22, :343:41, :367:29, :368:13, :386:{13,19}] end else // @[LoopConv.scala:342:87] state <= 2'h0; // @[LoopConv.scala:256:22] if (_T_4) begin // @[Decoupled.scala:51:35] req_outer_bounds_batch_size <= io_req_bits_outer_bounds_batch_size_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_in_row_dim <= io_req_bits_outer_bounds_in_row_dim_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_in_col_dim <= io_req_bits_outer_bounds_in_col_dim_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_in_channels <= io_req_bits_outer_bounds_in_channels_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_out_channels <= io_req_bits_outer_bounds_out_channels_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_out_col_dim <= io_req_bits_outer_bounds_out_col_dim_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_out_row_dim <= io_req_bits_outer_bounds_out_row_dim_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_out_stride <= io_req_bits_outer_bounds_out_stride_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_in_stride <= io_req_bits_outer_bounds_in_stride_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_weight_stride <= io_req_bits_outer_bounds_weight_stride_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_pool_out_row_dim <= io_req_bits_outer_bounds_pool_out_row_dim_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_pool_out_col_dim <= io_req_bits_outer_bounds_pool_out_col_dim_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_stride <= io_req_bits_outer_bounds_stride_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_padding <= io_req_bits_outer_bounds_padding_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_kernel_dim <= io_req_bits_outer_bounds_kernel_dim_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_kernel_dilation <= io_req_bits_outer_bounds_kernel_dilation_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_pool_size <= io_req_bits_outer_bounds_pool_size_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_pool_stride <= io_req_bits_outer_bounds_pool_stride_0; // @[LoopConv.scala:235:7, :258:16] req_outer_bounds_pool_padding <= io_req_bits_outer_bounds_pool_padding_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_batches <= io_req_bits_inner_bounds_batches_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_porows <= io_req_bits_inner_bounds_porows_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_pocols <= io_req_bits_inner_bounds_pocols_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_pochs <= io_req_bits_inner_bounds_pochs_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_krows <= io_req_bits_inner_bounds_krows_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_kcols <= io_req_bits_inner_bounds_kcols_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_kchs <= io_req_bits_inner_bounds_kchs_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_lpad <= io_req_bits_inner_bounds_lpad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_rpad <= io_req_bits_inner_bounds_rpad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_upad <= io_req_bits_inner_bounds_upad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_dpad <= io_req_bits_inner_bounds_dpad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_plpad <= io_req_bits_inner_bounds_plpad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_prad <= io_req_bits_inner_bounds_prad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_pupad <= io_req_bits_inner_bounds_pupad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_pdpad <= io_req_bits_inner_bounds_pdpad_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_orows <= io_req_bits_inner_bounds_orows_0; // @[LoopConv.scala:235:7, :258:16] req_inner_bounds_ocols <= io_req_bits_inner_bounds_ocols_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_ochs <= io_req_bits_derived_params_ochs_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_irows <= io_req_bits_derived_params_irows_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_icols <= io_req_bits_derived_params_icols_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_irows_unpadded <= io_req_bits_derived_params_irows_unpadded_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_icols_unpadded <= io_req_bits_derived_params_icols_unpadded_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_ichs <= io_req_bits_derived_params_ichs_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_out_channels_per_bank <= io_req_bits_derived_params_out_channels_per_bank_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_in_channels_per_bank <= io_req_bits_derived_params_in_channels_per_bank_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_bias_spad_stride <= io_req_bits_derived_params_bias_spad_stride_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_input_spad_stride <= io_req_bits_derived_params_input_spad_stride_0; // @[LoopConv.scala:235:7, :258:16] req_derived_params_weight_spad_stride <= io_req_bits_derived_params_weight_spad_stride_0; // @[LoopConv.scala:235:7, :258:16] req_addr_start <= io_req_bits_addr_start_0; // @[LoopConv.scala:235:7, :258:16] req_dram_addr <= io_req_bits_dram_addr_0; // @[LoopConv.scala:235:7, :258:16] req_downsample <= io_req_bits_downsample_0; // @[LoopConv.scala:235:7, :258:16] req_max_pixels_per_row <= io_req_bits_max_pixels_per_row_0; // @[LoopConv.scala:235:7, :258:16] req_input_dilated <= io_req_bits_input_dilated_0; // @[LoopConv.scala:235:7, :258:16] req_trans_input_3120 <= io_req_bits_trans_input_3120_0; // @[LoopConv.scala:235:7, :258:16] req_loop_id <= io_req_bits_loop_id_0; // @[LoopConv.scala:235:7, :258:16] b <= 16'h0; // @[LoopConv.scala:271:14, :279:23] irow <= _irow_T_3[15:0]; // @[LoopConv.scala:272:17, :396:{10,17}] icol <= _icol_T_3[15:0]; // @[LoopConv.scala:273:17, :397:{10,17}] ich <= 16'h0; // @[LoopConv.scala:274:16, :279:23] end else if (~(\|req_dram_addr) \| ~_T_2 \| _command_p_io_in_bits_cmd_T) begin // @[Decoupled.scala:51:35] end else begin // @[LoopConv.scala:274:16, :364:30, :366:36, :367:29] b <= next_b[15:0]; // @[Mux.scala:126:16] irow <= next_irow[15:0]; // @[Mux.scala:126:16] icol <= next_icol[15:0]; // @[Mux.scala:126:16] ich <= next_ich[15:0]; // @[Mux.scala:126:16] end always @(posedge) Pipeline_11 command_p ( // @[LoopConv.scala:313:25] .clock (clock), .reset (reset), .io_in_ready (_command_p_io_in_ready), .io_in_valid (_command_p_io_in_valid_T_4), // @[LoopConv.scala:342:69] .io_in_bits_cmd_inst_funct (_command_p_io_in_bits_cmd_T_1_inst_funct), // @[LoopConv.scala:343:34] .io_in_bits_cmd_rs1 (_command_p_io_in_bits_cmd_T_1_rs1), // @[LoopConv.scala:343:34] .io_in_bits_cmd_rs2 (_command_p_io_in_bits_cmd_T_1_rs2), // @[LoopConv.scala:343:34] .io_in_bits_dram_addr (dram_addr), // @[LoopConv.scala:286:22] .io_in_bits_spad_addr (spad_addr), // @[LoopConv.scala:287:22] .io_in_bits_I (I), // @[Mux.scala:126:16] .io_in_bits_K (K), // @[LoopConv.scala:302:14] .io_out_ready (_command_p_io_out_ready_T_1), // @[LoopConv.scala:349:42] .io_out_valid (_command_p_io_out_valid), .io_out_bits_cmd_inst_funct (_command_p_io_out_bits_cmd_inst_funct), .io_out_bits_cmd_inst_rs2 (io_cmd_bits_inst_rs2_0), .io_out_bits_cmd_inst_rs1 (io_cmd_bits_inst_rs1_0), .io_out_bits_cmd_inst_xd (io_cmd_bits_inst_xd_0), .io_out_bits_cmd_inst_xs1 (io_cmd_bits_inst_xs1_0), .io_out_bits_cmd_inst_xs2 (io_cmd_bits_inst_xs2_0), .io_out_bits_cmd_inst_rd (io_cmd_bits_inst_rd_0), .io_out_bits_cmd_inst_opcode (io_cmd_bits_inst_opcode_0), .io_out_bits_cmd_rs1 (_command_p_io_out_bits_cmd_rs1), .io_out_bits_cmd_rs2 (_command_p_io_out_bits_cmd_rs2), .io_out_bits_cmd_status_debug (io_cmd_bits_status_debug_0), .io_out_bits_cmd_status_cease (io_cmd_bits_status_cease_0), .io_out_bits_cmd_status_wfi (io_cmd_bits_status_wfi_0), .io_out_bits_cmd_status_isa (io_cmd_bits_status_isa_0), .io_out_bits_cmd_status_dprv (io_cmd_bits_status_dprv_0), .io_out_bits_cmd_status_dv (io_cmd_bits_status_dv_0), .io_out_bits_cmd_status_prv (io_cmd_bits_status_prv_0), .io_out_bits_cmd_status_v (io_cmd_bits_status_v_0), .io_out_bits_cmd_status_sd (io_cmd_bits_status_sd_0), .io_out_bits_cmd_status_zero2 (io_cmd_bits_status_zero2_0), .io_out_bits_cmd_status_mpv (io_cmd_bits_status_mpv_0), .io_out_bits_cmd_status_gva (io_cmd_bits_status_gva_0), .io_out_bits_cmd_status_mbe (io_cmd_bits_status_mbe_0), .io_out_bits_cmd_status_sbe (io_cmd_bits_status_sbe_0), .io_out_bits_cmd_status_sxl (io_cmd_bits_status_sxl_0), .io_out_bits_cmd_status_uxl (io_cmd_bits_status_uxl_0), .io_out_bits_cmd_status_sd_rv32 (io_cmd_bits_status_sd_rv32_0), .io_out_bits_cmd_status_zero1 (io_cmd_bits_status_zero1_0), .io_out_bits_cmd_status_tsr (io_cmd_bits_status_tsr_0), .io_out_bits_cmd_status_tw (io_cmd_bits_status_tw_0), .io_out_bits_cmd_status_tvm (io_cmd_bits_status_tvm_0), .io_out_bits_cmd_status_mxr (io_cmd_bits_status_mxr_0), .io_out_bits_cmd_status_sum (io_cmd_bits_status_sum_0), .io_out_bits_cmd_status_mprv (io_cmd_bits_status_mprv_0), .io_out_bits_cmd_status_xs (io_cmd_bits_status_xs_0), .io_out_bits_cmd_status_fs (io_cmd_bits_status_fs_0), .io_out_bits_cmd_status_mpp (io_cmd_bits_status_mpp_0), .io_out_bits_cmd_status_vs (io_cmd_bits_status_vs_0), .io_out_bits_cmd_status_spp (io_cmd_bits_status_spp_0), .io_out_bits_cmd_status_mpie (io_cmd_bits_status_mpie_0), .io_out_bits_cmd_status_ube (io_cmd_bits_status_ube_0), .io_out_bits_cmd_status_spie (io_cmd_bits_status_spie_0), .io_out_bits_cmd_status_upie (io_cmd_bits_status_upie_0), .io_out_bits_cmd_status_mie (io_cmd_bits_status_mie_0), .io_out_bits_cmd_status_hie (io_cmd_bits_status_hie_0), .io_out_bits_cmd_status_sie (io_cmd_bits_status_sie_0), .io_out_bits_cmd_status_uie (io_cmd_bits_status_uie_0), .io_out_bits_dram_addr (_command_p_io_out_bits_dram_addr), .io_out_bits_spad_addr (_mvin_cmd_rs2_local_addr_result_result_T), .io_out_bits_I (_command_p_io_out_bits_I), .io_out_bits_K (_mvin_cmd_rs2_num_cols_T), .io_busy (_command_p_io_busy) ); // @[LoopConv.scala:313:25] assign io_cmd_bits_inst_funct_0 = _command_p_io_out_bits_cmd_inst_funct; // @[LoopConv.scala:235:7, :313:25] assign io_req_ready = io_req_ready_0; // @[LoopConv.scala:235:7] assign io_cmd_valid = io_cmd_valid_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_funct = io_cmd_bits_inst_funct_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_rs2 = io_cmd_bits_inst_rs2_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_rs1 = io_cmd_bits_inst_rs1_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_xd = io_cmd_bits_inst_xd_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_xs1 = io_cmd_bits_inst_xs1_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_xs2 = io_cmd_bits_inst_xs2_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_rd = io_cmd_bits_inst_rd_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_inst_opcode = io_cmd_bits_inst_opcode_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_rs1 = io_cmd_bits_rs1_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_rs2 = io_cmd_bits_rs2_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_debug = io_cmd_bits_status_debug_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_cease = io_cmd_bits_status_cease_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_wfi = io_cmd_bits_status_wfi_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_isa = io_cmd_bits_status_isa_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_dprv = io_cmd_bits_status_dprv_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_dv = io_cmd_bits_status_dv_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_prv = io_cmd_bits_status_prv_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_v = io_cmd_bits_status_v_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_sd = io_cmd_bits_status_sd_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_zero2 = io_cmd_bits_status_zero2_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_mpv = io_cmd_bits_status_mpv_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_gva = io_cmd_bits_status_gva_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_mbe = io_cmd_bits_status_mbe_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_sbe = io_cmd_bits_status_sbe_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_sxl = io_cmd_bits_status_sxl_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_uxl = io_cmd_bits_status_uxl_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_sd_rv32 = io_cmd_bits_status_sd_rv32_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_zero1 = io_cmd_bits_status_zero1_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_tsr = io_cmd_bits_status_tsr_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_tw = io_cmd_bits_status_tw_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_tvm = io_cmd_bits_status_tvm_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_mxr = io_cmd_bits_status_mxr_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_sum = io_cmd_bits_status_sum_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_mprv = io_cmd_bits_status_mprv_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_xs = io_cmd_bits_status_xs_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_fs = io_cmd_bits_status_fs_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_mpp = io_cmd_bits_status_mpp_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_vs = io_cmd_bits_status_vs_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_spp = io_cmd_bits_status_spp_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_mpie = io_cmd_bits_status_mpie_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_ube = io_cmd_bits_status_ube_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_spie = io_cmd_bits_status_spie_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_upie = io_cmd_bits_status_upie_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_mie = io_cmd_bits_status_mie_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_hie = io_cmd_bits_status_hie_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_sie = io_cmd_bits_status_sie_0; // @[LoopConv.scala:235:7] assign io_cmd_bits_status_uie = io_cmd_bits_status_uie_0; // @[LoopConv.scala:235:7] assign io_idle = io_idle_0; // @[LoopConv.scala:235:7] assign io_loop_id = io_loop_id_0; // @[LoopConv.scala:235:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_40( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [26:0] _GEN_0 = {23'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [8:0] b_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [8:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [1:0] _GEN_1 = {1'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [1:0] _GEN_6 = {1'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [7:0] inflight_2; // @[Monitor.scala:828:27] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_9 = {5'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35] wire [7:0] d_set = _GEN_8 ? 8'h1 << _GEN_9 : 8'h0; // @[OneHot.scala:58:35] wire _GEN_10 = io_in_e_ready & io_in_e_valid; // @[Decoupled.scala:51:35] wire [7:0] _GEN_11 = {5'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File SourceE.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ class SourceERequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val sink = UInt(params.outer.bundle.sinkBits.W) } class SourceE(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceERequest(params))) val e = Decoupled(new TLBundleE(params.outer.bundle)) }) // ready must be a register, because we derive valid from ready require (!params.micro.outerBuf.e.pipe && params.micro.outerBuf.e.isDefined) val e = Wire(chiselTypeOf(io.e)) io.e <> params.micro.outerBuf.e(e) io.req.ready := e.ready e.valid := io.req.valid e.bits.sink := io.req.bits.sink // we can't cover valid+!ready, because no backpressure on E is common }	module SourceE_4( // @[SourceE.scala:29:7] input clock, // @[SourceE.scala:29:7] input reset, // @[SourceE.scala:29:7] output io_req_ready, // @[SourceE.scala:31:14] input io_req_valid, // @[SourceE.scala:31:14] input [2:0] io_req_bits_sink, // @[SourceE.scala:31:14] output io_e_valid, // @[SourceE.scala:31:14] output [2:0] io_e_bits_sink // @[SourceE.scala:31:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceE.scala:29:7] wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceE.scala:29:7] wire io_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire e_ready; // @[SourceE.scala:39:15] wire e_valid = io_req_valid_0; // @[SourceE.scala:29:7, :39:15] wire [2:0] e_bits_sink = io_req_bits_sink_0; // @[SourceE.scala:29:7, :39:15] wire io_req_ready_0; // @[SourceE.scala:29:7] wire [2:0] io_e_bits_sink_0; // @[SourceE.scala:29:7] wire io_e_valid_0; // @[SourceE.scala:29:7] assign io_req_ready_0 = e_ready; // @[SourceE.scala:29:7, :39:15] Queue2_TLBundleE_a32d64s4k3z3c_4 io_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (e_ready), .io_enq_valid (e_valid), // @[SourceE.scala:39:15] .io_enq_bits_sink (e_bits_sink), // @[SourceE.scala:39:15] .io_deq_valid (io_e_valid_0), .io_deq_bits_sink (io_e_bits_sink_0) ); // @[Decoupled.scala:362:21] assign io_req_ready = io_req_ready_0; // @[SourceE.scala:29:7] assign io_e_valid = io_e_valid_0; // @[SourceE.scala:29:7] assign io_e_bits_sink = io_e_bits_sink_0; // @[SourceE.scala:29:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLBuffer_a32d64s4k1z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire auto_in_a_bits_user_amba_prot_bufferable_0 = auto_in_a_bits_user_amba_prot_bufferable; // @[Buffer.scala:40:9] wire auto_in_a_bits_user_amba_prot_modifiable_0 = auto_in_a_bits_user_amba_prot_modifiable; // @[Buffer.scala:40:9] wire auto_in_a_bits_user_amba_prot_readalloc_0 = auto_in_a_bits_user_amba_prot_readalloc; // @[Buffer.scala:40:9] wire auto_in_a_bits_user_amba_prot_writealloc_0 = auto_in_a_bits_user_amba_prot_writealloc; // @[Buffer.scala:40:9] wire auto_in_a_bits_user_amba_prot_privileged_0 = auto_in_a_bits_user_amba_prot_privileged; // @[Buffer.scala:40:9] wire auto_in_a_bits_user_amba_prot_secure_0 = auto_in_a_bits_user_amba_prot_secure; // @[Buffer.scala:40:9] wire auto_in_a_bits_user_amba_prot_fetch_0 = auto_in_a_bits_user_amba_prot_fetch; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [2:0] auto_in_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_user_amba_prot_bufferable = auto_in_a_bits_user_amba_prot_bufferable_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_user_amba_prot_modifiable = auto_in_a_bits_user_amba_prot_modifiable_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_user_amba_prot_readalloc = auto_in_a_bits_user_amba_prot_readalloc_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_user_amba_prot_writealloc = auto_in_a_bits_user_amba_prot_writealloc_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_user_amba_prot_privileged = auto_in_a_bits_user_amba_prot_privileged_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_user_amba_prot_secure = auto_in_a_bits_user_amba_prot_secure_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_user_amba_prot_fetch = auto_in_a_bits_user_amba_prot_fetch_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_user_amba_prot_bufferable; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_user_amba_prot_modifiable; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_user_amba_prot_readalloc; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_user_amba_prot_writealloc; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_user_amba_prot_privileged; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_user_amba_prot_secure; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_user_amba_prot_fetch; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_user_amba_prot_bufferable_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_user_amba_prot_modifiable_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_user_amba_prot_readalloc_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_user_amba_prot_writealloc_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_user_amba_prot_privileged_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_user_amba_prot_secure_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_user_amba_prot_fetch_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_bufferable_0 = nodeOut_a_bits_user_amba_prot_bufferable; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_modifiable_0 = nodeOut_a_bits_user_amba_prot_modifiable; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_readalloc_0 = nodeOut_a_bits_user_amba_prot_readalloc; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_writealloc_0 = nodeOut_a_bits_user_amba_prot_writealloc; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_privileged_0 = nodeOut_a_bits_user_amba_prot_privileged; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_secure_0 = nodeOut_a_bits_user_amba_prot_secure; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_fetch_0 = nodeOut_a_bits_user_amba_prot_fetch; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_18 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_user_amba_prot_bufferable (nodeIn_a_bits_user_amba_prot_bufferable), // @[MixedNode.scala:551:17] .io_in_a_bits_user_amba_prot_modifiable (nodeIn_a_bits_user_amba_prot_modifiable), // @[MixedNode.scala:551:17] .io_in_a_bits_user_amba_prot_readalloc (nodeIn_a_bits_user_amba_prot_readalloc), // @[MixedNode.scala:551:17] .io_in_a_bits_user_amba_prot_writealloc (nodeIn_a_bits_user_amba_prot_writealloc), // @[MixedNode.scala:551:17] .io_in_a_bits_user_amba_prot_privileged (nodeIn_a_bits_user_amba_prot_privileged), // @[MixedNode.scala:551:17] .io_in_a_bits_user_amba_prot_secure (nodeIn_a_bits_user_amba_prot_secure), // @[MixedNode.scala:551:17] .io_in_a_bits_user_amba_prot_fetch (nodeIn_a_bits_user_amba_prot_fetch), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s4k1z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_user_amba_prot_bufferable (nodeIn_a_bits_user_amba_prot_bufferable), // @[MixedNode.scala:551:17] .io_enq_bits_user_amba_prot_modifiable (nodeIn_a_bits_user_amba_prot_modifiable), // @[MixedNode.scala:551:17] .io_enq_bits_user_amba_prot_readalloc (nodeIn_a_bits_user_amba_prot_readalloc), // @[MixedNode.scala:551:17] .io_enq_bits_user_amba_prot_writealloc (nodeIn_a_bits_user_amba_prot_writealloc), // @[MixedNode.scala:551:17] .io_enq_bits_user_amba_prot_privileged (nodeIn_a_bits_user_amba_prot_privileged), // @[MixedNode.scala:551:17] .io_enq_bits_user_amba_prot_secure (nodeIn_a_bits_user_amba_prot_secure), // @[MixedNode.scala:551:17] .io_enq_bits_user_amba_prot_fetch (nodeIn_a_bits_user_amba_prot_fetch), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_user_amba_prot_bufferable (nodeOut_a_bits_user_amba_prot_bufferable), .io_deq_bits_user_amba_prot_modifiable (nodeOut_a_bits_user_amba_prot_modifiable), .io_deq_bits_user_amba_prot_readalloc (nodeOut_a_bits_user_amba_prot_readalloc), .io_deq_bits_user_amba_prot_writealloc (nodeOut_a_bits_user_amba_prot_writealloc), .io_deq_bits_user_amba_prot_privileged (nodeOut_a_bits_user_amba_prot_privileged), .io_deq_bits_user_amba_prot_secure (nodeOut_a_bits_user_amba_prot_secure), .io_deq_bits_user_amba_prot_fetch (nodeOut_a_bits_user_amba_prot_fetch), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s4k1z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_bufferable = auto_out_a_bits_user_amba_prot_bufferable_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_modifiable = auto_out_a_bits_user_amba_prot_modifiable_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_readalloc = auto_out_a_bits_user_amba_prot_readalloc_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_writealloc = auto_out_a_bits_user_amba_prot_writealloc_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_privileged = auto_out_a_bits_user_amba_prot_privileged_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_secure = auto_out_a_bits_user_amba_prot_secure_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_user_amba_prot_fetch = auto_out_a_bits_user_amba_prot_fetch_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_1( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [4:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [26:0] _GEN_0 = {23'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [4:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [8:0] b_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [8:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [3:0] _GEN_1 = {2'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [3:0] _GEN_4 = {2'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [3:0] _GEN_6 = {2'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [31:0] inflight_2; // @[Monitor.scala:828:27] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [31:0] _GEN_9 = {27'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35] wire [31:0] d_set = _GEN_8 ? 32'h1 << _GEN_9 : 32'h0; // @[OneHot.scala:58:35] wire _GEN_10 = io_in_e_ready & io_in_e_valid; // @[Decoupled.scala:51:35] wire [31:0] _GEN_11 = {27'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_379( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid \|\| io.clear \|\| io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 \|\| rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_\|\|_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_\|\|_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready \|\| agen_ready \|\| dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }	module IssueSlot_40( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [1:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7] wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_327( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_236( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_253 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Protocol.scala: package rerocc.bus import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import rerocc.client.{ReRoCCClientParams} import rerocc.manager.{ReRoCCManagerParams} object ReRoCCProtocol { val width = 3 val mAcquire = 0.U(width.W) // beat0: data = inst // beat1: data = mstatus[63:0] // beat2: data = mstatus[127:64] val mInst = 1.U(width.W) // beat0: data = mstatus[63:0] // beat1: data = mstatus[127:0] val mUStatus = 2.U(width.W) // beat0: data = ptbr val mUPtbr = 3.U(width.W) val mRelease = 4.U(width.W) val mUnbusy = 5.U(width.W) // data // data = acquired val sAcqResp = 0.U(width.W) // data = 0 val sInstAck = 1.U(width.W) // beat0: data = data // beat1: data = rd val sWrite = 2.U(width.W) val sRelResp = 3.U(width.W) val sUnbusyAck = 4.U(width.W) val MAX_BEATS = 3 } class ReRoCCMsgBundle(val params: ReRoCCBundleParams) extends Bundle { val opcode = UInt(ReRoCCProtocol.width.W) val client_id = UInt(params.clientIdBits.W) val manager_id = UInt(params.managerIdBits.W) val data = UInt(64.W) } object ReRoCCMsgFirstLast { def apply(m: DecoupledIO[ReRoCCMsgBundle], isReq: Boolean): (Bool, Bool, UInt) = { val beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W)) val max_beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W)) val first = beat === 0.U val last = Wire(Bool()) val inst = m.bits.data.asTypeOf(new RoCCInstruction) when (m.fire && first) { max_beat := 0.U if (isReq) { when (m.bits.opcode === ReRoCCProtocol.mInst) { max_beat := inst.xs1 +& inst.xs2 } .elsewhen (m.bits.opcode === ReRoCCProtocol.mUStatus) { max_beat := 1.U } } else { when (m.bits.opcode === ReRoCCProtocol.sWrite) { max_beat := 1.U } } } last := true.B if (isReq) { when (m.bits.opcode === ReRoCCProtocol.mUStatus) { last := beat === max_beat && !first } .elsewhen (m.bits.opcode === ReRoCCProtocol.mInst) { last := Mux(first, !inst.xs1 && !inst.xs2, beat === max_beat) } } else { when (m.bits.opcode === ReRoCCProtocol.sWrite) { last := beat === max_beat && !first } } when (m.fire) { beat := beat + 1.U } when (m.fire && last) { max_beat := 0.U beat := 0.U } (first, last, beat) } } class ReRoCCBundle(val params: ReRoCCBundleParams) extends Bundle { val req = Decoupled(new ReRoCCMsgBundle(params)) val resp = Flipped(Decoupled(new ReRoCCMsgBundle(params))) } case class EmptyParams() object ReRoCCImp extends SimpleNodeImp[ReRoCCClientPortParams, ReRoCCManagerPortParams, ReRoCCEdgeParams, ReRoCCBundle] { def edge(pd: ReRoCCClientPortParams, pu: ReRoCCManagerPortParams, p: Parameters, sourceInfo: SourceInfo) = { ReRoCCEdgeParams(pu, pd) } def bundle(e: ReRoCCEdgeParams) = new ReRoCCBundle(e.bundle) def render(ei: ReRoCCEdgeParams) = RenderedEdge(colour = "#000000" /* black /) } case class ReRoCCClientNode(clientParams: ReRoCCClientParams)(implicit valName: ValName) extends SourceNode(ReRoCCImp)(Seq(ReRoCCClientPortParams(Seq(clientParams)))) case class ReRoCCManagerNode(managerParams: ReRoCCManagerParams)(implicit valName: ValName) extends SinkNode(ReRoCCImp)(Seq(ReRoCCManagerPortParams(Seq(managerParams)))) class ReRoCCBuffer(b: BufferParams = BufferParams.default)(implicit p: Parameters) extends LazyModule { val node = new AdapterNode(ReRoCCImp)({s => s}, {s => s}) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, _), (out, _)) => out.req <> b(in.req) in.resp <> b(out.resp) } } } object ReRoCCBuffer { def apply(b: BufferParams = BufferParams.default)(implicit p: Parameters) = { val rerocc_buffer = LazyModule(new ReRoCCBuffer(b)(p)) rerocc_buffer.node } } case class ReRoCCIdentityNode()(implicit valName: ValName) extends IdentityNode(ReRoCCImp)() File Arbiter.scala: package rerocc.bus import chisel3._ import chisel3.util._ import freechips.rocketchip.util.{HellaLockingArbiter} class ReRoCCMsgArbiter(bundle: ReRoCCBundleParams, arbN: Int, isReq: Boolean) extends HellaLockingArbiter(new ReRoCCMsgBundle(bundle), arbN, false) { when (io.out.fire) { when (!locked) { lockIdx := choice locked := true.B } when (ReRoCCMsgFirstLast(io.out, isReq)._2) { locked := false.B } } } File Arbiters.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters /* A generalized locking RR arbiter that addresses the limitations of the * version in the Chisel standard library / abstract class HellaLockingArbiter[T <: Data](typ: T, arbN: Int, rr: Boolean = false) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(arbN, Decoupled(typ.cloneType))) val out = Decoupled(typ.cloneType) }) def rotateLeft[T <: Data](norm: Vec[T], rot: UInt): Vec[T] = { val n = norm.size VecInit.tabulate(n) { i => Mux(rot < (n - i).U, norm(i.U + rot), norm(rot - (n - i).U)) } } val lockIdx = RegInit(0.U(log2Up(arbN).W)) val locked = RegInit(false.B) val choice = if (rr) { PriorityMux( rotateLeft(VecInit(io.in.map(_.valid)), lockIdx + 1.U), rotateLeft(VecInit((0 until arbN).map(_.U)), lockIdx + 1.U)) } else { PriorityEncoder(io.in.map(_.valid)) } val chosen = Mux(locked, lockIdx, choice) for (i <- 0 until arbN) { io.in(i).ready := io.out.ready && chosen === i.U } io.out.valid := io.in(chosen).valid io.out.bits := io.in(chosen).bits } /* This locking arbiter determines when it is safe to unlock * by peeking at the data / class HellaPeekingArbiter[T <: Data]( typ: T, arbN: Int, canUnlock: T => Bool, needsLock: Option[T => Bool] = None, rr: Boolean = false) extends HellaLockingArbiter(typ, arbN, rr) { def realNeedsLock(data: T): Bool = needsLock.map(_(data)).getOrElse(true.B) when (io.out.fire) { when (!locked && realNeedsLock(io.out.bits)) { lockIdx := choice locked := true.B } // the unlock statement takes precedent when (canUnlock(io.out.bits)) { locked := false.B } } } /* This arbiter determines when it is safe to unlock by counting transactions / class HellaCountingArbiter[T <: Data]( typ: T, arbN: Int, count: Int, val needsLock: Option[T => Bool] = None, rr: Boolean = false) extends HellaLockingArbiter(typ, arbN, rr) { def realNeedsLock(data: T): Bool = needsLock.map(_(data)).getOrElse(true.B) // if count is 1, you should use a non-locking arbiter require(count > 1, "CountingArbiter cannot have count <= 1") val lock_ctr = Counter(count) when (io.out.fire) { when (!locked && realNeedsLock(io.out.bits)) { lockIdx := choice locked := true.B lock_ctr.inc() } when (locked) { when (lock_ctr.inc()) { locked := false.B } } } } /* This arbiter preserves the order of responses */ class InOrderArbiter[T <: Data, U <: Data](reqTyp: T, respTyp: U, n: Int) (implicit p: Parameters) extends Module { val io = IO(new Bundle { val in_req = Flipped(Vec(n, Decoupled(reqTyp))) val in_resp = Vec(n, Decoupled(respTyp)) val out_req = Decoupled(reqTyp) val out_resp = Flipped(Decoupled(respTyp)) }) if (n > 1) { val route_q = Module(new Queue(UInt(log2Up(n).W), 2)) val req_arb = Module(new RRArbiter(reqTyp, n)) req_arb.io.in <> io.in_req val req_helper = DecoupledHelper( req_arb.io.out.valid, route_q.io.enq.ready, io.out_req.ready) io.out_req.bits := req_arb.io.out.bits io.out_req.valid := req_helper.fire(io.out_req.ready) route_q.io.enq.bits := req_arb.io.chosen route_q.io.enq.valid := req_helper.fire(route_q.io.enq.ready) req_arb.io.out.ready := req_helper.fire(req_arb.io.out.valid) val resp_sel = route_q.io.deq.bits val resp_ready = io.in_resp(resp_sel).ready val resp_helper = DecoupledHelper( resp_ready, route_q.io.deq.valid, io.out_resp.valid) val resp_valid = resp_helper.fire(resp_ready) for (i <- 0 until n) { io.in_resp(i).bits := io.out_resp.bits io.in_resp(i).valid := resp_valid && resp_sel === i.U } route_q.io.deq.ready := resp_helper.fire(route_q.io.deq.valid) io.out_resp.ready := resp_helper.fire(io.out_resp.valid) } else { io.out_req <> io.in_req.head io.in_resp.head <> io.out_resp } }	module ReRoCCMsgArbiter_7( // @[Arbiter.scala:7:7] input clock, // @[Arbiter.scala:7:7] input reset, // @[Arbiter.scala:7:7] output io_in_0_ready, // @[Arbiters.scala:14:14] input io_in_0_valid, // @[Arbiters.scala:14:14] input [2:0] io_in_0_bits_opcode, // @[Arbiters.scala:14:14] input [3:0] io_in_0_bits_client_id, // @[Arbiters.scala:14:14] input [2:0] io_in_0_bits_manager_id, // @[Arbiters.scala:14:14] input [63:0] io_in_0_bits_data, // @[Arbiters.scala:14:14] input io_out_ready, // @[Arbiters.scala:14:14] output io_out_valid, // @[Arbiters.scala:14:14] output [2:0] io_out_bits_opcode, // @[Arbiters.scala:14:14] output [3:0] io_out_bits_client_id, // @[Arbiters.scala:14:14] output [2:0] io_out_bits_manager_id, // @[Arbiters.scala:14:14] output [63:0] io_out_bits_data // @[Arbiters.scala:14:14] ); wire io_in_0_valid_0 = io_in_0_valid; // @[Arbiter.scala:7:7] wire [2:0] io_in_0_bits_opcode_0 = io_in_0_bits_opcode; // @[Arbiter.scala:7:7] wire [3:0] io_in_0_bits_client_id_0 = io_in_0_bits_client_id; // @[Arbiter.scala:7:7] wire [2:0] io_in_0_bits_manager_id_0 = io_in_0_bits_manager_id; // @[Arbiter.scala:7:7] wire [63:0] io_in_0_bits_data_0 = io_in_0_bits_data; // @[Arbiter.scala:7:7] wire io_out_ready_0 = io_out_ready; // @[Arbiter.scala:7:7] wire _io_in_0_ready_T = 1'h1; // @[Arbiters.scala:40:46] wire chosen = 1'h0; // @[Arbiters.scala:37:19] wire _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] wire _io_out_valid_WIRE = 1'h0; wire _io_out_bits_WIRE = 1'h0; wire io_out_valid_0 = io_in_0_valid_0; // @[Arbiter.scala:7:7] wire [2:0] io_out_bits_opcode_0 = io_in_0_bits_opcode_0; // @[Arbiter.scala:7:7] wire [3:0] io_out_bits_client_id_0 = io_in_0_bits_client_id_0; // @[Arbiter.scala:7:7] wire [2:0] io_out_bits_manager_id_0 = io_in_0_bits_manager_id_0; // @[Arbiter.scala:7:7] wire [63:0] io_out_bits_data_0 = io_in_0_bits_data_0; // @[Arbiter.scala:7:7] assign _io_in_0_ready_T_1 = io_out_ready_0; // @[Arbiters.scala:40:36] wire io_in_0_ready_0; // @[Arbiter.scala:7:7] reg locked; // @[Arbiters.scala:27:23] assign io_in_0_ready_0 = _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] reg [1:0] beat; // @[Protocol.scala:54:23] reg [1:0] max_beat; // @[Protocol.scala:55:27] wire first = beat == 2'h0; // @[Protocol.scala:54:23, :56:22] wire last; // @[Protocol.scala:57:20] wire [6:0] _inst_T_7; // @[Protocol.scala:58:36] wire [4:0] _inst_T_6; // @[Protocol.scala:58:36] wire [4:0] _inst_T_5; // @[Protocol.scala:58:36] wire _inst_T_4; // @[Protocol.scala:58:36] wire _inst_T_3; // @[Protocol.scala:58:36] wire _inst_T_2; // @[Protocol.scala:58:36] wire [4:0] _inst_T_1; // @[Protocol.scala:58:36] wire [6:0] _inst_T; // @[Protocol.scala:58:36] wire [6:0] inst_funct; // @[Protocol.scala:58:36] wire [4:0] inst_rs2; // @[Protocol.scala:58:36] wire [4:0] inst_rs1; // @[Protocol.scala:58:36] wire inst_xd; // @[Protocol.scala:58:36] wire inst_xs1; // @[Protocol.scala:58:36] wire inst_xs2; // @[Protocol.scala:58:36] wire [4:0] inst_rd; // @[Protocol.scala:58:36] wire [6:0] inst_opcode; // @[Protocol.scala:58:36] wire [31:0] _inst_WIRE = io_out_bits_data_0[31:0]; // @[Protocol.scala:58:36] assign _inst_T = _inst_WIRE[6:0]; // @[Protocol.scala:58:36] assign inst_opcode = _inst_T; // @[Protocol.scala:58:36] assign _inst_T_1 = _inst_WIRE[11:7]; // @[Protocol.scala:58:36] assign inst_rd = _inst_T_1; // @[Protocol.scala:58:36] assign _inst_T_2 = _inst_WIRE[12]; // @[Protocol.scala:58:36] assign inst_xs2 = _inst_T_2; // @[Protocol.scala:58:36] assign _inst_T_3 = _inst_WIRE[13]; // @[Protocol.scala:58:36] assign inst_xs1 = _inst_T_3; // @[Protocol.scala:58:36] assign _inst_T_4 = _inst_WIRE[14]; // @[Protocol.scala:58:36] assign inst_xd = _inst_T_4; // @[Protocol.scala:58:36] assign _inst_T_5 = _inst_WIRE[19:15]; // @[Protocol.scala:58:36] assign inst_rs1 = _inst_T_5; // @[Protocol.scala:58:36] assign _inst_T_6 = _inst_WIRE[24:20]; // @[Protocol.scala:58:36] assign inst_rs2 = _inst_T_6; // @[Protocol.scala:58:36] assign _inst_T_7 = _inst_WIRE[31:25]; // @[Protocol.scala:58:36] assign inst_funct = _inst_T_7; // @[Protocol.scala:58:36] wire [1:0] _max_beat_T = {1'h0, inst_xs1} + {1'h0, inst_xs2}; // @[Protocol.scala:58:36, :63:32] wire _GEN = beat == max_beat; // @[Protocol.scala:54:23, :55:27, :77:22] wire _last_T; // @[Protocol.scala:77:22] assign _last_T = _GEN; // @[Protocol.scala:77:22] wire _last_T_6; // @[Protocol.scala:79:57] assign _last_T_6 = _GEN; // @[Protocol.scala:77:22, :79:57] wire _last_T_1 = ~first; // @[Protocol.scala:56:22, :77:38] wire _last_T_2 = _last_T & _last_T_1; // @[Protocol.scala:77:{22,35,38}] wire _last_T_3 = ~inst_xs1; // @[Protocol.scala:58:36, :79:28] wire _last_T_4 = ~inst_xs2; // @[Protocol.scala:58:36, :79:41] wire _last_T_5 = _last_T_3 & _last_T_4; // @[Protocol.scala:79:{28,38,41}] wire _last_T_7 = first ? _last_T_5 : _last_T_6; // @[Protocol.scala:56:22, :79:{20,38,57}] assign last = io_out_bits_opcode_0 == 3'h2 ? _last_T_2 : io_out_bits_opcode_0 != 3'h1 \| _last_T_7; // @[Protocol.scala:57:20, :74:10, :76:{27,56}, :77:{14,35}, :78:{34,60}, :79:{14,20}, :87:34] wire [2:0] _beat_T = {1'h0, beat} + 3'h1; // @[Protocol.scala:54:23, :87:34] wire [1:0] _beat_T_1 = _beat_T[1:0]; // @[Protocol.scala:87:34] wire _T_9 = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Arbiter.scala:7:7] if (reset) begin // @[Arbiter.scala:7:7] locked <= 1'h0; // @[Arbiters.scala:27:23] beat <= 2'h0; // @[Protocol.scala:54:23] max_beat <= 2'h0; // @[Protocol.scala:55:27] end else begin // @[Arbiter.scala:7:7] if (_T_9) // @[Decoupled.scala:51:35] locked <= ~last; // @[Arbiters.scala:27:23] if (_T_9 & last) begin // @[Decoupled.scala:51:35] beat <= 2'h0; // @[Protocol.scala:54:23] max_beat <= 2'h0; // @[Protocol.scala:55:27] end else begin // @[Protocol.scala:88:18] if (_T_9) // @[Decoupled.scala:51:35] beat <= _beat_T_1; // @[Protocol.scala:54:23, :87:34] if (_T_9 & first) // @[Decoupled.scala:51:35] max_beat <= io_out_bits_opcode_0 == 3'h1 ? _max_beat_T : {1'h0, io_out_bits_opcode_0 == 3'h2}; // @[Protocol.scala:55:27, :60:16, :62:{29,55}, :63:{20,32}, :64:{36,65}, :65:20, :87:34] end end always @(posedge) assign io_in_0_ready = io_in_0_ready_0; // @[Arbiter.scala:7:7] assign io_out_valid = io_out_valid_0; // @[Arbiter.scala:7:7] assign io_out_bits_opcode = io_out_bits_opcode_0; // @[Arbiter.scala:7:7] assign io_out_bits_client_id = io_out_bits_client_id_0; // @[Arbiter.scala:7:7] assign io_out_bits_manager_id = io_out_bits_manager_id_0; // @[Arbiter.scala:7:7] assign io_out_bits_data = io_out_bits_data_0; // @[Arbiter.scala:7:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module mem_24x75( // @[InputUnit.scala:85:18] input [4:0] R0_addr, input R0_en, input R0_clk, output [74:0] R0_data, input [4:0] R1_addr, input R1_en, input R1_clk, output [74:0] R1_data, input [4:0] R2_addr, input R2_en, input R2_clk, output [74:0] R2_data, input [4:0] R3_addr, input R3_en, input R3_clk, output [74:0] R3_data, input [4:0] R4_addr, input R4_en, input R4_clk, output [74:0] R4_data, input [4:0] R5_addr, input R5_en, input R5_clk, output [74:0] R5_data, input [4:0] R6_addr, input R6_en, input R6_clk, output [74:0] R6_data, input [4:0] R7_addr, input R7_en, input R7_clk, output [74:0] R7_data, input [4:0] R8_addr, input R8_en, input R8_clk, output [74:0] R8_data, input [4:0] R9_addr, input R9_en, input R9_clk, output [74:0] R9_data, input [4:0] R10_addr, input R10_en, input R10_clk, output [74:0] R10_data, input [4:0] R11_addr, input R11_en, input R11_clk, output [74:0] R11_data, input [4:0] R12_addr, input R12_en, input R12_clk, output [74:0] R12_data, input [4:0] R13_addr, input R13_en, input R13_clk, output [74:0] R13_data, input [4:0] R14_addr, input R14_en, input R14_clk, output [74:0] R14_data, input [4:0] R15_addr, input R15_en, input R15_clk, output [74:0] R15_data, input [4:0] R16_addr, input R16_en, input R16_clk, output [74:0] R16_data, input [4:0] R17_addr, input R17_en, input R17_clk, output [74:0] R17_data, input [4:0] R18_addr, input R18_en, input R18_clk, output [74:0] R18_data, input [4:0] R19_addr, input R19_en, input R19_clk, output [74:0] R19_data, input [4:0] R20_addr, input R20_en, input R20_clk, output [74:0] R20_data, input [4:0] R21_addr, input R21_en, input R21_clk, output [74:0] R21_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [74:0] W0_data ); reg [74:0] Memory[0:23]; // @[InputUnit.scala:85:18] always @(posedge W0_clk) begin // @[InputUnit.scala:85:18] if (W0_en & 1'h1) // @[InputUnit.scala:85:18] Memory[W0_addr] <= W0_data; // @[InputUnit.scala:85:18] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_111( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)